1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Define target-specific opcode support 4 * Copyright (c) 2021 WANG Xuerui <git@xen0n.name> 5 */ 6 7 #ifndef TCG_TARGET_HAS_H 8 #define TCG_TARGET_HAS_H 9 10 #include "host/cpuinfo.h" 11 12 /* optional instructions */ 13 #define TCG_TARGET_HAS_negsetcond_i32 0 14 #define TCG_TARGET_HAS_div_i32 1 15 #define TCG_TARGET_HAS_rem_i32 1 16 #define TCG_TARGET_HAS_div2_i32 0 17 #define TCG_TARGET_HAS_rot_i32 1 18 #define TCG_TARGET_HAS_extract2_i32 0 19 #define TCG_TARGET_HAS_add2_i32 0 20 #define TCG_TARGET_HAS_sub2_i32 0 21 #define TCG_TARGET_HAS_mulu2_i32 0 22 #define TCG_TARGET_HAS_muls2_i32 0 23 #define TCG_TARGET_HAS_muluh_i32 1 24 #define TCG_TARGET_HAS_mulsh_i32 1 25 #define TCG_TARGET_HAS_bswap16_i32 1 26 #define TCG_TARGET_HAS_bswap32_i32 1 27 #define TCG_TARGET_HAS_not_i32 1 28 #define TCG_TARGET_HAS_nand_i32 0 29 #define TCG_TARGET_HAS_nor_i32 1 30 #define TCG_TARGET_HAS_clz_i32 1 31 #define TCG_TARGET_HAS_ctz_i32 1 32 #define TCG_TARGET_HAS_ctpop_i32 0 33 #define TCG_TARGET_HAS_qemu_st8_i32 0 34 35 /* 64-bit operations */ 36 #define TCG_TARGET_HAS_negsetcond_i64 0 37 #define TCG_TARGET_HAS_div_i64 1 38 #define TCG_TARGET_HAS_rem_i64 1 39 #define TCG_TARGET_HAS_div2_i64 0 40 #define TCG_TARGET_HAS_rot_i64 1 41 #define TCG_TARGET_HAS_extract2_i64 0 42 #define TCG_TARGET_HAS_extr_i64_i32 1 43 #define TCG_TARGET_HAS_bswap16_i64 1 44 #define TCG_TARGET_HAS_bswap32_i64 1 45 #define TCG_TARGET_HAS_bswap64_i64 1 46 #define TCG_TARGET_HAS_not_i64 1 47 #define TCG_TARGET_HAS_nand_i64 0 48 #define TCG_TARGET_HAS_nor_i64 1 49 #define TCG_TARGET_HAS_clz_i64 1 50 #define TCG_TARGET_HAS_ctz_i64 1 51 #define TCG_TARGET_HAS_ctpop_i64 0 52 #define TCG_TARGET_HAS_add2_i64 0 53 #define TCG_TARGET_HAS_sub2_i64 0 54 #define TCG_TARGET_HAS_mulu2_i64 0 55 #define TCG_TARGET_HAS_muls2_i64 0 56 #define TCG_TARGET_HAS_muluh_i64 1 57 #define TCG_TARGET_HAS_mulsh_i64 1 58 59 #define TCG_TARGET_HAS_qemu_ldst_i128 (cpuinfo & CPUINFO_LSX) 60 61 #define TCG_TARGET_HAS_tst 0 62 63 #define TCG_TARGET_HAS_v64 (cpuinfo & CPUINFO_LSX) 64 #define TCG_TARGET_HAS_v128 (cpuinfo & CPUINFO_LSX) 65 #define TCG_TARGET_HAS_v256 (cpuinfo & CPUINFO_LASX) 66 67 #define TCG_TARGET_HAS_not_vec 1 68 #define TCG_TARGET_HAS_neg_vec 1 69 #define TCG_TARGET_HAS_abs_vec 0 70 #define TCG_TARGET_HAS_andc_vec 1 71 #define TCG_TARGET_HAS_orc_vec 1 72 #define TCG_TARGET_HAS_nand_vec 0 73 #define TCG_TARGET_HAS_nor_vec 1 74 #define TCG_TARGET_HAS_eqv_vec 0 75 #define TCG_TARGET_HAS_mul_vec 1 76 #define TCG_TARGET_HAS_shi_vec 1 77 #define TCG_TARGET_HAS_shs_vec 0 78 #define TCG_TARGET_HAS_shv_vec 1 79 #define TCG_TARGET_HAS_roti_vec 1 80 #define TCG_TARGET_HAS_rots_vec 0 81 #define TCG_TARGET_HAS_rotv_vec 1 82 #define TCG_TARGET_HAS_sat_vec 1 83 #define TCG_TARGET_HAS_minmax_vec 1 84 #define TCG_TARGET_HAS_bitsel_vec 1 85 #define TCG_TARGET_HAS_cmpsel_vec 0 86 #define TCG_TARGET_HAS_tst_vec 0 87 88 #define TCG_TARGET_extract_valid(type, ofs, len) 1 89 #define TCG_TARGET_deposit_valid(type, ofs, len) 1 90 91 static inline bool 92 tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len) 93 { 94 if (type == TCG_TYPE_I64 && ofs + len == 32) { 95 return true; 96 } 97 return ofs == 0 && (len == 8 || len == 16); 98 } 99 #define TCG_TARGET_sextract_valid tcg_target_sextract_valid 100 101 #endif 102