1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Define target-specific opcode support 4 * Copyright (c) 2021 WANG Xuerui <git@xen0n.name> 5 */ 6 7 #ifndef TCG_TARGET_HAS_H 8 #define TCG_TARGET_HAS_H 9 10 #include "host/cpuinfo.h" 11 12 /* optional instructions */ 13 #define TCG_TARGET_HAS_extract2_i32 0 14 #define TCG_TARGET_HAS_add2_i32 0 15 #define TCG_TARGET_HAS_sub2_i32 0 16 #define TCG_TARGET_HAS_qemu_st8_i32 0 17 18 /* 64-bit operations */ 19 #define TCG_TARGET_HAS_extract2_i64 0 20 #define TCG_TARGET_HAS_extr_i64_i32 1 21 #define TCG_TARGET_HAS_add2_i64 0 22 #define TCG_TARGET_HAS_sub2_i64 0 23 24 #define TCG_TARGET_HAS_qemu_ldst_i128 (cpuinfo & CPUINFO_LSX) 25 26 #define TCG_TARGET_HAS_tst 0 27 28 #define TCG_TARGET_HAS_v64 (cpuinfo & CPUINFO_LSX) 29 #define TCG_TARGET_HAS_v128 (cpuinfo & CPUINFO_LSX) 30 #define TCG_TARGET_HAS_v256 (cpuinfo & CPUINFO_LASX) 31 32 #define TCG_TARGET_HAS_not_vec 1 33 #define TCG_TARGET_HAS_neg_vec 1 34 #define TCG_TARGET_HAS_abs_vec 0 35 #define TCG_TARGET_HAS_andc_vec 1 36 #define TCG_TARGET_HAS_orc_vec 1 37 #define TCG_TARGET_HAS_nand_vec 0 38 #define TCG_TARGET_HAS_nor_vec 1 39 #define TCG_TARGET_HAS_eqv_vec 0 40 #define TCG_TARGET_HAS_mul_vec 1 41 #define TCG_TARGET_HAS_shi_vec 1 42 #define TCG_TARGET_HAS_shs_vec 0 43 #define TCG_TARGET_HAS_shv_vec 1 44 #define TCG_TARGET_HAS_roti_vec 1 45 #define TCG_TARGET_HAS_rots_vec 0 46 #define TCG_TARGET_HAS_rotv_vec 1 47 #define TCG_TARGET_HAS_sat_vec 1 48 #define TCG_TARGET_HAS_minmax_vec 1 49 #define TCG_TARGET_HAS_bitsel_vec 1 50 #define TCG_TARGET_HAS_cmpsel_vec 0 51 #define TCG_TARGET_HAS_tst_vec 0 52 53 #define TCG_TARGET_extract_valid(type, ofs, len) 1 54 #define TCG_TARGET_deposit_valid(type, ofs, len) 1 55 56 static inline bool 57 tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len) 58 { 59 if (type == TCG_TYPE_I64 && ofs + len == 32) { 60 return true; 61 } 62 return ofs == 0 && (len == 8 || len == 16); 63 } 64 #define TCG_TARGET_sextract_valid tcg_target_sextract_valid 65 66 #endif 67