xref: /openbmc/qemu/tcg/loongarch64/tcg-target-has.h (revision 40efe733e10cc00e4fb4f9f5790a28e744e63c62)
10a16d036SRichard Henderson /* SPDX-License-Identifier: MIT */
20a16d036SRichard Henderson /*
30a16d036SRichard Henderson  * Define target-specific opcode support
40a16d036SRichard Henderson  * Copyright (c) 2021 WANG Xuerui <git@xen0n.name>
50a16d036SRichard Henderson  */
60a16d036SRichard Henderson 
70a16d036SRichard Henderson #ifndef TCG_TARGET_HAS_H
80a16d036SRichard Henderson #define TCG_TARGET_HAS_H
90a16d036SRichard Henderson 
100a16d036SRichard Henderson #include "host/cpuinfo.h"
110a16d036SRichard Henderson 
120a16d036SRichard Henderson /* optional instructions */
130a16d036SRichard Henderson #define TCG_TARGET_HAS_negsetcond_i32   0
140a16d036SRichard Henderson #define TCG_TARGET_HAS_div_i32          1
150a16d036SRichard Henderson #define TCG_TARGET_HAS_rem_i32          1
160a16d036SRichard Henderson #define TCG_TARGET_HAS_div2_i32         0
170a16d036SRichard Henderson #define TCG_TARGET_HAS_rot_i32          1
180a16d036SRichard Henderson #define TCG_TARGET_HAS_extract2_i32     0
190a16d036SRichard Henderson #define TCG_TARGET_HAS_add2_i32         0
200a16d036SRichard Henderson #define TCG_TARGET_HAS_sub2_i32         0
210a16d036SRichard Henderson #define TCG_TARGET_HAS_mulu2_i32        0
220a16d036SRichard Henderson #define TCG_TARGET_HAS_muls2_i32        0
230a16d036SRichard Henderson #define TCG_TARGET_HAS_muluh_i32        1
240a16d036SRichard Henderson #define TCG_TARGET_HAS_mulsh_i32        1
250a16d036SRichard Henderson #define TCG_TARGET_HAS_ext8s_i32        1
260a16d036SRichard Henderson #define TCG_TARGET_HAS_ext16s_i32       1
270a16d036SRichard Henderson #define TCG_TARGET_HAS_ext8u_i32        1
280a16d036SRichard Henderson #define TCG_TARGET_HAS_ext16u_i32       1
290a16d036SRichard Henderson #define TCG_TARGET_HAS_bswap16_i32      1
300a16d036SRichard Henderson #define TCG_TARGET_HAS_bswap32_i32      1
310a16d036SRichard Henderson #define TCG_TARGET_HAS_not_i32          1
320a16d036SRichard Henderson #define TCG_TARGET_HAS_andc_i32         1
330a16d036SRichard Henderson #define TCG_TARGET_HAS_orc_i32          1
340a16d036SRichard Henderson #define TCG_TARGET_HAS_eqv_i32          0
350a16d036SRichard Henderson #define TCG_TARGET_HAS_nand_i32         0
360a16d036SRichard Henderson #define TCG_TARGET_HAS_nor_i32          1
370a16d036SRichard Henderson #define TCG_TARGET_HAS_clz_i32          1
380a16d036SRichard Henderson #define TCG_TARGET_HAS_ctz_i32          1
390a16d036SRichard Henderson #define TCG_TARGET_HAS_ctpop_i32        0
400a16d036SRichard Henderson #define TCG_TARGET_HAS_qemu_st8_i32     0
410a16d036SRichard Henderson 
420a16d036SRichard Henderson /* 64-bit operations */
430a16d036SRichard Henderson #define TCG_TARGET_HAS_negsetcond_i64   0
440a16d036SRichard Henderson #define TCG_TARGET_HAS_div_i64          1
450a16d036SRichard Henderson #define TCG_TARGET_HAS_rem_i64          1
460a16d036SRichard Henderson #define TCG_TARGET_HAS_div2_i64         0
470a16d036SRichard Henderson #define TCG_TARGET_HAS_rot_i64          1
480a16d036SRichard Henderson #define TCG_TARGET_HAS_extract2_i64     0
490a16d036SRichard Henderson #define TCG_TARGET_HAS_extr_i64_i32     1
500a16d036SRichard Henderson #define TCG_TARGET_HAS_ext8s_i64        1
510a16d036SRichard Henderson #define TCG_TARGET_HAS_ext16s_i64       1
520a16d036SRichard Henderson #define TCG_TARGET_HAS_ext32s_i64       1
530a16d036SRichard Henderson #define TCG_TARGET_HAS_ext8u_i64        1
540a16d036SRichard Henderson #define TCG_TARGET_HAS_ext16u_i64       1
550a16d036SRichard Henderson #define TCG_TARGET_HAS_ext32u_i64       1
560a16d036SRichard Henderson #define TCG_TARGET_HAS_bswap16_i64      1
570a16d036SRichard Henderson #define TCG_TARGET_HAS_bswap32_i64      1
580a16d036SRichard Henderson #define TCG_TARGET_HAS_bswap64_i64      1
590a16d036SRichard Henderson #define TCG_TARGET_HAS_not_i64          1
600a16d036SRichard Henderson #define TCG_TARGET_HAS_andc_i64         1
610a16d036SRichard Henderson #define TCG_TARGET_HAS_orc_i64          1
620a16d036SRichard Henderson #define TCG_TARGET_HAS_eqv_i64          0
630a16d036SRichard Henderson #define TCG_TARGET_HAS_nand_i64         0
640a16d036SRichard Henderson #define TCG_TARGET_HAS_nor_i64          1
650a16d036SRichard Henderson #define TCG_TARGET_HAS_clz_i64          1
660a16d036SRichard Henderson #define TCG_TARGET_HAS_ctz_i64          1
670a16d036SRichard Henderson #define TCG_TARGET_HAS_ctpop_i64        0
680a16d036SRichard Henderson #define TCG_TARGET_HAS_add2_i64         0
690a16d036SRichard Henderson #define TCG_TARGET_HAS_sub2_i64         0
700a16d036SRichard Henderson #define TCG_TARGET_HAS_mulu2_i64        0
710a16d036SRichard Henderson #define TCG_TARGET_HAS_muls2_i64        0
720a16d036SRichard Henderson #define TCG_TARGET_HAS_muluh_i64        1
730a16d036SRichard Henderson #define TCG_TARGET_HAS_mulsh_i64        1
740a16d036SRichard Henderson 
750a16d036SRichard Henderson #define TCG_TARGET_HAS_qemu_ldst_i128   (cpuinfo & CPUINFO_LSX)
760a16d036SRichard Henderson 
770a16d036SRichard Henderson #define TCG_TARGET_HAS_tst              0
780a16d036SRichard Henderson 
790a16d036SRichard Henderson #define TCG_TARGET_HAS_v64              (cpuinfo & CPUINFO_LSX)
800a16d036SRichard Henderson #define TCG_TARGET_HAS_v128             (cpuinfo & CPUINFO_LSX)
810a16d036SRichard Henderson #define TCG_TARGET_HAS_v256             (cpuinfo & CPUINFO_LASX)
820a16d036SRichard Henderson 
830a16d036SRichard Henderson #define TCG_TARGET_HAS_not_vec          1
840a16d036SRichard Henderson #define TCG_TARGET_HAS_neg_vec          1
850a16d036SRichard Henderson #define TCG_TARGET_HAS_abs_vec          0
860a16d036SRichard Henderson #define TCG_TARGET_HAS_andc_vec         1
870a16d036SRichard Henderson #define TCG_TARGET_HAS_orc_vec          1
880a16d036SRichard Henderson #define TCG_TARGET_HAS_nand_vec         0
890a16d036SRichard Henderson #define TCG_TARGET_HAS_nor_vec          1
900a16d036SRichard Henderson #define TCG_TARGET_HAS_eqv_vec          0
910a16d036SRichard Henderson #define TCG_TARGET_HAS_mul_vec          1
920a16d036SRichard Henderson #define TCG_TARGET_HAS_shi_vec          1
930a16d036SRichard Henderson #define TCG_TARGET_HAS_shs_vec          0
940a16d036SRichard Henderson #define TCG_TARGET_HAS_shv_vec          1
950a16d036SRichard Henderson #define TCG_TARGET_HAS_roti_vec         1
960a16d036SRichard Henderson #define TCG_TARGET_HAS_rots_vec         0
970a16d036SRichard Henderson #define TCG_TARGET_HAS_rotv_vec         1
980a16d036SRichard Henderson #define TCG_TARGET_HAS_sat_vec          1
990a16d036SRichard Henderson #define TCG_TARGET_HAS_minmax_vec       1
1000a16d036SRichard Henderson #define TCG_TARGET_HAS_bitsel_vec       1
1010a16d036SRichard Henderson #define TCG_TARGET_HAS_cmpsel_vec       0
1020a16d036SRichard Henderson #define TCG_TARGET_HAS_tst_vec          0
1030a16d036SRichard Henderson 
1040c44a4d3SRichard Henderson #define TCG_TARGET_extract_valid(type, ofs, len)   1
105*6482e9d2SRichard Henderson #define TCG_TARGET_deposit_valid(type, ofs, len)   1
1060c44a4d3SRichard Henderson 
1070c44a4d3SRichard Henderson static inline bool
tcg_target_sextract_valid(TCGType type,unsigned ofs,unsigned len)1080c44a4d3SRichard Henderson tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len)
1090c44a4d3SRichard Henderson {
1100c44a4d3SRichard Henderson     if (type == TCG_TYPE_I64 && ofs + len == 32) {
1110c44a4d3SRichard Henderson         return true;
1120c44a4d3SRichard Henderson     }
1130c44a4d3SRichard Henderson     return ofs == 0 && (len == 8 || len == 16);
1140c44a4d3SRichard Henderson }
1150c44a4d3SRichard Henderson #define TCG_TARGET_sextract_valid  tcg_target_sextract_valid
1160a16d036SRichard Henderson 
1170a16d036SRichard Henderson #endif
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