1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #ifndef I386_TCG_TARGET_H 26 #define I386_TCG_TARGET_H 27 28 #define TCG_TARGET_INSN_UNIT_SIZE 1 29 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 31 30 31 #ifdef __x86_64__ 32 # define TCG_TARGET_REG_BITS 64 33 # define TCG_TARGET_NB_REGS 32 34 # define MAX_CODE_GEN_BUFFER_SIZE (2 * GiB) 35 #else 36 # define TCG_TARGET_REG_BITS 32 37 # define TCG_TARGET_NB_REGS 24 38 # define MAX_CODE_GEN_BUFFER_SIZE UINT32_MAX 39 #endif 40 41 typedef enum { 42 TCG_REG_EAX = 0, 43 TCG_REG_ECX, 44 TCG_REG_EDX, 45 TCG_REG_EBX, 46 TCG_REG_ESP, 47 TCG_REG_EBP, 48 TCG_REG_ESI, 49 TCG_REG_EDI, 50 51 /* 64-bit registers; always define the symbols to avoid 52 too much if-deffing. */ 53 TCG_REG_R8, 54 TCG_REG_R9, 55 TCG_REG_R10, 56 TCG_REG_R11, 57 TCG_REG_R12, 58 TCG_REG_R13, 59 TCG_REG_R14, 60 TCG_REG_R15, 61 62 TCG_REG_XMM0, 63 TCG_REG_XMM1, 64 TCG_REG_XMM2, 65 TCG_REG_XMM3, 66 TCG_REG_XMM4, 67 TCG_REG_XMM5, 68 TCG_REG_XMM6, 69 TCG_REG_XMM7, 70 71 /* 64-bit registers; likewise always define. */ 72 TCG_REG_XMM8, 73 TCG_REG_XMM9, 74 TCG_REG_XMM10, 75 TCG_REG_XMM11, 76 TCG_REG_XMM12, 77 TCG_REG_XMM13, 78 TCG_REG_XMM14, 79 TCG_REG_XMM15, 80 81 TCG_REG_RAX = TCG_REG_EAX, 82 TCG_REG_RCX = TCG_REG_ECX, 83 TCG_REG_RDX = TCG_REG_EDX, 84 TCG_REG_RBX = TCG_REG_EBX, 85 TCG_REG_RSP = TCG_REG_ESP, 86 TCG_REG_RBP = TCG_REG_EBP, 87 TCG_REG_RSI = TCG_REG_ESI, 88 TCG_REG_RDI = TCG_REG_EDI, 89 90 TCG_AREG0 = TCG_REG_EBP, 91 TCG_REG_CALL_STACK = TCG_REG_ESP 92 } TCGReg; 93 94 /* used for function call generation */ 95 #define TCG_TARGET_STACK_ALIGN 16 96 #if defined(_WIN64) 97 #define TCG_TARGET_CALL_STACK_OFFSET 32 98 #else 99 #define TCG_TARGET_CALL_STACK_OFFSET 0 100 #endif 101 102 extern bool have_bmi1; 103 extern bool have_popcnt; 104 extern bool have_avx1; 105 extern bool have_avx2; 106 extern bool have_movbe; 107 108 /* optional instructions */ 109 #define TCG_TARGET_HAS_div2_i32 1 110 #define TCG_TARGET_HAS_rot_i32 1 111 #define TCG_TARGET_HAS_ext8s_i32 1 112 #define TCG_TARGET_HAS_ext16s_i32 1 113 #define TCG_TARGET_HAS_ext8u_i32 1 114 #define TCG_TARGET_HAS_ext16u_i32 1 115 #define TCG_TARGET_HAS_bswap16_i32 1 116 #define TCG_TARGET_HAS_bswap32_i32 1 117 #define TCG_TARGET_HAS_neg_i32 1 118 #define TCG_TARGET_HAS_not_i32 1 119 #define TCG_TARGET_HAS_andc_i32 have_bmi1 120 #define TCG_TARGET_HAS_orc_i32 0 121 #define TCG_TARGET_HAS_eqv_i32 0 122 #define TCG_TARGET_HAS_nand_i32 0 123 #define TCG_TARGET_HAS_nor_i32 0 124 #define TCG_TARGET_HAS_clz_i32 1 125 #define TCG_TARGET_HAS_ctz_i32 1 126 #define TCG_TARGET_HAS_ctpop_i32 have_popcnt 127 #define TCG_TARGET_HAS_deposit_i32 1 128 #define TCG_TARGET_HAS_extract_i32 1 129 #define TCG_TARGET_HAS_sextract_i32 1 130 #define TCG_TARGET_HAS_extract2_i32 1 131 #define TCG_TARGET_HAS_movcond_i32 1 132 #define TCG_TARGET_HAS_add2_i32 1 133 #define TCG_TARGET_HAS_sub2_i32 1 134 #define TCG_TARGET_HAS_mulu2_i32 1 135 #define TCG_TARGET_HAS_muls2_i32 1 136 #define TCG_TARGET_HAS_muluh_i32 0 137 #define TCG_TARGET_HAS_mulsh_i32 0 138 #define TCG_TARGET_HAS_direct_jump 1 139 140 #if TCG_TARGET_REG_BITS == 64 141 /* Keep target addresses zero-extended in a register. */ 142 #define TCG_TARGET_HAS_extrl_i64_i32 (TARGET_LONG_BITS == 32) 143 #define TCG_TARGET_HAS_extrh_i64_i32 (TARGET_LONG_BITS == 32) 144 #define TCG_TARGET_HAS_div2_i64 1 145 #define TCG_TARGET_HAS_rot_i64 1 146 #define TCG_TARGET_HAS_ext8s_i64 1 147 #define TCG_TARGET_HAS_ext16s_i64 1 148 #define TCG_TARGET_HAS_ext32s_i64 1 149 #define TCG_TARGET_HAS_ext8u_i64 1 150 #define TCG_TARGET_HAS_ext16u_i64 1 151 #define TCG_TARGET_HAS_ext32u_i64 1 152 #define TCG_TARGET_HAS_bswap16_i64 1 153 #define TCG_TARGET_HAS_bswap32_i64 1 154 #define TCG_TARGET_HAS_bswap64_i64 1 155 #define TCG_TARGET_HAS_neg_i64 1 156 #define TCG_TARGET_HAS_not_i64 1 157 #define TCG_TARGET_HAS_andc_i64 have_bmi1 158 #define TCG_TARGET_HAS_orc_i64 0 159 #define TCG_TARGET_HAS_eqv_i64 0 160 #define TCG_TARGET_HAS_nand_i64 0 161 #define TCG_TARGET_HAS_nor_i64 0 162 #define TCG_TARGET_HAS_clz_i64 1 163 #define TCG_TARGET_HAS_ctz_i64 1 164 #define TCG_TARGET_HAS_ctpop_i64 have_popcnt 165 #define TCG_TARGET_HAS_deposit_i64 1 166 #define TCG_TARGET_HAS_extract_i64 1 167 #define TCG_TARGET_HAS_sextract_i64 0 168 #define TCG_TARGET_HAS_extract2_i64 1 169 #define TCG_TARGET_HAS_movcond_i64 1 170 #define TCG_TARGET_HAS_add2_i64 1 171 #define TCG_TARGET_HAS_sub2_i64 1 172 #define TCG_TARGET_HAS_mulu2_i64 1 173 #define TCG_TARGET_HAS_muls2_i64 1 174 #define TCG_TARGET_HAS_muluh_i64 0 175 #define TCG_TARGET_HAS_mulsh_i64 0 176 #define TCG_TARGET_HAS_qemu_st8_i32 0 177 #else 178 #define TCG_TARGET_HAS_qemu_st8_i32 1 179 #endif 180 181 /* We do not support older SSE systems, only beginning with AVX1. */ 182 #define TCG_TARGET_HAS_v64 have_avx1 183 #define TCG_TARGET_HAS_v128 have_avx1 184 #define TCG_TARGET_HAS_v256 have_avx2 185 186 #define TCG_TARGET_HAS_andc_vec 1 187 #define TCG_TARGET_HAS_orc_vec 0 188 #define TCG_TARGET_HAS_not_vec 0 189 #define TCG_TARGET_HAS_neg_vec 0 190 #define TCG_TARGET_HAS_abs_vec 1 191 #define TCG_TARGET_HAS_roti_vec 0 192 #define TCG_TARGET_HAS_rots_vec 0 193 #define TCG_TARGET_HAS_rotv_vec 0 194 #define TCG_TARGET_HAS_shi_vec 1 195 #define TCG_TARGET_HAS_shs_vec 1 196 #define TCG_TARGET_HAS_shv_vec have_avx2 197 #define TCG_TARGET_HAS_mul_vec 1 198 #define TCG_TARGET_HAS_sat_vec 1 199 #define TCG_TARGET_HAS_minmax_vec 1 200 #define TCG_TARGET_HAS_bitsel_vec 0 201 #define TCG_TARGET_HAS_cmpsel_vec -1 202 203 #define TCG_TARGET_deposit_i32_valid(ofs, len) \ 204 (((ofs) == 0 && (len) == 8) || ((ofs) == 8 && (len) == 8) || \ 205 ((ofs) == 0 && (len) == 16)) 206 #define TCG_TARGET_deposit_i64_valid TCG_TARGET_deposit_i32_valid 207 208 /* Check for the possibility of high-byte extraction and, for 64-bit, 209 zero-extending 32-bit right-shift. */ 210 #define TCG_TARGET_extract_i32_valid(ofs, len) ((ofs) == 8 && (len) == 8) 211 #define TCG_TARGET_extract_i64_valid(ofs, len) \ 212 (((ofs) == 8 && (len) == 8) || ((ofs) + (len)) == 32) 213 214 static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, 215 uintptr_t jmp_rw, uintptr_t addr) 216 { 217 /* patch the branch destination */ 218 qatomic_set((int32_t *)jmp_rw, addr - (jmp_rx + 4)); 219 /* no need to flush icache explicitly */ 220 } 221 222 /* This defines the natural memory order supported by this 223 * architecture before guarantees made by various barrier 224 * instructions. 225 * 226 * The x86 has a pretty strong memory ordering which only really 227 * allows for some stores to be re-ordered after loads. 228 */ 229 #include "tcg/tcg-mo.h" 230 231 #define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) 232 233 #define TCG_TARGET_HAS_MEMORY_BSWAP have_movbe 234 235 #define TCG_TARGET_NEED_LDST_LABELS 236 #define TCG_TARGET_NEED_POOL_LABELS 237 238 #endif 239