1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #define TCG_TARGET_I386 1 25 26 //#define TCG_TARGET_WORDS_BIGENDIAN 27 28 #if TCG_TARGET_REG_BITS == 64 29 # define TCG_TARGET_NB_REGS 16 30 #else 31 # define TCG_TARGET_NB_REGS 8 32 #endif 33 34 typedef enum { 35 TCG_REG_EAX = 0, 36 TCG_REG_ECX, 37 TCG_REG_EDX, 38 TCG_REG_EBX, 39 TCG_REG_ESP, 40 TCG_REG_EBP, 41 TCG_REG_ESI, 42 TCG_REG_EDI, 43 44 /* 64-bit registers; always define the symbols to avoid 45 too much if-deffing. */ 46 TCG_REG_R8, 47 TCG_REG_R9, 48 TCG_REG_R10, 49 TCG_REG_R11, 50 TCG_REG_R12, 51 TCG_REG_R13, 52 TCG_REG_R14, 53 TCG_REG_R15, 54 TCG_REG_RAX = TCG_REG_EAX, 55 TCG_REG_RCX = TCG_REG_ECX, 56 TCG_REG_RDX = TCG_REG_EDX, 57 TCG_REG_RBX = TCG_REG_EBX, 58 TCG_REG_RSP = TCG_REG_ESP, 59 TCG_REG_RBP = TCG_REG_EBP, 60 TCG_REG_RSI = TCG_REG_ESI, 61 TCG_REG_RDI = TCG_REG_EDI, 62 } TCGReg; 63 64 #define TCG_CT_CONST_S32 0x100 65 #define TCG_CT_CONST_U32 0x200 66 67 /* used for function call generation */ 68 #define TCG_REG_CALL_STACK TCG_REG_ESP 69 #define TCG_TARGET_STACK_ALIGN 16 70 #if defined(_WIN64) 71 #define TCG_TARGET_CALL_STACK_OFFSET 32 72 #else 73 #define TCG_TARGET_CALL_STACK_OFFSET 0 74 #endif 75 76 /* optional instructions */ 77 #define TCG_TARGET_HAS_div2_i32 1 78 #define TCG_TARGET_HAS_rot_i32 1 79 #define TCG_TARGET_HAS_ext8s_i32 1 80 #define TCG_TARGET_HAS_ext16s_i32 1 81 #define TCG_TARGET_HAS_ext8u_i32 1 82 #define TCG_TARGET_HAS_ext16u_i32 1 83 #define TCG_TARGET_HAS_bswap16_i32 1 84 #define TCG_TARGET_HAS_bswap32_i32 1 85 #define TCG_TARGET_HAS_neg_i32 1 86 #define TCG_TARGET_HAS_not_i32 1 87 #define TCG_TARGET_HAS_andc_i32 0 88 #define TCG_TARGET_HAS_orc_i32 0 89 #define TCG_TARGET_HAS_eqv_i32 0 90 #define TCG_TARGET_HAS_nand_i32 0 91 #define TCG_TARGET_HAS_nor_i32 0 92 #define TCG_TARGET_HAS_deposit_i32 1 93 #if defined(__x86_64__) || defined(__i686__) 94 /* Use cmov only if the compiler is already doing so. */ 95 #define TCG_TARGET_HAS_movcond_i32 1 96 #else 97 #define TCG_TARGET_HAS_movcond_i32 0 98 #endif 99 100 #if TCG_TARGET_REG_BITS == 64 101 #define TCG_TARGET_HAS_div2_i64 1 102 #define TCG_TARGET_HAS_rot_i64 1 103 #define TCG_TARGET_HAS_ext8s_i64 1 104 #define TCG_TARGET_HAS_ext16s_i64 1 105 #define TCG_TARGET_HAS_ext32s_i64 1 106 #define TCG_TARGET_HAS_ext8u_i64 1 107 #define TCG_TARGET_HAS_ext16u_i64 1 108 #define TCG_TARGET_HAS_ext32u_i64 1 109 #define TCG_TARGET_HAS_bswap16_i64 1 110 #define TCG_TARGET_HAS_bswap32_i64 1 111 #define TCG_TARGET_HAS_bswap64_i64 1 112 #define TCG_TARGET_HAS_neg_i64 1 113 #define TCG_TARGET_HAS_not_i64 1 114 #define TCG_TARGET_HAS_andc_i64 0 115 #define TCG_TARGET_HAS_orc_i64 0 116 #define TCG_TARGET_HAS_eqv_i64 0 117 #define TCG_TARGET_HAS_nand_i64 0 118 #define TCG_TARGET_HAS_nor_i64 0 119 #define TCG_TARGET_HAS_deposit_i64 1 120 #define TCG_TARGET_HAS_movcond_i64 1 121 #endif 122 123 #define TCG_TARGET_deposit_i32_valid(ofs, len) \ 124 (((ofs) == 0 && (len) == 8) || ((ofs) == 8 && (len) == 8) || \ 125 ((ofs) == 0 && (len) == 16)) 126 #define TCG_TARGET_deposit_i64_valid TCG_TARGET_deposit_i32_valid 127 128 #if TCG_TARGET_REG_BITS == 64 129 # define TCG_AREG0 TCG_REG_R14 130 #else 131 # define TCG_AREG0 TCG_REG_EBP 132 #endif 133 134 static inline void flush_icache_range(tcg_target_ulong start, 135 tcg_target_ulong stop) 136 { 137 } 138