1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25/* Used for function call generation. */ 26#define TCG_TARGET_STACK_ALIGN 16 27#if defined(_WIN64) 28#define TCG_TARGET_CALL_STACK_OFFSET 32 29#else 30#define TCG_TARGET_CALL_STACK_OFFSET 0 31#endif 32#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL 33#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL 34#if defined(_WIN64) 35# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_BY_REF 36# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_VEC 37#elif TCG_TARGET_REG_BITS == 64 38# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL 39# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL 40#else 41# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL 42# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF 43#endif 44 45#ifdef CONFIG_DEBUG_TCG 46static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 47#if TCG_TARGET_REG_BITS == 64 48 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", 49#else 50 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", 51#endif 52 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", 53 "%xmm0", "%xmm1", "%xmm2", "%xmm3", "%xmm4", "%xmm5", "%xmm6", "%xmm7", 54#if TCG_TARGET_REG_BITS == 64 55 "%xmm8", "%xmm9", "%xmm10", "%xmm11", 56 "%xmm12", "%xmm13", "%xmm14", "%xmm15", 57#endif 58}; 59#endif 60 61static const int tcg_target_reg_alloc_order[] = { 62#if TCG_TARGET_REG_BITS == 64 63 TCG_REG_RBP, 64 TCG_REG_RBX, 65 TCG_REG_R12, 66 TCG_REG_R13, 67 TCG_REG_R14, 68 TCG_REG_R15, 69 TCG_REG_R10, 70 TCG_REG_R11, 71 TCG_REG_R9, 72 TCG_REG_R8, 73 TCG_REG_RCX, 74 TCG_REG_RDX, 75 TCG_REG_RSI, 76 TCG_REG_RDI, 77 TCG_REG_RAX, 78#else 79 TCG_REG_EBX, 80 TCG_REG_ESI, 81 TCG_REG_EDI, 82 TCG_REG_EBP, 83 TCG_REG_ECX, 84 TCG_REG_EDX, 85 TCG_REG_EAX, 86#endif 87 TCG_REG_XMM0, 88 TCG_REG_XMM1, 89 TCG_REG_XMM2, 90 TCG_REG_XMM3, 91 TCG_REG_XMM4, 92 TCG_REG_XMM5, 93#ifndef _WIN64 94 /* The Win64 ABI has xmm6-xmm15 as caller-saves, and we do not save 95 any of them. Therefore only allow xmm0-xmm5 to be allocated. */ 96 TCG_REG_XMM6, 97 TCG_REG_XMM7, 98#if TCG_TARGET_REG_BITS == 64 99 TCG_REG_XMM8, 100 TCG_REG_XMM9, 101 TCG_REG_XMM10, 102 TCG_REG_XMM11, 103 TCG_REG_XMM12, 104 TCG_REG_XMM13, 105 TCG_REG_XMM14, 106 TCG_REG_XMM15, 107#endif 108#endif 109}; 110 111#define TCG_TMP_VEC TCG_REG_XMM5 112 113static const int tcg_target_call_iarg_regs[] = { 114#if TCG_TARGET_REG_BITS == 64 115#if defined(_WIN64) 116 TCG_REG_RCX, 117 TCG_REG_RDX, 118#else 119 TCG_REG_RDI, 120 TCG_REG_RSI, 121 TCG_REG_RDX, 122 TCG_REG_RCX, 123#endif 124 TCG_REG_R8, 125 TCG_REG_R9, 126#else 127 /* 32 bit mode uses stack based calling convention (GCC default). */ 128#endif 129}; 130 131static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 132{ 133 switch (kind) { 134 case TCG_CALL_RET_NORMAL: 135 tcg_debug_assert(slot >= 0 && slot <= 1); 136 return slot ? TCG_REG_EDX : TCG_REG_EAX; 137#ifdef _WIN64 138 case TCG_CALL_RET_BY_VEC: 139 tcg_debug_assert(slot == 0); 140 return TCG_REG_XMM0; 141#endif 142 default: 143 g_assert_not_reached(); 144 } 145} 146 147/* Constants we accept. */ 148#define TCG_CT_CONST_S32 0x100 149#define TCG_CT_CONST_U32 0x200 150#define TCG_CT_CONST_I32 0x400 151#define TCG_CT_CONST_WSZ 0x800 152#define TCG_CT_CONST_TST 0x1000 153#define TCG_CT_CONST_ZERO 0x2000 154 155/* Registers used with L constraint, which are the first argument 156 registers on x86_64, and two random call clobbered registers on 157 i386. */ 158#if TCG_TARGET_REG_BITS == 64 159# define TCG_REG_L0 tcg_target_call_iarg_regs[0] 160# define TCG_REG_L1 tcg_target_call_iarg_regs[1] 161#else 162# define TCG_REG_L0 TCG_REG_EAX 163# define TCG_REG_L1 TCG_REG_EDX 164#endif 165 166#if TCG_TARGET_REG_BITS == 64 167# define ALL_GENERAL_REGS 0x0000ffffu 168# define ALL_VECTOR_REGS 0xffff0000u 169# define ALL_BYTEL_REGS ALL_GENERAL_REGS 170#else 171# define ALL_GENERAL_REGS 0x000000ffu 172# define ALL_VECTOR_REGS 0x00ff0000u 173# define ALL_BYTEL_REGS 0x0000000fu 174#endif 175#define SOFTMMU_RESERVE_REGS \ 176 (tcg_use_softmmu ? (1 << TCG_REG_L0) | (1 << TCG_REG_L1) : 0) 177 178#define have_bmi2 (cpuinfo & CPUINFO_BMI2) 179#define have_lzcnt (cpuinfo & CPUINFO_LZCNT) 180 181static const tcg_insn_unit *tb_ret_addr; 182 183static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 184 intptr_t value, intptr_t addend) 185{ 186 value += addend; 187 switch(type) { 188 case R_386_PC32: 189 value -= (uintptr_t)tcg_splitwx_to_rx(code_ptr); 190 if (value != (int32_t)value) { 191 return false; 192 } 193 /* FALLTHRU */ 194 case R_386_32: 195 tcg_patch32(code_ptr, value); 196 break; 197 case R_386_PC8: 198 value -= (uintptr_t)tcg_splitwx_to_rx(code_ptr); 199 if (value != (int8_t)value) { 200 return false; 201 } 202 tcg_patch8(code_ptr, value); 203 break; 204 default: 205 g_assert_not_reached(); 206 } 207 return true; 208} 209 210/* test if a constant matches the constraint */ 211static bool tcg_target_const_match(int64_t val, int ct, 212 TCGType type, TCGCond cond, int vece) 213{ 214 if (ct & TCG_CT_CONST) { 215 return 1; 216 } 217 if (type == TCG_TYPE_I32) { 218 if (ct & (TCG_CT_CONST_S32 | TCG_CT_CONST_U32 | 219 TCG_CT_CONST_I32 | TCG_CT_CONST_TST)) { 220 return 1; 221 } 222 } else { 223 if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) { 224 return 1; 225 } 226 if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) { 227 return 1; 228 } 229 if ((ct & TCG_CT_CONST_I32) && ~val == (int32_t)~val) { 230 return 1; 231 } 232 /* 233 * This will be used in combination with TCG_CT_CONST_S32, 234 * so "normal" TESTQ is already matched. Also accept: 235 * TESTQ -> TESTL (uint32_t) 236 * TESTQ -> BT (is_power_of_2) 237 */ 238 if ((ct & TCG_CT_CONST_TST) 239 && is_tst_cond(cond) 240 && (val == (uint32_t)val || is_power_of_2(val))) { 241 return 1; 242 } 243 } 244 if ((ct & TCG_CT_CONST_WSZ) && val == (type == TCG_TYPE_I32 ? 32 : 64)) { 245 return 1; 246 } 247 if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 248 return 1; 249 } 250 return 0; 251} 252 253# define LOWREGMASK(x) ((x) & 7) 254 255#define P_EXT 0x100 /* 0x0f opcode prefix */ 256#define P_EXT38 0x200 /* 0x0f 0x38 opcode prefix */ 257#define P_DATA16 0x400 /* 0x66 opcode prefix */ 258#define P_VEXW 0x1000 /* Set VEX.W = 1 */ 259#if TCG_TARGET_REG_BITS == 64 260# define P_REXW P_VEXW /* Set REX.W = 1; match VEXW */ 261# define P_REXB_R 0x2000 /* REG field as byte register */ 262# define P_REXB_RM 0x4000 /* R/M field as byte register */ 263# define P_GS 0x8000 /* gs segment override */ 264#else 265# define P_REXW 0 266# define P_REXB_R 0 267# define P_REXB_RM 0 268# define P_GS 0 269#endif 270#define P_EXT3A 0x10000 /* 0x0f 0x3a opcode prefix */ 271#define P_SIMDF3 0x20000 /* 0xf3 opcode prefix */ 272#define P_SIMDF2 0x40000 /* 0xf2 opcode prefix */ 273#define P_VEXL 0x80000 /* Set VEX.L = 1 */ 274#define P_EVEX 0x100000 /* Requires EVEX encoding */ 275 276#define OPC_ARITH_EbIb (0x80) 277#define OPC_ARITH_EvIz (0x81) 278#define OPC_ARITH_EvIb (0x83) 279#define OPC_ARITH_GvEv (0x03) /* ... plus (ARITH_FOO << 3) */ 280#define OPC_ANDN (0xf2 | P_EXT38) 281#define OPC_ADD_GvEv (OPC_ARITH_GvEv | (ARITH_ADD << 3)) 282#define OPC_AND_GvEv (OPC_ARITH_GvEv | (ARITH_AND << 3)) 283#define OPC_BLENDPS (0x0c | P_EXT3A | P_DATA16) 284#define OPC_BSF (0xbc | P_EXT) 285#define OPC_BSR (0xbd | P_EXT) 286#define OPC_BSWAP (0xc8 | P_EXT) 287#define OPC_CALL_Jz (0xe8) 288#define OPC_CMOVCC (0x40 | P_EXT) /* ... plus condition code */ 289#define OPC_CMP_GvEv (OPC_ARITH_GvEv | (ARITH_CMP << 3)) 290#define OPC_DEC_r32 (0x48) 291#define OPC_IMUL_GvEv (0xaf | P_EXT) 292#define OPC_IMUL_GvEvIb (0x6b) 293#define OPC_IMUL_GvEvIz (0x69) 294#define OPC_INC_r32 (0x40) 295#define OPC_JCC_long (0x80 | P_EXT) /* ... plus condition code */ 296#define OPC_JCC_short (0x70) /* ... plus condition code */ 297#define OPC_JMP_long (0xe9) 298#define OPC_JMP_short (0xeb) 299#define OPC_LEA (0x8d) 300#define OPC_LZCNT (0xbd | P_EXT | P_SIMDF3) 301#define OPC_MOVB_EvGv (0x88) /* stores, more or less */ 302#define OPC_MOVL_EvGv (0x89) /* stores, more or less */ 303#define OPC_MOVL_GvEv (0x8b) /* loads, more or less */ 304#define OPC_MOVB_EvIz (0xc6) 305#define OPC_MOVL_EvIz (0xc7) 306#define OPC_MOVB_Ib (0xb0) 307#define OPC_MOVL_Iv (0xb8) 308#define OPC_MOVBE_GyMy (0xf0 | P_EXT38) 309#define OPC_MOVBE_MyGy (0xf1 | P_EXT38) 310#define OPC_MOVD_VyEy (0x6e | P_EXT | P_DATA16) 311#define OPC_MOVD_EyVy (0x7e | P_EXT | P_DATA16) 312#define OPC_MOVDDUP (0x12 | P_EXT | P_SIMDF2) 313#define OPC_MOVDQA_VxWx (0x6f | P_EXT | P_DATA16) 314#define OPC_MOVDQA_WxVx (0x7f | P_EXT | P_DATA16) 315#define OPC_MOVDQU_VxWx (0x6f | P_EXT | P_SIMDF3) 316#define OPC_MOVDQU_WxVx (0x7f | P_EXT | P_SIMDF3) 317#define OPC_MOVQ_VqWq (0x7e | P_EXT | P_SIMDF3) 318#define OPC_MOVQ_WqVq (0xd6 | P_EXT | P_DATA16) 319#define OPC_MOVSBL (0xbe | P_EXT) 320#define OPC_MOVSWL (0xbf | P_EXT) 321#define OPC_MOVSLQ (0x63 | P_REXW) 322#define OPC_MOVZBL (0xb6 | P_EXT) 323#define OPC_MOVZWL (0xb7 | P_EXT) 324#define OPC_PABSB (0x1c | P_EXT38 | P_DATA16) 325#define OPC_PABSW (0x1d | P_EXT38 | P_DATA16) 326#define OPC_PABSD (0x1e | P_EXT38 | P_DATA16) 327#define OPC_VPABSQ (0x1f | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 328#define OPC_PACKSSDW (0x6b | P_EXT | P_DATA16) 329#define OPC_PACKSSWB (0x63 | P_EXT | P_DATA16) 330#define OPC_PACKUSDW (0x2b | P_EXT38 | P_DATA16) 331#define OPC_PACKUSWB (0x67 | P_EXT | P_DATA16) 332#define OPC_PADDB (0xfc | P_EXT | P_DATA16) 333#define OPC_PADDW (0xfd | P_EXT | P_DATA16) 334#define OPC_PADDD (0xfe | P_EXT | P_DATA16) 335#define OPC_PADDQ (0xd4 | P_EXT | P_DATA16) 336#define OPC_PADDSB (0xec | P_EXT | P_DATA16) 337#define OPC_PADDSW (0xed | P_EXT | P_DATA16) 338#define OPC_PADDUB (0xdc | P_EXT | P_DATA16) 339#define OPC_PADDUW (0xdd | P_EXT | P_DATA16) 340#define OPC_PAND (0xdb | P_EXT | P_DATA16) 341#define OPC_PANDN (0xdf | P_EXT | P_DATA16) 342#define OPC_PBLENDW (0x0e | P_EXT3A | P_DATA16) 343#define OPC_PCMPEQB (0x74 | P_EXT | P_DATA16) 344#define OPC_PCMPEQW (0x75 | P_EXT | P_DATA16) 345#define OPC_PCMPEQD (0x76 | P_EXT | P_DATA16) 346#define OPC_PCMPEQQ (0x29 | P_EXT38 | P_DATA16) 347#define OPC_PCMPGTB (0x64 | P_EXT | P_DATA16) 348#define OPC_PCMPGTW (0x65 | P_EXT | P_DATA16) 349#define OPC_PCMPGTD (0x66 | P_EXT | P_DATA16) 350#define OPC_PCMPGTQ (0x37 | P_EXT38 | P_DATA16) 351#define OPC_PEXTRD (0x16 | P_EXT3A | P_DATA16) 352#define OPC_PINSRD (0x22 | P_EXT3A | P_DATA16) 353#define OPC_PMAXSB (0x3c | P_EXT38 | P_DATA16) 354#define OPC_PMAXSW (0xee | P_EXT | P_DATA16) 355#define OPC_PMAXSD (0x3d | P_EXT38 | P_DATA16) 356#define OPC_VPMAXSQ (0x3d | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 357#define OPC_PMAXUB (0xde | P_EXT | P_DATA16) 358#define OPC_PMAXUW (0x3e | P_EXT38 | P_DATA16) 359#define OPC_PMAXUD (0x3f | P_EXT38 | P_DATA16) 360#define OPC_VPMAXUQ (0x3f | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 361#define OPC_PMINSB (0x38 | P_EXT38 | P_DATA16) 362#define OPC_PMINSW (0xea | P_EXT | P_DATA16) 363#define OPC_PMINSD (0x39 | P_EXT38 | P_DATA16) 364#define OPC_VPMINSQ (0x39 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 365#define OPC_PMINUB (0xda | P_EXT | P_DATA16) 366#define OPC_PMINUW (0x3a | P_EXT38 | P_DATA16) 367#define OPC_PMINUD (0x3b | P_EXT38 | P_DATA16) 368#define OPC_VPMINUQ (0x3b | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 369#define OPC_PMOVSXBW (0x20 | P_EXT38 | P_DATA16) 370#define OPC_PMOVSXWD (0x23 | P_EXT38 | P_DATA16) 371#define OPC_PMOVSXDQ (0x25 | P_EXT38 | P_DATA16) 372#define OPC_PMOVZXBW (0x30 | P_EXT38 | P_DATA16) 373#define OPC_PMOVZXWD (0x33 | P_EXT38 | P_DATA16) 374#define OPC_PMOVZXDQ (0x35 | P_EXT38 | P_DATA16) 375#define OPC_PMULLW (0xd5 | P_EXT | P_DATA16) 376#define OPC_PMULLD (0x40 | P_EXT38 | P_DATA16) 377#define OPC_VPMULLQ (0x40 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 378#define OPC_POR (0xeb | P_EXT | P_DATA16) 379#define OPC_PSHUFB (0x00 | P_EXT38 | P_DATA16) 380#define OPC_PSHUFD (0x70 | P_EXT | P_DATA16) 381#define OPC_PSHUFLW (0x70 | P_EXT | P_SIMDF2) 382#define OPC_PSHUFHW (0x70 | P_EXT | P_SIMDF3) 383#define OPC_PSHIFTW_Ib (0x71 | P_EXT | P_DATA16) /* /2 /6 /4 */ 384#define OPC_PSHIFTD_Ib (0x72 | P_EXT | P_DATA16) /* /1 /2 /6 /4 */ 385#define OPC_PSHIFTQ_Ib (0x73 | P_EXT | P_DATA16) /* /2 /6 /4 */ 386#define OPC_PSLLW (0xf1 | P_EXT | P_DATA16) 387#define OPC_PSLLD (0xf2 | P_EXT | P_DATA16) 388#define OPC_PSLLQ (0xf3 | P_EXT | P_DATA16) 389#define OPC_PSRAW (0xe1 | P_EXT | P_DATA16) 390#define OPC_PSRAD (0xe2 | P_EXT | P_DATA16) 391#define OPC_VPSRAQ (0xe2 | P_EXT | P_DATA16 | P_VEXW | P_EVEX) 392#define OPC_PSRLW (0xd1 | P_EXT | P_DATA16) 393#define OPC_PSRLD (0xd2 | P_EXT | P_DATA16) 394#define OPC_PSRLQ (0xd3 | P_EXT | P_DATA16) 395#define OPC_PSUBB (0xf8 | P_EXT | P_DATA16) 396#define OPC_PSUBW (0xf9 | P_EXT | P_DATA16) 397#define OPC_PSUBD (0xfa | P_EXT | P_DATA16) 398#define OPC_PSUBQ (0xfb | P_EXT | P_DATA16) 399#define OPC_PSUBSB (0xe8 | P_EXT | P_DATA16) 400#define OPC_PSUBSW (0xe9 | P_EXT | P_DATA16) 401#define OPC_PSUBUB (0xd8 | P_EXT | P_DATA16) 402#define OPC_PSUBUW (0xd9 | P_EXT | P_DATA16) 403#define OPC_PUNPCKLBW (0x60 | P_EXT | P_DATA16) 404#define OPC_PUNPCKLWD (0x61 | P_EXT | P_DATA16) 405#define OPC_PUNPCKLDQ (0x62 | P_EXT | P_DATA16) 406#define OPC_PUNPCKLQDQ (0x6c | P_EXT | P_DATA16) 407#define OPC_PUNPCKHBW (0x68 | P_EXT | P_DATA16) 408#define OPC_PUNPCKHWD (0x69 | P_EXT | P_DATA16) 409#define OPC_PUNPCKHDQ (0x6a | P_EXT | P_DATA16) 410#define OPC_PUNPCKHQDQ (0x6d | P_EXT | P_DATA16) 411#define OPC_PXOR (0xef | P_EXT | P_DATA16) 412#define OPC_POP_r32 (0x58) 413#define OPC_POPCNT (0xb8 | P_EXT | P_SIMDF3) 414#define OPC_PUSH_r32 (0x50) 415#define OPC_PUSH_Iv (0x68) 416#define OPC_PUSH_Ib (0x6a) 417#define OPC_RET (0xc3) 418#define OPC_SETCC (0x90 | P_EXT | P_REXB_RM) /* ... plus cc */ 419#define OPC_SHIFT_1 (0xd1) 420#define OPC_SHIFT_Ib (0xc1) 421#define OPC_SHIFT_cl (0xd3) 422#define OPC_SARX (0xf7 | P_EXT38 | P_SIMDF3) 423#define OPC_SHUFPS (0xc6 | P_EXT) 424#define OPC_SHLX (0xf7 | P_EXT38 | P_DATA16) 425#define OPC_SHRX (0xf7 | P_EXT38 | P_SIMDF2) 426#define OPC_SHRD_Ib (0xac | P_EXT) 427#define OPC_STC (0xf9) 428#define OPC_TESTB (0x84) 429#define OPC_TESTL (0x85) 430#define OPC_TZCNT (0xbc | P_EXT | P_SIMDF3) 431#define OPC_UD2 (0x0b | P_EXT) 432#define OPC_VPBLENDD (0x02 | P_EXT3A | P_DATA16) 433#define OPC_VPBLENDVB (0x4c | P_EXT3A | P_DATA16) 434#define OPC_VPBLENDMB (0x66 | P_EXT38 | P_DATA16 | P_EVEX) 435#define OPC_VPBLENDMW (0x66 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 436#define OPC_VPBLENDMD (0x64 | P_EXT38 | P_DATA16 | P_EVEX) 437#define OPC_VPBLENDMQ (0x64 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 438#define OPC_VPCMPB (0x3f | P_EXT3A | P_DATA16 | P_EVEX) 439#define OPC_VPCMPUB (0x3e | P_EXT3A | P_DATA16 | P_EVEX) 440#define OPC_VPCMPW (0x3f | P_EXT3A | P_DATA16 | P_VEXW | P_EVEX) 441#define OPC_VPCMPUW (0x3e | P_EXT3A | P_DATA16 | P_VEXW | P_EVEX) 442#define OPC_VPCMPD (0x1f | P_EXT3A | P_DATA16 | P_EVEX) 443#define OPC_VPCMPUD (0x1e | P_EXT3A | P_DATA16 | P_EVEX) 444#define OPC_VPCMPQ (0x1f | P_EXT3A | P_DATA16 | P_VEXW | P_EVEX) 445#define OPC_VPCMPUQ (0x1e | P_EXT3A | P_DATA16 | P_VEXW | P_EVEX) 446#define OPC_VPINSRB (0x20 | P_EXT3A | P_DATA16) 447#define OPC_VPINSRW (0xc4 | P_EXT | P_DATA16) 448#define OPC_VBROADCASTSS (0x18 | P_EXT38 | P_DATA16) 449#define OPC_VBROADCASTSD (0x19 | P_EXT38 | P_DATA16) 450#define OPC_VPBROADCASTB (0x78 | P_EXT38 | P_DATA16) 451#define OPC_VPBROADCASTW (0x79 | P_EXT38 | P_DATA16) 452#define OPC_VPBROADCASTD (0x58 | P_EXT38 | P_DATA16) 453#define OPC_VPBROADCASTQ (0x59 | P_EXT38 | P_DATA16) 454#define OPC_VPMOVM2B (0x28 | P_EXT38 | P_SIMDF3 | P_EVEX) 455#define OPC_VPMOVM2W (0x28 | P_EXT38 | P_SIMDF3 | P_VEXW | P_EVEX) 456#define OPC_VPMOVM2D (0x38 | P_EXT38 | P_SIMDF3 | P_EVEX) 457#define OPC_VPMOVM2Q (0x38 | P_EXT38 | P_SIMDF3 | P_VEXW | P_EVEX) 458#define OPC_VPERMQ (0x00 | P_EXT3A | P_DATA16 | P_VEXW) 459#define OPC_VPERM2I128 (0x46 | P_EXT3A | P_DATA16 | P_VEXL) 460#define OPC_VPROLVD (0x15 | P_EXT38 | P_DATA16 | P_EVEX) 461#define OPC_VPROLVQ (0x15 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 462#define OPC_VPRORVD (0x14 | P_EXT38 | P_DATA16 | P_EVEX) 463#define OPC_VPRORVQ (0x14 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 464#define OPC_VPSHLDW (0x70 | P_EXT3A | P_DATA16 | P_VEXW | P_EVEX) 465#define OPC_VPSHLDD (0x71 | P_EXT3A | P_DATA16 | P_EVEX) 466#define OPC_VPSHLDQ (0x71 | P_EXT3A | P_DATA16 | P_VEXW | P_EVEX) 467#define OPC_VPSHLDVW (0x70 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 468#define OPC_VPSHLDVD (0x71 | P_EXT38 | P_DATA16 | P_EVEX) 469#define OPC_VPSHLDVQ (0x71 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 470#define OPC_VPSHRDVW (0x72 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 471#define OPC_VPSHRDVD (0x73 | P_EXT38 | P_DATA16 | P_EVEX) 472#define OPC_VPSHRDVQ (0x73 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 473#define OPC_VPSLLVW (0x12 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 474#define OPC_VPSLLVD (0x47 | P_EXT38 | P_DATA16) 475#define OPC_VPSLLVQ (0x47 | P_EXT38 | P_DATA16 | P_VEXW) 476#define OPC_VPSRAVW (0x11 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 477#define OPC_VPSRAVD (0x46 | P_EXT38 | P_DATA16) 478#define OPC_VPSRAVQ (0x46 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 479#define OPC_VPSRLVW (0x10 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 480#define OPC_VPSRLVD (0x45 | P_EXT38 | P_DATA16) 481#define OPC_VPSRLVQ (0x45 | P_EXT38 | P_DATA16 | P_VEXW) 482#define OPC_VPTERNLOGQ (0x25 | P_EXT3A | P_DATA16 | P_VEXW | P_EVEX) 483#define OPC_VPTESTMB (0x26 | P_EXT38 | P_DATA16 | P_EVEX) 484#define OPC_VPTESTMW (0x26 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 485#define OPC_VPTESTMD (0x27 | P_EXT38 | P_DATA16 | P_EVEX) 486#define OPC_VPTESTMQ (0x27 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 487#define OPC_VPTESTNMB (0x26 | P_EXT38 | P_SIMDF3 | P_EVEX) 488#define OPC_VPTESTNMW (0x26 | P_EXT38 | P_SIMDF3 | P_VEXW | P_EVEX) 489#define OPC_VPTESTNMD (0x27 | P_EXT38 | P_SIMDF3 | P_EVEX) 490#define OPC_VPTESTNMQ (0x27 | P_EXT38 | P_SIMDF3 | P_VEXW | P_EVEX) 491#define OPC_VZEROUPPER (0x77 | P_EXT) 492#define OPC_XCHG_ax_r32 (0x90) 493#define OPC_XCHG_EvGv (0x87) 494 495#define OPC_GRP3_Eb (0xf6) 496#define OPC_GRP3_Ev (0xf7) 497#define OPC_GRP5 (0xff) 498#define OPC_GRP14 (0x73 | P_EXT | P_DATA16) 499#define OPC_GRPBT (0xba | P_EXT) 500 501#define OPC_GRPBT_BT 4 502#define OPC_GRPBT_BTS 5 503#define OPC_GRPBT_BTR 6 504#define OPC_GRPBT_BTC 7 505 506/* Group 1 opcode extensions for 0x80-0x83. 507 These are also used as modifiers for OPC_ARITH. */ 508#define ARITH_ADD 0 509#define ARITH_OR 1 510#define ARITH_ADC 2 511#define ARITH_SBB 3 512#define ARITH_AND 4 513#define ARITH_SUB 5 514#define ARITH_XOR 6 515#define ARITH_CMP 7 516 517/* Group 2 opcode extensions for 0xc0, 0xc1, 0xd0-0xd3. */ 518#define SHIFT_ROL 0 519#define SHIFT_ROR 1 520#define SHIFT_SHL 4 521#define SHIFT_SHR 5 522#define SHIFT_SAR 7 523 524/* Group 3 opcode extensions for 0xf6, 0xf7. To be used with OPC_GRP3. */ 525#define EXT3_TESTi 0 526#define EXT3_NOT 2 527#define EXT3_NEG 3 528#define EXT3_MUL 4 529#define EXT3_IMUL 5 530#define EXT3_DIV 6 531#define EXT3_IDIV 7 532 533/* Group 5 opcode extensions for 0xff. To be used with OPC_GRP5. */ 534#define EXT5_INC_Ev 0 535#define EXT5_DEC_Ev 1 536#define EXT5_CALLN_Ev 2 537#define EXT5_JMPN_Ev 4 538 539/* Condition codes to be added to OPC_JCC_{long,short}. */ 540#define JCC_JMP (-1) 541#define JCC_JO 0x0 542#define JCC_JNO 0x1 543#define JCC_JB 0x2 544#define JCC_JAE 0x3 545#define JCC_JE 0x4 546#define JCC_JNE 0x5 547#define JCC_JBE 0x6 548#define JCC_JA 0x7 549#define JCC_JS 0x8 550#define JCC_JNS 0x9 551#define JCC_JP 0xa 552#define JCC_JNP 0xb 553#define JCC_JL 0xc 554#define JCC_JGE 0xd 555#define JCC_JLE 0xe 556#define JCC_JG 0xf 557 558static const uint8_t tcg_cond_to_jcc[] = { 559 [TCG_COND_EQ] = JCC_JE, 560 [TCG_COND_NE] = JCC_JNE, 561 [TCG_COND_LT] = JCC_JL, 562 [TCG_COND_GE] = JCC_JGE, 563 [TCG_COND_LE] = JCC_JLE, 564 [TCG_COND_GT] = JCC_JG, 565 [TCG_COND_LTU] = JCC_JB, 566 [TCG_COND_GEU] = JCC_JAE, 567 [TCG_COND_LEU] = JCC_JBE, 568 [TCG_COND_GTU] = JCC_JA, 569 [TCG_COND_TSTEQ] = JCC_JE, 570 [TCG_COND_TSTNE] = JCC_JNE, 571}; 572 573#if TCG_TARGET_REG_BITS == 64 574static void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x) 575{ 576 int rex; 577 578 if (opc & P_GS) { 579 tcg_out8(s, 0x65); 580 } 581 if (opc & P_DATA16) { 582 /* We should never be asking for both 16 and 64-bit operation. */ 583 tcg_debug_assert((opc & P_REXW) == 0); 584 tcg_out8(s, 0x66); 585 } 586 if (opc & P_SIMDF3) { 587 tcg_out8(s, 0xf3); 588 } else if (opc & P_SIMDF2) { 589 tcg_out8(s, 0xf2); 590 } 591 592 rex = 0; 593 rex |= (opc & P_REXW) ? 0x8 : 0x0; /* REX.W */ 594 rex |= (r & 8) >> 1; /* REX.R */ 595 rex |= (x & 8) >> 2; /* REX.X */ 596 rex |= (rm & 8) >> 3; /* REX.B */ 597 598 /* P_REXB_{R,RM} indicates that the given register is the low byte. 599 For %[abcd]l we need no REX prefix, but for %{si,di,bp,sp}l we do, 600 as otherwise the encoding indicates %[abcd]h. Note that the values 601 that are ORed in merely indicate that the REX byte must be present; 602 those bits get discarded in output. */ 603 rex |= opc & (r >= 4 ? P_REXB_R : 0); 604 rex |= opc & (rm >= 4 ? P_REXB_RM : 0); 605 606 if (rex) { 607 tcg_out8(s, (uint8_t)(rex | 0x40)); 608 } 609 610 if (opc & (P_EXT | P_EXT38 | P_EXT3A)) { 611 tcg_out8(s, 0x0f); 612 if (opc & P_EXT38) { 613 tcg_out8(s, 0x38); 614 } else if (opc & P_EXT3A) { 615 tcg_out8(s, 0x3a); 616 } 617 } 618 619 tcg_out8(s, opc); 620} 621#else 622static void tcg_out_opc(TCGContext *s, int opc) 623{ 624 if (opc & P_DATA16) { 625 tcg_out8(s, 0x66); 626 } 627 if (opc & P_SIMDF3) { 628 tcg_out8(s, 0xf3); 629 } else if (opc & P_SIMDF2) { 630 tcg_out8(s, 0xf2); 631 } 632 if (opc & (P_EXT | P_EXT38 | P_EXT3A)) { 633 tcg_out8(s, 0x0f); 634 if (opc & P_EXT38) { 635 tcg_out8(s, 0x38); 636 } else if (opc & P_EXT3A) { 637 tcg_out8(s, 0x3a); 638 } 639 } 640 tcg_out8(s, opc); 641} 642/* Discard the register arguments to tcg_out_opc early, so as not to penalize 643 the 32-bit compilation paths. This method works with all versions of gcc, 644 whereas relying on optimization may not be able to exclude them. */ 645#define tcg_out_opc(s, opc, r, rm, x) (tcg_out_opc)(s, opc) 646#endif 647 648static void tcg_out_modrm(TCGContext *s, int opc, int r, int rm) 649{ 650 tcg_out_opc(s, opc, r, rm, 0); 651 tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm)); 652} 653 654static void tcg_out_vex_opc(TCGContext *s, int opc, int r, int v, 655 int rm, int index) 656{ 657 int tmp; 658 659 if (opc & P_GS) { 660 tcg_out8(s, 0x65); 661 } 662 /* Use the two byte form if possible, which cannot encode 663 VEX.W, VEX.B, VEX.X, or an m-mmmm field other than P_EXT. */ 664 if ((opc & (P_EXT | P_EXT38 | P_EXT3A | P_VEXW)) == P_EXT 665 && ((rm | index) & 8) == 0) { 666 /* Two byte VEX prefix. */ 667 tcg_out8(s, 0xc5); 668 669 tmp = (r & 8 ? 0 : 0x80); /* VEX.R */ 670 } else { 671 /* Three byte VEX prefix. */ 672 tcg_out8(s, 0xc4); 673 674 /* VEX.m-mmmm */ 675 if (opc & P_EXT3A) { 676 tmp = 3; 677 } else if (opc & P_EXT38) { 678 tmp = 2; 679 } else if (opc & P_EXT) { 680 tmp = 1; 681 } else { 682 g_assert_not_reached(); 683 } 684 tmp |= (r & 8 ? 0 : 0x80); /* VEX.R */ 685 tmp |= (index & 8 ? 0 : 0x40); /* VEX.X */ 686 tmp |= (rm & 8 ? 0 : 0x20); /* VEX.B */ 687 tcg_out8(s, tmp); 688 689 tmp = (opc & P_VEXW ? 0x80 : 0); /* VEX.W */ 690 } 691 692 tmp |= (opc & P_VEXL ? 0x04 : 0); /* VEX.L */ 693 /* VEX.pp */ 694 if (opc & P_DATA16) { 695 tmp |= 1; /* 0x66 */ 696 } else if (opc & P_SIMDF3) { 697 tmp |= 2; /* 0xf3 */ 698 } else if (opc & P_SIMDF2) { 699 tmp |= 3; /* 0xf2 */ 700 } 701 tmp |= (~v & 15) << 3; /* VEX.vvvv */ 702 tcg_out8(s, tmp); 703 tcg_out8(s, opc); 704} 705 706static void tcg_out_evex_opc(TCGContext *s, int opc, int r, int v, 707 int rm, int index, int aaa, bool z) 708{ 709 /* The entire 4-byte evex prefix; with R' and V' set. */ 710 uint32_t p = 0x08041062; 711 int mm, pp; 712 713 tcg_debug_assert(have_avx512vl); 714 715 /* EVEX.mm */ 716 if (opc & P_EXT3A) { 717 mm = 3; 718 } else if (opc & P_EXT38) { 719 mm = 2; 720 } else if (opc & P_EXT) { 721 mm = 1; 722 } else { 723 g_assert_not_reached(); 724 } 725 726 /* EVEX.pp */ 727 if (opc & P_DATA16) { 728 pp = 1; /* 0x66 */ 729 } else if (opc & P_SIMDF3) { 730 pp = 2; /* 0xf3 */ 731 } else if (opc & P_SIMDF2) { 732 pp = 3; /* 0xf2 */ 733 } else { 734 pp = 0; 735 } 736 737 p = deposit32(p, 8, 2, mm); 738 p = deposit32(p, 13, 1, (rm & 8) == 0); /* EVEX.RXB.B */ 739 p = deposit32(p, 14, 1, (index & 8) == 0); /* EVEX.RXB.X */ 740 p = deposit32(p, 15, 1, (r & 8) == 0); /* EVEX.RXB.R */ 741 p = deposit32(p, 16, 2, pp); 742 p = deposit32(p, 19, 4, ~v); 743 p = deposit32(p, 23, 1, (opc & P_VEXW) != 0); 744 p = deposit32(p, 24, 3, aaa); 745 p = deposit32(p, 29, 2, (opc & P_VEXL) != 0); 746 p = deposit32(p, 31, 1, z); 747 748 tcg_out32(s, p); 749 tcg_out8(s, opc); 750} 751 752static void tcg_out_vex_modrm(TCGContext *s, int opc, int r, int v, int rm) 753{ 754 if (opc & P_EVEX) { 755 tcg_out_evex_opc(s, opc, r, v, rm, 0, 0, false); 756 } else { 757 tcg_out_vex_opc(s, opc, r, v, rm, 0); 758 } 759 tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm)); 760} 761 762static void tcg_out_vex_modrm_type(TCGContext *s, int opc, 763 int r, int v, int rm, TCGType type) 764{ 765 if (type == TCG_TYPE_V256) { 766 opc |= P_VEXL; 767 } 768 tcg_out_vex_modrm(s, opc, r, v, rm); 769} 770 771static void tcg_out_evex_modrm_type(TCGContext *s, int opc, int r, int v, 772 int rm, int aaa, bool z, TCGType type) 773{ 774 if (type == TCG_TYPE_V256) { 775 opc |= P_VEXL; 776 } 777 tcg_out_evex_opc(s, opc, r, v, rm, 0, aaa, z); 778 tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm)); 779} 780 781/* Output an opcode with a full "rm + (index<<shift) + offset" address mode. 782 We handle either RM and INDEX missing with a negative value. In 64-bit 783 mode for absolute addresses, ~RM is the size of the immediate operand 784 that will follow the instruction. */ 785 786static void tcg_out_sib_offset(TCGContext *s, int r, int rm, int index, 787 int shift, intptr_t offset) 788{ 789 int mod, len; 790 791 if (index < 0 && rm < 0) { 792 if (TCG_TARGET_REG_BITS == 64) { 793 /* Try for a rip-relative addressing mode. This has replaced 794 the 32-bit-mode absolute addressing encoding. */ 795 intptr_t pc = (intptr_t)s->code_ptr + 5 + ~rm; 796 intptr_t disp = offset - pc; 797 if (disp == (int32_t)disp) { 798 tcg_out8(s, (LOWREGMASK(r) << 3) | 5); 799 tcg_out32(s, disp); 800 return; 801 } 802 803 /* Try for an absolute address encoding. This requires the 804 use of the MODRM+SIB encoding and is therefore larger than 805 rip-relative addressing. */ 806 if (offset == (int32_t)offset) { 807 tcg_out8(s, (LOWREGMASK(r) << 3) | 4); 808 tcg_out8(s, (4 << 3) | 5); 809 tcg_out32(s, offset); 810 return; 811 } 812 813 /* ??? The memory isn't directly addressable. */ 814 g_assert_not_reached(); 815 } else { 816 /* Absolute address. */ 817 tcg_out8(s, (r << 3) | 5); 818 tcg_out32(s, offset); 819 return; 820 } 821 } 822 823 /* Find the length of the immediate addend. Note that the encoding 824 that would be used for (%ebp) indicates absolute addressing. */ 825 if (rm < 0) { 826 mod = 0, len = 4, rm = 5; 827 } else if (offset == 0 && LOWREGMASK(rm) != TCG_REG_EBP) { 828 mod = 0, len = 0; 829 } else if (offset == (int8_t)offset) { 830 mod = 0x40, len = 1; 831 } else { 832 mod = 0x80, len = 4; 833 } 834 835 /* Use a single byte MODRM format if possible. Note that the encoding 836 that would be used for %esp is the escape to the two byte form. */ 837 if (index < 0 && LOWREGMASK(rm) != TCG_REG_ESP) { 838 /* Single byte MODRM format. */ 839 tcg_out8(s, mod | (LOWREGMASK(r) << 3) | LOWREGMASK(rm)); 840 } else { 841 /* Two byte MODRM+SIB format. */ 842 843 /* Note that the encoding that would place %esp into the index 844 field indicates no index register. In 64-bit mode, the REX.X 845 bit counts, so %r12 can be used as the index. */ 846 if (index < 0) { 847 index = 4; 848 } else { 849 tcg_debug_assert(index != TCG_REG_ESP); 850 } 851 852 tcg_out8(s, mod | (LOWREGMASK(r) << 3) | 4); 853 tcg_out8(s, (shift << 6) | (LOWREGMASK(index) << 3) | LOWREGMASK(rm)); 854 } 855 856 if (len == 1) { 857 tcg_out8(s, offset); 858 } else if (len == 4) { 859 tcg_out32(s, offset); 860 } 861} 862 863static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm, 864 int index, int shift, intptr_t offset) 865{ 866 tcg_out_opc(s, opc, r, rm < 0 ? 0 : rm, index < 0 ? 0 : index); 867 tcg_out_sib_offset(s, r, rm, index, shift, offset); 868} 869 870static void tcg_out_vex_modrm_sib_offset(TCGContext *s, int opc, int r, int v, 871 int rm, int index, int shift, 872 intptr_t offset) 873{ 874 tcg_out_vex_opc(s, opc, r, v, rm < 0 ? 0 : rm, index < 0 ? 0 : index); 875 tcg_out_sib_offset(s, r, rm, index, shift, offset); 876} 877 878/* A simplification of the above with no index or shift. */ 879static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, 880 int rm, intptr_t offset) 881{ 882 tcg_out_modrm_sib_offset(s, opc, r, rm, -1, 0, offset); 883} 884 885static inline void tcg_out_vex_modrm_offset(TCGContext *s, int opc, int r, 886 int v, int rm, intptr_t offset) 887{ 888 tcg_out_vex_modrm_sib_offset(s, opc, r, v, rm, -1, 0, offset); 889} 890 891/* Output an opcode with an expected reference to the constant pool. */ 892static inline void tcg_out_modrm_pool(TCGContext *s, int opc, int r) 893{ 894 tcg_out_opc(s, opc, r, 0, 0); 895 /* Absolute for 32-bit, pc-relative for 64-bit. */ 896 tcg_out8(s, LOWREGMASK(r) << 3 | 5); 897 tcg_out32(s, 0); 898} 899 900/* Output an opcode with an expected reference to the constant pool. */ 901static inline void tcg_out_vex_modrm_pool(TCGContext *s, int opc, int r) 902{ 903 tcg_out_vex_opc(s, opc, r, 0, 0, 0); 904 /* Absolute for 32-bit, pc-relative for 64-bit. */ 905 tcg_out8(s, LOWREGMASK(r) << 3 | 5); 906 tcg_out32(s, 0); 907} 908 909/* Generate dest op= src. Uses the same ARITH_* codes as tgen_arithi. */ 910static inline void tgen_arithr(TCGContext *s, int subop, int dest, int src) 911{ 912 /* Propagate an opcode prefix, such as P_REXW. */ 913 int ext = subop & ~0x7; 914 subop &= 0x7; 915 916 tcg_out_modrm(s, OPC_ARITH_GvEv + (subop << 3) + ext, dest, src); 917} 918 919static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 920{ 921 int rexw = 0; 922 923 if (arg == ret) { 924 return true; 925 } 926 switch (type) { 927 case TCG_TYPE_I64: 928 rexw = P_REXW; 929 /* fallthru */ 930 case TCG_TYPE_I32: 931 if (ret < 16) { 932 if (arg < 16) { 933 tcg_out_modrm(s, OPC_MOVL_GvEv + rexw, ret, arg); 934 } else { 935 tcg_out_vex_modrm(s, OPC_MOVD_EyVy + rexw, arg, 0, ret); 936 } 937 } else { 938 if (arg < 16) { 939 tcg_out_vex_modrm(s, OPC_MOVD_VyEy + rexw, ret, 0, arg); 940 } else { 941 tcg_out_vex_modrm(s, OPC_MOVQ_VqWq, ret, 0, arg); 942 } 943 } 944 break; 945 946 case TCG_TYPE_V64: 947 tcg_debug_assert(ret >= 16 && arg >= 16); 948 tcg_out_vex_modrm(s, OPC_MOVQ_VqWq, ret, 0, arg); 949 break; 950 case TCG_TYPE_V128: 951 tcg_debug_assert(ret >= 16 && arg >= 16); 952 tcg_out_vex_modrm(s, OPC_MOVDQA_VxWx, ret, 0, arg); 953 break; 954 case TCG_TYPE_V256: 955 tcg_debug_assert(ret >= 16 && arg >= 16); 956 tcg_out_vex_modrm(s, OPC_MOVDQA_VxWx | P_VEXL, ret, 0, arg); 957 break; 958 959 default: 960 g_assert_not_reached(); 961 } 962 return true; 963} 964 965static const int avx2_dup_insn[4] = { 966 OPC_VPBROADCASTB, OPC_VPBROADCASTW, 967 OPC_VPBROADCASTD, OPC_VPBROADCASTQ, 968}; 969 970static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 971 TCGReg r, TCGReg a) 972{ 973 if (have_avx2) { 974 tcg_out_vex_modrm_type(s, avx2_dup_insn[vece], r, 0, a, type); 975 } else { 976 switch (vece) { 977 case MO_8: 978 /* ??? With zero in a register, use PSHUFB. */ 979 tcg_out_vex_modrm(s, OPC_PUNPCKLBW, r, a, a); 980 a = r; 981 /* FALLTHRU */ 982 case MO_16: 983 tcg_out_vex_modrm(s, OPC_PUNPCKLWD, r, a, a); 984 a = r; 985 /* FALLTHRU */ 986 case MO_32: 987 tcg_out_vex_modrm(s, OPC_PSHUFD, r, 0, a); 988 /* imm8 operand: all output lanes selected from input lane 0. */ 989 tcg_out8(s, 0); 990 break; 991 case MO_64: 992 tcg_out_vex_modrm(s, OPC_PUNPCKLQDQ, r, a, a); 993 break; 994 default: 995 g_assert_not_reached(); 996 } 997 } 998 return true; 999} 1000 1001static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 1002 TCGReg r, TCGReg base, intptr_t offset) 1003{ 1004 if (have_avx2) { 1005 int vex_l = (type == TCG_TYPE_V256 ? P_VEXL : 0); 1006 tcg_out_vex_modrm_offset(s, avx2_dup_insn[vece] + vex_l, 1007 r, 0, base, offset); 1008 } else { 1009 switch (vece) { 1010 case MO_64: 1011 tcg_out_vex_modrm_offset(s, OPC_MOVDDUP, r, 0, base, offset); 1012 break; 1013 case MO_32: 1014 tcg_out_vex_modrm_offset(s, OPC_VBROADCASTSS, r, 0, base, offset); 1015 break; 1016 case MO_16: 1017 tcg_out_vex_modrm_offset(s, OPC_VPINSRW, r, r, base, offset); 1018 tcg_out8(s, 0); /* imm8 */ 1019 tcg_out_dup_vec(s, type, vece, r, r); 1020 break; 1021 case MO_8: 1022 tcg_out_vex_modrm_offset(s, OPC_VPINSRB, r, r, base, offset); 1023 tcg_out8(s, 0); /* imm8 */ 1024 tcg_out_dup_vec(s, type, vece, r, r); 1025 break; 1026 default: 1027 g_assert_not_reached(); 1028 } 1029 } 1030 return true; 1031} 1032 1033static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 1034 TCGReg ret, int64_t arg) 1035{ 1036 int vex_l = (type == TCG_TYPE_V256 ? P_VEXL : 0); 1037 1038 if (arg == 0) { 1039 tcg_out_vex_modrm(s, OPC_PXOR, ret, ret, ret); 1040 return; 1041 } 1042 if (arg == -1) { 1043 tcg_out_vex_modrm(s, OPC_PCMPEQB + vex_l, ret, ret, ret); 1044 return; 1045 } 1046 1047 if (TCG_TARGET_REG_BITS == 32 && vece < MO_64) { 1048 if (have_avx2) { 1049 tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTD + vex_l, ret); 1050 } else { 1051 tcg_out_vex_modrm_pool(s, OPC_VBROADCASTSS, ret); 1052 } 1053 new_pool_label(s, arg, R_386_32, s->code_ptr - 4, 0); 1054 } else { 1055 if (type == TCG_TYPE_V64) { 1056 tcg_out_vex_modrm_pool(s, OPC_MOVQ_VqWq, ret); 1057 } else if (have_avx2) { 1058 tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTQ + vex_l, ret); 1059 } else { 1060 tcg_out_vex_modrm_pool(s, OPC_MOVDDUP, ret); 1061 } 1062 if (TCG_TARGET_REG_BITS == 64) { 1063 new_pool_label(s, arg, R_386_PC32, s->code_ptr - 4, -4); 1064 } else { 1065 new_pool_l2(s, R_386_32, s->code_ptr - 4, 0, arg, arg >> 32); 1066 } 1067 } 1068} 1069 1070static void tcg_out_movi_vec(TCGContext *s, TCGType type, 1071 TCGReg ret, tcg_target_long arg) 1072{ 1073 if (arg == 0) { 1074 tcg_out_vex_modrm(s, OPC_PXOR, ret, ret, ret); 1075 return; 1076 } 1077 if (arg == -1) { 1078 tcg_out_vex_modrm(s, OPC_PCMPEQB, ret, ret, ret); 1079 return; 1080 } 1081 1082 int rexw = (type == TCG_TYPE_I32 ? 0 : P_REXW); 1083 tcg_out_vex_modrm_pool(s, OPC_MOVD_VyEy + rexw, ret); 1084 if (TCG_TARGET_REG_BITS == 64) { 1085 new_pool_label(s, arg, R_386_PC32, s->code_ptr - 4, -4); 1086 } else { 1087 new_pool_label(s, arg, R_386_32, s->code_ptr - 4, 0); 1088 } 1089} 1090 1091static void tcg_out_movi_int(TCGContext *s, TCGType type, 1092 TCGReg ret, tcg_target_long arg) 1093{ 1094 tcg_target_long diff; 1095 1096 if (arg == 0 && !s->carry_live) { 1097 tgen_arithr(s, ARITH_XOR, ret, ret); 1098 return; 1099 } 1100 if (arg == (uint32_t)arg || type == TCG_TYPE_I32) { 1101 tcg_out_opc(s, OPC_MOVL_Iv + LOWREGMASK(ret), 0, ret, 0); 1102 tcg_out32(s, arg); 1103 return; 1104 } 1105 if (arg == (int32_t)arg) { 1106 tcg_out_modrm(s, OPC_MOVL_EvIz + P_REXW, 0, ret); 1107 tcg_out32(s, arg); 1108 return; 1109 } 1110 1111 /* Try a 7 byte pc-relative lea before the 10 byte movq. */ 1112 diff = tcg_pcrel_diff(s, (const void *)arg) - 7; 1113 if (diff == (int32_t)diff) { 1114 tcg_out_opc(s, OPC_LEA | P_REXW, ret, 0, 0); 1115 tcg_out8(s, (LOWREGMASK(ret) << 3) | 5); 1116 tcg_out32(s, diff); 1117 return; 1118 } 1119 1120 tcg_out_opc(s, OPC_MOVL_Iv + P_REXW + LOWREGMASK(ret), 0, ret, 0); 1121 tcg_out64(s, arg); 1122} 1123 1124static void tcg_out_movi(TCGContext *s, TCGType type, 1125 TCGReg ret, tcg_target_long arg) 1126{ 1127 switch (type) { 1128 case TCG_TYPE_I32: 1129#if TCG_TARGET_REG_BITS == 64 1130 case TCG_TYPE_I64: 1131#endif 1132 if (ret < 16) { 1133 tcg_out_movi_int(s, type, ret, arg); 1134 } else { 1135 tcg_out_movi_vec(s, type, ret, arg); 1136 } 1137 break; 1138 default: 1139 g_assert_not_reached(); 1140 } 1141} 1142 1143static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 1144{ 1145 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 1146 tcg_out_modrm(s, OPC_XCHG_EvGv + rexw, r1, r2); 1147 return true; 1148} 1149 1150static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 1151 tcg_target_long imm) 1152{ 1153 /* This function is only used for passing structs by reference. */ 1154 tcg_debug_assert(imm == (int32_t)imm); 1155 tcg_out_modrm_offset(s, OPC_LEA | P_REXW, rd, rs, imm); 1156} 1157 1158static inline void tcg_out_pushi(TCGContext *s, tcg_target_long val) 1159{ 1160 if (val == (int8_t)val) { 1161 tcg_out_opc(s, OPC_PUSH_Ib, 0, 0, 0); 1162 tcg_out8(s, val); 1163 } else if (val == (int32_t)val) { 1164 tcg_out_opc(s, OPC_PUSH_Iv, 0, 0, 0); 1165 tcg_out32(s, val); 1166 } else { 1167 g_assert_not_reached(); 1168 } 1169} 1170 1171static inline void tcg_out_mb(TCGContext *s, TCGArg a0) 1172{ 1173 /* Given the strength of x86 memory ordering, we only need care for 1174 store-load ordering. Experimentally, "lock orl $0,0(%esp)" is 1175 faster than "mfence", so don't bother with the sse insn. */ 1176 if (a0 & TCG_MO_ST_LD) { 1177 tcg_out8(s, 0xf0); 1178 tcg_out_modrm_offset(s, OPC_ARITH_EvIb, ARITH_OR, TCG_REG_ESP, 0); 1179 tcg_out8(s, 0); 1180 } 1181} 1182 1183static inline void tcg_out_push(TCGContext *s, int reg) 1184{ 1185 tcg_out_opc(s, OPC_PUSH_r32 + LOWREGMASK(reg), 0, reg, 0); 1186} 1187 1188static inline void tcg_out_pop(TCGContext *s, int reg) 1189{ 1190 tcg_out_opc(s, OPC_POP_r32 + LOWREGMASK(reg), 0, reg, 0); 1191} 1192 1193static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, 1194 TCGReg arg1, intptr_t arg2) 1195{ 1196 switch (type) { 1197 case TCG_TYPE_I32: 1198 if (ret < 16) { 1199 tcg_out_modrm_offset(s, OPC_MOVL_GvEv, ret, arg1, arg2); 1200 } else { 1201 tcg_out_vex_modrm_offset(s, OPC_MOVD_VyEy, ret, 0, arg1, arg2); 1202 } 1203 break; 1204 case TCG_TYPE_I64: 1205 if (ret < 16) { 1206 tcg_out_modrm_offset(s, OPC_MOVL_GvEv | P_REXW, ret, arg1, arg2); 1207 break; 1208 } 1209 /* FALLTHRU */ 1210 case TCG_TYPE_V64: 1211 /* There is no instruction that can validate 8-byte alignment. */ 1212 tcg_debug_assert(ret >= 16); 1213 tcg_out_vex_modrm_offset(s, OPC_MOVQ_VqWq, ret, 0, arg1, arg2); 1214 break; 1215 case TCG_TYPE_V128: 1216 /* 1217 * The gvec infrastructure is asserts that v128 vector loads 1218 * and stores use a 16-byte aligned offset. Validate that the 1219 * final pointer is aligned by using an insn that will SIGSEGV. 1220 */ 1221 tcg_debug_assert(ret >= 16); 1222 tcg_out_vex_modrm_offset(s, OPC_MOVDQA_VxWx, ret, 0, arg1, arg2); 1223 break; 1224 case TCG_TYPE_V256: 1225 /* 1226 * The gvec infrastructure only requires 16-byte alignment, 1227 * so here we must use an unaligned load. 1228 */ 1229 tcg_debug_assert(ret >= 16); 1230 tcg_out_vex_modrm_offset(s, OPC_MOVDQU_VxWx | P_VEXL, 1231 ret, 0, arg1, arg2); 1232 break; 1233 default: 1234 g_assert_not_reached(); 1235 } 1236} 1237 1238static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 1239 TCGReg arg1, intptr_t arg2) 1240{ 1241 switch (type) { 1242 case TCG_TYPE_I32: 1243 if (arg < 16) { 1244 tcg_out_modrm_offset(s, OPC_MOVL_EvGv, arg, arg1, arg2); 1245 } else { 1246 tcg_out_vex_modrm_offset(s, OPC_MOVD_EyVy, arg, 0, arg1, arg2); 1247 } 1248 break; 1249 case TCG_TYPE_I64: 1250 if (arg < 16) { 1251 tcg_out_modrm_offset(s, OPC_MOVL_EvGv | P_REXW, arg, arg1, arg2); 1252 break; 1253 } 1254 /* FALLTHRU */ 1255 case TCG_TYPE_V64: 1256 /* There is no instruction that can validate 8-byte alignment. */ 1257 tcg_debug_assert(arg >= 16); 1258 tcg_out_vex_modrm_offset(s, OPC_MOVQ_WqVq, arg, 0, arg1, arg2); 1259 break; 1260 case TCG_TYPE_V128: 1261 /* 1262 * The gvec infrastructure is asserts that v128 vector loads 1263 * and stores use a 16-byte aligned offset. Validate that the 1264 * final pointer is aligned by using an insn that will SIGSEGV. 1265 * 1266 * This specific instance is also used by TCG_CALL_RET_BY_VEC, 1267 * for _WIN64, which must have SSE2 but may not have AVX. 1268 */ 1269 tcg_debug_assert(arg >= 16); 1270 if (have_avx1) { 1271 tcg_out_vex_modrm_offset(s, OPC_MOVDQA_WxVx, arg, 0, arg1, arg2); 1272 } else { 1273 tcg_out_modrm_offset(s, OPC_MOVDQA_WxVx, arg, arg1, arg2); 1274 } 1275 break; 1276 case TCG_TYPE_V256: 1277 /* 1278 * The gvec infrastructure only requires 16-byte alignment, 1279 * so here we must use an unaligned store. 1280 */ 1281 tcg_debug_assert(arg >= 16); 1282 tcg_out_vex_modrm_offset(s, OPC_MOVDQU_WxVx | P_VEXL, 1283 arg, 0, arg1, arg2); 1284 break; 1285 default: 1286 g_assert_not_reached(); 1287 } 1288} 1289 1290static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 1291 TCGReg base, intptr_t ofs) 1292{ 1293 int rexw = 0; 1294 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64) { 1295 if (val != (int32_t)val) { 1296 return false; 1297 } 1298 rexw = P_REXW; 1299 } else if (type != TCG_TYPE_I32) { 1300 return false; 1301 } 1302 tcg_out_modrm_offset(s, OPC_MOVL_EvIz | rexw, 0, base, ofs); 1303 tcg_out32(s, val); 1304 return true; 1305} 1306 1307static void tcg_out_shifti(TCGContext *s, int subopc, int reg, int count) 1308{ 1309 /* Propagate an opcode prefix, such as P_DATA16. */ 1310 int ext = subopc & ~0x7; 1311 subopc &= 0x7; 1312 1313 if (count == 1) { 1314 tcg_out_modrm(s, OPC_SHIFT_1 + ext, subopc, reg); 1315 } else { 1316 tcg_out_modrm(s, OPC_SHIFT_Ib + ext, subopc, reg); 1317 tcg_out8(s, count); 1318 } 1319} 1320 1321static inline void tcg_out_bswap32(TCGContext *s, int reg) 1322{ 1323 tcg_out_opc(s, OPC_BSWAP + LOWREGMASK(reg), 0, reg, 0); 1324} 1325 1326static inline void tcg_out_rolw_8(TCGContext *s, int reg) 1327{ 1328 tcg_out_shifti(s, SHIFT_ROL + P_DATA16, reg, 8); 1329} 1330 1331static void tcg_out_ext8u(TCGContext *s, TCGReg dest, TCGReg src) 1332{ 1333 if (TCG_TARGET_REG_BITS == 32 && src >= 4) { 1334 tcg_out_mov(s, TCG_TYPE_I32, dest, src); 1335 if (dest >= 4) { 1336 tcg_out_modrm(s, OPC_ARITH_EvIz, ARITH_AND, dest); 1337 tcg_out32(s, 0xff); 1338 return; 1339 } 1340 src = dest; 1341 } 1342 tcg_out_modrm(s, OPC_MOVZBL + P_REXB_RM, dest, src); 1343} 1344 1345static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) 1346{ 1347 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 1348 1349 if (TCG_TARGET_REG_BITS == 32 && src >= 4) { 1350 tcg_out_mov(s, TCG_TYPE_I32, dest, src); 1351 if (dest >= 4) { 1352 tcg_out_shifti(s, SHIFT_SHL, dest, 24); 1353 tcg_out_shifti(s, SHIFT_SAR, dest, 24); 1354 return; 1355 } 1356 src = dest; 1357 } 1358 tcg_out_modrm(s, OPC_MOVSBL + P_REXB_RM + rexw, dest, src); 1359} 1360 1361static void tcg_out_ext16u(TCGContext *s, TCGReg dest, TCGReg src) 1362{ 1363 /* movzwl */ 1364 tcg_out_modrm(s, OPC_MOVZWL, dest, src); 1365} 1366 1367static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) 1368{ 1369 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 1370 /* movsw[lq] */ 1371 tcg_out_modrm(s, OPC_MOVSWL + rexw, dest, src); 1372} 1373 1374static void tcg_out_ext32u(TCGContext *s, TCGReg dest, TCGReg src) 1375{ 1376 /* 32-bit mov zero extends. */ 1377 tcg_out_modrm(s, OPC_MOVL_GvEv, dest, src); 1378} 1379 1380static void tcg_out_ext32s(TCGContext *s, TCGReg dest, TCGReg src) 1381{ 1382 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 1383 tcg_out_modrm(s, OPC_MOVSLQ, dest, src); 1384} 1385 1386static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg dest, TCGReg src) 1387{ 1388 tcg_out_ext32s(s, dest, src); 1389} 1390 1391static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg dest, TCGReg src) 1392{ 1393 if (dest != src) { 1394 tcg_out_ext32u(s, dest, src); 1395 } 1396} 1397 1398static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg dest, TCGReg src) 1399{ 1400 tcg_out_ext32u(s, dest, src); 1401} 1402 1403static inline void tcg_out_bswap64(TCGContext *s, int reg) 1404{ 1405 tcg_out_opc(s, OPC_BSWAP + P_REXW + LOWREGMASK(reg), 0, reg, 0); 1406} 1407 1408static void tgen_arithi(TCGContext *s, int c, int r0, 1409 tcg_target_long val, int cf) 1410{ 1411 int rexw = 0; 1412 1413 if (TCG_TARGET_REG_BITS == 64) { 1414 rexw = c & -8; 1415 c &= 7; 1416 } 1417 1418 switch (c) { 1419 case ARITH_ADD: 1420 case ARITH_SUB: 1421 if (!cf) { 1422 /* 1423 * ??? While INC is 2 bytes shorter than ADDL $1, they also induce 1424 * partial flags update stalls on Pentium4 and are not recommended 1425 * by current Intel optimization manuals. 1426 */ 1427 if (val == 1 || val == -1) { 1428 int is_inc = (c == ARITH_ADD) ^ (val < 0); 1429 if (TCG_TARGET_REG_BITS == 64) { 1430 /* 1431 * The single-byte increment encodings are re-tasked 1432 * as the REX prefixes. Use the MODRM encoding. 1433 */ 1434 tcg_out_modrm(s, OPC_GRP5 + rexw, 1435 (is_inc ? EXT5_INC_Ev : EXT5_DEC_Ev), r0); 1436 } else { 1437 tcg_out8(s, (is_inc ? OPC_INC_r32 : OPC_DEC_r32) + r0); 1438 } 1439 return; 1440 } 1441 if (val == 128) { 1442 /* 1443 * Facilitate using an 8-bit immediate. Carry is inverted 1444 * by this transformation, so do it only if cf == 0. 1445 */ 1446 c ^= ARITH_ADD ^ ARITH_SUB; 1447 val = -128; 1448 } 1449 } 1450 break; 1451 1452 case ARITH_AND: 1453 if (TCG_TARGET_REG_BITS == 64) { 1454 if (val == 0xffffffffu) { 1455 tcg_out_ext32u(s, r0, r0); 1456 return; 1457 } 1458 if (val == (uint32_t)val) { 1459 /* AND with no high bits set can use a 32-bit operation. */ 1460 rexw = 0; 1461 } 1462 } 1463 if (val == 0xffu && (r0 < 4 || TCG_TARGET_REG_BITS == 64)) { 1464 tcg_out_ext8u(s, r0, r0); 1465 return; 1466 } 1467 if (val == 0xffffu) { 1468 tcg_out_ext16u(s, r0, r0); 1469 return; 1470 } 1471 break; 1472 1473 case ARITH_OR: 1474 case ARITH_XOR: 1475 if (val >= 0x80 && val <= 0xff 1476 && (r0 < 4 || TCG_TARGET_REG_BITS == 64)) { 1477 tcg_out_modrm(s, OPC_ARITH_EbIb + P_REXB_RM, c, r0); 1478 tcg_out8(s, val); 1479 return; 1480 } 1481 break; 1482 } 1483 1484 if (val == (int8_t)val) { 1485 tcg_out_modrm(s, OPC_ARITH_EvIb + rexw, c, r0); 1486 tcg_out8(s, val); 1487 return; 1488 } 1489 if (rexw == 0 || val == (int32_t)val) { 1490 tcg_out_modrm(s, OPC_ARITH_EvIz + rexw, c, r0); 1491 tcg_out32(s, val); 1492 return; 1493 } 1494 1495 g_assert_not_reached(); 1496} 1497 1498static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val) 1499{ 1500 if (val != 0) { 1501 tgen_arithi(s, ARITH_ADD + P_REXW, reg, val, 0); 1502 } 1503} 1504 1505/* Set SMALL to force a short forward branch. */ 1506static void tcg_out_jxx(TCGContext *s, int opc, TCGLabel *l, bool small) 1507{ 1508 int32_t val, val1; 1509 1510 if (l->has_value) { 1511 val = tcg_pcrel_diff(s, l->u.value_ptr); 1512 val1 = val - 2; 1513 if ((int8_t)val1 == val1) { 1514 if (opc == -1) { 1515 tcg_out8(s, OPC_JMP_short); 1516 } else { 1517 tcg_out8(s, OPC_JCC_short + opc); 1518 } 1519 tcg_out8(s, val1); 1520 } else { 1521 tcg_debug_assert(!small); 1522 if (opc == -1) { 1523 tcg_out8(s, OPC_JMP_long); 1524 tcg_out32(s, val - 5); 1525 } else { 1526 tcg_out_opc(s, OPC_JCC_long + opc, 0, 0, 0); 1527 tcg_out32(s, val - 6); 1528 } 1529 } 1530 } else if (small) { 1531 if (opc == -1) { 1532 tcg_out8(s, OPC_JMP_short); 1533 } else { 1534 tcg_out8(s, OPC_JCC_short + opc); 1535 } 1536 tcg_out_reloc(s, s->code_ptr, R_386_PC8, l, -1); 1537 s->code_ptr += 1; 1538 } else { 1539 if (opc == -1) { 1540 tcg_out8(s, OPC_JMP_long); 1541 } else { 1542 tcg_out_opc(s, OPC_JCC_long + opc, 0, 0, 0); 1543 } 1544 tcg_out_reloc(s, s->code_ptr, R_386_PC32, l, -4); 1545 s->code_ptr += 4; 1546 } 1547} 1548 1549static int tcg_out_cmp(TCGContext *s, TCGCond cond, TCGArg arg1, 1550 TCGArg arg2, int const_arg2, int rexw) 1551{ 1552 int jz, js; 1553 1554 if (!is_tst_cond(cond)) { 1555 if (!const_arg2) { 1556 tgen_arithr(s, ARITH_CMP + rexw, arg1, arg2); 1557 } else if (arg2 == 0) { 1558 tcg_out_modrm(s, OPC_TESTL + rexw, arg1, arg1); 1559 } else { 1560 tcg_debug_assert(!rexw || arg2 == (int32_t)arg2); 1561 tgen_arithi(s, ARITH_CMP + rexw, arg1, arg2, 0); 1562 } 1563 return tcg_cond_to_jcc[cond]; 1564 } 1565 1566 jz = tcg_cond_to_jcc[cond]; 1567 js = (cond == TCG_COND_TSTNE ? JCC_JS : JCC_JNS); 1568 1569 if (!const_arg2) { 1570 tcg_out_modrm(s, OPC_TESTL + rexw, arg1, arg2); 1571 return jz; 1572 } 1573 1574 if (arg2 <= 0xff && (TCG_TARGET_REG_BITS == 64 || arg1 < 4)) { 1575 if (arg2 == 0x80) { 1576 tcg_out_modrm(s, OPC_TESTB | P_REXB_R, arg1, arg1); 1577 return js; 1578 } 1579 if (arg2 == 0xff) { 1580 tcg_out_modrm(s, OPC_TESTB | P_REXB_R, arg1, arg1); 1581 return jz; 1582 } 1583 tcg_out_modrm(s, OPC_GRP3_Eb | P_REXB_RM, EXT3_TESTi, arg1); 1584 tcg_out8(s, arg2); 1585 return jz; 1586 } 1587 1588 if ((arg2 & ~0xff00) == 0 && arg1 < 4) { 1589 if (arg2 == 0x8000) { 1590 tcg_out_modrm(s, OPC_TESTB, arg1 + 4, arg1 + 4); 1591 return js; 1592 } 1593 if (arg2 == 0xff00) { 1594 tcg_out_modrm(s, OPC_TESTB, arg1 + 4, arg1 + 4); 1595 return jz; 1596 } 1597 tcg_out_modrm(s, OPC_GRP3_Eb, EXT3_TESTi, arg1 + 4); 1598 tcg_out8(s, arg2 >> 8); 1599 return jz; 1600 } 1601 1602 if (arg2 == 0xffff) { 1603 tcg_out_modrm(s, OPC_TESTL | P_DATA16, arg1, arg1); 1604 return jz; 1605 } 1606 if (arg2 == 0xffffffffu) { 1607 tcg_out_modrm(s, OPC_TESTL, arg1, arg1); 1608 return jz; 1609 } 1610 1611 if (is_power_of_2(rexw ? arg2 : (uint32_t)arg2)) { 1612 int jc = (cond == TCG_COND_TSTNE ? JCC_JB : JCC_JAE); 1613 int sh = ctz64(arg2); 1614 1615 rexw = (sh & 32 ? P_REXW : 0); 1616 if ((sh & 31) == 31) { 1617 tcg_out_modrm(s, OPC_TESTL | rexw, arg1, arg1); 1618 return js; 1619 } else { 1620 tcg_out_modrm(s, OPC_GRPBT | rexw, OPC_GRPBT_BT, arg1); 1621 tcg_out8(s, sh); 1622 return jc; 1623 } 1624 } 1625 1626 if (rexw) { 1627 if (arg2 == (uint32_t)arg2) { 1628 rexw = 0; 1629 } else { 1630 tcg_debug_assert(arg2 == (int32_t)arg2); 1631 } 1632 } 1633 tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_TESTi, arg1); 1634 tcg_out32(s, arg2); 1635 return jz; 1636} 1637 1638static void tcg_out_brcond(TCGContext *s, int rexw, TCGCond cond, 1639 TCGArg arg1, TCGArg arg2, int const_arg2, 1640 TCGLabel *label, bool small) 1641{ 1642 int jcc = tcg_out_cmp(s, cond, arg1, arg2, const_arg2, rexw); 1643 tcg_out_jxx(s, jcc, label, small); 1644} 1645 1646static void tgen_brcond(TCGContext *s, TCGType type, TCGCond cond, 1647 TCGReg arg1, TCGReg arg2, TCGLabel *label) 1648{ 1649 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 1650 tcg_out_brcond(s, rexw, cond, arg1, arg2, false, label, false); 1651} 1652 1653static void tgen_brcondi(TCGContext *s, TCGType type, TCGCond cond, 1654 TCGReg arg1, tcg_target_long arg2, TCGLabel *label) 1655{ 1656 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 1657 tcg_out_brcond(s, rexw, cond, arg1, arg2, true, label, false); 1658} 1659 1660static const TCGOutOpBrcond outop_brcond = { 1661 .base.static_constraint = C_O0_I2(r, reT), 1662 .out_rr = tgen_brcond, 1663 .out_ri = tgen_brcondi, 1664}; 1665 1666static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, 1667 TCGReg ah, TCGArg bl, bool blconst, 1668 TCGArg bh, bool bhconst, 1669 TCGLabel *label_this, bool small) 1670{ 1671 TCGLabel *label_next = gen_new_label(); 1672 1673 switch (cond) { 1674 case TCG_COND_EQ: 1675 case TCG_COND_TSTEQ: 1676 tcg_out_brcond(s, 0, tcg_invert_cond(cond), 1677 al, bl, blconst, label_next, true); 1678 tcg_out_brcond(s, 0, cond, ah, bh, bhconst, label_this, small); 1679 break; 1680 1681 case TCG_COND_NE: 1682 case TCG_COND_TSTNE: 1683 tcg_out_brcond(s, 0, cond, al, bl, blconst, label_this, small); 1684 tcg_out_brcond(s, 0, cond, ah, bh, bhconst, label_this, small); 1685 break; 1686 1687 default: 1688 tcg_out_brcond(s, 0, tcg_high_cond(cond), 1689 ah, bh, bhconst, label_this, small); 1690 tcg_out_jxx(s, JCC_JNE, label_next, 1); 1691 tcg_out_brcond(s, 0, tcg_unsigned_cond(cond), 1692 al, bl, blconst, label_this, small); 1693 break; 1694 } 1695 tcg_out_label(s, label_next); 1696} 1697 1698static void tgen_brcond2(TCGContext *s, TCGCond cond, TCGReg al, 1699 TCGReg ah, TCGArg bl, bool blconst, 1700 TCGArg bh, bool bhconst, TCGLabel *l) 1701{ 1702 tcg_out_brcond2(s, cond, al, ah, bl, blconst, bh, bhconst, l, false); 1703} 1704 1705#if TCG_TARGET_REG_BITS != 32 1706__attribute__((unused)) 1707#endif 1708static const TCGOutOpBrcond2 outop_brcond2 = { 1709 .base.static_constraint = C_O0_I4(r, r, ri, ri), 1710 .out = tgen_brcond2, 1711}; 1712 1713static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond, 1714 TCGReg dest, TCGReg arg1, TCGArg arg2, 1715 bool const_arg2, bool neg) 1716{ 1717 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 1718 int cmp_rexw = rexw; 1719 bool inv = false; 1720 bool cleared; 1721 int jcc; 1722 1723 switch (cond) { 1724 case TCG_COND_NE: 1725 inv = true; 1726 /* fall through */ 1727 case TCG_COND_EQ: 1728 /* If arg2 is 0, convert to LTU/GEU vs 1. */ 1729 if (const_arg2 && arg2 == 0) { 1730 arg2 = 1; 1731 goto do_ltu; 1732 } 1733 break; 1734 1735 case TCG_COND_TSTNE: 1736 inv = true; 1737 /* fall through */ 1738 case TCG_COND_TSTEQ: 1739 /* If arg2 is -1, convert to LTU/GEU vs 1. */ 1740 if (const_arg2 && arg2 == 0xffffffffu) { 1741 arg2 = 1; 1742 cmp_rexw = 0; 1743 goto do_ltu; 1744 } 1745 break; 1746 1747 case TCG_COND_LEU: 1748 inv = true; 1749 /* fall through */ 1750 case TCG_COND_GTU: 1751 /* If arg2 is a register, swap for LTU/GEU. */ 1752 if (!const_arg2) { 1753 TCGReg t = arg1; 1754 arg1 = arg2; 1755 arg2 = t; 1756 goto do_ltu; 1757 } 1758 break; 1759 1760 case TCG_COND_GEU: 1761 inv = true; 1762 /* fall through */ 1763 case TCG_COND_LTU: 1764 do_ltu: 1765 /* 1766 * Relying on the carry bit, use SBB to produce -1 if LTU, 0 if GEU. 1767 * We can then use NEG or INC to produce the desired result. 1768 * This is always smaller than the SETCC expansion. 1769 */ 1770 tcg_out_cmp(s, TCG_COND_LTU, arg1, arg2, const_arg2, cmp_rexw); 1771 1772 /* X - X - C = -C = (C ? -1 : 0) */ 1773 tgen_arithr(s, ARITH_SBB + (neg ? rexw : 0), dest, dest); 1774 if (inv && neg) { 1775 /* ~(C ? -1 : 0) = (C ? 0 : -1) */ 1776 tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NOT, dest); 1777 } else if (inv) { 1778 /* (C ? -1 : 0) + 1 = (C ? 0 : 1) */ 1779 tgen_arithi(s, ARITH_ADD, dest, 1, 0); 1780 } else if (!neg) { 1781 /* -(C ? -1 : 0) = (C ? 1 : 0) */ 1782 tcg_out_modrm(s, OPC_GRP3_Ev, EXT3_NEG, dest); 1783 } 1784 return; 1785 1786 case TCG_COND_GE: 1787 inv = true; 1788 /* fall through */ 1789 case TCG_COND_LT: 1790 /* If arg2 is 0, extract the sign bit. */ 1791 if (const_arg2 && arg2 == 0) { 1792 tcg_out_mov(s, type, dest, arg1); 1793 if (inv) { 1794 tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NOT, dest); 1795 } 1796 tcg_out_shifti(s, (neg ? SHIFT_SAR : SHIFT_SHR) + rexw, 1797 dest, rexw ? 63 : 31); 1798 return; 1799 } 1800 break; 1801 1802 default: 1803 break; 1804 } 1805 1806 /* 1807 * If dest does not overlap the inputs, clearing it first is preferred. 1808 * The XOR breaks any false dependency for the low-byte write to dest, 1809 * and is also one byte smaller than MOVZBL. 1810 */ 1811 cleared = false; 1812 if (dest != arg1 && (const_arg2 || dest != arg2)) { 1813 tgen_arithr(s, ARITH_XOR, dest, dest); 1814 cleared = true; 1815 } 1816 1817 jcc = tcg_out_cmp(s, cond, arg1, arg2, const_arg2, cmp_rexw); 1818 tcg_out_modrm(s, OPC_SETCC | jcc, 0, dest); 1819 1820 if (!cleared) { 1821 tcg_out_ext8u(s, dest, dest); 1822 } 1823 if (neg) { 1824 tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NEG, dest); 1825 } 1826} 1827 1828static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, 1829 TCGReg dest, TCGReg arg1, TCGReg arg2) 1830{ 1831 tcg_out_setcond(s, type, cond, dest, arg1, arg2, false, false); 1832} 1833 1834static void tgen_setcondi(TCGContext *s, TCGType type, TCGCond cond, 1835 TCGReg dest, TCGReg arg1, tcg_target_long arg2) 1836{ 1837 tcg_out_setcond(s, type, cond, dest, arg1, arg2, true, false); 1838} 1839 1840static const TCGOutOpSetcond outop_setcond = { 1841 .base.static_constraint = C_O1_I2(q, r, reT), 1842 .out_rrr = tgen_setcond, 1843 .out_rri = tgen_setcondi, 1844}; 1845 1846static void tgen_negsetcond(TCGContext *s, TCGType type, TCGCond cond, 1847 TCGReg dest, TCGReg arg1, TCGReg arg2) 1848{ 1849 tcg_out_setcond(s, type, cond, dest, arg1, arg2, false, true); 1850} 1851 1852static void tgen_negsetcondi(TCGContext *s, TCGType type, TCGCond cond, 1853 TCGReg dest, TCGReg arg1, tcg_target_long arg2) 1854{ 1855 tcg_out_setcond(s, type, cond, dest, arg1, arg2, true, true); 1856} 1857 1858static const TCGOutOpSetcond outop_negsetcond = { 1859 .base.static_constraint = C_O1_I2(q, r, reT), 1860 .out_rrr = tgen_negsetcond, 1861 .out_rri = tgen_negsetcondi, 1862}; 1863 1864static void tgen_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, 1865 TCGReg al, TCGReg ah, 1866 TCGArg bl, bool const_bl, 1867 TCGArg bh, bool const_bh) 1868{ 1869 TCGLabel *label_over = gen_new_label(); 1870 1871 if (ret == al || ret == ah 1872 || (!const_bl && ret == bl) 1873 || (!const_bh && ret == bh)) { 1874 /* 1875 * When the destination overlaps with one of the argument 1876 * registers, don't do anything tricky. 1877 */ 1878 TCGLabel *label_true = gen_new_label(); 1879 1880 tcg_out_brcond2(s, cond, al, ah, bl, const_bl, 1881 bh, const_bh, label_true, true); 1882 1883 tcg_out_movi(s, TCG_TYPE_I32, ret, 0); 1884 tcg_out_jxx(s, JCC_JMP, label_over, 1); 1885 tcg_out_label(s, label_true); 1886 1887 tcg_out_movi(s, TCG_TYPE_I32, ret, 1); 1888 } else { 1889 /* 1890 * When the destination does not overlap one of the arguments, 1891 * clear the destination first, jump if cond false, and emit an 1892 * increment in the true case. This results in smaller code. 1893 */ 1894 tcg_out_movi(s, TCG_TYPE_I32, ret, 0); 1895 1896 tcg_out_brcond2(s, tcg_invert_cond(cond), al, ah, bl, const_bl, 1897 bh, const_bh, label_over, true); 1898 1899 tgen_arithi(s, ARITH_ADD, ret, 1, 0); 1900 } 1901 tcg_out_label(s, label_over); 1902} 1903 1904#if TCG_TARGET_REG_BITS != 32 1905__attribute__((unused)) 1906#endif 1907static const TCGOutOpSetcond2 outop_setcond2 = { 1908 .base.static_constraint = C_O1_I4(r, r, r, ri, ri), 1909 .out = tgen_setcond2, 1910}; 1911 1912static void tcg_out_cmov(TCGContext *s, int jcc, int rexw, 1913 TCGReg dest, TCGReg v1) 1914{ 1915 tcg_out_modrm(s, OPC_CMOVCC | jcc | rexw, dest, v1); 1916} 1917 1918static void tgen_movcond(TCGContext *s, TCGType type, TCGCond cond, 1919 TCGReg dest, TCGReg c1, TCGArg c2, bool const_c2, 1920 TCGArg vt, bool const_vt, 1921 TCGArg vf, bool consf_vf) 1922{ 1923 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 1924 int jcc = tcg_out_cmp(s, cond, c1, c2, const_c2, rexw); 1925 tcg_out_cmov(s, jcc, rexw, dest, vt); 1926} 1927 1928static const TCGOutOpMovcond outop_movcond = { 1929 .base.static_constraint = C_O1_I4(r, r, reT, r, 0), 1930 .out = tgen_movcond, 1931}; 1932 1933static void tcg_out_branch(TCGContext *s, int call, const tcg_insn_unit *dest) 1934{ 1935 intptr_t disp = tcg_pcrel_diff(s, dest) - 5; 1936 1937 if (disp == (int32_t)disp) { 1938 tcg_out_opc(s, call ? OPC_CALL_Jz : OPC_JMP_long, 0, 0, 0); 1939 tcg_out32(s, disp); 1940 } else { 1941 /* rip-relative addressing into the constant pool. 1942 This is 6 + 8 = 14 bytes, as compared to using an 1943 immediate load 10 + 6 = 16 bytes, plus we may 1944 be able to re-use the pool constant for more calls. */ 1945 tcg_out_opc(s, OPC_GRP5, 0, 0, 0); 1946 tcg_out8(s, (call ? EXT5_CALLN_Ev : EXT5_JMPN_Ev) << 3 | 5); 1947 new_pool_label(s, (uintptr_t)dest, R_386_PC32, s->code_ptr, -4); 1948 tcg_out32(s, 0); 1949 } 1950} 1951 1952static void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest, 1953 const TCGHelperInfo *info) 1954{ 1955 tcg_out_branch(s, 1, dest); 1956 1957#ifndef _WIN32 1958 if (TCG_TARGET_REG_BITS == 32 && info->out_kind == TCG_CALL_RET_BY_REF) { 1959 /* 1960 * The sysv i386 abi for struct return places a reference as the 1961 * first argument of the stack, and pops that argument with the 1962 * return statement. Since we want to retain the aligned stack 1963 * pointer for the callee, we do not want to actually push that 1964 * argument before the call but rely on the normal store to the 1965 * stack slot. But we do need to compensate for the pop in order 1966 * to reset our correct stack pointer value. 1967 * Pushing a garbage value back onto the stack is quickest. 1968 */ 1969 tcg_out_push(s, TCG_REG_EAX); 1970 } 1971#endif 1972} 1973 1974static void tcg_out_jmp(TCGContext *s, const tcg_insn_unit *dest) 1975{ 1976 tcg_out_branch(s, 0, dest); 1977} 1978 1979static void tcg_out_nopn(TCGContext *s, int n) 1980{ 1981 int i; 1982 /* Emit 1 or 2 operand size prefixes for the standard one byte nop, 1983 * "xchg %eax,%eax", forming "xchg %ax,%ax". All cores accept the 1984 * duplicate prefix, and all of the interesting recent cores can 1985 * decode and discard the duplicates in a single cycle. 1986 */ 1987 tcg_debug_assert(n >= 1); 1988 for (i = 1; i < n; ++i) { 1989 tcg_out8(s, 0x66); 1990 } 1991 tcg_out8(s, 0x90); 1992} 1993 1994typedef struct { 1995 TCGReg base; 1996 int index; 1997 int ofs; 1998 int seg; 1999 TCGAtomAlign aa; 2000} HostAddress; 2001 2002bool tcg_target_has_memory_bswap(MemOp memop) 2003{ 2004 TCGAtomAlign aa; 2005 2006 if (!have_movbe) { 2007 return false; 2008 } 2009 if ((memop & MO_SIZE) < MO_128) { 2010 return true; 2011 } 2012 2013 /* 2014 * Reject 16-byte memop with 16-byte atomicity, i.e. VMOVDQA, 2015 * but do allow a pair of 64-bit operations, i.e. MOVBEQ. 2016 */ 2017 aa = atom_and_align_for_opc(tcg_ctx, memop, MO_ATOM_IFALIGN, true); 2018 return aa.atom < MO_128; 2019} 2020 2021/* 2022 * Because i686 has no register parameters and because x86_64 has xchg 2023 * to handle addr/data register overlap, we have placed all input arguments 2024 * before we need might need a scratch reg. 2025 * 2026 * Even then, a scratch is only needed for l->raddr. Rather than expose 2027 * a general-purpose scratch when we don't actually know it's available, 2028 * use the ra_gen hook to load into RAX if needed. 2029 */ 2030#if TCG_TARGET_REG_BITS == 64 2031static TCGReg ldst_ra_gen(TCGContext *s, const TCGLabelQemuLdst *l, int arg) 2032{ 2033 if (arg < 0) { 2034 arg = TCG_REG_RAX; 2035 } 2036 tcg_out_movi(s, TCG_TYPE_PTR, arg, (uintptr_t)l->raddr); 2037 return arg; 2038} 2039static const TCGLdstHelperParam ldst_helper_param = { 2040 .ra_gen = ldst_ra_gen 2041}; 2042#else 2043static const TCGLdstHelperParam ldst_helper_param = { }; 2044#endif 2045 2046static void tcg_out_vec_to_pair(TCGContext *s, TCGType type, 2047 TCGReg l, TCGReg h, TCGReg v) 2048{ 2049 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2050 2051 /* vpmov{d,q} %v, %l */ 2052 tcg_out_vex_modrm(s, OPC_MOVD_EyVy + rexw, v, 0, l); 2053 /* vpextr{d,q} $1, %v, %h */ 2054 tcg_out_vex_modrm(s, OPC_PEXTRD + rexw, v, 0, h); 2055 tcg_out8(s, 1); 2056} 2057 2058static void tcg_out_pair_to_vec(TCGContext *s, TCGType type, 2059 TCGReg v, TCGReg l, TCGReg h) 2060{ 2061 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2062 2063 /* vmov{d,q} %l, %v */ 2064 tcg_out_vex_modrm(s, OPC_MOVD_VyEy + rexw, v, 0, l); 2065 /* vpinsr{d,q} $1, %h, %v, %v */ 2066 tcg_out_vex_modrm(s, OPC_PINSRD + rexw, v, v, h); 2067 tcg_out8(s, 1); 2068} 2069 2070/* 2071 * Generate code for the slow path for a load at the end of block 2072 */ 2073static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 2074{ 2075 MemOp opc = get_memop(l->oi); 2076 tcg_insn_unit **label_ptr = &l->label_ptr[0]; 2077 2078 /* resolve label address */ 2079 tcg_patch32(label_ptr[0], s->code_ptr - label_ptr[0] - 4); 2080 if (label_ptr[1]) { 2081 tcg_patch32(label_ptr[1], s->code_ptr - label_ptr[1] - 4); 2082 } 2083 2084 tcg_out_ld_helper_args(s, l, &ldst_helper_param); 2085 tcg_out_branch(s, 1, qemu_ld_helpers[opc & MO_SIZE]); 2086 tcg_out_ld_helper_ret(s, l, false, &ldst_helper_param); 2087 2088 tcg_out_jmp(s, l->raddr); 2089 return true; 2090} 2091 2092/* 2093 * Generate code for the slow path for a store at the end of block 2094 */ 2095static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 2096{ 2097 MemOp opc = get_memop(l->oi); 2098 tcg_insn_unit **label_ptr = &l->label_ptr[0]; 2099 2100 /* resolve label address */ 2101 tcg_patch32(label_ptr[0], s->code_ptr - label_ptr[0] - 4); 2102 if (label_ptr[1]) { 2103 tcg_patch32(label_ptr[1], s->code_ptr - label_ptr[1] - 4); 2104 } 2105 2106 tcg_out_st_helper_args(s, l, &ldst_helper_param); 2107 tcg_out_branch(s, 1, qemu_st_helpers[opc & MO_SIZE]); 2108 2109 tcg_out_jmp(s, l->raddr); 2110 return true; 2111} 2112 2113#ifdef CONFIG_USER_ONLY 2114static HostAddress x86_guest_base = { 2115 .index = -1 2116}; 2117 2118#if defined(__x86_64__) && defined(__linux__) 2119# include <asm/prctl.h> 2120# include <sys/prctl.h> 2121int arch_prctl(int code, unsigned long addr); 2122static inline int setup_guest_base_seg(void) 2123{ 2124 if (arch_prctl(ARCH_SET_GS, guest_base) == 0) { 2125 return P_GS; 2126 } 2127 return 0; 2128} 2129#define setup_guest_base_seg setup_guest_base_seg 2130#elif defined(__x86_64__) && \ 2131 (defined (__FreeBSD__) || defined (__FreeBSD_kernel__)) 2132# include <machine/sysarch.h> 2133static inline int setup_guest_base_seg(void) 2134{ 2135 if (sysarch(AMD64_SET_GSBASE, &guest_base) == 0) { 2136 return P_GS; 2137 } 2138 return 0; 2139} 2140#define setup_guest_base_seg setup_guest_base_seg 2141#endif 2142#else 2143# define x86_guest_base (*(HostAddress *)({ qemu_build_not_reached(); NULL; })) 2144#endif /* CONFIG_USER_ONLY */ 2145#ifndef setup_guest_base_seg 2146# define setup_guest_base_seg() 0 2147#endif 2148 2149#define MIN_TLB_MASK_TABLE_OFS INT_MIN 2150 2151/* 2152 * For softmmu, perform the TLB load and compare. 2153 * For useronly, perform any required alignment tests. 2154 * In both cases, return a TCGLabelQemuLdst structure if the slow path 2155 * is required and fill in @h with the host address for the fast path. 2156 */ 2157static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 2158 TCGReg addr, MemOpIdx oi, bool is_ld) 2159{ 2160 TCGLabelQemuLdst *ldst = NULL; 2161 MemOp opc = get_memop(oi); 2162 MemOp s_bits = opc & MO_SIZE; 2163 unsigned a_mask; 2164 2165 if (tcg_use_softmmu) { 2166 h->index = TCG_REG_L0; 2167 h->ofs = 0; 2168 h->seg = 0; 2169 } else { 2170 *h = x86_guest_base; 2171 } 2172 h->base = addr; 2173 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, s_bits == MO_128); 2174 a_mask = (1 << h->aa.align) - 1; 2175 2176 if (tcg_use_softmmu) { 2177 int cmp_ofs = is_ld ? offsetof(CPUTLBEntry, addr_read) 2178 : offsetof(CPUTLBEntry, addr_write); 2179 TCGType ttype = TCG_TYPE_I32; 2180 TCGType tlbtype = TCG_TYPE_I32; 2181 int trexw = 0, hrexw = 0, tlbrexw = 0; 2182 unsigned mem_index = get_mmuidx(oi); 2183 unsigned s_mask = (1 << s_bits) - 1; 2184 int fast_ofs = tlb_mask_table_ofs(s, mem_index); 2185 int tlb_mask; 2186 2187 ldst = new_ldst_label(s); 2188 ldst->is_ld = is_ld; 2189 ldst->oi = oi; 2190 ldst->addr_reg = addr; 2191 2192 if (TCG_TARGET_REG_BITS == 64) { 2193 ttype = s->addr_type; 2194 trexw = (ttype == TCG_TYPE_I32 ? 0 : P_REXW); 2195 if (TCG_TYPE_PTR == TCG_TYPE_I64) { 2196 hrexw = P_REXW; 2197 if (s->page_bits + s->tlb_dyn_max_bits > 32) { 2198 tlbtype = TCG_TYPE_I64; 2199 tlbrexw = P_REXW; 2200 } 2201 } 2202 } 2203 2204 tcg_out_mov(s, tlbtype, TCG_REG_L0, addr); 2205 tcg_out_shifti(s, SHIFT_SHR + tlbrexw, TCG_REG_L0, 2206 s->page_bits - CPU_TLB_ENTRY_BITS); 2207 2208 tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, TCG_REG_L0, TCG_AREG0, 2209 fast_ofs + offsetof(CPUTLBDescFast, mask)); 2210 2211 tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, TCG_REG_L0, TCG_AREG0, 2212 fast_ofs + offsetof(CPUTLBDescFast, table)); 2213 2214 /* 2215 * If the required alignment is at least as large as the access, 2216 * simply copy the address and mask. For lesser alignments, 2217 * check that we don't cross pages for the complete access. 2218 */ 2219 if (a_mask >= s_mask) { 2220 tcg_out_mov(s, ttype, TCG_REG_L1, addr); 2221 } else { 2222 tcg_out_modrm_offset(s, OPC_LEA + trexw, TCG_REG_L1, 2223 addr, s_mask - a_mask); 2224 } 2225 tlb_mask = s->page_mask | a_mask; 2226 tgen_arithi(s, ARITH_AND + trexw, TCG_REG_L1, tlb_mask, 0); 2227 2228 /* cmp 0(TCG_REG_L0), TCG_REG_L1 */ 2229 tcg_out_modrm_offset(s, OPC_CMP_GvEv + trexw, 2230 TCG_REG_L1, TCG_REG_L0, cmp_ofs); 2231 2232 /* jne slow_path */ 2233 tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); 2234 ldst->label_ptr[0] = s->code_ptr; 2235 s->code_ptr += 4; 2236 2237 /* TLB Hit. */ 2238 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_L0, TCG_REG_L0, 2239 offsetof(CPUTLBEntry, addend)); 2240 } else if (a_mask) { 2241 int jcc; 2242 2243 ldst = new_ldst_label(s); 2244 ldst->is_ld = is_ld; 2245 ldst->oi = oi; 2246 ldst->addr_reg = addr; 2247 2248 /* jne slow_path */ 2249 jcc = tcg_out_cmp(s, TCG_COND_TSTNE, addr, a_mask, true, false); 2250 tcg_out_opc(s, OPC_JCC_long + jcc, 0, 0, 0); 2251 ldst->label_ptr[0] = s->code_ptr; 2252 s->code_ptr += 4; 2253 } 2254 2255 return ldst; 2256} 2257 2258static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, 2259 HostAddress h, TCGType type, MemOp memop) 2260{ 2261 bool use_movbe = false; 2262 int rexw = (type == TCG_TYPE_I32 ? 0 : P_REXW); 2263 int movop = OPC_MOVL_GvEv; 2264 2265 /* Do big-endian loads with movbe. */ 2266 if (memop & MO_BSWAP) { 2267 tcg_debug_assert(have_movbe); 2268 use_movbe = true; 2269 movop = OPC_MOVBE_GyMy; 2270 } 2271 2272 switch (memop & MO_SSIZE) { 2273 case MO_UB: 2274 tcg_out_modrm_sib_offset(s, OPC_MOVZBL + h.seg, datalo, 2275 h.base, h.index, 0, h.ofs); 2276 break; 2277 case MO_SB: 2278 tcg_out_modrm_sib_offset(s, OPC_MOVSBL + rexw + h.seg, datalo, 2279 h.base, h.index, 0, h.ofs); 2280 break; 2281 case MO_UW: 2282 if (use_movbe) { 2283 /* There is no extending movbe; only low 16-bits are modified. */ 2284 if (datalo != h.base && datalo != h.index) { 2285 /* XOR breaks dependency chains. */ 2286 tgen_arithr(s, ARITH_XOR, datalo, datalo); 2287 tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + h.seg, 2288 datalo, h.base, h.index, 0, h.ofs); 2289 } else { 2290 tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + h.seg, 2291 datalo, h.base, h.index, 0, h.ofs); 2292 tcg_out_ext16u(s, datalo, datalo); 2293 } 2294 } else { 2295 tcg_out_modrm_sib_offset(s, OPC_MOVZWL + h.seg, datalo, 2296 h.base, h.index, 0, h.ofs); 2297 } 2298 break; 2299 case MO_SW: 2300 if (use_movbe) { 2301 tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + h.seg, 2302 datalo, h.base, h.index, 0, h.ofs); 2303 tcg_out_ext16s(s, type, datalo, datalo); 2304 } else { 2305 tcg_out_modrm_sib_offset(s, OPC_MOVSWL + rexw + h.seg, 2306 datalo, h.base, h.index, 0, h.ofs); 2307 } 2308 break; 2309 case MO_UL: 2310 tcg_out_modrm_sib_offset(s, movop + h.seg, datalo, 2311 h.base, h.index, 0, h.ofs); 2312 break; 2313#if TCG_TARGET_REG_BITS == 64 2314 case MO_SL: 2315 if (use_movbe) { 2316 tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + h.seg, datalo, 2317 h.base, h.index, 0, h.ofs); 2318 tcg_out_ext32s(s, datalo, datalo); 2319 } else { 2320 tcg_out_modrm_sib_offset(s, OPC_MOVSLQ + h.seg, datalo, 2321 h.base, h.index, 0, h.ofs); 2322 } 2323 break; 2324#endif 2325 case MO_UQ: 2326 if (TCG_TARGET_REG_BITS == 64) { 2327 tcg_out_modrm_sib_offset(s, movop + P_REXW + h.seg, datalo, 2328 h.base, h.index, 0, h.ofs); 2329 break; 2330 } 2331 if (use_movbe) { 2332 TCGReg t = datalo; 2333 datalo = datahi; 2334 datahi = t; 2335 } 2336 if (h.base == datalo || h.index == datalo) { 2337 tcg_out_modrm_sib_offset(s, OPC_LEA, datahi, 2338 h.base, h.index, 0, h.ofs); 2339 tcg_out_modrm_offset(s, movop + h.seg, datalo, datahi, 0); 2340 tcg_out_modrm_offset(s, movop + h.seg, datahi, datahi, 4); 2341 } else { 2342 tcg_out_modrm_sib_offset(s, movop + h.seg, datalo, 2343 h.base, h.index, 0, h.ofs); 2344 tcg_out_modrm_sib_offset(s, movop + h.seg, datahi, 2345 h.base, h.index, 0, h.ofs + 4); 2346 } 2347 break; 2348 2349 case MO_128: 2350 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 2351 2352 /* 2353 * Without 16-byte atomicity, use integer regs. 2354 * That is where we want the data, and it allows bswaps. 2355 */ 2356 if (h.aa.atom < MO_128) { 2357 if (use_movbe) { 2358 TCGReg t = datalo; 2359 datalo = datahi; 2360 datahi = t; 2361 } 2362 if (h.base == datalo || h.index == datalo) { 2363 tcg_out_modrm_sib_offset(s, OPC_LEA + P_REXW, datahi, 2364 h.base, h.index, 0, h.ofs); 2365 tcg_out_modrm_offset(s, movop + P_REXW + h.seg, 2366 datalo, datahi, 0); 2367 tcg_out_modrm_offset(s, movop + P_REXW + h.seg, 2368 datahi, datahi, 8); 2369 } else { 2370 tcg_out_modrm_sib_offset(s, movop + P_REXW + h.seg, datalo, 2371 h.base, h.index, 0, h.ofs); 2372 tcg_out_modrm_sib_offset(s, movop + P_REXW + h.seg, datahi, 2373 h.base, h.index, 0, h.ofs + 8); 2374 } 2375 break; 2376 } 2377 2378 /* 2379 * With 16-byte atomicity, a vector load is required. 2380 * If we already have 16-byte alignment, then VMOVDQA always works. 2381 * Else if VMOVDQU has atomicity with dynamic alignment, use that. 2382 * Else use we require a runtime test for alignment for VMOVDQA; 2383 * use VMOVDQU on the unaligned nonatomic path for simplicity. 2384 */ 2385 if (h.aa.align >= MO_128) { 2386 tcg_out_vex_modrm_sib_offset(s, OPC_MOVDQA_VxWx + h.seg, 2387 TCG_TMP_VEC, 0, 2388 h.base, h.index, 0, h.ofs); 2389 } else if (cpuinfo & CPUINFO_ATOMIC_VMOVDQU) { 2390 tcg_out_vex_modrm_sib_offset(s, OPC_MOVDQU_VxWx + h.seg, 2391 TCG_TMP_VEC, 0, 2392 h.base, h.index, 0, h.ofs); 2393 } else { 2394 TCGLabel *l1 = gen_new_label(); 2395 TCGLabel *l2 = gen_new_label(); 2396 int jcc; 2397 2398 jcc = tcg_out_cmp(s, TCG_COND_TSTNE, h.base, 15, true, false); 2399 tcg_out_jxx(s, jcc, l1, true); 2400 2401 tcg_out_vex_modrm_sib_offset(s, OPC_MOVDQA_VxWx + h.seg, 2402 TCG_TMP_VEC, 0, 2403 h.base, h.index, 0, h.ofs); 2404 tcg_out_jxx(s, JCC_JMP, l2, true); 2405 2406 tcg_out_label(s, l1); 2407 tcg_out_vex_modrm_sib_offset(s, OPC_MOVDQU_VxWx + h.seg, 2408 TCG_TMP_VEC, 0, 2409 h.base, h.index, 0, h.ofs); 2410 tcg_out_label(s, l2); 2411 } 2412 tcg_out_vec_to_pair(s, TCG_TYPE_I64, datalo, datahi, TCG_TMP_VEC); 2413 break; 2414 2415 default: 2416 g_assert_not_reached(); 2417 } 2418} 2419 2420static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, 2421 TCGReg addr, MemOpIdx oi, TCGType data_type) 2422{ 2423 TCGLabelQemuLdst *ldst; 2424 HostAddress h; 2425 2426 ldst = prepare_host_addr(s, &h, addr, oi, true); 2427 tcg_out_qemu_ld_direct(s, datalo, datahi, h, data_type, get_memop(oi)); 2428 2429 if (ldst) { 2430 ldst->type = data_type; 2431 ldst->datalo_reg = datalo; 2432 ldst->datahi_reg = datahi; 2433 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 2434 } 2435} 2436 2437static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, 2438 HostAddress h, MemOp memop) 2439{ 2440 bool use_movbe = false; 2441 int movop = OPC_MOVL_EvGv; 2442 2443 /* 2444 * Do big-endian stores with movbe or system-mode. 2445 * User-only without movbe will have its swapping done generically. 2446 */ 2447 if (memop & MO_BSWAP) { 2448 tcg_debug_assert(have_movbe); 2449 use_movbe = true; 2450 movop = OPC_MOVBE_MyGy; 2451 } 2452 2453 switch (memop & MO_SIZE) { 2454 case MO_8: 2455 /* This is handled with constraints on INDEX_op_qemu_st8_i32. */ 2456 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || datalo < 4); 2457 tcg_out_modrm_sib_offset(s, OPC_MOVB_EvGv + P_REXB_R + h.seg, 2458 datalo, h.base, h.index, 0, h.ofs); 2459 break; 2460 case MO_16: 2461 tcg_out_modrm_sib_offset(s, movop + P_DATA16 + h.seg, datalo, 2462 h.base, h.index, 0, h.ofs); 2463 break; 2464 case MO_32: 2465 tcg_out_modrm_sib_offset(s, movop + h.seg, datalo, 2466 h.base, h.index, 0, h.ofs); 2467 break; 2468 case MO_64: 2469 if (TCG_TARGET_REG_BITS == 64) { 2470 tcg_out_modrm_sib_offset(s, movop + P_REXW + h.seg, datalo, 2471 h.base, h.index, 0, h.ofs); 2472 } else { 2473 if (use_movbe) { 2474 TCGReg t = datalo; 2475 datalo = datahi; 2476 datahi = t; 2477 } 2478 tcg_out_modrm_sib_offset(s, movop + h.seg, datalo, 2479 h.base, h.index, 0, h.ofs); 2480 tcg_out_modrm_sib_offset(s, movop + h.seg, datahi, 2481 h.base, h.index, 0, h.ofs + 4); 2482 } 2483 break; 2484 2485 case MO_128: 2486 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 2487 2488 /* 2489 * Without 16-byte atomicity, use integer regs. 2490 * That is where we have the data, and it allows bswaps. 2491 */ 2492 if (h.aa.atom < MO_128) { 2493 if (use_movbe) { 2494 TCGReg t = datalo; 2495 datalo = datahi; 2496 datahi = t; 2497 } 2498 tcg_out_modrm_sib_offset(s, movop + P_REXW + h.seg, datalo, 2499 h.base, h.index, 0, h.ofs); 2500 tcg_out_modrm_sib_offset(s, movop + P_REXW + h.seg, datahi, 2501 h.base, h.index, 0, h.ofs + 8); 2502 break; 2503 } 2504 2505 /* 2506 * With 16-byte atomicity, a vector store is required. 2507 * If we already have 16-byte alignment, then VMOVDQA always works. 2508 * Else if VMOVDQU has atomicity with dynamic alignment, use that. 2509 * Else use we require a runtime test for alignment for VMOVDQA; 2510 * use VMOVDQU on the unaligned nonatomic path for simplicity. 2511 */ 2512 tcg_out_pair_to_vec(s, TCG_TYPE_I64, TCG_TMP_VEC, datalo, datahi); 2513 if (h.aa.align >= MO_128) { 2514 tcg_out_vex_modrm_sib_offset(s, OPC_MOVDQA_WxVx + h.seg, 2515 TCG_TMP_VEC, 0, 2516 h.base, h.index, 0, h.ofs); 2517 } else if (cpuinfo & CPUINFO_ATOMIC_VMOVDQU) { 2518 tcg_out_vex_modrm_sib_offset(s, OPC_MOVDQU_WxVx + h.seg, 2519 TCG_TMP_VEC, 0, 2520 h.base, h.index, 0, h.ofs); 2521 } else { 2522 TCGLabel *l1 = gen_new_label(); 2523 TCGLabel *l2 = gen_new_label(); 2524 int jcc; 2525 2526 jcc = tcg_out_cmp(s, TCG_COND_TSTNE, h.base, 15, true, false); 2527 tcg_out_jxx(s, jcc, l1, true); 2528 2529 tcg_out_vex_modrm_sib_offset(s, OPC_MOVDQA_WxVx + h.seg, 2530 TCG_TMP_VEC, 0, 2531 h.base, h.index, 0, h.ofs); 2532 tcg_out_jxx(s, JCC_JMP, l2, true); 2533 2534 tcg_out_label(s, l1); 2535 tcg_out_vex_modrm_sib_offset(s, OPC_MOVDQU_WxVx + h.seg, 2536 TCG_TMP_VEC, 0, 2537 h.base, h.index, 0, h.ofs); 2538 tcg_out_label(s, l2); 2539 } 2540 break; 2541 2542 default: 2543 g_assert_not_reached(); 2544 } 2545} 2546 2547static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, 2548 TCGReg addr, MemOpIdx oi, TCGType data_type) 2549{ 2550 TCGLabelQemuLdst *ldst; 2551 HostAddress h; 2552 2553 ldst = prepare_host_addr(s, &h, addr, oi, false); 2554 tcg_out_qemu_st_direct(s, datalo, datahi, h, get_memop(oi)); 2555 2556 if (ldst) { 2557 ldst->type = data_type; 2558 ldst->datalo_reg = datalo; 2559 ldst->datahi_reg = datahi; 2560 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 2561 } 2562} 2563 2564static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 2565{ 2566 /* Reuse the zeroing that exists for goto_ptr. */ 2567 if (a0 == 0) { 2568 tcg_out_jmp(s, tcg_code_gen_epilogue); 2569 } else { 2570 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_EAX, a0); 2571 tcg_out_jmp(s, tb_ret_addr); 2572 } 2573} 2574 2575static void tcg_out_goto_tb(TCGContext *s, int which) 2576{ 2577 /* 2578 * Jump displacement must be aligned for atomic patching; 2579 * see if we need to add extra nops before jump 2580 */ 2581 int gap = QEMU_ALIGN_PTR_UP(s->code_ptr + 1, 4) - s->code_ptr; 2582 if (gap != 1) { 2583 tcg_out_nopn(s, gap - 1); 2584 } 2585 tcg_out8(s, OPC_JMP_long); /* jmp im */ 2586 set_jmp_insn_offset(s, which); 2587 tcg_out32(s, 0); 2588 set_jmp_reset_offset(s, which); 2589} 2590 2591void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 2592 uintptr_t jmp_rx, uintptr_t jmp_rw) 2593{ 2594 /* patch the branch destination */ 2595 uintptr_t addr = tb->jmp_target_addr[n]; 2596 qatomic_set((int32_t *)jmp_rw, addr - (jmp_rx + 4)); 2597 /* no need to flush icache explicitly */ 2598} 2599 2600 2601static void tgen_add(TCGContext *s, TCGType type, 2602 TCGReg a0, TCGReg a1, TCGReg a2) 2603{ 2604 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2605 2606 if (a0 == a1) { 2607 tgen_arithr(s, ARITH_ADD + rexw, a0, a2); 2608 } else if (a0 == a2) { 2609 tgen_arithr(s, ARITH_ADD + rexw, a0, a1); 2610 } else { 2611 tcg_out_modrm_sib_offset(s, OPC_LEA + rexw, a0, a1, a2, 0, 0); 2612 } 2613} 2614 2615static void tgen_addi(TCGContext *s, TCGType type, 2616 TCGReg a0, TCGReg a1, tcg_target_long a2) 2617{ 2618 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2619 2620 if (a0 == a1) { 2621 tgen_arithi(s, ARITH_ADD + rexw, a0, a2, false); 2622 } else { 2623 tcg_out_modrm_sib_offset(s, OPC_LEA + rexw, a0, a1, -1, 0, a2); 2624 } 2625} 2626 2627static const TCGOutOpBinary outop_add = { 2628 .base.static_constraint = C_O1_I2(r, r, re), 2629 .out_rrr = tgen_add, 2630 .out_rri = tgen_addi, 2631}; 2632 2633static void tgen_addco(TCGContext *s, TCGType type, 2634 TCGReg a0, TCGReg a1, TCGReg a2) 2635{ 2636 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2637 tgen_arithr(s, ARITH_ADD + rexw, a0, a2); 2638} 2639 2640static void tgen_addco_imm(TCGContext *s, TCGType type, 2641 TCGReg a0, TCGReg a1, tcg_target_long a2) 2642{ 2643 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2644 tgen_arithi(s, ARITH_ADD + rexw, a0, a2, true); 2645} 2646 2647static const TCGOutOpBinary outop_addco = { 2648 .base.static_constraint = C_O1_I2(r, 0, re), 2649 .out_rrr = tgen_addco, 2650 .out_rri = tgen_addco_imm, 2651}; 2652 2653static void tgen_addcio(TCGContext *s, TCGType type, 2654 TCGReg a0, TCGReg a1, TCGReg a2) 2655{ 2656 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2657 tgen_arithr(s, ARITH_ADC + rexw, a0, a2); 2658} 2659 2660static void tgen_addcio_imm(TCGContext *s, TCGType type, 2661 TCGReg a0, TCGReg a1, tcg_target_long a2) 2662{ 2663 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2664 tgen_arithi(s, ARITH_ADC + rexw, a0, a2, true); 2665} 2666 2667static const TCGOutOpBinary outop_addcio = { 2668 .base.static_constraint = C_O1_I2(r, 0, re), 2669 .out_rrr = tgen_addcio, 2670 .out_rri = tgen_addcio_imm, 2671}; 2672 2673static void tgen_addci_rrr(TCGContext *s, TCGType type, 2674 TCGReg a0, TCGReg a1, TCGReg a2) 2675{ 2676 /* Because "0O" is not a valid constraint, we must match ourselves. */ 2677 if (a0 == a2) { 2678 tgen_addcio(s, type, a0, a0, a1); 2679 } else { 2680 tcg_out_mov(s, type, a0, a1); 2681 tgen_addcio(s, type, a0, a0, a2); 2682 } 2683} 2684 2685static void tgen_addci_rri(TCGContext *s, TCGType type, 2686 TCGReg a0, TCGReg a1, tcg_target_long a2) 2687{ 2688 tcg_out_mov(s, type, a0, a1); 2689 tgen_addcio_imm(s, type, a0, a0, a2); 2690} 2691 2692static void tgen_addci_rir(TCGContext *s, TCGType type, 2693 TCGReg a0, tcg_target_long a1, TCGReg a2) 2694{ 2695 tgen_addci_rri(s, type, a0, a2, a1); 2696} 2697 2698static void tgen_addci_rii(TCGContext *s, TCGType type, TCGReg a0, 2699 tcg_target_long a1, tcg_target_long a2) 2700{ 2701 if (a2 == 0) { 2702 /* Implement 0 + 0 + C with -(x - x - c). */ 2703 tgen_arithr(s, ARITH_SBB, a0, a0); 2704 tcg_out_modrm(s, OPC_GRP3_Ev, EXT3_NEG, a0); 2705 } else { 2706 tcg_out_movi(s, type, a0, a2); 2707 tgen_addcio_imm(s, type, a0, a0, a1); 2708 } 2709} 2710 2711static const TCGOutOpAddSubCarry outop_addci = { 2712 .base.static_constraint = C_O1_I2(r, rO, re), 2713 .out_rrr = tgen_addci_rrr, 2714 .out_rri = tgen_addci_rri, 2715 .out_rir = tgen_addci_rir, 2716 .out_rii = tgen_addci_rii, 2717}; 2718 2719static void tcg_out_set_carry(TCGContext *s) 2720{ 2721 tcg_out8(s, OPC_STC); 2722} 2723 2724static void tgen_and(TCGContext *s, TCGType type, 2725 TCGReg a0, TCGReg a1, TCGReg a2) 2726{ 2727 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2728 tgen_arithr(s, ARITH_AND + rexw, a0, a2); 2729} 2730 2731static void tgen_andi(TCGContext *s, TCGType type, 2732 TCGReg a0, TCGReg a1, tcg_target_long a2) 2733{ 2734 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2735 tgen_arithi(s, ARITH_AND + rexw, a0, a2, false); 2736} 2737 2738static const TCGOutOpBinary outop_and = { 2739 .base.static_constraint = C_O1_I2(r, 0, reZ), 2740 .out_rrr = tgen_and, 2741 .out_rri = tgen_andi, 2742}; 2743 2744static void tgen_andc(TCGContext *s, TCGType type, 2745 TCGReg a0, TCGReg a1, TCGReg a2) 2746{ 2747 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2748 tcg_out_vex_modrm(s, OPC_ANDN + rexw, a0, a2, a1); 2749} 2750 2751static TCGConstraintSetIndex cset_andc(TCGType type, unsigned flags) 2752{ 2753 return have_bmi1 ? C_O1_I2(r, r, r) : C_NotImplemented; 2754} 2755 2756static const TCGOutOpBinary outop_andc = { 2757 .base.static_constraint = C_Dynamic, 2758 .base.dynamic_constraint = cset_andc, 2759 .out_rrr = tgen_andc, 2760}; 2761 2762static void tgen_clz(TCGContext *s, TCGType type, 2763 TCGReg a0, TCGReg a1, TCGReg a2) 2764{ 2765 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2766 int jcc; 2767 2768 if (have_lzcnt) { 2769 tcg_out_modrm(s, OPC_LZCNT + rexw, a0, a1); 2770 jcc = JCC_JB; 2771 } else { 2772 /* Recall that the output of BSR is the index not the count. */ 2773 tcg_out_modrm(s, OPC_BSR + rexw, a0, a1); 2774 tgen_arithi(s, ARITH_XOR + rexw, a0, rexw ? 63 : 31, 0); 2775 2776 /* Since we have destroyed the flags from BSR, we have to re-test. */ 2777 jcc = tcg_out_cmp(s, TCG_COND_EQ, a1, 0, 1, rexw); 2778 } 2779 tcg_out_cmov(s, jcc, rexw, a0, a2); 2780} 2781 2782static void tgen_clzi(TCGContext *s, TCGType type, 2783 TCGReg a0, TCGReg a1, tcg_target_long a2) 2784{ 2785 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2786 tcg_out_modrm(s, OPC_LZCNT + rexw, a0, a1); 2787} 2788 2789static TCGConstraintSetIndex cset_clz(TCGType type, unsigned flags) 2790{ 2791 return have_lzcnt ? C_N1_I2(r, r, rW) : C_N1_I2(r, r, r); 2792} 2793 2794static const TCGOutOpBinary outop_clz = { 2795 .base.static_constraint = C_Dynamic, 2796 .base.dynamic_constraint = cset_clz, 2797 .out_rrr = tgen_clz, 2798 .out_rri = tgen_clzi, 2799}; 2800 2801static void tgen_ctpop(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2802{ 2803 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2804 tcg_out_modrm(s, OPC_POPCNT + rexw, a0, a1); 2805} 2806 2807static TCGConstraintSetIndex cset_ctpop(TCGType type, unsigned flags) 2808{ 2809 return have_popcnt ? C_O1_I1(r, r) : C_NotImplemented; 2810} 2811 2812static const TCGOutOpUnary outop_ctpop = { 2813 .base.static_constraint = C_Dynamic, 2814 .base.dynamic_constraint = cset_ctpop, 2815 .out_rr = tgen_ctpop, 2816}; 2817 2818static void tgen_ctz(TCGContext *s, TCGType type, 2819 TCGReg a0, TCGReg a1, TCGReg a2) 2820{ 2821 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2822 int jcc; 2823 2824 if (have_bmi1) { 2825 tcg_out_modrm(s, OPC_TZCNT + rexw, a0, a1); 2826 jcc = JCC_JB; 2827 } else { 2828 tcg_out_modrm(s, OPC_BSF + rexw, a0, a1); 2829 jcc = JCC_JE; 2830 } 2831 tcg_out_cmov(s, jcc, rexw, a0, a2); 2832} 2833 2834static void tgen_ctzi(TCGContext *s, TCGType type, 2835 TCGReg a0, TCGReg a1, tcg_target_long a2) 2836{ 2837 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2838 tcg_out_modrm(s, OPC_TZCNT + rexw, a0, a1); 2839} 2840 2841static TCGConstraintSetIndex cset_ctz(TCGType type, unsigned flags) 2842{ 2843 return have_bmi1 ? C_N1_I2(r, r, rW) : C_N1_I2(r, r, r); 2844} 2845 2846static const TCGOutOpBinary outop_ctz = { 2847 .base.static_constraint = C_Dynamic, 2848 .base.dynamic_constraint = cset_ctz, 2849 .out_rrr = tgen_ctz, 2850 .out_rri = tgen_ctzi, 2851}; 2852 2853static const TCGOutOpBinary outop_divs = { 2854 .base.static_constraint = C_NotImplemented, 2855}; 2856 2857static void tgen_divs2(TCGContext *s, TCGType type, 2858 TCGReg a0, TCGReg a1, TCGReg a4) 2859{ 2860 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2861 tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_IDIV, a4); 2862} 2863 2864static const TCGOutOpDivRem outop_divs2 = { 2865 .base.static_constraint = C_O2_I3(a, d, 0, 1, r), 2866 .out_rr01r = tgen_divs2, 2867}; 2868 2869static const TCGOutOpBinary outop_divu = { 2870 .base.static_constraint = C_NotImplemented, 2871}; 2872 2873static void tgen_divu2(TCGContext *s, TCGType type, 2874 TCGReg a0, TCGReg a1, TCGReg a4) 2875{ 2876 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2877 tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_DIV, a4); 2878} 2879 2880static const TCGOutOpDivRem outop_divu2 = { 2881 .base.static_constraint = C_O2_I3(a, d, 0, 1, r), 2882 .out_rr01r = tgen_divu2, 2883}; 2884 2885static const TCGOutOpBinary outop_eqv = { 2886 .base.static_constraint = C_NotImplemented, 2887}; 2888 2889#if TCG_TARGET_REG_BITS == 64 2890static void tgen_extrh_i64_i32(TCGContext *s, TCGType t, TCGReg a0, TCGReg a1) 2891{ 2892 tcg_out_shifti(s, SHIFT_SHR + P_REXW, a0, 32); 2893} 2894 2895static const TCGOutOpUnary outop_extrh_i64_i32 = { 2896 .base.static_constraint = C_O1_I1(r, 0), 2897 .out_rr = tgen_extrh_i64_i32, 2898}; 2899#endif /* TCG_TARGET_REG_BITS == 64 */ 2900 2901static void tgen_mul(TCGContext *s, TCGType type, 2902 TCGReg a0, TCGReg a1, TCGReg a2) 2903{ 2904 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2905 tcg_out_modrm(s, OPC_IMUL_GvEv + rexw, a0, a2); 2906} 2907 2908static void tgen_muli(TCGContext *s, TCGType type, 2909 TCGReg a0, TCGReg a1, tcg_target_long a2) 2910{ 2911 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2912 2913 if (a2 == (int8_t)a2) { 2914 tcg_out_modrm(s, OPC_IMUL_GvEvIb + rexw, a0, a0); 2915 tcg_out8(s, a2); 2916 } else { 2917 tcg_out_modrm(s, OPC_IMUL_GvEvIz + rexw, a0, a0); 2918 tcg_out32(s, a2); 2919 } 2920} 2921 2922static const TCGOutOpBinary outop_mul = { 2923 .base.static_constraint = C_O1_I2(r, 0, re), 2924 .out_rrr = tgen_mul, 2925 .out_rri = tgen_muli, 2926}; 2927 2928static void tgen_muls2(TCGContext *s, TCGType type, 2929 TCGReg a0, TCGReg a1, TCGReg a2, TCGReg a3) 2930{ 2931 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2932 tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_IMUL, a3); 2933} 2934 2935static const TCGOutOpMul2 outop_muls2 = { 2936 .base.static_constraint = C_O2_I2(a, d, a, r), 2937 .out_rrrr = tgen_muls2, 2938}; 2939 2940static const TCGOutOpBinary outop_mulsh = { 2941 .base.static_constraint = C_NotImplemented, 2942}; 2943 2944static const TCGOutOpBinary outop_muluh = { 2945 .base.static_constraint = C_NotImplemented, 2946}; 2947 2948static void tgen_mulu2(TCGContext *s, TCGType type, 2949 TCGReg a0, TCGReg a1, TCGReg a2, TCGReg a3) 2950{ 2951 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2952 tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_MUL, a3); 2953} 2954 2955static const TCGOutOpMul2 outop_mulu2 = { 2956 .base.static_constraint = C_O2_I2(a, d, a, r), 2957 .out_rrrr = tgen_mulu2, 2958}; 2959 2960static const TCGOutOpBinary outop_nand = { 2961 .base.static_constraint = C_NotImplemented, 2962}; 2963 2964static const TCGOutOpBinary outop_nor = { 2965 .base.static_constraint = C_NotImplemented, 2966}; 2967 2968static void tgen_or(TCGContext *s, TCGType type, 2969 TCGReg a0, TCGReg a1, TCGReg a2) 2970{ 2971 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2972 tgen_arithr(s, ARITH_OR + rexw, a0, a2); 2973} 2974 2975static void tgen_ori(TCGContext *s, TCGType type, 2976 TCGReg a0, TCGReg a1, tcg_target_long a2) 2977{ 2978 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2979 tgen_arithi(s, ARITH_OR + rexw, a0, a2, false); 2980} 2981 2982static const TCGOutOpBinary outop_or = { 2983 .base.static_constraint = C_O1_I2(r, 0, re), 2984 .out_rrr = tgen_or, 2985 .out_rri = tgen_ori, 2986}; 2987 2988static const TCGOutOpBinary outop_orc = { 2989 .base.static_constraint = C_NotImplemented, 2990}; 2991 2992static const TCGOutOpBinary outop_rems = { 2993 .base.static_constraint = C_NotImplemented, 2994}; 2995 2996static const TCGOutOpBinary outop_remu = { 2997 .base.static_constraint = C_NotImplemented, 2998}; 2999 3000static void tgen_rotl(TCGContext *s, TCGType type, 3001 TCGReg a0, TCGReg a1, TCGReg a2) 3002{ 3003 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 3004 tcg_out_modrm(s, OPC_SHIFT_cl + rexw, SHIFT_ROL, a0); 3005} 3006 3007static void tgen_rotli(TCGContext *s, TCGType type, 3008 TCGReg a0, TCGReg a1, tcg_target_long a2) 3009{ 3010 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 3011 tcg_out_shifti(s, SHIFT_ROL + rexw, a0, a2); 3012} 3013 3014static const TCGOutOpBinary outop_rotl = { 3015 .base.static_constraint = C_O1_I2(r, 0, ci), 3016 .out_rrr = tgen_rotl, 3017 .out_rri = tgen_rotli, 3018}; 3019 3020static void tgen_rotr(TCGContext *s, TCGType type, 3021 TCGReg a0, TCGReg a1, TCGReg a2) 3022{ 3023 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 3024 tcg_out_modrm(s, OPC_SHIFT_cl + rexw, SHIFT_ROR, a0); 3025} 3026 3027static void tgen_rotri(TCGContext *s, TCGType type, 3028 TCGReg a0, TCGReg a1, tcg_target_long a2) 3029{ 3030 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 3031 tcg_out_shifti(s, SHIFT_ROR + rexw, a0, a2); 3032} 3033 3034static const TCGOutOpBinary outop_rotr = { 3035 .base.static_constraint = C_O1_I2(r, 0, ci), 3036 .out_rrr = tgen_rotr, 3037 .out_rri = tgen_rotri, 3038}; 3039 3040static TCGConstraintSetIndex cset_shift(TCGType type, unsigned flags) 3041{ 3042 return have_bmi2 ? C_O1_I2(r, r, ri) : C_O1_I2(r, 0, ci); 3043} 3044 3045static void tgen_sar(TCGContext *s, TCGType type, 3046 TCGReg a0, TCGReg a1, TCGReg a2) 3047{ 3048 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 3049 if (have_bmi2) { 3050 tcg_out_vex_modrm(s, OPC_SARX + rexw, a0, a2, a1); 3051 } else { 3052 tcg_out_modrm(s, OPC_SHIFT_cl + rexw, SHIFT_SAR, a0); 3053 } 3054} 3055 3056static void tgen_sari(TCGContext *s, TCGType type, 3057 TCGReg a0, TCGReg a1, tcg_target_long a2) 3058{ 3059 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 3060 3061 tcg_out_mov(s, type, a0, a1); 3062 tcg_out_shifti(s, SHIFT_SAR + rexw, a0, a2); 3063} 3064 3065static const TCGOutOpBinary outop_sar = { 3066 .base.static_constraint = C_Dynamic, 3067 .base.dynamic_constraint = cset_shift, 3068 .out_rrr = tgen_sar, 3069 .out_rri = tgen_sari, 3070}; 3071 3072static void tgen_shl(TCGContext *s, TCGType type, 3073 TCGReg a0, TCGReg a1, TCGReg a2) 3074{ 3075 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 3076 if (have_bmi2) { 3077 tcg_out_vex_modrm(s, OPC_SHLX + rexw, a0, a2, a1); 3078 } else { 3079 tcg_out_modrm(s, OPC_SHIFT_cl + rexw, SHIFT_SHL, a0); 3080 } 3081} 3082 3083static void tgen_shli(TCGContext *s, TCGType type, 3084 TCGReg a0, TCGReg a1, tcg_target_long a2) 3085{ 3086 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 3087 3088 /* For small constant 3-operand shift, use LEA. */ 3089 if (a0 != a1 && a2 >= 1 && a2 <= 3) { 3090 if (a2 == 1) { 3091 /* shl $1,a1,a0 -> lea (a1,a1),a0 */ 3092 tcg_out_modrm_sib_offset(s, OPC_LEA + rexw, a0, a1, a1, 0, 0); 3093 } else { 3094 /* shl $n,a1,a0 -> lea 0(,a1,n),a0 */ 3095 tcg_out_modrm_sib_offset(s, OPC_LEA + rexw, a0, -1, a1, a2, 0); 3096 } 3097 return; 3098 } 3099 tcg_out_mov(s, type, a0, a1); 3100 tcg_out_shifti(s, SHIFT_SHL + rexw, a0, a2); 3101} 3102 3103static const TCGOutOpBinary outop_shl = { 3104 .base.static_constraint = C_Dynamic, 3105 .base.dynamic_constraint = cset_shift, 3106 .out_rrr = tgen_shl, 3107 .out_rri = tgen_shli, 3108}; 3109 3110static void tgen_shr(TCGContext *s, TCGType type, 3111 TCGReg a0, TCGReg a1, TCGReg a2) 3112{ 3113 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 3114 if (have_bmi2) { 3115 tcg_out_vex_modrm(s, OPC_SHRX + rexw, a0, a2, a1); 3116 } else { 3117 tcg_out_modrm(s, OPC_SHIFT_cl + rexw, SHIFT_SHR, a0); 3118 } 3119} 3120 3121static void tgen_shri(TCGContext *s, TCGType type, 3122 TCGReg a0, TCGReg a1, tcg_target_long a2) 3123{ 3124 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 3125 3126 tcg_out_mov(s, type, a0, a1); 3127 tcg_out_shifti(s, SHIFT_SHR + rexw, a0, a2); 3128} 3129 3130static const TCGOutOpBinary outop_shr = { 3131 .base.static_constraint = C_Dynamic, 3132 .base.dynamic_constraint = cset_shift, 3133 .out_rrr = tgen_shr, 3134 .out_rri = tgen_shri, 3135}; 3136 3137static void tgen_sub(TCGContext *s, TCGType type, 3138 TCGReg a0, TCGReg a1, TCGReg a2) 3139{ 3140 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 3141 tgen_arithr(s, ARITH_SUB + rexw, a0, a2); 3142} 3143 3144static const TCGOutOpSubtract outop_sub = { 3145 .base.static_constraint = C_O1_I2(r, 0, r), 3146 .out_rrr = tgen_sub, 3147}; 3148 3149static void tgen_subbo_rri(TCGContext *s, TCGType type, 3150 TCGReg a0, TCGReg a1, tcg_target_long a2) 3151{ 3152 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 3153 tgen_arithi(s, ARITH_SUB + rexw, a0, a2, 1); 3154} 3155 3156static const TCGOutOpAddSubCarry outop_subbo = { 3157 .base.static_constraint = C_O1_I2(r, 0, re), 3158 .out_rrr = tgen_sub, 3159 .out_rri = tgen_subbo_rri, 3160}; 3161 3162static void tgen_subbio_rrr(TCGContext *s, TCGType type, 3163 TCGReg a0, TCGReg a1, TCGReg a2) 3164{ 3165 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 3166 tgen_arithr(s, ARITH_SBB + rexw, a0, a2); 3167} 3168 3169static void tgen_subbio_rri(TCGContext *s, TCGType type, 3170 TCGReg a0, TCGReg a1, tcg_target_long a2) 3171{ 3172 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 3173 tgen_arithi(s, ARITH_SBB + rexw, a0, a2, 1); 3174} 3175 3176static const TCGOutOpAddSubCarry outop_subbio = { 3177 .base.static_constraint = C_O1_I2(r, 0, re), 3178 .out_rrr = tgen_subbio_rrr, 3179 .out_rri = tgen_subbio_rri, 3180}; 3181 3182#define outop_subbi outop_subbio 3183 3184static void tcg_out_set_borrow(TCGContext *s) 3185{ 3186 tcg_out8(s, OPC_STC); 3187} 3188 3189static void tgen_xor(TCGContext *s, TCGType type, 3190 TCGReg a0, TCGReg a1, TCGReg a2) 3191{ 3192 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 3193 tgen_arithr(s, ARITH_XOR + rexw, a0, a2); 3194} 3195 3196static void tgen_xori(TCGContext *s, TCGType type, 3197 TCGReg a0, TCGReg a1, tcg_target_long a2) 3198{ 3199 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 3200 tgen_arithi(s, ARITH_XOR + rexw, a0, a2, false); 3201} 3202 3203static const TCGOutOpBinary outop_xor = { 3204 .base.static_constraint = C_O1_I2(r, 0, re), 3205 .out_rrr = tgen_xor, 3206 .out_rri = tgen_xori, 3207}; 3208 3209static void tgen_bswap16(TCGContext *s, TCGType type, 3210 TCGReg a0, TCGReg a1, unsigned flags) 3211{ 3212 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 3213 3214 if (flags & TCG_BSWAP_OS) { 3215 /* Output must be sign-extended. */ 3216 if (rexw) { 3217 tcg_out_bswap64(s, a0); 3218 tcg_out_shifti(s, SHIFT_SAR + rexw, a0, 48); 3219 } else { 3220 tcg_out_bswap32(s, a0); 3221 tcg_out_shifti(s, SHIFT_SAR, a0, 16); 3222 } 3223 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 3224 /* Output must be zero-extended, but input isn't. */ 3225 tcg_out_bswap32(s, a0); 3226 tcg_out_shifti(s, SHIFT_SHR, a0, 16); 3227 } else { 3228 tcg_out_rolw_8(s, a0); 3229 } 3230} 3231 3232static const TCGOutOpBswap outop_bswap16 = { 3233 .base.static_constraint = C_O1_I1(r, 0), 3234 .out_rr = tgen_bswap16, 3235}; 3236 3237static void tgen_bswap32(TCGContext *s, TCGType type, 3238 TCGReg a0, TCGReg a1, unsigned flags) 3239{ 3240 tcg_out_bswap32(s, a0); 3241 if (flags & TCG_BSWAP_OS) { 3242 tcg_out_ext32s(s, a0, a0); 3243 } 3244} 3245 3246static const TCGOutOpBswap outop_bswap32 = { 3247 .base.static_constraint = C_O1_I1(r, 0), 3248 .out_rr = tgen_bswap32, 3249}; 3250 3251#if TCG_TARGET_REG_BITS == 64 3252static void tgen_bswap64(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 3253{ 3254 tcg_out_bswap64(s, a0); 3255} 3256 3257static const TCGOutOpUnary outop_bswap64 = { 3258 .base.static_constraint = C_O1_I1(r, 0), 3259 .out_rr = tgen_bswap64, 3260}; 3261#endif 3262 3263static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 3264{ 3265 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 3266 tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NEG, a0); 3267} 3268 3269static const TCGOutOpUnary outop_neg = { 3270 .base.static_constraint = C_O1_I1(r, 0), 3271 .out_rr = tgen_neg, 3272}; 3273 3274static void tgen_not(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 3275{ 3276 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 3277 tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NOT, a0); 3278} 3279 3280static const TCGOutOpUnary outop_not = { 3281 .base.static_constraint = C_O1_I1(r, 0), 3282 .out_rr = tgen_not, 3283}; 3284 3285static void tgen_deposit(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, 3286 TCGReg a2, unsigned ofs, unsigned len) 3287{ 3288 if (ofs == 0 && len == 8) { 3289 tcg_out_modrm(s, OPC_MOVB_EvGv | P_REXB_R | P_REXB_RM, a2, a0); 3290 } else if (ofs == 0 && len == 16) { 3291 tcg_out_modrm(s, OPC_MOVL_EvGv | P_DATA16, a2, a0); 3292 } else if (TCG_TARGET_REG_BITS == 32 && ofs == 8 && len == 8) { 3293 tcg_out_modrm(s, OPC_MOVB_EvGv, a2, a0 + 4); 3294 } else { 3295 g_assert_not_reached(); 3296 } 3297} 3298 3299static void tgen_depositi(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, 3300 tcg_target_long a2, unsigned ofs, unsigned len) 3301{ 3302 if (ofs == 0 && len == 8) { 3303 tcg_out_opc(s, OPC_MOVB_Ib | P_REXB_RM | LOWREGMASK(a0), 0, a0, 0); 3304 tcg_out8(s, a2); 3305 } else if (ofs == 0 && len == 16) { 3306 tcg_out_opc(s, OPC_MOVL_Iv | P_DATA16 | LOWREGMASK(a0), 0, a0, 0); 3307 tcg_out16(s, a2); 3308 } else if (TCG_TARGET_REG_BITS == 32 && ofs == 8 && len == 8) { 3309 tcg_out8(s, OPC_MOVB_Ib + a0 + 4); 3310 tcg_out8(s, a2); 3311 } else { 3312 g_assert_not_reached(); 3313 } 3314} 3315 3316static const TCGOutOpDeposit outop_deposit = { 3317 .base.static_constraint = C_O1_I2(q, 0, qi), 3318 .out_rrr = tgen_deposit, 3319 .out_rri = tgen_depositi, 3320}; 3321 3322static void tgen_extract(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, 3323 unsigned ofs, unsigned len) 3324{ 3325 if (ofs == 0) { 3326 switch (len) { 3327 case 8: 3328 tcg_out_ext8u(s, a0, a1); 3329 return; 3330 case 16: 3331 tcg_out_ext16u(s, a0, a1); 3332 return; 3333 case 32: 3334 tcg_out_ext32u(s, a0, a1); 3335 return; 3336 } 3337 } else if (TCG_TARGET_REG_BITS == 64 && ofs + len == 32) { 3338 /* This is a 32-bit zero-extending right shift. */ 3339 tcg_out_mov(s, TCG_TYPE_I32, a0, a1); 3340 tcg_out_shifti(s, SHIFT_SHR, a0, ofs); 3341 return; 3342 } else if (ofs == 8 && len == 8) { 3343 /* 3344 * On the off-chance that we can use the high-byte registers. 3345 * Otherwise we emit the same ext16 + shift pattern that we 3346 * would have gotten from the normal tcg-op.c expansion. 3347 */ 3348 if (a1 < 4 && (TCG_TARGET_REG_BITS == 32 || a0 < 8)) { 3349 tcg_out_modrm(s, OPC_MOVZBL, a0, a1 + 4); 3350 } else { 3351 tcg_out_ext16u(s, a0, a1); 3352 tcg_out_shifti(s, SHIFT_SHR, a0, 8); 3353 } 3354 return; 3355 } 3356 g_assert_not_reached(); 3357} 3358 3359static const TCGOutOpExtract outop_extract = { 3360 .base.static_constraint = C_O1_I1(r, r), 3361 .out_rr = tgen_extract, 3362}; 3363 3364static void tgen_sextract(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, 3365 unsigned ofs, unsigned len) 3366{ 3367 if (ofs == 0) { 3368 switch (len) { 3369 case 8: 3370 tcg_out_ext8s(s, type, a0, a1); 3371 return; 3372 case 16: 3373 tcg_out_ext16s(s, type, a0, a1); 3374 return; 3375 case 32: 3376 tcg_out_ext32s(s, a0, a1); 3377 return; 3378 } 3379 } else if (ofs == 8 && len == 8) { 3380 if (type == TCG_TYPE_I32 && a1 < 4 && a0 < 8) { 3381 tcg_out_modrm(s, OPC_MOVSBL, a0, a1 + 4); 3382 } else { 3383 tcg_out_ext16s(s, type, a0, a1); 3384 tgen_sari(s, type, a0, a0, 8); 3385 } 3386 return; 3387 } 3388 g_assert_not_reached(); 3389} 3390 3391static const TCGOutOpExtract outop_sextract = { 3392 .base.static_constraint = C_O1_I1(r, r), 3393 .out_rr = tgen_sextract, 3394}; 3395 3396static void tgen_extract2(TCGContext *s, TCGType type, TCGReg a0, 3397 TCGReg a1, TCGReg a2, unsigned shr) 3398{ 3399 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 3400 3401 /* Note that SHRD outputs to the r/m operand. */ 3402 tcg_out_modrm(s, OPC_SHRD_Ib + rexw, a2, a0); 3403 tcg_out8(s, shr); 3404} 3405 3406static const TCGOutOpExtract2 outop_extract2 = { 3407 .base.static_constraint = C_O1_I2(r, 0, r), 3408 .out_rrr = tgen_extract2, 3409}; 3410 3411 3412static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, 3413 const TCGArg args[TCG_MAX_OP_ARGS], 3414 const int const_args[TCG_MAX_OP_ARGS]) 3415{ 3416 TCGArg a0, a1, a2; 3417 int rexw; 3418 3419#if TCG_TARGET_REG_BITS == 64 3420# define OP_32_64(x) \ 3421 case glue(glue(INDEX_op_, x), _i64): \ 3422 case glue(glue(INDEX_op_, x), _i32) 3423#else 3424# define OP_32_64(x) \ 3425 case glue(glue(INDEX_op_, x), _i32) 3426#endif 3427 3428 /* Hoist the loads of the most common arguments. */ 3429 a0 = args[0]; 3430 a1 = args[1]; 3431 a2 = args[2]; 3432 rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 3433 3434 switch (opc) { 3435 case INDEX_op_goto_ptr: 3436 /* jmp to the given host address (could be epilogue) */ 3437 tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, a0); 3438 break; 3439 case INDEX_op_br: 3440 tcg_out_jxx(s, JCC_JMP, arg_label(a0), 0); 3441 break; 3442 OP_32_64(ld8u): 3443 /* Note that we can ignore REXW for the zero-extend to 64-bit. */ 3444 tcg_out_modrm_offset(s, OPC_MOVZBL, a0, a1, a2); 3445 break; 3446 OP_32_64(ld8s): 3447 tcg_out_modrm_offset(s, OPC_MOVSBL + rexw, a0, a1, a2); 3448 break; 3449 OP_32_64(ld16u): 3450 /* Note that we can ignore REXW for the zero-extend to 64-bit. */ 3451 tcg_out_modrm_offset(s, OPC_MOVZWL, a0, a1, a2); 3452 break; 3453 OP_32_64(ld16s): 3454 tcg_out_modrm_offset(s, OPC_MOVSWL + rexw, a0, a1, a2); 3455 break; 3456#if TCG_TARGET_REG_BITS == 64 3457 case INDEX_op_ld32u_i64: 3458#endif 3459 case INDEX_op_ld_i32: 3460 tcg_out_ld(s, TCG_TYPE_I32, a0, a1, a2); 3461 break; 3462 3463 OP_32_64(st8): 3464 if (const_args[0]) { 3465 tcg_out_modrm_offset(s, OPC_MOVB_EvIz, 0, a1, a2); 3466 tcg_out8(s, a0); 3467 } else { 3468 tcg_out_modrm_offset(s, OPC_MOVB_EvGv | P_REXB_R, a0, a1, a2); 3469 } 3470 break; 3471 OP_32_64(st16): 3472 if (const_args[0]) { 3473 tcg_out_modrm_offset(s, OPC_MOVL_EvIz | P_DATA16, 0, a1, a2); 3474 tcg_out16(s, a0); 3475 } else { 3476 tcg_out_modrm_offset(s, OPC_MOVL_EvGv | P_DATA16, a0, a1, a2); 3477 } 3478 break; 3479#if TCG_TARGET_REG_BITS == 64 3480 case INDEX_op_st32_i64: 3481#endif 3482 case INDEX_op_st_i32: 3483 if (const_args[0]) { 3484 tcg_out_modrm_offset(s, OPC_MOVL_EvIz, 0, a1, a2); 3485 tcg_out32(s, a0); 3486 } else { 3487 tcg_out_st(s, TCG_TYPE_I32, a0, a1, a2); 3488 } 3489 break; 3490 3491 case INDEX_op_qemu_ld_i32: 3492 tcg_out_qemu_ld(s, a0, -1, a1, a2, TCG_TYPE_I32); 3493 break; 3494 case INDEX_op_qemu_ld_i64: 3495 if (TCG_TARGET_REG_BITS == 64) { 3496 tcg_out_qemu_ld(s, a0, -1, a1, a2, TCG_TYPE_I64); 3497 } else { 3498 tcg_out_qemu_ld(s, a0, a1, a2, args[3], TCG_TYPE_I64); 3499 } 3500 break; 3501 case INDEX_op_qemu_ld_i128: 3502 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 3503 tcg_out_qemu_ld(s, a0, a1, a2, args[3], TCG_TYPE_I128); 3504 break; 3505 3506 case INDEX_op_qemu_st_i32: 3507 case INDEX_op_qemu_st8_i32: 3508 tcg_out_qemu_st(s, a0, -1, a1, a2, TCG_TYPE_I32); 3509 break; 3510 case INDEX_op_qemu_st_i64: 3511 if (TCG_TARGET_REG_BITS == 64) { 3512 tcg_out_qemu_st(s, a0, -1, a1, a2, TCG_TYPE_I64); 3513 } else { 3514 tcg_out_qemu_st(s, a0, a1, a2, args[3], TCG_TYPE_I64); 3515 } 3516 break; 3517 case INDEX_op_qemu_st_i128: 3518 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 3519 tcg_out_qemu_st(s, a0, a1, a2, args[3], TCG_TYPE_I128); 3520 break; 3521 3522#if TCG_TARGET_REG_BITS == 64 3523 case INDEX_op_ld32s_i64: 3524 tcg_out_modrm_offset(s, OPC_MOVSLQ, a0, a1, a2); 3525 break; 3526 case INDEX_op_ld_i64: 3527 tcg_out_ld(s, TCG_TYPE_I64, a0, a1, a2); 3528 break; 3529 case INDEX_op_st_i64: 3530 if (const_args[0]) { 3531 tcg_out_modrm_offset(s, OPC_MOVL_EvIz | P_REXW, 0, a1, a2); 3532 tcg_out32(s, a0); 3533 } else { 3534 tcg_out_st(s, TCG_TYPE_I64, a0, a1, a2); 3535 } 3536 break; 3537#endif 3538 3539 case INDEX_op_mb: 3540 tcg_out_mb(s, a0); 3541 break; 3542 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 3543 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 3544 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 3545 default: 3546 g_assert_not_reached(); 3547 } 3548 3549#undef OP_32_64 3550} 3551 3552static int const umin_insn[4] = { 3553 OPC_PMINUB, OPC_PMINUW, OPC_PMINUD, OPC_VPMINUQ 3554}; 3555 3556static int const umax_insn[4] = { 3557 OPC_PMAXUB, OPC_PMAXUW, OPC_PMAXUD, OPC_VPMAXUQ 3558}; 3559 3560static bool tcg_out_cmp_vec_noinv(TCGContext *s, TCGType type, unsigned vece, 3561 TCGReg v0, TCGReg v1, TCGReg v2, TCGCond cond) 3562{ 3563 static int const cmpeq_insn[4] = { 3564 OPC_PCMPEQB, OPC_PCMPEQW, OPC_PCMPEQD, OPC_PCMPEQQ 3565 }; 3566 static int const cmpgt_insn[4] = { 3567 OPC_PCMPGTB, OPC_PCMPGTW, OPC_PCMPGTD, OPC_PCMPGTQ 3568 }; 3569 3570 enum { 3571 NEED_INV = 1, 3572 NEED_SWAP = 2, 3573 NEED_UMIN = 4, 3574 NEED_UMAX = 8, 3575 INVALID = 16, 3576 }; 3577 static const uint8_t cond_fixup[16] = { 3578 [0 ... 15] = INVALID, 3579 [TCG_COND_EQ] = 0, 3580 [TCG_COND_GT] = 0, 3581 [TCG_COND_NE] = NEED_INV, 3582 [TCG_COND_LE] = NEED_INV, 3583 [TCG_COND_LT] = NEED_SWAP, 3584 [TCG_COND_GE] = NEED_SWAP | NEED_INV, 3585 [TCG_COND_LEU] = NEED_UMIN, 3586 [TCG_COND_GTU] = NEED_UMIN | NEED_INV, 3587 [TCG_COND_GEU] = NEED_UMAX, 3588 [TCG_COND_LTU] = NEED_UMAX | NEED_INV, 3589 }; 3590 int fixup = cond_fixup[cond]; 3591 3592 assert(!(fixup & INVALID)); 3593 3594 if (fixup & NEED_INV) { 3595 cond = tcg_invert_cond(cond); 3596 } 3597 3598 if (fixup & NEED_SWAP) { 3599 TCGReg swap = v1; 3600 v1 = v2; 3601 v2 = swap; 3602 cond = tcg_swap_cond(cond); 3603 } 3604 3605 if (fixup & (NEED_UMIN | NEED_UMAX)) { 3606 int op = (fixup & NEED_UMIN ? umin_insn[vece] : umax_insn[vece]); 3607 3608 /* avx2 does not have 64-bit min/max; adjusted during expand. */ 3609 assert(vece <= MO_32); 3610 3611 tcg_out_vex_modrm_type(s, op, TCG_TMP_VEC, v1, v2, type); 3612 v2 = TCG_TMP_VEC; 3613 cond = TCG_COND_EQ; 3614 } 3615 3616 switch (cond) { 3617 case TCG_COND_EQ: 3618 tcg_out_vex_modrm_type(s, cmpeq_insn[vece], v0, v1, v2, type); 3619 break; 3620 case TCG_COND_GT: 3621 tcg_out_vex_modrm_type(s, cmpgt_insn[vece], v0, v1, v2, type); 3622 break; 3623 default: 3624 g_assert_not_reached(); 3625 } 3626 return fixup & NEED_INV; 3627} 3628 3629static void tcg_out_cmp_vec_k1(TCGContext *s, TCGType type, unsigned vece, 3630 TCGReg v1, TCGReg v2, TCGCond cond) 3631{ 3632 static const int cmpm_insn[2][4] = { 3633 { OPC_VPCMPB, OPC_VPCMPW, OPC_VPCMPD, OPC_VPCMPQ }, 3634 { OPC_VPCMPUB, OPC_VPCMPUW, OPC_VPCMPUD, OPC_VPCMPUQ } 3635 }; 3636 static const int testm_insn[4] = { 3637 OPC_VPTESTMB, OPC_VPTESTMW, OPC_VPTESTMD, OPC_VPTESTMQ 3638 }; 3639 static const int testnm_insn[4] = { 3640 OPC_VPTESTNMB, OPC_VPTESTNMW, OPC_VPTESTNMD, OPC_VPTESTNMQ 3641 }; 3642 3643 static const int cond_ext[16] = { 3644 [TCG_COND_EQ] = 0, 3645 [TCG_COND_NE] = 4, 3646 [TCG_COND_LT] = 1, 3647 [TCG_COND_LTU] = 1, 3648 [TCG_COND_LE] = 2, 3649 [TCG_COND_LEU] = 2, 3650 [TCG_COND_NEVER] = 3, 3651 [TCG_COND_GE] = 5, 3652 [TCG_COND_GEU] = 5, 3653 [TCG_COND_GT] = 6, 3654 [TCG_COND_GTU] = 6, 3655 [TCG_COND_ALWAYS] = 7, 3656 }; 3657 3658 switch (cond) { 3659 case TCG_COND_TSTNE: 3660 tcg_out_vex_modrm_type(s, testm_insn[vece], /* k1 */ 1, v1, v2, type); 3661 break; 3662 case TCG_COND_TSTEQ: 3663 tcg_out_vex_modrm_type(s, testnm_insn[vece], /* k1 */ 1, v1, v2, type); 3664 break; 3665 default: 3666 tcg_out_vex_modrm_type(s, cmpm_insn[is_unsigned_cond(cond)][vece], 3667 /* k1 */ 1, v1, v2, type); 3668 tcg_out8(s, cond_ext[cond]); 3669 break; 3670 } 3671} 3672 3673static void tcg_out_k1_to_vec(TCGContext *s, TCGType type, 3674 unsigned vece, TCGReg dest) 3675{ 3676 static const int movm_insn[] = { 3677 OPC_VPMOVM2B, OPC_VPMOVM2W, OPC_VPMOVM2D, OPC_VPMOVM2Q 3678 }; 3679 tcg_out_vex_modrm_type(s, movm_insn[vece], dest, 0, /* k1 */ 1, type); 3680} 3681 3682static void tcg_out_cmp_vec(TCGContext *s, TCGType type, unsigned vece, 3683 TCGReg v0, TCGReg v1, TCGReg v2, TCGCond cond) 3684{ 3685 /* 3686 * With avx512, we have a complete set of comparisons into mask. 3687 * Unless there's a single insn expansion for the comparision, 3688 * expand via a mask in k1. 3689 */ 3690 if ((vece <= MO_16 ? have_avx512bw : have_avx512dq) 3691 && cond != TCG_COND_EQ 3692 && cond != TCG_COND_LT 3693 && cond != TCG_COND_GT) { 3694 tcg_out_cmp_vec_k1(s, type, vece, v1, v2, cond); 3695 tcg_out_k1_to_vec(s, type, vece, v0); 3696 return; 3697 } 3698 3699 if (tcg_out_cmp_vec_noinv(s, type, vece, v0, v1, v2, cond)) { 3700 tcg_out_dupi_vec(s, type, vece, TCG_TMP_VEC, -1); 3701 tcg_out_vex_modrm_type(s, OPC_PXOR, v0, v0, TCG_TMP_VEC, type); 3702 } 3703} 3704 3705static void tcg_out_cmpsel_vec_k1(TCGContext *s, TCGType type, unsigned vece, 3706 TCGReg v0, TCGReg c1, TCGReg c2, 3707 TCGReg v3, TCGReg v4, TCGCond cond) 3708{ 3709 static const int vpblendm_insn[] = { 3710 OPC_VPBLENDMB, OPC_VPBLENDMW, OPC_VPBLENDMD, OPC_VPBLENDMQ 3711 }; 3712 bool z = false; 3713 3714 /* Swap to place constant in V4 to take advantage of zero-masking. */ 3715 if (!v3) { 3716 z = true; 3717 v3 = v4; 3718 cond = tcg_invert_cond(cond); 3719 } 3720 3721 tcg_out_cmp_vec_k1(s, type, vece, c1, c2, cond); 3722 tcg_out_evex_modrm_type(s, vpblendm_insn[vece], v0, v4, v3, 3723 /* k1 */1, z, type); 3724} 3725 3726static void tcg_out_cmpsel_vec(TCGContext *s, TCGType type, unsigned vece, 3727 TCGReg v0, TCGReg c1, TCGReg c2, 3728 TCGReg v3, TCGReg v4, TCGCond cond) 3729{ 3730 bool inv; 3731 3732 if (vece <= MO_16 ? have_avx512bw : have_avx512vl) { 3733 tcg_out_cmpsel_vec_k1(s, type, vece, v0, c1, c2, v3, v4, cond); 3734 return; 3735 } 3736 3737 inv = tcg_out_cmp_vec_noinv(s, type, vece, TCG_TMP_VEC, c1, c2, cond); 3738 3739 /* 3740 * Since XMM0 is 16, the only way we get 0 into V3 3741 * is via the constant zero constraint. 3742 */ 3743 if (!v3) { 3744 if (inv) { 3745 tcg_out_vex_modrm_type(s, OPC_PAND, v0, TCG_TMP_VEC, v4, type); 3746 } else { 3747 tcg_out_vex_modrm_type(s, OPC_PANDN, v0, TCG_TMP_VEC, v4, type); 3748 } 3749 } else { 3750 if (inv) { 3751 TCGReg swap = v3; 3752 v3 = v4; 3753 v4 = swap; 3754 } 3755 tcg_out_vex_modrm_type(s, OPC_VPBLENDVB, v0, v4, v3, type); 3756 tcg_out8(s, (TCG_TMP_VEC - TCG_REG_XMM0) << 4); 3757 } 3758} 3759 3760static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 3761 unsigned vecl, unsigned vece, 3762 const TCGArg args[TCG_MAX_OP_ARGS], 3763 const int const_args[TCG_MAX_OP_ARGS]) 3764{ 3765 static int const add_insn[4] = { 3766 OPC_PADDB, OPC_PADDW, OPC_PADDD, OPC_PADDQ 3767 }; 3768 static int const ssadd_insn[4] = { 3769 OPC_PADDSB, OPC_PADDSW, OPC_UD2, OPC_UD2 3770 }; 3771 static int const usadd_insn[4] = { 3772 OPC_PADDUB, OPC_PADDUW, OPC_UD2, OPC_UD2 3773 }; 3774 static int const sub_insn[4] = { 3775 OPC_PSUBB, OPC_PSUBW, OPC_PSUBD, OPC_PSUBQ 3776 }; 3777 static int const sssub_insn[4] = { 3778 OPC_PSUBSB, OPC_PSUBSW, OPC_UD2, OPC_UD2 3779 }; 3780 static int const ussub_insn[4] = { 3781 OPC_PSUBUB, OPC_PSUBUW, OPC_UD2, OPC_UD2 3782 }; 3783 static int const mul_insn[4] = { 3784 OPC_UD2, OPC_PMULLW, OPC_PMULLD, OPC_VPMULLQ 3785 }; 3786 static int const shift_imm_insn[4] = { 3787 OPC_UD2, OPC_PSHIFTW_Ib, OPC_PSHIFTD_Ib, OPC_PSHIFTQ_Ib 3788 }; 3789 static int const punpckl_insn[4] = { 3790 OPC_PUNPCKLBW, OPC_PUNPCKLWD, OPC_PUNPCKLDQ, OPC_PUNPCKLQDQ 3791 }; 3792 static int const punpckh_insn[4] = { 3793 OPC_PUNPCKHBW, OPC_PUNPCKHWD, OPC_PUNPCKHDQ, OPC_PUNPCKHQDQ 3794 }; 3795 static int const packss_insn[4] = { 3796 OPC_PACKSSWB, OPC_PACKSSDW, OPC_UD2, OPC_UD2 3797 }; 3798 static int const packus_insn[4] = { 3799 OPC_PACKUSWB, OPC_PACKUSDW, OPC_UD2, OPC_UD2 3800 }; 3801 static int const smin_insn[4] = { 3802 OPC_PMINSB, OPC_PMINSW, OPC_PMINSD, OPC_VPMINSQ 3803 }; 3804 static int const smax_insn[4] = { 3805 OPC_PMAXSB, OPC_PMAXSW, OPC_PMAXSD, OPC_VPMAXSQ 3806 }; 3807 static int const rotlv_insn[4] = { 3808 OPC_UD2, OPC_UD2, OPC_VPROLVD, OPC_VPROLVQ 3809 }; 3810 static int const rotrv_insn[4] = { 3811 OPC_UD2, OPC_UD2, OPC_VPRORVD, OPC_VPRORVQ 3812 }; 3813 static int const shlv_insn[4] = { 3814 OPC_UD2, OPC_VPSLLVW, OPC_VPSLLVD, OPC_VPSLLVQ 3815 }; 3816 static int const shrv_insn[4] = { 3817 OPC_UD2, OPC_VPSRLVW, OPC_VPSRLVD, OPC_VPSRLVQ 3818 }; 3819 static int const sarv_insn[4] = { 3820 OPC_UD2, OPC_VPSRAVW, OPC_VPSRAVD, OPC_VPSRAVQ 3821 }; 3822 static int const shls_insn[4] = { 3823 OPC_UD2, OPC_PSLLW, OPC_PSLLD, OPC_PSLLQ 3824 }; 3825 static int const shrs_insn[4] = { 3826 OPC_UD2, OPC_PSRLW, OPC_PSRLD, OPC_PSRLQ 3827 }; 3828 static int const sars_insn[4] = { 3829 OPC_UD2, OPC_PSRAW, OPC_PSRAD, OPC_VPSRAQ 3830 }; 3831 static int const vpshldi_insn[4] = { 3832 OPC_UD2, OPC_VPSHLDW, OPC_VPSHLDD, OPC_VPSHLDQ 3833 }; 3834 static int const vpshldv_insn[4] = { 3835 OPC_UD2, OPC_VPSHLDVW, OPC_VPSHLDVD, OPC_VPSHLDVQ 3836 }; 3837 static int const vpshrdv_insn[4] = { 3838 OPC_UD2, OPC_VPSHRDVW, OPC_VPSHRDVD, OPC_VPSHRDVQ 3839 }; 3840 static int const abs_insn[4] = { 3841 OPC_PABSB, OPC_PABSW, OPC_PABSD, OPC_VPABSQ 3842 }; 3843 3844 TCGType type = vecl + TCG_TYPE_V64; 3845 int insn, sub; 3846 TCGArg a0, a1, a2, a3; 3847 3848 a0 = args[0]; 3849 a1 = args[1]; 3850 a2 = args[2]; 3851 3852 switch (opc) { 3853 case INDEX_op_add_vec: 3854 insn = add_insn[vece]; 3855 goto gen_simd; 3856 case INDEX_op_ssadd_vec: 3857 insn = ssadd_insn[vece]; 3858 goto gen_simd; 3859 case INDEX_op_usadd_vec: 3860 insn = usadd_insn[vece]; 3861 goto gen_simd; 3862 case INDEX_op_sub_vec: 3863 insn = sub_insn[vece]; 3864 goto gen_simd; 3865 case INDEX_op_sssub_vec: 3866 insn = sssub_insn[vece]; 3867 goto gen_simd; 3868 case INDEX_op_ussub_vec: 3869 insn = ussub_insn[vece]; 3870 goto gen_simd; 3871 case INDEX_op_mul_vec: 3872 insn = mul_insn[vece]; 3873 goto gen_simd; 3874 case INDEX_op_and_vec: 3875 insn = OPC_PAND; 3876 goto gen_simd; 3877 case INDEX_op_or_vec: 3878 insn = OPC_POR; 3879 goto gen_simd; 3880 case INDEX_op_xor_vec: 3881 insn = OPC_PXOR; 3882 goto gen_simd; 3883 case INDEX_op_smin_vec: 3884 insn = smin_insn[vece]; 3885 goto gen_simd; 3886 case INDEX_op_umin_vec: 3887 insn = umin_insn[vece]; 3888 goto gen_simd; 3889 case INDEX_op_smax_vec: 3890 insn = smax_insn[vece]; 3891 goto gen_simd; 3892 case INDEX_op_umax_vec: 3893 insn = umax_insn[vece]; 3894 goto gen_simd; 3895 case INDEX_op_shlv_vec: 3896 insn = shlv_insn[vece]; 3897 goto gen_simd; 3898 case INDEX_op_shrv_vec: 3899 insn = shrv_insn[vece]; 3900 goto gen_simd; 3901 case INDEX_op_sarv_vec: 3902 insn = sarv_insn[vece]; 3903 goto gen_simd; 3904 case INDEX_op_rotlv_vec: 3905 insn = rotlv_insn[vece]; 3906 goto gen_simd; 3907 case INDEX_op_rotrv_vec: 3908 insn = rotrv_insn[vece]; 3909 goto gen_simd; 3910 case INDEX_op_shls_vec: 3911 insn = shls_insn[vece]; 3912 goto gen_simd; 3913 case INDEX_op_shrs_vec: 3914 insn = shrs_insn[vece]; 3915 goto gen_simd; 3916 case INDEX_op_sars_vec: 3917 insn = sars_insn[vece]; 3918 goto gen_simd; 3919 case INDEX_op_x86_punpckl_vec: 3920 insn = punpckl_insn[vece]; 3921 goto gen_simd; 3922 case INDEX_op_x86_punpckh_vec: 3923 insn = punpckh_insn[vece]; 3924 goto gen_simd; 3925 case INDEX_op_x86_packss_vec: 3926 insn = packss_insn[vece]; 3927 goto gen_simd; 3928 case INDEX_op_x86_packus_vec: 3929 insn = packus_insn[vece]; 3930 goto gen_simd; 3931 case INDEX_op_x86_vpshldv_vec: 3932 insn = vpshldv_insn[vece]; 3933 a1 = a2; 3934 a2 = args[3]; 3935 goto gen_simd; 3936 case INDEX_op_x86_vpshrdv_vec: 3937 insn = vpshrdv_insn[vece]; 3938 a1 = a2; 3939 a2 = args[3]; 3940 goto gen_simd; 3941#if TCG_TARGET_REG_BITS == 32 3942 case INDEX_op_dup2_vec: 3943 /* First merge the two 32-bit inputs to a single 64-bit element. */ 3944 tcg_out_vex_modrm(s, OPC_PUNPCKLDQ, a0, a1, a2); 3945 /* Then replicate the 64-bit elements across the rest of the vector. */ 3946 if (type != TCG_TYPE_V64) { 3947 tcg_out_dup_vec(s, type, MO_64, a0, a0); 3948 } 3949 break; 3950#endif 3951 case INDEX_op_abs_vec: 3952 insn = abs_insn[vece]; 3953 a2 = a1; 3954 a1 = 0; 3955 goto gen_simd; 3956 gen_simd: 3957 tcg_debug_assert(insn != OPC_UD2); 3958 tcg_out_vex_modrm_type(s, insn, a0, a1, a2, type); 3959 break; 3960 3961 case INDEX_op_cmp_vec: 3962 tcg_out_cmp_vec(s, type, vece, a0, a1, a2, args[3]); 3963 break; 3964 3965 case INDEX_op_cmpsel_vec: 3966 tcg_out_cmpsel_vec(s, type, vece, a0, a1, a2, 3967 args[3], args[4], args[5]); 3968 break; 3969 3970 case INDEX_op_andc_vec: 3971 insn = OPC_PANDN; 3972 tcg_out_vex_modrm_type(s, insn, a0, a2, a1, type); 3973 break; 3974 3975 case INDEX_op_shli_vec: 3976 insn = shift_imm_insn[vece]; 3977 sub = 6; 3978 goto gen_shift; 3979 case INDEX_op_shri_vec: 3980 insn = shift_imm_insn[vece]; 3981 sub = 2; 3982 goto gen_shift; 3983 case INDEX_op_sari_vec: 3984 if (vece == MO_64) { 3985 insn = OPC_PSHIFTD_Ib | P_VEXW | P_EVEX; 3986 } else { 3987 insn = shift_imm_insn[vece]; 3988 } 3989 sub = 4; 3990 goto gen_shift; 3991 case INDEX_op_rotli_vec: 3992 insn = OPC_PSHIFTD_Ib | P_EVEX; /* VPROL[DQ] */ 3993 if (vece == MO_64) { 3994 insn |= P_VEXW; 3995 } 3996 sub = 1; 3997 goto gen_shift; 3998 gen_shift: 3999 tcg_debug_assert(vece != MO_8); 4000 tcg_out_vex_modrm_type(s, insn, sub, a0, a1, type); 4001 tcg_out8(s, a2); 4002 break; 4003 4004 case INDEX_op_ld_vec: 4005 tcg_out_ld(s, type, a0, a1, a2); 4006 break; 4007 case INDEX_op_st_vec: 4008 tcg_out_st(s, type, a0, a1, a2); 4009 break; 4010 case INDEX_op_dupm_vec: 4011 tcg_out_dupm_vec(s, type, vece, a0, a1, a2); 4012 break; 4013 4014 case INDEX_op_x86_shufps_vec: 4015 insn = OPC_SHUFPS; 4016 sub = args[3]; 4017 goto gen_simd_imm8; 4018 case INDEX_op_x86_blend_vec: 4019 if (vece == MO_16) { 4020 insn = OPC_PBLENDW; 4021 } else if (vece == MO_32) { 4022 insn = (have_avx2 ? OPC_VPBLENDD : OPC_BLENDPS); 4023 } else { 4024 g_assert_not_reached(); 4025 } 4026 sub = args[3]; 4027 goto gen_simd_imm8; 4028 case INDEX_op_x86_vperm2i128_vec: 4029 insn = OPC_VPERM2I128; 4030 sub = args[3]; 4031 goto gen_simd_imm8; 4032 case INDEX_op_x86_vpshldi_vec: 4033 insn = vpshldi_insn[vece]; 4034 sub = args[3]; 4035 goto gen_simd_imm8; 4036 4037 case INDEX_op_not_vec: 4038 insn = OPC_VPTERNLOGQ; 4039 a2 = a1; 4040 sub = 0x33; /* !B */ 4041 goto gen_simd_imm8; 4042 case INDEX_op_nor_vec: 4043 insn = OPC_VPTERNLOGQ; 4044 sub = 0x11; /* norCB */ 4045 goto gen_simd_imm8; 4046 case INDEX_op_nand_vec: 4047 insn = OPC_VPTERNLOGQ; 4048 sub = 0x77; /* nandCB */ 4049 goto gen_simd_imm8; 4050 case INDEX_op_eqv_vec: 4051 insn = OPC_VPTERNLOGQ; 4052 sub = 0x99; /* xnorCB */ 4053 goto gen_simd_imm8; 4054 case INDEX_op_orc_vec: 4055 insn = OPC_VPTERNLOGQ; 4056 sub = 0xdd; /* orB!C */ 4057 goto gen_simd_imm8; 4058 4059 case INDEX_op_bitsel_vec: 4060 insn = OPC_VPTERNLOGQ; 4061 a3 = args[3]; 4062 if (a0 == a1) { 4063 a1 = a2; 4064 a2 = a3; 4065 sub = 0xca; /* A?B:C */ 4066 } else if (a0 == a2) { 4067 a2 = a3; 4068 sub = 0xe2; /* B?A:C */ 4069 } else { 4070 tcg_out_mov(s, type, a0, a3); 4071 sub = 0xb8; /* B?C:A */ 4072 } 4073 goto gen_simd_imm8; 4074 4075 gen_simd_imm8: 4076 tcg_debug_assert(insn != OPC_UD2); 4077 tcg_out_vex_modrm_type(s, insn, a0, a1, a2, type); 4078 tcg_out8(s, sub); 4079 break; 4080 4081 case INDEX_op_x86_psrldq_vec: 4082 tcg_out_vex_modrm(s, OPC_GRP14, 3, a0, a1); 4083 tcg_out8(s, a2); 4084 break; 4085 4086 case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ 4087 case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ 4088 default: 4089 g_assert_not_reached(); 4090 } 4091} 4092 4093static TCGConstraintSetIndex 4094tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) 4095{ 4096 switch (op) { 4097 case INDEX_op_goto_ptr: 4098 return C_O0_I1(r); 4099 4100 case INDEX_op_ld8u_i32: 4101 case INDEX_op_ld8u_i64: 4102 case INDEX_op_ld8s_i32: 4103 case INDEX_op_ld8s_i64: 4104 case INDEX_op_ld16u_i32: 4105 case INDEX_op_ld16u_i64: 4106 case INDEX_op_ld16s_i32: 4107 case INDEX_op_ld16s_i64: 4108 case INDEX_op_ld_i32: 4109 case INDEX_op_ld32u_i64: 4110 case INDEX_op_ld32s_i64: 4111 case INDEX_op_ld_i64: 4112 return C_O1_I1(r, r); 4113 4114 case INDEX_op_st8_i32: 4115 case INDEX_op_st8_i64: 4116 return C_O0_I2(qi, r); 4117 4118 case INDEX_op_st16_i32: 4119 case INDEX_op_st16_i64: 4120 case INDEX_op_st_i32: 4121 case INDEX_op_st32_i64: 4122 return C_O0_I2(ri, r); 4123 4124 case INDEX_op_st_i64: 4125 return C_O0_I2(re, r); 4126 4127 case INDEX_op_qemu_ld_i32: 4128 return C_O1_I1(r, L); 4129 4130 case INDEX_op_qemu_st_i32: 4131 return C_O0_I2(L, L); 4132 case INDEX_op_qemu_st8_i32: 4133 return C_O0_I2(s, L); 4134 4135 case INDEX_op_qemu_ld_i64: 4136 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L) : C_O2_I1(r, r, L); 4137 4138 case INDEX_op_qemu_st_i64: 4139 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(L, L) : C_O0_I3(L, L, L); 4140 4141 case INDEX_op_qemu_ld_i128: 4142 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 4143 return C_O2_I1(r, r, L); 4144 case INDEX_op_qemu_st_i128: 4145 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 4146 return C_O0_I3(L, L, L); 4147 4148 case INDEX_op_ld_vec: 4149 case INDEX_op_dupm_vec: 4150 return C_O1_I1(x, r); 4151 4152 case INDEX_op_st_vec: 4153 return C_O0_I2(x, r); 4154 4155 case INDEX_op_add_vec: 4156 case INDEX_op_sub_vec: 4157 case INDEX_op_mul_vec: 4158 case INDEX_op_and_vec: 4159 case INDEX_op_or_vec: 4160 case INDEX_op_xor_vec: 4161 case INDEX_op_andc_vec: 4162 case INDEX_op_orc_vec: 4163 case INDEX_op_nand_vec: 4164 case INDEX_op_nor_vec: 4165 case INDEX_op_eqv_vec: 4166 case INDEX_op_ssadd_vec: 4167 case INDEX_op_usadd_vec: 4168 case INDEX_op_sssub_vec: 4169 case INDEX_op_ussub_vec: 4170 case INDEX_op_smin_vec: 4171 case INDEX_op_umin_vec: 4172 case INDEX_op_smax_vec: 4173 case INDEX_op_umax_vec: 4174 case INDEX_op_shlv_vec: 4175 case INDEX_op_shrv_vec: 4176 case INDEX_op_sarv_vec: 4177 case INDEX_op_rotlv_vec: 4178 case INDEX_op_rotrv_vec: 4179 case INDEX_op_shls_vec: 4180 case INDEX_op_shrs_vec: 4181 case INDEX_op_sars_vec: 4182 case INDEX_op_cmp_vec: 4183 case INDEX_op_x86_shufps_vec: 4184 case INDEX_op_x86_blend_vec: 4185 case INDEX_op_x86_packss_vec: 4186 case INDEX_op_x86_packus_vec: 4187 case INDEX_op_x86_vperm2i128_vec: 4188 case INDEX_op_x86_punpckl_vec: 4189 case INDEX_op_x86_punpckh_vec: 4190 case INDEX_op_x86_vpshldi_vec: 4191#if TCG_TARGET_REG_BITS == 32 4192 case INDEX_op_dup2_vec: 4193#endif 4194 return C_O1_I2(x, x, x); 4195 4196 case INDEX_op_abs_vec: 4197 case INDEX_op_dup_vec: 4198 case INDEX_op_not_vec: 4199 case INDEX_op_shli_vec: 4200 case INDEX_op_shri_vec: 4201 case INDEX_op_sari_vec: 4202 case INDEX_op_rotli_vec: 4203 case INDEX_op_x86_psrldq_vec: 4204 return C_O1_I1(x, x); 4205 4206 case INDEX_op_x86_vpshldv_vec: 4207 case INDEX_op_x86_vpshrdv_vec: 4208 return C_O1_I3(x, 0, x, x); 4209 4210 case INDEX_op_bitsel_vec: 4211 return C_O1_I3(x, x, x, x); 4212 case INDEX_op_cmpsel_vec: 4213 return C_O1_I4(x, x, x, xO, x); 4214 4215 default: 4216 return C_NotImplemented; 4217 } 4218} 4219 4220int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 4221{ 4222 switch (opc) { 4223 case INDEX_op_add_vec: 4224 case INDEX_op_sub_vec: 4225 case INDEX_op_and_vec: 4226 case INDEX_op_or_vec: 4227 case INDEX_op_xor_vec: 4228 case INDEX_op_andc_vec: 4229 case INDEX_op_orc_vec: 4230 case INDEX_op_nand_vec: 4231 case INDEX_op_nor_vec: 4232 case INDEX_op_eqv_vec: 4233 case INDEX_op_not_vec: 4234 case INDEX_op_bitsel_vec: 4235 return 1; 4236 case INDEX_op_cmp_vec: 4237 case INDEX_op_cmpsel_vec: 4238 return -1; 4239 4240 case INDEX_op_rotli_vec: 4241 return have_avx512vl && vece >= MO_32 ? 1 : -1; 4242 4243 case INDEX_op_shli_vec: 4244 case INDEX_op_shri_vec: 4245 /* We must expand the operation for MO_8. */ 4246 return vece == MO_8 ? -1 : 1; 4247 4248 case INDEX_op_sari_vec: 4249 switch (vece) { 4250 case MO_8: 4251 return -1; 4252 case MO_16: 4253 case MO_32: 4254 return 1; 4255 case MO_64: 4256 if (have_avx512vl) { 4257 return 1; 4258 } 4259 /* 4260 * We can emulate this for MO_64, but it does not pay off 4261 * unless we're producing at least 4 values. 4262 */ 4263 return type >= TCG_TYPE_V256 ? -1 : 0; 4264 } 4265 return 0; 4266 4267 case INDEX_op_shls_vec: 4268 case INDEX_op_shrs_vec: 4269 return vece >= MO_16; 4270 case INDEX_op_sars_vec: 4271 switch (vece) { 4272 case MO_16: 4273 case MO_32: 4274 return 1; 4275 case MO_64: 4276 return have_avx512vl; 4277 } 4278 return 0; 4279 case INDEX_op_rotls_vec: 4280 return vece >= MO_16 ? -1 : 0; 4281 4282 case INDEX_op_shlv_vec: 4283 case INDEX_op_shrv_vec: 4284 switch (vece) { 4285 case MO_16: 4286 return have_avx512bw; 4287 case MO_32: 4288 case MO_64: 4289 return have_avx2; 4290 } 4291 return 0; 4292 case INDEX_op_sarv_vec: 4293 switch (vece) { 4294 case MO_16: 4295 return have_avx512bw; 4296 case MO_32: 4297 return have_avx2; 4298 case MO_64: 4299 return have_avx512vl; 4300 } 4301 return 0; 4302 case INDEX_op_rotlv_vec: 4303 case INDEX_op_rotrv_vec: 4304 switch (vece) { 4305 case MO_16: 4306 return have_avx512vbmi2 ? -1 : 0; 4307 case MO_32: 4308 case MO_64: 4309 return have_avx512vl ? 1 : have_avx2 ? -1 : 0; 4310 } 4311 return 0; 4312 4313 case INDEX_op_mul_vec: 4314 switch (vece) { 4315 case MO_8: 4316 return -1; 4317 case MO_64: 4318 return have_avx512dq; 4319 } 4320 return 1; 4321 4322 case INDEX_op_ssadd_vec: 4323 case INDEX_op_usadd_vec: 4324 case INDEX_op_sssub_vec: 4325 case INDEX_op_ussub_vec: 4326 return vece <= MO_16; 4327 case INDEX_op_smin_vec: 4328 case INDEX_op_smax_vec: 4329 case INDEX_op_umin_vec: 4330 case INDEX_op_umax_vec: 4331 case INDEX_op_abs_vec: 4332 return vece <= MO_32 || have_avx512vl; 4333 4334 default: 4335 return 0; 4336 } 4337} 4338 4339static void expand_vec_shi(TCGType type, unsigned vece, bool right, 4340 TCGv_vec v0, TCGv_vec v1, TCGArg imm) 4341{ 4342 uint8_t mask; 4343 4344 tcg_debug_assert(vece == MO_8); 4345 if (right) { 4346 mask = 0xff >> imm; 4347 tcg_gen_shri_vec(MO_16, v0, v1, imm); 4348 } else { 4349 mask = 0xff << imm; 4350 tcg_gen_shli_vec(MO_16, v0, v1, imm); 4351 } 4352 tcg_gen_and_vec(MO_8, v0, v0, tcg_constant_vec(type, MO_8, mask)); 4353} 4354 4355static void expand_vec_sari(TCGType type, unsigned vece, 4356 TCGv_vec v0, TCGv_vec v1, TCGArg imm) 4357{ 4358 TCGv_vec t1, t2; 4359 4360 switch (vece) { 4361 case MO_8: 4362 /* Unpack to 16-bit, shift, and repack. */ 4363 t1 = tcg_temp_new_vec(type); 4364 t2 = tcg_temp_new_vec(type); 4365 vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8, 4366 tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(v1)); 4367 vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8, 4368 tcgv_vec_arg(t2), tcgv_vec_arg(v1), tcgv_vec_arg(v1)); 4369 tcg_gen_sari_vec(MO_16, t1, t1, imm + 8); 4370 tcg_gen_sari_vec(MO_16, t2, t2, imm + 8); 4371 vec_gen_3(INDEX_op_x86_packss_vec, type, MO_8, 4372 tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t2)); 4373 tcg_temp_free_vec(t1); 4374 tcg_temp_free_vec(t2); 4375 break; 4376 4377 case MO_64: 4378 t1 = tcg_temp_new_vec(type); 4379 if (imm <= 32) { 4380 /* 4381 * We can emulate a small sign extend by performing an arithmetic 4382 * 32-bit shift and overwriting the high half of a 64-bit logical 4383 * shift. Note that the ISA says shift of 32 is valid, but TCG 4384 * does not, so we have to bound the smaller shift -- we get the 4385 * same result in the high half either way. 4386 */ 4387 tcg_gen_sari_vec(MO_32, t1, v1, MIN(imm, 31)); 4388 tcg_gen_shri_vec(MO_64, v0, v1, imm); 4389 vec_gen_4(INDEX_op_x86_blend_vec, type, MO_32, 4390 tcgv_vec_arg(v0), tcgv_vec_arg(v0), 4391 tcgv_vec_arg(t1), 0xaa); 4392 } else { 4393 /* Otherwise we will need to use a compare vs 0 to produce 4394 * the sign-extend, shift and merge. 4395 */ 4396 tcg_gen_cmp_vec(TCG_COND_GT, MO_64, t1, 4397 tcg_constant_vec(type, MO_64, 0), v1); 4398 tcg_gen_shri_vec(MO_64, v0, v1, imm); 4399 tcg_gen_shli_vec(MO_64, t1, t1, 64 - imm); 4400 tcg_gen_or_vec(MO_64, v0, v0, t1); 4401 } 4402 tcg_temp_free_vec(t1); 4403 break; 4404 4405 default: 4406 g_assert_not_reached(); 4407 } 4408} 4409 4410static void expand_vec_rotli(TCGType type, unsigned vece, 4411 TCGv_vec v0, TCGv_vec v1, TCGArg imm) 4412{ 4413 TCGv_vec t; 4414 4415 if (vece != MO_8 && have_avx512vbmi2) { 4416 vec_gen_4(INDEX_op_x86_vpshldi_vec, type, vece, 4417 tcgv_vec_arg(v0), tcgv_vec_arg(v1), tcgv_vec_arg(v1), imm); 4418 return; 4419 } 4420 4421 t = tcg_temp_new_vec(type); 4422 tcg_gen_shli_vec(vece, t, v1, imm); 4423 tcg_gen_shri_vec(vece, v0, v1, (8 << vece) - imm); 4424 tcg_gen_or_vec(vece, v0, v0, t); 4425 tcg_temp_free_vec(t); 4426} 4427 4428static void expand_vec_rotv(TCGType type, unsigned vece, TCGv_vec v0, 4429 TCGv_vec v1, TCGv_vec sh, bool right) 4430{ 4431 TCGv_vec t; 4432 4433 if (have_avx512vbmi2) { 4434 vec_gen_4(right ? INDEX_op_x86_vpshrdv_vec : INDEX_op_x86_vpshldv_vec, 4435 type, vece, tcgv_vec_arg(v0), tcgv_vec_arg(v1), 4436 tcgv_vec_arg(v1), tcgv_vec_arg(sh)); 4437 return; 4438 } 4439 4440 t = tcg_temp_new_vec(type); 4441 tcg_gen_dupi_vec(vece, t, 8 << vece); 4442 tcg_gen_sub_vec(vece, t, t, sh); 4443 if (right) { 4444 tcg_gen_shlv_vec(vece, t, v1, t); 4445 tcg_gen_shrv_vec(vece, v0, v1, sh); 4446 } else { 4447 tcg_gen_shrv_vec(vece, t, v1, t); 4448 tcg_gen_shlv_vec(vece, v0, v1, sh); 4449 } 4450 tcg_gen_or_vec(vece, v0, v0, t); 4451 tcg_temp_free_vec(t); 4452} 4453 4454static void expand_vec_rotls(TCGType type, unsigned vece, 4455 TCGv_vec v0, TCGv_vec v1, TCGv_i32 lsh) 4456{ 4457 TCGv_vec t = tcg_temp_new_vec(type); 4458 4459 tcg_debug_assert(vece != MO_8); 4460 4461 if (vece >= MO_32 ? have_avx512vl : have_avx512vbmi2) { 4462 tcg_gen_dup_i32_vec(vece, t, lsh); 4463 if (vece >= MO_32) { 4464 tcg_gen_rotlv_vec(vece, v0, v1, t); 4465 } else { 4466 expand_vec_rotv(type, vece, v0, v1, t, false); 4467 } 4468 } else { 4469 TCGv_i32 rsh = tcg_temp_new_i32(); 4470 4471 tcg_gen_neg_i32(rsh, lsh); 4472 tcg_gen_andi_i32(rsh, rsh, (8 << vece) - 1); 4473 tcg_gen_shls_vec(vece, t, v1, lsh); 4474 tcg_gen_shrs_vec(vece, v0, v1, rsh); 4475 tcg_gen_or_vec(vece, v0, v0, t); 4476 4477 tcg_temp_free_i32(rsh); 4478 } 4479 4480 tcg_temp_free_vec(t); 4481} 4482 4483static void expand_vec_mul(TCGType type, unsigned vece, 4484 TCGv_vec v0, TCGv_vec v1, TCGv_vec v2) 4485{ 4486 TCGv_vec t1, t2, t3, t4, zero; 4487 4488 tcg_debug_assert(vece == MO_8); 4489 4490 /* 4491 * Unpack v1 bytes to words, 0 | x. 4492 * Unpack v2 bytes to words, y | 0. 4493 * This leaves the 8-bit result, x * y, with 8 bits of right padding. 4494 * Shift logical right by 8 bits to clear the high 8 bytes before 4495 * using an unsigned saturated pack. 4496 * 4497 * The difference between the V64, V128 and V256 cases is merely how 4498 * we distribute the expansion between temporaries. 4499 */ 4500 switch (type) { 4501 case TCG_TYPE_V64: 4502 t1 = tcg_temp_new_vec(TCG_TYPE_V128); 4503 t2 = tcg_temp_new_vec(TCG_TYPE_V128); 4504 zero = tcg_constant_vec(TCG_TYPE_V128, MO_8, 0); 4505 vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_8, 4506 tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(zero)); 4507 vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_8, 4508 tcgv_vec_arg(t2), tcgv_vec_arg(zero), tcgv_vec_arg(v2)); 4509 tcg_gen_mul_vec(MO_16, t1, t1, t2); 4510 tcg_gen_shri_vec(MO_16, t1, t1, 8); 4511 vec_gen_3(INDEX_op_x86_packus_vec, TCG_TYPE_V128, MO_8, 4512 tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t1)); 4513 tcg_temp_free_vec(t1); 4514 tcg_temp_free_vec(t2); 4515 break; 4516 4517 case TCG_TYPE_V128: 4518 case TCG_TYPE_V256: 4519 t1 = tcg_temp_new_vec(type); 4520 t2 = tcg_temp_new_vec(type); 4521 t3 = tcg_temp_new_vec(type); 4522 t4 = tcg_temp_new_vec(type); 4523 zero = tcg_constant_vec(TCG_TYPE_V128, MO_8, 0); 4524 vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8, 4525 tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(zero)); 4526 vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8, 4527 tcgv_vec_arg(t2), tcgv_vec_arg(zero), tcgv_vec_arg(v2)); 4528 vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8, 4529 tcgv_vec_arg(t3), tcgv_vec_arg(v1), tcgv_vec_arg(zero)); 4530 vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8, 4531 tcgv_vec_arg(t4), tcgv_vec_arg(zero), tcgv_vec_arg(v2)); 4532 tcg_gen_mul_vec(MO_16, t1, t1, t2); 4533 tcg_gen_mul_vec(MO_16, t3, t3, t4); 4534 tcg_gen_shri_vec(MO_16, t1, t1, 8); 4535 tcg_gen_shri_vec(MO_16, t3, t3, 8); 4536 vec_gen_3(INDEX_op_x86_packus_vec, type, MO_8, 4537 tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t3)); 4538 tcg_temp_free_vec(t1); 4539 tcg_temp_free_vec(t2); 4540 tcg_temp_free_vec(t3); 4541 tcg_temp_free_vec(t4); 4542 break; 4543 4544 default: 4545 g_assert_not_reached(); 4546 } 4547} 4548 4549static TCGCond expand_vec_cond(TCGType type, unsigned vece, 4550 TCGArg *a1, TCGArg *a2, TCGCond cond) 4551{ 4552 /* 4553 * Without AVX512, there are no 64-bit unsigned comparisons. 4554 * We must bias the inputs so that they become signed. 4555 * All other swapping and inversion are handled during code generation. 4556 */ 4557 if (vece == MO_64 && !have_avx512dq && is_unsigned_cond(cond)) { 4558 TCGv_vec v1 = temp_tcgv_vec(arg_temp(*a1)); 4559 TCGv_vec v2 = temp_tcgv_vec(arg_temp(*a2)); 4560 TCGv_vec t1 = tcg_temp_new_vec(type); 4561 TCGv_vec t2 = tcg_temp_new_vec(type); 4562 TCGv_vec t3 = tcg_constant_vec(type, vece, 1ull << ((8 << vece) - 1)); 4563 4564 tcg_gen_sub_vec(vece, t1, v1, t3); 4565 tcg_gen_sub_vec(vece, t2, v2, t3); 4566 *a1 = tcgv_vec_arg(t1); 4567 *a2 = tcgv_vec_arg(t2); 4568 cond = tcg_signed_cond(cond); 4569 } 4570 return cond; 4571} 4572 4573static void expand_vec_cmp(TCGType type, unsigned vece, TCGArg a0, 4574 TCGArg a1, TCGArg a2, TCGCond cond) 4575{ 4576 cond = expand_vec_cond(type, vece, &a1, &a2, cond); 4577 /* Expand directly; do not recurse. */ 4578 vec_gen_4(INDEX_op_cmp_vec, type, vece, a0, a1, a2, cond); 4579} 4580 4581static void expand_vec_cmpsel(TCGType type, unsigned vece, TCGArg a0, 4582 TCGArg a1, TCGArg a2, 4583 TCGArg a3, TCGArg a4, TCGCond cond) 4584{ 4585 cond = expand_vec_cond(type, vece, &a1, &a2, cond); 4586 /* Expand directly; do not recurse. */ 4587 vec_gen_6(INDEX_op_cmpsel_vec, type, vece, a0, a1, a2, a3, a4, cond); 4588} 4589 4590void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 4591 TCGArg a0, ...) 4592{ 4593 va_list va; 4594 TCGArg a1, a2, a3, a4, a5; 4595 TCGv_vec v0, v1, v2; 4596 4597 va_start(va, a0); 4598 a1 = va_arg(va, TCGArg); 4599 a2 = va_arg(va, TCGArg); 4600 v0 = temp_tcgv_vec(arg_temp(a0)); 4601 v1 = temp_tcgv_vec(arg_temp(a1)); 4602 4603 switch (opc) { 4604 case INDEX_op_shli_vec: 4605 expand_vec_shi(type, vece, false, v0, v1, a2); 4606 break; 4607 case INDEX_op_shri_vec: 4608 expand_vec_shi(type, vece, true, v0, v1, a2); 4609 break; 4610 case INDEX_op_sari_vec: 4611 expand_vec_sari(type, vece, v0, v1, a2); 4612 break; 4613 4614 case INDEX_op_rotli_vec: 4615 expand_vec_rotli(type, vece, v0, v1, a2); 4616 break; 4617 4618 case INDEX_op_rotls_vec: 4619 expand_vec_rotls(type, vece, v0, v1, temp_tcgv_i32(arg_temp(a2))); 4620 break; 4621 4622 case INDEX_op_rotlv_vec: 4623 v2 = temp_tcgv_vec(arg_temp(a2)); 4624 expand_vec_rotv(type, vece, v0, v1, v2, false); 4625 break; 4626 case INDEX_op_rotrv_vec: 4627 v2 = temp_tcgv_vec(arg_temp(a2)); 4628 expand_vec_rotv(type, vece, v0, v1, v2, true); 4629 break; 4630 4631 case INDEX_op_mul_vec: 4632 v2 = temp_tcgv_vec(arg_temp(a2)); 4633 expand_vec_mul(type, vece, v0, v1, v2); 4634 break; 4635 4636 case INDEX_op_cmp_vec: 4637 a3 = va_arg(va, TCGArg); 4638 expand_vec_cmp(type, vece, a0, a1, a2, a3); 4639 break; 4640 4641 case INDEX_op_cmpsel_vec: 4642 a3 = va_arg(va, TCGArg); 4643 a4 = va_arg(va, TCGArg); 4644 a5 = va_arg(va, TCGArg); 4645 expand_vec_cmpsel(type, vece, a0, a1, a2, a3, a4, a5); 4646 break; 4647 4648 default: 4649 break; 4650 } 4651 4652 va_end(va); 4653} 4654 4655static const int tcg_target_callee_save_regs[] = { 4656#if TCG_TARGET_REG_BITS == 64 4657 TCG_REG_RBP, 4658 TCG_REG_RBX, 4659#if defined(_WIN64) 4660 TCG_REG_RDI, 4661 TCG_REG_RSI, 4662#endif 4663 TCG_REG_R12, 4664 TCG_REG_R13, 4665 TCG_REG_R14, /* Currently used for the global env. */ 4666 TCG_REG_R15, 4667#else 4668 TCG_REG_EBP, /* Currently used for the global env. */ 4669 TCG_REG_EBX, 4670 TCG_REG_ESI, 4671 TCG_REG_EDI, 4672#endif 4673}; 4674 4675/* Compute frame size via macros, to share between tcg_target_qemu_prologue 4676 and tcg_register_jit. */ 4677 4678#define PUSH_SIZE \ 4679 ((1 + ARRAY_SIZE(tcg_target_callee_save_regs)) \ 4680 * (TCG_TARGET_REG_BITS / 8)) 4681 4682#define FRAME_SIZE \ 4683 ((PUSH_SIZE \ 4684 + TCG_STATIC_CALL_ARGS_SIZE \ 4685 + CPU_TEMP_BUF_NLONGS * sizeof(long) \ 4686 + TCG_TARGET_STACK_ALIGN - 1) \ 4687 & ~(TCG_TARGET_STACK_ALIGN - 1)) 4688 4689/* Generate global QEMU prologue and epilogue code */ 4690static void tcg_target_qemu_prologue(TCGContext *s) 4691{ 4692 int i, stack_addend; 4693 4694 /* TB prologue */ 4695 4696 /* Reserve some stack space, also for TCG temps. */ 4697 stack_addend = FRAME_SIZE - PUSH_SIZE; 4698 tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE, 4699 CPU_TEMP_BUF_NLONGS * sizeof(long)); 4700 4701 /* Save all callee saved registers. */ 4702 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 4703 tcg_out_push(s, tcg_target_callee_save_regs[i]); 4704 } 4705 4706 if (!tcg_use_softmmu && guest_base) { 4707 int seg = setup_guest_base_seg(); 4708 if (seg != 0) { 4709 x86_guest_base.seg = seg; 4710 } else if (guest_base == (int32_t)guest_base) { 4711 x86_guest_base.ofs = guest_base; 4712 } else { 4713 assert(TCG_TARGET_REG_BITS == 64); 4714 /* Choose R12 because, as a base, it requires a SIB byte. */ 4715 x86_guest_base.index = TCG_REG_R12; 4716 tcg_out_movi(s, TCG_TYPE_PTR, x86_guest_base.index, guest_base); 4717 tcg_regset_set_reg(s->reserved_regs, x86_guest_base.index); 4718 } 4719 } 4720 4721 if (TCG_TARGET_REG_BITS == 32) { 4722 tcg_out_ld(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, 4723 (ARRAY_SIZE(tcg_target_callee_save_regs) + 1) * 4); 4724 tcg_out_addi(s, TCG_REG_ESP, -stack_addend); 4725 /* jmp *tb. */ 4726 tcg_out_modrm_offset(s, OPC_GRP5, EXT5_JMPN_Ev, TCG_REG_ESP, 4727 (ARRAY_SIZE(tcg_target_callee_save_regs) + 2) * 4 4728 + stack_addend); 4729 } else { 4730 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 4731 tcg_out_addi(s, TCG_REG_ESP, -stack_addend); 4732 /* jmp *tb. */ 4733 tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, tcg_target_call_iarg_regs[1]); 4734 } 4735 4736 /* 4737 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 4738 * and fall through to the rest of the epilogue. 4739 */ 4740 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 4741 tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_EAX, 0); 4742 4743 /* TB epilogue */ 4744 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 4745 4746 tcg_out_addi(s, TCG_REG_CALL_STACK, stack_addend); 4747 4748 if (have_avx2) { 4749 tcg_out_vex_opc(s, OPC_VZEROUPPER, 0, 0, 0, 0); 4750 } 4751 for (i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) { 4752 tcg_out_pop(s, tcg_target_callee_save_regs[i]); 4753 } 4754 tcg_out_opc(s, OPC_RET, 0, 0, 0); 4755} 4756 4757static void tcg_out_tb_start(TCGContext *s) 4758{ 4759 /* nothing to do */ 4760} 4761 4762static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 4763{ 4764 memset(p, 0x90, count); 4765} 4766 4767static void tcg_target_init(TCGContext *s) 4768{ 4769 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS; 4770 if (TCG_TARGET_REG_BITS == 64) { 4771 tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS; 4772 } 4773 if (have_avx1) { 4774 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS; 4775 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS; 4776 } 4777 if (have_avx2) { 4778 tcg_target_available_regs[TCG_TYPE_V256] = ALL_VECTOR_REGS; 4779 } 4780 4781 tcg_target_call_clobber_regs = ALL_VECTOR_REGS; 4782 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_EAX); 4783 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_EDX); 4784 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_ECX); 4785 if (TCG_TARGET_REG_BITS == 64) { 4786#if !defined(_WIN64) 4787 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_RDI); 4788 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_RSI); 4789#endif 4790 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8); 4791 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9); 4792 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10); 4793 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11); 4794 } 4795 4796 s->reserved_regs = 0; 4797 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); 4798 tcg_regset_set_reg(s->reserved_regs, TCG_TMP_VEC); 4799#ifdef _WIN64 4800 /* These are call saved, and we don't save them, so don't use them. */ 4801 tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM6); 4802 tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM7); 4803 tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM8); 4804 tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM9); 4805 tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM10); 4806 tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM11); 4807 tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM12); 4808 tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM13); 4809 tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM14); 4810 tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM15); 4811#endif 4812} 4813 4814typedef struct { 4815 DebugFrameHeader h; 4816 uint8_t fde_def_cfa[4]; 4817 uint8_t fde_reg_ofs[14]; 4818} DebugFrame; 4819 4820/* We're expecting a 2 byte uleb128 encoded value. */ 4821QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); 4822 4823#if !defined(__ELF__) 4824 /* Host machine without ELF. */ 4825#elif TCG_TARGET_REG_BITS == 64 4826#define ELF_HOST_MACHINE EM_X86_64 4827static const DebugFrame debug_frame = { 4828 .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ 4829 .h.cie.id = -1, 4830 .h.cie.version = 1, 4831 .h.cie.code_align = 1, 4832 .h.cie.data_align = 0x78, /* sleb128 -8 */ 4833 .h.cie.return_column = 16, 4834 4835 /* Total FDE size does not include the "len" member. */ 4836 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 4837 4838 .fde_def_cfa = { 4839 12, 7, /* DW_CFA_def_cfa %rsp, ... */ 4840 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 4841 (FRAME_SIZE >> 7) 4842 }, 4843 .fde_reg_ofs = { 4844 0x90, 1, /* DW_CFA_offset, %rip, -8 */ 4845 /* The following ordering must match tcg_target_callee_save_regs. */ 4846 0x86, 2, /* DW_CFA_offset, %rbp, -16 */ 4847 0x83, 3, /* DW_CFA_offset, %rbx, -24 */ 4848 0x8c, 4, /* DW_CFA_offset, %r12, -32 */ 4849 0x8d, 5, /* DW_CFA_offset, %r13, -40 */ 4850 0x8e, 6, /* DW_CFA_offset, %r14, -48 */ 4851 0x8f, 7, /* DW_CFA_offset, %r15, -56 */ 4852 } 4853}; 4854#else 4855#define ELF_HOST_MACHINE EM_386 4856static const DebugFrame debug_frame = { 4857 .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ 4858 .h.cie.id = -1, 4859 .h.cie.version = 1, 4860 .h.cie.code_align = 1, 4861 .h.cie.data_align = 0x7c, /* sleb128 -4 */ 4862 .h.cie.return_column = 8, 4863 4864 /* Total FDE size does not include the "len" member. */ 4865 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 4866 4867 .fde_def_cfa = { 4868 12, 4, /* DW_CFA_def_cfa %esp, ... */ 4869 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 4870 (FRAME_SIZE >> 7) 4871 }, 4872 .fde_reg_ofs = { 4873 0x88, 1, /* DW_CFA_offset, %eip, -4 */ 4874 /* The following ordering must match tcg_target_callee_save_regs. */ 4875 0x85, 2, /* DW_CFA_offset, %ebp, -8 */ 4876 0x83, 3, /* DW_CFA_offset, %ebx, -12 */ 4877 0x86, 4, /* DW_CFA_offset, %esi, -16 */ 4878 0x87, 5, /* DW_CFA_offset, %edi, -20 */ 4879 } 4880}; 4881#endif 4882 4883#if defined(ELF_HOST_MACHINE) 4884void tcg_register_jit(const void *buf, size_t buf_size) 4885{ 4886 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 4887} 4888#endif 4889