1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25#include "../tcg-ldst.c.inc" 26#include "../tcg-pool.c.inc" 27 28#ifdef CONFIG_DEBUG_TCG 29static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 30#if TCG_TARGET_REG_BITS == 64 31 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", 32#else 33 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", 34#endif 35 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", 36 "%xmm0", "%xmm1", "%xmm2", "%xmm3", "%xmm4", "%xmm5", "%xmm6", "%xmm7", 37#if TCG_TARGET_REG_BITS == 64 38 "%xmm8", "%xmm9", "%xmm10", "%xmm11", 39 "%xmm12", "%xmm13", "%xmm14", "%xmm15", 40#endif 41}; 42#endif 43 44static const int tcg_target_reg_alloc_order[] = { 45#if TCG_TARGET_REG_BITS == 64 46 TCG_REG_RBP, 47 TCG_REG_RBX, 48 TCG_REG_R12, 49 TCG_REG_R13, 50 TCG_REG_R14, 51 TCG_REG_R15, 52 TCG_REG_R10, 53 TCG_REG_R11, 54 TCG_REG_R9, 55 TCG_REG_R8, 56 TCG_REG_RCX, 57 TCG_REG_RDX, 58 TCG_REG_RSI, 59 TCG_REG_RDI, 60 TCG_REG_RAX, 61#else 62 TCG_REG_EBX, 63 TCG_REG_ESI, 64 TCG_REG_EDI, 65 TCG_REG_EBP, 66 TCG_REG_ECX, 67 TCG_REG_EDX, 68 TCG_REG_EAX, 69#endif 70 TCG_REG_XMM0, 71 TCG_REG_XMM1, 72 TCG_REG_XMM2, 73 TCG_REG_XMM3, 74 TCG_REG_XMM4, 75 TCG_REG_XMM5, 76#ifndef _WIN64 77 /* The Win64 ABI has xmm6-xmm15 as caller-saves, and we do not save 78 any of them. Therefore only allow xmm0-xmm5 to be allocated. */ 79 TCG_REG_XMM6, 80 TCG_REG_XMM7, 81#if TCG_TARGET_REG_BITS == 64 82 TCG_REG_XMM8, 83 TCG_REG_XMM9, 84 TCG_REG_XMM10, 85 TCG_REG_XMM11, 86 TCG_REG_XMM12, 87 TCG_REG_XMM13, 88 TCG_REG_XMM14, 89 TCG_REG_XMM15, 90#endif 91#endif 92}; 93 94#define TCG_TMP_VEC TCG_REG_XMM5 95 96static const int tcg_target_call_iarg_regs[] = { 97#if TCG_TARGET_REG_BITS == 64 98#if defined(_WIN64) 99 TCG_REG_RCX, 100 TCG_REG_RDX, 101#else 102 TCG_REG_RDI, 103 TCG_REG_RSI, 104 TCG_REG_RDX, 105 TCG_REG_RCX, 106#endif 107 TCG_REG_R8, 108 TCG_REG_R9, 109#else 110 /* 32 bit mode uses stack based calling convention (GCC default). */ 111#endif 112}; 113 114static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 115{ 116 switch (kind) { 117 case TCG_CALL_RET_NORMAL: 118 tcg_debug_assert(slot >= 0 && slot <= 1); 119 return slot ? TCG_REG_EDX : TCG_REG_EAX; 120#ifdef _WIN64 121 case TCG_CALL_RET_BY_VEC: 122 tcg_debug_assert(slot == 0); 123 return TCG_REG_XMM0; 124#endif 125 default: 126 g_assert_not_reached(); 127 } 128} 129 130/* Constants we accept. */ 131#define TCG_CT_CONST_S32 0x100 132#define TCG_CT_CONST_U32 0x200 133#define TCG_CT_CONST_I32 0x400 134#define TCG_CT_CONST_WSZ 0x800 135 136/* Registers used with L constraint, which are the first argument 137 registers on x86_64, and two random call clobbered registers on 138 i386. */ 139#if TCG_TARGET_REG_BITS == 64 140# define TCG_REG_L0 tcg_target_call_iarg_regs[0] 141# define TCG_REG_L1 tcg_target_call_iarg_regs[1] 142#else 143# define TCG_REG_L0 TCG_REG_EAX 144# define TCG_REG_L1 TCG_REG_EDX 145#endif 146 147#if TCG_TARGET_REG_BITS == 64 148# define ALL_GENERAL_REGS 0x0000ffffu 149# define ALL_VECTOR_REGS 0xffff0000u 150# define ALL_BYTEL_REGS ALL_GENERAL_REGS 151#else 152# define ALL_GENERAL_REGS 0x000000ffu 153# define ALL_VECTOR_REGS 0x00ff0000u 154# define ALL_BYTEL_REGS 0x0000000fu 155#endif 156#ifdef CONFIG_SOFTMMU 157# define SOFTMMU_RESERVE_REGS ((1 << TCG_REG_L0) | (1 << TCG_REG_L1)) 158#else 159# define SOFTMMU_RESERVE_REGS 0 160#endif 161 162/* For 64-bit, we always know that CMOV is available. */ 163#if TCG_TARGET_REG_BITS == 64 164# define have_cmov true 165#else 166# define have_cmov (cpuinfo & CPUINFO_CMOV) 167#endif 168#define have_bmi2 (cpuinfo & CPUINFO_BMI2) 169#define have_lzcnt (cpuinfo & CPUINFO_LZCNT) 170 171static const tcg_insn_unit *tb_ret_addr; 172 173static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 174 intptr_t value, intptr_t addend) 175{ 176 value += addend; 177 switch(type) { 178 case R_386_PC32: 179 value -= (uintptr_t)tcg_splitwx_to_rx(code_ptr); 180 if (value != (int32_t)value) { 181 return false; 182 } 183 /* FALLTHRU */ 184 case R_386_32: 185 tcg_patch32(code_ptr, value); 186 break; 187 case R_386_PC8: 188 value -= (uintptr_t)tcg_splitwx_to_rx(code_ptr); 189 if (value != (int8_t)value) { 190 return false; 191 } 192 tcg_patch8(code_ptr, value); 193 break; 194 default: 195 g_assert_not_reached(); 196 } 197 return true; 198} 199 200/* test if a constant matches the constraint */ 201static bool tcg_target_const_match(int64_t val, TCGType type, int ct) 202{ 203 if (ct & TCG_CT_CONST) { 204 return 1; 205 } 206 if (type == TCG_TYPE_I32) { 207 if (ct & (TCG_CT_CONST_S32 | TCG_CT_CONST_U32 | TCG_CT_CONST_I32)) { 208 return 1; 209 } 210 } else { 211 if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) { 212 return 1; 213 } 214 if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) { 215 return 1; 216 } 217 if ((ct & TCG_CT_CONST_I32) && ~val == (int32_t)~val) { 218 return 1; 219 } 220 } 221 if ((ct & TCG_CT_CONST_WSZ) && val == (type == TCG_TYPE_I32 ? 32 : 64)) { 222 return 1; 223 } 224 return 0; 225} 226 227# define LOWREGMASK(x) ((x) & 7) 228 229#define P_EXT 0x100 /* 0x0f opcode prefix */ 230#define P_EXT38 0x200 /* 0x0f 0x38 opcode prefix */ 231#define P_DATA16 0x400 /* 0x66 opcode prefix */ 232#define P_VEXW 0x1000 /* Set VEX.W = 1 */ 233#if TCG_TARGET_REG_BITS == 64 234# define P_REXW P_VEXW /* Set REX.W = 1; match VEXW */ 235# define P_REXB_R 0x2000 /* REG field as byte register */ 236# define P_REXB_RM 0x4000 /* R/M field as byte register */ 237# define P_GS 0x8000 /* gs segment override */ 238#else 239# define P_REXW 0 240# define P_REXB_R 0 241# define P_REXB_RM 0 242# define P_GS 0 243#endif 244#define P_EXT3A 0x10000 /* 0x0f 0x3a opcode prefix */ 245#define P_SIMDF3 0x20000 /* 0xf3 opcode prefix */ 246#define P_SIMDF2 0x40000 /* 0xf2 opcode prefix */ 247#define P_VEXL 0x80000 /* Set VEX.L = 1 */ 248#define P_EVEX 0x100000 /* Requires EVEX encoding */ 249 250#define OPC_ARITH_EvIz (0x81) 251#define OPC_ARITH_EvIb (0x83) 252#define OPC_ARITH_GvEv (0x03) /* ... plus (ARITH_FOO << 3) */ 253#define OPC_ANDN (0xf2 | P_EXT38) 254#define OPC_ADD_GvEv (OPC_ARITH_GvEv | (ARITH_ADD << 3)) 255#define OPC_AND_GvEv (OPC_ARITH_GvEv | (ARITH_AND << 3)) 256#define OPC_BLENDPS (0x0c | P_EXT3A | P_DATA16) 257#define OPC_BSF (0xbc | P_EXT) 258#define OPC_BSR (0xbd | P_EXT) 259#define OPC_BSWAP (0xc8 | P_EXT) 260#define OPC_CALL_Jz (0xe8) 261#define OPC_CMOVCC (0x40 | P_EXT) /* ... plus condition code */ 262#define OPC_CMP_GvEv (OPC_ARITH_GvEv | (ARITH_CMP << 3)) 263#define OPC_DEC_r32 (0x48) 264#define OPC_IMUL_GvEv (0xaf | P_EXT) 265#define OPC_IMUL_GvEvIb (0x6b) 266#define OPC_IMUL_GvEvIz (0x69) 267#define OPC_INC_r32 (0x40) 268#define OPC_JCC_long (0x80 | P_EXT) /* ... plus condition code */ 269#define OPC_JCC_short (0x70) /* ... plus condition code */ 270#define OPC_JMP_long (0xe9) 271#define OPC_JMP_short (0xeb) 272#define OPC_LEA (0x8d) 273#define OPC_LZCNT (0xbd | P_EXT | P_SIMDF3) 274#define OPC_MOVB_EvGv (0x88) /* stores, more or less */ 275#define OPC_MOVL_EvGv (0x89) /* stores, more or less */ 276#define OPC_MOVL_GvEv (0x8b) /* loads, more or less */ 277#define OPC_MOVB_EvIz (0xc6) 278#define OPC_MOVL_EvIz (0xc7) 279#define OPC_MOVB_Ib (0xb0) 280#define OPC_MOVL_Iv (0xb8) 281#define OPC_MOVBE_GyMy (0xf0 | P_EXT38) 282#define OPC_MOVBE_MyGy (0xf1 | P_EXT38) 283#define OPC_MOVD_VyEy (0x6e | P_EXT | P_DATA16) 284#define OPC_MOVD_EyVy (0x7e | P_EXT | P_DATA16) 285#define OPC_MOVDDUP (0x12 | P_EXT | P_SIMDF2) 286#define OPC_MOVDQA_VxWx (0x6f | P_EXT | P_DATA16) 287#define OPC_MOVDQA_WxVx (0x7f | P_EXT | P_DATA16) 288#define OPC_MOVDQU_VxWx (0x6f | P_EXT | P_SIMDF3) 289#define OPC_MOVDQU_WxVx (0x7f | P_EXT | P_SIMDF3) 290#define OPC_MOVQ_VqWq (0x7e | P_EXT | P_SIMDF3) 291#define OPC_MOVQ_WqVq (0xd6 | P_EXT | P_DATA16) 292#define OPC_MOVSBL (0xbe | P_EXT) 293#define OPC_MOVSWL (0xbf | P_EXT) 294#define OPC_MOVSLQ (0x63 | P_REXW) 295#define OPC_MOVZBL (0xb6 | P_EXT) 296#define OPC_MOVZWL (0xb7 | P_EXT) 297#define OPC_PABSB (0x1c | P_EXT38 | P_DATA16) 298#define OPC_PABSW (0x1d | P_EXT38 | P_DATA16) 299#define OPC_PABSD (0x1e | P_EXT38 | P_DATA16) 300#define OPC_VPABSQ (0x1f | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 301#define OPC_PACKSSDW (0x6b | P_EXT | P_DATA16) 302#define OPC_PACKSSWB (0x63 | P_EXT | P_DATA16) 303#define OPC_PACKUSDW (0x2b | P_EXT38 | P_DATA16) 304#define OPC_PACKUSWB (0x67 | P_EXT | P_DATA16) 305#define OPC_PADDB (0xfc | P_EXT | P_DATA16) 306#define OPC_PADDW (0xfd | P_EXT | P_DATA16) 307#define OPC_PADDD (0xfe | P_EXT | P_DATA16) 308#define OPC_PADDQ (0xd4 | P_EXT | P_DATA16) 309#define OPC_PADDSB (0xec | P_EXT | P_DATA16) 310#define OPC_PADDSW (0xed | P_EXT | P_DATA16) 311#define OPC_PADDUB (0xdc | P_EXT | P_DATA16) 312#define OPC_PADDUW (0xdd | P_EXT | P_DATA16) 313#define OPC_PAND (0xdb | P_EXT | P_DATA16) 314#define OPC_PANDN (0xdf | P_EXT | P_DATA16) 315#define OPC_PBLENDW (0x0e | P_EXT3A | P_DATA16) 316#define OPC_PCMPEQB (0x74 | P_EXT | P_DATA16) 317#define OPC_PCMPEQW (0x75 | P_EXT | P_DATA16) 318#define OPC_PCMPEQD (0x76 | P_EXT | P_DATA16) 319#define OPC_PCMPEQQ (0x29 | P_EXT38 | P_DATA16) 320#define OPC_PCMPGTB (0x64 | P_EXT | P_DATA16) 321#define OPC_PCMPGTW (0x65 | P_EXT | P_DATA16) 322#define OPC_PCMPGTD (0x66 | P_EXT | P_DATA16) 323#define OPC_PCMPGTQ (0x37 | P_EXT38 | P_DATA16) 324#define OPC_PEXTRD (0x16 | P_EXT3A | P_DATA16) 325#define OPC_PINSRD (0x22 | P_EXT3A | P_DATA16) 326#define OPC_PMAXSB (0x3c | P_EXT38 | P_DATA16) 327#define OPC_PMAXSW (0xee | P_EXT | P_DATA16) 328#define OPC_PMAXSD (0x3d | P_EXT38 | P_DATA16) 329#define OPC_VPMAXSQ (0x3d | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 330#define OPC_PMAXUB (0xde | P_EXT | P_DATA16) 331#define OPC_PMAXUW (0x3e | P_EXT38 | P_DATA16) 332#define OPC_PMAXUD (0x3f | P_EXT38 | P_DATA16) 333#define OPC_VPMAXUQ (0x3f | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 334#define OPC_PMINSB (0x38 | P_EXT38 | P_DATA16) 335#define OPC_PMINSW (0xea | P_EXT | P_DATA16) 336#define OPC_PMINSD (0x39 | P_EXT38 | P_DATA16) 337#define OPC_VPMINSQ (0x39 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 338#define OPC_PMINUB (0xda | P_EXT | P_DATA16) 339#define OPC_PMINUW (0x3a | P_EXT38 | P_DATA16) 340#define OPC_PMINUD (0x3b | P_EXT38 | P_DATA16) 341#define OPC_VPMINUQ (0x3b | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 342#define OPC_PMOVSXBW (0x20 | P_EXT38 | P_DATA16) 343#define OPC_PMOVSXWD (0x23 | P_EXT38 | P_DATA16) 344#define OPC_PMOVSXDQ (0x25 | P_EXT38 | P_DATA16) 345#define OPC_PMOVZXBW (0x30 | P_EXT38 | P_DATA16) 346#define OPC_PMOVZXWD (0x33 | P_EXT38 | P_DATA16) 347#define OPC_PMOVZXDQ (0x35 | P_EXT38 | P_DATA16) 348#define OPC_PMULLW (0xd5 | P_EXT | P_DATA16) 349#define OPC_PMULLD (0x40 | P_EXT38 | P_DATA16) 350#define OPC_VPMULLQ (0x40 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 351#define OPC_POR (0xeb | P_EXT | P_DATA16) 352#define OPC_PSHUFB (0x00 | P_EXT38 | P_DATA16) 353#define OPC_PSHUFD (0x70 | P_EXT | P_DATA16) 354#define OPC_PSHUFLW (0x70 | P_EXT | P_SIMDF2) 355#define OPC_PSHUFHW (0x70 | P_EXT | P_SIMDF3) 356#define OPC_PSHIFTW_Ib (0x71 | P_EXT | P_DATA16) /* /2 /6 /4 */ 357#define OPC_PSHIFTD_Ib (0x72 | P_EXT | P_DATA16) /* /1 /2 /6 /4 */ 358#define OPC_PSHIFTQ_Ib (0x73 | P_EXT | P_DATA16) /* /2 /6 /4 */ 359#define OPC_PSLLW (0xf1 | P_EXT | P_DATA16) 360#define OPC_PSLLD (0xf2 | P_EXT | P_DATA16) 361#define OPC_PSLLQ (0xf3 | P_EXT | P_DATA16) 362#define OPC_PSRAW (0xe1 | P_EXT | P_DATA16) 363#define OPC_PSRAD (0xe2 | P_EXT | P_DATA16) 364#define OPC_VPSRAQ (0xe2 | P_EXT | P_DATA16 | P_VEXW | P_EVEX) 365#define OPC_PSRLW (0xd1 | P_EXT | P_DATA16) 366#define OPC_PSRLD (0xd2 | P_EXT | P_DATA16) 367#define OPC_PSRLQ (0xd3 | P_EXT | P_DATA16) 368#define OPC_PSUBB (0xf8 | P_EXT | P_DATA16) 369#define OPC_PSUBW (0xf9 | P_EXT | P_DATA16) 370#define OPC_PSUBD (0xfa | P_EXT | P_DATA16) 371#define OPC_PSUBQ (0xfb | P_EXT | P_DATA16) 372#define OPC_PSUBSB (0xe8 | P_EXT | P_DATA16) 373#define OPC_PSUBSW (0xe9 | P_EXT | P_DATA16) 374#define OPC_PSUBUB (0xd8 | P_EXT | P_DATA16) 375#define OPC_PSUBUW (0xd9 | P_EXT | P_DATA16) 376#define OPC_PUNPCKLBW (0x60 | P_EXT | P_DATA16) 377#define OPC_PUNPCKLWD (0x61 | P_EXT | P_DATA16) 378#define OPC_PUNPCKLDQ (0x62 | P_EXT | P_DATA16) 379#define OPC_PUNPCKLQDQ (0x6c | P_EXT | P_DATA16) 380#define OPC_PUNPCKHBW (0x68 | P_EXT | P_DATA16) 381#define OPC_PUNPCKHWD (0x69 | P_EXT | P_DATA16) 382#define OPC_PUNPCKHDQ (0x6a | P_EXT | P_DATA16) 383#define OPC_PUNPCKHQDQ (0x6d | P_EXT | P_DATA16) 384#define OPC_PXOR (0xef | P_EXT | P_DATA16) 385#define OPC_POP_r32 (0x58) 386#define OPC_POPCNT (0xb8 | P_EXT | P_SIMDF3) 387#define OPC_PUSH_r32 (0x50) 388#define OPC_PUSH_Iv (0x68) 389#define OPC_PUSH_Ib (0x6a) 390#define OPC_RET (0xc3) 391#define OPC_SETCC (0x90 | P_EXT | P_REXB_RM) /* ... plus cc */ 392#define OPC_SHIFT_1 (0xd1) 393#define OPC_SHIFT_Ib (0xc1) 394#define OPC_SHIFT_cl (0xd3) 395#define OPC_SARX (0xf7 | P_EXT38 | P_SIMDF3) 396#define OPC_SHUFPS (0xc6 | P_EXT) 397#define OPC_SHLX (0xf7 | P_EXT38 | P_DATA16) 398#define OPC_SHRX (0xf7 | P_EXT38 | P_SIMDF2) 399#define OPC_SHRD_Ib (0xac | P_EXT) 400#define OPC_TESTL (0x85) 401#define OPC_TZCNT (0xbc | P_EXT | P_SIMDF3) 402#define OPC_UD2 (0x0b | P_EXT) 403#define OPC_VPBLENDD (0x02 | P_EXT3A | P_DATA16) 404#define OPC_VPBLENDVB (0x4c | P_EXT3A | P_DATA16) 405#define OPC_VPINSRB (0x20 | P_EXT3A | P_DATA16) 406#define OPC_VPINSRW (0xc4 | P_EXT | P_DATA16) 407#define OPC_VBROADCASTSS (0x18 | P_EXT38 | P_DATA16) 408#define OPC_VBROADCASTSD (0x19 | P_EXT38 | P_DATA16) 409#define OPC_VPBROADCASTB (0x78 | P_EXT38 | P_DATA16) 410#define OPC_VPBROADCASTW (0x79 | P_EXT38 | P_DATA16) 411#define OPC_VPBROADCASTD (0x58 | P_EXT38 | P_DATA16) 412#define OPC_VPBROADCASTQ (0x59 | P_EXT38 | P_DATA16) 413#define OPC_VPERMQ (0x00 | P_EXT3A | P_DATA16 | P_VEXW) 414#define OPC_VPERM2I128 (0x46 | P_EXT3A | P_DATA16 | P_VEXL) 415#define OPC_VPROLVD (0x15 | P_EXT38 | P_DATA16 | P_EVEX) 416#define OPC_VPROLVQ (0x15 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 417#define OPC_VPRORVD (0x14 | P_EXT38 | P_DATA16 | P_EVEX) 418#define OPC_VPRORVQ (0x14 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 419#define OPC_VPSHLDW (0x70 | P_EXT3A | P_DATA16 | P_VEXW | P_EVEX) 420#define OPC_VPSHLDD (0x71 | P_EXT3A | P_DATA16 | P_EVEX) 421#define OPC_VPSHLDQ (0x71 | P_EXT3A | P_DATA16 | P_VEXW | P_EVEX) 422#define OPC_VPSHLDVW (0x70 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 423#define OPC_VPSHLDVD (0x71 | P_EXT38 | P_DATA16 | P_EVEX) 424#define OPC_VPSHLDVQ (0x71 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 425#define OPC_VPSHRDVW (0x72 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 426#define OPC_VPSHRDVD (0x73 | P_EXT38 | P_DATA16 | P_EVEX) 427#define OPC_VPSHRDVQ (0x73 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 428#define OPC_VPSLLVW (0x12 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 429#define OPC_VPSLLVD (0x47 | P_EXT38 | P_DATA16) 430#define OPC_VPSLLVQ (0x47 | P_EXT38 | P_DATA16 | P_VEXW) 431#define OPC_VPSRAVW (0x11 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 432#define OPC_VPSRAVD (0x46 | P_EXT38 | P_DATA16) 433#define OPC_VPSRAVQ (0x46 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 434#define OPC_VPSRLVW (0x10 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 435#define OPC_VPSRLVD (0x45 | P_EXT38 | P_DATA16) 436#define OPC_VPSRLVQ (0x45 | P_EXT38 | P_DATA16 | P_VEXW) 437#define OPC_VPTERNLOGQ (0x25 | P_EXT3A | P_DATA16 | P_VEXW | P_EVEX) 438#define OPC_VZEROUPPER (0x77 | P_EXT) 439#define OPC_XCHG_ax_r32 (0x90) 440#define OPC_XCHG_EvGv (0x87) 441 442#define OPC_GRP3_Eb (0xf6) 443#define OPC_GRP3_Ev (0xf7) 444#define OPC_GRP5 (0xff) 445#define OPC_GRP14 (0x73 | P_EXT | P_DATA16) 446 447/* Group 1 opcode extensions for 0x80-0x83. 448 These are also used as modifiers for OPC_ARITH. */ 449#define ARITH_ADD 0 450#define ARITH_OR 1 451#define ARITH_ADC 2 452#define ARITH_SBB 3 453#define ARITH_AND 4 454#define ARITH_SUB 5 455#define ARITH_XOR 6 456#define ARITH_CMP 7 457 458/* Group 2 opcode extensions for 0xc0, 0xc1, 0xd0-0xd3. */ 459#define SHIFT_ROL 0 460#define SHIFT_ROR 1 461#define SHIFT_SHL 4 462#define SHIFT_SHR 5 463#define SHIFT_SAR 7 464 465/* Group 3 opcode extensions for 0xf6, 0xf7. To be used with OPC_GRP3. */ 466#define EXT3_TESTi 0 467#define EXT3_NOT 2 468#define EXT3_NEG 3 469#define EXT3_MUL 4 470#define EXT3_IMUL 5 471#define EXT3_DIV 6 472#define EXT3_IDIV 7 473 474/* Group 5 opcode extensions for 0xff. To be used with OPC_GRP5. */ 475#define EXT5_INC_Ev 0 476#define EXT5_DEC_Ev 1 477#define EXT5_CALLN_Ev 2 478#define EXT5_JMPN_Ev 4 479 480/* Condition codes to be added to OPC_JCC_{long,short}. */ 481#define JCC_JMP (-1) 482#define JCC_JO 0x0 483#define JCC_JNO 0x1 484#define JCC_JB 0x2 485#define JCC_JAE 0x3 486#define JCC_JE 0x4 487#define JCC_JNE 0x5 488#define JCC_JBE 0x6 489#define JCC_JA 0x7 490#define JCC_JS 0x8 491#define JCC_JNS 0x9 492#define JCC_JP 0xa 493#define JCC_JNP 0xb 494#define JCC_JL 0xc 495#define JCC_JGE 0xd 496#define JCC_JLE 0xe 497#define JCC_JG 0xf 498 499static const uint8_t tcg_cond_to_jcc[] = { 500 [TCG_COND_EQ] = JCC_JE, 501 [TCG_COND_NE] = JCC_JNE, 502 [TCG_COND_LT] = JCC_JL, 503 [TCG_COND_GE] = JCC_JGE, 504 [TCG_COND_LE] = JCC_JLE, 505 [TCG_COND_GT] = JCC_JG, 506 [TCG_COND_LTU] = JCC_JB, 507 [TCG_COND_GEU] = JCC_JAE, 508 [TCG_COND_LEU] = JCC_JBE, 509 [TCG_COND_GTU] = JCC_JA, 510}; 511 512#if TCG_TARGET_REG_BITS == 64 513static void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x) 514{ 515 int rex; 516 517 if (opc & P_GS) { 518 tcg_out8(s, 0x65); 519 } 520 if (opc & P_DATA16) { 521 /* We should never be asking for both 16 and 64-bit operation. */ 522 tcg_debug_assert((opc & P_REXW) == 0); 523 tcg_out8(s, 0x66); 524 } 525 if (opc & P_SIMDF3) { 526 tcg_out8(s, 0xf3); 527 } else if (opc & P_SIMDF2) { 528 tcg_out8(s, 0xf2); 529 } 530 531 rex = 0; 532 rex |= (opc & P_REXW) ? 0x8 : 0x0; /* REX.W */ 533 rex |= (r & 8) >> 1; /* REX.R */ 534 rex |= (x & 8) >> 2; /* REX.X */ 535 rex |= (rm & 8) >> 3; /* REX.B */ 536 537 /* P_REXB_{R,RM} indicates that the given register is the low byte. 538 For %[abcd]l we need no REX prefix, but for %{si,di,bp,sp}l we do, 539 as otherwise the encoding indicates %[abcd]h. Note that the values 540 that are ORed in merely indicate that the REX byte must be present; 541 those bits get discarded in output. */ 542 rex |= opc & (r >= 4 ? P_REXB_R : 0); 543 rex |= opc & (rm >= 4 ? P_REXB_RM : 0); 544 545 if (rex) { 546 tcg_out8(s, (uint8_t)(rex | 0x40)); 547 } 548 549 if (opc & (P_EXT | P_EXT38 | P_EXT3A)) { 550 tcg_out8(s, 0x0f); 551 if (opc & P_EXT38) { 552 tcg_out8(s, 0x38); 553 } else if (opc & P_EXT3A) { 554 tcg_out8(s, 0x3a); 555 } 556 } 557 558 tcg_out8(s, opc); 559} 560#else 561static void tcg_out_opc(TCGContext *s, int opc) 562{ 563 if (opc & P_DATA16) { 564 tcg_out8(s, 0x66); 565 } 566 if (opc & P_SIMDF3) { 567 tcg_out8(s, 0xf3); 568 } else if (opc & P_SIMDF2) { 569 tcg_out8(s, 0xf2); 570 } 571 if (opc & (P_EXT | P_EXT38 | P_EXT3A)) { 572 tcg_out8(s, 0x0f); 573 if (opc & P_EXT38) { 574 tcg_out8(s, 0x38); 575 } else if (opc & P_EXT3A) { 576 tcg_out8(s, 0x3a); 577 } 578 } 579 tcg_out8(s, opc); 580} 581/* Discard the register arguments to tcg_out_opc early, so as not to penalize 582 the 32-bit compilation paths. This method works with all versions of gcc, 583 whereas relying on optimization may not be able to exclude them. */ 584#define tcg_out_opc(s, opc, r, rm, x) (tcg_out_opc)(s, opc) 585#endif 586 587static void tcg_out_modrm(TCGContext *s, int opc, int r, int rm) 588{ 589 tcg_out_opc(s, opc, r, rm, 0); 590 tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm)); 591} 592 593static void tcg_out_vex_opc(TCGContext *s, int opc, int r, int v, 594 int rm, int index) 595{ 596 int tmp; 597 598 if (opc & P_GS) { 599 tcg_out8(s, 0x65); 600 } 601 /* Use the two byte form if possible, which cannot encode 602 VEX.W, VEX.B, VEX.X, or an m-mmmm field other than P_EXT. */ 603 if ((opc & (P_EXT | P_EXT38 | P_EXT3A | P_VEXW)) == P_EXT 604 && ((rm | index) & 8) == 0) { 605 /* Two byte VEX prefix. */ 606 tcg_out8(s, 0xc5); 607 608 tmp = (r & 8 ? 0 : 0x80); /* VEX.R */ 609 } else { 610 /* Three byte VEX prefix. */ 611 tcg_out8(s, 0xc4); 612 613 /* VEX.m-mmmm */ 614 if (opc & P_EXT3A) { 615 tmp = 3; 616 } else if (opc & P_EXT38) { 617 tmp = 2; 618 } else if (opc & P_EXT) { 619 tmp = 1; 620 } else { 621 g_assert_not_reached(); 622 } 623 tmp |= (r & 8 ? 0 : 0x80); /* VEX.R */ 624 tmp |= (index & 8 ? 0 : 0x40); /* VEX.X */ 625 tmp |= (rm & 8 ? 0 : 0x20); /* VEX.B */ 626 tcg_out8(s, tmp); 627 628 tmp = (opc & P_VEXW ? 0x80 : 0); /* VEX.W */ 629 } 630 631 tmp |= (opc & P_VEXL ? 0x04 : 0); /* VEX.L */ 632 /* VEX.pp */ 633 if (opc & P_DATA16) { 634 tmp |= 1; /* 0x66 */ 635 } else if (opc & P_SIMDF3) { 636 tmp |= 2; /* 0xf3 */ 637 } else if (opc & P_SIMDF2) { 638 tmp |= 3; /* 0xf2 */ 639 } 640 tmp |= (~v & 15) << 3; /* VEX.vvvv */ 641 tcg_out8(s, tmp); 642 tcg_out8(s, opc); 643} 644 645static void tcg_out_evex_opc(TCGContext *s, int opc, int r, int v, 646 int rm, int index) 647{ 648 /* The entire 4-byte evex prefix; with R' and V' set. */ 649 uint32_t p = 0x08041062; 650 int mm, pp; 651 652 tcg_debug_assert(have_avx512vl); 653 654 /* EVEX.mm */ 655 if (opc & P_EXT3A) { 656 mm = 3; 657 } else if (opc & P_EXT38) { 658 mm = 2; 659 } else if (opc & P_EXT) { 660 mm = 1; 661 } else { 662 g_assert_not_reached(); 663 } 664 665 /* EVEX.pp */ 666 if (opc & P_DATA16) { 667 pp = 1; /* 0x66 */ 668 } else if (opc & P_SIMDF3) { 669 pp = 2; /* 0xf3 */ 670 } else if (opc & P_SIMDF2) { 671 pp = 3; /* 0xf2 */ 672 } else { 673 pp = 0; 674 } 675 676 p = deposit32(p, 8, 2, mm); 677 p = deposit32(p, 13, 1, (rm & 8) == 0); /* EVEX.RXB.B */ 678 p = deposit32(p, 14, 1, (index & 8) == 0); /* EVEX.RXB.X */ 679 p = deposit32(p, 15, 1, (r & 8) == 0); /* EVEX.RXB.R */ 680 p = deposit32(p, 16, 2, pp); 681 p = deposit32(p, 19, 4, ~v); 682 p = deposit32(p, 23, 1, (opc & P_VEXW) != 0); 683 p = deposit32(p, 29, 2, (opc & P_VEXL) != 0); 684 685 tcg_out32(s, p); 686 tcg_out8(s, opc); 687} 688 689static void tcg_out_vex_modrm(TCGContext *s, int opc, int r, int v, int rm) 690{ 691 if (opc & P_EVEX) { 692 tcg_out_evex_opc(s, opc, r, v, rm, 0); 693 } else { 694 tcg_out_vex_opc(s, opc, r, v, rm, 0); 695 } 696 tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm)); 697} 698 699/* Output an opcode with a full "rm + (index<<shift) + offset" address mode. 700 We handle either RM and INDEX missing with a negative value. In 64-bit 701 mode for absolute addresses, ~RM is the size of the immediate operand 702 that will follow the instruction. */ 703 704static void tcg_out_sib_offset(TCGContext *s, int r, int rm, int index, 705 int shift, intptr_t offset) 706{ 707 int mod, len; 708 709 if (index < 0 && rm < 0) { 710 if (TCG_TARGET_REG_BITS == 64) { 711 /* Try for a rip-relative addressing mode. This has replaced 712 the 32-bit-mode absolute addressing encoding. */ 713 intptr_t pc = (intptr_t)s->code_ptr + 5 + ~rm; 714 intptr_t disp = offset - pc; 715 if (disp == (int32_t)disp) { 716 tcg_out8(s, (LOWREGMASK(r) << 3) | 5); 717 tcg_out32(s, disp); 718 return; 719 } 720 721 /* Try for an absolute address encoding. This requires the 722 use of the MODRM+SIB encoding and is therefore larger than 723 rip-relative addressing. */ 724 if (offset == (int32_t)offset) { 725 tcg_out8(s, (LOWREGMASK(r) << 3) | 4); 726 tcg_out8(s, (4 << 3) | 5); 727 tcg_out32(s, offset); 728 return; 729 } 730 731 /* ??? The memory isn't directly addressable. */ 732 g_assert_not_reached(); 733 } else { 734 /* Absolute address. */ 735 tcg_out8(s, (r << 3) | 5); 736 tcg_out32(s, offset); 737 return; 738 } 739 } 740 741 /* Find the length of the immediate addend. Note that the encoding 742 that would be used for (%ebp) indicates absolute addressing. */ 743 if (rm < 0) { 744 mod = 0, len = 4, rm = 5; 745 } else if (offset == 0 && LOWREGMASK(rm) != TCG_REG_EBP) { 746 mod = 0, len = 0; 747 } else if (offset == (int8_t)offset) { 748 mod = 0x40, len = 1; 749 } else { 750 mod = 0x80, len = 4; 751 } 752 753 /* Use a single byte MODRM format if possible. Note that the encoding 754 that would be used for %esp is the escape to the two byte form. */ 755 if (index < 0 && LOWREGMASK(rm) != TCG_REG_ESP) { 756 /* Single byte MODRM format. */ 757 tcg_out8(s, mod | (LOWREGMASK(r) << 3) | LOWREGMASK(rm)); 758 } else { 759 /* Two byte MODRM+SIB format. */ 760 761 /* Note that the encoding that would place %esp into the index 762 field indicates no index register. In 64-bit mode, the REX.X 763 bit counts, so %r12 can be used as the index. */ 764 if (index < 0) { 765 index = 4; 766 } else { 767 tcg_debug_assert(index != TCG_REG_ESP); 768 } 769 770 tcg_out8(s, mod | (LOWREGMASK(r) << 3) | 4); 771 tcg_out8(s, (shift << 6) | (LOWREGMASK(index) << 3) | LOWREGMASK(rm)); 772 } 773 774 if (len == 1) { 775 tcg_out8(s, offset); 776 } else if (len == 4) { 777 tcg_out32(s, offset); 778 } 779} 780 781static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm, 782 int index, int shift, intptr_t offset) 783{ 784 tcg_out_opc(s, opc, r, rm < 0 ? 0 : rm, index < 0 ? 0 : index); 785 tcg_out_sib_offset(s, r, rm, index, shift, offset); 786} 787 788static void tcg_out_vex_modrm_sib_offset(TCGContext *s, int opc, int r, int v, 789 int rm, int index, int shift, 790 intptr_t offset) 791{ 792 tcg_out_vex_opc(s, opc, r, v, rm < 0 ? 0 : rm, index < 0 ? 0 : index); 793 tcg_out_sib_offset(s, r, rm, index, shift, offset); 794} 795 796/* A simplification of the above with no index or shift. */ 797static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, 798 int rm, intptr_t offset) 799{ 800 tcg_out_modrm_sib_offset(s, opc, r, rm, -1, 0, offset); 801} 802 803static inline void tcg_out_vex_modrm_offset(TCGContext *s, int opc, int r, 804 int v, int rm, intptr_t offset) 805{ 806 tcg_out_vex_modrm_sib_offset(s, opc, r, v, rm, -1, 0, offset); 807} 808 809/* Output an opcode with an expected reference to the constant pool. */ 810static inline void tcg_out_modrm_pool(TCGContext *s, int opc, int r) 811{ 812 tcg_out_opc(s, opc, r, 0, 0); 813 /* Absolute for 32-bit, pc-relative for 64-bit. */ 814 tcg_out8(s, LOWREGMASK(r) << 3 | 5); 815 tcg_out32(s, 0); 816} 817 818/* Output an opcode with an expected reference to the constant pool. */ 819static inline void tcg_out_vex_modrm_pool(TCGContext *s, int opc, int r) 820{ 821 tcg_out_vex_opc(s, opc, r, 0, 0, 0); 822 /* Absolute for 32-bit, pc-relative for 64-bit. */ 823 tcg_out8(s, LOWREGMASK(r) << 3 | 5); 824 tcg_out32(s, 0); 825} 826 827/* Generate dest op= src. Uses the same ARITH_* codes as tgen_arithi. */ 828static inline void tgen_arithr(TCGContext *s, int subop, int dest, int src) 829{ 830 /* Propagate an opcode prefix, such as P_REXW. */ 831 int ext = subop & ~0x7; 832 subop &= 0x7; 833 834 tcg_out_modrm(s, OPC_ARITH_GvEv + (subop << 3) + ext, dest, src); 835} 836 837static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 838{ 839 int rexw = 0; 840 841 if (arg == ret) { 842 return true; 843 } 844 switch (type) { 845 case TCG_TYPE_I64: 846 rexw = P_REXW; 847 /* fallthru */ 848 case TCG_TYPE_I32: 849 if (ret < 16) { 850 if (arg < 16) { 851 tcg_out_modrm(s, OPC_MOVL_GvEv + rexw, ret, arg); 852 } else { 853 tcg_out_vex_modrm(s, OPC_MOVD_EyVy + rexw, arg, 0, ret); 854 } 855 } else { 856 if (arg < 16) { 857 tcg_out_vex_modrm(s, OPC_MOVD_VyEy + rexw, ret, 0, arg); 858 } else { 859 tcg_out_vex_modrm(s, OPC_MOVQ_VqWq, ret, 0, arg); 860 } 861 } 862 break; 863 864 case TCG_TYPE_V64: 865 tcg_debug_assert(ret >= 16 && arg >= 16); 866 tcg_out_vex_modrm(s, OPC_MOVQ_VqWq, ret, 0, arg); 867 break; 868 case TCG_TYPE_V128: 869 tcg_debug_assert(ret >= 16 && arg >= 16); 870 tcg_out_vex_modrm(s, OPC_MOVDQA_VxWx, ret, 0, arg); 871 break; 872 case TCG_TYPE_V256: 873 tcg_debug_assert(ret >= 16 && arg >= 16); 874 tcg_out_vex_modrm(s, OPC_MOVDQA_VxWx | P_VEXL, ret, 0, arg); 875 break; 876 877 default: 878 g_assert_not_reached(); 879 } 880 return true; 881} 882 883static const int avx2_dup_insn[4] = { 884 OPC_VPBROADCASTB, OPC_VPBROADCASTW, 885 OPC_VPBROADCASTD, OPC_VPBROADCASTQ, 886}; 887 888static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 889 TCGReg r, TCGReg a) 890{ 891 if (have_avx2) { 892 int vex_l = (type == TCG_TYPE_V256 ? P_VEXL : 0); 893 tcg_out_vex_modrm(s, avx2_dup_insn[vece] + vex_l, r, 0, a); 894 } else { 895 switch (vece) { 896 case MO_8: 897 /* ??? With zero in a register, use PSHUFB. */ 898 tcg_out_vex_modrm(s, OPC_PUNPCKLBW, r, a, a); 899 a = r; 900 /* FALLTHRU */ 901 case MO_16: 902 tcg_out_vex_modrm(s, OPC_PUNPCKLWD, r, a, a); 903 a = r; 904 /* FALLTHRU */ 905 case MO_32: 906 tcg_out_vex_modrm(s, OPC_PSHUFD, r, 0, a); 907 /* imm8 operand: all output lanes selected from input lane 0. */ 908 tcg_out8(s, 0); 909 break; 910 case MO_64: 911 tcg_out_vex_modrm(s, OPC_PUNPCKLQDQ, r, a, a); 912 break; 913 default: 914 g_assert_not_reached(); 915 } 916 } 917 return true; 918} 919 920static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 921 TCGReg r, TCGReg base, intptr_t offset) 922{ 923 if (have_avx2) { 924 int vex_l = (type == TCG_TYPE_V256 ? P_VEXL : 0); 925 tcg_out_vex_modrm_offset(s, avx2_dup_insn[vece] + vex_l, 926 r, 0, base, offset); 927 } else { 928 switch (vece) { 929 case MO_64: 930 tcg_out_vex_modrm_offset(s, OPC_MOVDDUP, r, 0, base, offset); 931 break; 932 case MO_32: 933 tcg_out_vex_modrm_offset(s, OPC_VBROADCASTSS, r, 0, base, offset); 934 break; 935 case MO_16: 936 tcg_out_vex_modrm_offset(s, OPC_VPINSRW, r, r, base, offset); 937 tcg_out8(s, 0); /* imm8 */ 938 tcg_out_dup_vec(s, type, vece, r, r); 939 break; 940 case MO_8: 941 tcg_out_vex_modrm_offset(s, OPC_VPINSRB, r, r, base, offset); 942 tcg_out8(s, 0); /* imm8 */ 943 tcg_out_dup_vec(s, type, vece, r, r); 944 break; 945 default: 946 g_assert_not_reached(); 947 } 948 } 949 return true; 950} 951 952static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 953 TCGReg ret, int64_t arg) 954{ 955 int vex_l = (type == TCG_TYPE_V256 ? P_VEXL : 0); 956 957 if (arg == 0) { 958 tcg_out_vex_modrm(s, OPC_PXOR, ret, ret, ret); 959 return; 960 } 961 if (arg == -1) { 962 tcg_out_vex_modrm(s, OPC_PCMPEQB + vex_l, ret, ret, ret); 963 return; 964 } 965 966 if (TCG_TARGET_REG_BITS == 32 && vece < MO_64) { 967 if (have_avx2) { 968 tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTD + vex_l, ret); 969 } else { 970 tcg_out_vex_modrm_pool(s, OPC_VBROADCASTSS, ret); 971 } 972 new_pool_label(s, arg, R_386_32, s->code_ptr - 4, 0); 973 } else { 974 if (type == TCG_TYPE_V64) { 975 tcg_out_vex_modrm_pool(s, OPC_MOVQ_VqWq, ret); 976 } else if (have_avx2) { 977 tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTQ + vex_l, ret); 978 } else { 979 tcg_out_vex_modrm_pool(s, OPC_MOVDDUP, ret); 980 } 981 if (TCG_TARGET_REG_BITS == 64) { 982 new_pool_label(s, arg, R_386_PC32, s->code_ptr - 4, -4); 983 } else { 984 new_pool_l2(s, R_386_32, s->code_ptr - 4, 0, arg, arg >> 32); 985 } 986 } 987} 988 989static void tcg_out_movi_vec(TCGContext *s, TCGType type, 990 TCGReg ret, tcg_target_long arg) 991{ 992 if (arg == 0) { 993 tcg_out_vex_modrm(s, OPC_PXOR, ret, ret, ret); 994 return; 995 } 996 if (arg == -1) { 997 tcg_out_vex_modrm(s, OPC_PCMPEQB, ret, ret, ret); 998 return; 999 } 1000 1001 int rexw = (type == TCG_TYPE_I32 ? 0 : P_REXW); 1002 tcg_out_vex_modrm_pool(s, OPC_MOVD_VyEy + rexw, ret); 1003 if (TCG_TARGET_REG_BITS == 64) { 1004 new_pool_label(s, arg, R_386_PC32, s->code_ptr - 4, -4); 1005 } else { 1006 new_pool_label(s, arg, R_386_32, s->code_ptr - 4, 0); 1007 } 1008} 1009 1010static void tcg_out_movi_int(TCGContext *s, TCGType type, 1011 TCGReg ret, tcg_target_long arg) 1012{ 1013 tcg_target_long diff; 1014 1015 if (arg == 0) { 1016 tgen_arithr(s, ARITH_XOR, ret, ret); 1017 return; 1018 } 1019 if (arg == (uint32_t)arg || type == TCG_TYPE_I32) { 1020 tcg_out_opc(s, OPC_MOVL_Iv + LOWREGMASK(ret), 0, ret, 0); 1021 tcg_out32(s, arg); 1022 return; 1023 } 1024 if (arg == (int32_t)arg) { 1025 tcg_out_modrm(s, OPC_MOVL_EvIz + P_REXW, 0, ret); 1026 tcg_out32(s, arg); 1027 return; 1028 } 1029 1030 /* Try a 7 byte pc-relative lea before the 10 byte movq. */ 1031 diff = tcg_pcrel_diff(s, (const void *)arg) - 7; 1032 if (diff == (int32_t)diff) { 1033 tcg_out_opc(s, OPC_LEA | P_REXW, ret, 0, 0); 1034 tcg_out8(s, (LOWREGMASK(ret) << 3) | 5); 1035 tcg_out32(s, diff); 1036 return; 1037 } 1038 1039 tcg_out_opc(s, OPC_MOVL_Iv + P_REXW + LOWREGMASK(ret), 0, ret, 0); 1040 tcg_out64(s, arg); 1041} 1042 1043static void tcg_out_movi(TCGContext *s, TCGType type, 1044 TCGReg ret, tcg_target_long arg) 1045{ 1046 switch (type) { 1047 case TCG_TYPE_I32: 1048#if TCG_TARGET_REG_BITS == 64 1049 case TCG_TYPE_I64: 1050#endif 1051 if (ret < 16) { 1052 tcg_out_movi_int(s, type, ret, arg); 1053 } else { 1054 tcg_out_movi_vec(s, type, ret, arg); 1055 } 1056 break; 1057 default: 1058 g_assert_not_reached(); 1059 } 1060} 1061 1062static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 1063{ 1064 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 1065 tcg_out_modrm(s, OPC_XCHG_EvGv + rexw, r1, r2); 1066 return true; 1067} 1068 1069static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 1070 tcg_target_long imm) 1071{ 1072 /* This function is only used for passing structs by reference. */ 1073 tcg_debug_assert(imm == (int32_t)imm); 1074 tcg_out_modrm_offset(s, OPC_LEA | P_REXW, rd, rs, imm); 1075} 1076 1077static inline void tcg_out_pushi(TCGContext *s, tcg_target_long val) 1078{ 1079 if (val == (int8_t)val) { 1080 tcg_out_opc(s, OPC_PUSH_Ib, 0, 0, 0); 1081 tcg_out8(s, val); 1082 } else if (val == (int32_t)val) { 1083 tcg_out_opc(s, OPC_PUSH_Iv, 0, 0, 0); 1084 tcg_out32(s, val); 1085 } else { 1086 g_assert_not_reached(); 1087 } 1088} 1089 1090static inline void tcg_out_mb(TCGContext *s, TCGArg a0) 1091{ 1092 /* Given the strength of x86 memory ordering, we only need care for 1093 store-load ordering. Experimentally, "lock orl $0,0(%esp)" is 1094 faster than "mfence", so don't bother with the sse insn. */ 1095 if (a0 & TCG_MO_ST_LD) { 1096 tcg_out8(s, 0xf0); 1097 tcg_out_modrm_offset(s, OPC_ARITH_EvIb, ARITH_OR, TCG_REG_ESP, 0); 1098 tcg_out8(s, 0); 1099 } 1100} 1101 1102static inline void tcg_out_push(TCGContext *s, int reg) 1103{ 1104 tcg_out_opc(s, OPC_PUSH_r32 + LOWREGMASK(reg), 0, reg, 0); 1105} 1106 1107static inline void tcg_out_pop(TCGContext *s, int reg) 1108{ 1109 tcg_out_opc(s, OPC_POP_r32 + LOWREGMASK(reg), 0, reg, 0); 1110} 1111 1112static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, 1113 TCGReg arg1, intptr_t arg2) 1114{ 1115 switch (type) { 1116 case TCG_TYPE_I32: 1117 if (ret < 16) { 1118 tcg_out_modrm_offset(s, OPC_MOVL_GvEv, ret, arg1, arg2); 1119 } else { 1120 tcg_out_vex_modrm_offset(s, OPC_MOVD_VyEy, ret, 0, arg1, arg2); 1121 } 1122 break; 1123 case TCG_TYPE_I64: 1124 if (ret < 16) { 1125 tcg_out_modrm_offset(s, OPC_MOVL_GvEv | P_REXW, ret, arg1, arg2); 1126 break; 1127 } 1128 /* FALLTHRU */ 1129 case TCG_TYPE_V64: 1130 /* There is no instruction that can validate 8-byte alignment. */ 1131 tcg_debug_assert(ret >= 16); 1132 tcg_out_vex_modrm_offset(s, OPC_MOVQ_VqWq, ret, 0, arg1, arg2); 1133 break; 1134 case TCG_TYPE_V128: 1135 /* 1136 * The gvec infrastructure is asserts that v128 vector loads 1137 * and stores use a 16-byte aligned offset. Validate that the 1138 * final pointer is aligned by using an insn that will SIGSEGV. 1139 */ 1140 tcg_debug_assert(ret >= 16); 1141 tcg_out_vex_modrm_offset(s, OPC_MOVDQA_VxWx, ret, 0, arg1, arg2); 1142 break; 1143 case TCG_TYPE_V256: 1144 /* 1145 * The gvec infrastructure only requires 16-byte alignment, 1146 * so here we must use an unaligned load. 1147 */ 1148 tcg_debug_assert(ret >= 16); 1149 tcg_out_vex_modrm_offset(s, OPC_MOVDQU_VxWx | P_VEXL, 1150 ret, 0, arg1, arg2); 1151 break; 1152 default: 1153 g_assert_not_reached(); 1154 } 1155} 1156 1157static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 1158 TCGReg arg1, intptr_t arg2) 1159{ 1160 switch (type) { 1161 case TCG_TYPE_I32: 1162 if (arg < 16) { 1163 tcg_out_modrm_offset(s, OPC_MOVL_EvGv, arg, arg1, arg2); 1164 } else { 1165 tcg_out_vex_modrm_offset(s, OPC_MOVD_EyVy, arg, 0, arg1, arg2); 1166 } 1167 break; 1168 case TCG_TYPE_I64: 1169 if (arg < 16) { 1170 tcg_out_modrm_offset(s, OPC_MOVL_EvGv | P_REXW, arg, arg1, arg2); 1171 break; 1172 } 1173 /* FALLTHRU */ 1174 case TCG_TYPE_V64: 1175 /* There is no instruction that can validate 8-byte alignment. */ 1176 tcg_debug_assert(arg >= 16); 1177 tcg_out_vex_modrm_offset(s, OPC_MOVQ_WqVq, arg, 0, arg1, arg2); 1178 break; 1179 case TCG_TYPE_V128: 1180 /* 1181 * The gvec infrastructure is asserts that v128 vector loads 1182 * and stores use a 16-byte aligned offset. Validate that the 1183 * final pointer is aligned by using an insn that will SIGSEGV. 1184 * 1185 * This specific instance is also used by TCG_CALL_RET_BY_VEC, 1186 * for _WIN64, which must have SSE2 but may not have AVX. 1187 */ 1188 tcg_debug_assert(arg >= 16); 1189 if (have_avx1) { 1190 tcg_out_vex_modrm_offset(s, OPC_MOVDQA_WxVx, arg, 0, arg1, arg2); 1191 } else { 1192 tcg_out_modrm_offset(s, OPC_MOVDQA_WxVx, arg, arg1, arg2); 1193 } 1194 break; 1195 case TCG_TYPE_V256: 1196 /* 1197 * The gvec infrastructure only requires 16-byte alignment, 1198 * so here we must use an unaligned store. 1199 */ 1200 tcg_debug_assert(arg >= 16); 1201 tcg_out_vex_modrm_offset(s, OPC_MOVDQU_WxVx | P_VEXL, 1202 arg, 0, arg1, arg2); 1203 break; 1204 default: 1205 g_assert_not_reached(); 1206 } 1207} 1208 1209static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 1210 TCGReg base, intptr_t ofs) 1211{ 1212 int rexw = 0; 1213 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64) { 1214 if (val != (int32_t)val) { 1215 return false; 1216 } 1217 rexw = P_REXW; 1218 } else if (type != TCG_TYPE_I32) { 1219 return false; 1220 } 1221 tcg_out_modrm_offset(s, OPC_MOVL_EvIz | rexw, 0, base, ofs); 1222 tcg_out32(s, val); 1223 return true; 1224} 1225 1226static void tcg_out_shifti(TCGContext *s, int subopc, int reg, int count) 1227{ 1228 /* Propagate an opcode prefix, such as P_DATA16. */ 1229 int ext = subopc & ~0x7; 1230 subopc &= 0x7; 1231 1232 if (count == 1) { 1233 tcg_out_modrm(s, OPC_SHIFT_1 + ext, subopc, reg); 1234 } else { 1235 tcg_out_modrm(s, OPC_SHIFT_Ib + ext, subopc, reg); 1236 tcg_out8(s, count); 1237 } 1238} 1239 1240static inline void tcg_out_bswap32(TCGContext *s, int reg) 1241{ 1242 tcg_out_opc(s, OPC_BSWAP + LOWREGMASK(reg), 0, reg, 0); 1243} 1244 1245static inline void tcg_out_rolw_8(TCGContext *s, int reg) 1246{ 1247 tcg_out_shifti(s, SHIFT_ROL + P_DATA16, reg, 8); 1248} 1249 1250static void tcg_out_ext8u(TCGContext *s, TCGReg dest, TCGReg src) 1251{ 1252 /* movzbl */ 1253 tcg_debug_assert(src < 4 || TCG_TARGET_REG_BITS == 64); 1254 tcg_out_modrm(s, OPC_MOVZBL + P_REXB_RM, dest, src); 1255} 1256 1257static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) 1258{ 1259 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 1260 /* movsbl */ 1261 tcg_debug_assert(src < 4 || TCG_TARGET_REG_BITS == 64); 1262 tcg_out_modrm(s, OPC_MOVSBL + P_REXB_RM + rexw, dest, src); 1263} 1264 1265static void tcg_out_ext16u(TCGContext *s, TCGReg dest, TCGReg src) 1266{ 1267 /* movzwl */ 1268 tcg_out_modrm(s, OPC_MOVZWL, dest, src); 1269} 1270 1271static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) 1272{ 1273 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 1274 /* movsw[lq] */ 1275 tcg_out_modrm(s, OPC_MOVSWL + rexw, dest, src); 1276} 1277 1278static void tcg_out_ext32u(TCGContext *s, TCGReg dest, TCGReg src) 1279{ 1280 /* 32-bit mov zero extends. */ 1281 tcg_out_modrm(s, OPC_MOVL_GvEv, dest, src); 1282} 1283 1284static void tcg_out_ext32s(TCGContext *s, TCGReg dest, TCGReg src) 1285{ 1286 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 1287 tcg_out_modrm(s, OPC_MOVSLQ, dest, src); 1288} 1289 1290static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg dest, TCGReg src) 1291{ 1292 tcg_out_ext32s(s, dest, src); 1293} 1294 1295static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg dest, TCGReg src) 1296{ 1297 if (dest != src) { 1298 tcg_out_ext32u(s, dest, src); 1299 } 1300} 1301 1302static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg dest, TCGReg src) 1303{ 1304 tcg_out_ext32u(s, dest, src); 1305} 1306 1307static inline void tcg_out_bswap64(TCGContext *s, int reg) 1308{ 1309 tcg_out_opc(s, OPC_BSWAP + P_REXW + LOWREGMASK(reg), 0, reg, 0); 1310} 1311 1312static void tgen_arithi(TCGContext *s, int c, int r0, 1313 tcg_target_long val, int cf) 1314{ 1315 int rexw = 0; 1316 1317 if (TCG_TARGET_REG_BITS == 64) { 1318 rexw = c & -8; 1319 c &= 7; 1320 } 1321 1322 /* ??? While INC is 2 bytes shorter than ADDL $1, they also induce 1323 partial flags update stalls on Pentium4 and are not recommended 1324 by current Intel optimization manuals. */ 1325 if (!cf && (c == ARITH_ADD || c == ARITH_SUB) && (val == 1 || val == -1)) { 1326 int is_inc = (c == ARITH_ADD) ^ (val < 0); 1327 if (TCG_TARGET_REG_BITS == 64) { 1328 /* The single-byte increment encodings are re-tasked as the 1329 REX prefixes. Use the MODRM encoding. */ 1330 tcg_out_modrm(s, OPC_GRP5 + rexw, 1331 (is_inc ? EXT5_INC_Ev : EXT5_DEC_Ev), r0); 1332 } else { 1333 tcg_out8(s, (is_inc ? OPC_INC_r32 : OPC_DEC_r32) + r0); 1334 } 1335 return; 1336 } 1337 1338 if (c == ARITH_AND) { 1339 if (TCG_TARGET_REG_BITS == 64) { 1340 if (val == 0xffffffffu) { 1341 tcg_out_ext32u(s, r0, r0); 1342 return; 1343 } 1344 if (val == (uint32_t)val) { 1345 /* AND with no high bits set can use a 32-bit operation. */ 1346 rexw = 0; 1347 } 1348 } 1349 if (val == 0xffu && (r0 < 4 || TCG_TARGET_REG_BITS == 64)) { 1350 tcg_out_ext8u(s, r0, r0); 1351 return; 1352 } 1353 if (val == 0xffffu) { 1354 tcg_out_ext16u(s, r0, r0); 1355 return; 1356 } 1357 } 1358 1359 if (val == (int8_t)val) { 1360 tcg_out_modrm(s, OPC_ARITH_EvIb + rexw, c, r0); 1361 tcg_out8(s, val); 1362 return; 1363 } 1364 if (rexw == 0 || val == (int32_t)val) { 1365 tcg_out_modrm(s, OPC_ARITH_EvIz + rexw, c, r0); 1366 tcg_out32(s, val); 1367 return; 1368 } 1369 1370 g_assert_not_reached(); 1371} 1372 1373static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val) 1374{ 1375 if (val != 0) { 1376 tgen_arithi(s, ARITH_ADD + P_REXW, reg, val, 0); 1377 } 1378} 1379 1380/* Set SMALL to force a short forward branch. */ 1381static void tcg_out_jxx(TCGContext *s, int opc, TCGLabel *l, bool small) 1382{ 1383 int32_t val, val1; 1384 1385 if (l->has_value) { 1386 val = tcg_pcrel_diff(s, l->u.value_ptr); 1387 val1 = val - 2; 1388 if ((int8_t)val1 == val1) { 1389 if (opc == -1) { 1390 tcg_out8(s, OPC_JMP_short); 1391 } else { 1392 tcg_out8(s, OPC_JCC_short + opc); 1393 } 1394 tcg_out8(s, val1); 1395 } else { 1396 tcg_debug_assert(!small); 1397 if (opc == -1) { 1398 tcg_out8(s, OPC_JMP_long); 1399 tcg_out32(s, val - 5); 1400 } else { 1401 tcg_out_opc(s, OPC_JCC_long + opc, 0, 0, 0); 1402 tcg_out32(s, val - 6); 1403 } 1404 } 1405 } else if (small) { 1406 if (opc == -1) { 1407 tcg_out8(s, OPC_JMP_short); 1408 } else { 1409 tcg_out8(s, OPC_JCC_short + opc); 1410 } 1411 tcg_out_reloc(s, s->code_ptr, R_386_PC8, l, -1); 1412 s->code_ptr += 1; 1413 } else { 1414 if (opc == -1) { 1415 tcg_out8(s, OPC_JMP_long); 1416 } else { 1417 tcg_out_opc(s, OPC_JCC_long + opc, 0, 0, 0); 1418 } 1419 tcg_out_reloc(s, s->code_ptr, R_386_PC32, l, -4); 1420 s->code_ptr += 4; 1421 } 1422} 1423 1424static void tcg_out_cmp(TCGContext *s, TCGArg arg1, TCGArg arg2, 1425 int const_arg2, int rexw) 1426{ 1427 if (const_arg2) { 1428 if (arg2 == 0) { 1429 /* test r, r */ 1430 tcg_out_modrm(s, OPC_TESTL + rexw, arg1, arg1); 1431 } else { 1432 tgen_arithi(s, ARITH_CMP + rexw, arg1, arg2, 0); 1433 } 1434 } else { 1435 tgen_arithr(s, ARITH_CMP + rexw, arg1, arg2); 1436 } 1437} 1438 1439static void tcg_out_brcond32(TCGContext *s, TCGCond cond, 1440 TCGArg arg1, TCGArg arg2, int const_arg2, 1441 TCGLabel *label, int small) 1442{ 1443 tcg_out_cmp(s, arg1, arg2, const_arg2, 0); 1444 tcg_out_jxx(s, tcg_cond_to_jcc[cond], label, small); 1445} 1446 1447#if TCG_TARGET_REG_BITS == 64 1448static void tcg_out_brcond64(TCGContext *s, TCGCond cond, 1449 TCGArg arg1, TCGArg arg2, int const_arg2, 1450 TCGLabel *label, int small) 1451{ 1452 tcg_out_cmp(s, arg1, arg2, const_arg2, P_REXW); 1453 tcg_out_jxx(s, tcg_cond_to_jcc[cond], label, small); 1454} 1455#else 1456/* XXX: we implement it at the target level to avoid having to 1457 handle cross basic blocks temporaries */ 1458static void tcg_out_brcond2(TCGContext *s, const TCGArg *args, 1459 const int *const_args, int small) 1460{ 1461 TCGLabel *label_next = gen_new_label(); 1462 TCGLabel *label_this = arg_label(args[5]); 1463 1464 switch(args[4]) { 1465 case TCG_COND_EQ: 1466 tcg_out_brcond32(s, TCG_COND_NE, args[0], args[2], const_args[2], 1467 label_next, 1); 1468 tcg_out_brcond32(s, TCG_COND_EQ, args[1], args[3], const_args[3], 1469 label_this, small); 1470 break; 1471 case TCG_COND_NE: 1472 tcg_out_brcond32(s, TCG_COND_NE, args[0], args[2], const_args[2], 1473 label_this, small); 1474 tcg_out_brcond32(s, TCG_COND_NE, args[1], args[3], const_args[3], 1475 label_this, small); 1476 break; 1477 case TCG_COND_LT: 1478 tcg_out_brcond32(s, TCG_COND_LT, args[1], args[3], const_args[3], 1479 label_this, small); 1480 tcg_out_jxx(s, JCC_JNE, label_next, 1); 1481 tcg_out_brcond32(s, TCG_COND_LTU, args[0], args[2], const_args[2], 1482 label_this, small); 1483 break; 1484 case TCG_COND_LE: 1485 tcg_out_brcond32(s, TCG_COND_LT, args[1], args[3], const_args[3], 1486 label_this, small); 1487 tcg_out_jxx(s, JCC_JNE, label_next, 1); 1488 tcg_out_brcond32(s, TCG_COND_LEU, args[0], args[2], const_args[2], 1489 label_this, small); 1490 break; 1491 case TCG_COND_GT: 1492 tcg_out_brcond32(s, TCG_COND_GT, args[1], args[3], const_args[3], 1493 label_this, small); 1494 tcg_out_jxx(s, JCC_JNE, label_next, 1); 1495 tcg_out_brcond32(s, TCG_COND_GTU, args[0], args[2], const_args[2], 1496 label_this, small); 1497 break; 1498 case TCG_COND_GE: 1499 tcg_out_brcond32(s, TCG_COND_GT, args[1], args[3], const_args[3], 1500 label_this, small); 1501 tcg_out_jxx(s, JCC_JNE, label_next, 1); 1502 tcg_out_brcond32(s, TCG_COND_GEU, args[0], args[2], const_args[2], 1503 label_this, small); 1504 break; 1505 case TCG_COND_LTU: 1506 tcg_out_brcond32(s, TCG_COND_LTU, args[1], args[3], const_args[3], 1507 label_this, small); 1508 tcg_out_jxx(s, JCC_JNE, label_next, 1); 1509 tcg_out_brcond32(s, TCG_COND_LTU, args[0], args[2], const_args[2], 1510 label_this, small); 1511 break; 1512 case TCG_COND_LEU: 1513 tcg_out_brcond32(s, TCG_COND_LTU, args[1], args[3], const_args[3], 1514 label_this, small); 1515 tcg_out_jxx(s, JCC_JNE, label_next, 1); 1516 tcg_out_brcond32(s, TCG_COND_LEU, args[0], args[2], const_args[2], 1517 label_this, small); 1518 break; 1519 case TCG_COND_GTU: 1520 tcg_out_brcond32(s, TCG_COND_GTU, args[1], args[3], const_args[3], 1521 label_this, small); 1522 tcg_out_jxx(s, JCC_JNE, label_next, 1); 1523 tcg_out_brcond32(s, TCG_COND_GTU, args[0], args[2], const_args[2], 1524 label_this, small); 1525 break; 1526 case TCG_COND_GEU: 1527 tcg_out_brcond32(s, TCG_COND_GTU, args[1], args[3], const_args[3], 1528 label_this, small); 1529 tcg_out_jxx(s, JCC_JNE, label_next, 1); 1530 tcg_out_brcond32(s, TCG_COND_GEU, args[0], args[2], const_args[2], 1531 label_this, small); 1532 break; 1533 default: 1534 g_assert_not_reached(); 1535 } 1536 tcg_out_label(s, label_next); 1537} 1538#endif 1539 1540static void tcg_out_setcond32(TCGContext *s, TCGCond cond, TCGArg dest, 1541 TCGArg arg1, TCGArg arg2, int const_arg2) 1542{ 1543 tcg_out_cmp(s, arg1, arg2, const_arg2, 0); 1544 tcg_out_modrm(s, OPC_SETCC | tcg_cond_to_jcc[cond], 0, dest); 1545 tcg_out_ext8u(s, dest, dest); 1546} 1547 1548#if TCG_TARGET_REG_BITS == 64 1549static void tcg_out_setcond64(TCGContext *s, TCGCond cond, TCGArg dest, 1550 TCGArg arg1, TCGArg arg2, int const_arg2) 1551{ 1552 tcg_out_cmp(s, arg1, arg2, const_arg2, P_REXW); 1553 tcg_out_modrm(s, OPC_SETCC | tcg_cond_to_jcc[cond], 0, dest); 1554 tcg_out_ext8u(s, dest, dest); 1555} 1556#else 1557static void tcg_out_setcond2(TCGContext *s, const TCGArg *args, 1558 const int *const_args) 1559{ 1560 TCGArg new_args[6]; 1561 TCGLabel *label_true, *label_over; 1562 1563 memcpy(new_args, args+1, 5*sizeof(TCGArg)); 1564 1565 if (args[0] == args[1] || args[0] == args[2] 1566 || (!const_args[3] && args[0] == args[3]) 1567 || (!const_args[4] && args[0] == args[4])) { 1568 /* When the destination overlaps with one of the argument 1569 registers, don't do anything tricky. */ 1570 label_true = gen_new_label(); 1571 label_over = gen_new_label(); 1572 1573 new_args[5] = label_arg(label_true); 1574 tcg_out_brcond2(s, new_args, const_args+1, 1); 1575 1576 tcg_out_movi(s, TCG_TYPE_I32, args[0], 0); 1577 tcg_out_jxx(s, JCC_JMP, label_over, 1); 1578 tcg_out_label(s, label_true); 1579 1580 tcg_out_movi(s, TCG_TYPE_I32, args[0], 1); 1581 tcg_out_label(s, label_over); 1582 } else { 1583 /* When the destination does not overlap one of the arguments, 1584 clear the destination first, jump if cond false, and emit an 1585 increment in the true case. This results in smaller code. */ 1586 1587 tcg_out_movi(s, TCG_TYPE_I32, args[0], 0); 1588 1589 label_over = gen_new_label(); 1590 new_args[4] = tcg_invert_cond(new_args[4]); 1591 new_args[5] = label_arg(label_over); 1592 tcg_out_brcond2(s, new_args, const_args+1, 1); 1593 1594 tgen_arithi(s, ARITH_ADD, args[0], 1, 0); 1595 tcg_out_label(s, label_over); 1596 } 1597} 1598#endif 1599 1600static void tcg_out_cmov(TCGContext *s, TCGCond cond, int rexw, 1601 TCGReg dest, TCGReg v1) 1602{ 1603 if (have_cmov) { 1604 tcg_out_modrm(s, OPC_CMOVCC | tcg_cond_to_jcc[cond] | rexw, dest, v1); 1605 } else { 1606 TCGLabel *over = gen_new_label(); 1607 tcg_out_jxx(s, tcg_cond_to_jcc[tcg_invert_cond(cond)], over, 1); 1608 tcg_out_mov(s, TCG_TYPE_I32, dest, v1); 1609 tcg_out_label(s, over); 1610 } 1611} 1612 1613static void tcg_out_movcond32(TCGContext *s, TCGCond cond, TCGReg dest, 1614 TCGReg c1, TCGArg c2, int const_c2, 1615 TCGReg v1) 1616{ 1617 tcg_out_cmp(s, c1, c2, const_c2, 0); 1618 tcg_out_cmov(s, cond, 0, dest, v1); 1619} 1620 1621#if TCG_TARGET_REG_BITS == 64 1622static void tcg_out_movcond64(TCGContext *s, TCGCond cond, TCGReg dest, 1623 TCGReg c1, TCGArg c2, int const_c2, 1624 TCGReg v1) 1625{ 1626 tcg_out_cmp(s, c1, c2, const_c2, P_REXW); 1627 tcg_out_cmov(s, cond, P_REXW, dest, v1); 1628} 1629#endif 1630 1631static void tcg_out_ctz(TCGContext *s, int rexw, TCGReg dest, TCGReg arg1, 1632 TCGArg arg2, bool const_a2) 1633{ 1634 if (have_bmi1) { 1635 tcg_out_modrm(s, OPC_TZCNT + rexw, dest, arg1); 1636 if (const_a2) { 1637 tcg_debug_assert(arg2 == (rexw ? 64 : 32)); 1638 } else { 1639 tcg_debug_assert(dest != arg2); 1640 tcg_out_cmov(s, TCG_COND_LTU, rexw, dest, arg2); 1641 } 1642 } else { 1643 tcg_debug_assert(dest != arg2); 1644 tcg_out_modrm(s, OPC_BSF + rexw, dest, arg1); 1645 tcg_out_cmov(s, TCG_COND_EQ, rexw, dest, arg2); 1646 } 1647} 1648 1649static void tcg_out_clz(TCGContext *s, int rexw, TCGReg dest, TCGReg arg1, 1650 TCGArg arg2, bool const_a2) 1651{ 1652 if (have_lzcnt) { 1653 tcg_out_modrm(s, OPC_LZCNT + rexw, dest, arg1); 1654 if (const_a2) { 1655 tcg_debug_assert(arg2 == (rexw ? 64 : 32)); 1656 } else { 1657 tcg_debug_assert(dest != arg2); 1658 tcg_out_cmov(s, TCG_COND_LTU, rexw, dest, arg2); 1659 } 1660 } else { 1661 tcg_debug_assert(!const_a2); 1662 tcg_debug_assert(dest != arg1); 1663 tcg_debug_assert(dest != arg2); 1664 1665 /* Recall that the output of BSR is the index not the count. */ 1666 tcg_out_modrm(s, OPC_BSR + rexw, dest, arg1); 1667 tgen_arithi(s, ARITH_XOR + rexw, dest, rexw ? 63 : 31, 0); 1668 1669 /* Since we have destroyed the flags from BSR, we have to re-test. */ 1670 tcg_out_cmp(s, arg1, 0, 1, rexw); 1671 tcg_out_cmov(s, TCG_COND_EQ, rexw, dest, arg2); 1672 } 1673} 1674 1675static void tcg_out_branch(TCGContext *s, int call, const tcg_insn_unit *dest) 1676{ 1677 intptr_t disp = tcg_pcrel_diff(s, dest) - 5; 1678 1679 if (disp == (int32_t)disp) { 1680 tcg_out_opc(s, call ? OPC_CALL_Jz : OPC_JMP_long, 0, 0, 0); 1681 tcg_out32(s, disp); 1682 } else { 1683 /* rip-relative addressing into the constant pool. 1684 This is 6 + 8 = 14 bytes, as compared to using an 1685 immediate load 10 + 6 = 16 bytes, plus we may 1686 be able to re-use the pool constant for more calls. */ 1687 tcg_out_opc(s, OPC_GRP5, 0, 0, 0); 1688 tcg_out8(s, (call ? EXT5_CALLN_Ev : EXT5_JMPN_Ev) << 3 | 5); 1689 new_pool_label(s, (uintptr_t)dest, R_386_PC32, s->code_ptr, -4); 1690 tcg_out32(s, 0); 1691 } 1692} 1693 1694static void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest, 1695 const TCGHelperInfo *info) 1696{ 1697 tcg_out_branch(s, 1, dest); 1698 1699#ifndef _WIN32 1700 if (TCG_TARGET_REG_BITS == 32 && info->out_kind == TCG_CALL_RET_BY_REF) { 1701 /* 1702 * The sysv i386 abi for struct return places a reference as the 1703 * first argument of the stack, and pops that argument with the 1704 * return statement. Since we want to retain the aligned stack 1705 * pointer for the callee, we do not want to actually push that 1706 * argument before the call but rely on the normal store to the 1707 * stack slot. But we do need to compensate for the pop in order 1708 * to reset our correct stack pointer value. 1709 * Pushing a garbage value back onto the stack is quickest. 1710 */ 1711 tcg_out_push(s, TCG_REG_EAX); 1712 } 1713#endif 1714} 1715 1716static void tcg_out_jmp(TCGContext *s, const tcg_insn_unit *dest) 1717{ 1718 tcg_out_branch(s, 0, dest); 1719} 1720 1721static void tcg_out_nopn(TCGContext *s, int n) 1722{ 1723 int i; 1724 /* Emit 1 or 2 operand size prefixes for the standard one byte nop, 1725 * "xchg %eax,%eax", forming "xchg %ax,%ax". All cores accept the 1726 * duplicate prefix, and all of the interesting recent cores can 1727 * decode and discard the duplicates in a single cycle. 1728 */ 1729 tcg_debug_assert(n >= 1); 1730 for (i = 1; i < n; ++i) { 1731 tcg_out8(s, 0x66); 1732 } 1733 tcg_out8(s, 0x90); 1734} 1735 1736/* Test register R vs immediate bits I, setting Z flag for EQ/NE. */ 1737static void __attribute__((unused)) 1738tcg_out_testi(TCGContext *s, TCGReg r, uint32_t i) 1739{ 1740 /* 1741 * This is used for testing alignment, so we can usually use testb. 1742 * For i686, we have to use testl for %esi/%edi. 1743 */ 1744 if (i <= 0xff && (TCG_TARGET_REG_BITS == 64 || r < 4)) { 1745 tcg_out_modrm(s, OPC_GRP3_Eb | P_REXB_RM, EXT3_TESTi, r); 1746 tcg_out8(s, i); 1747 } else { 1748 tcg_out_modrm(s, OPC_GRP3_Ev, EXT3_TESTi, r); 1749 tcg_out32(s, i); 1750 } 1751} 1752 1753typedef struct { 1754 TCGReg base; 1755 int index; 1756 int ofs; 1757 int seg; 1758 TCGAtomAlign aa; 1759} HostAddress; 1760 1761bool tcg_target_has_memory_bswap(MemOp memop) 1762{ 1763 TCGAtomAlign aa; 1764 1765 if (!have_movbe) { 1766 return false; 1767 } 1768 if ((memop & MO_SIZE) < MO_128) { 1769 return true; 1770 } 1771 1772 /* 1773 * Reject 16-byte memop with 16-byte atomicity, i.e. VMOVDQA, 1774 * but do allow a pair of 64-bit operations, i.e. MOVBEQ. 1775 */ 1776 aa = atom_and_align_for_opc(tcg_ctx, memop, MO_ATOM_IFALIGN, true); 1777 return aa.atom < MO_128; 1778} 1779 1780/* 1781 * Because i686 has no register parameters and because x86_64 has xchg 1782 * to handle addr/data register overlap, we have placed all input arguments 1783 * before we need might need a scratch reg. 1784 * 1785 * Even then, a scratch is only needed for l->raddr. Rather than expose 1786 * a general-purpose scratch when we don't actually know it's available, 1787 * use the ra_gen hook to load into RAX if needed. 1788 */ 1789#if TCG_TARGET_REG_BITS == 64 1790static TCGReg ldst_ra_gen(TCGContext *s, const TCGLabelQemuLdst *l, int arg) 1791{ 1792 if (arg < 0) { 1793 arg = TCG_REG_RAX; 1794 } 1795 tcg_out_movi(s, TCG_TYPE_PTR, arg, (uintptr_t)l->raddr); 1796 return arg; 1797} 1798static const TCGLdstHelperParam ldst_helper_param = { 1799 .ra_gen = ldst_ra_gen 1800}; 1801#else 1802static const TCGLdstHelperParam ldst_helper_param = { }; 1803#endif 1804 1805static void tcg_out_vec_to_pair(TCGContext *s, TCGType type, 1806 TCGReg l, TCGReg h, TCGReg v) 1807{ 1808 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 1809 1810 /* vpmov{d,q} %v, %l */ 1811 tcg_out_vex_modrm(s, OPC_MOVD_EyVy + rexw, v, 0, l); 1812 /* vpextr{d,q} $1, %v, %h */ 1813 tcg_out_vex_modrm(s, OPC_PEXTRD + rexw, v, 0, h); 1814 tcg_out8(s, 1); 1815} 1816 1817static void tcg_out_pair_to_vec(TCGContext *s, TCGType type, 1818 TCGReg v, TCGReg l, TCGReg h) 1819{ 1820 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 1821 1822 /* vmov{d,q} %l, %v */ 1823 tcg_out_vex_modrm(s, OPC_MOVD_VyEy + rexw, v, 0, l); 1824 /* vpinsr{d,q} $1, %h, %v, %v */ 1825 tcg_out_vex_modrm(s, OPC_PINSRD + rexw, v, v, h); 1826 tcg_out8(s, 1); 1827} 1828 1829/* 1830 * Generate code for the slow path for a load at the end of block 1831 */ 1832static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1833{ 1834 MemOp opc = get_memop(l->oi); 1835 tcg_insn_unit **label_ptr = &l->label_ptr[0]; 1836 1837 /* resolve label address */ 1838 tcg_patch32(label_ptr[0], s->code_ptr - label_ptr[0] - 4); 1839 if (label_ptr[1]) { 1840 tcg_patch32(label_ptr[1], s->code_ptr - label_ptr[1] - 4); 1841 } 1842 1843 tcg_out_ld_helper_args(s, l, &ldst_helper_param); 1844 tcg_out_branch(s, 1, qemu_ld_helpers[opc & MO_SIZE]); 1845 tcg_out_ld_helper_ret(s, l, false, &ldst_helper_param); 1846 1847 tcg_out_jmp(s, l->raddr); 1848 return true; 1849} 1850 1851/* 1852 * Generate code for the slow path for a store at the end of block 1853 */ 1854static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1855{ 1856 MemOp opc = get_memop(l->oi); 1857 tcg_insn_unit **label_ptr = &l->label_ptr[0]; 1858 1859 /* resolve label address */ 1860 tcg_patch32(label_ptr[0], s->code_ptr - label_ptr[0] - 4); 1861 if (label_ptr[1]) { 1862 tcg_patch32(label_ptr[1], s->code_ptr - label_ptr[1] - 4); 1863 } 1864 1865 tcg_out_st_helper_args(s, l, &ldst_helper_param); 1866 tcg_out_branch(s, 1, qemu_st_helpers[opc & MO_SIZE]); 1867 1868 tcg_out_jmp(s, l->raddr); 1869 return true; 1870} 1871 1872#ifndef CONFIG_SOFTMMU 1873static HostAddress x86_guest_base = { 1874 .index = -1 1875}; 1876 1877#if defined(__x86_64__) && defined(__linux__) 1878# include <asm/prctl.h> 1879# include <sys/prctl.h> 1880int arch_prctl(int code, unsigned long addr); 1881static inline int setup_guest_base_seg(void) 1882{ 1883 if (arch_prctl(ARCH_SET_GS, guest_base) == 0) { 1884 return P_GS; 1885 } 1886 return 0; 1887} 1888#elif defined(__x86_64__) && \ 1889 (defined (__FreeBSD__) || defined (__FreeBSD_kernel__)) 1890# include <machine/sysarch.h> 1891static inline int setup_guest_base_seg(void) 1892{ 1893 if (sysarch(AMD64_SET_GSBASE, &guest_base) == 0) { 1894 return P_GS; 1895 } 1896 return 0; 1897} 1898#else 1899static inline int setup_guest_base_seg(void) 1900{ 1901 return 0; 1902} 1903#endif /* setup_guest_base_seg */ 1904#endif /* !SOFTMMU */ 1905 1906#define MIN_TLB_MASK_TABLE_OFS INT_MIN 1907 1908/* 1909 * For softmmu, perform the TLB load and compare. 1910 * For useronly, perform any required alignment tests. 1911 * In both cases, return a TCGLabelQemuLdst structure if the slow path 1912 * is required and fill in @h with the host address for the fast path. 1913 */ 1914static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1915 TCGReg addrlo, TCGReg addrhi, 1916 MemOpIdx oi, bool is_ld) 1917{ 1918 TCGLabelQemuLdst *ldst = NULL; 1919 MemOp opc = get_memop(oi); 1920 MemOp s_bits = opc & MO_SIZE; 1921 unsigned a_mask; 1922 1923#ifdef CONFIG_SOFTMMU 1924 h->index = TCG_REG_L0; 1925 h->ofs = 0; 1926 h->seg = 0; 1927#else 1928 *h = x86_guest_base; 1929#endif 1930 h->base = addrlo; 1931 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, s_bits == MO_128); 1932 a_mask = (1 << h->aa.align) - 1; 1933 1934#ifdef CONFIG_SOFTMMU 1935 int cmp_ofs = is_ld ? offsetof(CPUTLBEntry, addr_read) 1936 : offsetof(CPUTLBEntry, addr_write); 1937 TCGType ttype = TCG_TYPE_I32; 1938 TCGType tlbtype = TCG_TYPE_I32; 1939 int trexw = 0, hrexw = 0, tlbrexw = 0; 1940 unsigned mem_index = get_mmuidx(oi); 1941 unsigned s_mask = (1 << s_bits) - 1; 1942 int fast_ofs = tlb_mask_table_ofs(s, mem_index); 1943 int tlb_mask; 1944 1945 ldst = new_ldst_label(s); 1946 ldst->is_ld = is_ld; 1947 ldst->oi = oi; 1948 ldst->addrlo_reg = addrlo; 1949 ldst->addrhi_reg = addrhi; 1950 1951 if (TCG_TARGET_REG_BITS == 64) { 1952 ttype = s->addr_type; 1953 trexw = (ttype == TCG_TYPE_I32 ? 0 : P_REXW); 1954 if (TCG_TYPE_PTR == TCG_TYPE_I64) { 1955 hrexw = P_REXW; 1956 if (s->page_bits + s->tlb_dyn_max_bits > 32) { 1957 tlbtype = TCG_TYPE_I64; 1958 tlbrexw = P_REXW; 1959 } 1960 } 1961 } 1962 1963 tcg_out_mov(s, tlbtype, TCG_REG_L0, addrlo); 1964 tcg_out_shifti(s, SHIFT_SHR + tlbrexw, TCG_REG_L0, 1965 s->page_bits - CPU_TLB_ENTRY_BITS); 1966 1967 tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, TCG_REG_L0, TCG_AREG0, 1968 fast_ofs + offsetof(CPUTLBDescFast, mask)); 1969 1970 tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, TCG_REG_L0, TCG_AREG0, 1971 fast_ofs + offsetof(CPUTLBDescFast, table)); 1972 1973 /* 1974 * If the required alignment is at least as large as the access, simply 1975 * copy the address and mask. For lesser alignments, check that we don't 1976 * cross pages for the complete access. 1977 */ 1978 if (a_mask >= s_mask) { 1979 tcg_out_mov(s, ttype, TCG_REG_L1, addrlo); 1980 } else { 1981 tcg_out_modrm_offset(s, OPC_LEA + trexw, TCG_REG_L1, 1982 addrlo, s_mask - a_mask); 1983 } 1984 tlb_mask = s->page_mask | a_mask; 1985 tgen_arithi(s, ARITH_AND + trexw, TCG_REG_L1, tlb_mask, 0); 1986 1987 /* cmp 0(TCG_REG_L0), TCG_REG_L1 */ 1988 tcg_out_modrm_offset(s, OPC_CMP_GvEv + trexw, 1989 TCG_REG_L1, TCG_REG_L0, cmp_ofs); 1990 1991 /* jne slow_path */ 1992 tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); 1993 ldst->label_ptr[0] = s->code_ptr; 1994 s->code_ptr += 4; 1995 1996 if (TCG_TARGET_REG_BITS == 32 && s->addr_type == TCG_TYPE_I64) { 1997 /* cmp 4(TCG_REG_L0), addrhi */ 1998 tcg_out_modrm_offset(s, OPC_CMP_GvEv, addrhi, TCG_REG_L0, cmp_ofs + 4); 1999 2000 /* jne slow_path */ 2001 tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); 2002 ldst->label_ptr[1] = s->code_ptr; 2003 s->code_ptr += 4; 2004 } 2005 2006 /* TLB Hit. */ 2007 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_L0, TCG_REG_L0, 2008 offsetof(CPUTLBEntry, addend)); 2009#else 2010 if (a_mask) { 2011 ldst = new_ldst_label(s); 2012 2013 ldst->is_ld = is_ld; 2014 ldst->oi = oi; 2015 ldst->addrlo_reg = addrlo; 2016 ldst->addrhi_reg = addrhi; 2017 2018 tcg_out_testi(s, addrlo, a_mask); 2019 /* jne slow_path */ 2020 tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); 2021 ldst->label_ptr[0] = s->code_ptr; 2022 s->code_ptr += 4; 2023 } 2024#endif 2025 2026 return ldst; 2027} 2028 2029static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, 2030 HostAddress h, TCGType type, MemOp memop) 2031{ 2032 bool use_movbe = false; 2033 int rexw = (type == TCG_TYPE_I32 ? 0 : P_REXW); 2034 int movop = OPC_MOVL_GvEv; 2035 2036 /* Do big-endian loads with movbe. */ 2037 if (memop & MO_BSWAP) { 2038 tcg_debug_assert(have_movbe); 2039 use_movbe = true; 2040 movop = OPC_MOVBE_GyMy; 2041 } 2042 2043 switch (memop & MO_SSIZE) { 2044 case MO_UB: 2045 tcg_out_modrm_sib_offset(s, OPC_MOVZBL + h.seg, datalo, 2046 h.base, h.index, 0, h.ofs); 2047 break; 2048 case MO_SB: 2049 tcg_out_modrm_sib_offset(s, OPC_MOVSBL + rexw + h.seg, datalo, 2050 h.base, h.index, 0, h.ofs); 2051 break; 2052 case MO_UW: 2053 if (use_movbe) { 2054 /* There is no extending movbe; only low 16-bits are modified. */ 2055 if (datalo != h.base && datalo != h.index) { 2056 /* XOR breaks dependency chains. */ 2057 tgen_arithr(s, ARITH_XOR, datalo, datalo); 2058 tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + h.seg, 2059 datalo, h.base, h.index, 0, h.ofs); 2060 } else { 2061 tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + h.seg, 2062 datalo, h.base, h.index, 0, h.ofs); 2063 tcg_out_ext16u(s, datalo, datalo); 2064 } 2065 } else { 2066 tcg_out_modrm_sib_offset(s, OPC_MOVZWL + h.seg, datalo, 2067 h.base, h.index, 0, h.ofs); 2068 } 2069 break; 2070 case MO_SW: 2071 if (use_movbe) { 2072 tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + h.seg, 2073 datalo, h.base, h.index, 0, h.ofs); 2074 tcg_out_ext16s(s, type, datalo, datalo); 2075 } else { 2076 tcg_out_modrm_sib_offset(s, OPC_MOVSWL + rexw + h.seg, 2077 datalo, h.base, h.index, 0, h.ofs); 2078 } 2079 break; 2080 case MO_UL: 2081 tcg_out_modrm_sib_offset(s, movop + h.seg, datalo, 2082 h.base, h.index, 0, h.ofs); 2083 break; 2084#if TCG_TARGET_REG_BITS == 64 2085 case MO_SL: 2086 if (use_movbe) { 2087 tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + h.seg, datalo, 2088 h.base, h.index, 0, h.ofs); 2089 tcg_out_ext32s(s, datalo, datalo); 2090 } else { 2091 tcg_out_modrm_sib_offset(s, OPC_MOVSLQ + h.seg, datalo, 2092 h.base, h.index, 0, h.ofs); 2093 } 2094 break; 2095#endif 2096 case MO_UQ: 2097 if (TCG_TARGET_REG_BITS == 64) { 2098 tcg_out_modrm_sib_offset(s, movop + P_REXW + h.seg, datalo, 2099 h.base, h.index, 0, h.ofs); 2100 break; 2101 } 2102 if (use_movbe) { 2103 TCGReg t = datalo; 2104 datalo = datahi; 2105 datahi = t; 2106 } 2107 if (h.base == datalo || h.index == datalo) { 2108 tcg_out_modrm_sib_offset(s, OPC_LEA, datahi, 2109 h.base, h.index, 0, h.ofs); 2110 tcg_out_modrm_offset(s, movop + h.seg, datalo, datahi, 0); 2111 tcg_out_modrm_offset(s, movop + h.seg, datahi, datahi, 4); 2112 } else { 2113 tcg_out_modrm_sib_offset(s, movop + h.seg, datalo, 2114 h.base, h.index, 0, h.ofs); 2115 tcg_out_modrm_sib_offset(s, movop + h.seg, datahi, 2116 h.base, h.index, 0, h.ofs + 4); 2117 } 2118 break; 2119 2120 case MO_128: 2121 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 2122 2123 /* 2124 * Without 16-byte atomicity, use integer regs. 2125 * That is where we want the data, and it allows bswaps. 2126 */ 2127 if (h.aa.atom < MO_128) { 2128 if (use_movbe) { 2129 TCGReg t = datalo; 2130 datalo = datahi; 2131 datahi = t; 2132 } 2133 if (h.base == datalo || h.index == datalo) { 2134 tcg_out_modrm_sib_offset(s, OPC_LEA + P_REXW, datahi, 2135 h.base, h.index, 0, h.ofs); 2136 tcg_out_modrm_offset(s, movop + P_REXW + h.seg, 2137 datalo, datahi, 0); 2138 tcg_out_modrm_offset(s, movop + P_REXW + h.seg, 2139 datahi, datahi, 8); 2140 } else { 2141 tcg_out_modrm_sib_offset(s, movop + P_REXW + h.seg, datalo, 2142 h.base, h.index, 0, h.ofs); 2143 tcg_out_modrm_sib_offset(s, movop + P_REXW + h.seg, datahi, 2144 h.base, h.index, 0, h.ofs + 8); 2145 } 2146 break; 2147 } 2148 2149 /* 2150 * With 16-byte atomicity, a vector load is required. 2151 * If we already have 16-byte alignment, then VMOVDQA always works. 2152 * Else if VMOVDQU has atomicity with dynamic alignment, use that. 2153 * Else use we require a runtime test for alignment for VMOVDQA; 2154 * use VMOVDQU on the unaligned nonatomic path for simplicity. 2155 */ 2156 if (h.aa.align >= MO_128) { 2157 tcg_out_vex_modrm_sib_offset(s, OPC_MOVDQA_VxWx + h.seg, 2158 TCG_TMP_VEC, 0, 2159 h.base, h.index, 0, h.ofs); 2160 } else if (cpuinfo & CPUINFO_ATOMIC_VMOVDQU) { 2161 tcg_out_vex_modrm_sib_offset(s, OPC_MOVDQU_VxWx + h.seg, 2162 TCG_TMP_VEC, 0, 2163 h.base, h.index, 0, h.ofs); 2164 } else { 2165 TCGLabel *l1 = gen_new_label(); 2166 TCGLabel *l2 = gen_new_label(); 2167 2168 tcg_out_testi(s, h.base, 15); 2169 tcg_out_jxx(s, JCC_JNE, l1, true); 2170 2171 tcg_out_vex_modrm_sib_offset(s, OPC_MOVDQA_VxWx + h.seg, 2172 TCG_TMP_VEC, 0, 2173 h.base, h.index, 0, h.ofs); 2174 tcg_out_jxx(s, JCC_JMP, l2, true); 2175 2176 tcg_out_label(s, l1); 2177 tcg_out_vex_modrm_sib_offset(s, OPC_MOVDQU_VxWx + h.seg, 2178 TCG_TMP_VEC, 0, 2179 h.base, h.index, 0, h.ofs); 2180 tcg_out_label(s, l2); 2181 } 2182 tcg_out_vec_to_pair(s, TCG_TYPE_I64, datalo, datahi, TCG_TMP_VEC); 2183 break; 2184 2185 default: 2186 g_assert_not_reached(); 2187 } 2188} 2189 2190static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, 2191 TCGReg addrlo, TCGReg addrhi, 2192 MemOpIdx oi, TCGType data_type) 2193{ 2194 TCGLabelQemuLdst *ldst; 2195 HostAddress h; 2196 2197 ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, true); 2198 tcg_out_qemu_ld_direct(s, datalo, datahi, h, data_type, get_memop(oi)); 2199 2200 if (ldst) { 2201 ldst->type = data_type; 2202 ldst->datalo_reg = datalo; 2203 ldst->datahi_reg = datahi; 2204 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 2205 } 2206} 2207 2208static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, 2209 HostAddress h, MemOp memop) 2210{ 2211 bool use_movbe = false; 2212 int movop = OPC_MOVL_EvGv; 2213 2214 /* 2215 * Do big-endian stores with movbe or softmmu. 2216 * User-only without movbe will have its swapping done generically. 2217 */ 2218 if (memop & MO_BSWAP) { 2219 tcg_debug_assert(have_movbe); 2220 use_movbe = true; 2221 movop = OPC_MOVBE_MyGy; 2222 } 2223 2224 switch (memop & MO_SIZE) { 2225 case MO_8: 2226 /* This is handled with constraints on INDEX_op_qemu_st8_i32. */ 2227 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || datalo < 4); 2228 tcg_out_modrm_sib_offset(s, OPC_MOVB_EvGv + P_REXB_R + h.seg, 2229 datalo, h.base, h.index, 0, h.ofs); 2230 break; 2231 case MO_16: 2232 tcg_out_modrm_sib_offset(s, movop + P_DATA16 + h.seg, datalo, 2233 h.base, h.index, 0, h.ofs); 2234 break; 2235 case MO_32: 2236 tcg_out_modrm_sib_offset(s, movop + h.seg, datalo, 2237 h.base, h.index, 0, h.ofs); 2238 break; 2239 case MO_64: 2240 if (TCG_TARGET_REG_BITS == 64) { 2241 tcg_out_modrm_sib_offset(s, movop + P_REXW + h.seg, datalo, 2242 h.base, h.index, 0, h.ofs); 2243 } else { 2244 if (use_movbe) { 2245 TCGReg t = datalo; 2246 datalo = datahi; 2247 datahi = t; 2248 } 2249 tcg_out_modrm_sib_offset(s, movop + h.seg, datalo, 2250 h.base, h.index, 0, h.ofs); 2251 tcg_out_modrm_sib_offset(s, movop + h.seg, datahi, 2252 h.base, h.index, 0, h.ofs + 4); 2253 } 2254 break; 2255 2256 case MO_128: 2257 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 2258 2259 /* 2260 * Without 16-byte atomicity, use integer regs. 2261 * That is where we have the data, and it allows bswaps. 2262 */ 2263 if (h.aa.atom < MO_128) { 2264 if (use_movbe) { 2265 TCGReg t = datalo; 2266 datalo = datahi; 2267 datahi = t; 2268 } 2269 tcg_out_modrm_sib_offset(s, movop + P_REXW + h.seg, datalo, 2270 h.base, h.index, 0, h.ofs); 2271 tcg_out_modrm_sib_offset(s, movop + P_REXW + h.seg, datahi, 2272 h.base, h.index, 0, h.ofs + 8); 2273 break; 2274 } 2275 2276 /* 2277 * With 16-byte atomicity, a vector store is required. 2278 * If we already have 16-byte alignment, then VMOVDQA always works. 2279 * Else if VMOVDQU has atomicity with dynamic alignment, use that. 2280 * Else use we require a runtime test for alignment for VMOVDQA; 2281 * use VMOVDQU on the unaligned nonatomic path for simplicity. 2282 */ 2283 tcg_out_pair_to_vec(s, TCG_TYPE_I64, TCG_TMP_VEC, datalo, datahi); 2284 if (h.aa.align >= MO_128) { 2285 tcg_out_vex_modrm_sib_offset(s, OPC_MOVDQA_WxVx + h.seg, 2286 TCG_TMP_VEC, 0, 2287 h.base, h.index, 0, h.ofs); 2288 } else if (cpuinfo & CPUINFO_ATOMIC_VMOVDQU) { 2289 tcg_out_vex_modrm_sib_offset(s, OPC_MOVDQU_WxVx + h.seg, 2290 TCG_TMP_VEC, 0, 2291 h.base, h.index, 0, h.ofs); 2292 } else { 2293 TCGLabel *l1 = gen_new_label(); 2294 TCGLabel *l2 = gen_new_label(); 2295 2296 tcg_out_testi(s, h.base, 15); 2297 tcg_out_jxx(s, JCC_JNE, l1, true); 2298 2299 tcg_out_vex_modrm_sib_offset(s, OPC_MOVDQA_WxVx + h.seg, 2300 TCG_TMP_VEC, 0, 2301 h.base, h.index, 0, h.ofs); 2302 tcg_out_jxx(s, JCC_JMP, l2, true); 2303 2304 tcg_out_label(s, l1); 2305 tcg_out_vex_modrm_sib_offset(s, OPC_MOVDQU_WxVx + h.seg, 2306 TCG_TMP_VEC, 0, 2307 h.base, h.index, 0, h.ofs); 2308 tcg_out_label(s, l2); 2309 } 2310 break; 2311 2312 default: 2313 g_assert_not_reached(); 2314 } 2315} 2316 2317static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, 2318 TCGReg addrlo, TCGReg addrhi, 2319 MemOpIdx oi, TCGType data_type) 2320{ 2321 TCGLabelQemuLdst *ldst; 2322 HostAddress h; 2323 2324 ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, false); 2325 tcg_out_qemu_st_direct(s, datalo, datahi, h, get_memop(oi)); 2326 2327 if (ldst) { 2328 ldst->type = data_type; 2329 ldst->datalo_reg = datalo; 2330 ldst->datahi_reg = datahi; 2331 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 2332 } 2333} 2334 2335static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 2336{ 2337 /* Reuse the zeroing that exists for goto_ptr. */ 2338 if (a0 == 0) { 2339 tcg_out_jmp(s, tcg_code_gen_epilogue); 2340 } else { 2341 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_EAX, a0); 2342 tcg_out_jmp(s, tb_ret_addr); 2343 } 2344} 2345 2346static void tcg_out_goto_tb(TCGContext *s, int which) 2347{ 2348 /* 2349 * Jump displacement must be aligned for atomic patching; 2350 * see if we need to add extra nops before jump 2351 */ 2352 int gap = QEMU_ALIGN_PTR_UP(s->code_ptr + 1, 4) - s->code_ptr; 2353 if (gap != 1) { 2354 tcg_out_nopn(s, gap - 1); 2355 } 2356 tcg_out8(s, OPC_JMP_long); /* jmp im */ 2357 set_jmp_insn_offset(s, which); 2358 tcg_out32(s, 0); 2359 set_jmp_reset_offset(s, which); 2360} 2361 2362void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 2363 uintptr_t jmp_rx, uintptr_t jmp_rw) 2364{ 2365 /* patch the branch destination */ 2366 uintptr_t addr = tb->jmp_target_addr[n]; 2367 qatomic_set((int32_t *)jmp_rw, addr - (jmp_rx + 4)); 2368 /* no need to flush icache explicitly */ 2369} 2370 2371static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, 2372 const TCGArg args[TCG_MAX_OP_ARGS], 2373 const int const_args[TCG_MAX_OP_ARGS]) 2374{ 2375 TCGArg a0, a1, a2; 2376 int c, const_a2, vexop, rexw = 0; 2377 2378#if TCG_TARGET_REG_BITS == 64 2379# define OP_32_64(x) \ 2380 case glue(glue(INDEX_op_, x), _i64): \ 2381 rexw = P_REXW; /* FALLTHRU */ \ 2382 case glue(glue(INDEX_op_, x), _i32) 2383#else 2384# define OP_32_64(x) \ 2385 case glue(glue(INDEX_op_, x), _i32) 2386#endif 2387 2388 /* Hoist the loads of the most common arguments. */ 2389 a0 = args[0]; 2390 a1 = args[1]; 2391 a2 = args[2]; 2392 const_a2 = const_args[2]; 2393 2394 switch (opc) { 2395 case INDEX_op_goto_ptr: 2396 /* jmp to the given host address (could be epilogue) */ 2397 tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, a0); 2398 break; 2399 case INDEX_op_br: 2400 tcg_out_jxx(s, JCC_JMP, arg_label(a0), 0); 2401 break; 2402 OP_32_64(ld8u): 2403 /* Note that we can ignore REXW for the zero-extend to 64-bit. */ 2404 tcg_out_modrm_offset(s, OPC_MOVZBL, a0, a1, a2); 2405 break; 2406 OP_32_64(ld8s): 2407 tcg_out_modrm_offset(s, OPC_MOVSBL + rexw, a0, a1, a2); 2408 break; 2409 OP_32_64(ld16u): 2410 /* Note that we can ignore REXW for the zero-extend to 64-bit. */ 2411 tcg_out_modrm_offset(s, OPC_MOVZWL, a0, a1, a2); 2412 break; 2413 OP_32_64(ld16s): 2414 tcg_out_modrm_offset(s, OPC_MOVSWL + rexw, a0, a1, a2); 2415 break; 2416#if TCG_TARGET_REG_BITS == 64 2417 case INDEX_op_ld32u_i64: 2418#endif 2419 case INDEX_op_ld_i32: 2420 tcg_out_ld(s, TCG_TYPE_I32, a0, a1, a2); 2421 break; 2422 2423 OP_32_64(st8): 2424 if (const_args[0]) { 2425 tcg_out_modrm_offset(s, OPC_MOVB_EvIz, 0, a1, a2); 2426 tcg_out8(s, a0); 2427 } else { 2428 tcg_out_modrm_offset(s, OPC_MOVB_EvGv | P_REXB_R, a0, a1, a2); 2429 } 2430 break; 2431 OP_32_64(st16): 2432 if (const_args[0]) { 2433 tcg_out_modrm_offset(s, OPC_MOVL_EvIz | P_DATA16, 0, a1, a2); 2434 tcg_out16(s, a0); 2435 } else { 2436 tcg_out_modrm_offset(s, OPC_MOVL_EvGv | P_DATA16, a0, a1, a2); 2437 } 2438 break; 2439#if TCG_TARGET_REG_BITS == 64 2440 case INDEX_op_st32_i64: 2441#endif 2442 case INDEX_op_st_i32: 2443 if (const_args[0]) { 2444 tcg_out_modrm_offset(s, OPC_MOVL_EvIz, 0, a1, a2); 2445 tcg_out32(s, a0); 2446 } else { 2447 tcg_out_st(s, TCG_TYPE_I32, a0, a1, a2); 2448 } 2449 break; 2450 2451 OP_32_64(add): 2452 /* For 3-operand addition, use LEA. */ 2453 if (a0 != a1) { 2454 TCGArg c3 = 0; 2455 if (const_a2) { 2456 c3 = a2, a2 = -1; 2457 } else if (a0 == a2) { 2458 /* Watch out for dest = src + dest, since we've removed 2459 the matching constraint on the add. */ 2460 tgen_arithr(s, ARITH_ADD + rexw, a0, a1); 2461 break; 2462 } 2463 2464 tcg_out_modrm_sib_offset(s, OPC_LEA + rexw, a0, a1, a2, 0, c3); 2465 break; 2466 } 2467 c = ARITH_ADD; 2468 goto gen_arith; 2469 OP_32_64(sub): 2470 c = ARITH_SUB; 2471 goto gen_arith; 2472 OP_32_64(and): 2473 c = ARITH_AND; 2474 goto gen_arith; 2475 OP_32_64(or): 2476 c = ARITH_OR; 2477 goto gen_arith; 2478 OP_32_64(xor): 2479 c = ARITH_XOR; 2480 goto gen_arith; 2481 gen_arith: 2482 if (const_a2) { 2483 tgen_arithi(s, c + rexw, a0, a2, 0); 2484 } else { 2485 tgen_arithr(s, c + rexw, a0, a2); 2486 } 2487 break; 2488 2489 OP_32_64(andc): 2490 if (const_a2) { 2491 tcg_out_mov(s, rexw ? TCG_TYPE_I64 : TCG_TYPE_I32, a0, a1); 2492 tgen_arithi(s, ARITH_AND + rexw, a0, ~a2, 0); 2493 } else { 2494 tcg_out_vex_modrm(s, OPC_ANDN + rexw, a0, a2, a1); 2495 } 2496 break; 2497 2498 OP_32_64(mul): 2499 if (const_a2) { 2500 int32_t val; 2501 val = a2; 2502 if (val == (int8_t)val) { 2503 tcg_out_modrm(s, OPC_IMUL_GvEvIb + rexw, a0, a0); 2504 tcg_out8(s, val); 2505 } else { 2506 tcg_out_modrm(s, OPC_IMUL_GvEvIz + rexw, a0, a0); 2507 tcg_out32(s, val); 2508 } 2509 } else { 2510 tcg_out_modrm(s, OPC_IMUL_GvEv + rexw, a0, a2); 2511 } 2512 break; 2513 2514 OP_32_64(div2): 2515 tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_IDIV, args[4]); 2516 break; 2517 OP_32_64(divu2): 2518 tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_DIV, args[4]); 2519 break; 2520 2521 OP_32_64(shl): 2522 /* For small constant 3-operand shift, use LEA. */ 2523 if (const_a2 && a0 != a1 && (a2 - 1) < 3) { 2524 if (a2 - 1 == 0) { 2525 /* shl $1,a1,a0 -> lea (a1,a1),a0 */ 2526 tcg_out_modrm_sib_offset(s, OPC_LEA + rexw, a0, a1, a1, 0, 0); 2527 } else { 2528 /* shl $n,a1,a0 -> lea 0(,a1,n),a0 */ 2529 tcg_out_modrm_sib_offset(s, OPC_LEA + rexw, a0, -1, a1, a2, 0); 2530 } 2531 break; 2532 } 2533 c = SHIFT_SHL; 2534 vexop = OPC_SHLX; 2535 goto gen_shift_maybe_vex; 2536 OP_32_64(shr): 2537 c = SHIFT_SHR; 2538 vexop = OPC_SHRX; 2539 goto gen_shift_maybe_vex; 2540 OP_32_64(sar): 2541 c = SHIFT_SAR; 2542 vexop = OPC_SARX; 2543 goto gen_shift_maybe_vex; 2544 OP_32_64(rotl): 2545 c = SHIFT_ROL; 2546 goto gen_shift; 2547 OP_32_64(rotr): 2548 c = SHIFT_ROR; 2549 goto gen_shift; 2550 gen_shift_maybe_vex: 2551 if (have_bmi2) { 2552 if (!const_a2) { 2553 tcg_out_vex_modrm(s, vexop + rexw, a0, a2, a1); 2554 break; 2555 } 2556 tcg_out_mov(s, rexw ? TCG_TYPE_I64 : TCG_TYPE_I32, a0, a1); 2557 } 2558 /* FALLTHRU */ 2559 gen_shift: 2560 if (const_a2) { 2561 tcg_out_shifti(s, c + rexw, a0, a2); 2562 } else { 2563 tcg_out_modrm(s, OPC_SHIFT_cl + rexw, c, a0); 2564 } 2565 break; 2566 2567 OP_32_64(ctz): 2568 tcg_out_ctz(s, rexw, args[0], args[1], args[2], const_args[2]); 2569 break; 2570 OP_32_64(clz): 2571 tcg_out_clz(s, rexw, args[0], args[1], args[2], const_args[2]); 2572 break; 2573 OP_32_64(ctpop): 2574 tcg_out_modrm(s, OPC_POPCNT + rexw, a0, a1); 2575 break; 2576 2577 case INDEX_op_brcond_i32: 2578 tcg_out_brcond32(s, a2, a0, a1, const_args[1], arg_label(args[3]), 0); 2579 break; 2580 case INDEX_op_setcond_i32: 2581 tcg_out_setcond32(s, args[3], a0, a1, a2, const_a2); 2582 break; 2583 case INDEX_op_movcond_i32: 2584 tcg_out_movcond32(s, args[5], a0, a1, a2, const_a2, args[3]); 2585 break; 2586 2587 OP_32_64(bswap16): 2588 if (a2 & TCG_BSWAP_OS) { 2589 /* Output must be sign-extended. */ 2590 if (rexw) { 2591 tcg_out_bswap64(s, a0); 2592 tcg_out_shifti(s, SHIFT_SAR + rexw, a0, 48); 2593 } else { 2594 tcg_out_bswap32(s, a0); 2595 tcg_out_shifti(s, SHIFT_SAR, a0, 16); 2596 } 2597 } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 2598 /* Output must be zero-extended, but input isn't. */ 2599 tcg_out_bswap32(s, a0); 2600 tcg_out_shifti(s, SHIFT_SHR, a0, 16); 2601 } else { 2602 tcg_out_rolw_8(s, a0); 2603 } 2604 break; 2605 OP_32_64(bswap32): 2606 tcg_out_bswap32(s, a0); 2607 if (rexw && (a2 & TCG_BSWAP_OS)) { 2608 tcg_out_ext32s(s, a0, a0); 2609 } 2610 break; 2611 2612 OP_32_64(neg): 2613 tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NEG, a0); 2614 break; 2615 OP_32_64(not): 2616 tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NOT, a0); 2617 break; 2618 2619 case INDEX_op_qemu_ld_a64_i32: 2620 if (TCG_TARGET_REG_BITS == 32) { 2621 tcg_out_qemu_ld(s, a0, -1, a1, a2, args[3], TCG_TYPE_I32); 2622 break; 2623 } 2624 /* fall through */ 2625 case INDEX_op_qemu_ld_a32_i32: 2626 tcg_out_qemu_ld(s, a0, -1, a1, -1, a2, TCG_TYPE_I32); 2627 break; 2628 case INDEX_op_qemu_ld_a32_i64: 2629 if (TCG_TARGET_REG_BITS == 64) { 2630 tcg_out_qemu_ld(s, a0, -1, a1, -1, a2, TCG_TYPE_I64); 2631 } else { 2632 tcg_out_qemu_ld(s, a0, a1, a2, -1, args[3], TCG_TYPE_I64); 2633 } 2634 break; 2635 case INDEX_op_qemu_ld_a64_i64: 2636 if (TCG_TARGET_REG_BITS == 64) { 2637 tcg_out_qemu_ld(s, a0, -1, a1, -1, a2, TCG_TYPE_I64); 2638 } else { 2639 tcg_out_qemu_ld(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64); 2640 } 2641 break; 2642 case INDEX_op_qemu_ld_a32_i128: 2643 case INDEX_op_qemu_ld_a64_i128: 2644 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 2645 tcg_out_qemu_ld(s, a0, a1, a2, -1, args[3], TCG_TYPE_I128); 2646 break; 2647 2648 case INDEX_op_qemu_st_a64_i32: 2649 case INDEX_op_qemu_st8_a64_i32: 2650 if (TCG_TARGET_REG_BITS == 32) { 2651 tcg_out_qemu_st(s, a0, -1, a1, a2, args[3], TCG_TYPE_I32); 2652 break; 2653 } 2654 /* fall through */ 2655 case INDEX_op_qemu_st_a32_i32: 2656 case INDEX_op_qemu_st8_a32_i32: 2657 tcg_out_qemu_st(s, a0, -1, a1, -1, a2, TCG_TYPE_I32); 2658 break; 2659 case INDEX_op_qemu_st_a32_i64: 2660 if (TCG_TARGET_REG_BITS == 64) { 2661 tcg_out_qemu_st(s, a0, -1, a1, -1, a2, TCG_TYPE_I64); 2662 } else { 2663 tcg_out_qemu_st(s, a0, a1, a2, -1, args[3], TCG_TYPE_I64); 2664 } 2665 break; 2666 case INDEX_op_qemu_st_a64_i64: 2667 if (TCG_TARGET_REG_BITS == 64) { 2668 tcg_out_qemu_st(s, a0, -1, a1, -1, a2, TCG_TYPE_I64); 2669 } else { 2670 tcg_out_qemu_st(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64); 2671 } 2672 break; 2673 case INDEX_op_qemu_st_a32_i128: 2674 case INDEX_op_qemu_st_a64_i128: 2675 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 2676 tcg_out_qemu_st(s, a0, a1, a2, -1, args[3], TCG_TYPE_I128); 2677 break; 2678 2679 OP_32_64(mulu2): 2680 tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_MUL, args[3]); 2681 break; 2682 OP_32_64(muls2): 2683 tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_IMUL, args[3]); 2684 break; 2685 OP_32_64(add2): 2686 if (const_args[4]) { 2687 tgen_arithi(s, ARITH_ADD + rexw, a0, args[4], 1); 2688 } else { 2689 tgen_arithr(s, ARITH_ADD + rexw, a0, args[4]); 2690 } 2691 if (const_args[5]) { 2692 tgen_arithi(s, ARITH_ADC + rexw, a1, args[5], 1); 2693 } else { 2694 tgen_arithr(s, ARITH_ADC + rexw, a1, args[5]); 2695 } 2696 break; 2697 OP_32_64(sub2): 2698 if (const_args[4]) { 2699 tgen_arithi(s, ARITH_SUB + rexw, a0, args[4], 1); 2700 } else { 2701 tgen_arithr(s, ARITH_SUB + rexw, a0, args[4]); 2702 } 2703 if (const_args[5]) { 2704 tgen_arithi(s, ARITH_SBB + rexw, a1, args[5], 1); 2705 } else { 2706 tgen_arithr(s, ARITH_SBB + rexw, a1, args[5]); 2707 } 2708 break; 2709 2710#if TCG_TARGET_REG_BITS == 32 2711 case INDEX_op_brcond2_i32: 2712 tcg_out_brcond2(s, args, const_args, 0); 2713 break; 2714 case INDEX_op_setcond2_i32: 2715 tcg_out_setcond2(s, args, const_args); 2716 break; 2717#else /* TCG_TARGET_REG_BITS == 64 */ 2718 case INDEX_op_ld32s_i64: 2719 tcg_out_modrm_offset(s, OPC_MOVSLQ, a0, a1, a2); 2720 break; 2721 case INDEX_op_ld_i64: 2722 tcg_out_ld(s, TCG_TYPE_I64, a0, a1, a2); 2723 break; 2724 case INDEX_op_st_i64: 2725 if (const_args[0]) { 2726 tcg_out_modrm_offset(s, OPC_MOVL_EvIz | P_REXW, 0, a1, a2); 2727 tcg_out32(s, a0); 2728 } else { 2729 tcg_out_st(s, TCG_TYPE_I64, a0, a1, a2); 2730 } 2731 break; 2732 2733 case INDEX_op_brcond_i64: 2734 tcg_out_brcond64(s, a2, a0, a1, const_args[1], arg_label(args[3]), 0); 2735 break; 2736 case INDEX_op_setcond_i64: 2737 tcg_out_setcond64(s, args[3], a0, a1, a2, const_a2); 2738 break; 2739 case INDEX_op_movcond_i64: 2740 tcg_out_movcond64(s, args[5], a0, a1, a2, const_a2, args[3]); 2741 break; 2742 2743 case INDEX_op_bswap64_i64: 2744 tcg_out_bswap64(s, a0); 2745 break; 2746 case INDEX_op_extrh_i64_i32: 2747 tcg_out_shifti(s, SHIFT_SHR + P_REXW, a0, 32); 2748 break; 2749#endif 2750 2751 OP_32_64(deposit): 2752 if (args[3] == 0 && args[4] == 8) { 2753 /* load bits 0..7 */ 2754 if (const_a2) { 2755 tcg_out_opc(s, OPC_MOVB_Ib | P_REXB_RM | LOWREGMASK(a0), 2756 0, a0, 0); 2757 tcg_out8(s, a2); 2758 } else { 2759 tcg_out_modrm(s, OPC_MOVB_EvGv | P_REXB_R | P_REXB_RM, a2, a0); 2760 } 2761 } else if (TCG_TARGET_REG_BITS == 32 && args[3] == 8 && args[4] == 8) { 2762 /* load bits 8..15 */ 2763 if (const_a2) { 2764 tcg_out8(s, OPC_MOVB_Ib + a0 + 4); 2765 tcg_out8(s, a2); 2766 } else { 2767 tcg_out_modrm(s, OPC_MOVB_EvGv, a2, a0 + 4); 2768 } 2769 } else if (args[3] == 0 && args[4] == 16) { 2770 /* load bits 0..15 */ 2771 if (const_a2) { 2772 tcg_out_opc(s, OPC_MOVL_Iv | P_DATA16 | LOWREGMASK(a0), 2773 0, a0, 0); 2774 tcg_out16(s, a2); 2775 } else { 2776 tcg_out_modrm(s, OPC_MOVL_EvGv | P_DATA16, a2, a0); 2777 } 2778 } else { 2779 g_assert_not_reached(); 2780 } 2781 break; 2782 2783 case INDEX_op_extract_i64: 2784 if (a2 + args[3] == 32) { 2785 /* This is a 32-bit zero-extending right shift. */ 2786 tcg_out_mov(s, TCG_TYPE_I32, a0, a1); 2787 tcg_out_shifti(s, SHIFT_SHR, a0, a2); 2788 break; 2789 } 2790 /* FALLTHRU */ 2791 case INDEX_op_extract_i32: 2792 /* On the off-chance that we can use the high-byte registers. 2793 Otherwise we emit the same ext16 + shift pattern that we 2794 would have gotten from the normal tcg-op.c expansion. */ 2795 tcg_debug_assert(a2 == 8 && args[3] == 8); 2796 if (a1 < 4 && a0 < 8) { 2797 tcg_out_modrm(s, OPC_MOVZBL, a0, a1 + 4); 2798 } else { 2799 tcg_out_ext16u(s, a0, a1); 2800 tcg_out_shifti(s, SHIFT_SHR, a0, 8); 2801 } 2802 break; 2803 2804 case INDEX_op_sextract_i32: 2805 /* We don't implement sextract_i64, as we cannot sign-extend to 2806 64-bits without using the REX prefix that explicitly excludes 2807 access to the high-byte registers. */ 2808 tcg_debug_assert(a2 == 8 && args[3] == 8); 2809 if (a1 < 4 && a0 < 8) { 2810 tcg_out_modrm(s, OPC_MOVSBL, a0, a1 + 4); 2811 } else { 2812 tcg_out_ext16s(s, TCG_TYPE_I32, a0, a1); 2813 tcg_out_shifti(s, SHIFT_SAR, a0, 8); 2814 } 2815 break; 2816 2817 OP_32_64(extract2): 2818 /* Note that SHRD outputs to the r/m operand. */ 2819 tcg_out_modrm(s, OPC_SHRD_Ib + rexw, a2, a0); 2820 tcg_out8(s, args[3]); 2821 break; 2822 2823 case INDEX_op_mb: 2824 tcg_out_mb(s, a0); 2825 break; 2826 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ 2827 case INDEX_op_mov_i64: 2828 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2829 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2830 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2831 case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ 2832 case INDEX_op_ext8s_i64: 2833 case INDEX_op_ext8u_i32: 2834 case INDEX_op_ext8u_i64: 2835 case INDEX_op_ext16s_i32: 2836 case INDEX_op_ext16s_i64: 2837 case INDEX_op_ext16u_i32: 2838 case INDEX_op_ext16u_i64: 2839 case INDEX_op_ext32s_i64: 2840 case INDEX_op_ext32u_i64: 2841 case INDEX_op_ext_i32_i64: 2842 case INDEX_op_extu_i32_i64: 2843 case INDEX_op_extrl_i64_i32: 2844 default: 2845 g_assert_not_reached(); 2846 } 2847 2848#undef OP_32_64 2849} 2850 2851static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 2852 unsigned vecl, unsigned vece, 2853 const TCGArg args[TCG_MAX_OP_ARGS], 2854 const int const_args[TCG_MAX_OP_ARGS]) 2855{ 2856 static int const add_insn[4] = { 2857 OPC_PADDB, OPC_PADDW, OPC_PADDD, OPC_PADDQ 2858 }; 2859 static int const ssadd_insn[4] = { 2860 OPC_PADDSB, OPC_PADDSW, OPC_UD2, OPC_UD2 2861 }; 2862 static int const usadd_insn[4] = { 2863 OPC_PADDUB, OPC_PADDUW, OPC_UD2, OPC_UD2 2864 }; 2865 static int const sub_insn[4] = { 2866 OPC_PSUBB, OPC_PSUBW, OPC_PSUBD, OPC_PSUBQ 2867 }; 2868 static int const sssub_insn[4] = { 2869 OPC_PSUBSB, OPC_PSUBSW, OPC_UD2, OPC_UD2 2870 }; 2871 static int const ussub_insn[4] = { 2872 OPC_PSUBUB, OPC_PSUBUW, OPC_UD2, OPC_UD2 2873 }; 2874 static int const mul_insn[4] = { 2875 OPC_UD2, OPC_PMULLW, OPC_PMULLD, OPC_VPMULLQ 2876 }; 2877 static int const shift_imm_insn[4] = { 2878 OPC_UD2, OPC_PSHIFTW_Ib, OPC_PSHIFTD_Ib, OPC_PSHIFTQ_Ib 2879 }; 2880 static int const cmpeq_insn[4] = { 2881 OPC_PCMPEQB, OPC_PCMPEQW, OPC_PCMPEQD, OPC_PCMPEQQ 2882 }; 2883 static int const cmpgt_insn[4] = { 2884 OPC_PCMPGTB, OPC_PCMPGTW, OPC_PCMPGTD, OPC_PCMPGTQ 2885 }; 2886 static int const punpckl_insn[4] = { 2887 OPC_PUNPCKLBW, OPC_PUNPCKLWD, OPC_PUNPCKLDQ, OPC_PUNPCKLQDQ 2888 }; 2889 static int const punpckh_insn[4] = { 2890 OPC_PUNPCKHBW, OPC_PUNPCKHWD, OPC_PUNPCKHDQ, OPC_PUNPCKHQDQ 2891 }; 2892 static int const packss_insn[4] = { 2893 OPC_PACKSSWB, OPC_PACKSSDW, OPC_UD2, OPC_UD2 2894 }; 2895 static int const packus_insn[4] = { 2896 OPC_PACKUSWB, OPC_PACKUSDW, OPC_UD2, OPC_UD2 2897 }; 2898 static int const smin_insn[4] = { 2899 OPC_PMINSB, OPC_PMINSW, OPC_PMINSD, OPC_VPMINSQ 2900 }; 2901 static int const smax_insn[4] = { 2902 OPC_PMAXSB, OPC_PMAXSW, OPC_PMAXSD, OPC_VPMAXSQ 2903 }; 2904 static int const umin_insn[4] = { 2905 OPC_PMINUB, OPC_PMINUW, OPC_PMINUD, OPC_VPMINUQ 2906 }; 2907 static int const umax_insn[4] = { 2908 OPC_PMAXUB, OPC_PMAXUW, OPC_PMAXUD, OPC_VPMAXUQ 2909 }; 2910 static int const rotlv_insn[4] = { 2911 OPC_UD2, OPC_UD2, OPC_VPROLVD, OPC_VPROLVQ 2912 }; 2913 static int const rotrv_insn[4] = { 2914 OPC_UD2, OPC_UD2, OPC_VPRORVD, OPC_VPRORVQ 2915 }; 2916 static int const shlv_insn[4] = { 2917 OPC_UD2, OPC_VPSLLVW, OPC_VPSLLVD, OPC_VPSLLVQ 2918 }; 2919 static int const shrv_insn[4] = { 2920 OPC_UD2, OPC_VPSRLVW, OPC_VPSRLVD, OPC_VPSRLVQ 2921 }; 2922 static int const sarv_insn[4] = { 2923 OPC_UD2, OPC_VPSRAVW, OPC_VPSRAVD, OPC_VPSRAVQ 2924 }; 2925 static int const shls_insn[4] = { 2926 OPC_UD2, OPC_PSLLW, OPC_PSLLD, OPC_PSLLQ 2927 }; 2928 static int const shrs_insn[4] = { 2929 OPC_UD2, OPC_PSRLW, OPC_PSRLD, OPC_PSRLQ 2930 }; 2931 static int const sars_insn[4] = { 2932 OPC_UD2, OPC_PSRAW, OPC_PSRAD, OPC_VPSRAQ 2933 }; 2934 static int const vpshldi_insn[4] = { 2935 OPC_UD2, OPC_VPSHLDW, OPC_VPSHLDD, OPC_VPSHLDQ 2936 }; 2937 static int const vpshldv_insn[4] = { 2938 OPC_UD2, OPC_VPSHLDVW, OPC_VPSHLDVD, OPC_VPSHLDVQ 2939 }; 2940 static int const vpshrdv_insn[4] = { 2941 OPC_UD2, OPC_VPSHRDVW, OPC_VPSHRDVD, OPC_VPSHRDVQ 2942 }; 2943 static int const abs_insn[4] = { 2944 OPC_PABSB, OPC_PABSW, OPC_PABSD, OPC_VPABSQ 2945 }; 2946 2947 TCGType type = vecl + TCG_TYPE_V64; 2948 int insn, sub; 2949 TCGArg a0, a1, a2, a3; 2950 2951 a0 = args[0]; 2952 a1 = args[1]; 2953 a2 = args[2]; 2954 2955 switch (opc) { 2956 case INDEX_op_add_vec: 2957 insn = add_insn[vece]; 2958 goto gen_simd; 2959 case INDEX_op_ssadd_vec: 2960 insn = ssadd_insn[vece]; 2961 goto gen_simd; 2962 case INDEX_op_usadd_vec: 2963 insn = usadd_insn[vece]; 2964 goto gen_simd; 2965 case INDEX_op_sub_vec: 2966 insn = sub_insn[vece]; 2967 goto gen_simd; 2968 case INDEX_op_sssub_vec: 2969 insn = sssub_insn[vece]; 2970 goto gen_simd; 2971 case INDEX_op_ussub_vec: 2972 insn = ussub_insn[vece]; 2973 goto gen_simd; 2974 case INDEX_op_mul_vec: 2975 insn = mul_insn[vece]; 2976 goto gen_simd; 2977 case INDEX_op_and_vec: 2978 insn = OPC_PAND; 2979 goto gen_simd; 2980 case INDEX_op_or_vec: 2981 insn = OPC_POR; 2982 goto gen_simd; 2983 case INDEX_op_xor_vec: 2984 insn = OPC_PXOR; 2985 goto gen_simd; 2986 case INDEX_op_smin_vec: 2987 insn = smin_insn[vece]; 2988 goto gen_simd; 2989 case INDEX_op_umin_vec: 2990 insn = umin_insn[vece]; 2991 goto gen_simd; 2992 case INDEX_op_smax_vec: 2993 insn = smax_insn[vece]; 2994 goto gen_simd; 2995 case INDEX_op_umax_vec: 2996 insn = umax_insn[vece]; 2997 goto gen_simd; 2998 case INDEX_op_shlv_vec: 2999 insn = shlv_insn[vece]; 3000 goto gen_simd; 3001 case INDEX_op_shrv_vec: 3002 insn = shrv_insn[vece]; 3003 goto gen_simd; 3004 case INDEX_op_sarv_vec: 3005 insn = sarv_insn[vece]; 3006 goto gen_simd; 3007 case INDEX_op_rotlv_vec: 3008 insn = rotlv_insn[vece]; 3009 goto gen_simd; 3010 case INDEX_op_rotrv_vec: 3011 insn = rotrv_insn[vece]; 3012 goto gen_simd; 3013 case INDEX_op_shls_vec: 3014 insn = shls_insn[vece]; 3015 goto gen_simd; 3016 case INDEX_op_shrs_vec: 3017 insn = shrs_insn[vece]; 3018 goto gen_simd; 3019 case INDEX_op_sars_vec: 3020 insn = sars_insn[vece]; 3021 goto gen_simd; 3022 case INDEX_op_x86_punpckl_vec: 3023 insn = punpckl_insn[vece]; 3024 goto gen_simd; 3025 case INDEX_op_x86_punpckh_vec: 3026 insn = punpckh_insn[vece]; 3027 goto gen_simd; 3028 case INDEX_op_x86_packss_vec: 3029 insn = packss_insn[vece]; 3030 goto gen_simd; 3031 case INDEX_op_x86_packus_vec: 3032 insn = packus_insn[vece]; 3033 goto gen_simd; 3034 case INDEX_op_x86_vpshldv_vec: 3035 insn = vpshldv_insn[vece]; 3036 a1 = a2; 3037 a2 = args[3]; 3038 goto gen_simd; 3039 case INDEX_op_x86_vpshrdv_vec: 3040 insn = vpshrdv_insn[vece]; 3041 a1 = a2; 3042 a2 = args[3]; 3043 goto gen_simd; 3044#if TCG_TARGET_REG_BITS == 32 3045 case INDEX_op_dup2_vec: 3046 /* First merge the two 32-bit inputs to a single 64-bit element. */ 3047 tcg_out_vex_modrm(s, OPC_PUNPCKLDQ, a0, a1, a2); 3048 /* Then replicate the 64-bit elements across the rest of the vector. */ 3049 if (type != TCG_TYPE_V64) { 3050 tcg_out_dup_vec(s, type, MO_64, a0, a0); 3051 } 3052 break; 3053#endif 3054 case INDEX_op_abs_vec: 3055 insn = abs_insn[vece]; 3056 a2 = a1; 3057 a1 = 0; 3058 goto gen_simd; 3059 gen_simd: 3060 tcg_debug_assert(insn != OPC_UD2); 3061 if (type == TCG_TYPE_V256) { 3062 insn |= P_VEXL; 3063 } 3064 tcg_out_vex_modrm(s, insn, a0, a1, a2); 3065 break; 3066 3067 case INDEX_op_cmp_vec: 3068 sub = args[3]; 3069 if (sub == TCG_COND_EQ) { 3070 insn = cmpeq_insn[vece]; 3071 } else if (sub == TCG_COND_GT) { 3072 insn = cmpgt_insn[vece]; 3073 } else { 3074 g_assert_not_reached(); 3075 } 3076 goto gen_simd; 3077 3078 case INDEX_op_andc_vec: 3079 insn = OPC_PANDN; 3080 if (type == TCG_TYPE_V256) { 3081 insn |= P_VEXL; 3082 } 3083 tcg_out_vex_modrm(s, insn, a0, a2, a1); 3084 break; 3085 3086 case INDEX_op_shli_vec: 3087 insn = shift_imm_insn[vece]; 3088 sub = 6; 3089 goto gen_shift; 3090 case INDEX_op_shri_vec: 3091 insn = shift_imm_insn[vece]; 3092 sub = 2; 3093 goto gen_shift; 3094 case INDEX_op_sari_vec: 3095 if (vece == MO_64) { 3096 insn = OPC_PSHIFTD_Ib | P_VEXW | P_EVEX; 3097 } else { 3098 insn = shift_imm_insn[vece]; 3099 } 3100 sub = 4; 3101 goto gen_shift; 3102 case INDEX_op_rotli_vec: 3103 insn = OPC_PSHIFTD_Ib | P_EVEX; /* VPROL[DQ] */ 3104 if (vece == MO_64) { 3105 insn |= P_VEXW; 3106 } 3107 sub = 1; 3108 goto gen_shift; 3109 gen_shift: 3110 tcg_debug_assert(vece != MO_8); 3111 if (type == TCG_TYPE_V256) { 3112 insn |= P_VEXL; 3113 } 3114 tcg_out_vex_modrm(s, insn, sub, a0, a1); 3115 tcg_out8(s, a2); 3116 break; 3117 3118 case INDEX_op_ld_vec: 3119 tcg_out_ld(s, type, a0, a1, a2); 3120 break; 3121 case INDEX_op_st_vec: 3122 tcg_out_st(s, type, a0, a1, a2); 3123 break; 3124 case INDEX_op_dupm_vec: 3125 tcg_out_dupm_vec(s, type, vece, a0, a1, a2); 3126 break; 3127 3128 case INDEX_op_x86_shufps_vec: 3129 insn = OPC_SHUFPS; 3130 sub = args[3]; 3131 goto gen_simd_imm8; 3132 case INDEX_op_x86_blend_vec: 3133 if (vece == MO_16) { 3134 insn = OPC_PBLENDW; 3135 } else if (vece == MO_32) { 3136 insn = (have_avx2 ? OPC_VPBLENDD : OPC_BLENDPS); 3137 } else { 3138 g_assert_not_reached(); 3139 } 3140 sub = args[3]; 3141 goto gen_simd_imm8; 3142 case INDEX_op_x86_vperm2i128_vec: 3143 insn = OPC_VPERM2I128; 3144 sub = args[3]; 3145 goto gen_simd_imm8; 3146 case INDEX_op_x86_vpshldi_vec: 3147 insn = vpshldi_insn[vece]; 3148 sub = args[3]; 3149 goto gen_simd_imm8; 3150 3151 case INDEX_op_not_vec: 3152 insn = OPC_VPTERNLOGQ; 3153 a2 = a1; 3154 sub = 0x33; /* !B */ 3155 goto gen_simd_imm8; 3156 case INDEX_op_nor_vec: 3157 insn = OPC_VPTERNLOGQ; 3158 sub = 0x11; /* norCB */ 3159 goto gen_simd_imm8; 3160 case INDEX_op_nand_vec: 3161 insn = OPC_VPTERNLOGQ; 3162 sub = 0x77; /* nandCB */ 3163 goto gen_simd_imm8; 3164 case INDEX_op_eqv_vec: 3165 insn = OPC_VPTERNLOGQ; 3166 sub = 0x99; /* xnorCB */ 3167 goto gen_simd_imm8; 3168 case INDEX_op_orc_vec: 3169 insn = OPC_VPTERNLOGQ; 3170 sub = 0xdd; /* orB!C */ 3171 goto gen_simd_imm8; 3172 3173 case INDEX_op_bitsel_vec: 3174 insn = OPC_VPTERNLOGQ; 3175 a3 = args[3]; 3176 if (a0 == a1) { 3177 a1 = a2; 3178 a2 = a3; 3179 sub = 0xca; /* A?B:C */ 3180 } else if (a0 == a2) { 3181 a2 = a3; 3182 sub = 0xe2; /* B?A:C */ 3183 } else { 3184 tcg_out_mov(s, type, a0, a3); 3185 sub = 0xb8; /* B?C:A */ 3186 } 3187 goto gen_simd_imm8; 3188 3189 gen_simd_imm8: 3190 tcg_debug_assert(insn != OPC_UD2); 3191 if (type == TCG_TYPE_V256) { 3192 insn |= P_VEXL; 3193 } 3194 tcg_out_vex_modrm(s, insn, a0, a1, a2); 3195 tcg_out8(s, sub); 3196 break; 3197 3198 case INDEX_op_x86_vpblendvb_vec: 3199 insn = OPC_VPBLENDVB; 3200 if (type == TCG_TYPE_V256) { 3201 insn |= P_VEXL; 3202 } 3203 tcg_out_vex_modrm(s, insn, a0, a1, a2); 3204 tcg_out8(s, args[3] << 4); 3205 break; 3206 3207 case INDEX_op_x86_psrldq_vec: 3208 tcg_out_vex_modrm(s, OPC_GRP14, 3, a0, a1); 3209 tcg_out8(s, a2); 3210 break; 3211 3212 case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ 3213 case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ 3214 default: 3215 g_assert_not_reached(); 3216 } 3217} 3218 3219static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) 3220{ 3221 switch (op) { 3222 case INDEX_op_goto_ptr: 3223 return C_O0_I1(r); 3224 3225 case INDEX_op_ld8u_i32: 3226 case INDEX_op_ld8u_i64: 3227 case INDEX_op_ld8s_i32: 3228 case INDEX_op_ld8s_i64: 3229 case INDEX_op_ld16u_i32: 3230 case INDEX_op_ld16u_i64: 3231 case INDEX_op_ld16s_i32: 3232 case INDEX_op_ld16s_i64: 3233 case INDEX_op_ld_i32: 3234 case INDEX_op_ld32u_i64: 3235 case INDEX_op_ld32s_i64: 3236 case INDEX_op_ld_i64: 3237 return C_O1_I1(r, r); 3238 3239 case INDEX_op_st8_i32: 3240 case INDEX_op_st8_i64: 3241 return C_O0_I2(qi, r); 3242 3243 case INDEX_op_st16_i32: 3244 case INDEX_op_st16_i64: 3245 case INDEX_op_st_i32: 3246 case INDEX_op_st32_i64: 3247 return C_O0_I2(ri, r); 3248 3249 case INDEX_op_st_i64: 3250 return C_O0_I2(re, r); 3251 3252 case INDEX_op_add_i32: 3253 case INDEX_op_add_i64: 3254 return C_O1_I2(r, r, re); 3255 3256 case INDEX_op_sub_i32: 3257 case INDEX_op_sub_i64: 3258 case INDEX_op_mul_i32: 3259 case INDEX_op_mul_i64: 3260 case INDEX_op_or_i32: 3261 case INDEX_op_or_i64: 3262 case INDEX_op_xor_i32: 3263 case INDEX_op_xor_i64: 3264 return C_O1_I2(r, 0, re); 3265 3266 case INDEX_op_and_i32: 3267 case INDEX_op_and_i64: 3268 return C_O1_I2(r, 0, reZ); 3269 3270 case INDEX_op_andc_i32: 3271 case INDEX_op_andc_i64: 3272 return C_O1_I2(r, r, rI); 3273 3274 case INDEX_op_shl_i32: 3275 case INDEX_op_shl_i64: 3276 case INDEX_op_shr_i32: 3277 case INDEX_op_shr_i64: 3278 case INDEX_op_sar_i32: 3279 case INDEX_op_sar_i64: 3280 return have_bmi2 ? C_O1_I2(r, r, ri) : C_O1_I2(r, 0, ci); 3281 3282 case INDEX_op_rotl_i32: 3283 case INDEX_op_rotl_i64: 3284 case INDEX_op_rotr_i32: 3285 case INDEX_op_rotr_i64: 3286 return C_O1_I2(r, 0, ci); 3287 3288 case INDEX_op_brcond_i32: 3289 case INDEX_op_brcond_i64: 3290 return C_O0_I2(r, re); 3291 3292 case INDEX_op_bswap16_i32: 3293 case INDEX_op_bswap16_i64: 3294 case INDEX_op_bswap32_i32: 3295 case INDEX_op_bswap32_i64: 3296 case INDEX_op_bswap64_i64: 3297 case INDEX_op_neg_i32: 3298 case INDEX_op_neg_i64: 3299 case INDEX_op_not_i32: 3300 case INDEX_op_not_i64: 3301 case INDEX_op_extrh_i64_i32: 3302 return C_O1_I1(r, 0); 3303 3304 case INDEX_op_ext8s_i32: 3305 case INDEX_op_ext8s_i64: 3306 case INDEX_op_ext8u_i32: 3307 case INDEX_op_ext8u_i64: 3308 return C_O1_I1(r, q); 3309 3310 case INDEX_op_ext16s_i32: 3311 case INDEX_op_ext16s_i64: 3312 case INDEX_op_ext16u_i32: 3313 case INDEX_op_ext16u_i64: 3314 case INDEX_op_ext32s_i64: 3315 case INDEX_op_ext32u_i64: 3316 case INDEX_op_ext_i32_i64: 3317 case INDEX_op_extu_i32_i64: 3318 case INDEX_op_extrl_i64_i32: 3319 case INDEX_op_extract_i32: 3320 case INDEX_op_extract_i64: 3321 case INDEX_op_sextract_i32: 3322 case INDEX_op_ctpop_i32: 3323 case INDEX_op_ctpop_i64: 3324 return C_O1_I1(r, r); 3325 3326 case INDEX_op_extract2_i32: 3327 case INDEX_op_extract2_i64: 3328 return C_O1_I2(r, 0, r); 3329 3330 case INDEX_op_deposit_i32: 3331 case INDEX_op_deposit_i64: 3332 return C_O1_I2(q, 0, qi); 3333 3334 case INDEX_op_setcond_i32: 3335 case INDEX_op_setcond_i64: 3336 return C_O1_I2(q, r, re); 3337 3338 case INDEX_op_movcond_i32: 3339 case INDEX_op_movcond_i64: 3340 return C_O1_I4(r, r, re, r, 0); 3341 3342 case INDEX_op_div2_i32: 3343 case INDEX_op_div2_i64: 3344 case INDEX_op_divu2_i32: 3345 case INDEX_op_divu2_i64: 3346 return C_O2_I3(a, d, 0, 1, r); 3347 3348 case INDEX_op_mulu2_i32: 3349 case INDEX_op_mulu2_i64: 3350 case INDEX_op_muls2_i32: 3351 case INDEX_op_muls2_i64: 3352 return C_O2_I2(a, d, a, r); 3353 3354 case INDEX_op_add2_i32: 3355 case INDEX_op_add2_i64: 3356 case INDEX_op_sub2_i32: 3357 case INDEX_op_sub2_i64: 3358 return C_N1_O1_I4(r, r, 0, 1, re, re); 3359 3360 case INDEX_op_ctz_i32: 3361 case INDEX_op_ctz_i64: 3362 return have_bmi1 ? C_N1_I2(r, r, rW) : C_N1_I2(r, r, r); 3363 3364 case INDEX_op_clz_i32: 3365 case INDEX_op_clz_i64: 3366 return have_lzcnt ? C_N1_I2(r, r, rW) : C_N1_I2(r, r, r); 3367 3368 case INDEX_op_qemu_ld_a32_i32: 3369 return C_O1_I1(r, L); 3370 case INDEX_op_qemu_ld_a64_i32: 3371 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L) : C_O1_I2(r, L, L); 3372 3373 case INDEX_op_qemu_st_a32_i32: 3374 return C_O0_I2(L, L); 3375 case INDEX_op_qemu_st_a64_i32: 3376 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(L, L) : C_O0_I3(L, L, L); 3377 case INDEX_op_qemu_st8_a32_i32: 3378 return C_O0_I2(s, L); 3379 case INDEX_op_qemu_st8_a64_i32: 3380 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(s, L) : C_O0_I3(s, L, L); 3381 3382 case INDEX_op_qemu_ld_a32_i64: 3383 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L) : C_O2_I1(r, r, L); 3384 case INDEX_op_qemu_ld_a64_i64: 3385 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L) : C_O2_I2(r, r, L, L); 3386 3387 case INDEX_op_qemu_st_a32_i64: 3388 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(L, L) : C_O0_I3(L, L, L); 3389 case INDEX_op_qemu_st_a64_i64: 3390 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(L, L) : C_O0_I4(L, L, L, L); 3391 3392 case INDEX_op_qemu_ld_a32_i128: 3393 case INDEX_op_qemu_ld_a64_i128: 3394 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 3395 return C_O2_I1(r, r, L); 3396 case INDEX_op_qemu_st_a32_i128: 3397 case INDEX_op_qemu_st_a64_i128: 3398 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 3399 return C_O0_I3(L, L, L); 3400 3401 case INDEX_op_brcond2_i32: 3402 return C_O0_I4(r, r, ri, ri); 3403 3404 case INDEX_op_setcond2_i32: 3405 return C_O1_I4(r, r, r, ri, ri); 3406 3407 case INDEX_op_ld_vec: 3408 case INDEX_op_dupm_vec: 3409 return C_O1_I1(x, r); 3410 3411 case INDEX_op_st_vec: 3412 return C_O0_I2(x, r); 3413 3414 case INDEX_op_add_vec: 3415 case INDEX_op_sub_vec: 3416 case INDEX_op_mul_vec: 3417 case INDEX_op_and_vec: 3418 case INDEX_op_or_vec: 3419 case INDEX_op_xor_vec: 3420 case INDEX_op_andc_vec: 3421 case INDEX_op_orc_vec: 3422 case INDEX_op_nand_vec: 3423 case INDEX_op_nor_vec: 3424 case INDEX_op_eqv_vec: 3425 case INDEX_op_ssadd_vec: 3426 case INDEX_op_usadd_vec: 3427 case INDEX_op_sssub_vec: 3428 case INDEX_op_ussub_vec: 3429 case INDEX_op_smin_vec: 3430 case INDEX_op_umin_vec: 3431 case INDEX_op_smax_vec: 3432 case INDEX_op_umax_vec: 3433 case INDEX_op_shlv_vec: 3434 case INDEX_op_shrv_vec: 3435 case INDEX_op_sarv_vec: 3436 case INDEX_op_rotlv_vec: 3437 case INDEX_op_rotrv_vec: 3438 case INDEX_op_shls_vec: 3439 case INDEX_op_shrs_vec: 3440 case INDEX_op_sars_vec: 3441 case INDEX_op_cmp_vec: 3442 case INDEX_op_x86_shufps_vec: 3443 case INDEX_op_x86_blend_vec: 3444 case INDEX_op_x86_packss_vec: 3445 case INDEX_op_x86_packus_vec: 3446 case INDEX_op_x86_vperm2i128_vec: 3447 case INDEX_op_x86_punpckl_vec: 3448 case INDEX_op_x86_punpckh_vec: 3449 case INDEX_op_x86_vpshldi_vec: 3450#if TCG_TARGET_REG_BITS == 32 3451 case INDEX_op_dup2_vec: 3452#endif 3453 return C_O1_I2(x, x, x); 3454 3455 case INDEX_op_abs_vec: 3456 case INDEX_op_dup_vec: 3457 case INDEX_op_not_vec: 3458 case INDEX_op_shli_vec: 3459 case INDEX_op_shri_vec: 3460 case INDEX_op_sari_vec: 3461 case INDEX_op_rotli_vec: 3462 case INDEX_op_x86_psrldq_vec: 3463 return C_O1_I1(x, x); 3464 3465 case INDEX_op_x86_vpshldv_vec: 3466 case INDEX_op_x86_vpshrdv_vec: 3467 return C_O1_I3(x, 0, x, x); 3468 3469 case INDEX_op_bitsel_vec: 3470 case INDEX_op_x86_vpblendvb_vec: 3471 return C_O1_I3(x, x, x, x); 3472 3473 default: 3474 g_assert_not_reached(); 3475 } 3476} 3477 3478int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 3479{ 3480 switch (opc) { 3481 case INDEX_op_add_vec: 3482 case INDEX_op_sub_vec: 3483 case INDEX_op_and_vec: 3484 case INDEX_op_or_vec: 3485 case INDEX_op_xor_vec: 3486 case INDEX_op_andc_vec: 3487 case INDEX_op_orc_vec: 3488 case INDEX_op_nand_vec: 3489 case INDEX_op_nor_vec: 3490 case INDEX_op_eqv_vec: 3491 case INDEX_op_not_vec: 3492 case INDEX_op_bitsel_vec: 3493 return 1; 3494 case INDEX_op_cmp_vec: 3495 case INDEX_op_cmpsel_vec: 3496 return -1; 3497 3498 case INDEX_op_rotli_vec: 3499 return have_avx512vl && vece >= MO_32 ? 1 : -1; 3500 3501 case INDEX_op_shli_vec: 3502 case INDEX_op_shri_vec: 3503 /* We must expand the operation for MO_8. */ 3504 return vece == MO_8 ? -1 : 1; 3505 3506 case INDEX_op_sari_vec: 3507 switch (vece) { 3508 case MO_8: 3509 return -1; 3510 case MO_16: 3511 case MO_32: 3512 return 1; 3513 case MO_64: 3514 if (have_avx512vl) { 3515 return 1; 3516 } 3517 /* 3518 * We can emulate this for MO_64, but it does not pay off 3519 * unless we're producing at least 4 values. 3520 */ 3521 return type >= TCG_TYPE_V256 ? -1 : 0; 3522 } 3523 return 0; 3524 3525 case INDEX_op_shls_vec: 3526 case INDEX_op_shrs_vec: 3527 return vece >= MO_16; 3528 case INDEX_op_sars_vec: 3529 switch (vece) { 3530 case MO_16: 3531 case MO_32: 3532 return 1; 3533 case MO_64: 3534 return have_avx512vl; 3535 } 3536 return 0; 3537 case INDEX_op_rotls_vec: 3538 return vece >= MO_16 ? -1 : 0; 3539 3540 case INDEX_op_shlv_vec: 3541 case INDEX_op_shrv_vec: 3542 switch (vece) { 3543 case MO_16: 3544 return have_avx512bw; 3545 case MO_32: 3546 case MO_64: 3547 return have_avx2; 3548 } 3549 return 0; 3550 case INDEX_op_sarv_vec: 3551 switch (vece) { 3552 case MO_16: 3553 return have_avx512bw; 3554 case MO_32: 3555 return have_avx2; 3556 case MO_64: 3557 return have_avx512vl; 3558 } 3559 return 0; 3560 case INDEX_op_rotlv_vec: 3561 case INDEX_op_rotrv_vec: 3562 switch (vece) { 3563 case MO_16: 3564 return have_avx512vbmi2 ? -1 : 0; 3565 case MO_32: 3566 case MO_64: 3567 return have_avx512vl ? 1 : have_avx2 ? -1 : 0; 3568 } 3569 return 0; 3570 3571 case INDEX_op_mul_vec: 3572 switch (vece) { 3573 case MO_8: 3574 return -1; 3575 case MO_64: 3576 return have_avx512dq; 3577 } 3578 return 1; 3579 3580 case INDEX_op_ssadd_vec: 3581 case INDEX_op_usadd_vec: 3582 case INDEX_op_sssub_vec: 3583 case INDEX_op_ussub_vec: 3584 return vece <= MO_16; 3585 case INDEX_op_smin_vec: 3586 case INDEX_op_smax_vec: 3587 case INDEX_op_umin_vec: 3588 case INDEX_op_umax_vec: 3589 case INDEX_op_abs_vec: 3590 return vece <= MO_32 || have_avx512vl; 3591 3592 default: 3593 return 0; 3594 } 3595} 3596 3597static void expand_vec_shi(TCGType type, unsigned vece, TCGOpcode opc, 3598 TCGv_vec v0, TCGv_vec v1, TCGArg imm) 3599{ 3600 TCGv_vec t1, t2; 3601 3602 tcg_debug_assert(vece == MO_8); 3603 3604 t1 = tcg_temp_new_vec(type); 3605 t2 = tcg_temp_new_vec(type); 3606 3607 /* 3608 * Unpack to W, shift, and repack. Tricky bits: 3609 * (1) Use punpck*bw x,x to produce DDCCBBAA, 3610 * i.e. duplicate in other half of the 16-bit lane. 3611 * (2) For right-shift, add 8 so that the high half of the lane 3612 * becomes zero. For left-shift, and left-rotate, we must 3613 * shift up and down again. 3614 * (3) Step 2 leaves high half zero such that PACKUSWB 3615 * (pack with unsigned saturation) does not modify 3616 * the quantity. 3617 */ 3618 vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8, 3619 tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(v1)); 3620 vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8, 3621 tcgv_vec_arg(t2), tcgv_vec_arg(v1), tcgv_vec_arg(v1)); 3622 3623 if (opc != INDEX_op_rotli_vec) { 3624 imm += 8; 3625 } 3626 if (opc == INDEX_op_shri_vec) { 3627 tcg_gen_shri_vec(MO_16, t1, t1, imm); 3628 tcg_gen_shri_vec(MO_16, t2, t2, imm); 3629 } else { 3630 tcg_gen_shli_vec(MO_16, t1, t1, imm); 3631 tcg_gen_shli_vec(MO_16, t2, t2, imm); 3632 tcg_gen_shri_vec(MO_16, t1, t1, 8); 3633 tcg_gen_shri_vec(MO_16, t2, t2, 8); 3634 } 3635 3636 vec_gen_3(INDEX_op_x86_packus_vec, type, MO_8, 3637 tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t2)); 3638 tcg_temp_free_vec(t1); 3639 tcg_temp_free_vec(t2); 3640} 3641 3642static void expand_vec_sari(TCGType type, unsigned vece, 3643 TCGv_vec v0, TCGv_vec v1, TCGArg imm) 3644{ 3645 TCGv_vec t1, t2; 3646 3647 switch (vece) { 3648 case MO_8: 3649 /* Unpack to W, shift, and repack, as in expand_vec_shi. */ 3650 t1 = tcg_temp_new_vec(type); 3651 t2 = tcg_temp_new_vec(type); 3652 vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8, 3653 tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(v1)); 3654 vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8, 3655 tcgv_vec_arg(t2), tcgv_vec_arg(v1), tcgv_vec_arg(v1)); 3656 tcg_gen_sari_vec(MO_16, t1, t1, imm + 8); 3657 tcg_gen_sari_vec(MO_16, t2, t2, imm + 8); 3658 vec_gen_3(INDEX_op_x86_packss_vec, type, MO_8, 3659 tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t2)); 3660 tcg_temp_free_vec(t1); 3661 tcg_temp_free_vec(t2); 3662 break; 3663 3664 case MO_64: 3665 t1 = tcg_temp_new_vec(type); 3666 if (imm <= 32) { 3667 /* 3668 * We can emulate a small sign extend by performing an arithmetic 3669 * 32-bit shift and overwriting the high half of a 64-bit logical 3670 * shift. Note that the ISA says shift of 32 is valid, but TCG 3671 * does not, so we have to bound the smaller shift -- we get the 3672 * same result in the high half either way. 3673 */ 3674 tcg_gen_sari_vec(MO_32, t1, v1, MIN(imm, 31)); 3675 tcg_gen_shri_vec(MO_64, v0, v1, imm); 3676 vec_gen_4(INDEX_op_x86_blend_vec, type, MO_32, 3677 tcgv_vec_arg(v0), tcgv_vec_arg(v0), 3678 tcgv_vec_arg(t1), 0xaa); 3679 } else { 3680 /* Otherwise we will need to use a compare vs 0 to produce 3681 * the sign-extend, shift and merge. 3682 */ 3683 tcg_gen_cmp_vec(TCG_COND_GT, MO_64, t1, 3684 tcg_constant_vec(type, MO_64, 0), v1); 3685 tcg_gen_shri_vec(MO_64, v0, v1, imm); 3686 tcg_gen_shli_vec(MO_64, t1, t1, 64 - imm); 3687 tcg_gen_or_vec(MO_64, v0, v0, t1); 3688 } 3689 tcg_temp_free_vec(t1); 3690 break; 3691 3692 default: 3693 g_assert_not_reached(); 3694 } 3695} 3696 3697static void expand_vec_rotli(TCGType type, unsigned vece, 3698 TCGv_vec v0, TCGv_vec v1, TCGArg imm) 3699{ 3700 TCGv_vec t; 3701 3702 if (vece == MO_8) { 3703 expand_vec_shi(type, vece, INDEX_op_rotli_vec, v0, v1, imm); 3704 return; 3705 } 3706 3707 if (have_avx512vbmi2) { 3708 vec_gen_4(INDEX_op_x86_vpshldi_vec, type, vece, 3709 tcgv_vec_arg(v0), tcgv_vec_arg(v1), tcgv_vec_arg(v1), imm); 3710 return; 3711 } 3712 3713 t = tcg_temp_new_vec(type); 3714 tcg_gen_shli_vec(vece, t, v1, imm); 3715 tcg_gen_shri_vec(vece, v0, v1, (8 << vece) - imm); 3716 tcg_gen_or_vec(vece, v0, v0, t); 3717 tcg_temp_free_vec(t); 3718} 3719 3720static void expand_vec_rotv(TCGType type, unsigned vece, TCGv_vec v0, 3721 TCGv_vec v1, TCGv_vec sh, bool right) 3722{ 3723 TCGv_vec t; 3724 3725 if (have_avx512vbmi2) { 3726 vec_gen_4(right ? INDEX_op_x86_vpshrdv_vec : INDEX_op_x86_vpshldv_vec, 3727 type, vece, tcgv_vec_arg(v0), tcgv_vec_arg(v1), 3728 tcgv_vec_arg(v1), tcgv_vec_arg(sh)); 3729 return; 3730 } 3731 3732 t = tcg_temp_new_vec(type); 3733 tcg_gen_dupi_vec(vece, t, 8 << vece); 3734 tcg_gen_sub_vec(vece, t, t, sh); 3735 if (right) { 3736 tcg_gen_shlv_vec(vece, t, v1, t); 3737 tcg_gen_shrv_vec(vece, v0, v1, sh); 3738 } else { 3739 tcg_gen_shrv_vec(vece, t, v1, t); 3740 tcg_gen_shlv_vec(vece, v0, v1, sh); 3741 } 3742 tcg_gen_or_vec(vece, v0, v0, t); 3743 tcg_temp_free_vec(t); 3744} 3745 3746static void expand_vec_rotls(TCGType type, unsigned vece, 3747 TCGv_vec v0, TCGv_vec v1, TCGv_i32 lsh) 3748{ 3749 TCGv_vec t = tcg_temp_new_vec(type); 3750 3751 tcg_debug_assert(vece != MO_8); 3752 3753 if (vece >= MO_32 ? have_avx512vl : have_avx512vbmi2) { 3754 tcg_gen_dup_i32_vec(vece, t, lsh); 3755 if (vece >= MO_32) { 3756 tcg_gen_rotlv_vec(vece, v0, v1, t); 3757 } else { 3758 expand_vec_rotv(type, vece, v0, v1, t, false); 3759 } 3760 } else { 3761 TCGv_i32 rsh = tcg_temp_new_i32(); 3762 3763 tcg_gen_neg_i32(rsh, lsh); 3764 tcg_gen_andi_i32(rsh, rsh, (8 << vece) - 1); 3765 tcg_gen_shls_vec(vece, t, v1, lsh); 3766 tcg_gen_shrs_vec(vece, v0, v1, rsh); 3767 tcg_gen_or_vec(vece, v0, v0, t); 3768 3769 tcg_temp_free_i32(rsh); 3770 } 3771 3772 tcg_temp_free_vec(t); 3773} 3774 3775static void expand_vec_mul(TCGType type, unsigned vece, 3776 TCGv_vec v0, TCGv_vec v1, TCGv_vec v2) 3777{ 3778 TCGv_vec t1, t2, t3, t4, zero; 3779 3780 tcg_debug_assert(vece == MO_8); 3781 3782 /* 3783 * Unpack v1 bytes to words, 0 | x. 3784 * Unpack v2 bytes to words, y | 0. 3785 * This leaves the 8-bit result, x * y, with 8 bits of right padding. 3786 * Shift logical right by 8 bits to clear the high 8 bytes before 3787 * using an unsigned saturated pack. 3788 * 3789 * The difference between the V64, V128 and V256 cases is merely how 3790 * we distribute the expansion between temporaries. 3791 */ 3792 switch (type) { 3793 case TCG_TYPE_V64: 3794 t1 = tcg_temp_new_vec(TCG_TYPE_V128); 3795 t2 = tcg_temp_new_vec(TCG_TYPE_V128); 3796 zero = tcg_constant_vec(TCG_TYPE_V128, MO_8, 0); 3797 vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_8, 3798 tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(zero)); 3799 vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_8, 3800 tcgv_vec_arg(t2), tcgv_vec_arg(zero), tcgv_vec_arg(v2)); 3801 tcg_gen_mul_vec(MO_16, t1, t1, t2); 3802 tcg_gen_shri_vec(MO_16, t1, t1, 8); 3803 vec_gen_3(INDEX_op_x86_packus_vec, TCG_TYPE_V128, MO_8, 3804 tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t1)); 3805 tcg_temp_free_vec(t1); 3806 tcg_temp_free_vec(t2); 3807 break; 3808 3809 case TCG_TYPE_V128: 3810 case TCG_TYPE_V256: 3811 t1 = tcg_temp_new_vec(type); 3812 t2 = tcg_temp_new_vec(type); 3813 t3 = tcg_temp_new_vec(type); 3814 t4 = tcg_temp_new_vec(type); 3815 zero = tcg_constant_vec(TCG_TYPE_V128, MO_8, 0); 3816 vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8, 3817 tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(zero)); 3818 vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8, 3819 tcgv_vec_arg(t2), tcgv_vec_arg(zero), tcgv_vec_arg(v2)); 3820 vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8, 3821 tcgv_vec_arg(t3), tcgv_vec_arg(v1), tcgv_vec_arg(zero)); 3822 vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8, 3823 tcgv_vec_arg(t4), tcgv_vec_arg(zero), tcgv_vec_arg(v2)); 3824 tcg_gen_mul_vec(MO_16, t1, t1, t2); 3825 tcg_gen_mul_vec(MO_16, t3, t3, t4); 3826 tcg_gen_shri_vec(MO_16, t1, t1, 8); 3827 tcg_gen_shri_vec(MO_16, t3, t3, 8); 3828 vec_gen_3(INDEX_op_x86_packus_vec, type, MO_8, 3829 tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t3)); 3830 tcg_temp_free_vec(t1); 3831 tcg_temp_free_vec(t2); 3832 tcg_temp_free_vec(t3); 3833 tcg_temp_free_vec(t4); 3834 break; 3835 3836 default: 3837 g_assert_not_reached(); 3838 } 3839} 3840 3841static bool expand_vec_cmp_noinv(TCGType type, unsigned vece, TCGv_vec v0, 3842 TCGv_vec v1, TCGv_vec v2, TCGCond cond) 3843{ 3844 enum { 3845 NEED_INV = 1, 3846 NEED_SWAP = 2, 3847 NEED_BIAS = 4, 3848 NEED_UMIN = 8, 3849 NEED_UMAX = 16, 3850 }; 3851 TCGv_vec t1, t2, t3; 3852 uint8_t fixup; 3853 3854 switch (cond) { 3855 case TCG_COND_EQ: 3856 case TCG_COND_GT: 3857 fixup = 0; 3858 break; 3859 case TCG_COND_NE: 3860 case TCG_COND_LE: 3861 fixup = NEED_INV; 3862 break; 3863 case TCG_COND_LT: 3864 fixup = NEED_SWAP; 3865 break; 3866 case TCG_COND_GE: 3867 fixup = NEED_SWAP | NEED_INV; 3868 break; 3869 case TCG_COND_LEU: 3870 if (tcg_can_emit_vec_op(INDEX_op_umin_vec, type, vece)) { 3871 fixup = NEED_UMIN; 3872 } else { 3873 fixup = NEED_BIAS | NEED_INV; 3874 } 3875 break; 3876 case TCG_COND_GTU: 3877 if (tcg_can_emit_vec_op(INDEX_op_umin_vec, type, vece)) { 3878 fixup = NEED_UMIN | NEED_INV; 3879 } else { 3880 fixup = NEED_BIAS; 3881 } 3882 break; 3883 case TCG_COND_GEU: 3884 if (tcg_can_emit_vec_op(INDEX_op_umax_vec, type, vece)) { 3885 fixup = NEED_UMAX; 3886 } else { 3887 fixup = NEED_BIAS | NEED_SWAP | NEED_INV; 3888 } 3889 break; 3890 case TCG_COND_LTU: 3891 if (tcg_can_emit_vec_op(INDEX_op_umax_vec, type, vece)) { 3892 fixup = NEED_UMAX | NEED_INV; 3893 } else { 3894 fixup = NEED_BIAS | NEED_SWAP; 3895 } 3896 break; 3897 default: 3898 g_assert_not_reached(); 3899 } 3900 3901 if (fixup & NEED_INV) { 3902 cond = tcg_invert_cond(cond); 3903 } 3904 if (fixup & NEED_SWAP) { 3905 t1 = v1, v1 = v2, v2 = t1; 3906 cond = tcg_swap_cond(cond); 3907 } 3908 3909 t1 = t2 = NULL; 3910 if (fixup & (NEED_UMIN | NEED_UMAX)) { 3911 t1 = tcg_temp_new_vec(type); 3912 if (fixup & NEED_UMIN) { 3913 tcg_gen_umin_vec(vece, t1, v1, v2); 3914 } else { 3915 tcg_gen_umax_vec(vece, t1, v1, v2); 3916 } 3917 v2 = t1; 3918 cond = TCG_COND_EQ; 3919 } else if (fixup & NEED_BIAS) { 3920 t1 = tcg_temp_new_vec(type); 3921 t2 = tcg_temp_new_vec(type); 3922 t3 = tcg_constant_vec(type, vece, 1ull << ((8 << vece) - 1)); 3923 tcg_gen_sub_vec(vece, t1, v1, t3); 3924 tcg_gen_sub_vec(vece, t2, v2, t3); 3925 v1 = t1; 3926 v2 = t2; 3927 cond = tcg_signed_cond(cond); 3928 } 3929 3930 tcg_debug_assert(cond == TCG_COND_EQ || cond == TCG_COND_GT); 3931 /* Expand directly; do not recurse. */ 3932 vec_gen_4(INDEX_op_cmp_vec, type, vece, 3933 tcgv_vec_arg(v0), tcgv_vec_arg(v1), tcgv_vec_arg(v2), cond); 3934 3935 if (t1) { 3936 tcg_temp_free_vec(t1); 3937 if (t2) { 3938 tcg_temp_free_vec(t2); 3939 } 3940 } 3941 return fixup & NEED_INV; 3942} 3943 3944static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0, 3945 TCGv_vec v1, TCGv_vec v2, TCGCond cond) 3946{ 3947 if (expand_vec_cmp_noinv(type, vece, v0, v1, v2, cond)) { 3948 tcg_gen_not_vec(vece, v0, v0); 3949 } 3950} 3951 3952static void expand_vec_cmpsel(TCGType type, unsigned vece, TCGv_vec v0, 3953 TCGv_vec c1, TCGv_vec c2, 3954 TCGv_vec v3, TCGv_vec v4, TCGCond cond) 3955{ 3956 TCGv_vec t = tcg_temp_new_vec(type); 3957 3958 if (expand_vec_cmp_noinv(type, vece, t, c1, c2, cond)) { 3959 /* Invert the sense of the compare by swapping arguments. */ 3960 TCGv_vec x; 3961 x = v3, v3 = v4, v4 = x; 3962 } 3963 vec_gen_4(INDEX_op_x86_vpblendvb_vec, type, vece, 3964 tcgv_vec_arg(v0), tcgv_vec_arg(v4), 3965 tcgv_vec_arg(v3), tcgv_vec_arg(t)); 3966 tcg_temp_free_vec(t); 3967} 3968 3969void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 3970 TCGArg a0, ...) 3971{ 3972 va_list va; 3973 TCGArg a2; 3974 TCGv_vec v0, v1, v2, v3, v4; 3975 3976 va_start(va, a0); 3977 v0 = temp_tcgv_vec(arg_temp(a0)); 3978 v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 3979 a2 = va_arg(va, TCGArg); 3980 3981 switch (opc) { 3982 case INDEX_op_shli_vec: 3983 case INDEX_op_shri_vec: 3984 expand_vec_shi(type, vece, opc, v0, v1, a2); 3985 break; 3986 3987 case INDEX_op_sari_vec: 3988 expand_vec_sari(type, vece, v0, v1, a2); 3989 break; 3990 3991 case INDEX_op_rotli_vec: 3992 expand_vec_rotli(type, vece, v0, v1, a2); 3993 break; 3994 3995 case INDEX_op_rotls_vec: 3996 expand_vec_rotls(type, vece, v0, v1, temp_tcgv_i32(arg_temp(a2))); 3997 break; 3998 3999 case INDEX_op_rotlv_vec: 4000 v2 = temp_tcgv_vec(arg_temp(a2)); 4001 expand_vec_rotv(type, vece, v0, v1, v2, false); 4002 break; 4003 case INDEX_op_rotrv_vec: 4004 v2 = temp_tcgv_vec(arg_temp(a2)); 4005 expand_vec_rotv(type, vece, v0, v1, v2, true); 4006 break; 4007 4008 case INDEX_op_mul_vec: 4009 v2 = temp_tcgv_vec(arg_temp(a2)); 4010 expand_vec_mul(type, vece, v0, v1, v2); 4011 break; 4012 4013 case INDEX_op_cmp_vec: 4014 v2 = temp_tcgv_vec(arg_temp(a2)); 4015 expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg)); 4016 break; 4017 4018 case INDEX_op_cmpsel_vec: 4019 v2 = temp_tcgv_vec(arg_temp(a2)); 4020 v3 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 4021 v4 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 4022 expand_vec_cmpsel(type, vece, v0, v1, v2, v3, v4, va_arg(va, TCGArg)); 4023 break; 4024 4025 default: 4026 break; 4027 } 4028 4029 va_end(va); 4030} 4031 4032static const int tcg_target_callee_save_regs[] = { 4033#if TCG_TARGET_REG_BITS == 64 4034 TCG_REG_RBP, 4035 TCG_REG_RBX, 4036#if defined(_WIN64) 4037 TCG_REG_RDI, 4038 TCG_REG_RSI, 4039#endif 4040 TCG_REG_R12, 4041 TCG_REG_R13, 4042 TCG_REG_R14, /* Currently used for the global env. */ 4043 TCG_REG_R15, 4044#else 4045 TCG_REG_EBP, /* Currently used for the global env. */ 4046 TCG_REG_EBX, 4047 TCG_REG_ESI, 4048 TCG_REG_EDI, 4049#endif 4050}; 4051 4052/* Compute frame size via macros, to share between tcg_target_qemu_prologue 4053 and tcg_register_jit. */ 4054 4055#define PUSH_SIZE \ 4056 ((1 + ARRAY_SIZE(tcg_target_callee_save_regs)) \ 4057 * (TCG_TARGET_REG_BITS / 8)) 4058 4059#define FRAME_SIZE \ 4060 ((PUSH_SIZE \ 4061 + TCG_STATIC_CALL_ARGS_SIZE \ 4062 + CPU_TEMP_BUF_NLONGS * sizeof(long) \ 4063 + TCG_TARGET_STACK_ALIGN - 1) \ 4064 & ~(TCG_TARGET_STACK_ALIGN - 1)) 4065 4066/* Generate global QEMU prologue and epilogue code */ 4067static void tcg_target_qemu_prologue(TCGContext *s) 4068{ 4069 int i, stack_addend; 4070 4071 /* TB prologue */ 4072 4073 /* Reserve some stack space, also for TCG temps. */ 4074 stack_addend = FRAME_SIZE - PUSH_SIZE; 4075 tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE, 4076 CPU_TEMP_BUF_NLONGS * sizeof(long)); 4077 4078 /* Save all callee saved registers. */ 4079 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 4080 tcg_out_push(s, tcg_target_callee_save_regs[i]); 4081 } 4082 4083#if TCG_TARGET_REG_BITS == 32 4084 tcg_out_ld(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, 4085 (ARRAY_SIZE(tcg_target_callee_save_regs) + 1) * 4); 4086 tcg_out_addi(s, TCG_REG_ESP, -stack_addend); 4087 /* jmp *tb. */ 4088 tcg_out_modrm_offset(s, OPC_GRP5, EXT5_JMPN_Ev, TCG_REG_ESP, 4089 (ARRAY_SIZE(tcg_target_callee_save_regs) + 2) * 4 4090 + stack_addend); 4091#else 4092# if !defined(CONFIG_SOFTMMU) 4093 if (guest_base) { 4094 int seg = setup_guest_base_seg(); 4095 if (seg != 0) { 4096 x86_guest_base.seg = seg; 4097 } else if (guest_base == (int32_t)guest_base) { 4098 x86_guest_base.ofs = guest_base; 4099 } else { 4100 /* Choose R12 because, as a base, it requires a SIB byte. */ 4101 x86_guest_base.index = TCG_REG_R12; 4102 tcg_out_movi(s, TCG_TYPE_PTR, x86_guest_base.index, guest_base); 4103 tcg_regset_set_reg(s->reserved_regs, x86_guest_base.index); 4104 } 4105 } 4106# endif 4107 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 4108 tcg_out_addi(s, TCG_REG_ESP, -stack_addend); 4109 /* jmp *tb. */ 4110 tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, tcg_target_call_iarg_regs[1]); 4111#endif 4112 4113 /* 4114 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 4115 * and fall through to the rest of the epilogue. 4116 */ 4117 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 4118 tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_EAX, 0); 4119 4120 /* TB epilogue */ 4121 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 4122 4123 tcg_out_addi(s, TCG_REG_CALL_STACK, stack_addend); 4124 4125 if (have_avx2) { 4126 tcg_out_vex_opc(s, OPC_VZEROUPPER, 0, 0, 0, 0); 4127 } 4128 for (i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) { 4129 tcg_out_pop(s, tcg_target_callee_save_regs[i]); 4130 } 4131 tcg_out_opc(s, OPC_RET, 0, 0, 0); 4132} 4133 4134static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 4135{ 4136 memset(p, 0x90, count); 4137} 4138 4139static void tcg_target_init(TCGContext *s) 4140{ 4141 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS; 4142 if (TCG_TARGET_REG_BITS == 64) { 4143 tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS; 4144 } 4145 if (have_avx1) { 4146 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS; 4147 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS; 4148 } 4149 if (have_avx2) { 4150 tcg_target_available_regs[TCG_TYPE_V256] = ALL_VECTOR_REGS; 4151 } 4152 4153 tcg_target_call_clobber_regs = ALL_VECTOR_REGS; 4154 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_EAX); 4155 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_EDX); 4156 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_ECX); 4157 if (TCG_TARGET_REG_BITS == 64) { 4158#if !defined(_WIN64) 4159 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_RDI); 4160 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_RSI); 4161#endif 4162 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8); 4163 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9); 4164 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10); 4165 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11); 4166 } 4167 4168 s->reserved_regs = 0; 4169 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); 4170 tcg_regset_set_reg(s->reserved_regs, TCG_TMP_VEC); 4171#ifdef _WIN64 4172 /* These are call saved, and we don't save them, so don't use them. */ 4173 tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM6); 4174 tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM7); 4175 tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM8); 4176 tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM9); 4177 tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM10); 4178 tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM11); 4179 tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM12); 4180 tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM13); 4181 tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM14); 4182 tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM15); 4183#endif 4184} 4185 4186typedef struct { 4187 DebugFrameHeader h; 4188 uint8_t fde_def_cfa[4]; 4189 uint8_t fde_reg_ofs[14]; 4190} DebugFrame; 4191 4192/* We're expecting a 2 byte uleb128 encoded value. */ 4193QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); 4194 4195#if !defined(__ELF__) 4196 /* Host machine without ELF. */ 4197#elif TCG_TARGET_REG_BITS == 64 4198#define ELF_HOST_MACHINE EM_X86_64 4199static const DebugFrame debug_frame = { 4200 .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ 4201 .h.cie.id = -1, 4202 .h.cie.version = 1, 4203 .h.cie.code_align = 1, 4204 .h.cie.data_align = 0x78, /* sleb128 -8 */ 4205 .h.cie.return_column = 16, 4206 4207 /* Total FDE size does not include the "len" member. */ 4208 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 4209 4210 .fde_def_cfa = { 4211 12, 7, /* DW_CFA_def_cfa %rsp, ... */ 4212 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 4213 (FRAME_SIZE >> 7) 4214 }, 4215 .fde_reg_ofs = { 4216 0x90, 1, /* DW_CFA_offset, %rip, -8 */ 4217 /* The following ordering must match tcg_target_callee_save_regs. */ 4218 0x86, 2, /* DW_CFA_offset, %rbp, -16 */ 4219 0x83, 3, /* DW_CFA_offset, %rbx, -24 */ 4220 0x8c, 4, /* DW_CFA_offset, %r12, -32 */ 4221 0x8d, 5, /* DW_CFA_offset, %r13, -40 */ 4222 0x8e, 6, /* DW_CFA_offset, %r14, -48 */ 4223 0x8f, 7, /* DW_CFA_offset, %r15, -56 */ 4224 } 4225}; 4226#else 4227#define ELF_HOST_MACHINE EM_386 4228static const DebugFrame debug_frame = { 4229 .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ 4230 .h.cie.id = -1, 4231 .h.cie.version = 1, 4232 .h.cie.code_align = 1, 4233 .h.cie.data_align = 0x7c, /* sleb128 -4 */ 4234 .h.cie.return_column = 8, 4235 4236 /* Total FDE size does not include the "len" member. */ 4237 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 4238 4239 .fde_def_cfa = { 4240 12, 4, /* DW_CFA_def_cfa %esp, ... */ 4241 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 4242 (FRAME_SIZE >> 7) 4243 }, 4244 .fde_reg_ofs = { 4245 0x88, 1, /* DW_CFA_offset, %eip, -4 */ 4246 /* The following ordering must match tcg_target_callee_save_regs. */ 4247 0x85, 2, /* DW_CFA_offset, %ebp, -8 */ 4248 0x83, 3, /* DW_CFA_offset, %ebx, -12 */ 4249 0x86, 4, /* DW_CFA_offset, %esi, -16 */ 4250 0x87, 5, /* DW_CFA_offset, %edi, -20 */ 4251 } 4252}; 4253#endif 4254 4255#if defined(ELF_HOST_MACHINE) 4256void tcg_register_jit(const void *buf, size_t buf_size) 4257{ 4258 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 4259} 4260#endif 4261