1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25/* Used for function call generation. */ 26#define TCG_TARGET_STACK_ALIGN 16 27#if defined(_WIN64) 28#define TCG_TARGET_CALL_STACK_OFFSET 32 29#else 30#define TCG_TARGET_CALL_STACK_OFFSET 0 31#endif 32#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL 33#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL 34#if defined(_WIN64) 35# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_BY_REF 36# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_VEC 37#elif TCG_TARGET_REG_BITS == 64 38# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL 39# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL 40#else 41# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL 42# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF 43#endif 44 45#ifdef CONFIG_DEBUG_TCG 46static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 47#if TCG_TARGET_REG_BITS == 64 48 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", 49#else 50 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", 51#endif 52 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", 53 "%xmm0", "%xmm1", "%xmm2", "%xmm3", "%xmm4", "%xmm5", "%xmm6", "%xmm7", 54#if TCG_TARGET_REG_BITS == 64 55 "%xmm8", "%xmm9", "%xmm10", "%xmm11", 56 "%xmm12", "%xmm13", "%xmm14", "%xmm15", 57#endif 58}; 59#endif 60 61static const int tcg_target_reg_alloc_order[] = { 62#if TCG_TARGET_REG_BITS == 64 63 TCG_REG_RBP, 64 TCG_REG_RBX, 65 TCG_REG_R12, 66 TCG_REG_R13, 67 TCG_REG_R14, 68 TCG_REG_R15, 69 TCG_REG_R10, 70 TCG_REG_R11, 71 TCG_REG_R9, 72 TCG_REG_R8, 73 TCG_REG_RCX, 74 TCG_REG_RDX, 75 TCG_REG_RSI, 76 TCG_REG_RDI, 77 TCG_REG_RAX, 78#else 79 TCG_REG_EBX, 80 TCG_REG_ESI, 81 TCG_REG_EDI, 82 TCG_REG_EBP, 83 TCG_REG_ECX, 84 TCG_REG_EDX, 85 TCG_REG_EAX, 86#endif 87 TCG_REG_XMM0, 88 TCG_REG_XMM1, 89 TCG_REG_XMM2, 90 TCG_REG_XMM3, 91 TCG_REG_XMM4, 92 TCG_REG_XMM5, 93#ifndef _WIN64 94 /* The Win64 ABI has xmm6-xmm15 as caller-saves, and we do not save 95 any of them. Therefore only allow xmm0-xmm5 to be allocated. */ 96 TCG_REG_XMM6, 97 TCG_REG_XMM7, 98#if TCG_TARGET_REG_BITS == 64 99 TCG_REG_XMM8, 100 TCG_REG_XMM9, 101 TCG_REG_XMM10, 102 TCG_REG_XMM11, 103 TCG_REG_XMM12, 104 TCG_REG_XMM13, 105 TCG_REG_XMM14, 106 TCG_REG_XMM15, 107#endif 108#endif 109}; 110 111#define TCG_TMP_VEC TCG_REG_XMM5 112 113static const int tcg_target_call_iarg_regs[] = { 114#if TCG_TARGET_REG_BITS == 64 115#if defined(_WIN64) 116 TCG_REG_RCX, 117 TCG_REG_RDX, 118#else 119 TCG_REG_RDI, 120 TCG_REG_RSI, 121 TCG_REG_RDX, 122 TCG_REG_RCX, 123#endif 124 TCG_REG_R8, 125 TCG_REG_R9, 126#else 127 /* 32 bit mode uses stack based calling convention (GCC default). */ 128#endif 129}; 130 131static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 132{ 133 switch (kind) { 134 case TCG_CALL_RET_NORMAL: 135 tcg_debug_assert(slot >= 0 && slot <= 1); 136 return slot ? TCG_REG_EDX : TCG_REG_EAX; 137#ifdef _WIN64 138 case TCG_CALL_RET_BY_VEC: 139 tcg_debug_assert(slot == 0); 140 return TCG_REG_XMM0; 141#endif 142 default: 143 g_assert_not_reached(); 144 } 145} 146 147/* Constants we accept. */ 148#define TCG_CT_CONST_S32 0x100 149#define TCG_CT_CONST_U32 0x200 150#define TCG_CT_CONST_I32 0x400 151#define TCG_CT_CONST_WSZ 0x800 152#define TCG_CT_CONST_TST 0x1000 153#define TCG_CT_CONST_ZERO 0x2000 154 155/* Registers used with L constraint, which are the first argument 156 registers on x86_64, and two random call clobbered registers on 157 i386. */ 158#if TCG_TARGET_REG_BITS == 64 159# define TCG_REG_L0 tcg_target_call_iarg_regs[0] 160# define TCG_REG_L1 tcg_target_call_iarg_regs[1] 161#else 162# define TCG_REG_L0 TCG_REG_EAX 163# define TCG_REG_L1 TCG_REG_EDX 164#endif 165 166#if TCG_TARGET_REG_BITS == 64 167# define ALL_GENERAL_REGS 0x0000ffffu 168# define ALL_VECTOR_REGS 0xffff0000u 169# define ALL_BYTEL_REGS ALL_GENERAL_REGS 170#else 171# define ALL_GENERAL_REGS 0x000000ffu 172# define ALL_VECTOR_REGS 0x00ff0000u 173# define ALL_BYTEL_REGS 0x0000000fu 174#endif 175#define SOFTMMU_RESERVE_REGS \ 176 (tcg_use_softmmu ? (1 << TCG_REG_L0) | (1 << TCG_REG_L1) : 0) 177 178#define have_bmi2 (cpuinfo & CPUINFO_BMI2) 179#define have_lzcnt (cpuinfo & CPUINFO_LZCNT) 180 181static const tcg_insn_unit *tb_ret_addr; 182 183static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 184 intptr_t value, intptr_t addend) 185{ 186 value += addend; 187 switch(type) { 188 case R_386_PC32: 189 value -= (uintptr_t)tcg_splitwx_to_rx(code_ptr); 190 if (value != (int32_t)value) { 191 return false; 192 } 193 /* FALLTHRU */ 194 case R_386_32: 195 tcg_patch32(code_ptr, value); 196 break; 197 case R_386_PC8: 198 value -= (uintptr_t)tcg_splitwx_to_rx(code_ptr); 199 if (value != (int8_t)value) { 200 return false; 201 } 202 tcg_patch8(code_ptr, value); 203 break; 204 default: 205 g_assert_not_reached(); 206 } 207 return true; 208} 209 210/* test if a constant matches the constraint */ 211static bool tcg_target_const_match(int64_t val, int ct, 212 TCGType type, TCGCond cond, int vece) 213{ 214 if (ct & TCG_CT_CONST) { 215 return 1; 216 } 217 if (type == TCG_TYPE_I32) { 218 if (ct & (TCG_CT_CONST_S32 | TCG_CT_CONST_U32 | 219 TCG_CT_CONST_I32 | TCG_CT_CONST_TST)) { 220 return 1; 221 } 222 } else { 223 if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) { 224 return 1; 225 } 226 if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) { 227 return 1; 228 } 229 if ((ct & TCG_CT_CONST_I32) && ~val == (int32_t)~val) { 230 return 1; 231 } 232 /* 233 * This will be used in combination with TCG_CT_CONST_S32, 234 * so "normal" TESTQ is already matched. Also accept: 235 * TESTQ -> TESTL (uint32_t) 236 * TESTQ -> BT (is_power_of_2) 237 */ 238 if ((ct & TCG_CT_CONST_TST) 239 && is_tst_cond(cond) 240 && (val == (uint32_t)val || is_power_of_2(val))) { 241 return 1; 242 } 243 } 244 if ((ct & TCG_CT_CONST_WSZ) && val == (type == TCG_TYPE_I32 ? 32 : 64)) { 245 return 1; 246 } 247 if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 248 return 1; 249 } 250 return 0; 251} 252 253# define LOWREGMASK(x) ((x) & 7) 254 255#define P_EXT 0x100 /* 0x0f opcode prefix */ 256#define P_EXT38 0x200 /* 0x0f 0x38 opcode prefix */ 257#define P_DATA16 0x400 /* 0x66 opcode prefix */ 258#define P_VEXW 0x1000 /* Set VEX.W = 1 */ 259#if TCG_TARGET_REG_BITS == 64 260# define P_REXW P_VEXW /* Set REX.W = 1; match VEXW */ 261# define P_REXB_R 0x2000 /* REG field as byte register */ 262# define P_REXB_RM 0x4000 /* R/M field as byte register */ 263# define P_GS 0x8000 /* gs segment override */ 264#else 265# define P_REXW 0 266# define P_REXB_R 0 267# define P_REXB_RM 0 268# define P_GS 0 269#endif 270#define P_EXT3A 0x10000 /* 0x0f 0x3a opcode prefix */ 271#define P_SIMDF3 0x20000 /* 0xf3 opcode prefix */ 272#define P_SIMDF2 0x40000 /* 0xf2 opcode prefix */ 273#define P_VEXL 0x80000 /* Set VEX.L = 1 */ 274#define P_EVEX 0x100000 /* Requires EVEX encoding */ 275 276#define OPC_ARITH_EbIb (0x80) 277#define OPC_ARITH_EvIz (0x81) 278#define OPC_ARITH_EvIb (0x83) 279#define OPC_ARITH_GvEv (0x03) /* ... plus (ARITH_FOO << 3) */ 280#define OPC_ANDN (0xf2 | P_EXT38) 281#define OPC_ADD_GvEv (OPC_ARITH_GvEv | (ARITH_ADD << 3)) 282#define OPC_AND_GvEv (OPC_ARITH_GvEv | (ARITH_AND << 3)) 283#define OPC_BLENDPS (0x0c | P_EXT3A | P_DATA16) 284#define OPC_BSF (0xbc | P_EXT) 285#define OPC_BSR (0xbd | P_EXT) 286#define OPC_BSWAP (0xc8 | P_EXT) 287#define OPC_CALL_Jz (0xe8) 288#define OPC_CMOVCC (0x40 | P_EXT) /* ... plus condition code */ 289#define OPC_CMP_GvEv (OPC_ARITH_GvEv | (ARITH_CMP << 3)) 290#define OPC_DEC_r32 (0x48) 291#define OPC_IMUL_GvEv (0xaf | P_EXT) 292#define OPC_IMUL_GvEvIb (0x6b) 293#define OPC_IMUL_GvEvIz (0x69) 294#define OPC_INC_r32 (0x40) 295#define OPC_JCC_long (0x80 | P_EXT) /* ... plus condition code */ 296#define OPC_JCC_short (0x70) /* ... plus condition code */ 297#define OPC_JMP_long (0xe9) 298#define OPC_JMP_short (0xeb) 299#define OPC_LEA (0x8d) 300#define OPC_LZCNT (0xbd | P_EXT | P_SIMDF3) 301#define OPC_MOVB_EvGv (0x88) /* stores, more or less */ 302#define OPC_MOVL_EvGv (0x89) /* stores, more or less */ 303#define OPC_MOVL_GvEv (0x8b) /* loads, more or less */ 304#define OPC_MOVB_EvIz (0xc6) 305#define OPC_MOVL_EvIz (0xc7) 306#define OPC_MOVB_Ib (0xb0) 307#define OPC_MOVL_Iv (0xb8) 308#define OPC_MOVBE_GyMy (0xf0 | P_EXT38) 309#define OPC_MOVBE_MyGy (0xf1 | P_EXT38) 310#define OPC_MOVD_VyEy (0x6e | P_EXT | P_DATA16) 311#define OPC_MOVD_EyVy (0x7e | P_EXT | P_DATA16) 312#define OPC_MOVDDUP (0x12 | P_EXT | P_SIMDF2) 313#define OPC_MOVDQA_VxWx (0x6f | P_EXT | P_DATA16) 314#define OPC_MOVDQA_WxVx (0x7f | P_EXT | P_DATA16) 315#define OPC_MOVDQU_VxWx (0x6f | P_EXT | P_SIMDF3) 316#define OPC_MOVDQU_WxVx (0x7f | P_EXT | P_SIMDF3) 317#define OPC_MOVQ_VqWq (0x7e | P_EXT | P_SIMDF3) 318#define OPC_MOVQ_WqVq (0xd6 | P_EXT | P_DATA16) 319#define OPC_MOVSBL (0xbe | P_EXT) 320#define OPC_MOVSWL (0xbf | P_EXT) 321#define OPC_MOVSLQ (0x63 | P_REXW) 322#define OPC_MOVZBL (0xb6 | P_EXT) 323#define OPC_MOVZWL (0xb7 | P_EXT) 324#define OPC_PABSB (0x1c | P_EXT38 | P_DATA16) 325#define OPC_PABSW (0x1d | P_EXT38 | P_DATA16) 326#define OPC_PABSD (0x1e | P_EXT38 | P_DATA16) 327#define OPC_VPABSQ (0x1f | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 328#define OPC_PACKSSDW (0x6b | P_EXT | P_DATA16) 329#define OPC_PACKSSWB (0x63 | P_EXT | P_DATA16) 330#define OPC_PACKUSDW (0x2b | P_EXT38 | P_DATA16) 331#define OPC_PACKUSWB (0x67 | P_EXT | P_DATA16) 332#define OPC_PADDB (0xfc | P_EXT | P_DATA16) 333#define OPC_PADDW (0xfd | P_EXT | P_DATA16) 334#define OPC_PADDD (0xfe | P_EXT | P_DATA16) 335#define OPC_PADDQ (0xd4 | P_EXT | P_DATA16) 336#define OPC_PADDSB (0xec | P_EXT | P_DATA16) 337#define OPC_PADDSW (0xed | P_EXT | P_DATA16) 338#define OPC_PADDUB (0xdc | P_EXT | P_DATA16) 339#define OPC_PADDUW (0xdd | P_EXT | P_DATA16) 340#define OPC_PAND (0xdb | P_EXT | P_DATA16) 341#define OPC_PANDN (0xdf | P_EXT | P_DATA16) 342#define OPC_PBLENDW (0x0e | P_EXT3A | P_DATA16) 343#define OPC_PCMPEQB (0x74 | P_EXT | P_DATA16) 344#define OPC_PCMPEQW (0x75 | P_EXT | P_DATA16) 345#define OPC_PCMPEQD (0x76 | P_EXT | P_DATA16) 346#define OPC_PCMPEQQ (0x29 | P_EXT38 | P_DATA16) 347#define OPC_PCMPGTB (0x64 | P_EXT | P_DATA16) 348#define OPC_PCMPGTW (0x65 | P_EXT | P_DATA16) 349#define OPC_PCMPGTD (0x66 | P_EXT | P_DATA16) 350#define OPC_PCMPGTQ (0x37 | P_EXT38 | P_DATA16) 351#define OPC_PEXTRD (0x16 | P_EXT3A | P_DATA16) 352#define OPC_PINSRD (0x22 | P_EXT3A | P_DATA16) 353#define OPC_PMAXSB (0x3c | P_EXT38 | P_DATA16) 354#define OPC_PMAXSW (0xee | P_EXT | P_DATA16) 355#define OPC_PMAXSD (0x3d | P_EXT38 | P_DATA16) 356#define OPC_VPMAXSQ (0x3d | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 357#define OPC_PMAXUB (0xde | P_EXT | P_DATA16) 358#define OPC_PMAXUW (0x3e | P_EXT38 | P_DATA16) 359#define OPC_PMAXUD (0x3f | P_EXT38 | P_DATA16) 360#define OPC_VPMAXUQ (0x3f | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 361#define OPC_PMINSB (0x38 | P_EXT38 | P_DATA16) 362#define OPC_PMINSW (0xea | P_EXT | P_DATA16) 363#define OPC_PMINSD (0x39 | P_EXT38 | P_DATA16) 364#define OPC_VPMINSQ (0x39 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 365#define OPC_PMINUB (0xda | P_EXT | P_DATA16) 366#define OPC_PMINUW (0x3a | P_EXT38 | P_DATA16) 367#define OPC_PMINUD (0x3b | P_EXT38 | P_DATA16) 368#define OPC_VPMINUQ (0x3b | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 369#define OPC_PMOVSXBW (0x20 | P_EXT38 | P_DATA16) 370#define OPC_PMOVSXWD (0x23 | P_EXT38 | P_DATA16) 371#define OPC_PMOVSXDQ (0x25 | P_EXT38 | P_DATA16) 372#define OPC_PMOVZXBW (0x30 | P_EXT38 | P_DATA16) 373#define OPC_PMOVZXWD (0x33 | P_EXT38 | P_DATA16) 374#define OPC_PMOVZXDQ (0x35 | P_EXT38 | P_DATA16) 375#define OPC_PMULLW (0xd5 | P_EXT | P_DATA16) 376#define OPC_PMULLD (0x40 | P_EXT38 | P_DATA16) 377#define OPC_VPMULLQ (0x40 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 378#define OPC_POR (0xeb | P_EXT | P_DATA16) 379#define OPC_PSHUFB (0x00 | P_EXT38 | P_DATA16) 380#define OPC_PSHUFD (0x70 | P_EXT | P_DATA16) 381#define OPC_PSHUFLW (0x70 | P_EXT | P_SIMDF2) 382#define OPC_PSHUFHW (0x70 | P_EXT | P_SIMDF3) 383#define OPC_PSHIFTW_Ib (0x71 | P_EXT | P_DATA16) /* /2 /6 /4 */ 384#define OPC_PSHIFTD_Ib (0x72 | P_EXT | P_DATA16) /* /1 /2 /6 /4 */ 385#define OPC_PSHIFTQ_Ib (0x73 | P_EXT | P_DATA16) /* /2 /6 /4 */ 386#define OPC_PSLLW (0xf1 | P_EXT | P_DATA16) 387#define OPC_PSLLD (0xf2 | P_EXT | P_DATA16) 388#define OPC_PSLLQ (0xf3 | P_EXT | P_DATA16) 389#define OPC_PSRAW (0xe1 | P_EXT | P_DATA16) 390#define OPC_PSRAD (0xe2 | P_EXT | P_DATA16) 391#define OPC_VPSRAQ (0xe2 | P_EXT | P_DATA16 | P_VEXW | P_EVEX) 392#define OPC_PSRLW (0xd1 | P_EXT | P_DATA16) 393#define OPC_PSRLD (0xd2 | P_EXT | P_DATA16) 394#define OPC_PSRLQ (0xd3 | P_EXT | P_DATA16) 395#define OPC_PSUBB (0xf8 | P_EXT | P_DATA16) 396#define OPC_PSUBW (0xf9 | P_EXT | P_DATA16) 397#define OPC_PSUBD (0xfa | P_EXT | P_DATA16) 398#define OPC_PSUBQ (0xfb | P_EXT | P_DATA16) 399#define OPC_PSUBSB (0xe8 | P_EXT | P_DATA16) 400#define OPC_PSUBSW (0xe9 | P_EXT | P_DATA16) 401#define OPC_PSUBUB (0xd8 | P_EXT | P_DATA16) 402#define OPC_PSUBUW (0xd9 | P_EXT | P_DATA16) 403#define OPC_PUNPCKLBW (0x60 | P_EXT | P_DATA16) 404#define OPC_PUNPCKLWD (0x61 | P_EXT | P_DATA16) 405#define OPC_PUNPCKLDQ (0x62 | P_EXT | P_DATA16) 406#define OPC_PUNPCKLQDQ (0x6c | P_EXT | P_DATA16) 407#define OPC_PUNPCKHBW (0x68 | P_EXT | P_DATA16) 408#define OPC_PUNPCKHWD (0x69 | P_EXT | P_DATA16) 409#define OPC_PUNPCKHDQ (0x6a | P_EXT | P_DATA16) 410#define OPC_PUNPCKHQDQ (0x6d | P_EXT | P_DATA16) 411#define OPC_PXOR (0xef | P_EXT | P_DATA16) 412#define OPC_POP_r32 (0x58) 413#define OPC_POPCNT (0xb8 | P_EXT | P_SIMDF3) 414#define OPC_PUSH_r32 (0x50) 415#define OPC_PUSH_Iv (0x68) 416#define OPC_PUSH_Ib (0x6a) 417#define OPC_RET (0xc3) 418#define OPC_SETCC (0x90 | P_EXT | P_REXB_RM) /* ... plus cc */ 419#define OPC_SHIFT_1 (0xd1) 420#define OPC_SHIFT_Ib (0xc1) 421#define OPC_SHIFT_cl (0xd3) 422#define OPC_SARX (0xf7 | P_EXT38 | P_SIMDF3) 423#define OPC_SHUFPS (0xc6 | P_EXT) 424#define OPC_SHLX (0xf7 | P_EXT38 | P_DATA16) 425#define OPC_SHRX (0xf7 | P_EXT38 | P_SIMDF2) 426#define OPC_SHRD_Ib (0xac | P_EXT) 427#define OPC_TESTB (0x84) 428#define OPC_TESTL (0x85) 429#define OPC_TZCNT (0xbc | P_EXT | P_SIMDF3) 430#define OPC_UD2 (0x0b | P_EXT) 431#define OPC_VPBLENDD (0x02 | P_EXT3A | P_DATA16) 432#define OPC_VPBLENDVB (0x4c | P_EXT3A | P_DATA16) 433#define OPC_VPBLENDMB (0x66 | P_EXT38 | P_DATA16 | P_EVEX) 434#define OPC_VPBLENDMW (0x66 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 435#define OPC_VPBLENDMD (0x64 | P_EXT38 | P_DATA16 | P_EVEX) 436#define OPC_VPBLENDMQ (0x64 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 437#define OPC_VPCMPB (0x3f | P_EXT3A | P_DATA16 | P_EVEX) 438#define OPC_VPCMPUB (0x3e | P_EXT3A | P_DATA16 | P_EVEX) 439#define OPC_VPCMPW (0x3f | P_EXT3A | P_DATA16 | P_VEXW | P_EVEX) 440#define OPC_VPCMPUW (0x3e | P_EXT3A | P_DATA16 | P_VEXW | P_EVEX) 441#define OPC_VPCMPD (0x1f | P_EXT3A | P_DATA16 | P_EVEX) 442#define OPC_VPCMPUD (0x1e | P_EXT3A | P_DATA16 | P_EVEX) 443#define OPC_VPCMPQ (0x1f | P_EXT3A | P_DATA16 | P_VEXW | P_EVEX) 444#define OPC_VPCMPUQ (0x1e | P_EXT3A | P_DATA16 | P_VEXW | P_EVEX) 445#define OPC_VPINSRB (0x20 | P_EXT3A | P_DATA16) 446#define OPC_VPINSRW (0xc4 | P_EXT | P_DATA16) 447#define OPC_VBROADCASTSS (0x18 | P_EXT38 | P_DATA16) 448#define OPC_VBROADCASTSD (0x19 | P_EXT38 | P_DATA16) 449#define OPC_VPBROADCASTB (0x78 | P_EXT38 | P_DATA16) 450#define OPC_VPBROADCASTW (0x79 | P_EXT38 | P_DATA16) 451#define OPC_VPBROADCASTD (0x58 | P_EXT38 | P_DATA16) 452#define OPC_VPBROADCASTQ (0x59 | P_EXT38 | P_DATA16) 453#define OPC_VPMOVM2B (0x28 | P_EXT38 | P_SIMDF3 | P_EVEX) 454#define OPC_VPMOVM2W (0x28 | P_EXT38 | P_SIMDF3 | P_VEXW | P_EVEX) 455#define OPC_VPMOVM2D (0x38 | P_EXT38 | P_SIMDF3 | P_EVEX) 456#define OPC_VPMOVM2Q (0x38 | P_EXT38 | P_SIMDF3 | P_VEXW | P_EVEX) 457#define OPC_VPERMQ (0x00 | P_EXT3A | P_DATA16 | P_VEXW) 458#define OPC_VPERM2I128 (0x46 | P_EXT3A | P_DATA16 | P_VEXL) 459#define OPC_VPROLVD (0x15 | P_EXT38 | P_DATA16 | P_EVEX) 460#define OPC_VPROLVQ (0x15 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 461#define OPC_VPRORVD (0x14 | P_EXT38 | P_DATA16 | P_EVEX) 462#define OPC_VPRORVQ (0x14 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 463#define OPC_VPSHLDW (0x70 | P_EXT3A | P_DATA16 | P_VEXW | P_EVEX) 464#define OPC_VPSHLDD (0x71 | P_EXT3A | P_DATA16 | P_EVEX) 465#define OPC_VPSHLDQ (0x71 | P_EXT3A | P_DATA16 | P_VEXW | P_EVEX) 466#define OPC_VPSHLDVW (0x70 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 467#define OPC_VPSHLDVD (0x71 | P_EXT38 | P_DATA16 | P_EVEX) 468#define OPC_VPSHLDVQ (0x71 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 469#define OPC_VPSHRDVW (0x72 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 470#define OPC_VPSHRDVD (0x73 | P_EXT38 | P_DATA16 | P_EVEX) 471#define OPC_VPSHRDVQ (0x73 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 472#define OPC_VPSLLVW (0x12 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 473#define OPC_VPSLLVD (0x47 | P_EXT38 | P_DATA16) 474#define OPC_VPSLLVQ (0x47 | P_EXT38 | P_DATA16 | P_VEXW) 475#define OPC_VPSRAVW (0x11 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 476#define OPC_VPSRAVD (0x46 | P_EXT38 | P_DATA16) 477#define OPC_VPSRAVQ (0x46 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 478#define OPC_VPSRLVW (0x10 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 479#define OPC_VPSRLVD (0x45 | P_EXT38 | P_DATA16) 480#define OPC_VPSRLVQ (0x45 | P_EXT38 | P_DATA16 | P_VEXW) 481#define OPC_VPTERNLOGQ (0x25 | P_EXT3A | P_DATA16 | P_VEXW | P_EVEX) 482#define OPC_VPTESTMB (0x26 | P_EXT38 | P_DATA16 | P_EVEX) 483#define OPC_VPTESTMW (0x26 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 484#define OPC_VPTESTMD (0x27 | P_EXT38 | P_DATA16 | P_EVEX) 485#define OPC_VPTESTMQ (0x27 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 486#define OPC_VPTESTNMB (0x26 | P_EXT38 | P_SIMDF3 | P_EVEX) 487#define OPC_VPTESTNMW (0x26 | P_EXT38 | P_SIMDF3 | P_VEXW | P_EVEX) 488#define OPC_VPTESTNMD (0x27 | P_EXT38 | P_SIMDF3 | P_EVEX) 489#define OPC_VPTESTNMQ (0x27 | P_EXT38 | P_SIMDF3 | P_VEXW | P_EVEX) 490#define OPC_VZEROUPPER (0x77 | P_EXT) 491#define OPC_XCHG_ax_r32 (0x90) 492#define OPC_XCHG_EvGv (0x87) 493 494#define OPC_GRP3_Eb (0xf6) 495#define OPC_GRP3_Ev (0xf7) 496#define OPC_GRP5 (0xff) 497#define OPC_GRP14 (0x73 | P_EXT | P_DATA16) 498#define OPC_GRPBT (0xba | P_EXT) 499 500#define OPC_GRPBT_BT 4 501#define OPC_GRPBT_BTS 5 502#define OPC_GRPBT_BTR 6 503#define OPC_GRPBT_BTC 7 504 505/* Group 1 opcode extensions for 0x80-0x83. 506 These are also used as modifiers for OPC_ARITH. */ 507#define ARITH_ADD 0 508#define ARITH_OR 1 509#define ARITH_ADC 2 510#define ARITH_SBB 3 511#define ARITH_AND 4 512#define ARITH_SUB 5 513#define ARITH_XOR 6 514#define ARITH_CMP 7 515 516/* Group 2 opcode extensions for 0xc0, 0xc1, 0xd0-0xd3. */ 517#define SHIFT_ROL 0 518#define SHIFT_ROR 1 519#define SHIFT_SHL 4 520#define SHIFT_SHR 5 521#define SHIFT_SAR 7 522 523/* Group 3 opcode extensions for 0xf6, 0xf7. To be used with OPC_GRP3. */ 524#define EXT3_TESTi 0 525#define EXT3_NOT 2 526#define EXT3_NEG 3 527#define EXT3_MUL 4 528#define EXT3_IMUL 5 529#define EXT3_DIV 6 530#define EXT3_IDIV 7 531 532/* Group 5 opcode extensions for 0xff. To be used with OPC_GRP5. */ 533#define EXT5_INC_Ev 0 534#define EXT5_DEC_Ev 1 535#define EXT5_CALLN_Ev 2 536#define EXT5_JMPN_Ev 4 537 538/* Condition codes to be added to OPC_JCC_{long,short}. */ 539#define JCC_JMP (-1) 540#define JCC_JO 0x0 541#define JCC_JNO 0x1 542#define JCC_JB 0x2 543#define JCC_JAE 0x3 544#define JCC_JE 0x4 545#define JCC_JNE 0x5 546#define JCC_JBE 0x6 547#define JCC_JA 0x7 548#define JCC_JS 0x8 549#define JCC_JNS 0x9 550#define JCC_JP 0xa 551#define JCC_JNP 0xb 552#define JCC_JL 0xc 553#define JCC_JGE 0xd 554#define JCC_JLE 0xe 555#define JCC_JG 0xf 556 557static const uint8_t tcg_cond_to_jcc[] = { 558 [TCG_COND_EQ] = JCC_JE, 559 [TCG_COND_NE] = JCC_JNE, 560 [TCG_COND_LT] = JCC_JL, 561 [TCG_COND_GE] = JCC_JGE, 562 [TCG_COND_LE] = JCC_JLE, 563 [TCG_COND_GT] = JCC_JG, 564 [TCG_COND_LTU] = JCC_JB, 565 [TCG_COND_GEU] = JCC_JAE, 566 [TCG_COND_LEU] = JCC_JBE, 567 [TCG_COND_GTU] = JCC_JA, 568 [TCG_COND_TSTEQ] = JCC_JE, 569 [TCG_COND_TSTNE] = JCC_JNE, 570}; 571 572#if TCG_TARGET_REG_BITS == 64 573static void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x) 574{ 575 int rex; 576 577 if (opc & P_GS) { 578 tcg_out8(s, 0x65); 579 } 580 if (opc & P_DATA16) { 581 /* We should never be asking for both 16 and 64-bit operation. */ 582 tcg_debug_assert((opc & P_REXW) == 0); 583 tcg_out8(s, 0x66); 584 } 585 if (opc & P_SIMDF3) { 586 tcg_out8(s, 0xf3); 587 } else if (opc & P_SIMDF2) { 588 tcg_out8(s, 0xf2); 589 } 590 591 rex = 0; 592 rex |= (opc & P_REXW) ? 0x8 : 0x0; /* REX.W */ 593 rex |= (r & 8) >> 1; /* REX.R */ 594 rex |= (x & 8) >> 2; /* REX.X */ 595 rex |= (rm & 8) >> 3; /* REX.B */ 596 597 /* P_REXB_{R,RM} indicates that the given register is the low byte. 598 For %[abcd]l we need no REX prefix, but for %{si,di,bp,sp}l we do, 599 as otherwise the encoding indicates %[abcd]h. Note that the values 600 that are ORed in merely indicate that the REX byte must be present; 601 those bits get discarded in output. */ 602 rex |= opc & (r >= 4 ? P_REXB_R : 0); 603 rex |= opc & (rm >= 4 ? P_REXB_RM : 0); 604 605 if (rex) { 606 tcg_out8(s, (uint8_t)(rex | 0x40)); 607 } 608 609 if (opc & (P_EXT | P_EXT38 | P_EXT3A)) { 610 tcg_out8(s, 0x0f); 611 if (opc & P_EXT38) { 612 tcg_out8(s, 0x38); 613 } else if (opc & P_EXT3A) { 614 tcg_out8(s, 0x3a); 615 } 616 } 617 618 tcg_out8(s, opc); 619} 620#else 621static void tcg_out_opc(TCGContext *s, int opc) 622{ 623 if (opc & P_DATA16) { 624 tcg_out8(s, 0x66); 625 } 626 if (opc & P_SIMDF3) { 627 tcg_out8(s, 0xf3); 628 } else if (opc & P_SIMDF2) { 629 tcg_out8(s, 0xf2); 630 } 631 if (opc & (P_EXT | P_EXT38 | P_EXT3A)) { 632 tcg_out8(s, 0x0f); 633 if (opc & P_EXT38) { 634 tcg_out8(s, 0x38); 635 } else if (opc & P_EXT3A) { 636 tcg_out8(s, 0x3a); 637 } 638 } 639 tcg_out8(s, opc); 640} 641/* Discard the register arguments to tcg_out_opc early, so as not to penalize 642 the 32-bit compilation paths. This method works with all versions of gcc, 643 whereas relying on optimization may not be able to exclude them. */ 644#define tcg_out_opc(s, opc, r, rm, x) (tcg_out_opc)(s, opc) 645#endif 646 647static void tcg_out_modrm(TCGContext *s, int opc, int r, int rm) 648{ 649 tcg_out_opc(s, opc, r, rm, 0); 650 tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm)); 651} 652 653static void tcg_out_vex_opc(TCGContext *s, int opc, int r, int v, 654 int rm, int index) 655{ 656 int tmp; 657 658 if (opc & P_GS) { 659 tcg_out8(s, 0x65); 660 } 661 /* Use the two byte form if possible, which cannot encode 662 VEX.W, VEX.B, VEX.X, or an m-mmmm field other than P_EXT. */ 663 if ((opc & (P_EXT | P_EXT38 | P_EXT3A | P_VEXW)) == P_EXT 664 && ((rm | index) & 8) == 0) { 665 /* Two byte VEX prefix. */ 666 tcg_out8(s, 0xc5); 667 668 tmp = (r & 8 ? 0 : 0x80); /* VEX.R */ 669 } else { 670 /* Three byte VEX prefix. */ 671 tcg_out8(s, 0xc4); 672 673 /* VEX.m-mmmm */ 674 if (opc & P_EXT3A) { 675 tmp = 3; 676 } else if (opc & P_EXT38) { 677 tmp = 2; 678 } else if (opc & P_EXT) { 679 tmp = 1; 680 } else { 681 g_assert_not_reached(); 682 } 683 tmp |= (r & 8 ? 0 : 0x80); /* VEX.R */ 684 tmp |= (index & 8 ? 0 : 0x40); /* VEX.X */ 685 tmp |= (rm & 8 ? 0 : 0x20); /* VEX.B */ 686 tcg_out8(s, tmp); 687 688 tmp = (opc & P_VEXW ? 0x80 : 0); /* VEX.W */ 689 } 690 691 tmp |= (opc & P_VEXL ? 0x04 : 0); /* VEX.L */ 692 /* VEX.pp */ 693 if (opc & P_DATA16) { 694 tmp |= 1; /* 0x66 */ 695 } else if (opc & P_SIMDF3) { 696 tmp |= 2; /* 0xf3 */ 697 } else if (opc & P_SIMDF2) { 698 tmp |= 3; /* 0xf2 */ 699 } 700 tmp |= (~v & 15) << 3; /* VEX.vvvv */ 701 tcg_out8(s, tmp); 702 tcg_out8(s, opc); 703} 704 705static void tcg_out_evex_opc(TCGContext *s, int opc, int r, int v, 706 int rm, int index, int aaa, bool z) 707{ 708 /* The entire 4-byte evex prefix; with R' and V' set. */ 709 uint32_t p = 0x08041062; 710 int mm, pp; 711 712 tcg_debug_assert(have_avx512vl); 713 714 /* EVEX.mm */ 715 if (opc & P_EXT3A) { 716 mm = 3; 717 } else if (opc & P_EXT38) { 718 mm = 2; 719 } else if (opc & P_EXT) { 720 mm = 1; 721 } else { 722 g_assert_not_reached(); 723 } 724 725 /* EVEX.pp */ 726 if (opc & P_DATA16) { 727 pp = 1; /* 0x66 */ 728 } else if (opc & P_SIMDF3) { 729 pp = 2; /* 0xf3 */ 730 } else if (opc & P_SIMDF2) { 731 pp = 3; /* 0xf2 */ 732 } else { 733 pp = 0; 734 } 735 736 p = deposit32(p, 8, 2, mm); 737 p = deposit32(p, 13, 1, (rm & 8) == 0); /* EVEX.RXB.B */ 738 p = deposit32(p, 14, 1, (index & 8) == 0); /* EVEX.RXB.X */ 739 p = deposit32(p, 15, 1, (r & 8) == 0); /* EVEX.RXB.R */ 740 p = deposit32(p, 16, 2, pp); 741 p = deposit32(p, 19, 4, ~v); 742 p = deposit32(p, 23, 1, (opc & P_VEXW) != 0); 743 p = deposit32(p, 24, 3, aaa); 744 p = deposit32(p, 29, 2, (opc & P_VEXL) != 0); 745 p = deposit32(p, 31, 1, z); 746 747 tcg_out32(s, p); 748 tcg_out8(s, opc); 749} 750 751static void tcg_out_vex_modrm(TCGContext *s, int opc, int r, int v, int rm) 752{ 753 if (opc & P_EVEX) { 754 tcg_out_evex_opc(s, opc, r, v, rm, 0, 0, false); 755 } else { 756 tcg_out_vex_opc(s, opc, r, v, rm, 0); 757 } 758 tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm)); 759} 760 761static void tcg_out_vex_modrm_type(TCGContext *s, int opc, 762 int r, int v, int rm, TCGType type) 763{ 764 if (type == TCG_TYPE_V256) { 765 opc |= P_VEXL; 766 } 767 tcg_out_vex_modrm(s, opc, r, v, rm); 768} 769 770static void tcg_out_evex_modrm_type(TCGContext *s, int opc, int r, int v, 771 int rm, int aaa, bool z, TCGType type) 772{ 773 if (type == TCG_TYPE_V256) { 774 opc |= P_VEXL; 775 } 776 tcg_out_evex_opc(s, opc, r, v, rm, 0, aaa, z); 777 tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm)); 778} 779 780/* Output an opcode with a full "rm + (index<<shift) + offset" address mode. 781 We handle either RM and INDEX missing with a negative value. In 64-bit 782 mode for absolute addresses, ~RM is the size of the immediate operand 783 that will follow the instruction. */ 784 785static void tcg_out_sib_offset(TCGContext *s, int r, int rm, int index, 786 int shift, intptr_t offset) 787{ 788 int mod, len; 789 790 if (index < 0 && rm < 0) { 791 if (TCG_TARGET_REG_BITS == 64) { 792 /* Try for a rip-relative addressing mode. This has replaced 793 the 32-bit-mode absolute addressing encoding. */ 794 intptr_t pc = (intptr_t)s->code_ptr + 5 + ~rm; 795 intptr_t disp = offset - pc; 796 if (disp == (int32_t)disp) { 797 tcg_out8(s, (LOWREGMASK(r) << 3) | 5); 798 tcg_out32(s, disp); 799 return; 800 } 801 802 /* Try for an absolute address encoding. This requires the 803 use of the MODRM+SIB encoding and is therefore larger than 804 rip-relative addressing. */ 805 if (offset == (int32_t)offset) { 806 tcg_out8(s, (LOWREGMASK(r) << 3) | 4); 807 tcg_out8(s, (4 << 3) | 5); 808 tcg_out32(s, offset); 809 return; 810 } 811 812 /* ??? The memory isn't directly addressable. */ 813 g_assert_not_reached(); 814 } else { 815 /* Absolute address. */ 816 tcg_out8(s, (r << 3) | 5); 817 tcg_out32(s, offset); 818 return; 819 } 820 } 821 822 /* Find the length of the immediate addend. Note that the encoding 823 that would be used for (%ebp) indicates absolute addressing. */ 824 if (rm < 0) { 825 mod = 0, len = 4, rm = 5; 826 } else if (offset == 0 && LOWREGMASK(rm) != TCG_REG_EBP) { 827 mod = 0, len = 0; 828 } else if (offset == (int8_t)offset) { 829 mod = 0x40, len = 1; 830 } else { 831 mod = 0x80, len = 4; 832 } 833 834 /* Use a single byte MODRM format if possible. Note that the encoding 835 that would be used for %esp is the escape to the two byte form. */ 836 if (index < 0 && LOWREGMASK(rm) != TCG_REG_ESP) { 837 /* Single byte MODRM format. */ 838 tcg_out8(s, mod | (LOWREGMASK(r) << 3) | LOWREGMASK(rm)); 839 } else { 840 /* Two byte MODRM+SIB format. */ 841 842 /* Note that the encoding that would place %esp into the index 843 field indicates no index register. In 64-bit mode, the REX.X 844 bit counts, so %r12 can be used as the index. */ 845 if (index < 0) { 846 index = 4; 847 } else { 848 tcg_debug_assert(index != TCG_REG_ESP); 849 } 850 851 tcg_out8(s, mod | (LOWREGMASK(r) << 3) | 4); 852 tcg_out8(s, (shift << 6) | (LOWREGMASK(index) << 3) | LOWREGMASK(rm)); 853 } 854 855 if (len == 1) { 856 tcg_out8(s, offset); 857 } else if (len == 4) { 858 tcg_out32(s, offset); 859 } 860} 861 862static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm, 863 int index, int shift, intptr_t offset) 864{ 865 tcg_out_opc(s, opc, r, rm < 0 ? 0 : rm, index < 0 ? 0 : index); 866 tcg_out_sib_offset(s, r, rm, index, shift, offset); 867} 868 869static void tcg_out_vex_modrm_sib_offset(TCGContext *s, int opc, int r, int v, 870 int rm, int index, int shift, 871 intptr_t offset) 872{ 873 tcg_out_vex_opc(s, opc, r, v, rm < 0 ? 0 : rm, index < 0 ? 0 : index); 874 tcg_out_sib_offset(s, r, rm, index, shift, offset); 875} 876 877/* A simplification of the above with no index or shift. */ 878static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, 879 int rm, intptr_t offset) 880{ 881 tcg_out_modrm_sib_offset(s, opc, r, rm, -1, 0, offset); 882} 883 884static inline void tcg_out_vex_modrm_offset(TCGContext *s, int opc, int r, 885 int v, int rm, intptr_t offset) 886{ 887 tcg_out_vex_modrm_sib_offset(s, opc, r, v, rm, -1, 0, offset); 888} 889 890/* Output an opcode with an expected reference to the constant pool. */ 891static inline void tcg_out_modrm_pool(TCGContext *s, int opc, int r) 892{ 893 tcg_out_opc(s, opc, r, 0, 0); 894 /* Absolute for 32-bit, pc-relative for 64-bit. */ 895 tcg_out8(s, LOWREGMASK(r) << 3 | 5); 896 tcg_out32(s, 0); 897} 898 899/* Output an opcode with an expected reference to the constant pool. */ 900static inline void tcg_out_vex_modrm_pool(TCGContext *s, int opc, int r) 901{ 902 tcg_out_vex_opc(s, opc, r, 0, 0, 0); 903 /* Absolute for 32-bit, pc-relative for 64-bit. */ 904 tcg_out8(s, LOWREGMASK(r) << 3 | 5); 905 tcg_out32(s, 0); 906} 907 908/* Generate dest op= src. Uses the same ARITH_* codes as tgen_arithi. */ 909static inline void tgen_arithr(TCGContext *s, int subop, int dest, int src) 910{ 911 /* Propagate an opcode prefix, such as P_REXW. */ 912 int ext = subop & ~0x7; 913 subop &= 0x7; 914 915 tcg_out_modrm(s, OPC_ARITH_GvEv + (subop << 3) + ext, dest, src); 916} 917 918static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 919{ 920 int rexw = 0; 921 922 if (arg == ret) { 923 return true; 924 } 925 switch (type) { 926 case TCG_TYPE_I64: 927 rexw = P_REXW; 928 /* fallthru */ 929 case TCG_TYPE_I32: 930 if (ret < 16) { 931 if (arg < 16) { 932 tcg_out_modrm(s, OPC_MOVL_GvEv + rexw, ret, arg); 933 } else { 934 tcg_out_vex_modrm(s, OPC_MOVD_EyVy + rexw, arg, 0, ret); 935 } 936 } else { 937 if (arg < 16) { 938 tcg_out_vex_modrm(s, OPC_MOVD_VyEy + rexw, ret, 0, arg); 939 } else { 940 tcg_out_vex_modrm(s, OPC_MOVQ_VqWq, ret, 0, arg); 941 } 942 } 943 break; 944 945 case TCG_TYPE_V64: 946 tcg_debug_assert(ret >= 16 && arg >= 16); 947 tcg_out_vex_modrm(s, OPC_MOVQ_VqWq, ret, 0, arg); 948 break; 949 case TCG_TYPE_V128: 950 tcg_debug_assert(ret >= 16 && arg >= 16); 951 tcg_out_vex_modrm(s, OPC_MOVDQA_VxWx, ret, 0, arg); 952 break; 953 case TCG_TYPE_V256: 954 tcg_debug_assert(ret >= 16 && arg >= 16); 955 tcg_out_vex_modrm(s, OPC_MOVDQA_VxWx | P_VEXL, ret, 0, arg); 956 break; 957 958 default: 959 g_assert_not_reached(); 960 } 961 return true; 962} 963 964static const int avx2_dup_insn[4] = { 965 OPC_VPBROADCASTB, OPC_VPBROADCASTW, 966 OPC_VPBROADCASTD, OPC_VPBROADCASTQ, 967}; 968 969static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 970 TCGReg r, TCGReg a) 971{ 972 if (have_avx2) { 973 tcg_out_vex_modrm_type(s, avx2_dup_insn[vece], r, 0, a, type); 974 } else { 975 switch (vece) { 976 case MO_8: 977 /* ??? With zero in a register, use PSHUFB. */ 978 tcg_out_vex_modrm(s, OPC_PUNPCKLBW, r, a, a); 979 a = r; 980 /* FALLTHRU */ 981 case MO_16: 982 tcg_out_vex_modrm(s, OPC_PUNPCKLWD, r, a, a); 983 a = r; 984 /* FALLTHRU */ 985 case MO_32: 986 tcg_out_vex_modrm(s, OPC_PSHUFD, r, 0, a); 987 /* imm8 operand: all output lanes selected from input lane 0. */ 988 tcg_out8(s, 0); 989 break; 990 case MO_64: 991 tcg_out_vex_modrm(s, OPC_PUNPCKLQDQ, r, a, a); 992 break; 993 default: 994 g_assert_not_reached(); 995 } 996 } 997 return true; 998} 999 1000static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 1001 TCGReg r, TCGReg base, intptr_t offset) 1002{ 1003 if (have_avx2) { 1004 int vex_l = (type == TCG_TYPE_V256 ? P_VEXL : 0); 1005 tcg_out_vex_modrm_offset(s, avx2_dup_insn[vece] + vex_l, 1006 r, 0, base, offset); 1007 } else { 1008 switch (vece) { 1009 case MO_64: 1010 tcg_out_vex_modrm_offset(s, OPC_MOVDDUP, r, 0, base, offset); 1011 break; 1012 case MO_32: 1013 tcg_out_vex_modrm_offset(s, OPC_VBROADCASTSS, r, 0, base, offset); 1014 break; 1015 case MO_16: 1016 tcg_out_vex_modrm_offset(s, OPC_VPINSRW, r, r, base, offset); 1017 tcg_out8(s, 0); /* imm8 */ 1018 tcg_out_dup_vec(s, type, vece, r, r); 1019 break; 1020 case MO_8: 1021 tcg_out_vex_modrm_offset(s, OPC_VPINSRB, r, r, base, offset); 1022 tcg_out8(s, 0); /* imm8 */ 1023 tcg_out_dup_vec(s, type, vece, r, r); 1024 break; 1025 default: 1026 g_assert_not_reached(); 1027 } 1028 } 1029 return true; 1030} 1031 1032static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 1033 TCGReg ret, int64_t arg) 1034{ 1035 int vex_l = (type == TCG_TYPE_V256 ? P_VEXL : 0); 1036 1037 if (arg == 0) { 1038 tcg_out_vex_modrm(s, OPC_PXOR, ret, ret, ret); 1039 return; 1040 } 1041 if (arg == -1) { 1042 tcg_out_vex_modrm(s, OPC_PCMPEQB + vex_l, ret, ret, ret); 1043 return; 1044 } 1045 1046 if (TCG_TARGET_REG_BITS == 32 && vece < MO_64) { 1047 if (have_avx2) { 1048 tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTD + vex_l, ret); 1049 } else { 1050 tcg_out_vex_modrm_pool(s, OPC_VBROADCASTSS, ret); 1051 } 1052 new_pool_label(s, arg, R_386_32, s->code_ptr - 4, 0); 1053 } else { 1054 if (type == TCG_TYPE_V64) { 1055 tcg_out_vex_modrm_pool(s, OPC_MOVQ_VqWq, ret); 1056 } else if (have_avx2) { 1057 tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTQ + vex_l, ret); 1058 } else { 1059 tcg_out_vex_modrm_pool(s, OPC_MOVDDUP, ret); 1060 } 1061 if (TCG_TARGET_REG_BITS == 64) { 1062 new_pool_label(s, arg, R_386_PC32, s->code_ptr - 4, -4); 1063 } else { 1064 new_pool_l2(s, R_386_32, s->code_ptr - 4, 0, arg, arg >> 32); 1065 } 1066 } 1067} 1068 1069static void tcg_out_movi_vec(TCGContext *s, TCGType type, 1070 TCGReg ret, tcg_target_long arg) 1071{ 1072 if (arg == 0) { 1073 tcg_out_vex_modrm(s, OPC_PXOR, ret, ret, ret); 1074 return; 1075 } 1076 if (arg == -1) { 1077 tcg_out_vex_modrm(s, OPC_PCMPEQB, ret, ret, ret); 1078 return; 1079 } 1080 1081 int rexw = (type == TCG_TYPE_I32 ? 0 : P_REXW); 1082 tcg_out_vex_modrm_pool(s, OPC_MOVD_VyEy + rexw, ret); 1083 if (TCG_TARGET_REG_BITS == 64) { 1084 new_pool_label(s, arg, R_386_PC32, s->code_ptr - 4, -4); 1085 } else { 1086 new_pool_label(s, arg, R_386_32, s->code_ptr - 4, 0); 1087 } 1088} 1089 1090static void tcg_out_movi_int(TCGContext *s, TCGType type, 1091 TCGReg ret, tcg_target_long arg) 1092{ 1093 tcg_target_long diff; 1094 1095 if (arg == 0) { 1096 tgen_arithr(s, ARITH_XOR, ret, ret); 1097 return; 1098 } 1099 if (arg == (uint32_t)arg || type == TCG_TYPE_I32) { 1100 tcg_out_opc(s, OPC_MOVL_Iv + LOWREGMASK(ret), 0, ret, 0); 1101 tcg_out32(s, arg); 1102 return; 1103 } 1104 if (arg == (int32_t)arg) { 1105 tcg_out_modrm(s, OPC_MOVL_EvIz + P_REXW, 0, ret); 1106 tcg_out32(s, arg); 1107 return; 1108 } 1109 1110 /* Try a 7 byte pc-relative lea before the 10 byte movq. */ 1111 diff = tcg_pcrel_diff(s, (const void *)arg) - 7; 1112 if (diff == (int32_t)diff) { 1113 tcg_out_opc(s, OPC_LEA | P_REXW, ret, 0, 0); 1114 tcg_out8(s, (LOWREGMASK(ret) << 3) | 5); 1115 tcg_out32(s, diff); 1116 return; 1117 } 1118 1119 tcg_out_opc(s, OPC_MOVL_Iv + P_REXW + LOWREGMASK(ret), 0, ret, 0); 1120 tcg_out64(s, arg); 1121} 1122 1123static void tcg_out_movi(TCGContext *s, TCGType type, 1124 TCGReg ret, tcg_target_long arg) 1125{ 1126 switch (type) { 1127 case TCG_TYPE_I32: 1128#if TCG_TARGET_REG_BITS == 64 1129 case TCG_TYPE_I64: 1130#endif 1131 if (ret < 16) { 1132 tcg_out_movi_int(s, type, ret, arg); 1133 } else { 1134 tcg_out_movi_vec(s, type, ret, arg); 1135 } 1136 break; 1137 default: 1138 g_assert_not_reached(); 1139 } 1140} 1141 1142static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 1143{ 1144 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 1145 tcg_out_modrm(s, OPC_XCHG_EvGv + rexw, r1, r2); 1146 return true; 1147} 1148 1149static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 1150 tcg_target_long imm) 1151{ 1152 /* This function is only used for passing structs by reference. */ 1153 tcg_debug_assert(imm == (int32_t)imm); 1154 tcg_out_modrm_offset(s, OPC_LEA | P_REXW, rd, rs, imm); 1155} 1156 1157static inline void tcg_out_pushi(TCGContext *s, tcg_target_long val) 1158{ 1159 if (val == (int8_t)val) { 1160 tcg_out_opc(s, OPC_PUSH_Ib, 0, 0, 0); 1161 tcg_out8(s, val); 1162 } else if (val == (int32_t)val) { 1163 tcg_out_opc(s, OPC_PUSH_Iv, 0, 0, 0); 1164 tcg_out32(s, val); 1165 } else { 1166 g_assert_not_reached(); 1167 } 1168} 1169 1170static inline void tcg_out_mb(TCGContext *s, TCGArg a0) 1171{ 1172 /* Given the strength of x86 memory ordering, we only need care for 1173 store-load ordering. Experimentally, "lock orl $0,0(%esp)" is 1174 faster than "mfence", so don't bother with the sse insn. */ 1175 if (a0 & TCG_MO_ST_LD) { 1176 tcg_out8(s, 0xf0); 1177 tcg_out_modrm_offset(s, OPC_ARITH_EvIb, ARITH_OR, TCG_REG_ESP, 0); 1178 tcg_out8(s, 0); 1179 } 1180} 1181 1182static inline void tcg_out_push(TCGContext *s, int reg) 1183{ 1184 tcg_out_opc(s, OPC_PUSH_r32 + LOWREGMASK(reg), 0, reg, 0); 1185} 1186 1187static inline void tcg_out_pop(TCGContext *s, int reg) 1188{ 1189 tcg_out_opc(s, OPC_POP_r32 + LOWREGMASK(reg), 0, reg, 0); 1190} 1191 1192static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, 1193 TCGReg arg1, intptr_t arg2) 1194{ 1195 switch (type) { 1196 case TCG_TYPE_I32: 1197 if (ret < 16) { 1198 tcg_out_modrm_offset(s, OPC_MOVL_GvEv, ret, arg1, arg2); 1199 } else { 1200 tcg_out_vex_modrm_offset(s, OPC_MOVD_VyEy, ret, 0, arg1, arg2); 1201 } 1202 break; 1203 case TCG_TYPE_I64: 1204 if (ret < 16) { 1205 tcg_out_modrm_offset(s, OPC_MOVL_GvEv | P_REXW, ret, arg1, arg2); 1206 break; 1207 } 1208 /* FALLTHRU */ 1209 case TCG_TYPE_V64: 1210 /* There is no instruction that can validate 8-byte alignment. */ 1211 tcg_debug_assert(ret >= 16); 1212 tcg_out_vex_modrm_offset(s, OPC_MOVQ_VqWq, ret, 0, arg1, arg2); 1213 break; 1214 case TCG_TYPE_V128: 1215 /* 1216 * The gvec infrastructure is asserts that v128 vector loads 1217 * and stores use a 16-byte aligned offset. Validate that the 1218 * final pointer is aligned by using an insn that will SIGSEGV. 1219 */ 1220 tcg_debug_assert(ret >= 16); 1221 tcg_out_vex_modrm_offset(s, OPC_MOVDQA_VxWx, ret, 0, arg1, arg2); 1222 break; 1223 case TCG_TYPE_V256: 1224 /* 1225 * The gvec infrastructure only requires 16-byte alignment, 1226 * so here we must use an unaligned load. 1227 */ 1228 tcg_debug_assert(ret >= 16); 1229 tcg_out_vex_modrm_offset(s, OPC_MOVDQU_VxWx | P_VEXL, 1230 ret, 0, arg1, arg2); 1231 break; 1232 default: 1233 g_assert_not_reached(); 1234 } 1235} 1236 1237static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 1238 TCGReg arg1, intptr_t arg2) 1239{ 1240 switch (type) { 1241 case TCG_TYPE_I32: 1242 if (arg < 16) { 1243 tcg_out_modrm_offset(s, OPC_MOVL_EvGv, arg, arg1, arg2); 1244 } else { 1245 tcg_out_vex_modrm_offset(s, OPC_MOVD_EyVy, arg, 0, arg1, arg2); 1246 } 1247 break; 1248 case TCG_TYPE_I64: 1249 if (arg < 16) { 1250 tcg_out_modrm_offset(s, OPC_MOVL_EvGv | P_REXW, arg, arg1, arg2); 1251 break; 1252 } 1253 /* FALLTHRU */ 1254 case TCG_TYPE_V64: 1255 /* There is no instruction that can validate 8-byte alignment. */ 1256 tcg_debug_assert(arg >= 16); 1257 tcg_out_vex_modrm_offset(s, OPC_MOVQ_WqVq, arg, 0, arg1, arg2); 1258 break; 1259 case TCG_TYPE_V128: 1260 /* 1261 * The gvec infrastructure is asserts that v128 vector loads 1262 * and stores use a 16-byte aligned offset. Validate that the 1263 * final pointer is aligned by using an insn that will SIGSEGV. 1264 * 1265 * This specific instance is also used by TCG_CALL_RET_BY_VEC, 1266 * for _WIN64, which must have SSE2 but may not have AVX. 1267 */ 1268 tcg_debug_assert(arg >= 16); 1269 if (have_avx1) { 1270 tcg_out_vex_modrm_offset(s, OPC_MOVDQA_WxVx, arg, 0, arg1, arg2); 1271 } else { 1272 tcg_out_modrm_offset(s, OPC_MOVDQA_WxVx, arg, arg1, arg2); 1273 } 1274 break; 1275 case TCG_TYPE_V256: 1276 /* 1277 * The gvec infrastructure only requires 16-byte alignment, 1278 * so here we must use an unaligned store. 1279 */ 1280 tcg_debug_assert(arg >= 16); 1281 tcg_out_vex_modrm_offset(s, OPC_MOVDQU_WxVx | P_VEXL, 1282 arg, 0, arg1, arg2); 1283 break; 1284 default: 1285 g_assert_not_reached(); 1286 } 1287} 1288 1289static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 1290 TCGReg base, intptr_t ofs) 1291{ 1292 int rexw = 0; 1293 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64) { 1294 if (val != (int32_t)val) { 1295 return false; 1296 } 1297 rexw = P_REXW; 1298 } else if (type != TCG_TYPE_I32) { 1299 return false; 1300 } 1301 tcg_out_modrm_offset(s, OPC_MOVL_EvIz | rexw, 0, base, ofs); 1302 tcg_out32(s, val); 1303 return true; 1304} 1305 1306static void tcg_out_shifti(TCGContext *s, int subopc, int reg, int count) 1307{ 1308 /* Propagate an opcode prefix, such as P_DATA16. */ 1309 int ext = subopc & ~0x7; 1310 subopc &= 0x7; 1311 1312 if (count == 1) { 1313 tcg_out_modrm(s, OPC_SHIFT_1 + ext, subopc, reg); 1314 } else { 1315 tcg_out_modrm(s, OPC_SHIFT_Ib + ext, subopc, reg); 1316 tcg_out8(s, count); 1317 } 1318} 1319 1320static inline void tcg_out_bswap32(TCGContext *s, int reg) 1321{ 1322 tcg_out_opc(s, OPC_BSWAP + LOWREGMASK(reg), 0, reg, 0); 1323} 1324 1325static inline void tcg_out_rolw_8(TCGContext *s, int reg) 1326{ 1327 tcg_out_shifti(s, SHIFT_ROL + P_DATA16, reg, 8); 1328} 1329 1330static void tcg_out_ext8u(TCGContext *s, TCGReg dest, TCGReg src) 1331{ 1332 if (TCG_TARGET_REG_BITS == 32 && src >= 4) { 1333 tcg_out_mov(s, TCG_TYPE_I32, dest, src); 1334 if (dest >= 4) { 1335 tcg_out_modrm(s, OPC_ARITH_EvIz, ARITH_AND, dest); 1336 tcg_out32(s, 0xff); 1337 return; 1338 } 1339 src = dest; 1340 } 1341 tcg_out_modrm(s, OPC_MOVZBL + P_REXB_RM, dest, src); 1342} 1343 1344static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) 1345{ 1346 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 1347 1348 if (TCG_TARGET_REG_BITS == 32 && src >= 4) { 1349 tcg_out_mov(s, TCG_TYPE_I32, dest, src); 1350 if (dest >= 4) { 1351 tcg_out_shifti(s, SHIFT_SHL, dest, 24); 1352 tcg_out_shifti(s, SHIFT_SAR, dest, 24); 1353 return; 1354 } 1355 src = dest; 1356 } 1357 tcg_out_modrm(s, OPC_MOVSBL + P_REXB_RM + rexw, dest, src); 1358} 1359 1360static void tcg_out_ext16u(TCGContext *s, TCGReg dest, TCGReg src) 1361{ 1362 /* movzwl */ 1363 tcg_out_modrm(s, OPC_MOVZWL, dest, src); 1364} 1365 1366static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) 1367{ 1368 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 1369 /* movsw[lq] */ 1370 tcg_out_modrm(s, OPC_MOVSWL + rexw, dest, src); 1371} 1372 1373static void tcg_out_ext32u(TCGContext *s, TCGReg dest, TCGReg src) 1374{ 1375 /* 32-bit mov zero extends. */ 1376 tcg_out_modrm(s, OPC_MOVL_GvEv, dest, src); 1377} 1378 1379static void tcg_out_ext32s(TCGContext *s, TCGReg dest, TCGReg src) 1380{ 1381 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 1382 tcg_out_modrm(s, OPC_MOVSLQ, dest, src); 1383} 1384 1385static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg dest, TCGReg src) 1386{ 1387 tcg_out_ext32s(s, dest, src); 1388} 1389 1390static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg dest, TCGReg src) 1391{ 1392 if (dest != src) { 1393 tcg_out_ext32u(s, dest, src); 1394 } 1395} 1396 1397static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg dest, TCGReg src) 1398{ 1399 tcg_out_ext32u(s, dest, src); 1400} 1401 1402static inline void tcg_out_bswap64(TCGContext *s, int reg) 1403{ 1404 tcg_out_opc(s, OPC_BSWAP + P_REXW + LOWREGMASK(reg), 0, reg, 0); 1405} 1406 1407static void tgen_arithi(TCGContext *s, int c, int r0, 1408 tcg_target_long val, int cf) 1409{ 1410 int rexw = 0; 1411 1412 if (TCG_TARGET_REG_BITS == 64) { 1413 rexw = c & -8; 1414 c &= 7; 1415 } 1416 1417 switch (c) { 1418 case ARITH_ADD: 1419 case ARITH_SUB: 1420 if (!cf) { 1421 /* 1422 * ??? While INC is 2 bytes shorter than ADDL $1, they also induce 1423 * partial flags update stalls on Pentium4 and are not recommended 1424 * by current Intel optimization manuals. 1425 */ 1426 if (val == 1 || val == -1) { 1427 int is_inc = (c == ARITH_ADD) ^ (val < 0); 1428 if (TCG_TARGET_REG_BITS == 64) { 1429 /* 1430 * The single-byte increment encodings are re-tasked 1431 * as the REX prefixes. Use the MODRM encoding. 1432 */ 1433 tcg_out_modrm(s, OPC_GRP5 + rexw, 1434 (is_inc ? EXT5_INC_Ev : EXT5_DEC_Ev), r0); 1435 } else { 1436 tcg_out8(s, (is_inc ? OPC_INC_r32 : OPC_DEC_r32) + r0); 1437 } 1438 return; 1439 } 1440 if (val == 128) { 1441 /* 1442 * Facilitate using an 8-bit immediate. Carry is inverted 1443 * by this transformation, so do it only if cf == 0. 1444 */ 1445 c ^= ARITH_ADD ^ ARITH_SUB; 1446 val = -128; 1447 } 1448 } 1449 break; 1450 1451 case ARITH_AND: 1452 if (TCG_TARGET_REG_BITS == 64) { 1453 if (val == 0xffffffffu) { 1454 tcg_out_ext32u(s, r0, r0); 1455 return; 1456 } 1457 if (val == (uint32_t)val) { 1458 /* AND with no high bits set can use a 32-bit operation. */ 1459 rexw = 0; 1460 } 1461 } 1462 if (val == 0xffu && (r0 < 4 || TCG_TARGET_REG_BITS == 64)) { 1463 tcg_out_ext8u(s, r0, r0); 1464 return; 1465 } 1466 if (val == 0xffffu) { 1467 tcg_out_ext16u(s, r0, r0); 1468 return; 1469 } 1470 break; 1471 1472 case ARITH_OR: 1473 case ARITH_XOR: 1474 if (val >= 0x80 && val <= 0xff 1475 && (r0 < 4 || TCG_TARGET_REG_BITS == 64)) { 1476 tcg_out_modrm(s, OPC_ARITH_EbIb + P_REXB_RM, c, r0); 1477 tcg_out8(s, val); 1478 return; 1479 } 1480 break; 1481 } 1482 1483 if (val == (int8_t)val) { 1484 tcg_out_modrm(s, OPC_ARITH_EvIb + rexw, c, r0); 1485 tcg_out8(s, val); 1486 return; 1487 } 1488 if (rexw == 0 || val == (int32_t)val) { 1489 tcg_out_modrm(s, OPC_ARITH_EvIz + rexw, c, r0); 1490 tcg_out32(s, val); 1491 return; 1492 } 1493 1494 g_assert_not_reached(); 1495} 1496 1497static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val) 1498{ 1499 if (val != 0) { 1500 tgen_arithi(s, ARITH_ADD + P_REXW, reg, val, 0); 1501 } 1502} 1503 1504/* Set SMALL to force a short forward branch. */ 1505static void tcg_out_jxx(TCGContext *s, int opc, TCGLabel *l, bool small) 1506{ 1507 int32_t val, val1; 1508 1509 if (l->has_value) { 1510 val = tcg_pcrel_diff(s, l->u.value_ptr); 1511 val1 = val - 2; 1512 if ((int8_t)val1 == val1) { 1513 if (opc == -1) { 1514 tcg_out8(s, OPC_JMP_short); 1515 } else { 1516 tcg_out8(s, OPC_JCC_short + opc); 1517 } 1518 tcg_out8(s, val1); 1519 } else { 1520 tcg_debug_assert(!small); 1521 if (opc == -1) { 1522 tcg_out8(s, OPC_JMP_long); 1523 tcg_out32(s, val - 5); 1524 } else { 1525 tcg_out_opc(s, OPC_JCC_long + opc, 0, 0, 0); 1526 tcg_out32(s, val - 6); 1527 } 1528 } 1529 } else if (small) { 1530 if (opc == -1) { 1531 tcg_out8(s, OPC_JMP_short); 1532 } else { 1533 tcg_out8(s, OPC_JCC_short + opc); 1534 } 1535 tcg_out_reloc(s, s->code_ptr, R_386_PC8, l, -1); 1536 s->code_ptr += 1; 1537 } else { 1538 if (opc == -1) { 1539 tcg_out8(s, OPC_JMP_long); 1540 } else { 1541 tcg_out_opc(s, OPC_JCC_long + opc, 0, 0, 0); 1542 } 1543 tcg_out_reloc(s, s->code_ptr, R_386_PC32, l, -4); 1544 s->code_ptr += 4; 1545 } 1546} 1547 1548static int tcg_out_cmp(TCGContext *s, TCGCond cond, TCGArg arg1, 1549 TCGArg arg2, int const_arg2, int rexw) 1550{ 1551 int jz, js; 1552 1553 if (!is_tst_cond(cond)) { 1554 if (!const_arg2) { 1555 tgen_arithr(s, ARITH_CMP + rexw, arg1, arg2); 1556 } else if (arg2 == 0) { 1557 tcg_out_modrm(s, OPC_TESTL + rexw, arg1, arg1); 1558 } else { 1559 tcg_debug_assert(!rexw || arg2 == (int32_t)arg2); 1560 tgen_arithi(s, ARITH_CMP + rexw, arg1, arg2, 0); 1561 } 1562 return tcg_cond_to_jcc[cond]; 1563 } 1564 1565 jz = tcg_cond_to_jcc[cond]; 1566 js = (cond == TCG_COND_TSTNE ? JCC_JS : JCC_JNS); 1567 1568 if (!const_arg2) { 1569 tcg_out_modrm(s, OPC_TESTL + rexw, arg1, arg2); 1570 return jz; 1571 } 1572 1573 if (arg2 <= 0xff && (TCG_TARGET_REG_BITS == 64 || arg1 < 4)) { 1574 if (arg2 == 0x80) { 1575 tcg_out_modrm(s, OPC_TESTB | P_REXB_R, arg1, arg1); 1576 return js; 1577 } 1578 if (arg2 == 0xff) { 1579 tcg_out_modrm(s, OPC_TESTB | P_REXB_R, arg1, arg1); 1580 return jz; 1581 } 1582 tcg_out_modrm(s, OPC_GRP3_Eb | P_REXB_RM, EXT3_TESTi, arg1); 1583 tcg_out8(s, arg2); 1584 return jz; 1585 } 1586 1587 if ((arg2 & ~0xff00) == 0 && arg1 < 4) { 1588 if (arg2 == 0x8000) { 1589 tcg_out_modrm(s, OPC_TESTB, arg1 + 4, arg1 + 4); 1590 return js; 1591 } 1592 if (arg2 == 0xff00) { 1593 tcg_out_modrm(s, OPC_TESTB, arg1 + 4, arg1 + 4); 1594 return jz; 1595 } 1596 tcg_out_modrm(s, OPC_GRP3_Eb, EXT3_TESTi, arg1 + 4); 1597 tcg_out8(s, arg2 >> 8); 1598 return jz; 1599 } 1600 1601 if (arg2 == 0xffff) { 1602 tcg_out_modrm(s, OPC_TESTL | P_DATA16, arg1, arg1); 1603 return jz; 1604 } 1605 if (arg2 == 0xffffffffu) { 1606 tcg_out_modrm(s, OPC_TESTL, arg1, arg1); 1607 return jz; 1608 } 1609 1610 if (is_power_of_2(rexw ? arg2 : (uint32_t)arg2)) { 1611 int jc = (cond == TCG_COND_TSTNE ? JCC_JB : JCC_JAE); 1612 int sh = ctz64(arg2); 1613 1614 rexw = (sh & 32 ? P_REXW : 0); 1615 if ((sh & 31) == 31) { 1616 tcg_out_modrm(s, OPC_TESTL | rexw, arg1, arg1); 1617 return js; 1618 } else { 1619 tcg_out_modrm(s, OPC_GRPBT | rexw, OPC_GRPBT_BT, arg1); 1620 tcg_out8(s, sh); 1621 return jc; 1622 } 1623 } 1624 1625 if (rexw) { 1626 if (arg2 == (uint32_t)arg2) { 1627 rexw = 0; 1628 } else { 1629 tcg_debug_assert(arg2 == (int32_t)arg2); 1630 } 1631 } 1632 tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_TESTi, arg1); 1633 tcg_out32(s, arg2); 1634 return jz; 1635} 1636 1637static void tcg_out_brcond(TCGContext *s, int rexw, TCGCond cond, 1638 TCGArg arg1, TCGArg arg2, int const_arg2, 1639 TCGLabel *label, bool small) 1640{ 1641 int jcc = tcg_out_cmp(s, cond, arg1, arg2, const_arg2, rexw); 1642 tcg_out_jxx(s, jcc, label, small); 1643} 1644 1645#if TCG_TARGET_REG_BITS == 32 1646static void tcg_out_brcond2(TCGContext *s, const TCGArg *args, 1647 const int *const_args, bool small) 1648{ 1649 TCGLabel *label_next = gen_new_label(); 1650 TCGLabel *label_this = arg_label(args[5]); 1651 TCGCond cond = args[4]; 1652 1653 switch (cond) { 1654 case TCG_COND_EQ: 1655 case TCG_COND_TSTEQ: 1656 tcg_out_brcond(s, 0, tcg_invert_cond(cond), 1657 args[0], args[2], const_args[2], label_next, 1); 1658 tcg_out_brcond(s, 0, cond, args[1], args[3], const_args[3], 1659 label_this, small); 1660 break; 1661 1662 case TCG_COND_NE: 1663 case TCG_COND_TSTNE: 1664 tcg_out_brcond(s, 0, cond, args[0], args[2], const_args[2], 1665 label_this, small); 1666 tcg_out_brcond(s, 0, cond, args[1], args[3], const_args[3], 1667 label_this, small); 1668 break; 1669 1670 default: 1671 tcg_out_brcond(s, 0, tcg_high_cond(cond), args[1], 1672 args[3], const_args[3], label_this, small); 1673 tcg_out_jxx(s, JCC_JNE, label_next, 1); 1674 tcg_out_brcond(s, 0, tcg_unsigned_cond(cond), args[0], 1675 args[2], const_args[2], label_this, small); 1676 break; 1677 } 1678 tcg_out_label(s, label_next); 1679} 1680#endif 1681 1682static void tcg_out_setcond(TCGContext *s, int rexw, TCGCond cond, 1683 TCGArg dest, TCGArg arg1, TCGArg arg2, 1684 int const_arg2, bool neg) 1685{ 1686 int cmp_rexw = rexw; 1687 bool inv = false; 1688 bool cleared; 1689 int jcc; 1690 1691 switch (cond) { 1692 case TCG_COND_NE: 1693 inv = true; 1694 /* fall through */ 1695 case TCG_COND_EQ: 1696 /* If arg2 is 0, convert to LTU/GEU vs 1. */ 1697 if (const_arg2 && arg2 == 0) { 1698 arg2 = 1; 1699 goto do_ltu; 1700 } 1701 break; 1702 1703 case TCG_COND_TSTNE: 1704 inv = true; 1705 /* fall through */ 1706 case TCG_COND_TSTEQ: 1707 /* If arg2 is -1, convert to LTU/GEU vs 1. */ 1708 if (const_arg2 && arg2 == 0xffffffffu) { 1709 arg2 = 1; 1710 cmp_rexw = 0; 1711 goto do_ltu; 1712 } 1713 break; 1714 1715 case TCG_COND_LEU: 1716 inv = true; 1717 /* fall through */ 1718 case TCG_COND_GTU: 1719 /* If arg2 is a register, swap for LTU/GEU. */ 1720 if (!const_arg2) { 1721 TCGReg t = arg1; 1722 arg1 = arg2; 1723 arg2 = t; 1724 goto do_ltu; 1725 } 1726 break; 1727 1728 case TCG_COND_GEU: 1729 inv = true; 1730 /* fall through */ 1731 case TCG_COND_LTU: 1732 do_ltu: 1733 /* 1734 * Relying on the carry bit, use SBB to produce -1 if LTU, 0 if GEU. 1735 * We can then use NEG or INC to produce the desired result. 1736 * This is always smaller than the SETCC expansion. 1737 */ 1738 tcg_out_cmp(s, TCG_COND_LTU, arg1, arg2, const_arg2, cmp_rexw); 1739 1740 /* X - X - C = -C = (C ? -1 : 0) */ 1741 tgen_arithr(s, ARITH_SBB + (neg ? rexw : 0), dest, dest); 1742 if (inv && neg) { 1743 /* ~(C ? -1 : 0) = (C ? 0 : -1) */ 1744 tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NOT, dest); 1745 } else if (inv) { 1746 /* (C ? -1 : 0) + 1 = (C ? 0 : 1) */ 1747 tgen_arithi(s, ARITH_ADD, dest, 1, 0); 1748 } else if (!neg) { 1749 /* -(C ? -1 : 0) = (C ? 1 : 0) */ 1750 tcg_out_modrm(s, OPC_GRP3_Ev, EXT3_NEG, dest); 1751 } 1752 return; 1753 1754 case TCG_COND_GE: 1755 inv = true; 1756 /* fall through */ 1757 case TCG_COND_LT: 1758 /* If arg2 is 0, extract the sign bit. */ 1759 if (const_arg2 && arg2 == 0) { 1760 tcg_out_mov(s, rexw ? TCG_TYPE_I64 : TCG_TYPE_I32, dest, arg1); 1761 if (inv) { 1762 tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NOT, dest); 1763 } 1764 tcg_out_shifti(s, (neg ? SHIFT_SAR : SHIFT_SHR) + rexw, 1765 dest, rexw ? 63 : 31); 1766 return; 1767 } 1768 break; 1769 1770 default: 1771 break; 1772 } 1773 1774 /* 1775 * If dest does not overlap the inputs, clearing it first is preferred. 1776 * The XOR breaks any false dependency for the low-byte write to dest, 1777 * and is also one byte smaller than MOVZBL. 1778 */ 1779 cleared = false; 1780 if (dest != arg1 && (const_arg2 || dest != arg2)) { 1781 tgen_arithr(s, ARITH_XOR, dest, dest); 1782 cleared = true; 1783 } 1784 1785 jcc = tcg_out_cmp(s, cond, arg1, arg2, const_arg2, cmp_rexw); 1786 tcg_out_modrm(s, OPC_SETCC | jcc, 0, dest); 1787 1788 if (!cleared) { 1789 tcg_out_ext8u(s, dest, dest); 1790 } 1791 if (neg) { 1792 tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NEG, dest); 1793 } 1794} 1795 1796#if TCG_TARGET_REG_BITS == 32 1797static void tcg_out_setcond2(TCGContext *s, const TCGArg *args, 1798 const int *const_args) 1799{ 1800 TCGArg new_args[6]; 1801 TCGLabel *label_true, *label_over; 1802 1803 memcpy(new_args, args+1, 5*sizeof(TCGArg)); 1804 1805 if (args[0] == args[1] || args[0] == args[2] 1806 || (!const_args[3] && args[0] == args[3]) 1807 || (!const_args[4] && args[0] == args[4])) { 1808 /* When the destination overlaps with one of the argument 1809 registers, don't do anything tricky. */ 1810 label_true = gen_new_label(); 1811 label_over = gen_new_label(); 1812 1813 new_args[5] = label_arg(label_true); 1814 tcg_out_brcond2(s, new_args, const_args+1, 1); 1815 1816 tcg_out_movi(s, TCG_TYPE_I32, args[0], 0); 1817 tcg_out_jxx(s, JCC_JMP, label_over, 1); 1818 tcg_out_label(s, label_true); 1819 1820 tcg_out_movi(s, TCG_TYPE_I32, args[0], 1); 1821 tcg_out_label(s, label_over); 1822 } else { 1823 /* When the destination does not overlap one of the arguments, 1824 clear the destination first, jump if cond false, and emit an 1825 increment in the true case. This results in smaller code. */ 1826 1827 tcg_out_movi(s, TCG_TYPE_I32, args[0], 0); 1828 1829 label_over = gen_new_label(); 1830 new_args[4] = tcg_invert_cond(new_args[4]); 1831 new_args[5] = label_arg(label_over); 1832 tcg_out_brcond2(s, new_args, const_args+1, 1); 1833 1834 tgen_arithi(s, ARITH_ADD, args[0], 1, 0); 1835 tcg_out_label(s, label_over); 1836 } 1837} 1838#endif 1839 1840static void tcg_out_cmov(TCGContext *s, int jcc, int rexw, 1841 TCGReg dest, TCGReg v1) 1842{ 1843 tcg_out_modrm(s, OPC_CMOVCC | jcc | rexw, dest, v1); 1844} 1845 1846static void tcg_out_movcond(TCGContext *s, int rexw, TCGCond cond, 1847 TCGReg dest, TCGReg c1, TCGArg c2, int const_c2, 1848 TCGReg v1) 1849{ 1850 int jcc = tcg_out_cmp(s, cond, c1, c2, const_c2, rexw); 1851 tcg_out_cmov(s, jcc, rexw, dest, v1); 1852} 1853 1854static void tcg_out_ctz(TCGContext *s, int rexw, TCGReg dest, TCGReg arg1, 1855 TCGArg arg2, bool const_a2) 1856{ 1857 if (have_bmi1) { 1858 tcg_out_modrm(s, OPC_TZCNT + rexw, dest, arg1); 1859 if (const_a2) { 1860 tcg_debug_assert(arg2 == (rexw ? 64 : 32)); 1861 } else { 1862 tcg_debug_assert(dest != arg2); 1863 tcg_out_cmov(s, JCC_JB, rexw, dest, arg2); 1864 } 1865 } else { 1866 tcg_debug_assert(dest != arg2); 1867 tcg_out_modrm(s, OPC_BSF + rexw, dest, arg1); 1868 tcg_out_cmov(s, JCC_JE, rexw, dest, arg2); 1869 } 1870} 1871 1872static void tcg_out_clz(TCGContext *s, int rexw, TCGReg dest, TCGReg arg1, 1873 TCGArg arg2, bool const_a2) 1874{ 1875 if (have_lzcnt) { 1876 tcg_out_modrm(s, OPC_LZCNT + rexw, dest, arg1); 1877 if (const_a2) { 1878 tcg_debug_assert(arg2 == (rexw ? 64 : 32)); 1879 } else { 1880 tcg_debug_assert(dest != arg2); 1881 tcg_out_cmov(s, JCC_JB, rexw, dest, arg2); 1882 } 1883 } else { 1884 tcg_debug_assert(!const_a2); 1885 tcg_debug_assert(dest != arg1); 1886 tcg_debug_assert(dest != arg2); 1887 1888 /* Recall that the output of BSR is the index not the count. */ 1889 tcg_out_modrm(s, OPC_BSR + rexw, dest, arg1); 1890 tgen_arithi(s, ARITH_XOR + rexw, dest, rexw ? 63 : 31, 0); 1891 1892 /* Since we have destroyed the flags from BSR, we have to re-test. */ 1893 int jcc = tcg_out_cmp(s, TCG_COND_EQ, arg1, 0, 1, rexw); 1894 tcg_out_cmov(s, jcc, rexw, dest, arg2); 1895 } 1896} 1897 1898static void tcg_out_branch(TCGContext *s, int call, const tcg_insn_unit *dest) 1899{ 1900 intptr_t disp = tcg_pcrel_diff(s, dest) - 5; 1901 1902 if (disp == (int32_t)disp) { 1903 tcg_out_opc(s, call ? OPC_CALL_Jz : OPC_JMP_long, 0, 0, 0); 1904 tcg_out32(s, disp); 1905 } else { 1906 /* rip-relative addressing into the constant pool. 1907 This is 6 + 8 = 14 bytes, as compared to using an 1908 immediate load 10 + 6 = 16 bytes, plus we may 1909 be able to re-use the pool constant for more calls. */ 1910 tcg_out_opc(s, OPC_GRP5, 0, 0, 0); 1911 tcg_out8(s, (call ? EXT5_CALLN_Ev : EXT5_JMPN_Ev) << 3 | 5); 1912 new_pool_label(s, (uintptr_t)dest, R_386_PC32, s->code_ptr, -4); 1913 tcg_out32(s, 0); 1914 } 1915} 1916 1917static void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest, 1918 const TCGHelperInfo *info) 1919{ 1920 tcg_out_branch(s, 1, dest); 1921 1922#ifndef _WIN32 1923 if (TCG_TARGET_REG_BITS == 32 && info->out_kind == TCG_CALL_RET_BY_REF) { 1924 /* 1925 * The sysv i386 abi for struct return places a reference as the 1926 * first argument of the stack, and pops that argument with the 1927 * return statement. Since we want to retain the aligned stack 1928 * pointer for the callee, we do not want to actually push that 1929 * argument before the call but rely on the normal store to the 1930 * stack slot. But we do need to compensate for the pop in order 1931 * to reset our correct stack pointer value. 1932 * Pushing a garbage value back onto the stack is quickest. 1933 */ 1934 tcg_out_push(s, TCG_REG_EAX); 1935 } 1936#endif 1937} 1938 1939static void tcg_out_jmp(TCGContext *s, const tcg_insn_unit *dest) 1940{ 1941 tcg_out_branch(s, 0, dest); 1942} 1943 1944static void tcg_out_nopn(TCGContext *s, int n) 1945{ 1946 int i; 1947 /* Emit 1 or 2 operand size prefixes for the standard one byte nop, 1948 * "xchg %eax,%eax", forming "xchg %ax,%ax". All cores accept the 1949 * duplicate prefix, and all of the interesting recent cores can 1950 * decode and discard the duplicates in a single cycle. 1951 */ 1952 tcg_debug_assert(n >= 1); 1953 for (i = 1; i < n; ++i) { 1954 tcg_out8(s, 0x66); 1955 } 1956 tcg_out8(s, 0x90); 1957} 1958 1959typedef struct { 1960 TCGReg base; 1961 int index; 1962 int ofs; 1963 int seg; 1964 TCGAtomAlign aa; 1965} HostAddress; 1966 1967bool tcg_target_has_memory_bswap(MemOp memop) 1968{ 1969 TCGAtomAlign aa; 1970 1971 if (!have_movbe) { 1972 return false; 1973 } 1974 if ((memop & MO_SIZE) < MO_128) { 1975 return true; 1976 } 1977 1978 /* 1979 * Reject 16-byte memop with 16-byte atomicity, i.e. VMOVDQA, 1980 * but do allow a pair of 64-bit operations, i.e. MOVBEQ. 1981 */ 1982 aa = atom_and_align_for_opc(tcg_ctx, memop, MO_ATOM_IFALIGN, true); 1983 return aa.atom < MO_128; 1984} 1985 1986/* 1987 * Because i686 has no register parameters and because x86_64 has xchg 1988 * to handle addr/data register overlap, we have placed all input arguments 1989 * before we need might need a scratch reg. 1990 * 1991 * Even then, a scratch is only needed for l->raddr. Rather than expose 1992 * a general-purpose scratch when we don't actually know it's available, 1993 * use the ra_gen hook to load into RAX if needed. 1994 */ 1995#if TCG_TARGET_REG_BITS == 64 1996static TCGReg ldst_ra_gen(TCGContext *s, const TCGLabelQemuLdst *l, int arg) 1997{ 1998 if (arg < 0) { 1999 arg = TCG_REG_RAX; 2000 } 2001 tcg_out_movi(s, TCG_TYPE_PTR, arg, (uintptr_t)l->raddr); 2002 return arg; 2003} 2004static const TCGLdstHelperParam ldst_helper_param = { 2005 .ra_gen = ldst_ra_gen 2006}; 2007#else 2008static const TCGLdstHelperParam ldst_helper_param = { }; 2009#endif 2010 2011static void tcg_out_vec_to_pair(TCGContext *s, TCGType type, 2012 TCGReg l, TCGReg h, TCGReg v) 2013{ 2014 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2015 2016 /* vpmov{d,q} %v, %l */ 2017 tcg_out_vex_modrm(s, OPC_MOVD_EyVy + rexw, v, 0, l); 2018 /* vpextr{d,q} $1, %v, %h */ 2019 tcg_out_vex_modrm(s, OPC_PEXTRD + rexw, v, 0, h); 2020 tcg_out8(s, 1); 2021} 2022 2023static void tcg_out_pair_to_vec(TCGContext *s, TCGType type, 2024 TCGReg v, TCGReg l, TCGReg h) 2025{ 2026 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2027 2028 /* vmov{d,q} %l, %v */ 2029 tcg_out_vex_modrm(s, OPC_MOVD_VyEy + rexw, v, 0, l); 2030 /* vpinsr{d,q} $1, %h, %v, %v */ 2031 tcg_out_vex_modrm(s, OPC_PINSRD + rexw, v, v, h); 2032 tcg_out8(s, 1); 2033} 2034 2035/* 2036 * Generate code for the slow path for a load at the end of block 2037 */ 2038static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 2039{ 2040 MemOp opc = get_memop(l->oi); 2041 tcg_insn_unit **label_ptr = &l->label_ptr[0]; 2042 2043 /* resolve label address */ 2044 tcg_patch32(label_ptr[0], s->code_ptr - label_ptr[0] - 4); 2045 if (label_ptr[1]) { 2046 tcg_patch32(label_ptr[1], s->code_ptr - label_ptr[1] - 4); 2047 } 2048 2049 tcg_out_ld_helper_args(s, l, &ldst_helper_param); 2050 tcg_out_branch(s, 1, qemu_ld_helpers[opc & MO_SIZE]); 2051 tcg_out_ld_helper_ret(s, l, false, &ldst_helper_param); 2052 2053 tcg_out_jmp(s, l->raddr); 2054 return true; 2055} 2056 2057/* 2058 * Generate code for the slow path for a store at the end of block 2059 */ 2060static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 2061{ 2062 MemOp opc = get_memop(l->oi); 2063 tcg_insn_unit **label_ptr = &l->label_ptr[0]; 2064 2065 /* resolve label address */ 2066 tcg_patch32(label_ptr[0], s->code_ptr - label_ptr[0] - 4); 2067 if (label_ptr[1]) { 2068 tcg_patch32(label_ptr[1], s->code_ptr - label_ptr[1] - 4); 2069 } 2070 2071 tcg_out_st_helper_args(s, l, &ldst_helper_param); 2072 tcg_out_branch(s, 1, qemu_st_helpers[opc & MO_SIZE]); 2073 2074 tcg_out_jmp(s, l->raddr); 2075 return true; 2076} 2077 2078#ifdef CONFIG_USER_ONLY 2079static HostAddress x86_guest_base = { 2080 .index = -1 2081}; 2082 2083#if defined(__x86_64__) && defined(__linux__) 2084# include <asm/prctl.h> 2085# include <sys/prctl.h> 2086int arch_prctl(int code, unsigned long addr); 2087static inline int setup_guest_base_seg(void) 2088{ 2089 if (arch_prctl(ARCH_SET_GS, guest_base) == 0) { 2090 return P_GS; 2091 } 2092 return 0; 2093} 2094#define setup_guest_base_seg setup_guest_base_seg 2095#elif defined(__x86_64__) && \ 2096 (defined (__FreeBSD__) || defined (__FreeBSD_kernel__)) 2097# include <machine/sysarch.h> 2098static inline int setup_guest_base_seg(void) 2099{ 2100 if (sysarch(AMD64_SET_GSBASE, &guest_base) == 0) { 2101 return P_GS; 2102 } 2103 return 0; 2104} 2105#define setup_guest_base_seg setup_guest_base_seg 2106#endif 2107#else 2108# define x86_guest_base (*(HostAddress *)({ qemu_build_not_reached(); NULL; })) 2109#endif /* CONFIG_USER_ONLY */ 2110#ifndef setup_guest_base_seg 2111# define setup_guest_base_seg() 0 2112#endif 2113 2114#define MIN_TLB_MASK_TABLE_OFS INT_MIN 2115 2116/* 2117 * For softmmu, perform the TLB load and compare. 2118 * For useronly, perform any required alignment tests. 2119 * In both cases, return a TCGLabelQemuLdst structure if the slow path 2120 * is required and fill in @h with the host address for the fast path. 2121 */ 2122static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 2123 TCGReg addr, MemOpIdx oi, bool is_ld) 2124{ 2125 TCGLabelQemuLdst *ldst = NULL; 2126 MemOp opc = get_memop(oi); 2127 MemOp s_bits = opc & MO_SIZE; 2128 unsigned a_mask; 2129 2130 if (tcg_use_softmmu) { 2131 h->index = TCG_REG_L0; 2132 h->ofs = 0; 2133 h->seg = 0; 2134 } else { 2135 *h = x86_guest_base; 2136 } 2137 h->base = addr; 2138 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, s_bits == MO_128); 2139 a_mask = (1 << h->aa.align) - 1; 2140 2141 if (tcg_use_softmmu) { 2142 int cmp_ofs = is_ld ? offsetof(CPUTLBEntry, addr_read) 2143 : offsetof(CPUTLBEntry, addr_write); 2144 TCGType ttype = TCG_TYPE_I32; 2145 TCGType tlbtype = TCG_TYPE_I32; 2146 int trexw = 0, hrexw = 0, tlbrexw = 0; 2147 unsigned mem_index = get_mmuidx(oi); 2148 unsigned s_mask = (1 << s_bits) - 1; 2149 int fast_ofs = tlb_mask_table_ofs(s, mem_index); 2150 int tlb_mask; 2151 2152 ldst = new_ldst_label(s); 2153 ldst->is_ld = is_ld; 2154 ldst->oi = oi; 2155 ldst->addr_reg = addr; 2156 2157 if (TCG_TARGET_REG_BITS == 64) { 2158 ttype = s->addr_type; 2159 trexw = (ttype == TCG_TYPE_I32 ? 0 : P_REXW); 2160 if (TCG_TYPE_PTR == TCG_TYPE_I64) { 2161 hrexw = P_REXW; 2162 if (s->page_bits + s->tlb_dyn_max_bits > 32) { 2163 tlbtype = TCG_TYPE_I64; 2164 tlbrexw = P_REXW; 2165 } 2166 } 2167 } 2168 2169 tcg_out_mov(s, tlbtype, TCG_REG_L0, addr); 2170 tcg_out_shifti(s, SHIFT_SHR + tlbrexw, TCG_REG_L0, 2171 s->page_bits - CPU_TLB_ENTRY_BITS); 2172 2173 tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, TCG_REG_L0, TCG_AREG0, 2174 fast_ofs + offsetof(CPUTLBDescFast, mask)); 2175 2176 tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, TCG_REG_L0, TCG_AREG0, 2177 fast_ofs + offsetof(CPUTLBDescFast, table)); 2178 2179 /* 2180 * If the required alignment is at least as large as the access, 2181 * simply copy the address and mask. For lesser alignments, 2182 * check that we don't cross pages for the complete access. 2183 */ 2184 if (a_mask >= s_mask) { 2185 tcg_out_mov(s, ttype, TCG_REG_L1, addr); 2186 } else { 2187 tcg_out_modrm_offset(s, OPC_LEA + trexw, TCG_REG_L1, 2188 addr, s_mask - a_mask); 2189 } 2190 tlb_mask = s->page_mask | a_mask; 2191 tgen_arithi(s, ARITH_AND + trexw, TCG_REG_L1, tlb_mask, 0); 2192 2193 /* cmp 0(TCG_REG_L0), TCG_REG_L1 */ 2194 tcg_out_modrm_offset(s, OPC_CMP_GvEv + trexw, 2195 TCG_REG_L1, TCG_REG_L0, cmp_ofs); 2196 2197 /* jne slow_path */ 2198 tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); 2199 ldst->label_ptr[0] = s->code_ptr; 2200 s->code_ptr += 4; 2201 2202 /* TLB Hit. */ 2203 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_L0, TCG_REG_L0, 2204 offsetof(CPUTLBEntry, addend)); 2205 } else if (a_mask) { 2206 int jcc; 2207 2208 ldst = new_ldst_label(s); 2209 ldst->is_ld = is_ld; 2210 ldst->oi = oi; 2211 ldst->addr_reg = addr; 2212 2213 /* jne slow_path */ 2214 jcc = tcg_out_cmp(s, TCG_COND_TSTNE, addr, a_mask, true, false); 2215 tcg_out_opc(s, OPC_JCC_long + jcc, 0, 0, 0); 2216 ldst->label_ptr[0] = s->code_ptr; 2217 s->code_ptr += 4; 2218 } 2219 2220 return ldst; 2221} 2222 2223static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, 2224 HostAddress h, TCGType type, MemOp memop) 2225{ 2226 bool use_movbe = false; 2227 int rexw = (type == TCG_TYPE_I32 ? 0 : P_REXW); 2228 int movop = OPC_MOVL_GvEv; 2229 2230 /* Do big-endian loads with movbe. */ 2231 if (memop & MO_BSWAP) { 2232 tcg_debug_assert(have_movbe); 2233 use_movbe = true; 2234 movop = OPC_MOVBE_GyMy; 2235 } 2236 2237 switch (memop & MO_SSIZE) { 2238 case MO_UB: 2239 tcg_out_modrm_sib_offset(s, OPC_MOVZBL + h.seg, datalo, 2240 h.base, h.index, 0, h.ofs); 2241 break; 2242 case MO_SB: 2243 tcg_out_modrm_sib_offset(s, OPC_MOVSBL + rexw + h.seg, datalo, 2244 h.base, h.index, 0, h.ofs); 2245 break; 2246 case MO_UW: 2247 if (use_movbe) { 2248 /* There is no extending movbe; only low 16-bits are modified. */ 2249 if (datalo != h.base && datalo != h.index) { 2250 /* XOR breaks dependency chains. */ 2251 tgen_arithr(s, ARITH_XOR, datalo, datalo); 2252 tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + h.seg, 2253 datalo, h.base, h.index, 0, h.ofs); 2254 } else { 2255 tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + h.seg, 2256 datalo, h.base, h.index, 0, h.ofs); 2257 tcg_out_ext16u(s, datalo, datalo); 2258 } 2259 } else { 2260 tcg_out_modrm_sib_offset(s, OPC_MOVZWL + h.seg, datalo, 2261 h.base, h.index, 0, h.ofs); 2262 } 2263 break; 2264 case MO_SW: 2265 if (use_movbe) { 2266 tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + h.seg, 2267 datalo, h.base, h.index, 0, h.ofs); 2268 tcg_out_ext16s(s, type, datalo, datalo); 2269 } else { 2270 tcg_out_modrm_sib_offset(s, OPC_MOVSWL + rexw + h.seg, 2271 datalo, h.base, h.index, 0, h.ofs); 2272 } 2273 break; 2274 case MO_UL: 2275 tcg_out_modrm_sib_offset(s, movop + h.seg, datalo, 2276 h.base, h.index, 0, h.ofs); 2277 break; 2278#if TCG_TARGET_REG_BITS == 64 2279 case MO_SL: 2280 if (use_movbe) { 2281 tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + h.seg, datalo, 2282 h.base, h.index, 0, h.ofs); 2283 tcg_out_ext32s(s, datalo, datalo); 2284 } else { 2285 tcg_out_modrm_sib_offset(s, OPC_MOVSLQ + h.seg, datalo, 2286 h.base, h.index, 0, h.ofs); 2287 } 2288 break; 2289#endif 2290 case MO_UQ: 2291 if (TCG_TARGET_REG_BITS == 64) { 2292 tcg_out_modrm_sib_offset(s, movop + P_REXW + h.seg, datalo, 2293 h.base, h.index, 0, h.ofs); 2294 break; 2295 } 2296 if (use_movbe) { 2297 TCGReg t = datalo; 2298 datalo = datahi; 2299 datahi = t; 2300 } 2301 if (h.base == datalo || h.index == datalo) { 2302 tcg_out_modrm_sib_offset(s, OPC_LEA, datahi, 2303 h.base, h.index, 0, h.ofs); 2304 tcg_out_modrm_offset(s, movop + h.seg, datalo, datahi, 0); 2305 tcg_out_modrm_offset(s, movop + h.seg, datahi, datahi, 4); 2306 } else { 2307 tcg_out_modrm_sib_offset(s, movop + h.seg, datalo, 2308 h.base, h.index, 0, h.ofs); 2309 tcg_out_modrm_sib_offset(s, movop + h.seg, datahi, 2310 h.base, h.index, 0, h.ofs + 4); 2311 } 2312 break; 2313 2314 case MO_128: 2315 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 2316 2317 /* 2318 * Without 16-byte atomicity, use integer regs. 2319 * That is where we want the data, and it allows bswaps. 2320 */ 2321 if (h.aa.atom < MO_128) { 2322 if (use_movbe) { 2323 TCGReg t = datalo; 2324 datalo = datahi; 2325 datahi = t; 2326 } 2327 if (h.base == datalo || h.index == datalo) { 2328 tcg_out_modrm_sib_offset(s, OPC_LEA + P_REXW, datahi, 2329 h.base, h.index, 0, h.ofs); 2330 tcg_out_modrm_offset(s, movop + P_REXW + h.seg, 2331 datalo, datahi, 0); 2332 tcg_out_modrm_offset(s, movop + P_REXW + h.seg, 2333 datahi, datahi, 8); 2334 } else { 2335 tcg_out_modrm_sib_offset(s, movop + P_REXW + h.seg, datalo, 2336 h.base, h.index, 0, h.ofs); 2337 tcg_out_modrm_sib_offset(s, movop + P_REXW + h.seg, datahi, 2338 h.base, h.index, 0, h.ofs + 8); 2339 } 2340 break; 2341 } 2342 2343 /* 2344 * With 16-byte atomicity, a vector load is required. 2345 * If we already have 16-byte alignment, then VMOVDQA always works. 2346 * Else if VMOVDQU has atomicity with dynamic alignment, use that. 2347 * Else use we require a runtime test for alignment for VMOVDQA; 2348 * use VMOVDQU on the unaligned nonatomic path for simplicity. 2349 */ 2350 if (h.aa.align >= MO_128) { 2351 tcg_out_vex_modrm_sib_offset(s, OPC_MOVDQA_VxWx + h.seg, 2352 TCG_TMP_VEC, 0, 2353 h.base, h.index, 0, h.ofs); 2354 } else if (cpuinfo & CPUINFO_ATOMIC_VMOVDQU) { 2355 tcg_out_vex_modrm_sib_offset(s, OPC_MOVDQU_VxWx + h.seg, 2356 TCG_TMP_VEC, 0, 2357 h.base, h.index, 0, h.ofs); 2358 } else { 2359 TCGLabel *l1 = gen_new_label(); 2360 TCGLabel *l2 = gen_new_label(); 2361 int jcc; 2362 2363 jcc = tcg_out_cmp(s, TCG_COND_TSTNE, h.base, 15, true, false); 2364 tcg_out_jxx(s, jcc, l1, true); 2365 2366 tcg_out_vex_modrm_sib_offset(s, OPC_MOVDQA_VxWx + h.seg, 2367 TCG_TMP_VEC, 0, 2368 h.base, h.index, 0, h.ofs); 2369 tcg_out_jxx(s, JCC_JMP, l2, true); 2370 2371 tcg_out_label(s, l1); 2372 tcg_out_vex_modrm_sib_offset(s, OPC_MOVDQU_VxWx + h.seg, 2373 TCG_TMP_VEC, 0, 2374 h.base, h.index, 0, h.ofs); 2375 tcg_out_label(s, l2); 2376 } 2377 tcg_out_vec_to_pair(s, TCG_TYPE_I64, datalo, datahi, TCG_TMP_VEC); 2378 break; 2379 2380 default: 2381 g_assert_not_reached(); 2382 } 2383} 2384 2385static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, 2386 TCGReg addr, MemOpIdx oi, TCGType data_type) 2387{ 2388 TCGLabelQemuLdst *ldst; 2389 HostAddress h; 2390 2391 ldst = prepare_host_addr(s, &h, addr, oi, true); 2392 tcg_out_qemu_ld_direct(s, datalo, datahi, h, data_type, get_memop(oi)); 2393 2394 if (ldst) { 2395 ldst->type = data_type; 2396 ldst->datalo_reg = datalo; 2397 ldst->datahi_reg = datahi; 2398 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 2399 } 2400} 2401 2402static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, 2403 HostAddress h, MemOp memop) 2404{ 2405 bool use_movbe = false; 2406 int movop = OPC_MOVL_EvGv; 2407 2408 /* 2409 * Do big-endian stores with movbe or system-mode. 2410 * User-only without movbe will have its swapping done generically. 2411 */ 2412 if (memop & MO_BSWAP) { 2413 tcg_debug_assert(have_movbe); 2414 use_movbe = true; 2415 movop = OPC_MOVBE_MyGy; 2416 } 2417 2418 switch (memop & MO_SIZE) { 2419 case MO_8: 2420 /* This is handled with constraints on INDEX_op_qemu_st8_i32. */ 2421 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || datalo < 4); 2422 tcg_out_modrm_sib_offset(s, OPC_MOVB_EvGv + P_REXB_R + h.seg, 2423 datalo, h.base, h.index, 0, h.ofs); 2424 break; 2425 case MO_16: 2426 tcg_out_modrm_sib_offset(s, movop + P_DATA16 + h.seg, datalo, 2427 h.base, h.index, 0, h.ofs); 2428 break; 2429 case MO_32: 2430 tcg_out_modrm_sib_offset(s, movop + h.seg, datalo, 2431 h.base, h.index, 0, h.ofs); 2432 break; 2433 case MO_64: 2434 if (TCG_TARGET_REG_BITS == 64) { 2435 tcg_out_modrm_sib_offset(s, movop + P_REXW + h.seg, datalo, 2436 h.base, h.index, 0, h.ofs); 2437 } else { 2438 if (use_movbe) { 2439 TCGReg t = datalo; 2440 datalo = datahi; 2441 datahi = t; 2442 } 2443 tcg_out_modrm_sib_offset(s, movop + h.seg, datalo, 2444 h.base, h.index, 0, h.ofs); 2445 tcg_out_modrm_sib_offset(s, movop + h.seg, datahi, 2446 h.base, h.index, 0, h.ofs + 4); 2447 } 2448 break; 2449 2450 case MO_128: 2451 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 2452 2453 /* 2454 * Without 16-byte atomicity, use integer regs. 2455 * That is where we have the data, and it allows bswaps. 2456 */ 2457 if (h.aa.atom < MO_128) { 2458 if (use_movbe) { 2459 TCGReg t = datalo; 2460 datalo = datahi; 2461 datahi = t; 2462 } 2463 tcg_out_modrm_sib_offset(s, movop + P_REXW + h.seg, datalo, 2464 h.base, h.index, 0, h.ofs); 2465 tcg_out_modrm_sib_offset(s, movop + P_REXW + h.seg, datahi, 2466 h.base, h.index, 0, h.ofs + 8); 2467 break; 2468 } 2469 2470 /* 2471 * With 16-byte atomicity, a vector store is required. 2472 * If we already have 16-byte alignment, then VMOVDQA always works. 2473 * Else if VMOVDQU has atomicity with dynamic alignment, use that. 2474 * Else use we require a runtime test for alignment for VMOVDQA; 2475 * use VMOVDQU on the unaligned nonatomic path for simplicity. 2476 */ 2477 tcg_out_pair_to_vec(s, TCG_TYPE_I64, TCG_TMP_VEC, datalo, datahi); 2478 if (h.aa.align >= MO_128) { 2479 tcg_out_vex_modrm_sib_offset(s, OPC_MOVDQA_WxVx + h.seg, 2480 TCG_TMP_VEC, 0, 2481 h.base, h.index, 0, h.ofs); 2482 } else if (cpuinfo & CPUINFO_ATOMIC_VMOVDQU) { 2483 tcg_out_vex_modrm_sib_offset(s, OPC_MOVDQU_WxVx + h.seg, 2484 TCG_TMP_VEC, 0, 2485 h.base, h.index, 0, h.ofs); 2486 } else { 2487 TCGLabel *l1 = gen_new_label(); 2488 TCGLabel *l2 = gen_new_label(); 2489 int jcc; 2490 2491 jcc = tcg_out_cmp(s, TCG_COND_TSTNE, h.base, 15, true, false); 2492 tcg_out_jxx(s, jcc, l1, true); 2493 2494 tcg_out_vex_modrm_sib_offset(s, OPC_MOVDQA_WxVx + h.seg, 2495 TCG_TMP_VEC, 0, 2496 h.base, h.index, 0, h.ofs); 2497 tcg_out_jxx(s, JCC_JMP, l2, true); 2498 2499 tcg_out_label(s, l1); 2500 tcg_out_vex_modrm_sib_offset(s, OPC_MOVDQU_WxVx + h.seg, 2501 TCG_TMP_VEC, 0, 2502 h.base, h.index, 0, h.ofs); 2503 tcg_out_label(s, l2); 2504 } 2505 break; 2506 2507 default: 2508 g_assert_not_reached(); 2509 } 2510} 2511 2512static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, 2513 TCGReg addr, MemOpIdx oi, TCGType data_type) 2514{ 2515 TCGLabelQemuLdst *ldst; 2516 HostAddress h; 2517 2518 ldst = prepare_host_addr(s, &h, addr, oi, false); 2519 tcg_out_qemu_st_direct(s, datalo, datahi, h, get_memop(oi)); 2520 2521 if (ldst) { 2522 ldst->type = data_type; 2523 ldst->datalo_reg = datalo; 2524 ldst->datahi_reg = datahi; 2525 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 2526 } 2527} 2528 2529static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 2530{ 2531 /* Reuse the zeroing that exists for goto_ptr. */ 2532 if (a0 == 0) { 2533 tcg_out_jmp(s, tcg_code_gen_epilogue); 2534 } else { 2535 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_EAX, a0); 2536 tcg_out_jmp(s, tb_ret_addr); 2537 } 2538} 2539 2540static void tcg_out_goto_tb(TCGContext *s, int which) 2541{ 2542 /* 2543 * Jump displacement must be aligned for atomic patching; 2544 * see if we need to add extra nops before jump 2545 */ 2546 int gap = QEMU_ALIGN_PTR_UP(s->code_ptr + 1, 4) - s->code_ptr; 2547 if (gap != 1) { 2548 tcg_out_nopn(s, gap - 1); 2549 } 2550 tcg_out8(s, OPC_JMP_long); /* jmp im */ 2551 set_jmp_insn_offset(s, which); 2552 tcg_out32(s, 0); 2553 set_jmp_reset_offset(s, which); 2554} 2555 2556void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 2557 uintptr_t jmp_rx, uintptr_t jmp_rw) 2558{ 2559 /* patch the branch destination */ 2560 uintptr_t addr = tb->jmp_target_addr[n]; 2561 qatomic_set((int32_t *)jmp_rw, addr - (jmp_rx + 4)); 2562 /* no need to flush icache explicitly */ 2563} 2564 2565 2566static void tgen_add(TCGContext *s, TCGType type, 2567 TCGReg a0, TCGReg a1, TCGReg a2) 2568{ 2569 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2570 2571 if (a0 == a1) { 2572 tgen_arithr(s, ARITH_ADD + rexw, a0, a2); 2573 } else if (a0 == a2) { 2574 tgen_arithr(s, ARITH_ADD + rexw, a0, a1); 2575 } else { 2576 tcg_out_modrm_sib_offset(s, OPC_LEA + rexw, a0, a1, a2, 0, 0); 2577 } 2578} 2579 2580static void tgen_addi(TCGContext *s, TCGType type, 2581 TCGReg a0, TCGReg a1, tcg_target_long a2) 2582{ 2583 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2584 2585 if (a0 == a1) { 2586 tgen_arithi(s, ARITH_ADD + rexw, a0, a2, false); 2587 } else { 2588 tcg_out_modrm_sib_offset(s, OPC_LEA + rexw, a0, a1, -1, 0, a2); 2589 } 2590} 2591 2592static const TCGOutOpBinary outop_add = { 2593 .base.static_constraint = C_O1_I2(r, r, re), 2594 .out_rrr = tgen_add, 2595 .out_rri = tgen_addi, 2596}; 2597 2598static void tgen_and(TCGContext *s, TCGType type, 2599 TCGReg a0, TCGReg a1, TCGReg a2) 2600{ 2601 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2602 tgen_arithr(s, ARITH_AND + rexw, a0, a2); 2603} 2604 2605static void tgen_andi(TCGContext *s, TCGType type, 2606 TCGReg a0, TCGReg a1, tcg_target_long a2) 2607{ 2608 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2609 tgen_arithi(s, ARITH_AND + rexw, a0, a2, false); 2610} 2611 2612static const TCGOutOpBinary outop_and = { 2613 .base.static_constraint = C_O1_I2(r, 0, reZ), 2614 .out_rrr = tgen_and, 2615 .out_rri = tgen_andi, 2616}; 2617 2618static void tgen_andc(TCGContext *s, TCGType type, 2619 TCGReg a0, TCGReg a1, TCGReg a2) 2620{ 2621 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2622 tcg_out_vex_modrm(s, OPC_ANDN + rexw, a0, a2, a1); 2623} 2624 2625static TCGConstraintSetIndex cset_andc(TCGType type, unsigned flags) 2626{ 2627 return have_bmi1 ? C_O1_I2(r, r, r) : C_NotImplemented; 2628} 2629 2630static const TCGOutOpBinary outop_andc = { 2631 .base.static_constraint = C_Dynamic, 2632 .base.dynamic_constraint = cset_andc, 2633 .out_rrr = tgen_andc, 2634}; 2635 2636static const TCGOutOpBinary outop_divs = { 2637 .base.static_constraint = C_NotImplemented, 2638}; 2639 2640static void tgen_divs2(TCGContext *s, TCGType type, 2641 TCGReg a0, TCGReg a1, TCGReg a4) 2642{ 2643 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2644 tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_IDIV, a4); 2645} 2646 2647static const TCGOutOpDivRem outop_divs2 = { 2648 .base.static_constraint = C_O2_I3(a, d, 0, 1, r), 2649 .out_rr01r = tgen_divs2, 2650}; 2651 2652static const TCGOutOpBinary outop_divu = { 2653 .base.static_constraint = C_NotImplemented, 2654}; 2655 2656static void tgen_divu2(TCGContext *s, TCGType type, 2657 TCGReg a0, TCGReg a1, TCGReg a4) 2658{ 2659 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2660 tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_DIV, a4); 2661} 2662 2663static const TCGOutOpDivRem outop_divu2 = { 2664 .base.static_constraint = C_O2_I3(a, d, 0, 1, r), 2665 .out_rr01r = tgen_divu2, 2666}; 2667 2668static const TCGOutOpBinary outop_eqv = { 2669 .base.static_constraint = C_NotImplemented, 2670}; 2671 2672static void tgen_mul(TCGContext *s, TCGType type, 2673 TCGReg a0, TCGReg a1, TCGReg a2) 2674{ 2675 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2676 tcg_out_modrm(s, OPC_IMUL_GvEv + rexw, a0, a2); 2677} 2678 2679static void tgen_muli(TCGContext *s, TCGType type, 2680 TCGReg a0, TCGReg a1, tcg_target_long a2) 2681{ 2682 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2683 2684 if (a2 == (int8_t)a2) { 2685 tcg_out_modrm(s, OPC_IMUL_GvEvIb + rexw, a0, a0); 2686 tcg_out8(s, a2); 2687 } else { 2688 tcg_out_modrm(s, OPC_IMUL_GvEvIz + rexw, a0, a0); 2689 tcg_out32(s, a2); 2690 } 2691} 2692 2693static const TCGOutOpBinary outop_mul = { 2694 .base.static_constraint = C_O1_I2(r, 0, re), 2695 .out_rrr = tgen_mul, 2696 .out_rri = tgen_muli, 2697}; 2698 2699static const TCGOutOpBinary outop_mulsh = { 2700 .base.static_constraint = C_NotImplemented, 2701}; 2702 2703static const TCGOutOpBinary outop_muluh = { 2704 .base.static_constraint = C_NotImplemented, 2705}; 2706 2707static const TCGOutOpBinary outop_nand = { 2708 .base.static_constraint = C_NotImplemented, 2709}; 2710 2711static const TCGOutOpBinary outop_nor = { 2712 .base.static_constraint = C_NotImplemented, 2713}; 2714 2715static void tgen_or(TCGContext *s, TCGType type, 2716 TCGReg a0, TCGReg a1, TCGReg a2) 2717{ 2718 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2719 tgen_arithr(s, ARITH_OR + rexw, a0, a2); 2720} 2721 2722static void tgen_ori(TCGContext *s, TCGType type, 2723 TCGReg a0, TCGReg a1, tcg_target_long a2) 2724{ 2725 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2726 tgen_arithi(s, ARITH_OR + rexw, a0, a2, false); 2727} 2728 2729static const TCGOutOpBinary outop_or = { 2730 .base.static_constraint = C_O1_I2(r, 0, re), 2731 .out_rrr = tgen_or, 2732 .out_rri = tgen_ori, 2733}; 2734 2735static const TCGOutOpBinary outop_orc = { 2736 .base.static_constraint = C_NotImplemented, 2737}; 2738 2739static void tgen_sub(TCGContext *s, TCGType type, 2740 TCGReg a0, TCGReg a1, TCGReg a2) 2741{ 2742 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2743 tgen_arithr(s, ARITH_SUB + rexw, a0, a2); 2744} 2745 2746static const TCGOutOpSubtract outop_sub = { 2747 .base.static_constraint = C_O1_I2(r, 0, r), 2748 .out_rrr = tgen_sub, 2749}; 2750 2751static void tgen_xor(TCGContext *s, TCGType type, 2752 TCGReg a0, TCGReg a1, TCGReg a2) 2753{ 2754 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2755 tgen_arithr(s, ARITH_XOR + rexw, a0, a2); 2756} 2757 2758static void tgen_xori(TCGContext *s, TCGType type, 2759 TCGReg a0, TCGReg a1, tcg_target_long a2) 2760{ 2761 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2762 tgen_arithi(s, ARITH_XOR + rexw, a0, a2, false); 2763} 2764 2765static const TCGOutOpBinary outop_xor = { 2766 .base.static_constraint = C_O1_I2(r, 0, re), 2767 .out_rrr = tgen_xor, 2768 .out_rri = tgen_xori, 2769}; 2770 2771static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2772{ 2773 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2774 tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NEG, a0); 2775} 2776 2777static const TCGOutOpUnary outop_neg = { 2778 .base.static_constraint = C_O1_I1(r, 0), 2779 .out_rr = tgen_neg, 2780}; 2781 2782static void tgen_not(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2783{ 2784 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2785 tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NOT, a0); 2786} 2787 2788static const TCGOutOpUnary outop_not = { 2789 .base.static_constraint = C_O1_I1(r, 0), 2790 .out_rr = tgen_not, 2791}; 2792 2793 2794static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, 2795 const TCGArg args[TCG_MAX_OP_ARGS], 2796 const int const_args[TCG_MAX_OP_ARGS]) 2797{ 2798 TCGArg a0, a1, a2; 2799 int c, const_a2, vexop, rexw; 2800 2801#if TCG_TARGET_REG_BITS == 64 2802# define OP_32_64(x) \ 2803 case glue(glue(INDEX_op_, x), _i64): \ 2804 case glue(glue(INDEX_op_, x), _i32) 2805#else 2806# define OP_32_64(x) \ 2807 case glue(glue(INDEX_op_, x), _i32) 2808#endif 2809 2810 /* Hoist the loads of the most common arguments. */ 2811 a0 = args[0]; 2812 a1 = args[1]; 2813 a2 = args[2]; 2814 const_a2 = const_args[2]; 2815 rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2816 2817 switch (opc) { 2818 case INDEX_op_goto_ptr: 2819 /* jmp to the given host address (could be epilogue) */ 2820 tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, a0); 2821 break; 2822 case INDEX_op_br: 2823 tcg_out_jxx(s, JCC_JMP, arg_label(a0), 0); 2824 break; 2825 OP_32_64(ld8u): 2826 /* Note that we can ignore REXW for the zero-extend to 64-bit. */ 2827 tcg_out_modrm_offset(s, OPC_MOVZBL, a0, a1, a2); 2828 break; 2829 OP_32_64(ld8s): 2830 tcg_out_modrm_offset(s, OPC_MOVSBL + rexw, a0, a1, a2); 2831 break; 2832 OP_32_64(ld16u): 2833 /* Note that we can ignore REXW for the zero-extend to 64-bit. */ 2834 tcg_out_modrm_offset(s, OPC_MOVZWL, a0, a1, a2); 2835 break; 2836 OP_32_64(ld16s): 2837 tcg_out_modrm_offset(s, OPC_MOVSWL + rexw, a0, a1, a2); 2838 break; 2839#if TCG_TARGET_REG_BITS == 64 2840 case INDEX_op_ld32u_i64: 2841#endif 2842 case INDEX_op_ld_i32: 2843 tcg_out_ld(s, TCG_TYPE_I32, a0, a1, a2); 2844 break; 2845 2846 OP_32_64(st8): 2847 if (const_args[0]) { 2848 tcg_out_modrm_offset(s, OPC_MOVB_EvIz, 0, a1, a2); 2849 tcg_out8(s, a0); 2850 } else { 2851 tcg_out_modrm_offset(s, OPC_MOVB_EvGv | P_REXB_R, a0, a1, a2); 2852 } 2853 break; 2854 OP_32_64(st16): 2855 if (const_args[0]) { 2856 tcg_out_modrm_offset(s, OPC_MOVL_EvIz | P_DATA16, 0, a1, a2); 2857 tcg_out16(s, a0); 2858 } else { 2859 tcg_out_modrm_offset(s, OPC_MOVL_EvGv | P_DATA16, a0, a1, a2); 2860 } 2861 break; 2862#if TCG_TARGET_REG_BITS == 64 2863 case INDEX_op_st32_i64: 2864#endif 2865 case INDEX_op_st_i32: 2866 if (const_args[0]) { 2867 tcg_out_modrm_offset(s, OPC_MOVL_EvIz, 0, a1, a2); 2868 tcg_out32(s, a0); 2869 } else { 2870 tcg_out_st(s, TCG_TYPE_I32, a0, a1, a2); 2871 } 2872 break; 2873 2874 OP_32_64(shl): 2875 /* For small constant 3-operand shift, use LEA. */ 2876 if (const_a2 && a0 != a1 && (a2 - 1) < 3) { 2877 if (a2 - 1 == 0) { 2878 /* shl $1,a1,a0 -> lea (a1,a1),a0 */ 2879 tcg_out_modrm_sib_offset(s, OPC_LEA + rexw, a0, a1, a1, 0, 0); 2880 } else { 2881 /* shl $n,a1,a0 -> lea 0(,a1,n),a0 */ 2882 tcg_out_modrm_sib_offset(s, OPC_LEA + rexw, a0, -1, a1, a2, 0); 2883 } 2884 break; 2885 } 2886 c = SHIFT_SHL; 2887 vexop = OPC_SHLX; 2888 goto gen_shift_maybe_vex; 2889 OP_32_64(shr): 2890 c = SHIFT_SHR; 2891 vexop = OPC_SHRX; 2892 goto gen_shift_maybe_vex; 2893 OP_32_64(sar): 2894 c = SHIFT_SAR; 2895 vexop = OPC_SARX; 2896 goto gen_shift_maybe_vex; 2897 OP_32_64(rotl): 2898 c = SHIFT_ROL; 2899 goto gen_shift; 2900 OP_32_64(rotr): 2901 c = SHIFT_ROR; 2902 goto gen_shift; 2903 gen_shift_maybe_vex: 2904 if (have_bmi2) { 2905 if (!const_a2) { 2906 tcg_out_vex_modrm(s, vexop + rexw, a0, a2, a1); 2907 break; 2908 } 2909 tcg_out_mov(s, rexw ? TCG_TYPE_I64 : TCG_TYPE_I32, a0, a1); 2910 } 2911 /* FALLTHRU */ 2912 gen_shift: 2913 if (const_a2) { 2914 tcg_out_shifti(s, c + rexw, a0, a2); 2915 } else { 2916 tcg_out_modrm(s, OPC_SHIFT_cl + rexw, c, a0); 2917 } 2918 break; 2919 2920 OP_32_64(ctz): 2921 tcg_out_ctz(s, rexw, args[0], args[1], args[2], const_args[2]); 2922 break; 2923 OP_32_64(clz): 2924 tcg_out_clz(s, rexw, args[0], args[1], args[2], const_args[2]); 2925 break; 2926 OP_32_64(ctpop): 2927 tcg_out_modrm(s, OPC_POPCNT + rexw, a0, a1); 2928 break; 2929 2930 OP_32_64(brcond): 2931 tcg_out_brcond(s, rexw, a2, a0, a1, const_args[1], 2932 arg_label(args[3]), 0); 2933 break; 2934 OP_32_64(setcond): 2935 tcg_out_setcond(s, rexw, args[3], a0, a1, a2, const_a2, false); 2936 break; 2937 OP_32_64(negsetcond): 2938 tcg_out_setcond(s, rexw, args[3], a0, a1, a2, const_a2, true); 2939 break; 2940 OP_32_64(movcond): 2941 tcg_out_movcond(s, rexw, args[5], a0, a1, a2, const_a2, args[3]); 2942 break; 2943 2944 OP_32_64(bswap16): 2945 if (a2 & TCG_BSWAP_OS) { 2946 /* Output must be sign-extended. */ 2947 if (rexw) { 2948 tcg_out_bswap64(s, a0); 2949 tcg_out_shifti(s, SHIFT_SAR + rexw, a0, 48); 2950 } else { 2951 tcg_out_bswap32(s, a0); 2952 tcg_out_shifti(s, SHIFT_SAR, a0, 16); 2953 } 2954 } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 2955 /* Output must be zero-extended, but input isn't. */ 2956 tcg_out_bswap32(s, a0); 2957 tcg_out_shifti(s, SHIFT_SHR, a0, 16); 2958 } else { 2959 tcg_out_rolw_8(s, a0); 2960 } 2961 break; 2962 OP_32_64(bswap32): 2963 tcg_out_bswap32(s, a0); 2964 if (rexw && (a2 & TCG_BSWAP_OS)) { 2965 tcg_out_ext32s(s, a0, a0); 2966 } 2967 break; 2968 2969 case INDEX_op_qemu_ld_i32: 2970 tcg_out_qemu_ld(s, a0, -1, a1, a2, TCG_TYPE_I32); 2971 break; 2972 case INDEX_op_qemu_ld_i64: 2973 if (TCG_TARGET_REG_BITS == 64) { 2974 tcg_out_qemu_ld(s, a0, -1, a1, a2, TCG_TYPE_I64); 2975 } else { 2976 tcg_out_qemu_ld(s, a0, a1, a2, args[3], TCG_TYPE_I64); 2977 } 2978 break; 2979 case INDEX_op_qemu_ld_i128: 2980 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 2981 tcg_out_qemu_ld(s, a0, a1, a2, args[3], TCG_TYPE_I128); 2982 break; 2983 2984 case INDEX_op_qemu_st_i32: 2985 case INDEX_op_qemu_st8_i32: 2986 tcg_out_qemu_st(s, a0, -1, a1, a2, TCG_TYPE_I32); 2987 break; 2988 case INDEX_op_qemu_st_i64: 2989 if (TCG_TARGET_REG_BITS == 64) { 2990 tcg_out_qemu_st(s, a0, -1, a1, a2, TCG_TYPE_I64); 2991 } else { 2992 tcg_out_qemu_st(s, a0, a1, a2, args[3], TCG_TYPE_I64); 2993 } 2994 break; 2995 case INDEX_op_qemu_st_i128: 2996 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 2997 tcg_out_qemu_st(s, a0, a1, a2, args[3], TCG_TYPE_I128); 2998 break; 2999 3000 OP_32_64(mulu2): 3001 tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_MUL, args[3]); 3002 break; 3003 OP_32_64(muls2): 3004 tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_IMUL, args[3]); 3005 break; 3006 OP_32_64(add2): 3007 if (const_args[4]) { 3008 tgen_arithi(s, ARITH_ADD + rexw, a0, args[4], 1); 3009 } else { 3010 tgen_arithr(s, ARITH_ADD + rexw, a0, args[4]); 3011 } 3012 if (const_args[5]) { 3013 tgen_arithi(s, ARITH_ADC + rexw, a1, args[5], 1); 3014 } else { 3015 tgen_arithr(s, ARITH_ADC + rexw, a1, args[5]); 3016 } 3017 break; 3018 OP_32_64(sub2): 3019 if (const_args[4]) { 3020 tgen_arithi(s, ARITH_SUB + rexw, a0, args[4], 1); 3021 } else { 3022 tgen_arithr(s, ARITH_SUB + rexw, a0, args[4]); 3023 } 3024 if (const_args[5]) { 3025 tgen_arithi(s, ARITH_SBB + rexw, a1, args[5], 1); 3026 } else { 3027 tgen_arithr(s, ARITH_SBB + rexw, a1, args[5]); 3028 } 3029 break; 3030 3031#if TCG_TARGET_REG_BITS == 32 3032 case INDEX_op_brcond2_i32: 3033 tcg_out_brcond2(s, args, const_args, 0); 3034 break; 3035 case INDEX_op_setcond2_i32: 3036 tcg_out_setcond2(s, args, const_args); 3037 break; 3038#else /* TCG_TARGET_REG_BITS == 64 */ 3039 case INDEX_op_ld32s_i64: 3040 tcg_out_modrm_offset(s, OPC_MOVSLQ, a0, a1, a2); 3041 break; 3042 case INDEX_op_ld_i64: 3043 tcg_out_ld(s, TCG_TYPE_I64, a0, a1, a2); 3044 break; 3045 case INDEX_op_st_i64: 3046 if (const_args[0]) { 3047 tcg_out_modrm_offset(s, OPC_MOVL_EvIz | P_REXW, 0, a1, a2); 3048 tcg_out32(s, a0); 3049 } else { 3050 tcg_out_st(s, TCG_TYPE_I64, a0, a1, a2); 3051 } 3052 break; 3053 3054 case INDEX_op_bswap64_i64: 3055 tcg_out_bswap64(s, a0); 3056 break; 3057 case INDEX_op_extrh_i64_i32: 3058 tcg_out_shifti(s, SHIFT_SHR + P_REXW, a0, 32); 3059 break; 3060#endif 3061 3062 OP_32_64(deposit): 3063 if (args[3] == 0 && args[4] == 8) { 3064 /* load bits 0..7 */ 3065 if (const_a2) { 3066 tcg_out_opc(s, OPC_MOVB_Ib | P_REXB_RM | LOWREGMASK(a0), 3067 0, a0, 0); 3068 tcg_out8(s, a2); 3069 } else { 3070 tcg_out_modrm(s, OPC_MOVB_EvGv | P_REXB_R | P_REXB_RM, a2, a0); 3071 } 3072 } else if (TCG_TARGET_REG_BITS == 32 && args[3] == 8 && args[4] == 8) { 3073 /* load bits 8..15 */ 3074 if (const_a2) { 3075 tcg_out8(s, OPC_MOVB_Ib + a0 + 4); 3076 tcg_out8(s, a2); 3077 } else { 3078 tcg_out_modrm(s, OPC_MOVB_EvGv, a2, a0 + 4); 3079 } 3080 } else if (args[3] == 0 && args[4] == 16) { 3081 /* load bits 0..15 */ 3082 if (const_a2) { 3083 tcg_out_opc(s, OPC_MOVL_Iv | P_DATA16 | LOWREGMASK(a0), 3084 0, a0, 0); 3085 tcg_out16(s, a2); 3086 } else { 3087 tcg_out_modrm(s, OPC_MOVL_EvGv | P_DATA16, a2, a0); 3088 } 3089 } else { 3090 g_assert_not_reached(); 3091 } 3092 break; 3093 3094 case INDEX_op_extract_i64: 3095 if (a2 + args[3] == 32) { 3096 if (a2 == 0) { 3097 tcg_out_ext32u(s, a0, a1); 3098 break; 3099 } 3100 /* This is a 32-bit zero-extending right shift. */ 3101 tcg_out_mov(s, TCG_TYPE_I32, a0, a1); 3102 tcg_out_shifti(s, SHIFT_SHR, a0, a2); 3103 break; 3104 } 3105 /* FALLTHRU */ 3106 case INDEX_op_extract_i32: 3107 if (a2 == 0 && args[3] == 8) { 3108 tcg_out_ext8u(s, a0, a1); 3109 } else if (a2 == 0 && args[3] == 16) { 3110 tcg_out_ext16u(s, a0, a1); 3111 } else if (a2 == 8 && args[3] == 8) { 3112 /* 3113 * On the off-chance that we can use the high-byte registers. 3114 * Otherwise we emit the same ext16 + shift pattern that we 3115 * would have gotten from the normal tcg-op.c expansion. 3116 */ 3117 if (a1 < 4 && a0 < 8) { 3118 tcg_out_modrm(s, OPC_MOVZBL, a0, a1 + 4); 3119 } else { 3120 tcg_out_ext16u(s, a0, a1); 3121 tcg_out_shifti(s, SHIFT_SHR, a0, 8); 3122 } 3123 } else { 3124 g_assert_not_reached(); 3125 } 3126 break; 3127 3128 case INDEX_op_sextract_i64: 3129 if (a2 == 0 && args[3] == 8) { 3130 tcg_out_ext8s(s, TCG_TYPE_I64, a0, a1); 3131 } else if (a2 == 0 && args[3] == 16) { 3132 tcg_out_ext16s(s, TCG_TYPE_I64, a0, a1); 3133 } else if (a2 == 0 && args[3] == 32) { 3134 tcg_out_ext32s(s, a0, a1); 3135 } else { 3136 g_assert_not_reached(); 3137 } 3138 break; 3139 3140 case INDEX_op_sextract_i32: 3141 if (a2 == 0 && args[3] == 8) { 3142 tcg_out_ext8s(s, TCG_TYPE_I32, a0, a1); 3143 } else if (a2 == 0 && args[3] == 16) { 3144 tcg_out_ext16s(s, TCG_TYPE_I32, a0, a1); 3145 } else if (a2 == 8 && args[3] == 8) { 3146 if (a1 < 4 && a0 < 8) { 3147 tcg_out_modrm(s, OPC_MOVSBL, a0, a1 + 4); 3148 } else { 3149 tcg_out_ext16s(s, TCG_TYPE_I32, a0, a1); 3150 tcg_out_shifti(s, SHIFT_SAR, a0, 8); 3151 } 3152 } else { 3153 g_assert_not_reached(); 3154 } 3155 break; 3156 3157 OP_32_64(extract2): 3158 /* Note that SHRD outputs to the r/m operand. */ 3159 tcg_out_modrm(s, OPC_SHRD_Ib + rexw, a2, a0); 3160 tcg_out8(s, args[3]); 3161 break; 3162 3163 case INDEX_op_mb: 3164 tcg_out_mb(s, a0); 3165 break; 3166 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 3167 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 3168 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 3169 case INDEX_op_ext_i32_i64: /* Always emitted via tcg_reg_alloc_op. */ 3170 case INDEX_op_extu_i32_i64: 3171 case INDEX_op_extrl_i64_i32: 3172 default: 3173 g_assert_not_reached(); 3174 } 3175 3176#undef OP_32_64 3177} 3178 3179static int const umin_insn[4] = { 3180 OPC_PMINUB, OPC_PMINUW, OPC_PMINUD, OPC_VPMINUQ 3181}; 3182 3183static int const umax_insn[4] = { 3184 OPC_PMAXUB, OPC_PMAXUW, OPC_PMAXUD, OPC_VPMAXUQ 3185}; 3186 3187static bool tcg_out_cmp_vec_noinv(TCGContext *s, TCGType type, unsigned vece, 3188 TCGReg v0, TCGReg v1, TCGReg v2, TCGCond cond) 3189{ 3190 static int const cmpeq_insn[4] = { 3191 OPC_PCMPEQB, OPC_PCMPEQW, OPC_PCMPEQD, OPC_PCMPEQQ 3192 }; 3193 static int const cmpgt_insn[4] = { 3194 OPC_PCMPGTB, OPC_PCMPGTW, OPC_PCMPGTD, OPC_PCMPGTQ 3195 }; 3196 3197 enum { 3198 NEED_INV = 1, 3199 NEED_SWAP = 2, 3200 NEED_UMIN = 4, 3201 NEED_UMAX = 8, 3202 INVALID = 16, 3203 }; 3204 static const uint8_t cond_fixup[16] = { 3205 [0 ... 15] = INVALID, 3206 [TCG_COND_EQ] = 0, 3207 [TCG_COND_GT] = 0, 3208 [TCG_COND_NE] = NEED_INV, 3209 [TCG_COND_LE] = NEED_INV, 3210 [TCG_COND_LT] = NEED_SWAP, 3211 [TCG_COND_GE] = NEED_SWAP | NEED_INV, 3212 [TCG_COND_LEU] = NEED_UMIN, 3213 [TCG_COND_GTU] = NEED_UMIN | NEED_INV, 3214 [TCG_COND_GEU] = NEED_UMAX, 3215 [TCG_COND_LTU] = NEED_UMAX | NEED_INV, 3216 }; 3217 int fixup = cond_fixup[cond]; 3218 3219 assert(!(fixup & INVALID)); 3220 3221 if (fixup & NEED_INV) { 3222 cond = tcg_invert_cond(cond); 3223 } 3224 3225 if (fixup & NEED_SWAP) { 3226 TCGReg swap = v1; 3227 v1 = v2; 3228 v2 = swap; 3229 cond = tcg_swap_cond(cond); 3230 } 3231 3232 if (fixup & (NEED_UMIN | NEED_UMAX)) { 3233 int op = (fixup & NEED_UMIN ? umin_insn[vece] : umax_insn[vece]); 3234 3235 /* avx2 does not have 64-bit min/max; adjusted during expand. */ 3236 assert(vece <= MO_32); 3237 3238 tcg_out_vex_modrm_type(s, op, TCG_TMP_VEC, v1, v2, type); 3239 v2 = TCG_TMP_VEC; 3240 cond = TCG_COND_EQ; 3241 } 3242 3243 switch (cond) { 3244 case TCG_COND_EQ: 3245 tcg_out_vex_modrm_type(s, cmpeq_insn[vece], v0, v1, v2, type); 3246 break; 3247 case TCG_COND_GT: 3248 tcg_out_vex_modrm_type(s, cmpgt_insn[vece], v0, v1, v2, type); 3249 break; 3250 default: 3251 g_assert_not_reached(); 3252 } 3253 return fixup & NEED_INV; 3254} 3255 3256static void tcg_out_cmp_vec_k1(TCGContext *s, TCGType type, unsigned vece, 3257 TCGReg v1, TCGReg v2, TCGCond cond) 3258{ 3259 static const int cmpm_insn[2][4] = { 3260 { OPC_VPCMPB, OPC_VPCMPW, OPC_VPCMPD, OPC_VPCMPQ }, 3261 { OPC_VPCMPUB, OPC_VPCMPUW, OPC_VPCMPUD, OPC_VPCMPUQ } 3262 }; 3263 static const int testm_insn[4] = { 3264 OPC_VPTESTMB, OPC_VPTESTMW, OPC_VPTESTMD, OPC_VPTESTMQ 3265 }; 3266 static const int testnm_insn[4] = { 3267 OPC_VPTESTNMB, OPC_VPTESTNMW, OPC_VPTESTNMD, OPC_VPTESTNMQ 3268 }; 3269 3270 static const int cond_ext[16] = { 3271 [TCG_COND_EQ] = 0, 3272 [TCG_COND_NE] = 4, 3273 [TCG_COND_LT] = 1, 3274 [TCG_COND_LTU] = 1, 3275 [TCG_COND_LE] = 2, 3276 [TCG_COND_LEU] = 2, 3277 [TCG_COND_NEVER] = 3, 3278 [TCG_COND_GE] = 5, 3279 [TCG_COND_GEU] = 5, 3280 [TCG_COND_GT] = 6, 3281 [TCG_COND_GTU] = 6, 3282 [TCG_COND_ALWAYS] = 7, 3283 }; 3284 3285 switch (cond) { 3286 case TCG_COND_TSTNE: 3287 tcg_out_vex_modrm_type(s, testm_insn[vece], /* k1 */ 1, v1, v2, type); 3288 break; 3289 case TCG_COND_TSTEQ: 3290 tcg_out_vex_modrm_type(s, testnm_insn[vece], /* k1 */ 1, v1, v2, type); 3291 break; 3292 default: 3293 tcg_out_vex_modrm_type(s, cmpm_insn[is_unsigned_cond(cond)][vece], 3294 /* k1 */ 1, v1, v2, type); 3295 tcg_out8(s, cond_ext[cond]); 3296 break; 3297 } 3298} 3299 3300static void tcg_out_k1_to_vec(TCGContext *s, TCGType type, 3301 unsigned vece, TCGReg dest) 3302{ 3303 static const int movm_insn[] = { 3304 OPC_VPMOVM2B, OPC_VPMOVM2W, OPC_VPMOVM2D, OPC_VPMOVM2Q 3305 }; 3306 tcg_out_vex_modrm_type(s, movm_insn[vece], dest, 0, /* k1 */ 1, type); 3307} 3308 3309static void tcg_out_cmp_vec(TCGContext *s, TCGType type, unsigned vece, 3310 TCGReg v0, TCGReg v1, TCGReg v2, TCGCond cond) 3311{ 3312 /* 3313 * With avx512, we have a complete set of comparisons into mask. 3314 * Unless there's a single insn expansion for the comparision, 3315 * expand via a mask in k1. 3316 */ 3317 if ((vece <= MO_16 ? have_avx512bw : have_avx512dq) 3318 && cond != TCG_COND_EQ 3319 && cond != TCG_COND_LT 3320 && cond != TCG_COND_GT) { 3321 tcg_out_cmp_vec_k1(s, type, vece, v1, v2, cond); 3322 tcg_out_k1_to_vec(s, type, vece, v0); 3323 return; 3324 } 3325 3326 if (tcg_out_cmp_vec_noinv(s, type, vece, v0, v1, v2, cond)) { 3327 tcg_out_dupi_vec(s, type, vece, TCG_TMP_VEC, -1); 3328 tcg_out_vex_modrm_type(s, OPC_PXOR, v0, v0, TCG_TMP_VEC, type); 3329 } 3330} 3331 3332static void tcg_out_cmpsel_vec_k1(TCGContext *s, TCGType type, unsigned vece, 3333 TCGReg v0, TCGReg c1, TCGReg c2, 3334 TCGReg v3, TCGReg v4, TCGCond cond) 3335{ 3336 static const int vpblendm_insn[] = { 3337 OPC_VPBLENDMB, OPC_VPBLENDMW, OPC_VPBLENDMD, OPC_VPBLENDMQ 3338 }; 3339 bool z = false; 3340 3341 /* Swap to place constant in V4 to take advantage of zero-masking. */ 3342 if (!v3) { 3343 z = true; 3344 v3 = v4; 3345 cond = tcg_invert_cond(cond); 3346 } 3347 3348 tcg_out_cmp_vec_k1(s, type, vece, c1, c2, cond); 3349 tcg_out_evex_modrm_type(s, vpblendm_insn[vece], v0, v4, v3, 3350 /* k1 */1, z, type); 3351} 3352 3353static void tcg_out_cmpsel_vec(TCGContext *s, TCGType type, unsigned vece, 3354 TCGReg v0, TCGReg c1, TCGReg c2, 3355 TCGReg v3, TCGReg v4, TCGCond cond) 3356{ 3357 bool inv; 3358 3359 if (vece <= MO_16 ? have_avx512bw : have_avx512vl) { 3360 tcg_out_cmpsel_vec_k1(s, type, vece, v0, c1, c2, v3, v4, cond); 3361 return; 3362 } 3363 3364 inv = tcg_out_cmp_vec_noinv(s, type, vece, TCG_TMP_VEC, c1, c2, cond); 3365 3366 /* 3367 * Since XMM0 is 16, the only way we get 0 into V3 3368 * is via the constant zero constraint. 3369 */ 3370 if (!v3) { 3371 if (inv) { 3372 tcg_out_vex_modrm_type(s, OPC_PAND, v0, TCG_TMP_VEC, v4, type); 3373 } else { 3374 tcg_out_vex_modrm_type(s, OPC_PANDN, v0, TCG_TMP_VEC, v4, type); 3375 } 3376 } else { 3377 if (inv) { 3378 TCGReg swap = v3; 3379 v3 = v4; 3380 v4 = swap; 3381 } 3382 tcg_out_vex_modrm_type(s, OPC_VPBLENDVB, v0, v4, v3, type); 3383 tcg_out8(s, (TCG_TMP_VEC - TCG_REG_XMM0) << 4); 3384 } 3385} 3386 3387static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 3388 unsigned vecl, unsigned vece, 3389 const TCGArg args[TCG_MAX_OP_ARGS], 3390 const int const_args[TCG_MAX_OP_ARGS]) 3391{ 3392 static int const add_insn[4] = { 3393 OPC_PADDB, OPC_PADDW, OPC_PADDD, OPC_PADDQ 3394 }; 3395 static int const ssadd_insn[4] = { 3396 OPC_PADDSB, OPC_PADDSW, OPC_UD2, OPC_UD2 3397 }; 3398 static int const usadd_insn[4] = { 3399 OPC_PADDUB, OPC_PADDUW, OPC_UD2, OPC_UD2 3400 }; 3401 static int const sub_insn[4] = { 3402 OPC_PSUBB, OPC_PSUBW, OPC_PSUBD, OPC_PSUBQ 3403 }; 3404 static int const sssub_insn[4] = { 3405 OPC_PSUBSB, OPC_PSUBSW, OPC_UD2, OPC_UD2 3406 }; 3407 static int const ussub_insn[4] = { 3408 OPC_PSUBUB, OPC_PSUBUW, OPC_UD2, OPC_UD2 3409 }; 3410 static int const mul_insn[4] = { 3411 OPC_UD2, OPC_PMULLW, OPC_PMULLD, OPC_VPMULLQ 3412 }; 3413 static int const shift_imm_insn[4] = { 3414 OPC_UD2, OPC_PSHIFTW_Ib, OPC_PSHIFTD_Ib, OPC_PSHIFTQ_Ib 3415 }; 3416 static int const punpckl_insn[4] = { 3417 OPC_PUNPCKLBW, OPC_PUNPCKLWD, OPC_PUNPCKLDQ, OPC_PUNPCKLQDQ 3418 }; 3419 static int const punpckh_insn[4] = { 3420 OPC_PUNPCKHBW, OPC_PUNPCKHWD, OPC_PUNPCKHDQ, OPC_PUNPCKHQDQ 3421 }; 3422 static int const packss_insn[4] = { 3423 OPC_PACKSSWB, OPC_PACKSSDW, OPC_UD2, OPC_UD2 3424 }; 3425 static int const packus_insn[4] = { 3426 OPC_PACKUSWB, OPC_PACKUSDW, OPC_UD2, OPC_UD2 3427 }; 3428 static int const smin_insn[4] = { 3429 OPC_PMINSB, OPC_PMINSW, OPC_PMINSD, OPC_VPMINSQ 3430 }; 3431 static int const smax_insn[4] = { 3432 OPC_PMAXSB, OPC_PMAXSW, OPC_PMAXSD, OPC_VPMAXSQ 3433 }; 3434 static int const rotlv_insn[4] = { 3435 OPC_UD2, OPC_UD2, OPC_VPROLVD, OPC_VPROLVQ 3436 }; 3437 static int const rotrv_insn[4] = { 3438 OPC_UD2, OPC_UD2, OPC_VPRORVD, OPC_VPRORVQ 3439 }; 3440 static int const shlv_insn[4] = { 3441 OPC_UD2, OPC_VPSLLVW, OPC_VPSLLVD, OPC_VPSLLVQ 3442 }; 3443 static int const shrv_insn[4] = { 3444 OPC_UD2, OPC_VPSRLVW, OPC_VPSRLVD, OPC_VPSRLVQ 3445 }; 3446 static int const sarv_insn[4] = { 3447 OPC_UD2, OPC_VPSRAVW, OPC_VPSRAVD, OPC_VPSRAVQ 3448 }; 3449 static int const shls_insn[4] = { 3450 OPC_UD2, OPC_PSLLW, OPC_PSLLD, OPC_PSLLQ 3451 }; 3452 static int const shrs_insn[4] = { 3453 OPC_UD2, OPC_PSRLW, OPC_PSRLD, OPC_PSRLQ 3454 }; 3455 static int const sars_insn[4] = { 3456 OPC_UD2, OPC_PSRAW, OPC_PSRAD, OPC_VPSRAQ 3457 }; 3458 static int const vpshldi_insn[4] = { 3459 OPC_UD2, OPC_VPSHLDW, OPC_VPSHLDD, OPC_VPSHLDQ 3460 }; 3461 static int const vpshldv_insn[4] = { 3462 OPC_UD2, OPC_VPSHLDVW, OPC_VPSHLDVD, OPC_VPSHLDVQ 3463 }; 3464 static int const vpshrdv_insn[4] = { 3465 OPC_UD2, OPC_VPSHRDVW, OPC_VPSHRDVD, OPC_VPSHRDVQ 3466 }; 3467 static int const abs_insn[4] = { 3468 OPC_PABSB, OPC_PABSW, OPC_PABSD, OPC_VPABSQ 3469 }; 3470 3471 TCGType type = vecl + TCG_TYPE_V64; 3472 int insn, sub; 3473 TCGArg a0, a1, a2, a3; 3474 3475 a0 = args[0]; 3476 a1 = args[1]; 3477 a2 = args[2]; 3478 3479 switch (opc) { 3480 case INDEX_op_add_vec: 3481 insn = add_insn[vece]; 3482 goto gen_simd; 3483 case INDEX_op_ssadd_vec: 3484 insn = ssadd_insn[vece]; 3485 goto gen_simd; 3486 case INDEX_op_usadd_vec: 3487 insn = usadd_insn[vece]; 3488 goto gen_simd; 3489 case INDEX_op_sub_vec: 3490 insn = sub_insn[vece]; 3491 goto gen_simd; 3492 case INDEX_op_sssub_vec: 3493 insn = sssub_insn[vece]; 3494 goto gen_simd; 3495 case INDEX_op_ussub_vec: 3496 insn = ussub_insn[vece]; 3497 goto gen_simd; 3498 case INDEX_op_mul_vec: 3499 insn = mul_insn[vece]; 3500 goto gen_simd; 3501 case INDEX_op_and_vec: 3502 insn = OPC_PAND; 3503 goto gen_simd; 3504 case INDEX_op_or_vec: 3505 insn = OPC_POR; 3506 goto gen_simd; 3507 case INDEX_op_xor_vec: 3508 insn = OPC_PXOR; 3509 goto gen_simd; 3510 case INDEX_op_smin_vec: 3511 insn = smin_insn[vece]; 3512 goto gen_simd; 3513 case INDEX_op_umin_vec: 3514 insn = umin_insn[vece]; 3515 goto gen_simd; 3516 case INDEX_op_smax_vec: 3517 insn = smax_insn[vece]; 3518 goto gen_simd; 3519 case INDEX_op_umax_vec: 3520 insn = umax_insn[vece]; 3521 goto gen_simd; 3522 case INDEX_op_shlv_vec: 3523 insn = shlv_insn[vece]; 3524 goto gen_simd; 3525 case INDEX_op_shrv_vec: 3526 insn = shrv_insn[vece]; 3527 goto gen_simd; 3528 case INDEX_op_sarv_vec: 3529 insn = sarv_insn[vece]; 3530 goto gen_simd; 3531 case INDEX_op_rotlv_vec: 3532 insn = rotlv_insn[vece]; 3533 goto gen_simd; 3534 case INDEX_op_rotrv_vec: 3535 insn = rotrv_insn[vece]; 3536 goto gen_simd; 3537 case INDEX_op_shls_vec: 3538 insn = shls_insn[vece]; 3539 goto gen_simd; 3540 case INDEX_op_shrs_vec: 3541 insn = shrs_insn[vece]; 3542 goto gen_simd; 3543 case INDEX_op_sars_vec: 3544 insn = sars_insn[vece]; 3545 goto gen_simd; 3546 case INDEX_op_x86_punpckl_vec: 3547 insn = punpckl_insn[vece]; 3548 goto gen_simd; 3549 case INDEX_op_x86_punpckh_vec: 3550 insn = punpckh_insn[vece]; 3551 goto gen_simd; 3552 case INDEX_op_x86_packss_vec: 3553 insn = packss_insn[vece]; 3554 goto gen_simd; 3555 case INDEX_op_x86_packus_vec: 3556 insn = packus_insn[vece]; 3557 goto gen_simd; 3558 case INDEX_op_x86_vpshldv_vec: 3559 insn = vpshldv_insn[vece]; 3560 a1 = a2; 3561 a2 = args[3]; 3562 goto gen_simd; 3563 case INDEX_op_x86_vpshrdv_vec: 3564 insn = vpshrdv_insn[vece]; 3565 a1 = a2; 3566 a2 = args[3]; 3567 goto gen_simd; 3568#if TCG_TARGET_REG_BITS == 32 3569 case INDEX_op_dup2_vec: 3570 /* First merge the two 32-bit inputs to a single 64-bit element. */ 3571 tcg_out_vex_modrm(s, OPC_PUNPCKLDQ, a0, a1, a2); 3572 /* Then replicate the 64-bit elements across the rest of the vector. */ 3573 if (type != TCG_TYPE_V64) { 3574 tcg_out_dup_vec(s, type, MO_64, a0, a0); 3575 } 3576 break; 3577#endif 3578 case INDEX_op_abs_vec: 3579 insn = abs_insn[vece]; 3580 a2 = a1; 3581 a1 = 0; 3582 goto gen_simd; 3583 gen_simd: 3584 tcg_debug_assert(insn != OPC_UD2); 3585 tcg_out_vex_modrm_type(s, insn, a0, a1, a2, type); 3586 break; 3587 3588 case INDEX_op_cmp_vec: 3589 tcg_out_cmp_vec(s, type, vece, a0, a1, a2, args[3]); 3590 break; 3591 3592 case INDEX_op_cmpsel_vec: 3593 tcg_out_cmpsel_vec(s, type, vece, a0, a1, a2, 3594 args[3], args[4], args[5]); 3595 break; 3596 3597 case INDEX_op_andc_vec: 3598 insn = OPC_PANDN; 3599 tcg_out_vex_modrm_type(s, insn, a0, a2, a1, type); 3600 break; 3601 3602 case INDEX_op_shli_vec: 3603 insn = shift_imm_insn[vece]; 3604 sub = 6; 3605 goto gen_shift; 3606 case INDEX_op_shri_vec: 3607 insn = shift_imm_insn[vece]; 3608 sub = 2; 3609 goto gen_shift; 3610 case INDEX_op_sari_vec: 3611 if (vece == MO_64) { 3612 insn = OPC_PSHIFTD_Ib | P_VEXW | P_EVEX; 3613 } else { 3614 insn = shift_imm_insn[vece]; 3615 } 3616 sub = 4; 3617 goto gen_shift; 3618 case INDEX_op_rotli_vec: 3619 insn = OPC_PSHIFTD_Ib | P_EVEX; /* VPROL[DQ] */ 3620 if (vece == MO_64) { 3621 insn |= P_VEXW; 3622 } 3623 sub = 1; 3624 goto gen_shift; 3625 gen_shift: 3626 tcg_debug_assert(vece != MO_8); 3627 tcg_out_vex_modrm_type(s, insn, sub, a0, a1, type); 3628 tcg_out8(s, a2); 3629 break; 3630 3631 case INDEX_op_ld_vec: 3632 tcg_out_ld(s, type, a0, a1, a2); 3633 break; 3634 case INDEX_op_st_vec: 3635 tcg_out_st(s, type, a0, a1, a2); 3636 break; 3637 case INDEX_op_dupm_vec: 3638 tcg_out_dupm_vec(s, type, vece, a0, a1, a2); 3639 break; 3640 3641 case INDEX_op_x86_shufps_vec: 3642 insn = OPC_SHUFPS; 3643 sub = args[3]; 3644 goto gen_simd_imm8; 3645 case INDEX_op_x86_blend_vec: 3646 if (vece == MO_16) { 3647 insn = OPC_PBLENDW; 3648 } else if (vece == MO_32) { 3649 insn = (have_avx2 ? OPC_VPBLENDD : OPC_BLENDPS); 3650 } else { 3651 g_assert_not_reached(); 3652 } 3653 sub = args[3]; 3654 goto gen_simd_imm8; 3655 case INDEX_op_x86_vperm2i128_vec: 3656 insn = OPC_VPERM2I128; 3657 sub = args[3]; 3658 goto gen_simd_imm8; 3659 case INDEX_op_x86_vpshldi_vec: 3660 insn = vpshldi_insn[vece]; 3661 sub = args[3]; 3662 goto gen_simd_imm8; 3663 3664 case INDEX_op_not_vec: 3665 insn = OPC_VPTERNLOGQ; 3666 a2 = a1; 3667 sub = 0x33; /* !B */ 3668 goto gen_simd_imm8; 3669 case INDEX_op_nor_vec: 3670 insn = OPC_VPTERNLOGQ; 3671 sub = 0x11; /* norCB */ 3672 goto gen_simd_imm8; 3673 case INDEX_op_nand_vec: 3674 insn = OPC_VPTERNLOGQ; 3675 sub = 0x77; /* nandCB */ 3676 goto gen_simd_imm8; 3677 case INDEX_op_eqv_vec: 3678 insn = OPC_VPTERNLOGQ; 3679 sub = 0x99; /* xnorCB */ 3680 goto gen_simd_imm8; 3681 case INDEX_op_orc_vec: 3682 insn = OPC_VPTERNLOGQ; 3683 sub = 0xdd; /* orB!C */ 3684 goto gen_simd_imm8; 3685 3686 case INDEX_op_bitsel_vec: 3687 insn = OPC_VPTERNLOGQ; 3688 a3 = args[3]; 3689 if (a0 == a1) { 3690 a1 = a2; 3691 a2 = a3; 3692 sub = 0xca; /* A?B:C */ 3693 } else if (a0 == a2) { 3694 a2 = a3; 3695 sub = 0xe2; /* B?A:C */ 3696 } else { 3697 tcg_out_mov(s, type, a0, a3); 3698 sub = 0xb8; /* B?C:A */ 3699 } 3700 goto gen_simd_imm8; 3701 3702 gen_simd_imm8: 3703 tcg_debug_assert(insn != OPC_UD2); 3704 tcg_out_vex_modrm_type(s, insn, a0, a1, a2, type); 3705 tcg_out8(s, sub); 3706 break; 3707 3708 case INDEX_op_x86_psrldq_vec: 3709 tcg_out_vex_modrm(s, OPC_GRP14, 3, a0, a1); 3710 tcg_out8(s, a2); 3711 break; 3712 3713 case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ 3714 case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ 3715 default: 3716 g_assert_not_reached(); 3717 } 3718} 3719 3720static TCGConstraintSetIndex 3721tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) 3722{ 3723 switch (op) { 3724 case INDEX_op_goto_ptr: 3725 return C_O0_I1(r); 3726 3727 case INDEX_op_ld8u_i32: 3728 case INDEX_op_ld8u_i64: 3729 case INDEX_op_ld8s_i32: 3730 case INDEX_op_ld8s_i64: 3731 case INDEX_op_ld16u_i32: 3732 case INDEX_op_ld16u_i64: 3733 case INDEX_op_ld16s_i32: 3734 case INDEX_op_ld16s_i64: 3735 case INDEX_op_ld_i32: 3736 case INDEX_op_ld32u_i64: 3737 case INDEX_op_ld32s_i64: 3738 case INDEX_op_ld_i64: 3739 return C_O1_I1(r, r); 3740 3741 case INDEX_op_st8_i32: 3742 case INDEX_op_st8_i64: 3743 return C_O0_I2(qi, r); 3744 3745 case INDEX_op_st16_i32: 3746 case INDEX_op_st16_i64: 3747 case INDEX_op_st_i32: 3748 case INDEX_op_st32_i64: 3749 return C_O0_I2(ri, r); 3750 3751 case INDEX_op_st_i64: 3752 return C_O0_I2(re, r); 3753 3754 case INDEX_op_shl_i32: 3755 case INDEX_op_shl_i64: 3756 case INDEX_op_shr_i32: 3757 case INDEX_op_shr_i64: 3758 case INDEX_op_sar_i32: 3759 case INDEX_op_sar_i64: 3760 return have_bmi2 ? C_O1_I2(r, r, ri) : C_O1_I2(r, 0, ci); 3761 3762 case INDEX_op_rotl_i32: 3763 case INDEX_op_rotl_i64: 3764 case INDEX_op_rotr_i32: 3765 case INDEX_op_rotr_i64: 3766 return C_O1_I2(r, 0, ci); 3767 3768 case INDEX_op_brcond_i32: 3769 case INDEX_op_brcond_i64: 3770 return C_O0_I2(r, reT); 3771 3772 case INDEX_op_bswap16_i32: 3773 case INDEX_op_bswap16_i64: 3774 case INDEX_op_bswap32_i32: 3775 case INDEX_op_bswap32_i64: 3776 case INDEX_op_bswap64_i64: 3777 case INDEX_op_extrh_i64_i32: 3778 return C_O1_I1(r, 0); 3779 3780 case INDEX_op_ext_i32_i64: 3781 case INDEX_op_extu_i32_i64: 3782 case INDEX_op_extrl_i64_i32: 3783 case INDEX_op_extract_i32: 3784 case INDEX_op_extract_i64: 3785 case INDEX_op_sextract_i32: 3786 case INDEX_op_sextract_i64: 3787 case INDEX_op_ctpop_i32: 3788 case INDEX_op_ctpop_i64: 3789 return C_O1_I1(r, r); 3790 3791 case INDEX_op_extract2_i32: 3792 case INDEX_op_extract2_i64: 3793 return C_O1_I2(r, 0, r); 3794 3795 case INDEX_op_deposit_i32: 3796 case INDEX_op_deposit_i64: 3797 return C_O1_I2(q, 0, qi); 3798 3799 case INDEX_op_setcond_i32: 3800 case INDEX_op_setcond_i64: 3801 case INDEX_op_negsetcond_i32: 3802 case INDEX_op_negsetcond_i64: 3803 return C_O1_I2(q, r, reT); 3804 3805 case INDEX_op_movcond_i32: 3806 case INDEX_op_movcond_i64: 3807 return C_O1_I4(r, r, reT, r, 0); 3808 3809 case INDEX_op_mulu2_i32: 3810 case INDEX_op_mulu2_i64: 3811 case INDEX_op_muls2_i32: 3812 case INDEX_op_muls2_i64: 3813 return C_O2_I2(a, d, a, r); 3814 3815 case INDEX_op_add2_i32: 3816 case INDEX_op_add2_i64: 3817 case INDEX_op_sub2_i32: 3818 case INDEX_op_sub2_i64: 3819 return C_N1_O1_I4(r, r, 0, 1, re, re); 3820 3821 case INDEX_op_ctz_i32: 3822 case INDEX_op_ctz_i64: 3823 return have_bmi1 ? C_N1_I2(r, r, rW) : C_N1_I2(r, r, r); 3824 3825 case INDEX_op_clz_i32: 3826 case INDEX_op_clz_i64: 3827 return have_lzcnt ? C_N1_I2(r, r, rW) : C_N1_I2(r, r, r); 3828 3829 case INDEX_op_qemu_ld_i32: 3830 return C_O1_I1(r, L); 3831 3832 case INDEX_op_qemu_st_i32: 3833 return C_O0_I2(L, L); 3834 case INDEX_op_qemu_st8_i32: 3835 return C_O0_I2(s, L); 3836 3837 case INDEX_op_qemu_ld_i64: 3838 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L) : C_O2_I1(r, r, L); 3839 3840 case INDEX_op_qemu_st_i64: 3841 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(L, L) : C_O0_I3(L, L, L); 3842 3843 case INDEX_op_qemu_ld_i128: 3844 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 3845 return C_O2_I1(r, r, L); 3846 case INDEX_op_qemu_st_i128: 3847 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 3848 return C_O0_I3(L, L, L); 3849 3850 case INDEX_op_brcond2_i32: 3851 return C_O0_I4(r, r, ri, ri); 3852 3853 case INDEX_op_setcond2_i32: 3854 return C_O1_I4(r, r, r, ri, ri); 3855 3856 case INDEX_op_ld_vec: 3857 case INDEX_op_dupm_vec: 3858 return C_O1_I1(x, r); 3859 3860 case INDEX_op_st_vec: 3861 return C_O0_I2(x, r); 3862 3863 case INDEX_op_add_vec: 3864 case INDEX_op_sub_vec: 3865 case INDEX_op_mul_vec: 3866 case INDEX_op_and_vec: 3867 case INDEX_op_or_vec: 3868 case INDEX_op_xor_vec: 3869 case INDEX_op_andc_vec: 3870 case INDEX_op_orc_vec: 3871 case INDEX_op_nand_vec: 3872 case INDEX_op_nor_vec: 3873 case INDEX_op_eqv_vec: 3874 case INDEX_op_ssadd_vec: 3875 case INDEX_op_usadd_vec: 3876 case INDEX_op_sssub_vec: 3877 case INDEX_op_ussub_vec: 3878 case INDEX_op_smin_vec: 3879 case INDEX_op_umin_vec: 3880 case INDEX_op_smax_vec: 3881 case INDEX_op_umax_vec: 3882 case INDEX_op_shlv_vec: 3883 case INDEX_op_shrv_vec: 3884 case INDEX_op_sarv_vec: 3885 case INDEX_op_rotlv_vec: 3886 case INDEX_op_rotrv_vec: 3887 case INDEX_op_shls_vec: 3888 case INDEX_op_shrs_vec: 3889 case INDEX_op_sars_vec: 3890 case INDEX_op_cmp_vec: 3891 case INDEX_op_x86_shufps_vec: 3892 case INDEX_op_x86_blend_vec: 3893 case INDEX_op_x86_packss_vec: 3894 case INDEX_op_x86_packus_vec: 3895 case INDEX_op_x86_vperm2i128_vec: 3896 case INDEX_op_x86_punpckl_vec: 3897 case INDEX_op_x86_punpckh_vec: 3898 case INDEX_op_x86_vpshldi_vec: 3899#if TCG_TARGET_REG_BITS == 32 3900 case INDEX_op_dup2_vec: 3901#endif 3902 return C_O1_I2(x, x, x); 3903 3904 case INDEX_op_abs_vec: 3905 case INDEX_op_dup_vec: 3906 case INDEX_op_not_vec: 3907 case INDEX_op_shli_vec: 3908 case INDEX_op_shri_vec: 3909 case INDEX_op_sari_vec: 3910 case INDEX_op_rotli_vec: 3911 case INDEX_op_x86_psrldq_vec: 3912 return C_O1_I1(x, x); 3913 3914 case INDEX_op_x86_vpshldv_vec: 3915 case INDEX_op_x86_vpshrdv_vec: 3916 return C_O1_I3(x, 0, x, x); 3917 3918 case INDEX_op_bitsel_vec: 3919 return C_O1_I3(x, x, x, x); 3920 case INDEX_op_cmpsel_vec: 3921 return C_O1_I4(x, x, x, xO, x); 3922 3923 default: 3924 return C_NotImplemented; 3925 } 3926} 3927 3928int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 3929{ 3930 switch (opc) { 3931 case INDEX_op_add_vec: 3932 case INDEX_op_sub_vec: 3933 case INDEX_op_and_vec: 3934 case INDEX_op_or_vec: 3935 case INDEX_op_xor_vec: 3936 case INDEX_op_andc_vec: 3937 case INDEX_op_orc_vec: 3938 case INDEX_op_nand_vec: 3939 case INDEX_op_nor_vec: 3940 case INDEX_op_eqv_vec: 3941 case INDEX_op_not_vec: 3942 case INDEX_op_bitsel_vec: 3943 return 1; 3944 case INDEX_op_cmp_vec: 3945 case INDEX_op_cmpsel_vec: 3946 return -1; 3947 3948 case INDEX_op_rotli_vec: 3949 return have_avx512vl && vece >= MO_32 ? 1 : -1; 3950 3951 case INDEX_op_shli_vec: 3952 case INDEX_op_shri_vec: 3953 /* We must expand the operation for MO_8. */ 3954 return vece == MO_8 ? -1 : 1; 3955 3956 case INDEX_op_sari_vec: 3957 switch (vece) { 3958 case MO_8: 3959 return -1; 3960 case MO_16: 3961 case MO_32: 3962 return 1; 3963 case MO_64: 3964 if (have_avx512vl) { 3965 return 1; 3966 } 3967 /* 3968 * We can emulate this for MO_64, but it does not pay off 3969 * unless we're producing at least 4 values. 3970 */ 3971 return type >= TCG_TYPE_V256 ? -1 : 0; 3972 } 3973 return 0; 3974 3975 case INDEX_op_shls_vec: 3976 case INDEX_op_shrs_vec: 3977 return vece >= MO_16; 3978 case INDEX_op_sars_vec: 3979 switch (vece) { 3980 case MO_16: 3981 case MO_32: 3982 return 1; 3983 case MO_64: 3984 return have_avx512vl; 3985 } 3986 return 0; 3987 case INDEX_op_rotls_vec: 3988 return vece >= MO_16 ? -1 : 0; 3989 3990 case INDEX_op_shlv_vec: 3991 case INDEX_op_shrv_vec: 3992 switch (vece) { 3993 case MO_16: 3994 return have_avx512bw; 3995 case MO_32: 3996 case MO_64: 3997 return have_avx2; 3998 } 3999 return 0; 4000 case INDEX_op_sarv_vec: 4001 switch (vece) { 4002 case MO_16: 4003 return have_avx512bw; 4004 case MO_32: 4005 return have_avx2; 4006 case MO_64: 4007 return have_avx512vl; 4008 } 4009 return 0; 4010 case INDEX_op_rotlv_vec: 4011 case INDEX_op_rotrv_vec: 4012 switch (vece) { 4013 case MO_16: 4014 return have_avx512vbmi2 ? -1 : 0; 4015 case MO_32: 4016 case MO_64: 4017 return have_avx512vl ? 1 : have_avx2 ? -1 : 0; 4018 } 4019 return 0; 4020 4021 case INDEX_op_mul_vec: 4022 switch (vece) { 4023 case MO_8: 4024 return -1; 4025 case MO_64: 4026 return have_avx512dq; 4027 } 4028 return 1; 4029 4030 case INDEX_op_ssadd_vec: 4031 case INDEX_op_usadd_vec: 4032 case INDEX_op_sssub_vec: 4033 case INDEX_op_ussub_vec: 4034 return vece <= MO_16; 4035 case INDEX_op_smin_vec: 4036 case INDEX_op_smax_vec: 4037 case INDEX_op_umin_vec: 4038 case INDEX_op_umax_vec: 4039 case INDEX_op_abs_vec: 4040 return vece <= MO_32 || have_avx512vl; 4041 4042 default: 4043 return 0; 4044 } 4045} 4046 4047static void expand_vec_shi(TCGType type, unsigned vece, bool right, 4048 TCGv_vec v0, TCGv_vec v1, TCGArg imm) 4049{ 4050 uint8_t mask; 4051 4052 tcg_debug_assert(vece == MO_8); 4053 if (right) { 4054 mask = 0xff >> imm; 4055 tcg_gen_shri_vec(MO_16, v0, v1, imm); 4056 } else { 4057 mask = 0xff << imm; 4058 tcg_gen_shli_vec(MO_16, v0, v1, imm); 4059 } 4060 tcg_gen_and_vec(MO_8, v0, v0, tcg_constant_vec(type, MO_8, mask)); 4061} 4062 4063static void expand_vec_sari(TCGType type, unsigned vece, 4064 TCGv_vec v0, TCGv_vec v1, TCGArg imm) 4065{ 4066 TCGv_vec t1, t2; 4067 4068 switch (vece) { 4069 case MO_8: 4070 /* Unpack to 16-bit, shift, and repack. */ 4071 t1 = tcg_temp_new_vec(type); 4072 t2 = tcg_temp_new_vec(type); 4073 vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8, 4074 tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(v1)); 4075 vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8, 4076 tcgv_vec_arg(t2), tcgv_vec_arg(v1), tcgv_vec_arg(v1)); 4077 tcg_gen_sari_vec(MO_16, t1, t1, imm + 8); 4078 tcg_gen_sari_vec(MO_16, t2, t2, imm + 8); 4079 vec_gen_3(INDEX_op_x86_packss_vec, type, MO_8, 4080 tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t2)); 4081 tcg_temp_free_vec(t1); 4082 tcg_temp_free_vec(t2); 4083 break; 4084 4085 case MO_64: 4086 t1 = tcg_temp_new_vec(type); 4087 if (imm <= 32) { 4088 /* 4089 * We can emulate a small sign extend by performing an arithmetic 4090 * 32-bit shift and overwriting the high half of a 64-bit logical 4091 * shift. Note that the ISA says shift of 32 is valid, but TCG 4092 * does not, so we have to bound the smaller shift -- we get the 4093 * same result in the high half either way. 4094 */ 4095 tcg_gen_sari_vec(MO_32, t1, v1, MIN(imm, 31)); 4096 tcg_gen_shri_vec(MO_64, v0, v1, imm); 4097 vec_gen_4(INDEX_op_x86_blend_vec, type, MO_32, 4098 tcgv_vec_arg(v0), tcgv_vec_arg(v0), 4099 tcgv_vec_arg(t1), 0xaa); 4100 } else { 4101 /* Otherwise we will need to use a compare vs 0 to produce 4102 * the sign-extend, shift and merge. 4103 */ 4104 tcg_gen_cmp_vec(TCG_COND_GT, MO_64, t1, 4105 tcg_constant_vec(type, MO_64, 0), v1); 4106 tcg_gen_shri_vec(MO_64, v0, v1, imm); 4107 tcg_gen_shli_vec(MO_64, t1, t1, 64 - imm); 4108 tcg_gen_or_vec(MO_64, v0, v0, t1); 4109 } 4110 tcg_temp_free_vec(t1); 4111 break; 4112 4113 default: 4114 g_assert_not_reached(); 4115 } 4116} 4117 4118static void expand_vec_rotli(TCGType type, unsigned vece, 4119 TCGv_vec v0, TCGv_vec v1, TCGArg imm) 4120{ 4121 TCGv_vec t; 4122 4123 if (vece != MO_8 && have_avx512vbmi2) { 4124 vec_gen_4(INDEX_op_x86_vpshldi_vec, type, vece, 4125 tcgv_vec_arg(v0), tcgv_vec_arg(v1), tcgv_vec_arg(v1), imm); 4126 return; 4127 } 4128 4129 t = tcg_temp_new_vec(type); 4130 tcg_gen_shli_vec(vece, t, v1, imm); 4131 tcg_gen_shri_vec(vece, v0, v1, (8 << vece) - imm); 4132 tcg_gen_or_vec(vece, v0, v0, t); 4133 tcg_temp_free_vec(t); 4134} 4135 4136static void expand_vec_rotv(TCGType type, unsigned vece, TCGv_vec v0, 4137 TCGv_vec v1, TCGv_vec sh, bool right) 4138{ 4139 TCGv_vec t; 4140 4141 if (have_avx512vbmi2) { 4142 vec_gen_4(right ? INDEX_op_x86_vpshrdv_vec : INDEX_op_x86_vpshldv_vec, 4143 type, vece, tcgv_vec_arg(v0), tcgv_vec_arg(v1), 4144 tcgv_vec_arg(v1), tcgv_vec_arg(sh)); 4145 return; 4146 } 4147 4148 t = tcg_temp_new_vec(type); 4149 tcg_gen_dupi_vec(vece, t, 8 << vece); 4150 tcg_gen_sub_vec(vece, t, t, sh); 4151 if (right) { 4152 tcg_gen_shlv_vec(vece, t, v1, t); 4153 tcg_gen_shrv_vec(vece, v0, v1, sh); 4154 } else { 4155 tcg_gen_shrv_vec(vece, t, v1, t); 4156 tcg_gen_shlv_vec(vece, v0, v1, sh); 4157 } 4158 tcg_gen_or_vec(vece, v0, v0, t); 4159 tcg_temp_free_vec(t); 4160} 4161 4162static void expand_vec_rotls(TCGType type, unsigned vece, 4163 TCGv_vec v0, TCGv_vec v1, TCGv_i32 lsh) 4164{ 4165 TCGv_vec t = tcg_temp_new_vec(type); 4166 4167 tcg_debug_assert(vece != MO_8); 4168 4169 if (vece >= MO_32 ? have_avx512vl : have_avx512vbmi2) { 4170 tcg_gen_dup_i32_vec(vece, t, lsh); 4171 if (vece >= MO_32) { 4172 tcg_gen_rotlv_vec(vece, v0, v1, t); 4173 } else { 4174 expand_vec_rotv(type, vece, v0, v1, t, false); 4175 } 4176 } else { 4177 TCGv_i32 rsh = tcg_temp_new_i32(); 4178 4179 tcg_gen_neg_i32(rsh, lsh); 4180 tcg_gen_andi_i32(rsh, rsh, (8 << vece) - 1); 4181 tcg_gen_shls_vec(vece, t, v1, lsh); 4182 tcg_gen_shrs_vec(vece, v0, v1, rsh); 4183 tcg_gen_or_vec(vece, v0, v0, t); 4184 4185 tcg_temp_free_i32(rsh); 4186 } 4187 4188 tcg_temp_free_vec(t); 4189} 4190 4191static void expand_vec_mul(TCGType type, unsigned vece, 4192 TCGv_vec v0, TCGv_vec v1, TCGv_vec v2) 4193{ 4194 TCGv_vec t1, t2, t3, t4, zero; 4195 4196 tcg_debug_assert(vece == MO_8); 4197 4198 /* 4199 * Unpack v1 bytes to words, 0 | x. 4200 * Unpack v2 bytes to words, y | 0. 4201 * This leaves the 8-bit result, x * y, with 8 bits of right padding. 4202 * Shift logical right by 8 bits to clear the high 8 bytes before 4203 * using an unsigned saturated pack. 4204 * 4205 * The difference between the V64, V128 and V256 cases is merely how 4206 * we distribute the expansion between temporaries. 4207 */ 4208 switch (type) { 4209 case TCG_TYPE_V64: 4210 t1 = tcg_temp_new_vec(TCG_TYPE_V128); 4211 t2 = tcg_temp_new_vec(TCG_TYPE_V128); 4212 zero = tcg_constant_vec(TCG_TYPE_V128, MO_8, 0); 4213 vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_8, 4214 tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(zero)); 4215 vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_8, 4216 tcgv_vec_arg(t2), tcgv_vec_arg(zero), tcgv_vec_arg(v2)); 4217 tcg_gen_mul_vec(MO_16, t1, t1, t2); 4218 tcg_gen_shri_vec(MO_16, t1, t1, 8); 4219 vec_gen_3(INDEX_op_x86_packus_vec, TCG_TYPE_V128, MO_8, 4220 tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t1)); 4221 tcg_temp_free_vec(t1); 4222 tcg_temp_free_vec(t2); 4223 break; 4224 4225 case TCG_TYPE_V128: 4226 case TCG_TYPE_V256: 4227 t1 = tcg_temp_new_vec(type); 4228 t2 = tcg_temp_new_vec(type); 4229 t3 = tcg_temp_new_vec(type); 4230 t4 = tcg_temp_new_vec(type); 4231 zero = tcg_constant_vec(TCG_TYPE_V128, MO_8, 0); 4232 vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8, 4233 tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(zero)); 4234 vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8, 4235 tcgv_vec_arg(t2), tcgv_vec_arg(zero), tcgv_vec_arg(v2)); 4236 vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8, 4237 tcgv_vec_arg(t3), tcgv_vec_arg(v1), tcgv_vec_arg(zero)); 4238 vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8, 4239 tcgv_vec_arg(t4), tcgv_vec_arg(zero), tcgv_vec_arg(v2)); 4240 tcg_gen_mul_vec(MO_16, t1, t1, t2); 4241 tcg_gen_mul_vec(MO_16, t3, t3, t4); 4242 tcg_gen_shri_vec(MO_16, t1, t1, 8); 4243 tcg_gen_shri_vec(MO_16, t3, t3, 8); 4244 vec_gen_3(INDEX_op_x86_packus_vec, type, MO_8, 4245 tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t3)); 4246 tcg_temp_free_vec(t1); 4247 tcg_temp_free_vec(t2); 4248 tcg_temp_free_vec(t3); 4249 tcg_temp_free_vec(t4); 4250 break; 4251 4252 default: 4253 g_assert_not_reached(); 4254 } 4255} 4256 4257static TCGCond expand_vec_cond(TCGType type, unsigned vece, 4258 TCGArg *a1, TCGArg *a2, TCGCond cond) 4259{ 4260 /* 4261 * Without AVX512, there are no 64-bit unsigned comparisons. 4262 * We must bias the inputs so that they become signed. 4263 * All other swapping and inversion are handled during code generation. 4264 */ 4265 if (vece == MO_64 && !have_avx512dq && is_unsigned_cond(cond)) { 4266 TCGv_vec v1 = temp_tcgv_vec(arg_temp(*a1)); 4267 TCGv_vec v2 = temp_tcgv_vec(arg_temp(*a2)); 4268 TCGv_vec t1 = tcg_temp_new_vec(type); 4269 TCGv_vec t2 = tcg_temp_new_vec(type); 4270 TCGv_vec t3 = tcg_constant_vec(type, vece, 1ull << ((8 << vece) - 1)); 4271 4272 tcg_gen_sub_vec(vece, t1, v1, t3); 4273 tcg_gen_sub_vec(vece, t2, v2, t3); 4274 *a1 = tcgv_vec_arg(t1); 4275 *a2 = tcgv_vec_arg(t2); 4276 cond = tcg_signed_cond(cond); 4277 } 4278 return cond; 4279} 4280 4281static void expand_vec_cmp(TCGType type, unsigned vece, TCGArg a0, 4282 TCGArg a1, TCGArg a2, TCGCond cond) 4283{ 4284 cond = expand_vec_cond(type, vece, &a1, &a2, cond); 4285 /* Expand directly; do not recurse. */ 4286 vec_gen_4(INDEX_op_cmp_vec, type, vece, a0, a1, a2, cond); 4287} 4288 4289static void expand_vec_cmpsel(TCGType type, unsigned vece, TCGArg a0, 4290 TCGArg a1, TCGArg a2, 4291 TCGArg a3, TCGArg a4, TCGCond cond) 4292{ 4293 cond = expand_vec_cond(type, vece, &a1, &a2, cond); 4294 /* Expand directly; do not recurse. */ 4295 vec_gen_6(INDEX_op_cmpsel_vec, type, vece, a0, a1, a2, a3, a4, cond); 4296} 4297 4298void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 4299 TCGArg a0, ...) 4300{ 4301 va_list va; 4302 TCGArg a1, a2, a3, a4, a5; 4303 TCGv_vec v0, v1, v2; 4304 4305 va_start(va, a0); 4306 a1 = va_arg(va, TCGArg); 4307 a2 = va_arg(va, TCGArg); 4308 v0 = temp_tcgv_vec(arg_temp(a0)); 4309 v1 = temp_tcgv_vec(arg_temp(a1)); 4310 4311 switch (opc) { 4312 case INDEX_op_shli_vec: 4313 expand_vec_shi(type, vece, false, v0, v1, a2); 4314 break; 4315 case INDEX_op_shri_vec: 4316 expand_vec_shi(type, vece, true, v0, v1, a2); 4317 break; 4318 case INDEX_op_sari_vec: 4319 expand_vec_sari(type, vece, v0, v1, a2); 4320 break; 4321 4322 case INDEX_op_rotli_vec: 4323 expand_vec_rotli(type, vece, v0, v1, a2); 4324 break; 4325 4326 case INDEX_op_rotls_vec: 4327 expand_vec_rotls(type, vece, v0, v1, temp_tcgv_i32(arg_temp(a2))); 4328 break; 4329 4330 case INDEX_op_rotlv_vec: 4331 v2 = temp_tcgv_vec(arg_temp(a2)); 4332 expand_vec_rotv(type, vece, v0, v1, v2, false); 4333 break; 4334 case INDEX_op_rotrv_vec: 4335 v2 = temp_tcgv_vec(arg_temp(a2)); 4336 expand_vec_rotv(type, vece, v0, v1, v2, true); 4337 break; 4338 4339 case INDEX_op_mul_vec: 4340 v2 = temp_tcgv_vec(arg_temp(a2)); 4341 expand_vec_mul(type, vece, v0, v1, v2); 4342 break; 4343 4344 case INDEX_op_cmp_vec: 4345 a3 = va_arg(va, TCGArg); 4346 expand_vec_cmp(type, vece, a0, a1, a2, a3); 4347 break; 4348 4349 case INDEX_op_cmpsel_vec: 4350 a3 = va_arg(va, TCGArg); 4351 a4 = va_arg(va, TCGArg); 4352 a5 = va_arg(va, TCGArg); 4353 expand_vec_cmpsel(type, vece, a0, a1, a2, a3, a4, a5); 4354 break; 4355 4356 default: 4357 break; 4358 } 4359 4360 va_end(va); 4361} 4362 4363static const int tcg_target_callee_save_regs[] = { 4364#if TCG_TARGET_REG_BITS == 64 4365 TCG_REG_RBP, 4366 TCG_REG_RBX, 4367#if defined(_WIN64) 4368 TCG_REG_RDI, 4369 TCG_REG_RSI, 4370#endif 4371 TCG_REG_R12, 4372 TCG_REG_R13, 4373 TCG_REG_R14, /* Currently used for the global env. */ 4374 TCG_REG_R15, 4375#else 4376 TCG_REG_EBP, /* Currently used for the global env. */ 4377 TCG_REG_EBX, 4378 TCG_REG_ESI, 4379 TCG_REG_EDI, 4380#endif 4381}; 4382 4383/* Compute frame size via macros, to share between tcg_target_qemu_prologue 4384 and tcg_register_jit. */ 4385 4386#define PUSH_SIZE \ 4387 ((1 + ARRAY_SIZE(tcg_target_callee_save_regs)) \ 4388 * (TCG_TARGET_REG_BITS / 8)) 4389 4390#define FRAME_SIZE \ 4391 ((PUSH_SIZE \ 4392 + TCG_STATIC_CALL_ARGS_SIZE \ 4393 + CPU_TEMP_BUF_NLONGS * sizeof(long) \ 4394 + TCG_TARGET_STACK_ALIGN - 1) \ 4395 & ~(TCG_TARGET_STACK_ALIGN - 1)) 4396 4397/* Generate global QEMU prologue and epilogue code */ 4398static void tcg_target_qemu_prologue(TCGContext *s) 4399{ 4400 int i, stack_addend; 4401 4402 /* TB prologue */ 4403 4404 /* Reserve some stack space, also for TCG temps. */ 4405 stack_addend = FRAME_SIZE - PUSH_SIZE; 4406 tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE, 4407 CPU_TEMP_BUF_NLONGS * sizeof(long)); 4408 4409 /* Save all callee saved registers. */ 4410 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 4411 tcg_out_push(s, tcg_target_callee_save_regs[i]); 4412 } 4413 4414 if (!tcg_use_softmmu && guest_base) { 4415 int seg = setup_guest_base_seg(); 4416 if (seg != 0) { 4417 x86_guest_base.seg = seg; 4418 } else if (guest_base == (int32_t)guest_base) { 4419 x86_guest_base.ofs = guest_base; 4420 } else { 4421 assert(TCG_TARGET_REG_BITS == 64); 4422 /* Choose R12 because, as a base, it requires a SIB byte. */ 4423 x86_guest_base.index = TCG_REG_R12; 4424 tcg_out_movi(s, TCG_TYPE_PTR, x86_guest_base.index, guest_base); 4425 tcg_regset_set_reg(s->reserved_regs, x86_guest_base.index); 4426 } 4427 } 4428 4429 if (TCG_TARGET_REG_BITS == 32) { 4430 tcg_out_ld(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, 4431 (ARRAY_SIZE(tcg_target_callee_save_regs) + 1) * 4); 4432 tcg_out_addi(s, TCG_REG_ESP, -stack_addend); 4433 /* jmp *tb. */ 4434 tcg_out_modrm_offset(s, OPC_GRP5, EXT5_JMPN_Ev, TCG_REG_ESP, 4435 (ARRAY_SIZE(tcg_target_callee_save_regs) + 2) * 4 4436 + stack_addend); 4437 } else { 4438 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 4439 tcg_out_addi(s, TCG_REG_ESP, -stack_addend); 4440 /* jmp *tb. */ 4441 tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, tcg_target_call_iarg_regs[1]); 4442 } 4443 4444 /* 4445 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 4446 * and fall through to the rest of the epilogue. 4447 */ 4448 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 4449 tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_EAX, 0); 4450 4451 /* TB epilogue */ 4452 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 4453 4454 tcg_out_addi(s, TCG_REG_CALL_STACK, stack_addend); 4455 4456 if (have_avx2) { 4457 tcg_out_vex_opc(s, OPC_VZEROUPPER, 0, 0, 0, 0); 4458 } 4459 for (i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) { 4460 tcg_out_pop(s, tcg_target_callee_save_regs[i]); 4461 } 4462 tcg_out_opc(s, OPC_RET, 0, 0, 0); 4463} 4464 4465static void tcg_out_tb_start(TCGContext *s) 4466{ 4467 /* nothing to do */ 4468} 4469 4470static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 4471{ 4472 memset(p, 0x90, count); 4473} 4474 4475static void tcg_target_init(TCGContext *s) 4476{ 4477 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS; 4478 if (TCG_TARGET_REG_BITS == 64) { 4479 tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS; 4480 } 4481 if (have_avx1) { 4482 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS; 4483 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS; 4484 } 4485 if (have_avx2) { 4486 tcg_target_available_regs[TCG_TYPE_V256] = ALL_VECTOR_REGS; 4487 } 4488 4489 tcg_target_call_clobber_regs = ALL_VECTOR_REGS; 4490 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_EAX); 4491 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_EDX); 4492 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_ECX); 4493 if (TCG_TARGET_REG_BITS == 64) { 4494#if !defined(_WIN64) 4495 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_RDI); 4496 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_RSI); 4497#endif 4498 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8); 4499 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9); 4500 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10); 4501 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11); 4502 } 4503 4504 s->reserved_regs = 0; 4505 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); 4506 tcg_regset_set_reg(s->reserved_regs, TCG_TMP_VEC); 4507#ifdef _WIN64 4508 /* These are call saved, and we don't save them, so don't use them. */ 4509 tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM6); 4510 tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM7); 4511 tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM8); 4512 tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM9); 4513 tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM10); 4514 tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM11); 4515 tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM12); 4516 tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM13); 4517 tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM14); 4518 tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM15); 4519#endif 4520} 4521 4522typedef struct { 4523 DebugFrameHeader h; 4524 uint8_t fde_def_cfa[4]; 4525 uint8_t fde_reg_ofs[14]; 4526} DebugFrame; 4527 4528/* We're expecting a 2 byte uleb128 encoded value. */ 4529QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); 4530 4531#if !defined(__ELF__) 4532 /* Host machine without ELF. */ 4533#elif TCG_TARGET_REG_BITS == 64 4534#define ELF_HOST_MACHINE EM_X86_64 4535static const DebugFrame debug_frame = { 4536 .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ 4537 .h.cie.id = -1, 4538 .h.cie.version = 1, 4539 .h.cie.code_align = 1, 4540 .h.cie.data_align = 0x78, /* sleb128 -8 */ 4541 .h.cie.return_column = 16, 4542 4543 /* Total FDE size does not include the "len" member. */ 4544 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 4545 4546 .fde_def_cfa = { 4547 12, 7, /* DW_CFA_def_cfa %rsp, ... */ 4548 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 4549 (FRAME_SIZE >> 7) 4550 }, 4551 .fde_reg_ofs = { 4552 0x90, 1, /* DW_CFA_offset, %rip, -8 */ 4553 /* The following ordering must match tcg_target_callee_save_regs. */ 4554 0x86, 2, /* DW_CFA_offset, %rbp, -16 */ 4555 0x83, 3, /* DW_CFA_offset, %rbx, -24 */ 4556 0x8c, 4, /* DW_CFA_offset, %r12, -32 */ 4557 0x8d, 5, /* DW_CFA_offset, %r13, -40 */ 4558 0x8e, 6, /* DW_CFA_offset, %r14, -48 */ 4559 0x8f, 7, /* DW_CFA_offset, %r15, -56 */ 4560 } 4561}; 4562#else 4563#define ELF_HOST_MACHINE EM_386 4564static const DebugFrame debug_frame = { 4565 .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ 4566 .h.cie.id = -1, 4567 .h.cie.version = 1, 4568 .h.cie.code_align = 1, 4569 .h.cie.data_align = 0x7c, /* sleb128 -4 */ 4570 .h.cie.return_column = 8, 4571 4572 /* Total FDE size does not include the "len" member. */ 4573 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 4574 4575 .fde_def_cfa = { 4576 12, 4, /* DW_CFA_def_cfa %esp, ... */ 4577 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 4578 (FRAME_SIZE >> 7) 4579 }, 4580 .fde_reg_ofs = { 4581 0x88, 1, /* DW_CFA_offset, %eip, -4 */ 4582 /* The following ordering must match tcg_target_callee_save_regs. */ 4583 0x85, 2, /* DW_CFA_offset, %ebp, -8 */ 4584 0x83, 3, /* DW_CFA_offset, %ebx, -12 */ 4585 0x86, 4, /* DW_CFA_offset, %esi, -16 */ 4586 0x87, 5, /* DW_CFA_offset, %edi, -20 */ 4587 } 4588}; 4589#endif 4590 4591#if defined(ELF_HOST_MACHINE) 4592void tcg_register_jit(const void *buf, size_t buf_size) 4593{ 4594 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 4595} 4596#endif 4597