1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25/* Used for function call generation. */ 26#define TCG_TARGET_STACK_ALIGN 16 27#if defined(_WIN64) 28#define TCG_TARGET_CALL_STACK_OFFSET 32 29#else 30#define TCG_TARGET_CALL_STACK_OFFSET 0 31#endif 32#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL 33#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL 34#if defined(_WIN64) 35# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_BY_REF 36# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_VEC 37#elif TCG_TARGET_REG_BITS == 64 38# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL 39# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL 40#else 41# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL 42# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF 43#endif 44 45#ifdef CONFIG_DEBUG_TCG 46static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 47#if TCG_TARGET_REG_BITS == 64 48 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", 49#else 50 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", 51#endif 52 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", 53 "%xmm0", "%xmm1", "%xmm2", "%xmm3", "%xmm4", "%xmm5", "%xmm6", "%xmm7", 54#if TCG_TARGET_REG_BITS == 64 55 "%xmm8", "%xmm9", "%xmm10", "%xmm11", 56 "%xmm12", "%xmm13", "%xmm14", "%xmm15", 57#endif 58}; 59#endif 60 61static const int tcg_target_reg_alloc_order[] = { 62#if TCG_TARGET_REG_BITS == 64 63 TCG_REG_RBP, 64 TCG_REG_RBX, 65 TCG_REG_R12, 66 TCG_REG_R13, 67 TCG_REG_R14, 68 TCG_REG_R15, 69 TCG_REG_R10, 70 TCG_REG_R11, 71 TCG_REG_R9, 72 TCG_REG_R8, 73 TCG_REG_RCX, 74 TCG_REG_RDX, 75 TCG_REG_RSI, 76 TCG_REG_RDI, 77 TCG_REG_RAX, 78#else 79 TCG_REG_EBX, 80 TCG_REG_ESI, 81 TCG_REG_EDI, 82 TCG_REG_EBP, 83 TCG_REG_ECX, 84 TCG_REG_EDX, 85 TCG_REG_EAX, 86#endif 87 TCG_REG_XMM0, 88 TCG_REG_XMM1, 89 TCG_REG_XMM2, 90 TCG_REG_XMM3, 91 TCG_REG_XMM4, 92 TCG_REG_XMM5, 93#ifndef _WIN64 94 /* The Win64 ABI has xmm6-xmm15 as caller-saves, and we do not save 95 any of them. Therefore only allow xmm0-xmm5 to be allocated. */ 96 TCG_REG_XMM6, 97 TCG_REG_XMM7, 98#if TCG_TARGET_REG_BITS == 64 99 TCG_REG_XMM8, 100 TCG_REG_XMM9, 101 TCG_REG_XMM10, 102 TCG_REG_XMM11, 103 TCG_REG_XMM12, 104 TCG_REG_XMM13, 105 TCG_REG_XMM14, 106 TCG_REG_XMM15, 107#endif 108#endif 109}; 110 111#define TCG_TMP_VEC TCG_REG_XMM5 112 113static const int tcg_target_call_iarg_regs[] = { 114#if TCG_TARGET_REG_BITS == 64 115#if defined(_WIN64) 116 TCG_REG_RCX, 117 TCG_REG_RDX, 118#else 119 TCG_REG_RDI, 120 TCG_REG_RSI, 121 TCG_REG_RDX, 122 TCG_REG_RCX, 123#endif 124 TCG_REG_R8, 125 TCG_REG_R9, 126#else 127 /* 32 bit mode uses stack based calling convention (GCC default). */ 128#endif 129}; 130 131static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 132{ 133 switch (kind) { 134 case TCG_CALL_RET_NORMAL: 135 tcg_debug_assert(slot >= 0 && slot <= 1); 136 return slot ? TCG_REG_EDX : TCG_REG_EAX; 137#ifdef _WIN64 138 case TCG_CALL_RET_BY_VEC: 139 tcg_debug_assert(slot == 0); 140 return TCG_REG_XMM0; 141#endif 142 default: 143 g_assert_not_reached(); 144 } 145} 146 147/* Constants we accept. */ 148#define TCG_CT_CONST_S32 0x100 149#define TCG_CT_CONST_U32 0x200 150#define TCG_CT_CONST_I32 0x400 151#define TCG_CT_CONST_WSZ 0x800 152#define TCG_CT_CONST_TST 0x1000 153#define TCG_CT_CONST_ZERO 0x2000 154 155/* Registers used with L constraint, which are the first argument 156 registers on x86_64, and two random call clobbered registers on 157 i386. */ 158#if TCG_TARGET_REG_BITS == 64 159# define TCG_REG_L0 tcg_target_call_iarg_regs[0] 160# define TCG_REG_L1 tcg_target_call_iarg_regs[1] 161#else 162# define TCG_REG_L0 TCG_REG_EAX 163# define TCG_REG_L1 TCG_REG_EDX 164#endif 165 166#if TCG_TARGET_REG_BITS == 64 167# define ALL_GENERAL_REGS 0x0000ffffu 168# define ALL_VECTOR_REGS 0xffff0000u 169# define ALL_BYTEL_REGS ALL_GENERAL_REGS 170#else 171# define ALL_GENERAL_REGS 0x000000ffu 172# define ALL_VECTOR_REGS 0x00ff0000u 173# define ALL_BYTEL_REGS 0x0000000fu 174#endif 175#define SOFTMMU_RESERVE_REGS \ 176 (tcg_use_softmmu ? (1 << TCG_REG_L0) | (1 << TCG_REG_L1) : 0) 177 178#define have_bmi2 (cpuinfo & CPUINFO_BMI2) 179#define have_lzcnt (cpuinfo & CPUINFO_LZCNT) 180 181static const tcg_insn_unit *tb_ret_addr; 182 183static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 184 intptr_t value, intptr_t addend) 185{ 186 value += addend; 187 switch(type) { 188 case R_386_PC32: 189 value -= (uintptr_t)tcg_splitwx_to_rx(code_ptr); 190 if (value != (int32_t)value) { 191 return false; 192 } 193 /* FALLTHRU */ 194 case R_386_32: 195 tcg_patch32(code_ptr, value); 196 break; 197 case R_386_PC8: 198 value -= (uintptr_t)tcg_splitwx_to_rx(code_ptr); 199 if (value != (int8_t)value) { 200 return false; 201 } 202 tcg_patch8(code_ptr, value); 203 break; 204 default: 205 g_assert_not_reached(); 206 } 207 return true; 208} 209 210/* test if a constant matches the constraint */ 211static bool tcg_target_const_match(int64_t val, int ct, 212 TCGType type, TCGCond cond, int vece) 213{ 214 if (ct & TCG_CT_CONST) { 215 return 1; 216 } 217 if (type == TCG_TYPE_I32) { 218 if (ct & (TCG_CT_CONST_S32 | TCG_CT_CONST_U32 | 219 TCG_CT_CONST_I32 | TCG_CT_CONST_TST)) { 220 return 1; 221 } 222 } else { 223 if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) { 224 return 1; 225 } 226 if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) { 227 return 1; 228 } 229 if ((ct & TCG_CT_CONST_I32) && ~val == (int32_t)~val) { 230 return 1; 231 } 232 /* 233 * This will be used in combination with TCG_CT_CONST_S32, 234 * so "normal" TESTQ is already matched. Also accept: 235 * TESTQ -> TESTL (uint32_t) 236 * TESTQ -> BT (is_power_of_2) 237 */ 238 if ((ct & TCG_CT_CONST_TST) 239 && is_tst_cond(cond) 240 && (val == (uint32_t)val || is_power_of_2(val))) { 241 return 1; 242 } 243 } 244 if ((ct & TCG_CT_CONST_WSZ) && val == (type == TCG_TYPE_I32 ? 32 : 64)) { 245 return 1; 246 } 247 if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 248 return 1; 249 } 250 return 0; 251} 252 253# define LOWREGMASK(x) ((x) & 7) 254 255#define P_EXT 0x100 /* 0x0f opcode prefix */ 256#define P_EXT38 0x200 /* 0x0f 0x38 opcode prefix */ 257#define P_DATA16 0x400 /* 0x66 opcode prefix */ 258#define P_VEXW 0x1000 /* Set VEX.W = 1 */ 259#if TCG_TARGET_REG_BITS == 64 260# define P_REXW P_VEXW /* Set REX.W = 1; match VEXW */ 261# define P_REXB_R 0x2000 /* REG field as byte register */ 262# define P_REXB_RM 0x4000 /* R/M field as byte register */ 263# define P_GS 0x8000 /* gs segment override */ 264#else 265# define P_REXW 0 266# define P_REXB_R 0 267# define P_REXB_RM 0 268# define P_GS 0 269#endif 270#define P_EXT3A 0x10000 /* 0x0f 0x3a opcode prefix */ 271#define P_SIMDF3 0x20000 /* 0xf3 opcode prefix */ 272#define P_SIMDF2 0x40000 /* 0xf2 opcode prefix */ 273#define P_VEXL 0x80000 /* Set VEX.L = 1 */ 274#define P_EVEX 0x100000 /* Requires EVEX encoding */ 275 276#define OPC_ARITH_EbIb (0x80) 277#define OPC_ARITH_EvIz (0x81) 278#define OPC_ARITH_EvIb (0x83) 279#define OPC_ARITH_GvEv (0x03) /* ... plus (ARITH_FOO << 3) */ 280#define OPC_ANDN (0xf2 | P_EXT38) 281#define OPC_ADD_GvEv (OPC_ARITH_GvEv | (ARITH_ADD << 3)) 282#define OPC_AND_GvEv (OPC_ARITH_GvEv | (ARITH_AND << 3)) 283#define OPC_BLENDPS (0x0c | P_EXT3A | P_DATA16) 284#define OPC_BSF (0xbc | P_EXT) 285#define OPC_BSR (0xbd | P_EXT) 286#define OPC_BSWAP (0xc8 | P_EXT) 287#define OPC_CALL_Jz (0xe8) 288#define OPC_CMOVCC (0x40 | P_EXT) /* ... plus condition code */ 289#define OPC_CMP_GvEv (OPC_ARITH_GvEv | (ARITH_CMP << 3)) 290#define OPC_DEC_r32 (0x48) 291#define OPC_IMUL_GvEv (0xaf | P_EXT) 292#define OPC_IMUL_GvEvIb (0x6b) 293#define OPC_IMUL_GvEvIz (0x69) 294#define OPC_INC_r32 (0x40) 295#define OPC_JCC_long (0x80 | P_EXT) /* ... plus condition code */ 296#define OPC_JCC_short (0x70) /* ... plus condition code */ 297#define OPC_JMP_long (0xe9) 298#define OPC_JMP_short (0xeb) 299#define OPC_LEA (0x8d) 300#define OPC_LZCNT (0xbd | P_EXT | P_SIMDF3) 301#define OPC_MOVB_EvGv (0x88) /* stores, more or less */ 302#define OPC_MOVL_EvGv (0x89) /* stores, more or less */ 303#define OPC_MOVL_GvEv (0x8b) /* loads, more or less */ 304#define OPC_MOVB_EvIz (0xc6) 305#define OPC_MOVL_EvIz (0xc7) 306#define OPC_MOVB_Ib (0xb0) 307#define OPC_MOVL_Iv (0xb8) 308#define OPC_MOVBE_GyMy (0xf0 | P_EXT38) 309#define OPC_MOVBE_MyGy (0xf1 | P_EXT38) 310#define OPC_MOVD_VyEy (0x6e | P_EXT | P_DATA16) 311#define OPC_MOVD_EyVy (0x7e | P_EXT | P_DATA16) 312#define OPC_MOVDDUP (0x12 | P_EXT | P_SIMDF2) 313#define OPC_MOVDQA_VxWx (0x6f | P_EXT | P_DATA16) 314#define OPC_MOVDQA_WxVx (0x7f | P_EXT | P_DATA16) 315#define OPC_MOVDQU_VxWx (0x6f | P_EXT | P_SIMDF3) 316#define OPC_MOVDQU_WxVx (0x7f | P_EXT | P_SIMDF3) 317#define OPC_MOVQ_VqWq (0x7e | P_EXT | P_SIMDF3) 318#define OPC_MOVQ_WqVq (0xd6 | P_EXT | P_DATA16) 319#define OPC_MOVSBL (0xbe | P_EXT) 320#define OPC_MOVSWL (0xbf | P_EXT) 321#define OPC_MOVSLQ (0x63 | P_REXW) 322#define OPC_MOVZBL (0xb6 | P_EXT) 323#define OPC_MOVZWL (0xb7 | P_EXT) 324#define OPC_PABSB (0x1c | P_EXT38 | P_DATA16) 325#define OPC_PABSW (0x1d | P_EXT38 | P_DATA16) 326#define OPC_PABSD (0x1e | P_EXT38 | P_DATA16) 327#define OPC_VPABSQ (0x1f | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 328#define OPC_PACKSSDW (0x6b | P_EXT | P_DATA16) 329#define OPC_PACKSSWB (0x63 | P_EXT | P_DATA16) 330#define OPC_PACKUSDW (0x2b | P_EXT38 | P_DATA16) 331#define OPC_PACKUSWB (0x67 | P_EXT | P_DATA16) 332#define OPC_PADDB (0xfc | P_EXT | P_DATA16) 333#define OPC_PADDW (0xfd | P_EXT | P_DATA16) 334#define OPC_PADDD (0xfe | P_EXT | P_DATA16) 335#define OPC_PADDQ (0xd4 | P_EXT | P_DATA16) 336#define OPC_PADDSB (0xec | P_EXT | P_DATA16) 337#define OPC_PADDSW (0xed | P_EXT | P_DATA16) 338#define OPC_PADDUB (0xdc | P_EXT | P_DATA16) 339#define OPC_PADDUW (0xdd | P_EXT | P_DATA16) 340#define OPC_PAND (0xdb | P_EXT | P_DATA16) 341#define OPC_PANDN (0xdf | P_EXT | P_DATA16) 342#define OPC_PBLENDW (0x0e | P_EXT3A | P_DATA16) 343#define OPC_PCMPEQB (0x74 | P_EXT | P_DATA16) 344#define OPC_PCMPEQW (0x75 | P_EXT | P_DATA16) 345#define OPC_PCMPEQD (0x76 | P_EXT | P_DATA16) 346#define OPC_PCMPEQQ (0x29 | P_EXT38 | P_DATA16) 347#define OPC_PCMPGTB (0x64 | P_EXT | P_DATA16) 348#define OPC_PCMPGTW (0x65 | P_EXT | P_DATA16) 349#define OPC_PCMPGTD (0x66 | P_EXT | P_DATA16) 350#define OPC_PCMPGTQ (0x37 | P_EXT38 | P_DATA16) 351#define OPC_PEXTRD (0x16 | P_EXT3A | P_DATA16) 352#define OPC_PINSRD (0x22 | P_EXT3A | P_DATA16) 353#define OPC_PMAXSB (0x3c | P_EXT38 | P_DATA16) 354#define OPC_PMAXSW (0xee | P_EXT | P_DATA16) 355#define OPC_PMAXSD (0x3d | P_EXT38 | P_DATA16) 356#define OPC_VPMAXSQ (0x3d | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 357#define OPC_PMAXUB (0xde | P_EXT | P_DATA16) 358#define OPC_PMAXUW (0x3e | P_EXT38 | P_DATA16) 359#define OPC_PMAXUD (0x3f | P_EXT38 | P_DATA16) 360#define OPC_VPMAXUQ (0x3f | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 361#define OPC_PMINSB (0x38 | P_EXT38 | P_DATA16) 362#define OPC_PMINSW (0xea | P_EXT | P_DATA16) 363#define OPC_PMINSD (0x39 | P_EXT38 | P_DATA16) 364#define OPC_VPMINSQ (0x39 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 365#define OPC_PMINUB (0xda | P_EXT | P_DATA16) 366#define OPC_PMINUW (0x3a | P_EXT38 | P_DATA16) 367#define OPC_PMINUD (0x3b | P_EXT38 | P_DATA16) 368#define OPC_VPMINUQ (0x3b | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 369#define OPC_PMOVSXBW (0x20 | P_EXT38 | P_DATA16) 370#define OPC_PMOVSXWD (0x23 | P_EXT38 | P_DATA16) 371#define OPC_PMOVSXDQ (0x25 | P_EXT38 | P_DATA16) 372#define OPC_PMOVZXBW (0x30 | P_EXT38 | P_DATA16) 373#define OPC_PMOVZXWD (0x33 | P_EXT38 | P_DATA16) 374#define OPC_PMOVZXDQ (0x35 | P_EXT38 | P_DATA16) 375#define OPC_PMULLW (0xd5 | P_EXT | P_DATA16) 376#define OPC_PMULLD (0x40 | P_EXT38 | P_DATA16) 377#define OPC_VPMULLQ (0x40 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 378#define OPC_POR (0xeb | P_EXT | P_DATA16) 379#define OPC_PSHUFB (0x00 | P_EXT38 | P_DATA16) 380#define OPC_PSHUFD (0x70 | P_EXT | P_DATA16) 381#define OPC_PSHUFLW (0x70 | P_EXT | P_SIMDF2) 382#define OPC_PSHUFHW (0x70 | P_EXT | P_SIMDF3) 383#define OPC_PSHIFTW_Ib (0x71 | P_EXT | P_DATA16) /* /2 /6 /4 */ 384#define OPC_PSHIFTD_Ib (0x72 | P_EXT | P_DATA16) /* /1 /2 /6 /4 */ 385#define OPC_PSHIFTQ_Ib (0x73 | P_EXT | P_DATA16) /* /2 /6 /4 */ 386#define OPC_PSLLW (0xf1 | P_EXT | P_DATA16) 387#define OPC_PSLLD (0xf2 | P_EXT | P_DATA16) 388#define OPC_PSLLQ (0xf3 | P_EXT | P_DATA16) 389#define OPC_PSRAW (0xe1 | P_EXT | P_DATA16) 390#define OPC_PSRAD (0xe2 | P_EXT | P_DATA16) 391#define OPC_VPSRAQ (0xe2 | P_EXT | P_DATA16 | P_VEXW | P_EVEX) 392#define OPC_PSRLW (0xd1 | P_EXT | P_DATA16) 393#define OPC_PSRLD (0xd2 | P_EXT | P_DATA16) 394#define OPC_PSRLQ (0xd3 | P_EXT | P_DATA16) 395#define OPC_PSUBB (0xf8 | P_EXT | P_DATA16) 396#define OPC_PSUBW (0xf9 | P_EXT | P_DATA16) 397#define OPC_PSUBD (0xfa | P_EXT | P_DATA16) 398#define OPC_PSUBQ (0xfb | P_EXT | P_DATA16) 399#define OPC_PSUBSB (0xe8 | P_EXT | P_DATA16) 400#define OPC_PSUBSW (0xe9 | P_EXT | P_DATA16) 401#define OPC_PSUBUB (0xd8 | P_EXT | P_DATA16) 402#define OPC_PSUBUW (0xd9 | P_EXT | P_DATA16) 403#define OPC_PUNPCKLBW (0x60 | P_EXT | P_DATA16) 404#define OPC_PUNPCKLWD (0x61 | P_EXT | P_DATA16) 405#define OPC_PUNPCKLDQ (0x62 | P_EXT | P_DATA16) 406#define OPC_PUNPCKLQDQ (0x6c | P_EXT | P_DATA16) 407#define OPC_PUNPCKHBW (0x68 | P_EXT | P_DATA16) 408#define OPC_PUNPCKHWD (0x69 | P_EXT | P_DATA16) 409#define OPC_PUNPCKHDQ (0x6a | P_EXT | P_DATA16) 410#define OPC_PUNPCKHQDQ (0x6d | P_EXT | P_DATA16) 411#define OPC_PXOR (0xef | P_EXT | P_DATA16) 412#define OPC_POP_r32 (0x58) 413#define OPC_POPCNT (0xb8 | P_EXT | P_SIMDF3) 414#define OPC_PUSH_r32 (0x50) 415#define OPC_PUSH_Iv (0x68) 416#define OPC_PUSH_Ib (0x6a) 417#define OPC_RET (0xc3) 418#define OPC_SETCC (0x90 | P_EXT | P_REXB_RM) /* ... plus cc */ 419#define OPC_SHIFT_1 (0xd1) 420#define OPC_SHIFT_Ib (0xc1) 421#define OPC_SHIFT_cl (0xd3) 422#define OPC_SARX (0xf7 | P_EXT38 | P_SIMDF3) 423#define OPC_SHUFPS (0xc6 | P_EXT) 424#define OPC_SHLX (0xf7 | P_EXT38 | P_DATA16) 425#define OPC_SHRX (0xf7 | P_EXT38 | P_SIMDF2) 426#define OPC_SHRD_Ib (0xac | P_EXT) 427#define OPC_TESTB (0x84) 428#define OPC_TESTL (0x85) 429#define OPC_TZCNT (0xbc | P_EXT | P_SIMDF3) 430#define OPC_UD2 (0x0b | P_EXT) 431#define OPC_VPBLENDD (0x02 | P_EXT3A | P_DATA16) 432#define OPC_VPBLENDVB (0x4c | P_EXT3A | P_DATA16) 433#define OPC_VPBLENDMB (0x66 | P_EXT38 | P_DATA16 | P_EVEX) 434#define OPC_VPBLENDMW (0x66 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 435#define OPC_VPBLENDMD (0x64 | P_EXT38 | P_DATA16 | P_EVEX) 436#define OPC_VPBLENDMQ (0x64 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 437#define OPC_VPCMPB (0x3f | P_EXT3A | P_DATA16 | P_EVEX) 438#define OPC_VPCMPUB (0x3e | P_EXT3A | P_DATA16 | P_EVEX) 439#define OPC_VPCMPW (0x3f | P_EXT3A | P_DATA16 | P_VEXW | P_EVEX) 440#define OPC_VPCMPUW (0x3e | P_EXT3A | P_DATA16 | P_VEXW | P_EVEX) 441#define OPC_VPCMPD (0x1f | P_EXT3A | P_DATA16 | P_EVEX) 442#define OPC_VPCMPUD (0x1e | P_EXT3A | P_DATA16 | P_EVEX) 443#define OPC_VPCMPQ (0x1f | P_EXT3A | P_DATA16 | P_VEXW | P_EVEX) 444#define OPC_VPCMPUQ (0x1e | P_EXT3A | P_DATA16 | P_VEXW | P_EVEX) 445#define OPC_VPINSRB (0x20 | P_EXT3A | P_DATA16) 446#define OPC_VPINSRW (0xc4 | P_EXT | P_DATA16) 447#define OPC_VBROADCASTSS (0x18 | P_EXT38 | P_DATA16) 448#define OPC_VBROADCASTSD (0x19 | P_EXT38 | P_DATA16) 449#define OPC_VPBROADCASTB (0x78 | P_EXT38 | P_DATA16) 450#define OPC_VPBROADCASTW (0x79 | P_EXT38 | P_DATA16) 451#define OPC_VPBROADCASTD (0x58 | P_EXT38 | P_DATA16) 452#define OPC_VPBROADCASTQ (0x59 | P_EXT38 | P_DATA16) 453#define OPC_VPMOVM2B (0x28 | P_EXT38 | P_SIMDF3 | P_EVEX) 454#define OPC_VPMOVM2W (0x28 | P_EXT38 | P_SIMDF3 | P_VEXW | P_EVEX) 455#define OPC_VPMOVM2D (0x38 | P_EXT38 | P_SIMDF3 | P_EVEX) 456#define OPC_VPMOVM2Q (0x38 | P_EXT38 | P_SIMDF3 | P_VEXW | P_EVEX) 457#define OPC_VPERMQ (0x00 | P_EXT3A | P_DATA16 | P_VEXW) 458#define OPC_VPERM2I128 (0x46 | P_EXT3A | P_DATA16 | P_VEXL) 459#define OPC_VPROLVD (0x15 | P_EXT38 | P_DATA16 | P_EVEX) 460#define OPC_VPROLVQ (0x15 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 461#define OPC_VPRORVD (0x14 | P_EXT38 | P_DATA16 | P_EVEX) 462#define OPC_VPRORVQ (0x14 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 463#define OPC_VPSHLDW (0x70 | P_EXT3A | P_DATA16 | P_VEXW | P_EVEX) 464#define OPC_VPSHLDD (0x71 | P_EXT3A | P_DATA16 | P_EVEX) 465#define OPC_VPSHLDQ (0x71 | P_EXT3A | P_DATA16 | P_VEXW | P_EVEX) 466#define OPC_VPSHLDVW (0x70 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 467#define OPC_VPSHLDVD (0x71 | P_EXT38 | P_DATA16 | P_EVEX) 468#define OPC_VPSHLDVQ (0x71 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 469#define OPC_VPSHRDVW (0x72 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 470#define OPC_VPSHRDVD (0x73 | P_EXT38 | P_DATA16 | P_EVEX) 471#define OPC_VPSHRDVQ (0x73 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 472#define OPC_VPSLLVW (0x12 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 473#define OPC_VPSLLVD (0x47 | P_EXT38 | P_DATA16) 474#define OPC_VPSLLVQ (0x47 | P_EXT38 | P_DATA16 | P_VEXW) 475#define OPC_VPSRAVW (0x11 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 476#define OPC_VPSRAVD (0x46 | P_EXT38 | P_DATA16) 477#define OPC_VPSRAVQ (0x46 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 478#define OPC_VPSRLVW (0x10 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 479#define OPC_VPSRLVD (0x45 | P_EXT38 | P_DATA16) 480#define OPC_VPSRLVQ (0x45 | P_EXT38 | P_DATA16 | P_VEXW) 481#define OPC_VPTERNLOGQ (0x25 | P_EXT3A | P_DATA16 | P_VEXW | P_EVEX) 482#define OPC_VPTESTMB (0x26 | P_EXT38 | P_DATA16 | P_EVEX) 483#define OPC_VPTESTMW (0x26 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 484#define OPC_VPTESTMD (0x27 | P_EXT38 | P_DATA16 | P_EVEX) 485#define OPC_VPTESTMQ (0x27 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) 486#define OPC_VPTESTNMB (0x26 | P_EXT38 | P_SIMDF3 | P_EVEX) 487#define OPC_VPTESTNMW (0x26 | P_EXT38 | P_SIMDF3 | P_VEXW | P_EVEX) 488#define OPC_VPTESTNMD (0x27 | P_EXT38 | P_SIMDF3 | P_EVEX) 489#define OPC_VPTESTNMQ (0x27 | P_EXT38 | P_SIMDF3 | P_VEXW | P_EVEX) 490#define OPC_VZEROUPPER (0x77 | P_EXT) 491#define OPC_XCHG_ax_r32 (0x90) 492#define OPC_XCHG_EvGv (0x87) 493 494#define OPC_GRP3_Eb (0xf6) 495#define OPC_GRP3_Ev (0xf7) 496#define OPC_GRP5 (0xff) 497#define OPC_GRP14 (0x73 | P_EXT | P_DATA16) 498#define OPC_GRPBT (0xba | P_EXT) 499 500#define OPC_GRPBT_BT 4 501#define OPC_GRPBT_BTS 5 502#define OPC_GRPBT_BTR 6 503#define OPC_GRPBT_BTC 7 504 505/* Group 1 opcode extensions for 0x80-0x83. 506 These are also used as modifiers for OPC_ARITH. */ 507#define ARITH_ADD 0 508#define ARITH_OR 1 509#define ARITH_ADC 2 510#define ARITH_SBB 3 511#define ARITH_AND 4 512#define ARITH_SUB 5 513#define ARITH_XOR 6 514#define ARITH_CMP 7 515 516/* Group 2 opcode extensions for 0xc0, 0xc1, 0xd0-0xd3. */ 517#define SHIFT_ROL 0 518#define SHIFT_ROR 1 519#define SHIFT_SHL 4 520#define SHIFT_SHR 5 521#define SHIFT_SAR 7 522 523/* Group 3 opcode extensions for 0xf6, 0xf7. To be used with OPC_GRP3. */ 524#define EXT3_TESTi 0 525#define EXT3_NOT 2 526#define EXT3_NEG 3 527#define EXT3_MUL 4 528#define EXT3_IMUL 5 529#define EXT3_DIV 6 530#define EXT3_IDIV 7 531 532/* Group 5 opcode extensions for 0xff. To be used with OPC_GRP5. */ 533#define EXT5_INC_Ev 0 534#define EXT5_DEC_Ev 1 535#define EXT5_CALLN_Ev 2 536#define EXT5_JMPN_Ev 4 537 538/* Condition codes to be added to OPC_JCC_{long,short}. */ 539#define JCC_JMP (-1) 540#define JCC_JO 0x0 541#define JCC_JNO 0x1 542#define JCC_JB 0x2 543#define JCC_JAE 0x3 544#define JCC_JE 0x4 545#define JCC_JNE 0x5 546#define JCC_JBE 0x6 547#define JCC_JA 0x7 548#define JCC_JS 0x8 549#define JCC_JNS 0x9 550#define JCC_JP 0xa 551#define JCC_JNP 0xb 552#define JCC_JL 0xc 553#define JCC_JGE 0xd 554#define JCC_JLE 0xe 555#define JCC_JG 0xf 556 557static const uint8_t tcg_cond_to_jcc[] = { 558 [TCG_COND_EQ] = JCC_JE, 559 [TCG_COND_NE] = JCC_JNE, 560 [TCG_COND_LT] = JCC_JL, 561 [TCG_COND_GE] = JCC_JGE, 562 [TCG_COND_LE] = JCC_JLE, 563 [TCG_COND_GT] = JCC_JG, 564 [TCG_COND_LTU] = JCC_JB, 565 [TCG_COND_GEU] = JCC_JAE, 566 [TCG_COND_LEU] = JCC_JBE, 567 [TCG_COND_GTU] = JCC_JA, 568 [TCG_COND_TSTEQ] = JCC_JE, 569 [TCG_COND_TSTNE] = JCC_JNE, 570}; 571 572#if TCG_TARGET_REG_BITS == 64 573static void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x) 574{ 575 int rex; 576 577 if (opc & P_GS) { 578 tcg_out8(s, 0x65); 579 } 580 if (opc & P_DATA16) { 581 /* We should never be asking for both 16 and 64-bit operation. */ 582 tcg_debug_assert((opc & P_REXW) == 0); 583 tcg_out8(s, 0x66); 584 } 585 if (opc & P_SIMDF3) { 586 tcg_out8(s, 0xf3); 587 } else if (opc & P_SIMDF2) { 588 tcg_out8(s, 0xf2); 589 } 590 591 rex = 0; 592 rex |= (opc & P_REXW) ? 0x8 : 0x0; /* REX.W */ 593 rex |= (r & 8) >> 1; /* REX.R */ 594 rex |= (x & 8) >> 2; /* REX.X */ 595 rex |= (rm & 8) >> 3; /* REX.B */ 596 597 /* P_REXB_{R,RM} indicates that the given register is the low byte. 598 For %[abcd]l we need no REX prefix, but for %{si,di,bp,sp}l we do, 599 as otherwise the encoding indicates %[abcd]h. Note that the values 600 that are ORed in merely indicate that the REX byte must be present; 601 those bits get discarded in output. */ 602 rex |= opc & (r >= 4 ? P_REXB_R : 0); 603 rex |= opc & (rm >= 4 ? P_REXB_RM : 0); 604 605 if (rex) { 606 tcg_out8(s, (uint8_t)(rex | 0x40)); 607 } 608 609 if (opc & (P_EXT | P_EXT38 | P_EXT3A)) { 610 tcg_out8(s, 0x0f); 611 if (opc & P_EXT38) { 612 tcg_out8(s, 0x38); 613 } else if (opc & P_EXT3A) { 614 tcg_out8(s, 0x3a); 615 } 616 } 617 618 tcg_out8(s, opc); 619} 620#else 621static void tcg_out_opc(TCGContext *s, int opc) 622{ 623 if (opc & P_DATA16) { 624 tcg_out8(s, 0x66); 625 } 626 if (opc & P_SIMDF3) { 627 tcg_out8(s, 0xf3); 628 } else if (opc & P_SIMDF2) { 629 tcg_out8(s, 0xf2); 630 } 631 if (opc & (P_EXT | P_EXT38 | P_EXT3A)) { 632 tcg_out8(s, 0x0f); 633 if (opc & P_EXT38) { 634 tcg_out8(s, 0x38); 635 } else if (opc & P_EXT3A) { 636 tcg_out8(s, 0x3a); 637 } 638 } 639 tcg_out8(s, opc); 640} 641/* Discard the register arguments to tcg_out_opc early, so as not to penalize 642 the 32-bit compilation paths. This method works with all versions of gcc, 643 whereas relying on optimization may not be able to exclude them. */ 644#define tcg_out_opc(s, opc, r, rm, x) (tcg_out_opc)(s, opc) 645#endif 646 647static void tcg_out_modrm(TCGContext *s, int opc, int r, int rm) 648{ 649 tcg_out_opc(s, opc, r, rm, 0); 650 tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm)); 651} 652 653static void tcg_out_vex_opc(TCGContext *s, int opc, int r, int v, 654 int rm, int index) 655{ 656 int tmp; 657 658 if (opc & P_GS) { 659 tcg_out8(s, 0x65); 660 } 661 /* Use the two byte form if possible, which cannot encode 662 VEX.W, VEX.B, VEX.X, or an m-mmmm field other than P_EXT. */ 663 if ((opc & (P_EXT | P_EXT38 | P_EXT3A | P_VEXW)) == P_EXT 664 && ((rm | index) & 8) == 0) { 665 /* Two byte VEX prefix. */ 666 tcg_out8(s, 0xc5); 667 668 tmp = (r & 8 ? 0 : 0x80); /* VEX.R */ 669 } else { 670 /* Three byte VEX prefix. */ 671 tcg_out8(s, 0xc4); 672 673 /* VEX.m-mmmm */ 674 if (opc & P_EXT3A) { 675 tmp = 3; 676 } else if (opc & P_EXT38) { 677 tmp = 2; 678 } else if (opc & P_EXT) { 679 tmp = 1; 680 } else { 681 g_assert_not_reached(); 682 } 683 tmp |= (r & 8 ? 0 : 0x80); /* VEX.R */ 684 tmp |= (index & 8 ? 0 : 0x40); /* VEX.X */ 685 tmp |= (rm & 8 ? 0 : 0x20); /* VEX.B */ 686 tcg_out8(s, tmp); 687 688 tmp = (opc & P_VEXW ? 0x80 : 0); /* VEX.W */ 689 } 690 691 tmp |= (opc & P_VEXL ? 0x04 : 0); /* VEX.L */ 692 /* VEX.pp */ 693 if (opc & P_DATA16) { 694 tmp |= 1; /* 0x66 */ 695 } else if (opc & P_SIMDF3) { 696 tmp |= 2; /* 0xf3 */ 697 } else if (opc & P_SIMDF2) { 698 tmp |= 3; /* 0xf2 */ 699 } 700 tmp |= (~v & 15) << 3; /* VEX.vvvv */ 701 tcg_out8(s, tmp); 702 tcg_out8(s, opc); 703} 704 705static void tcg_out_evex_opc(TCGContext *s, int opc, int r, int v, 706 int rm, int index, int aaa, bool z) 707{ 708 /* The entire 4-byte evex prefix; with R' and V' set. */ 709 uint32_t p = 0x08041062; 710 int mm, pp; 711 712 tcg_debug_assert(have_avx512vl); 713 714 /* EVEX.mm */ 715 if (opc & P_EXT3A) { 716 mm = 3; 717 } else if (opc & P_EXT38) { 718 mm = 2; 719 } else if (opc & P_EXT) { 720 mm = 1; 721 } else { 722 g_assert_not_reached(); 723 } 724 725 /* EVEX.pp */ 726 if (opc & P_DATA16) { 727 pp = 1; /* 0x66 */ 728 } else if (opc & P_SIMDF3) { 729 pp = 2; /* 0xf3 */ 730 } else if (opc & P_SIMDF2) { 731 pp = 3; /* 0xf2 */ 732 } else { 733 pp = 0; 734 } 735 736 p = deposit32(p, 8, 2, mm); 737 p = deposit32(p, 13, 1, (rm & 8) == 0); /* EVEX.RXB.B */ 738 p = deposit32(p, 14, 1, (index & 8) == 0); /* EVEX.RXB.X */ 739 p = deposit32(p, 15, 1, (r & 8) == 0); /* EVEX.RXB.R */ 740 p = deposit32(p, 16, 2, pp); 741 p = deposit32(p, 19, 4, ~v); 742 p = deposit32(p, 23, 1, (opc & P_VEXW) != 0); 743 p = deposit32(p, 24, 3, aaa); 744 p = deposit32(p, 29, 2, (opc & P_VEXL) != 0); 745 p = deposit32(p, 31, 1, z); 746 747 tcg_out32(s, p); 748 tcg_out8(s, opc); 749} 750 751static void tcg_out_vex_modrm(TCGContext *s, int opc, int r, int v, int rm) 752{ 753 if (opc & P_EVEX) { 754 tcg_out_evex_opc(s, opc, r, v, rm, 0, 0, false); 755 } else { 756 tcg_out_vex_opc(s, opc, r, v, rm, 0); 757 } 758 tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm)); 759} 760 761static void tcg_out_vex_modrm_type(TCGContext *s, int opc, 762 int r, int v, int rm, TCGType type) 763{ 764 if (type == TCG_TYPE_V256) { 765 opc |= P_VEXL; 766 } 767 tcg_out_vex_modrm(s, opc, r, v, rm); 768} 769 770static void tcg_out_evex_modrm_type(TCGContext *s, int opc, int r, int v, 771 int rm, int aaa, bool z, TCGType type) 772{ 773 if (type == TCG_TYPE_V256) { 774 opc |= P_VEXL; 775 } 776 tcg_out_evex_opc(s, opc, r, v, rm, 0, aaa, z); 777 tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm)); 778} 779 780/* Output an opcode with a full "rm + (index<<shift) + offset" address mode. 781 We handle either RM and INDEX missing with a negative value. In 64-bit 782 mode for absolute addresses, ~RM is the size of the immediate operand 783 that will follow the instruction. */ 784 785static void tcg_out_sib_offset(TCGContext *s, int r, int rm, int index, 786 int shift, intptr_t offset) 787{ 788 int mod, len; 789 790 if (index < 0 && rm < 0) { 791 if (TCG_TARGET_REG_BITS == 64) { 792 /* Try for a rip-relative addressing mode. This has replaced 793 the 32-bit-mode absolute addressing encoding. */ 794 intptr_t pc = (intptr_t)s->code_ptr + 5 + ~rm; 795 intptr_t disp = offset - pc; 796 if (disp == (int32_t)disp) { 797 tcg_out8(s, (LOWREGMASK(r) << 3) | 5); 798 tcg_out32(s, disp); 799 return; 800 } 801 802 /* Try for an absolute address encoding. This requires the 803 use of the MODRM+SIB encoding and is therefore larger than 804 rip-relative addressing. */ 805 if (offset == (int32_t)offset) { 806 tcg_out8(s, (LOWREGMASK(r) << 3) | 4); 807 tcg_out8(s, (4 << 3) | 5); 808 tcg_out32(s, offset); 809 return; 810 } 811 812 /* ??? The memory isn't directly addressable. */ 813 g_assert_not_reached(); 814 } else { 815 /* Absolute address. */ 816 tcg_out8(s, (r << 3) | 5); 817 tcg_out32(s, offset); 818 return; 819 } 820 } 821 822 /* Find the length of the immediate addend. Note that the encoding 823 that would be used for (%ebp) indicates absolute addressing. */ 824 if (rm < 0) { 825 mod = 0, len = 4, rm = 5; 826 } else if (offset == 0 && LOWREGMASK(rm) != TCG_REG_EBP) { 827 mod = 0, len = 0; 828 } else if (offset == (int8_t)offset) { 829 mod = 0x40, len = 1; 830 } else { 831 mod = 0x80, len = 4; 832 } 833 834 /* Use a single byte MODRM format if possible. Note that the encoding 835 that would be used for %esp is the escape to the two byte form. */ 836 if (index < 0 && LOWREGMASK(rm) != TCG_REG_ESP) { 837 /* Single byte MODRM format. */ 838 tcg_out8(s, mod | (LOWREGMASK(r) << 3) | LOWREGMASK(rm)); 839 } else { 840 /* Two byte MODRM+SIB format. */ 841 842 /* Note that the encoding that would place %esp into the index 843 field indicates no index register. In 64-bit mode, the REX.X 844 bit counts, so %r12 can be used as the index. */ 845 if (index < 0) { 846 index = 4; 847 } else { 848 tcg_debug_assert(index != TCG_REG_ESP); 849 } 850 851 tcg_out8(s, mod | (LOWREGMASK(r) << 3) | 4); 852 tcg_out8(s, (shift << 6) | (LOWREGMASK(index) << 3) | LOWREGMASK(rm)); 853 } 854 855 if (len == 1) { 856 tcg_out8(s, offset); 857 } else if (len == 4) { 858 tcg_out32(s, offset); 859 } 860} 861 862static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm, 863 int index, int shift, intptr_t offset) 864{ 865 tcg_out_opc(s, opc, r, rm < 0 ? 0 : rm, index < 0 ? 0 : index); 866 tcg_out_sib_offset(s, r, rm, index, shift, offset); 867} 868 869static void tcg_out_vex_modrm_sib_offset(TCGContext *s, int opc, int r, int v, 870 int rm, int index, int shift, 871 intptr_t offset) 872{ 873 tcg_out_vex_opc(s, opc, r, v, rm < 0 ? 0 : rm, index < 0 ? 0 : index); 874 tcg_out_sib_offset(s, r, rm, index, shift, offset); 875} 876 877/* A simplification of the above with no index or shift. */ 878static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, 879 int rm, intptr_t offset) 880{ 881 tcg_out_modrm_sib_offset(s, opc, r, rm, -1, 0, offset); 882} 883 884static inline void tcg_out_vex_modrm_offset(TCGContext *s, int opc, int r, 885 int v, int rm, intptr_t offset) 886{ 887 tcg_out_vex_modrm_sib_offset(s, opc, r, v, rm, -1, 0, offset); 888} 889 890/* Output an opcode with an expected reference to the constant pool. */ 891static inline void tcg_out_modrm_pool(TCGContext *s, int opc, int r) 892{ 893 tcg_out_opc(s, opc, r, 0, 0); 894 /* Absolute for 32-bit, pc-relative for 64-bit. */ 895 tcg_out8(s, LOWREGMASK(r) << 3 | 5); 896 tcg_out32(s, 0); 897} 898 899/* Output an opcode with an expected reference to the constant pool. */ 900static inline void tcg_out_vex_modrm_pool(TCGContext *s, int opc, int r) 901{ 902 tcg_out_vex_opc(s, opc, r, 0, 0, 0); 903 /* Absolute for 32-bit, pc-relative for 64-bit. */ 904 tcg_out8(s, LOWREGMASK(r) << 3 | 5); 905 tcg_out32(s, 0); 906} 907 908/* Generate dest op= src. Uses the same ARITH_* codes as tgen_arithi. */ 909static inline void tgen_arithr(TCGContext *s, int subop, int dest, int src) 910{ 911 /* Propagate an opcode prefix, such as P_REXW. */ 912 int ext = subop & ~0x7; 913 subop &= 0x7; 914 915 tcg_out_modrm(s, OPC_ARITH_GvEv + (subop << 3) + ext, dest, src); 916} 917 918static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 919{ 920 int rexw = 0; 921 922 if (arg == ret) { 923 return true; 924 } 925 switch (type) { 926 case TCG_TYPE_I64: 927 rexw = P_REXW; 928 /* fallthru */ 929 case TCG_TYPE_I32: 930 if (ret < 16) { 931 if (arg < 16) { 932 tcg_out_modrm(s, OPC_MOVL_GvEv + rexw, ret, arg); 933 } else { 934 tcg_out_vex_modrm(s, OPC_MOVD_EyVy + rexw, arg, 0, ret); 935 } 936 } else { 937 if (arg < 16) { 938 tcg_out_vex_modrm(s, OPC_MOVD_VyEy + rexw, ret, 0, arg); 939 } else { 940 tcg_out_vex_modrm(s, OPC_MOVQ_VqWq, ret, 0, arg); 941 } 942 } 943 break; 944 945 case TCG_TYPE_V64: 946 tcg_debug_assert(ret >= 16 && arg >= 16); 947 tcg_out_vex_modrm(s, OPC_MOVQ_VqWq, ret, 0, arg); 948 break; 949 case TCG_TYPE_V128: 950 tcg_debug_assert(ret >= 16 && arg >= 16); 951 tcg_out_vex_modrm(s, OPC_MOVDQA_VxWx, ret, 0, arg); 952 break; 953 case TCG_TYPE_V256: 954 tcg_debug_assert(ret >= 16 && arg >= 16); 955 tcg_out_vex_modrm(s, OPC_MOVDQA_VxWx | P_VEXL, ret, 0, arg); 956 break; 957 958 default: 959 g_assert_not_reached(); 960 } 961 return true; 962} 963 964static const int avx2_dup_insn[4] = { 965 OPC_VPBROADCASTB, OPC_VPBROADCASTW, 966 OPC_VPBROADCASTD, OPC_VPBROADCASTQ, 967}; 968 969static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 970 TCGReg r, TCGReg a) 971{ 972 if (have_avx2) { 973 tcg_out_vex_modrm_type(s, avx2_dup_insn[vece], r, 0, a, type); 974 } else { 975 switch (vece) { 976 case MO_8: 977 /* ??? With zero in a register, use PSHUFB. */ 978 tcg_out_vex_modrm(s, OPC_PUNPCKLBW, r, a, a); 979 a = r; 980 /* FALLTHRU */ 981 case MO_16: 982 tcg_out_vex_modrm(s, OPC_PUNPCKLWD, r, a, a); 983 a = r; 984 /* FALLTHRU */ 985 case MO_32: 986 tcg_out_vex_modrm(s, OPC_PSHUFD, r, 0, a); 987 /* imm8 operand: all output lanes selected from input lane 0. */ 988 tcg_out8(s, 0); 989 break; 990 case MO_64: 991 tcg_out_vex_modrm(s, OPC_PUNPCKLQDQ, r, a, a); 992 break; 993 default: 994 g_assert_not_reached(); 995 } 996 } 997 return true; 998} 999 1000static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 1001 TCGReg r, TCGReg base, intptr_t offset) 1002{ 1003 if (have_avx2) { 1004 int vex_l = (type == TCG_TYPE_V256 ? P_VEXL : 0); 1005 tcg_out_vex_modrm_offset(s, avx2_dup_insn[vece] + vex_l, 1006 r, 0, base, offset); 1007 } else { 1008 switch (vece) { 1009 case MO_64: 1010 tcg_out_vex_modrm_offset(s, OPC_MOVDDUP, r, 0, base, offset); 1011 break; 1012 case MO_32: 1013 tcg_out_vex_modrm_offset(s, OPC_VBROADCASTSS, r, 0, base, offset); 1014 break; 1015 case MO_16: 1016 tcg_out_vex_modrm_offset(s, OPC_VPINSRW, r, r, base, offset); 1017 tcg_out8(s, 0); /* imm8 */ 1018 tcg_out_dup_vec(s, type, vece, r, r); 1019 break; 1020 case MO_8: 1021 tcg_out_vex_modrm_offset(s, OPC_VPINSRB, r, r, base, offset); 1022 tcg_out8(s, 0); /* imm8 */ 1023 tcg_out_dup_vec(s, type, vece, r, r); 1024 break; 1025 default: 1026 g_assert_not_reached(); 1027 } 1028 } 1029 return true; 1030} 1031 1032static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 1033 TCGReg ret, int64_t arg) 1034{ 1035 int vex_l = (type == TCG_TYPE_V256 ? P_VEXL : 0); 1036 1037 if (arg == 0) { 1038 tcg_out_vex_modrm(s, OPC_PXOR, ret, ret, ret); 1039 return; 1040 } 1041 if (arg == -1) { 1042 tcg_out_vex_modrm(s, OPC_PCMPEQB + vex_l, ret, ret, ret); 1043 return; 1044 } 1045 1046 if (TCG_TARGET_REG_BITS == 32 && vece < MO_64) { 1047 if (have_avx2) { 1048 tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTD + vex_l, ret); 1049 } else { 1050 tcg_out_vex_modrm_pool(s, OPC_VBROADCASTSS, ret); 1051 } 1052 new_pool_label(s, arg, R_386_32, s->code_ptr - 4, 0); 1053 } else { 1054 if (type == TCG_TYPE_V64) { 1055 tcg_out_vex_modrm_pool(s, OPC_MOVQ_VqWq, ret); 1056 } else if (have_avx2) { 1057 tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTQ + vex_l, ret); 1058 } else { 1059 tcg_out_vex_modrm_pool(s, OPC_MOVDDUP, ret); 1060 } 1061 if (TCG_TARGET_REG_BITS == 64) { 1062 new_pool_label(s, arg, R_386_PC32, s->code_ptr - 4, -4); 1063 } else { 1064 new_pool_l2(s, R_386_32, s->code_ptr - 4, 0, arg, arg >> 32); 1065 } 1066 } 1067} 1068 1069static void tcg_out_movi_vec(TCGContext *s, TCGType type, 1070 TCGReg ret, tcg_target_long arg) 1071{ 1072 if (arg == 0) { 1073 tcg_out_vex_modrm(s, OPC_PXOR, ret, ret, ret); 1074 return; 1075 } 1076 if (arg == -1) { 1077 tcg_out_vex_modrm(s, OPC_PCMPEQB, ret, ret, ret); 1078 return; 1079 } 1080 1081 int rexw = (type == TCG_TYPE_I32 ? 0 : P_REXW); 1082 tcg_out_vex_modrm_pool(s, OPC_MOVD_VyEy + rexw, ret); 1083 if (TCG_TARGET_REG_BITS == 64) { 1084 new_pool_label(s, arg, R_386_PC32, s->code_ptr - 4, -4); 1085 } else { 1086 new_pool_label(s, arg, R_386_32, s->code_ptr - 4, 0); 1087 } 1088} 1089 1090static void tcg_out_movi_int(TCGContext *s, TCGType type, 1091 TCGReg ret, tcg_target_long arg) 1092{ 1093 tcg_target_long diff; 1094 1095 if (arg == 0) { 1096 tgen_arithr(s, ARITH_XOR, ret, ret); 1097 return; 1098 } 1099 if (arg == (uint32_t)arg || type == TCG_TYPE_I32) { 1100 tcg_out_opc(s, OPC_MOVL_Iv + LOWREGMASK(ret), 0, ret, 0); 1101 tcg_out32(s, arg); 1102 return; 1103 } 1104 if (arg == (int32_t)arg) { 1105 tcg_out_modrm(s, OPC_MOVL_EvIz + P_REXW, 0, ret); 1106 tcg_out32(s, arg); 1107 return; 1108 } 1109 1110 /* Try a 7 byte pc-relative lea before the 10 byte movq. */ 1111 diff = tcg_pcrel_diff(s, (const void *)arg) - 7; 1112 if (diff == (int32_t)diff) { 1113 tcg_out_opc(s, OPC_LEA | P_REXW, ret, 0, 0); 1114 tcg_out8(s, (LOWREGMASK(ret) << 3) | 5); 1115 tcg_out32(s, diff); 1116 return; 1117 } 1118 1119 tcg_out_opc(s, OPC_MOVL_Iv + P_REXW + LOWREGMASK(ret), 0, ret, 0); 1120 tcg_out64(s, arg); 1121} 1122 1123static void tcg_out_movi(TCGContext *s, TCGType type, 1124 TCGReg ret, tcg_target_long arg) 1125{ 1126 switch (type) { 1127 case TCG_TYPE_I32: 1128#if TCG_TARGET_REG_BITS == 64 1129 case TCG_TYPE_I64: 1130#endif 1131 if (ret < 16) { 1132 tcg_out_movi_int(s, type, ret, arg); 1133 } else { 1134 tcg_out_movi_vec(s, type, ret, arg); 1135 } 1136 break; 1137 default: 1138 g_assert_not_reached(); 1139 } 1140} 1141 1142static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 1143{ 1144 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 1145 tcg_out_modrm(s, OPC_XCHG_EvGv + rexw, r1, r2); 1146 return true; 1147} 1148 1149static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 1150 tcg_target_long imm) 1151{ 1152 /* This function is only used for passing structs by reference. */ 1153 tcg_debug_assert(imm == (int32_t)imm); 1154 tcg_out_modrm_offset(s, OPC_LEA | P_REXW, rd, rs, imm); 1155} 1156 1157static inline void tcg_out_pushi(TCGContext *s, tcg_target_long val) 1158{ 1159 if (val == (int8_t)val) { 1160 tcg_out_opc(s, OPC_PUSH_Ib, 0, 0, 0); 1161 tcg_out8(s, val); 1162 } else if (val == (int32_t)val) { 1163 tcg_out_opc(s, OPC_PUSH_Iv, 0, 0, 0); 1164 tcg_out32(s, val); 1165 } else { 1166 g_assert_not_reached(); 1167 } 1168} 1169 1170static inline void tcg_out_mb(TCGContext *s, TCGArg a0) 1171{ 1172 /* Given the strength of x86 memory ordering, we only need care for 1173 store-load ordering. Experimentally, "lock orl $0,0(%esp)" is 1174 faster than "mfence", so don't bother with the sse insn. */ 1175 if (a0 & TCG_MO_ST_LD) { 1176 tcg_out8(s, 0xf0); 1177 tcg_out_modrm_offset(s, OPC_ARITH_EvIb, ARITH_OR, TCG_REG_ESP, 0); 1178 tcg_out8(s, 0); 1179 } 1180} 1181 1182static inline void tcg_out_push(TCGContext *s, int reg) 1183{ 1184 tcg_out_opc(s, OPC_PUSH_r32 + LOWREGMASK(reg), 0, reg, 0); 1185} 1186 1187static inline void tcg_out_pop(TCGContext *s, int reg) 1188{ 1189 tcg_out_opc(s, OPC_POP_r32 + LOWREGMASK(reg), 0, reg, 0); 1190} 1191 1192static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, 1193 TCGReg arg1, intptr_t arg2) 1194{ 1195 switch (type) { 1196 case TCG_TYPE_I32: 1197 if (ret < 16) { 1198 tcg_out_modrm_offset(s, OPC_MOVL_GvEv, ret, arg1, arg2); 1199 } else { 1200 tcg_out_vex_modrm_offset(s, OPC_MOVD_VyEy, ret, 0, arg1, arg2); 1201 } 1202 break; 1203 case TCG_TYPE_I64: 1204 if (ret < 16) { 1205 tcg_out_modrm_offset(s, OPC_MOVL_GvEv | P_REXW, ret, arg1, arg2); 1206 break; 1207 } 1208 /* FALLTHRU */ 1209 case TCG_TYPE_V64: 1210 /* There is no instruction that can validate 8-byte alignment. */ 1211 tcg_debug_assert(ret >= 16); 1212 tcg_out_vex_modrm_offset(s, OPC_MOVQ_VqWq, ret, 0, arg1, arg2); 1213 break; 1214 case TCG_TYPE_V128: 1215 /* 1216 * The gvec infrastructure is asserts that v128 vector loads 1217 * and stores use a 16-byte aligned offset. Validate that the 1218 * final pointer is aligned by using an insn that will SIGSEGV. 1219 */ 1220 tcg_debug_assert(ret >= 16); 1221 tcg_out_vex_modrm_offset(s, OPC_MOVDQA_VxWx, ret, 0, arg1, arg2); 1222 break; 1223 case TCG_TYPE_V256: 1224 /* 1225 * The gvec infrastructure only requires 16-byte alignment, 1226 * so here we must use an unaligned load. 1227 */ 1228 tcg_debug_assert(ret >= 16); 1229 tcg_out_vex_modrm_offset(s, OPC_MOVDQU_VxWx | P_VEXL, 1230 ret, 0, arg1, arg2); 1231 break; 1232 default: 1233 g_assert_not_reached(); 1234 } 1235} 1236 1237static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 1238 TCGReg arg1, intptr_t arg2) 1239{ 1240 switch (type) { 1241 case TCG_TYPE_I32: 1242 if (arg < 16) { 1243 tcg_out_modrm_offset(s, OPC_MOVL_EvGv, arg, arg1, arg2); 1244 } else { 1245 tcg_out_vex_modrm_offset(s, OPC_MOVD_EyVy, arg, 0, arg1, arg2); 1246 } 1247 break; 1248 case TCG_TYPE_I64: 1249 if (arg < 16) { 1250 tcg_out_modrm_offset(s, OPC_MOVL_EvGv | P_REXW, arg, arg1, arg2); 1251 break; 1252 } 1253 /* FALLTHRU */ 1254 case TCG_TYPE_V64: 1255 /* There is no instruction that can validate 8-byte alignment. */ 1256 tcg_debug_assert(arg >= 16); 1257 tcg_out_vex_modrm_offset(s, OPC_MOVQ_WqVq, arg, 0, arg1, arg2); 1258 break; 1259 case TCG_TYPE_V128: 1260 /* 1261 * The gvec infrastructure is asserts that v128 vector loads 1262 * and stores use a 16-byte aligned offset. Validate that the 1263 * final pointer is aligned by using an insn that will SIGSEGV. 1264 * 1265 * This specific instance is also used by TCG_CALL_RET_BY_VEC, 1266 * for _WIN64, which must have SSE2 but may not have AVX. 1267 */ 1268 tcg_debug_assert(arg >= 16); 1269 if (have_avx1) { 1270 tcg_out_vex_modrm_offset(s, OPC_MOVDQA_WxVx, arg, 0, arg1, arg2); 1271 } else { 1272 tcg_out_modrm_offset(s, OPC_MOVDQA_WxVx, arg, arg1, arg2); 1273 } 1274 break; 1275 case TCG_TYPE_V256: 1276 /* 1277 * The gvec infrastructure only requires 16-byte alignment, 1278 * so here we must use an unaligned store. 1279 */ 1280 tcg_debug_assert(arg >= 16); 1281 tcg_out_vex_modrm_offset(s, OPC_MOVDQU_WxVx | P_VEXL, 1282 arg, 0, arg1, arg2); 1283 break; 1284 default: 1285 g_assert_not_reached(); 1286 } 1287} 1288 1289static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 1290 TCGReg base, intptr_t ofs) 1291{ 1292 int rexw = 0; 1293 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64) { 1294 if (val != (int32_t)val) { 1295 return false; 1296 } 1297 rexw = P_REXW; 1298 } else if (type != TCG_TYPE_I32) { 1299 return false; 1300 } 1301 tcg_out_modrm_offset(s, OPC_MOVL_EvIz | rexw, 0, base, ofs); 1302 tcg_out32(s, val); 1303 return true; 1304} 1305 1306static void tcg_out_shifti(TCGContext *s, int subopc, int reg, int count) 1307{ 1308 /* Propagate an opcode prefix, such as P_DATA16. */ 1309 int ext = subopc & ~0x7; 1310 subopc &= 0x7; 1311 1312 if (count == 1) { 1313 tcg_out_modrm(s, OPC_SHIFT_1 + ext, subopc, reg); 1314 } else { 1315 tcg_out_modrm(s, OPC_SHIFT_Ib + ext, subopc, reg); 1316 tcg_out8(s, count); 1317 } 1318} 1319 1320static inline void tcg_out_bswap32(TCGContext *s, int reg) 1321{ 1322 tcg_out_opc(s, OPC_BSWAP + LOWREGMASK(reg), 0, reg, 0); 1323} 1324 1325static inline void tcg_out_rolw_8(TCGContext *s, int reg) 1326{ 1327 tcg_out_shifti(s, SHIFT_ROL + P_DATA16, reg, 8); 1328} 1329 1330static void tcg_out_ext8u(TCGContext *s, TCGReg dest, TCGReg src) 1331{ 1332 if (TCG_TARGET_REG_BITS == 32 && src >= 4) { 1333 tcg_out_mov(s, TCG_TYPE_I32, dest, src); 1334 if (dest >= 4) { 1335 tcg_out_modrm(s, OPC_ARITH_EvIz, ARITH_AND, dest); 1336 tcg_out32(s, 0xff); 1337 return; 1338 } 1339 src = dest; 1340 } 1341 tcg_out_modrm(s, OPC_MOVZBL + P_REXB_RM, dest, src); 1342} 1343 1344static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) 1345{ 1346 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 1347 1348 if (TCG_TARGET_REG_BITS == 32 && src >= 4) { 1349 tcg_out_mov(s, TCG_TYPE_I32, dest, src); 1350 if (dest >= 4) { 1351 tcg_out_shifti(s, SHIFT_SHL, dest, 24); 1352 tcg_out_shifti(s, SHIFT_SAR, dest, 24); 1353 return; 1354 } 1355 src = dest; 1356 } 1357 tcg_out_modrm(s, OPC_MOVSBL + P_REXB_RM + rexw, dest, src); 1358} 1359 1360static void tcg_out_ext16u(TCGContext *s, TCGReg dest, TCGReg src) 1361{ 1362 /* movzwl */ 1363 tcg_out_modrm(s, OPC_MOVZWL, dest, src); 1364} 1365 1366static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) 1367{ 1368 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 1369 /* movsw[lq] */ 1370 tcg_out_modrm(s, OPC_MOVSWL + rexw, dest, src); 1371} 1372 1373static void tcg_out_ext32u(TCGContext *s, TCGReg dest, TCGReg src) 1374{ 1375 /* 32-bit mov zero extends. */ 1376 tcg_out_modrm(s, OPC_MOVL_GvEv, dest, src); 1377} 1378 1379static void tcg_out_ext32s(TCGContext *s, TCGReg dest, TCGReg src) 1380{ 1381 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 1382 tcg_out_modrm(s, OPC_MOVSLQ, dest, src); 1383} 1384 1385static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg dest, TCGReg src) 1386{ 1387 tcg_out_ext32s(s, dest, src); 1388} 1389 1390static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg dest, TCGReg src) 1391{ 1392 if (dest != src) { 1393 tcg_out_ext32u(s, dest, src); 1394 } 1395} 1396 1397static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg dest, TCGReg src) 1398{ 1399 tcg_out_ext32u(s, dest, src); 1400} 1401 1402static inline void tcg_out_bswap64(TCGContext *s, int reg) 1403{ 1404 tcg_out_opc(s, OPC_BSWAP + P_REXW + LOWREGMASK(reg), 0, reg, 0); 1405} 1406 1407static void tgen_arithi(TCGContext *s, int c, int r0, 1408 tcg_target_long val, int cf) 1409{ 1410 int rexw = 0; 1411 1412 if (TCG_TARGET_REG_BITS == 64) { 1413 rexw = c & -8; 1414 c &= 7; 1415 } 1416 1417 switch (c) { 1418 case ARITH_ADD: 1419 case ARITH_SUB: 1420 if (!cf) { 1421 /* 1422 * ??? While INC is 2 bytes shorter than ADDL $1, they also induce 1423 * partial flags update stalls on Pentium4 and are not recommended 1424 * by current Intel optimization manuals. 1425 */ 1426 if (val == 1 || val == -1) { 1427 int is_inc = (c == ARITH_ADD) ^ (val < 0); 1428 if (TCG_TARGET_REG_BITS == 64) { 1429 /* 1430 * The single-byte increment encodings are re-tasked 1431 * as the REX prefixes. Use the MODRM encoding. 1432 */ 1433 tcg_out_modrm(s, OPC_GRP5 + rexw, 1434 (is_inc ? EXT5_INC_Ev : EXT5_DEC_Ev), r0); 1435 } else { 1436 tcg_out8(s, (is_inc ? OPC_INC_r32 : OPC_DEC_r32) + r0); 1437 } 1438 return; 1439 } 1440 if (val == 128) { 1441 /* 1442 * Facilitate using an 8-bit immediate. Carry is inverted 1443 * by this transformation, so do it only if cf == 0. 1444 */ 1445 c ^= ARITH_ADD ^ ARITH_SUB; 1446 val = -128; 1447 } 1448 } 1449 break; 1450 1451 case ARITH_AND: 1452 if (TCG_TARGET_REG_BITS == 64) { 1453 if (val == 0xffffffffu) { 1454 tcg_out_ext32u(s, r0, r0); 1455 return; 1456 } 1457 if (val == (uint32_t)val) { 1458 /* AND with no high bits set can use a 32-bit operation. */ 1459 rexw = 0; 1460 } 1461 } 1462 if (val == 0xffu && (r0 < 4 || TCG_TARGET_REG_BITS == 64)) { 1463 tcg_out_ext8u(s, r0, r0); 1464 return; 1465 } 1466 if (val == 0xffffu) { 1467 tcg_out_ext16u(s, r0, r0); 1468 return; 1469 } 1470 break; 1471 1472 case ARITH_OR: 1473 case ARITH_XOR: 1474 if (val >= 0x80 && val <= 0xff 1475 && (r0 < 4 || TCG_TARGET_REG_BITS == 64)) { 1476 tcg_out_modrm(s, OPC_ARITH_EbIb + P_REXB_RM, c, r0); 1477 tcg_out8(s, val); 1478 return; 1479 } 1480 break; 1481 } 1482 1483 if (val == (int8_t)val) { 1484 tcg_out_modrm(s, OPC_ARITH_EvIb + rexw, c, r0); 1485 tcg_out8(s, val); 1486 return; 1487 } 1488 if (rexw == 0 || val == (int32_t)val) { 1489 tcg_out_modrm(s, OPC_ARITH_EvIz + rexw, c, r0); 1490 tcg_out32(s, val); 1491 return; 1492 } 1493 1494 g_assert_not_reached(); 1495} 1496 1497static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val) 1498{ 1499 if (val != 0) { 1500 tgen_arithi(s, ARITH_ADD + P_REXW, reg, val, 0); 1501 } 1502} 1503 1504/* Set SMALL to force a short forward branch. */ 1505static void tcg_out_jxx(TCGContext *s, int opc, TCGLabel *l, bool small) 1506{ 1507 int32_t val, val1; 1508 1509 if (l->has_value) { 1510 val = tcg_pcrel_diff(s, l->u.value_ptr); 1511 val1 = val - 2; 1512 if ((int8_t)val1 == val1) { 1513 if (opc == -1) { 1514 tcg_out8(s, OPC_JMP_short); 1515 } else { 1516 tcg_out8(s, OPC_JCC_short + opc); 1517 } 1518 tcg_out8(s, val1); 1519 } else { 1520 tcg_debug_assert(!small); 1521 if (opc == -1) { 1522 tcg_out8(s, OPC_JMP_long); 1523 tcg_out32(s, val - 5); 1524 } else { 1525 tcg_out_opc(s, OPC_JCC_long + opc, 0, 0, 0); 1526 tcg_out32(s, val - 6); 1527 } 1528 } 1529 } else if (small) { 1530 if (opc == -1) { 1531 tcg_out8(s, OPC_JMP_short); 1532 } else { 1533 tcg_out8(s, OPC_JCC_short + opc); 1534 } 1535 tcg_out_reloc(s, s->code_ptr, R_386_PC8, l, -1); 1536 s->code_ptr += 1; 1537 } else { 1538 if (opc == -1) { 1539 tcg_out8(s, OPC_JMP_long); 1540 } else { 1541 tcg_out_opc(s, OPC_JCC_long + opc, 0, 0, 0); 1542 } 1543 tcg_out_reloc(s, s->code_ptr, R_386_PC32, l, -4); 1544 s->code_ptr += 4; 1545 } 1546} 1547 1548static int tcg_out_cmp(TCGContext *s, TCGCond cond, TCGArg arg1, 1549 TCGArg arg2, int const_arg2, int rexw) 1550{ 1551 int jz, js; 1552 1553 if (!is_tst_cond(cond)) { 1554 if (!const_arg2) { 1555 tgen_arithr(s, ARITH_CMP + rexw, arg1, arg2); 1556 } else if (arg2 == 0) { 1557 tcg_out_modrm(s, OPC_TESTL + rexw, arg1, arg1); 1558 } else { 1559 tcg_debug_assert(!rexw || arg2 == (int32_t)arg2); 1560 tgen_arithi(s, ARITH_CMP + rexw, arg1, arg2, 0); 1561 } 1562 return tcg_cond_to_jcc[cond]; 1563 } 1564 1565 jz = tcg_cond_to_jcc[cond]; 1566 js = (cond == TCG_COND_TSTNE ? JCC_JS : JCC_JNS); 1567 1568 if (!const_arg2) { 1569 tcg_out_modrm(s, OPC_TESTL + rexw, arg1, arg2); 1570 return jz; 1571 } 1572 1573 if (arg2 <= 0xff && (TCG_TARGET_REG_BITS == 64 || arg1 < 4)) { 1574 if (arg2 == 0x80) { 1575 tcg_out_modrm(s, OPC_TESTB | P_REXB_R, arg1, arg1); 1576 return js; 1577 } 1578 if (arg2 == 0xff) { 1579 tcg_out_modrm(s, OPC_TESTB | P_REXB_R, arg1, arg1); 1580 return jz; 1581 } 1582 tcg_out_modrm(s, OPC_GRP3_Eb | P_REXB_RM, EXT3_TESTi, arg1); 1583 tcg_out8(s, arg2); 1584 return jz; 1585 } 1586 1587 if ((arg2 & ~0xff00) == 0 && arg1 < 4) { 1588 if (arg2 == 0x8000) { 1589 tcg_out_modrm(s, OPC_TESTB, arg1 + 4, arg1 + 4); 1590 return js; 1591 } 1592 if (arg2 == 0xff00) { 1593 tcg_out_modrm(s, OPC_TESTB, arg1 + 4, arg1 + 4); 1594 return jz; 1595 } 1596 tcg_out_modrm(s, OPC_GRP3_Eb, EXT3_TESTi, arg1 + 4); 1597 tcg_out8(s, arg2 >> 8); 1598 return jz; 1599 } 1600 1601 if (arg2 == 0xffff) { 1602 tcg_out_modrm(s, OPC_TESTL | P_DATA16, arg1, arg1); 1603 return jz; 1604 } 1605 if (arg2 == 0xffffffffu) { 1606 tcg_out_modrm(s, OPC_TESTL, arg1, arg1); 1607 return jz; 1608 } 1609 1610 if (is_power_of_2(rexw ? arg2 : (uint32_t)arg2)) { 1611 int jc = (cond == TCG_COND_TSTNE ? JCC_JB : JCC_JAE); 1612 int sh = ctz64(arg2); 1613 1614 rexw = (sh & 32 ? P_REXW : 0); 1615 if ((sh & 31) == 31) { 1616 tcg_out_modrm(s, OPC_TESTL | rexw, arg1, arg1); 1617 return js; 1618 } else { 1619 tcg_out_modrm(s, OPC_GRPBT | rexw, OPC_GRPBT_BT, arg1); 1620 tcg_out8(s, sh); 1621 return jc; 1622 } 1623 } 1624 1625 if (rexw) { 1626 if (arg2 == (uint32_t)arg2) { 1627 rexw = 0; 1628 } else { 1629 tcg_debug_assert(arg2 == (int32_t)arg2); 1630 } 1631 } 1632 tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_TESTi, arg1); 1633 tcg_out32(s, arg2); 1634 return jz; 1635} 1636 1637static void tcg_out_brcond(TCGContext *s, int rexw, TCGCond cond, 1638 TCGArg arg1, TCGArg arg2, int const_arg2, 1639 TCGLabel *label, bool small) 1640{ 1641 int jcc = tcg_out_cmp(s, cond, arg1, arg2, const_arg2, rexw); 1642 tcg_out_jxx(s, jcc, label, small); 1643} 1644 1645#if TCG_TARGET_REG_BITS == 32 1646static void tcg_out_brcond2(TCGContext *s, const TCGArg *args, 1647 const int *const_args, bool small) 1648{ 1649 TCGLabel *label_next = gen_new_label(); 1650 TCGLabel *label_this = arg_label(args[5]); 1651 TCGCond cond = args[4]; 1652 1653 switch (cond) { 1654 case TCG_COND_EQ: 1655 case TCG_COND_TSTEQ: 1656 tcg_out_brcond(s, 0, tcg_invert_cond(cond), 1657 args[0], args[2], const_args[2], label_next, 1); 1658 tcg_out_brcond(s, 0, cond, args[1], args[3], const_args[3], 1659 label_this, small); 1660 break; 1661 case TCG_COND_NE: 1662 case TCG_COND_TSTNE: 1663 tcg_out_brcond(s, 0, cond, args[0], args[2], const_args[2], 1664 label_this, small); 1665 tcg_out_brcond(s, 0, cond, args[1], args[3], const_args[3], 1666 label_this, small); 1667 break; 1668 case TCG_COND_LT: 1669 tcg_out_brcond(s, 0, TCG_COND_LT, args[1], args[3], const_args[3], 1670 label_this, small); 1671 tcg_out_jxx(s, JCC_JNE, label_next, 1); 1672 tcg_out_brcond(s, 0, TCG_COND_LTU, args[0], args[2], const_args[2], 1673 label_this, small); 1674 break; 1675 case TCG_COND_LE: 1676 tcg_out_brcond(s, 0, TCG_COND_LT, args[1], args[3], const_args[3], 1677 label_this, small); 1678 tcg_out_jxx(s, JCC_JNE, label_next, 1); 1679 tcg_out_brcond(s, 0, TCG_COND_LEU, args[0], args[2], const_args[2], 1680 label_this, small); 1681 break; 1682 case TCG_COND_GT: 1683 tcg_out_brcond(s, 0, TCG_COND_GT, args[1], args[3], const_args[3], 1684 label_this, small); 1685 tcg_out_jxx(s, JCC_JNE, label_next, 1); 1686 tcg_out_brcond(s, 0, TCG_COND_GTU, args[0], args[2], const_args[2], 1687 label_this, small); 1688 break; 1689 case TCG_COND_GE: 1690 tcg_out_brcond(s, 0, TCG_COND_GT, args[1], args[3], const_args[3], 1691 label_this, small); 1692 tcg_out_jxx(s, JCC_JNE, label_next, 1); 1693 tcg_out_brcond(s, 0, TCG_COND_GEU, args[0], args[2], const_args[2], 1694 label_this, small); 1695 break; 1696 case TCG_COND_LTU: 1697 tcg_out_brcond(s, 0, TCG_COND_LTU, args[1], args[3], const_args[3], 1698 label_this, small); 1699 tcg_out_jxx(s, JCC_JNE, label_next, 1); 1700 tcg_out_brcond(s, 0, TCG_COND_LTU, args[0], args[2], const_args[2], 1701 label_this, small); 1702 break; 1703 case TCG_COND_LEU: 1704 tcg_out_brcond(s, 0, TCG_COND_LTU, args[1], args[3], const_args[3], 1705 label_this, small); 1706 tcg_out_jxx(s, JCC_JNE, label_next, 1); 1707 tcg_out_brcond(s, 0, TCG_COND_LEU, args[0], args[2], const_args[2], 1708 label_this, small); 1709 break; 1710 case TCG_COND_GTU: 1711 tcg_out_brcond(s, 0, TCG_COND_GTU, args[1], args[3], const_args[3], 1712 label_this, small); 1713 tcg_out_jxx(s, JCC_JNE, label_next, 1); 1714 tcg_out_brcond(s, 0, TCG_COND_GTU, args[0], args[2], const_args[2], 1715 label_this, small); 1716 break; 1717 case TCG_COND_GEU: 1718 tcg_out_brcond(s, 0, TCG_COND_GTU, args[1], args[3], const_args[3], 1719 label_this, small); 1720 tcg_out_jxx(s, JCC_JNE, label_next, 1); 1721 tcg_out_brcond(s, 0, TCG_COND_GEU, args[0], args[2], const_args[2], 1722 label_this, small); 1723 break; 1724 default: 1725 g_assert_not_reached(); 1726 } 1727 tcg_out_label(s, label_next); 1728} 1729#endif 1730 1731static void tcg_out_setcond(TCGContext *s, int rexw, TCGCond cond, 1732 TCGArg dest, TCGArg arg1, TCGArg arg2, 1733 int const_arg2, bool neg) 1734{ 1735 int cmp_rexw = rexw; 1736 bool inv = false; 1737 bool cleared; 1738 int jcc; 1739 1740 switch (cond) { 1741 case TCG_COND_NE: 1742 inv = true; 1743 /* fall through */ 1744 case TCG_COND_EQ: 1745 /* If arg2 is 0, convert to LTU/GEU vs 1. */ 1746 if (const_arg2 && arg2 == 0) { 1747 arg2 = 1; 1748 goto do_ltu; 1749 } 1750 break; 1751 1752 case TCG_COND_TSTNE: 1753 inv = true; 1754 /* fall through */ 1755 case TCG_COND_TSTEQ: 1756 /* If arg2 is -1, convert to LTU/GEU vs 1. */ 1757 if (const_arg2 && arg2 == 0xffffffffu) { 1758 arg2 = 1; 1759 cmp_rexw = 0; 1760 goto do_ltu; 1761 } 1762 break; 1763 1764 case TCG_COND_LEU: 1765 inv = true; 1766 /* fall through */ 1767 case TCG_COND_GTU: 1768 /* If arg2 is a register, swap for LTU/GEU. */ 1769 if (!const_arg2) { 1770 TCGReg t = arg1; 1771 arg1 = arg2; 1772 arg2 = t; 1773 goto do_ltu; 1774 } 1775 break; 1776 1777 case TCG_COND_GEU: 1778 inv = true; 1779 /* fall through */ 1780 case TCG_COND_LTU: 1781 do_ltu: 1782 /* 1783 * Relying on the carry bit, use SBB to produce -1 if LTU, 0 if GEU. 1784 * We can then use NEG or INC to produce the desired result. 1785 * This is always smaller than the SETCC expansion. 1786 */ 1787 tcg_out_cmp(s, TCG_COND_LTU, arg1, arg2, const_arg2, cmp_rexw); 1788 1789 /* X - X - C = -C = (C ? -1 : 0) */ 1790 tgen_arithr(s, ARITH_SBB + (neg ? rexw : 0), dest, dest); 1791 if (inv && neg) { 1792 /* ~(C ? -1 : 0) = (C ? 0 : -1) */ 1793 tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NOT, dest); 1794 } else if (inv) { 1795 /* (C ? -1 : 0) + 1 = (C ? 0 : 1) */ 1796 tgen_arithi(s, ARITH_ADD, dest, 1, 0); 1797 } else if (!neg) { 1798 /* -(C ? -1 : 0) = (C ? 1 : 0) */ 1799 tcg_out_modrm(s, OPC_GRP3_Ev, EXT3_NEG, dest); 1800 } 1801 return; 1802 1803 case TCG_COND_GE: 1804 inv = true; 1805 /* fall through */ 1806 case TCG_COND_LT: 1807 /* If arg2 is 0, extract the sign bit. */ 1808 if (const_arg2 && arg2 == 0) { 1809 tcg_out_mov(s, rexw ? TCG_TYPE_I64 : TCG_TYPE_I32, dest, arg1); 1810 if (inv) { 1811 tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NOT, dest); 1812 } 1813 tcg_out_shifti(s, (neg ? SHIFT_SAR : SHIFT_SHR) + rexw, 1814 dest, rexw ? 63 : 31); 1815 return; 1816 } 1817 break; 1818 1819 default: 1820 break; 1821 } 1822 1823 /* 1824 * If dest does not overlap the inputs, clearing it first is preferred. 1825 * The XOR breaks any false dependency for the low-byte write to dest, 1826 * and is also one byte smaller than MOVZBL. 1827 */ 1828 cleared = false; 1829 if (dest != arg1 && (const_arg2 || dest != arg2)) { 1830 tgen_arithr(s, ARITH_XOR, dest, dest); 1831 cleared = true; 1832 } 1833 1834 jcc = tcg_out_cmp(s, cond, arg1, arg2, const_arg2, cmp_rexw); 1835 tcg_out_modrm(s, OPC_SETCC | jcc, 0, dest); 1836 1837 if (!cleared) { 1838 tcg_out_ext8u(s, dest, dest); 1839 } 1840 if (neg) { 1841 tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NEG, dest); 1842 } 1843} 1844 1845#if TCG_TARGET_REG_BITS == 32 1846static void tcg_out_setcond2(TCGContext *s, const TCGArg *args, 1847 const int *const_args) 1848{ 1849 TCGArg new_args[6]; 1850 TCGLabel *label_true, *label_over; 1851 1852 memcpy(new_args, args+1, 5*sizeof(TCGArg)); 1853 1854 if (args[0] == args[1] || args[0] == args[2] 1855 || (!const_args[3] && args[0] == args[3]) 1856 || (!const_args[4] && args[0] == args[4])) { 1857 /* When the destination overlaps with one of the argument 1858 registers, don't do anything tricky. */ 1859 label_true = gen_new_label(); 1860 label_over = gen_new_label(); 1861 1862 new_args[5] = label_arg(label_true); 1863 tcg_out_brcond2(s, new_args, const_args+1, 1); 1864 1865 tcg_out_movi(s, TCG_TYPE_I32, args[0], 0); 1866 tcg_out_jxx(s, JCC_JMP, label_over, 1); 1867 tcg_out_label(s, label_true); 1868 1869 tcg_out_movi(s, TCG_TYPE_I32, args[0], 1); 1870 tcg_out_label(s, label_over); 1871 } else { 1872 /* When the destination does not overlap one of the arguments, 1873 clear the destination first, jump if cond false, and emit an 1874 increment in the true case. This results in smaller code. */ 1875 1876 tcg_out_movi(s, TCG_TYPE_I32, args[0], 0); 1877 1878 label_over = gen_new_label(); 1879 new_args[4] = tcg_invert_cond(new_args[4]); 1880 new_args[5] = label_arg(label_over); 1881 tcg_out_brcond2(s, new_args, const_args+1, 1); 1882 1883 tgen_arithi(s, ARITH_ADD, args[0], 1, 0); 1884 tcg_out_label(s, label_over); 1885 } 1886} 1887#endif 1888 1889static void tcg_out_cmov(TCGContext *s, int jcc, int rexw, 1890 TCGReg dest, TCGReg v1) 1891{ 1892 tcg_out_modrm(s, OPC_CMOVCC | jcc | rexw, dest, v1); 1893} 1894 1895static void tcg_out_movcond(TCGContext *s, int rexw, TCGCond cond, 1896 TCGReg dest, TCGReg c1, TCGArg c2, int const_c2, 1897 TCGReg v1) 1898{ 1899 int jcc = tcg_out_cmp(s, cond, c1, c2, const_c2, rexw); 1900 tcg_out_cmov(s, jcc, rexw, dest, v1); 1901} 1902 1903static void tcg_out_ctz(TCGContext *s, int rexw, TCGReg dest, TCGReg arg1, 1904 TCGArg arg2, bool const_a2) 1905{ 1906 if (have_bmi1) { 1907 tcg_out_modrm(s, OPC_TZCNT + rexw, dest, arg1); 1908 if (const_a2) { 1909 tcg_debug_assert(arg2 == (rexw ? 64 : 32)); 1910 } else { 1911 tcg_debug_assert(dest != arg2); 1912 tcg_out_cmov(s, JCC_JB, rexw, dest, arg2); 1913 } 1914 } else { 1915 tcg_debug_assert(dest != arg2); 1916 tcg_out_modrm(s, OPC_BSF + rexw, dest, arg1); 1917 tcg_out_cmov(s, JCC_JE, rexw, dest, arg2); 1918 } 1919} 1920 1921static void tcg_out_clz(TCGContext *s, int rexw, TCGReg dest, TCGReg arg1, 1922 TCGArg arg2, bool const_a2) 1923{ 1924 if (have_lzcnt) { 1925 tcg_out_modrm(s, OPC_LZCNT + rexw, dest, arg1); 1926 if (const_a2) { 1927 tcg_debug_assert(arg2 == (rexw ? 64 : 32)); 1928 } else { 1929 tcg_debug_assert(dest != arg2); 1930 tcg_out_cmov(s, JCC_JB, rexw, dest, arg2); 1931 } 1932 } else { 1933 tcg_debug_assert(!const_a2); 1934 tcg_debug_assert(dest != arg1); 1935 tcg_debug_assert(dest != arg2); 1936 1937 /* Recall that the output of BSR is the index not the count. */ 1938 tcg_out_modrm(s, OPC_BSR + rexw, dest, arg1); 1939 tgen_arithi(s, ARITH_XOR + rexw, dest, rexw ? 63 : 31, 0); 1940 1941 /* Since we have destroyed the flags from BSR, we have to re-test. */ 1942 int jcc = tcg_out_cmp(s, TCG_COND_EQ, arg1, 0, 1, rexw); 1943 tcg_out_cmov(s, jcc, rexw, dest, arg2); 1944 } 1945} 1946 1947static void tcg_out_branch(TCGContext *s, int call, const tcg_insn_unit *dest) 1948{ 1949 intptr_t disp = tcg_pcrel_diff(s, dest) - 5; 1950 1951 if (disp == (int32_t)disp) { 1952 tcg_out_opc(s, call ? OPC_CALL_Jz : OPC_JMP_long, 0, 0, 0); 1953 tcg_out32(s, disp); 1954 } else { 1955 /* rip-relative addressing into the constant pool. 1956 This is 6 + 8 = 14 bytes, as compared to using an 1957 immediate load 10 + 6 = 16 bytes, plus we may 1958 be able to re-use the pool constant for more calls. */ 1959 tcg_out_opc(s, OPC_GRP5, 0, 0, 0); 1960 tcg_out8(s, (call ? EXT5_CALLN_Ev : EXT5_JMPN_Ev) << 3 | 5); 1961 new_pool_label(s, (uintptr_t)dest, R_386_PC32, s->code_ptr, -4); 1962 tcg_out32(s, 0); 1963 } 1964} 1965 1966static void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest, 1967 const TCGHelperInfo *info) 1968{ 1969 tcg_out_branch(s, 1, dest); 1970 1971#ifndef _WIN32 1972 if (TCG_TARGET_REG_BITS == 32 && info->out_kind == TCG_CALL_RET_BY_REF) { 1973 /* 1974 * The sysv i386 abi for struct return places a reference as the 1975 * first argument of the stack, and pops that argument with the 1976 * return statement. Since we want to retain the aligned stack 1977 * pointer for the callee, we do not want to actually push that 1978 * argument before the call but rely on the normal store to the 1979 * stack slot. But we do need to compensate for the pop in order 1980 * to reset our correct stack pointer value. 1981 * Pushing a garbage value back onto the stack is quickest. 1982 */ 1983 tcg_out_push(s, TCG_REG_EAX); 1984 } 1985#endif 1986} 1987 1988static void tcg_out_jmp(TCGContext *s, const tcg_insn_unit *dest) 1989{ 1990 tcg_out_branch(s, 0, dest); 1991} 1992 1993static void tcg_out_nopn(TCGContext *s, int n) 1994{ 1995 int i; 1996 /* Emit 1 or 2 operand size prefixes for the standard one byte nop, 1997 * "xchg %eax,%eax", forming "xchg %ax,%ax". All cores accept the 1998 * duplicate prefix, and all of the interesting recent cores can 1999 * decode and discard the duplicates in a single cycle. 2000 */ 2001 tcg_debug_assert(n >= 1); 2002 for (i = 1; i < n; ++i) { 2003 tcg_out8(s, 0x66); 2004 } 2005 tcg_out8(s, 0x90); 2006} 2007 2008typedef struct { 2009 TCGReg base; 2010 int index; 2011 int ofs; 2012 int seg; 2013 TCGAtomAlign aa; 2014} HostAddress; 2015 2016bool tcg_target_has_memory_bswap(MemOp memop) 2017{ 2018 TCGAtomAlign aa; 2019 2020 if (!have_movbe) { 2021 return false; 2022 } 2023 if ((memop & MO_SIZE) < MO_128) { 2024 return true; 2025 } 2026 2027 /* 2028 * Reject 16-byte memop with 16-byte atomicity, i.e. VMOVDQA, 2029 * but do allow a pair of 64-bit operations, i.e. MOVBEQ. 2030 */ 2031 aa = atom_and_align_for_opc(tcg_ctx, memop, MO_ATOM_IFALIGN, true); 2032 return aa.atom < MO_128; 2033} 2034 2035/* 2036 * Because i686 has no register parameters and because x86_64 has xchg 2037 * to handle addr/data register overlap, we have placed all input arguments 2038 * before we need might need a scratch reg. 2039 * 2040 * Even then, a scratch is only needed for l->raddr. Rather than expose 2041 * a general-purpose scratch when we don't actually know it's available, 2042 * use the ra_gen hook to load into RAX if needed. 2043 */ 2044#if TCG_TARGET_REG_BITS == 64 2045static TCGReg ldst_ra_gen(TCGContext *s, const TCGLabelQemuLdst *l, int arg) 2046{ 2047 if (arg < 0) { 2048 arg = TCG_REG_RAX; 2049 } 2050 tcg_out_movi(s, TCG_TYPE_PTR, arg, (uintptr_t)l->raddr); 2051 return arg; 2052} 2053static const TCGLdstHelperParam ldst_helper_param = { 2054 .ra_gen = ldst_ra_gen 2055}; 2056#else 2057static const TCGLdstHelperParam ldst_helper_param = { }; 2058#endif 2059 2060static void tcg_out_vec_to_pair(TCGContext *s, TCGType type, 2061 TCGReg l, TCGReg h, TCGReg v) 2062{ 2063 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2064 2065 /* vpmov{d,q} %v, %l */ 2066 tcg_out_vex_modrm(s, OPC_MOVD_EyVy + rexw, v, 0, l); 2067 /* vpextr{d,q} $1, %v, %h */ 2068 tcg_out_vex_modrm(s, OPC_PEXTRD + rexw, v, 0, h); 2069 tcg_out8(s, 1); 2070} 2071 2072static void tcg_out_pair_to_vec(TCGContext *s, TCGType type, 2073 TCGReg v, TCGReg l, TCGReg h) 2074{ 2075 int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2076 2077 /* vmov{d,q} %l, %v */ 2078 tcg_out_vex_modrm(s, OPC_MOVD_VyEy + rexw, v, 0, l); 2079 /* vpinsr{d,q} $1, %h, %v, %v */ 2080 tcg_out_vex_modrm(s, OPC_PINSRD + rexw, v, v, h); 2081 tcg_out8(s, 1); 2082} 2083 2084/* 2085 * Generate code for the slow path for a load at the end of block 2086 */ 2087static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 2088{ 2089 MemOp opc = get_memop(l->oi); 2090 tcg_insn_unit **label_ptr = &l->label_ptr[0]; 2091 2092 /* resolve label address */ 2093 tcg_patch32(label_ptr[0], s->code_ptr - label_ptr[0] - 4); 2094 if (label_ptr[1]) { 2095 tcg_patch32(label_ptr[1], s->code_ptr - label_ptr[1] - 4); 2096 } 2097 2098 tcg_out_ld_helper_args(s, l, &ldst_helper_param); 2099 tcg_out_branch(s, 1, qemu_ld_helpers[opc & MO_SIZE]); 2100 tcg_out_ld_helper_ret(s, l, false, &ldst_helper_param); 2101 2102 tcg_out_jmp(s, l->raddr); 2103 return true; 2104} 2105 2106/* 2107 * Generate code for the slow path for a store at the end of block 2108 */ 2109static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 2110{ 2111 MemOp opc = get_memop(l->oi); 2112 tcg_insn_unit **label_ptr = &l->label_ptr[0]; 2113 2114 /* resolve label address */ 2115 tcg_patch32(label_ptr[0], s->code_ptr - label_ptr[0] - 4); 2116 if (label_ptr[1]) { 2117 tcg_patch32(label_ptr[1], s->code_ptr - label_ptr[1] - 4); 2118 } 2119 2120 tcg_out_st_helper_args(s, l, &ldst_helper_param); 2121 tcg_out_branch(s, 1, qemu_st_helpers[opc & MO_SIZE]); 2122 2123 tcg_out_jmp(s, l->raddr); 2124 return true; 2125} 2126 2127#ifdef CONFIG_USER_ONLY 2128static HostAddress x86_guest_base = { 2129 .index = -1 2130}; 2131 2132#if defined(__x86_64__) && defined(__linux__) 2133# include <asm/prctl.h> 2134# include <sys/prctl.h> 2135int arch_prctl(int code, unsigned long addr); 2136static inline int setup_guest_base_seg(void) 2137{ 2138 if (arch_prctl(ARCH_SET_GS, guest_base) == 0) { 2139 return P_GS; 2140 } 2141 return 0; 2142} 2143#define setup_guest_base_seg setup_guest_base_seg 2144#elif defined(__x86_64__) && \ 2145 (defined (__FreeBSD__) || defined (__FreeBSD_kernel__)) 2146# include <machine/sysarch.h> 2147static inline int setup_guest_base_seg(void) 2148{ 2149 if (sysarch(AMD64_SET_GSBASE, &guest_base) == 0) { 2150 return P_GS; 2151 } 2152 return 0; 2153} 2154#define setup_guest_base_seg setup_guest_base_seg 2155#endif 2156#else 2157# define x86_guest_base (*(HostAddress *)({ qemu_build_not_reached(); NULL; })) 2158#endif /* CONFIG_USER_ONLY */ 2159#ifndef setup_guest_base_seg 2160# define setup_guest_base_seg() 0 2161#endif 2162 2163#define MIN_TLB_MASK_TABLE_OFS INT_MIN 2164 2165/* 2166 * For softmmu, perform the TLB load and compare. 2167 * For useronly, perform any required alignment tests. 2168 * In both cases, return a TCGLabelQemuLdst structure if the slow path 2169 * is required and fill in @h with the host address for the fast path. 2170 */ 2171static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 2172 TCGReg addr, MemOpIdx oi, bool is_ld) 2173{ 2174 TCGLabelQemuLdst *ldst = NULL; 2175 MemOp opc = get_memop(oi); 2176 MemOp s_bits = opc & MO_SIZE; 2177 unsigned a_mask; 2178 2179 if (tcg_use_softmmu) { 2180 h->index = TCG_REG_L0; 2181 h->ofs = 0; 2182 h->seg = 0; 2183 } else { 2184 *h = x86_guest_base; 2185 } 2186 h->base = addr; 2187 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, s_bits == MO_128); 2188 a_mask = (1 << h->aa.align) - 1; 2189 2190 if (tcg_use_softmmu) { 2191 int cmp_ofs = is_ld ? offsetof(CPUTLBEntry, addr_read) 2192 : offsetof(CPUTLBEntry, addr_write); 2193 TCGType ttype = TCG_TYPE_I32; 2194 TCGType tlbtype = TCG_TYPE_I32; 2195 int trexw = 0, hrexw = 0, tlbrexw = 0; 2196 unsigned mem_index = get_mmuidx(oi); 2197 unsigned s_mask = (1 << s_bits) - 1; 2198 int fast_ofs = tlb_mask_table_ofs(s, mem_index); 2199 int tlb_mask; 2200 2201 ldst = new_ldst_label(s); 2202 ldst->is_ld = is_ld; 2203 ldst->oi = oi; 2204 ldst->addr_reg = addr; 2205 2206 if (TCG_TARGET_REG_BITS == 64) { 2207 ttype = s->addr_type; 2208 trexw = (ttype == TCG_TYPE_I32 ? 0 : P_REXW); 2209 if (TCG_TYPE_PTR == TCG_TYPE_I64) { 2210 hrexw = P_REXW; 2211 if (s->page_bits + s->tlb_dyn_max_bits > 32) { 2212 tlbtype = TCG_TYPE_I64; 2213 tlbrexw = P_REXW; 2214 } 2215 } 2216 } 2217 2218 tcg_out_mov(s, tlbtype, TCG_REG_L0, addr); 2219 tcg_out_shifti(s, SHIFT_SHR + tlbrexw, TCG_REG_L0, 2220 s->page_bits - CPU_TLB_ENTRY_BITS); 2221 2222 tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, TCG_REG_L0, TCG_AREG0, 2223 fast_ofs + offsetof(CPUTLBDescFast, mask)); 2224 2225 tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, TCG_REG_L0, TCG_AREG0, 2226 fast_ofs + offsetof(CPUTLBDescFast, table)); 2227 2228 /* 2229 * If the required alignment is at least as large as the access, 2230 * simply copy the address and mask. For lesser alignments, 2231 * check that we don't cross pages for the complete access. 2232 */ 2233 if (a_mask >= s_mask) { 2234 tcg_out_mov(s, ttype, TCG_REG_L1, addr); 2235 } else { 2236 tcg_out_modrm_offset(s, OPC_LEA + trexw, TCG_REG_L1, 2237 addr, s_mask - a_mask); 2238 } 2239 tlb_mask = s->page_mask | a_mask; 2240 tgen_arithi(s, ARITH_AND + trexw, TCG_REG_L1, tlb_mask, 0); 2241 2242 /* cmp 0(TCG_REG_L0), TCG_REG_L1 */ 2243 tcg_out_modrm_offset(s, OPC_CMP_GvEv + trexw, 2244 TCG_REG_L1, TCG_REG_L0, cmp_ofs); 2245 2246 /* jne slow_path */ 2247 tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); 2248 ldst->label_ptr[0] = s->code_ptr; 2249 s->code_ptr += 4; 2250 2251 /* TLB Hit. */ 2252 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_L0, TCG_REG_L0, 2253 offsetof(CPUTLBEntry, addend)); 2254 } else if (a_mask) { 2255 int jcc; 2256 2257 ldst = new_ldst_label(s); 2258 ldst->is_ld = is_ld; 2259 ldst->oi = oi; 2260 ldst->addr_reg = addr; 2261 2262 /* jne slow_path */ 2263 jcc = tcg_out_cmp(s, TCG_COND_TSTNE, addr, a_mask, true, false); 2264 tcg_out_opc(s, OPC_JCC_long + jcc, 0, 0, 0); 2265 ldst->label_ptr[0] = s->code_ptr; 2266 s->code_ptr += 4; 2267 } 2268 2269 return ldst; 2270} 2271 2272static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, 2273 HostAddress h, TCGType type, MemOp memop) 2274{ 2275 bool use_movbe = false; 2276 int rexw = (type == TCG_TYPE_I32 ? 0 : P_REXW); 2277 int movop = OPC_MOVL_GvEv; 2278 2279 /* Do big-endian loads with movbe. */ 2280 if (memop & MO_BSWAP) { 2281 tcg_debug_assert(have_movbe); 2282 use_movbe = true; 2283 movop = OPC_MOVBE_GyMy; 2284 } 2285 2286 switch (memop & MO_SSIZE) { 2287 case MO_UB: 2288 tcg_out_modrm_sib_offset(s, OPC_MOVZBL + h.seg, datalo, 2289 h.base, h.index, 0, h.ofs); 2290 break; 2291 case MO_SB: 2292 tcg_out_modrm_sib_offset(s, OPC_MOVSBL + rexw + h.seg, datalo, 2293 h.base, h.index, 0, h.ofs); 2294 break; 2295 case MO_UW: 2296 if (use_movbe) { 2297 /* There is no extending movbe; only low 16-bits are modified. */ 2298 if (datalo != h.base && datalo != h.index) { 2299 /* XOR breaks dependency chains. */ 2300 tgen_arithr(s, ARITH_XOR, datalo, datalo); 2301 tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + h.seg, 2302 datalo, h.base, h.index, 0, h.ofs); 2303 } else { 2304 tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + h.seg, 2305 datalo, h.base, h.index, 0, h.ofs); 2306 tcg_out_ext16u(s, datalo, datalo); 2307 } 2308 } else { 2309 tcg_out_modrm_sib_offset(s, OPC_MOVZWL + h.seg, datalo, 2310 h.base, h.index, 0, h.ofs); 2311 } 2312 break; 2313 case MO_SW: 2314 if (use_movbe) { 2315 tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + h.seg, 2316 datalo, h.base, h.index, 0, h.ofs); 2317 tcg_out_ext16s(s, type, datalo, datalo); 2318 } else { 2319 tcg_out_modrm_sib_offset(s, OPC_MOVSWL + rexw + h.seg, 2320 datalo, h.base, h.index, 0, h.ofs); 2321 } 2322 break; 2323 case MO_UL: 2324 tcg_out_modrm_sib_offset(s, movop + h.seg, datalo, 2325 h.base, h.index, 0, h.ofs); 2326 break; 2327#if TCG_TARGET_REG_BITS == 64 2328 case MO_SL: 2329 if (use_movbe) { 2330 tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + h.seg, datalo, 2331 h.base, h.index, 0, h.ofs); 2332 tcg_out_ext32s(s, datalo, datalo); 2333 } else { 2334 tcg_out_modrm_sib_offset(s, OPC_MOVSLQ + h.seg, datalo, 2335 h.base, h.index, 0, h.ofs); 2336 } 2337 break; 2338#endif 2339 case MO_UQ: 2340 if (TCG_TARGET_REG_BITS == 64) { 2341 tcg_out_modrm_sib_offset(s, movop + P_REXW + h.seg, datalo, 2342 h.base, h.index, 0, h.ofs); 2343 break; 2344 } 2345 if (use_movbe) { 2346 TCGReg t = datalo; 2347 datalo = datahi; 2348 datahi = t; 2349 } 2350 if (h.base == datalo || h.index == datalo) { 2351 tcg_out_modrm_sib_offset(s, OPC_LEA, datahi, 2352 h.base, h.index, 0, h.ofs); 2353 tcg_out_modrm_offset(s, movop + h.seg, datalo, datahi, 0); 2354 tcg_out_modrm_offset(s, movop + h.seg, datahi, datahi, 4); 2355 } else { 2356 tcg_out_modrm_sib_offset(s, movop + h.seg, datalo, 2357 h.base, h.index, 0, h.ofs); 2358 tcg_out_modrm_sib_offset(s, movop + h.seg, datahi, 2359 h.base, h.index, 0, h.ofs + 4); 2360 } 2361 break; 2362 2363 case MO_128: 2364 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 2365 2366 /* 2367 * Without 16-byte atomicity, use integer regs. 2368 * That is where we want the data, and it allows bswaps. 2369 */ 2370 if (h.aa.atom < MO_128) { 2371 if (use_movbe) { 2372 TCGReg t = datalo; 2373 datalo = datahi; 2374 datahi = t; 2375 } 2376 if (h.base == datalo || h.index == datalo) { 2377 tcg_out_modrm_sib_offset(s, OPC_LEA + P_REXW, datahi, 2378 h.base, h.index, 0, h.ofs); 2379 tcg_out_modrm_offset(s, movop + P_REXW + h.seg, 2380 datalo, datahi, 0); 2381 tcg_out_modrm_offset(s, movop + P_REXW + h.seg, 2382 datahi, datahi, 8); 2383 } else { 2384 tcg_out_modrm_sib_offset(s, movop + P_REXW + h.seg, datalo, 2385 h.base, h.index, 0, h.ofs); 2386 tcg_out_modrm_sib_offset(s, movop + P_REXW + h.seg, datahi, 2387 h.base, h.index, 0, h.ofs + 8); 2388 } 2389 break; 2390 } 2391 2392 /* 2393 * With 16-byte atomicity, a vector load is required. 2394 * If we already have 16-byte alignment, then VMOVDQA always works. 2395 * Else if VMOVDQU has atomicity with dynamic alignment, use that. 2396 * Else use we require a runtime test for alignment for VMOVDQA; 2397 * use VMOVDQU on the unaligned nonatomic path for simplicity. 2398 */ 2399 if (h.aa.align >= MO_128) { 2400 tcg_out_vex_modrm_sib_offset(s, OPC_MOVDQA_VxWx + h.seg, 2401 TCG_TMP_VEC, 0, 2402 h.base, h.index, 0, h.ofs); 2403 } else if (cpuinfo & CPUINFO_ATOMIC_VMOVDQU) { 2404 tcg_out_vex_modrm_sib_offset(s, OPC_MOVDQU_VxWx + h.seg, 2405 TCG_TMP_VEC, 0, 2406 h.base, h.index, 0, h.ofs); 2407 } else { 2408 TCGLabel *l1 = gen_new_label(); 2409 TCGLabel *l2 = gen_new_label(); 2410 int jcc; 2411 2412 jcc = tcg_out_cmp(s, TCG_COND_TSTNE, h.base, 15, true, false); 2413 tcg_out_jxx(s, jcc, l1, true); 2414 2415 tcg_out_vex_modrm_sib_offset(s, OPC_MOVDQA_VxWx + h.seg, 2416 TCG_TMP_VEC, 0, 2417 h.base, h.index, 0, h.ofs); 2418 tcg_out_jxx(s, JCC_JMP, l2, true); 2419 2420 tcg_out_label(s, l1); 2421 tcg_out_vex_modrm_sib_offset(s, OPC_MOVDQU_VxWx + h.seg, 2422 TCG_TMP_VEC, 0, 2423 h.base, h.index, 0, h.ofs); 2424 tcg_out_label(s, l2); 2425 } 2426 tcg_out_vec_to_pair(s, TCG_TYPE_I64, datalo, datahi, TCG_TMP_VEC); 2427 break; 2428 2429 default: 2430 g_assert_not_reached(); 2431 } 2432} 2433 2434static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, 2435 TCGReg addr, MemOpIdx oi, TCGType data_type) 2436{ 2437 TCGLabelQemuLdst *ldst; 2438 HostAddress h; 2439 2440 ldst = prepare_host_addr(s, &h, addr, oi, true); 2441 tcg_out_qemu_ld_direct(s, datalo, datahi, h, data_type, get_memop(oi)); 2442 2443 if (ldst) { 2444 ldst->type = data_type; 2445 ldst->datalo_reg = datalo; 2446 ldst->datahi_reg = datahi; 2447 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 2448 } 2449} 2450 2451static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, 2452 HostAddress h, MemOp memop) 2453{ 2454 bool use_movbe = false; 2455 int movop = OPC_MOVL_EvGv; 2456 2457 /* 2458 * Do big-endian stores with movbe or system-mode. 2459 * User-only without movbe will have its swapping done generically. 2460 */ 2461 if (memop & MO_BSWAP) { 2462 tcg_debug_assert(have_movbe); 2463 use_movbe = true; 2464 movop = OPC_MOVBE_MyGy; 2465 } 2466 2467 switch (memop & MO_SIZE) { 2468 case MO_8: 2469 /* This is handled with constraints on INDEX_op_qemu_st8_i32. */ 2470 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || datalo < 4); 2471 tcg_out_modrm_sib_offset(s, OPC_MOVB_EvGv + P_REXB_R + h.seg, 2472 datalo, h.base, h.index, 0, h.ofs); 2473 break; 2474 case MO_16: 2475 tcg_out_modrm_sib_offset(s, movop + P_DATA16 + h.seg, datalo, 2476 h.base, h.index, 0, h.ofs); 2477 break; 2478 case MO_32: 2479 tcg_out_modrm_sib_offset(s, movop + h.seg, datalo, 2480 h.base, h.index, 0, h.ofs); 2481 break; 2482 case MO_64: 2483 if (TCG_TARGET_REG_BITS == 64) { 2484 tcg_out_modrm_sib_offset(s, movop + P_REXW + h.seg, datalo, 2485 h.base, h.index, 0, h.ofs); 2486 } else { 2487 if (use_movbe) { 2488 TCGReg t = datalo; 2489 datalo = datahi; 2490 datahi = t; 2491 } 2492 tcg_out_modrm_sib_offset(s, movop + h.seg, datalo, 2493 h.base, h.index, 0, h.ofs); 2494 tcg_out_modrm_sib_offset(s, movop + h.seg, datahi, 2495 h.base, h.index, 0, h.ofs + 4); 2496 } 2497 break; 2498 2499 case MO_128: 2500 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 2501 2502 /* 2503 * Without 16-byte atomicity, use integer regs. 2504 * That is where we have the data, and it allows bswaps. 2505 */ 2506 if (h.aa.atom < MO_128) { 2507 if (use_movbe) { 2508 TCGReg t = datalo; 2509 datalo = datahi; 2510 datahi = t; 2511 } 2512 tcg_out_modrm_sib_offset(s, movop + P_REXW + h.seg, datalo, 2513 h.base, h.index, 0, h.ofs); 2514 tcg_out_modrm_sib_offset(s, movop + P_REXW + h.seg, datahi, 2515 h.base, h.index, 0, h.ofs + 8); 2516 break; 2517 } 2518 2519 /* 2520 * With 16-byte atomicity, a vector store is required. 2521 * If we already have 16-byte alignment, then VMOVDQA always works. 2522 * Else if VMOVDQU has atomicity with dynamic alignment, use that. 2523 * Else use we require a runtime test for alignment for VMOVDQA; 2524 * use VMOVDQU on the unaligned nonatomic path for simplicity. 2525 */ 2526 tcg_out_pair_to_vec(s, TCG_TYPE_I64, TCG_TMP_VEC, datalo, datahi); 2527 if (h.aa.align >= MO_128) { 2528 tcg_out_vex_modrm_sib_offset(s, OPC_MOVDQA_WxVx + h.seg, 2529 TCG_TMP_VEC, 0, 2530 h.base, h.index, 0, h.ofs); 2531 } else if (cpuinfo & CPUINFO_ATOMIC_VMOVDQU) { 2532 tcg_out_vex_modrm_sib_offset(s, OPC_MOVDQU_WxVx + h.seg, 2533 TCG_TMP_VEC, 0, 2534 h.base, h.index, 0, h.ofs); 2535 } else { 2536 TCGLabel *l1 = gen_new_label(); 2537 TCGLabel *l2 = gen_new_label(); 2538 int jcc; 2539 2540 jcc = tcg_out_cmp(s, TCG_COND_TSTNE, h.base, 15, true, false); 2541 tcg_out_jxx(s, jcc, l1, true); 2542 2543 tcg_out_vex_modrm_sib_offset(s, OPC_MOVDQA_WxVx + h.seg, 2544 TCG_TMP_VEC, 0, 2545 h.base, h.index, 0, h.ofs); 2546 tcg_out_jxx(s, JCC_JMP, l2, true); 2547 2548 tcg_out_label(s, l1); 2549 tcg_out_vex_modrm_sib_offset(s, OPC_MOVDQU_WxVx + h.seg, 2550 TCG_TMP_VEC, 0, 2551 h.base, h.index, 0, h.ofs); 2552 tcg_out_label(s, l2); 2553 } 2554 break; 2555 2556 default: 2557 g_assert_not_reached(); 2558 } 2559} 2560 2561static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, 2562 TCGReg addr, MemOpIdx oi, TCGType data_type) 2563{ 2564 TCGLabelQemuLdst *ldst; 2565 HostAddress h; 2566 2567 ldst = prepare_host_addr(s, &h, addr, oi, false); 2568 tcg_out_qemu_st_direct(s, datalo, datahi, h, get_memop(oi)); 2569 2570 if (ldst) { 2571 ldst->type = data_type; 2572 ldst->datalo_reg = datalo; 2573 ldst->datahi_reg = datahi; 2574 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 2575 } 2576} 2577 2578static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 2579{ 2580 /* Reuse the zeroing that exists for goto_ptr. */ 2581 if (a0 == 0) { 2582 tcg_out_jmp(s, tcg_code_gen_epilogue); 2583 } else { 2584 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_EAX, a0); 2585 tcg_out_jmp(s, tb_ret_addr); 2586 } 2587} 2588 2589static void tcg_out_goto_tb(TCGContext *s, int which) 2590{ 2591 /* 2592 * Jump displacement must be aligned for atomic patching; 2593 * see if we need to add extra nops before jump 2594 */ 2595 int gap = QEMU_ALIGN_PTR_UP(s->code_ptr + 1, 4) - s->code_ptr; 2596 if (gap != 1) { 2597 tcg_out_nopn(s, gap - 1); 2598 } 2599 tcg_out8(s, OPC_JMP_long); /* jmp im */ 2600 set_jmp_insn_offset(s, which); 2601 tcg_out32(s, 0); 2602 set_jmp_reset_offset(s, which); 2603} 2604 2605void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 2606 uintptr_t jmp_rx, uintptr_t jmp_rw) 2607{ 2608 /* patch the branch destination */ 2609 uintptr_t addr = tb->jmp_target_addr[n]; 2610 qatomic_set((int32_t *)jmp_rw, addr - (jmp_rx + 4)); 2611 /* no need to flush icache explicitly */ 2612} 2613 2614static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, 2615 const TCGArg args[TCG_MAX_OP_ARGS], 2616 const int const_args[TCG_MAX_OP_ARGS]) 2617{ 2618 TCGArg a0, a1, a2; 2619 int c, const_a2, vexop, rexw; 2620 2621#if TCG_TARGET_REG_BITS == 64 2622# define OP_32_64(x) \ 2623 case glue(glue(INDEX_op_, x), _i64): \ 2624 case glue(glue(INDEX_op_, x), _i32) 2625#else 2626# define OP_32_64(x) \ 2627 case glue(glue(INDEX_op_, x), _i32) 2628#endif 2629 2630 /* Hoist the loads of the most common arguments. */ 2631 a0 = args[0]; 2632 a1 = args[1]; 2633 a2 = args[2]; 2634 const_a2 = const_args[2]; 2635 rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; 2636 2637 switch (opc) { 2638 case INDEX_op_goto_ptr: 2639 /* jmp to the given host address (could be epilogue) */ 2640 tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, a0); 2641 break; 2642 case INDEX_op_br: 2643 tcg_out_jxx(s, JCC_JMP, arg_label(a0), 0); 2644 break; 2645 OP_32_64(ld8u): 2646 /* Note that we can ignore REXW for the zero-extend to 64-bit. */ 2647 tcg_out_modrm_offset(s, OPC_MOVZBL, a0, a1, a2); 2648 break; 2649 OP_32_64(ld8s): 2650 tcg_out_modrm_offset(s, OPC_MOVSBL + rexw, a0, a1, a2); 2651 break; 2652 OP_32_64(ld16u): 2653 /* Note that we can ignore REXW for the zero-extend to 64-bit. */ 2654 tcg_out_modrm_offset(s, OPC_MOVZWL, a0, a1, a2); 2655 break; 2656 OP_32_64(ld16s): 2657 tcg_out_modrm_offset(s, OPC_MOVSWL + rexw, a0, a1, a2); 2658 break; 2659#if TCG_TARGET_REG_BITS == 64 2660 case INDEX_op_ld32u_i64: 2661#endif 2662 case INDEX_op_ld_i32: 2663 tcg_out_ld(s, TCG_TYPE_I32, a0, a1, a2); 2664 break; 2665 2666 OP_32_64(st8): 2667 if (const_args[0]) { 2668 tcg_out_modrm_offset(s, OPC_MOVB_EvIz, 0, a1, a2); 2669 tcg_out8(s, a0); 2670 } else { 2671 tcg_out_modrm_offset(s, OPC_MOVB_EvGv | P_REXB_R, a0, a1, a2); 2672 } 2673 break; 2674 OP_32_64(st16): 2675 if (const_args[0]) { 2676 tcg_out_modrm_offset(s, OPC_MOVL_EvIz | P_DATA16, 0, a1, a2); 2677 tcg_out16(s, a0); 2678 } else { 2679 tcg_out_modrm_offset(s, OPC_MOVL_EvGv | P_DATA16, a0, a1, a2); 2680 } 2681 break; 2682#if TCG_TARGET_REG_BITS == 64 2683 case INDEX_op_st32_i64: 2684#endif 2685 case INDEX_op_st_i32: 2686 if (const_args[0]) { 2687 tcg_out_modrm_offset(s, OPC_MOVL_EvIz, 0, a1, a2); 2688 tcg_out32(s, a0); 2689 } else { 2690 tcg_out_st(s, TCG_TYPE_I32, a0, a1, a2); 2691 } 2692 break; 2693 2694 OP_32_64(add): 2695 /* For 3-operand addition, use LEA. */ 2696 if (a0 != a1) { 2697 TCGArg c3 = 0; 2698 if (const_a2) { 2699 c3 = a2, a2 = -1; 2700 } else if (a0 == a2) { 2701 /* Watch out for dest = src + dest, since we've removed 2702 the matching constraint on the add. */ 2703 tgen_arithr(s, ARITH_ADD + rexw, a0, a1); 2704 break; 2705 } 2706 2707 tcg_out_modrm_sib_offset(s, OPC_LEA + rexw, a0, a1, a2, 0, c3); 2708 break; 2709 } 2710 c = ARITH_ADD; 2711 goto gen_arith; 2712 OP_32_64(sub): 2713 c = ARITH_SUB; 2714 goto gen_arith; 2715 OP_32_64(and): 2716 c = ARITH_AND; 2717 goto gen_arith; 2718 OP_32_64(or): 2719 c = ARITH_OR; 2720 goto gen_arith; 2721 OP_32_64(xor): 2722 c = ARITH_XOR; 2723 goto gen_arith; 2724 gen_arith: 2725 if (const_a2) { 2726 tgen_arithi(s, c + rexw, a0, a2, 0); 2727 } else { 2728 tgen_arithr(s, c + rexw, a0, a2); 2729 } 2730 break; 2731 2732 OP_32_64(andc): 2733 if (const_a2) { 2734 tcg_out_mov(s, rexw ? TCG_TYPE_I64 : TCG_TYPE_I32, a0, a1); 2735 tgen_arithi(s, ARITH_AND + rexw, a0, ~a2, 0); 2736 } else { 2737 tcg_out_vex_modrm(s, OPC_ANDN + rexw, a0, a2, a1); 2738 } 2739 break; 2740 2741 OP_32_64(mul): 2742 if (const_a2) { 2743 int32_t val; 2744 val = a2; 2745 if (val == (int8_t)val) { 2746 tcg_out_modrm(s, OPC_IMUL_GvEvIb + rexw, a0, a0); 2747 tcg_out8(s, val); 2748 } else { 2749 tcg_out_modrm(s, OPC_IMUL_GvEvIz + rexw, a0, a0); 2750 tcg_out32(s, val); 2751 } 2752 } else { 2753 tcg_out_modrm(s, OPC_IMUL_GvEv + rexw, a0, a2); 2754 } 2755 break; 2756 2757 OP_32_64(div2): 2758 tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_IDIV, args[4]); 2759 break; 2760 OP_32_64(divu2): 2761 tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_DIV, args[4]); 2762 break; 2763 2764 OP_32_64(shl): 2765 /* For small constant 3-operand shift, use LEA. */ 2766 if (const_a2 && a0 != a1 && (a2 - 1) < 3) { 2767 if (a2 - 1 == 0) { 2768 /* shl $1,a1,a0 -> lea (a1,a1),a0 */ 2769 tcg_out_modrm_sib_offset(s, OPC_LEA + rexw, a0, a1, a1, 0, 0); 2770 } else { 2771 /* shl $n,a1,a0 -> lea 0(,a1,n),a0 */ 2772 tcg_out_modrm_sib_offset(s, OPC_LEA + rexw, a0, -1, a1, a2, 0); 2773 } 2774 break; 2775 } 2776 c = SHIFT_SHL; 2777 vexop = OPC_SHLX; 2778 goto gen_shift_maybe_vex; 2779 OP_32_64(shr): 2780 c = SHIFT_SHR; 2781 vexop = OPC_SHRX; 2782 goto gen_shift_maybe_vex; 2783 OP_32_64(sar): 2784 c = SHIFT_SAR; 2785 vexop = OPC_SARX; 2786 goto gen_shift_maybe_vex; 2787 OP_32_64(rotl): 2788 c = SHIFT_ROL; 2789 goto gen_shift; 2790 OP_32_64(rotr): 2791 c = SHIFT_ROR; 2792 goto gen_shift; 2793 gen_shift_maybe_vex: 2794 if (have_bmi2) { 2795 if (!const_a2) { 2796 tcg_out_vex_modrm(s, vexop + rexw, a0, a2, a1); 2797 break; 2798 } 2799 tcg_out_mov(s, rexw ? TCG_TYPE_I64 : TCG_TYPE_I32, a0, a1); 2800 } 2801 /* FALLTHRU */ 2802 gen_shift: 2803 if (const_a2) { 2804 tcg_out_shifti(s, c + rexw, a0, a2); 2805 } else { 2806 tcg_out_modrm(s, OPC_SHIFT_cl + rexw, c, a0); 2807 } 2808 break; 2809 2810 OP_32_64(ctz): 2811 tcg_out_ctz(s, rexw, args[0], args[1], args[2], const_args[2]); 2812 break; 2813 OP_32_64(clz): 2814 tcg_out_clz(s, rexw, args[0], args[1], args[2], const_args[2]); 2815 break; 2816 OP_32_64(ctpop): 2817 tcg_out_modrm(s, OPC_POPCNT + rexw, a0, a1); 2818 break; 2819 2820 OP_32_64(brcond): 2821 tcg_out_brcond(s, rexw, a2, a0, a1, const_args[1], 2822 arg_label(args[3]), 0); 2823 break; 2824 OP_32_64(setcond): 2825 tcg_out_setcond(s, rexw, args[3], a0, a1, a2, const_a2, false); 2826 break; 2827 OP_32_64(negsetcond): 2828 tcg_out_setcond(s, rexw, args[3], a0, a1, a2, const_a2, true); 2829 break; 2830 OP_32_64(movcond): 2831 tcg_out_movcond(s, rexw, args[5], a0, a1, a2, const_a2, args[3]); 2832 break; 2833 2834 OP_32_64(bswap16): 2835 if (a2 & TCG_BSWAP_OS) { 2836 /* Output must be sign-extended. */ 2837 if (rexw) { 2838 tcg_out_bswap64(s, a0); 2839 tcg_out_shifti(s, SHIFT_SAR + rexw, a0, 48); 2840 } else { 2841 tcg_out_bswap32(s, a0); 2842 tcg_out_shifti(s, SHIFT_SAR, a0, 16); 2843 } 2844 } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 2845 /* Output must be zero-extended, but input isn't. */ 2846 tcg_out_bswap32(s, a0); 2847 tcg_out_shifti(s, SHIFT_SHR, a0, 16); 2848 } else { 2849 tcg_out_rolw_8(s, a0); 2850 } 2851 break; 2852 OP_32_64(bswap32): 2853 tcg_out_bswap32(s, a0); 2854 if (rexw && (a2 & TCG_BSWAP_OS)) { 2855 tcg_out_ext32s(s, a0, a0); 2856 } 2857 break; 2858 2859 OP_32_64(neg): 2860 tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NEG, a0); 2861 break; 2862 OP_32_64(not): 2863 tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NOT, a0); 2864 break; 2865 2866 case INDEX_op_qemu_ld_i32: 2867 tcg_out_qemu_ld(s, a0, -1, a1, a2, TCG_TYPE_I32); 2868 break; 2869 case INDEX_op_qemu_ld_i64: 2870 if (TCG_TARGET_REG_BITS == 64) { 2871 tcg_out_qemu_ld(s, a0, -1, a1, a2, TCG_TYPE_I64); 2872 } else { 2873 tcg_out_qemu_ld(s, a0, a1, a2, args[3], TCG_TYPE_I64); 2874 } 2875 break; 2876 case INDEX_op_qemu_ld_i128: 2877 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 2878 tcg_out_qemu_ld(s, a0, a1, a2, args[3], TCG_TYPE_I128); 2879 break; 2880 2881 case INDEX_op_qemu_st_i32: 2882 case INDEX_op_qemu_st8_i32: 2883 tcg_out_qemu_st(s, a0, -1, a1, a2, TCG_TYPE_I32); 2884 break; 2885 case INDEX_op_qemu_st_i64: 2886 if (TCG_TARGET_REG_BITS == 64) { 2887 tcg_out_qemu_st(s, a0, -1, a1, a2, TCG_TYPE_I64); 2888 } else { 2889 tcg_out_qemu_st(s, a0, a1, a2, args[3], TCG_TYPE_I64); 2890 } 2891 break; 2892 case INDEX_op_qemu_st_i128: 2893 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 2894 tcg_out_qemu_st(s, a0, a1, a2, args[3], TCG_TYPE_I128); 2895 break; 2896 2897 OP_32_64(mulu2): 2898 tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_MUL, args[3]); 2899 break; 2900 OP_32_64(muls2): 2901 tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_IMUL, args[3]); 2902 break; 2903 OP_32_64(add2): 2904 if (const_args[4]) { 2905 tgen_arithi(s, ARITH_ADD + rexw, a0, args[4], 1); 2906 } else { 2907 tgen_arithr(s, ARITH_ADD + rexw, a0, args[4]); 2908 } 2909 if (const_args[5]) { 2910 tgen_arithi(s, ARITH_ADC + rexw, a1, args[5], 1); 2911 } else { 2912 tgen_arithr(s, ARITH_ADC + rexw, a1, args[5]); 2913 } 2914 break; 2915 OP_32_64(sub2): 2916 if (const_args[4]) { 2917 tgen_arithi(s, ARITH_SUB + rexw, a0, args[4], 1); 2918 } else { 2919 tgen_arithr(s, ARITH_SUB + rexw, a0, args[4]); 2920 } 2921 if (const_args[5]) { 2922 tgen_arithi(s, ARITH_SBB + rexw, a1, args[5], 1); 2923 } else { 2924 tgen_arithr(s, ARITH_SBB + rexw, a1, args[5]); 2925 } 2926 break; 2927 2928#if TCG_TARGET_REG_BITS == 32 2929 case INDEX_op_brcond2_i32: 2930 tcg_out_brcond2(s, args, const_args, 0); 2931 break; 2932 case INDEX_op_setcond2_i32: 2933 tcg_out_setcond2(s, args, const_args); 2934 break; 2935#else /* TCG_TARGET_REG_BITS == 64 */ 2936 case INDEX_op_ld32s_i64: 2937 tcg_out_modrm_offset(s, OPC_MOVSLQ, a0, a1, a2); 2938 break; 2939 case INDEX_op_ld_i64: 2940 tcg_out_ld(s, TCG_TYPE_I64, a0, a1, a2); 2941 break; 2942 case INDEX_op_st_i64: 2943 if (const_args[0]) { 2944 tcg_out_modrm_offset(s, OPC_MOVL_EvIz | P_REXW, 0, a1, a2); 2945 tcg_out32(s, a0); 2946 } else { 2947 tcg_out_st(s, TCG_TYPE_I64, a0, a1, a2); 2948 } 2949 break; 2950 2951 case INDEX_op_bswap64_i64: 2952 tcg_out_bswap64(s, a0); 2953 break; 2954 case INDEX_op_extrh_i64_i32: 2955 tcg_out_shifti(s, SHIFT_SHR + P_REXW, a0, 32); 2956 break; 2957#endif 2958 2959 OP_32_64(deposit): 2960 if (args[3] == 0 && args[4] == 8) { 2961 /* load bits 0..7 */ 2962 if (const_a2) { 2963 tcg_out_opc(s, OPC_MOVB_Ib | P_REXB_RM | LOWREGMASK(a0), 2964 0, a0, 0); 2965 tcg_out8(s, a2); 2966 } else { 2967 tcg_out_modrm(s, OPC_MOVB_EvGv | P_REXB_R | P_REXB_RM, a2, a0); 2968 } 2969 } else if (TCG_TARGET_REG_BITS == 32 && args[3] == 8 && args[4] == 8) { 2970 /* load bits 8..15 */ 2971 if (const_a2) { 2972 tcg_out8(s, OPC_MOVB_Ib + a0 + 4); 2973 tcg_out8(s, a2); 2974 } else { 2975 tcg_out_modrm(s, OPC_MOVB_EvGv, a2, a0 + 4); 2976 } 2977 } else if (args[3] == 0 && args[4] == 16) { 2978 /* load bits 0..15 */ 2979 if (const_a2) { 2980 tcg_out_opc(s, OPC_MOVL_Iv | P_DATA16 | LOWREGMASK(a0), 2981 0, a0, 0); 2982 tcg_out16(s, a2); 2983 } else { 2984 tcg_out_modrm(s, OPC_MOVL_EvGv | P_DATA16, a2, a0); 2985 } 2986 } else { 2987 g_assert_not_reached(); 2988 } 2989 break; 2990 2991 case INDEX_op_extract_i64: 2992 if (a2 + args[3] == 32) { 2993 if (a2 == 0) { 2994 tcg_out_ext32u(s, a0, a1); 2995 break; 2996 } 2997 /* This is a 32-bit zero-extending right shift. */ 2998 tcg_out_mov(s, TCG_TYPE_I32, a0, a1); 2999 tcg_out_shifti(s, SHIFT_SHR, a0, a2); 3000 break; 3001 } 3002 /* FALLTHRU */ 3003 case INDEX_op_extract_i32: 3004 if (a2 == 0 && args[3] == 8) { 3005 tcg_out_ext8u(s, a0, a1); 3006 } else if (a2 == 0 && args[3] == 16) { 3007 tcg_out_ext16u(s, a0, a1); 3008 } else if (a2 == 8 && args[3] == 8) { 3009 /* 3010 * On the off-chance that we can use the high-byte registers. 3011 * Otherwise we emit the same ext16 + shift pattern that we 3012 * would have gotten from the normal tcg-op.c expansion. 3013 */ 3014 if (a1 < 4 && a0 < 8) { 3015 tcg_out_modrm(s, OPC_MOVZBL, a0, a1 + 4); 3016 } else { 3017 tcg_out_ext16u(s, a0, a1); 3018 tcg_out_shifti(s, SHIFT_SHR, a0, 8); 3019 } 3020 } else { 3021 g_assert_not_reached(); 3022 } 3023 break; 3024 3025 case INDEX_op_sextract_i64: 3026 if (a2 == 0 && args[3] == 8) { 3027 tcg_out_ext8s(s, TCG_TYPE_I64, a0, a1); 3028 } else if (a2 == 0 && args[3] == 16) { 3029 tcg_out_ext16s(s, TCG_TYPE_I64, a0, a1); 3030 } else if (a2 == 0 && args[3] == 32) { 3031 tcg_out_ext32s(s, a0, a1); 3032 } else { 3033 g_assert_not_reached(); 3034 } 3035 break; 3036 3037 case INDEX_op_sextract_i32: 3038 if (a2 == 0 && args[3] == 8) { 3039 tcg_out_ext8s(s, TCG_TYPE_I32, a0, a1); 3040 } else if (a2 == 0 && args[3] == 16) { 3041 tcg_out_ext16s(s, TCG_TYPE_I32, a0, a1); 3042 } else if (a2 == 8 && args[3] == 8) { 3043 if (a1 < 4 && a0 < 8) { 3044 tcg_out_modrm(s, OPC_MOVSBL, a0, a1 + 4); 3045 } else { 3046 tcg_out_ext16s(s, TCG_TYPE_I32, a0, a1); 3047 tcg_out_shifti(s, SHIFT_SAR, a0, 8); 3048 } 3049 } else { 3050 g_assert_not_reached(); 3051 } 3052 break; 3053 3054 OP_32_64(extract2): 3055 /* Note that SHRD outputs to the r/m operand. */ 3056 tcg_out_modrm(s, OPC_SHRD_Ib + rexw, a2, a0); 3057 tcg_out8(s, args[3]); 3058 break; 3059 3060 case INDEX_op_mb: 3061 tcg_out_mb(s, a0); 3062 break; 3063 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ 3064 case INDEX_op_mov_i64: 3065 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 3066 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 3067 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 3068 case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ 3069 case INDEX_op_ext8s_i64: 3070 case INDEX_op_ext8u_i32: 3071 case INDEX_op_ext8u_i64: 3072 case INDEX_op_ext16s_i32: 3073 case INDEX_op_ext16s_i64: 3074 case INDEX_op_ext16u_i32: 3075 case INDEX_op_ext16u_i64: 3076 case INDEX_op_ext32s_i64: 3077 case INDEX_op_ext32u_i64: 3078 case INDEX_op_ext_i32_i64: 3079 case INDEX_op_extu_i32_i64: 3080 case INDEX_op_extrl_i64_i32: 3081 default: 3082 g_assert_not_reached(); 3083 } 3084 3085#undef OP_32_64 3086} 3087 3088static int const umin_insn[4] = { 3089 OPC_PMINUB, OPC_PMINUW, OPC_PMINUD, OPC_VPMINUQ 3090}; 3091 3092static int const umax_insn[4] = { 3093 OPC_PMAXUB, OPC_PMAXUW, OPC_PMAXUD, OPC_VPMAXUQ 3094}; 3095 3096static bool tcg_out_cmp_vec_noinv(TCGContext *s, TCGType type, unsigned vece, 3097 TCGReg v0, TCGReg v1, TCGReg v2, TCGCond cond) 3098{ 3099 static int const cmpeq_insn[4] = { 3100 OPC_PCMPEQB, OPC_PCMPEQW, OPC_PCMPEQD, OPC_PCMPEQQ 3101 }; 3102 static int const cmpgt_insn[4] = { 3103 OPC_PCMPGTB, OPC_PCMPGTW, OPC_PCMPGTD, OPC_PCMPGTQ 3104 }; 3105 3106 enum { 3107 NEED_INV = 1, 3108 NEED_SWAP = 2, 3109 NEED_UMIN = 4, 3110 NEED_UMAX = 8, 3111 INVALID = 16, 3112 }; 3113 static const uint8_t cond_fixup[16] = { 3114 [0 ... 15] = INVALID, 3115 [TCG_COND_EQ] = 0, 3116 [TCG_COND_GT] = 0, 3117 [TCG_COND_NE] = NEED_INV, 3118 [TCG_COND_LE] = NEED_INV, 3119 [TCG_COND_LT] = NEED_SWAP, 3120 [TCG_COND_GE] = NEED_SWAP | NEED_INV, 3121 [TCG_COND_LEU] = NEED_UMIN, 3122 [TCG_COND_GTU] = NEED_UMIN | NEED_INV, 3123 [TCG_COND_GEU] = NEED_UMAX, 3124 [TCG_COND_LTU] = NEED_UMAX | NEED_INV, 3125 }; 3126 int fixup = cond_fixup[cond]; 3127 3128 assert(!(fixup & INVALID)); 3129 3130 if (fixup & NEED_INV) { 3131 cond = tcg_invert_cond(cond); 3132 } 3133 3134 if (fixup & NEED_SWAP) { 3135 TCGReg swap = v1; 3136 v1 = v2; 3137 v2 = swap; 3138 cond = tcg_swap_cond(cond); 3139 } 3140 3141 if (fixup & (NEED_UMIN | NEED_UMAX)) { 3142 int op = (fixup & NEED_UMIN ? umin_insn[vece] : umax_insn[vece]); 3143 3144 /* avx2 does not have 64-bit min/max; adjusted during expand. */ 3145 assert(vece <= MO_32); 3146 3147 tcg_out_vex_modrm_type(s, op, TCG_TMP_VEC, v1, v2, type); 3148 v2 = TCG_TMP_VEC; 3149 cond = TCG_COND_EQ; 3150 } 3151 3152 switch (cond) { 3153 case TCG_COND_EQ: 3154 tcg_out_vex_modrm_type(s, cmpeq_insn[vece], v0, v1, v2, type); 3155 break; 3156 case TCG_COND_GT: 3157 tcg_out_vex_modrm_type(s, cmpgt_insn[vece], v0, v1, v2, type); 3158 break; 3159 default: 3160 g_assert_not_reached(); 3161 } 3162 return fixup & NEED_INV; 3163} 3164 3165static void tcg_out_cmp_vec_k1(TCGContext *s, TCGType type, unsigned vece, 3166 TCGReg v1, TCGReg v2, TCGCond cond) 3167{ 3168 static const int cmpm_insn[2][4] = { 3169 { OPC_VPCMPB, OPC_VPCMPW, OPC_VPCMPD, OPC_VPCMPQ }, 3170 { OPC_VPCMPUB, OPC_VPCMPUW, OPC_VPCMPUD, OPC_VPCMPUQ } 3171 }; 3172 static const int testm_insn[4] = { 3173 OPC_VPTESTMB, OPC_VPTESTMW, OPC_VPTESTMD, OPC_VPTESTMQ 3174 }; 3175 static const int testnm_insn[4] = { 3176 OPC_VPTESTNMB, OPC_VPTESTNMW, OPC_VPTESTNMD, OPC_VPTESTNMQ 3177 }; 3178 3179 static const int cond_ext[16] = { 3180 [TCG_COND_EQ] = 0, 3181 [TCG_COND_NE] = 4, 3182 [TCG_COND_LT] = 1, 3183 [TCG_COND_LTU] = 1, 3184 [TCG_COND_LE] = 2, 3185 [TCG_COND_LEU] = 2, 3186 [TCG_COND_NEVER] = 3, 3187 [TCG_COND_GE] = 5, 3188 [TCG_COND_GEU] = 5, 3189 [TCG_COND_GT] = 6, 3190 [TCG_COND_GTU] = 6, 3191 [TCG_COND_ALWAYS] = 7, 3192 }; 3193 3194 switch (cond) { 3195 case TCG_COND_TSTNE: 3196 tcg_out_vex_modrm_type(s, testm_insn[vece], /* k1 */ 1, v1, v2, type); 3197 break; 3198 case TCG_COND_TSTEQ: 3199 tcg_out_vex_modrm_type(s, testnm_insn[vece], /* k1 */ 1, v1, v2, type); 3200 break; 3201 default: 3202 tcg_out_vex_modrm_type(s, cmpm_insn[is_unsigned_cond(cond)][vece], 3203 /* k1 */ 1, v1, v2, type); 3204 tcg_out8(s, cond_ext[cond]); 3205 break; 3206 } 3207} 3208 3209static void tcg_out_k1_to_vec(TCGContext *s, TCGType type, 3210 unsigned vece, TCGReg dest) 3211{ 3212 static const int movm_insn[] = { 3213 OPC_VPMOVM2B, OPC_VPMOVM2W, OPC_VPMOVM2D, OPC_VPMOVM2Q 3214 }; 3215 tcg_out_vex_modrm_type(s, movm_insn[vece], dest, 0, /* k1 */ 1, type); 3216} 3217 3218static void tcg_out_cmp_vec(TCGContext *s, TCGType type, unsigned vece, 3219 TCGReg v0, TCGReg v1, TCGReg v2, TCGCond cond) 3220{ 3221 /* 3222 * With avx512, we have a complete set of comparisons into mask. 3223 * Unless there's a single insn expansion for the comparision, 3224 * expand via a mask in k1. 3225 */ 3226 if ((vece <= MO_16 ? have_avx512bw : have_avx512dq) 3227 && cond != TCG_COND_EQ 3228 && cond != TCG_COND_LT 3229 && cond != TCG_COND_GT) { 3230 tcg_out_cmp_vec_k1(s, type, vece, v1, v2, cond); 3231 tcg_out_k1_to_vec(s, type, vece, v0); 3232 return; 3233 } 3234 3235 if (tcg_out_cmp_vec_noinv(s, type, vece, v0, v1, v2, cond)) { 3236 tcg_out_dupi_vec(s, type, vece, TCG_TMP_VEC, -1); 3237 tcg_out_vex_modrm_type(s, OPC_PXOR, v0, v0, TCG_TMP_VEC, type); 3238 } 3239} 3240 3241static void tcg_out_cmpsel_vec_k1(TCGContext *s, TCGType type, unsigned vece, 3242 TCGReg v0, TCGReg c1, TCGReg c2, 3243 TCGReg v3, TCGReg v4, TCGCond cond) 3244{ 3245 static const int vpblendm_insn[] = { 3246 OPC_VPBLENDMB, OPC_VPBLENDMW, OPC_VPBLENDMD, OPC_VPBLENDMQ 3247 }; 3248 bool z = false; 3249 3250 /* Swap to place constant in V4 to take advantage of zero-masking. */ 3251 if (!v3) { 3252 z = true; 3253 v3 = v4; 3254 cond = tcg_invert_cond(cond); 3255 } 3256 3257 tcg_out_cmp_vec_k1(s, type, vece, c1, c2, cond); 3258 tcg_out_evex_modrm_type(s, vpblendm_insn[vece], v0, v4, v3, 3259 /* k1 */1, z, type); 3260} 3261 3262static void tcg_out_cmpsel_vec(TCGContext *s, TCGType type, unsigned vece, 3263 TCGReg v0, TCGReg c1, TCGReg c2, 3264 TCGReg v3, TCGReg v4, TCGCond cond) 3265{ 3266 bool inv; 3267 3268 if (vece <= MO_16 ? have_avx512bw : have_avx512vl) { 3269 tcg_out_cmpsel_vec_k1(s, type, vece, v0, c1, c2, v3, v4, cond); 3270 return; 3271 } 3272 3273 inv = tcg_out_cmp_vec_noinv(s, type, vece, TCG_TMP_VEC, c1, c2, cond); 3274 3275 /* 3276 * Since XMM0 is 16, the only way we get 0 into V3 3277 * is via the constant zero constraint. 3278 */ 3279 if (!v3) { 3280 if (inv) { 3281 tcg_out_vex_modrm_type(s, OPC_PAND, v0, TCG_TMP_VEC, v4, type); 3282 } else { 3283 tcg_out_vex_modrm_type(s, OPC_PANDN, v0, TCG_TMP_VEC, v4, type); 3284 } 3285 } else { 3286 if (inv) { 3287 TCGReg swap = v3; 3288 v3 = v4; 3289 v4 = swap; 3290 } 3291 tcg_out_vex_modrm_type(s, OPC_VPBLENDVB, v0, v4, v3, type); 3292 tcg_out8(s, (TCG_TMP_VEC - TCG_REG_XMM0) << 4); 3293 } 3294} 3295 3296static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 3297 unsigned vecl, unsigned vece, 3298 const TCGArg args[TCG_MAX_OP_ARGS], 3299 const int const_args[TCG_MAX_OP_ARGS]) 3300{ 3301 static int const add_insn[4] = { 3302 OPC_PADDB, OPC_PADDW, OPC_PADDD, OPC_PADDQ 3303 }; 3304 static int const ssadd_insn[4] = { 3305 OPC_PADDSB, OPC_PADDSW, OPC_UD2, OPC_UD2 3306 }; 3307 static int const usadd_insn[4] = { 3308 OPC_PADDUB, OPC_PADDUW, OPC_UD2, OPC_UD2 3309 }; 3310 static int const sub_insn[4] = { 3311 OPC_PSUBB, OPC_PSUBW, OPC_PSUBD, OPC_PSUBQ 3312 }; 3313 static int const sssub_insn[4] = { 3314 OPC_PSUBSB, OPC_PSUBSW, OPC_UD2, OPC_UD2 3315 }; 3316 static int const ussub_insn[4] = { 3317 OPC_PSUBUB, OPC_PSUBUW, OPC_UD2, OPC_UD2 3318 }; 3319 static int const mul_insn[4] = { 3320 OPC_UD2, OPC_PMULLW, OPC_PMULLD, OPC_VPMULLQ 3321 }; 3322 static int const shift_imm_insn[4] = { 3323 OPC_UD2, OPC_PSHIFTW_Ib, OPC_PSHIFTD_Ib, OPC_PSHIFTQ_Ib 3324 }; 3325 static int const punpckl_insn[4] = { 3326 OPC_PUNPCKLBW, OPC_PUNPCKLWD, OPC_PUNPCKLDQ, OPC_PUNPCKLQDQ 3327 }; 3328 static int const punpckh_insn[4] = { 3329 OPC_PUNPCKHBW, OPC_PUNPCKHWD, OPC_PUNPCKHDQ, OPC_PUNPCKHQDQ 3330 }; 3331 static int const packss_insn[4] = { 3332 OPC_PACKSSWB, OPC_PACKSSDW, OPC_UD2, OPC_UD2 3333 }; 3334 static int const packus_insn[4] = { 3335 OPC_PACKUSWB, OPC_PACKUSDW, OPC_UD2, OPC_UD2 3336 }; 3337 static int const smin_insn[4] = { 3338 OPC_PMINSB, OPC_PMINSW, OPC_PMINSD, OPC_VPMINSQ 3339 }; 3340 static int const smax_insn[4] = { 3341 OPC_PMAXSB, OPC_PMAXSW, OPC_PMAXSD, OPC_VPMAXSQ 3342 }; 3343 static int const rotlv_insn[4] = { 3344 OPC_UD2, OPC_UD2, OPC_VPROLVD, OPC_VPROLVQ 3345 }; 3346 static int const rotrv_insn[4] = { 3347 OPC_UD2, OPC_UD2, OPC_VPRORVD, OPC_VPRORVQ 3348 }; 3349 static int const shlv_insn[4] = { 3350 OPC_UD2, OPC_VPSLLVW, OPC_VPSLLVD, OPC_VPSLLVQ 3351 }; 3352 static int const shrv_insn[4] = { 3353 OPC_UD2, OPC_VPSRLVW, OPC_VPSRLVD, OPC_VPSRLVQ 3354 }; 3355 static int const sarv_insn[4] = { 3356 OPC_UD2, OPC_VPSRAVW, OPC_VPSRAVD, OPC_VPSRAVQ 3357 }; 3358 static int const shls_insn[4] = { 3359 OPC_UD2, OPC_PSLLW, OPC_PSLLD, OPC_PSLLQ 3360 }; 3361 static int const shrs_insn[4] = { 3362 OPC_UD2, OPC_PSRLW, OPC_PSRLD, OPC_PSRLQ 3363 }; 3364 static int const sars_insn[4] = { 3365 OPC_UD2, OPC_PSRAW, OPC_PSRAD, OPC_VPSRAQ 3366 }; 3367 static int const vpshldi_insn[4] = { 3368 OPC_UD2, OPC_VPSHLDW, OPC_VPSHLDD, OPC_VPSHLDQ 3369 }; 3370 static int const vpshldv_insn[4] = { 3371 OPC_UD2, OPC_VPSHLDVW, OPC_VPSHLDVD, OPC_VPSHLDVQ 3372 }; 3373 static int const vpshrdv_insn[4] = { 3374 OPC_UD2, OPC_VPSHRDVW, OPC_VPSHRDVD, OPC_VPSHRDVQ 3375 }; 3376 static int const abs_insn[4] = { 3377 OPC_PABSB, OPC_PABSW, OPC_PABSD, OPC_VPABSQ 3378 }; 3379 3380 TCGType type = vecl + TCG_TYPE_V64; 3381 int insn, sub; 3382 TCGArg a0, a1, a2, a3; 3383 3384 a0 = args[0]; 3385 a1 = args[1]; 3386 a2 = args[2]; 3387 3388 switch (opc) { 3389 case INDEX_op_add_vec: 3390 insn = add_insn[vece]; 3391 goto gen_simd; 3392 case INDEX_op_ssadd_vec: 3393 insn = ssadd_insn[vece]; 3394 goto gen_simd; 3395 case INDEX_op_usadd_vec: 3396 insn = usadd_insn[vece]; 3397 goto gen_simd; 3398 case INDEX_op_sub_vec: 3399 insn = sub_insn[vece]; 3400 goto gen_simd; 3401 case INDEX_op_sssub_vec: 3402 insn = sssub_insn[vece]; 3403 goto gen_simd; 3404 case INDEX_op_ussub_vec: 3405 insn = ussub_insn[vece]; 3406 goto gen_simd; 3407 case INDEX_op_mul_vec: 3408 insn = mul_insn[vece]; 3409 goto gen_simd; 3410 case INDEX_op_and_vec: 3411 insn = OPC_PAND; 3412 goto gen_simd; 3413 case INDEX_op_or_vec: 3414 insn = OPC_POR; 3415 goto gen_simd; 3416 case INDEX_op_xor_vec: 3417 insn = OPC_PXOR; 3418 goto gen_simd; 3419 case INDEX_op_smin_vec: 3420 insn = smin_insn[vece]; 3421 goto gen_simd; 3422 case INDEX_op_umin_vec: 3423 insn = umin_insn[vece]; 3424 goto gen_simd; 3425 case INDEX_op_smax_vec: 3426 insn = smax_insn[vece]; 3427 goto gen_simd; 3428 case INDEX_op_umax_vec: 3429 insn = umax_insn[vece]; 3430 goto gen_simd; 3431 case INDEX_op_shlv_vec: 3432 insn = shlv_insn[vece]; 3433 goto gen_simd; 3434 case INDEX_op_shrv_vec: 3435 insn = shrv_insn[vece]; 3436 goto gen_simd; 3437 case INDEX_op_sarv_vec: 3438 insn = sarv_insn[vece]; 3439 goto gen_simd; 3440 case INDEX_op_rotlv_vec: 3441 insn = rotlv_insn[vece]; 3442 goto gen_simd; 3443 case INDEX_op_rotrv_vec: 3444 insn = rotrv_insn[vece]; 3445 goto gen_simd; 3446 case INDEX_op_shls_vec: 3447 insn = shls_insn[vece]; 3448 goto gen_simd; 3449 case INDEX_op_shrs_vec: 3450 insn = shrs_insn[vece]; 3451 goto gen_simd; 3452 case INDEX_op_sars_vec: 3453 insn = sars_insn[vece]; 3454 goto gen_simd; 3455 case INDEX_op_x86_punpckl_vec: 3456 insn = punpckl_insn[vece]; 3457 goto gen_simd; 3458 case INDEX_op_x86_punpckh_vec: 3459 insn = punpckh_insn[vece]; 3460 goto gen_simd; 3461 case INDEX_op_x86_packss_vec: 3462 insn = packss_insn[vece]; 3463 goto gen_simd; 3464 case INDEX_op_x86_packus_vec: 3465 insn = packus_insn[vece]; 3466 goto gen_simd; 3467 case INDEX_op_x86_vpshldv_vec: 3468 insn = vpshldv_insn[vece]; 3469 a1 = a2; 3470 a2 = args[3]; 3471 goto gen_simd; 3472 case INDEX_op_x86_vpshrdv_vec: 3473 insn = vpshrdv_insn[vece]; 3474 a1 = a2; 3475 a2 = args[3]; 3476 goto gen_simd; 3477#if TCG_TARGET_REG_BITS == 32 3478 case INDEX_op_dup2_vec: 3479 /* First merge the two 32-bit inputs to a single 64-bit element. */ 3480 tcg_out_vex_modrm(s, OPC_PUNPCKLDQ, a0, a1, a2); 3481 /* Then replicate the 64-bit elements across the rest of the vector. */ 3482 if (type != TCG_TYPE_V64) { 3483 tcg_out_dup_vec(s, type, MO_64, a0, a0); 3484 } 3485 break; 3486#endif 3487 case INDEX_op_abs_vec: 3488 insn = abs_insn[vece]; 3489 a2 = a1; 3490 a1 = 0; 3491 goto gen_simd; 3492 gen_simd: 3493 tcg_debug_assert(insn != OPC_UD2); 3494 tcg_out_vex_modrm_type(s, insn, a0, a1, a2, type); 3495 break; 3496 3497 case INDEX_op_cmp_vec: 3498 tcg_out_cmp_vec(s, type, vece, a0, a1, a2, args[3]); 3499 break; 3500 3501 case INDEX_op_cmpsel_vec: 3502 tcg_out_cmpsel_vec(s, type, vece, a0, a1, a2, 3503 args[3], args[4], args[5]); 3504 break; 3505 3506 case INDEX_op_andc_vec: 3507 insn = OPC_PANDN; 3508 tcg_out_vex_modrm_type(s, insn, a0, a2, a1, type); 3509 break; 3510 3511 case INDEX_op_shli_vec: 3512 insn = shift_imm_insn[vece]; 3513 sub = 6; 3514 goto gen_shift; 3515 case INDEX_op_shri_vec: 3516 insn = shift_imm_insn[vece]; 3517 sub = 2; 3518 goto gen_shift; 3519 case INDEX_op_sari_vec: 3520 if (vece == MO_64) { 3521 insn = OPC_PSHIFTD_Ib | P_VEXW | P_EVEX; 3522 } else { 3523 insn = shift_imm_insn[vece]; 3524 } 3525 sub = 4; 3526 goto gen_shift; 3527 case INDEX_op_rotli_vec: 3528 insn = OPC_PSHIFTD_Ib | P_EVEX; /* VPROL[DQ] */ 3529 if (vece == MO_64) { 3530 insn |= P_VEXW; 3531 } 3532 sub = 1; 3533 goto gen_shift; 3534 gen_shift: 3535 tcg_debug_assert(vece != MO_8); 3536 tcg_out_vex_modrm_type(s, insn, sub, a0, a1, type); 3537 tcg_out8(s, a2); 3538 break; 3539 3540 case INDEX_op_ld_vec: 3541 tcg_out_ld(s, type, a0, a1, a2); 3542 break; 3543 case INDEX_op_st_vec: 3544 tcg_out_st(s, type, a0, a1, a2); 3545 break; 3546 case INDEX_op_dupm_vec: 3547 tcg_out_dupm_vec(s, type, vece, a0, a1, a2); 3548 break; 3549 3550 case INDEX_op_x86_shufps_vec: 3551 insn = OPC_SHUFPS; 3552 sub = args[3]; 3553 goto gen_simd_imm8; 3554 case INDEX_op_x86_blend_vec: 3555 if (vece == MO_16) { 3556 insn = OPC_PBLENDW; 3557 } else if (vece == MO_32) { 3558 insn = (have_avx2 ? OPC_VPBLENDD : OPC_BLENDPS); 3559 } else { 3560 g_assert_not_reached(); 3561 } 3562 sub = args[3]; 3563 goto gen_simd_imm8; 3564 case INDEX_op_x86_vperm2i128_vec: 3565 insn = OPC_VPERM2I128; 3566 sub = args[3]; 3567 goto gen_simd_imm8; 3568 case INDEX_op_x86_vpshldi_vec: 3569 insn = vpshldi_insn[vece]; 3570 sub = args[3]; 3571 goto gen_simd_imm8; 3572 3573 case INDEX_op_not_vec: 3574 insn = OPC_VPTERNLOGQ; 3575 a2 = a1; 3576 sub = 0x33; /* !B */ 3577 goto gen_simd_imm8; 3578 case INDEX_op_nor_vec: 3579 insn = OPC_VPTERNLOGQ; 3580 sub = 0x11; /* norCB */ 3581 goto gen_simd_imm8; 3582 case INDEX_op_nand_vec: 3583 insn = OPC_VPTERNLOGQ; 3584 sub = 0x77; /* nandCB */ 3585 goto gen_simd_imm8; 3586 case INDEX_op_eqv_vec: 3587 insn = OPC_VPTERNLOGQ; 3588 sub = 0x99; /* xnorCB */ 3589 goto gen_simd_imm8; 3590 case INDEX_op_orc_vec: 3591 insn = OPC_VPTERNLOGQ; 3592 sub = 0xdd; /* orB!C */ 3593 goto gen_simd_imm8; 3594 3595 case INDEX_op_bitsel_vec: 3596 insn = OPC_VPTERNLOGQ; 3597 a3 = args[3]; 3598 if (a0 == a1) { 3599 a1 = a2; 3600 a2 = a3; 3601 sub = 0xca; /* A?B:C */ 3602 } else if (a0 == a2) { 3603 a2 = a3; 3604 sub = 0xe2; /* B?A:C */ 3605 } else { 3606 tcg_out_mov(s, type, a0, a3); 3607 sub = 0xb8; /* B?C:A */ 3608 } 3609 goto gen_simd_imm8; 3610 3611 gen_simd_imm8: 3612 tcg_debug_assert(insn != OPC_UD2); 3613 tcg_out_vex_modrm_type(s, insn, a0, a1, a2, type); 3614 tcg_out8(s, sub); 3615 break; 3616 3617 case INDEX_op_x86_psrldq_vec: 3618 tcg_out_vex_modrm(s, OPC_GRP14, 3, a0, a1); 3619 tcg_out8(s, a2); 3620 break; 3621 3622 case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ 3623 case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ 3624 default: 3625 g_assert_not_reached(); 3626 } 3627} 3628 3629static TCGConstraintSetIndex 3630tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) 3631{ 3632 switch (op) { 3633 case INDEX_op_goto_ptr: 3634 return C_O0_I1(r); 3635 3636 case INDEX_op_ld8u_i32: 3637 case INDEX_op_ld8u_i64: 3638 case INDEX_op_ld8s_i32: 3639 case INDEX_op_ld8s_i64: 3640 case INDEX_op_ld16u_i32: 3641 case INDEX_op_ld16u_i64: 3642 case INDEX_op_ld16s_i32: 3643 case INDEX_op_ld16s_i64: 3644 case INDEX_op_ld_i32: 3645 case INDEX_op_ld32u_i64: 3646 case INDEX_op_ld32s_i64: 3647 case INDEX_op_ld_i64: 3648 return C_O1_I1(r, r); 3649 3650 case INDEX_op_st8_i32: 3651 case INDEX_op_st8_i64: 3652 return C_O0_I2(qi, r); 3653 3654 case INDEX_op_st16_i32: 3655 case INDEX_op_st16_i64: 3656 case INDEX_op_st_i32: 3657 case INDEX_op_st32_i64: 3658 return C_O0_I2(ri, r); 3659 3660 case INDEX_op_st_i64: 3661 return C_O0_I2(re, r); 3662 3663 case INDEX_op_add_i32: 3664 case INDEX_op_add_i64: 3665 return C_O1_I2(r, r, re); 3666 3667 case INDEX_op_sub_i32: 3668 case INDEX_op_sub_i64: 3669 case INDEX_op_mul_i32: 3670 case INDEX_op_mul_i64: 3671 case INDEX_op_or_i32: 3672 case INDEX_op_or_i64: 3673 case INDEX_op_xor_i32: 3674 case INDEX_op_xor_i64: 3675 return C_O1_I2(r, 0, re); 3676 3677 case INDEX_op_and_i32: 3678 case INDEX_op_and_i64: 3679 return C_O1_I2(r, 0, reZ); 3680 3681 case INDEX_op_andc_i32: 3682 case INDEX_op_andc_i64: 3683 return C_O1_I2(r, r, rI); 3684 3685 case INDEX_op_shl_i32: 3686 case INDEX_op_shl_i64: 3687 case INDEX_op_shr_i32: 3688 case INDEX_op_shr_i64: 3689 case INDEX_op_sar_i32: 3690 case INDEX_op_sar_i64: 3691 return have_bmi2 ? C_O1_I2(r, r, ri) : C_O1_I2(r, 0, ci); 3692 3693 case INDEX_op_rotl_i32: 3694 case INDEX_op_rotl_i64: 3695 case INDEX_op_rotr_i32: 3696 case INDEX_op_rotr_i64: 3697 return C_O1_I2(r, 0, ci); 3698 3699 case INDEX_op_brcond_i32: 3700 case INDEX_op_brcond_i64: 3701 return C_O0_I2(r, reT); 3702 3703 case INDEX_op_bswap16_i32: 3704 case INDEX_op_bswap16_i64: 3705 case INDEX_op_bswap32_i32: 3706 case INDEX_op_bswap32_i64: 3707 case INDEX_op_bswap64_i64: 3708 case INDEX_op_neg_i32: 3709 case INDEX_op_neg_i64: 3710 case INDEX_op_not_i32: 3711 case INDEX_op_not_i64: 3712 case INDEX_op_extrh_i64_i32: 3713 return C_O1_I1(r, 0); 3714 3715 case INDEX_op_ext8s_i32: 3716 case INDEX_op_ext8s_i64: 3717 case INDEX_op_ext8u_i32: 3718 case INDEX_op_ext8u_i64: 3719 return C_O1_I1(r, q); 3720 3721 case INDEX_op_ext16s_i32: 3722 case INDEX_op_ext16s_i64: 3723 case INDEX_op_ext16u_i32: 3724 case INDEX_op_ext16u_i64: 3725 case INDEX_op_ext32s_i64: 3726 case INDEX_op_ext32u_i64: 3727 case INDEX_op_ext_i32_i64: 3728 case INDEX_op_extu_i32_i64: 3729 case INDEX_op_extrl_i64_i32: 3730 case INDEX_op_extract_i32: 3731 case INDEX_op_extract_i64: 3732 case INDEX_op_sextract_i32: 3733 case INDEX_op_sextract_i64: 3734 case INDEX_op_ctpop_i32: 3735 case INDEX_op_ctpop_i64: 3736 return C_O1_I1(r, r); 3737 3738 case INDEX_op_extract2_i32: 3739 case INDEX_op_extract2_i64: 3740 return C_O1_I2(r, 0, r); 3741 3742 case INDEX_op_deposit_i32: 3743 case INDEX_op_deposit_i64: 3744 return C_O1_I2(q, 0, qi); 3745 3746 case INDEX_op_setcond_i32: 3747 case INDEX_op_setcond_i64: 3748 case INDEX_op_negsetcond_i32: 3749 case INDEX_op_negsetcond_i64: 3750 return C_O1_I2(q, r, reT); 3751 3752 case INDEX_op_movcond_i32: 3753 case INDEX_op_movcond_i64: 3754 return C_O1_I4(r, r, reT, r, 0); 3755 3756 case INDEX_op_div2_i32: 3757 case INDEX_op_div2_i64: 3758 case INDEX_op_divu2_i32: 3759 case INDEX_op_divu2_i64: 3760 return C_O2_I3(a, d, 0, 1, r); 3761 3762 case INDEX_op_mulu2_i32: 3763 case INDEX_op_mulu2_i64: 3764 case INDEX_op_muls2_i32: 3765 case INDEX_op_muls2_i64: 3766 return C_O2_I2(a, d, a, r); 3767 3768 case INDEX_op_add2_i32: 3769 case INDEX_op_add2_i64: 3770 case INDEX_op_sub2_i32: 3771 case INDEX_op_sub2_i64: 3772 return C_N1_O1_I4(r, r, 0, 1, re, re); 3773 3774 case INDEX_op_ctz_i32: 3775 case INDEX_op_ctz_i64: 3776 return have_bmi1 ? C_N1_I2(r, r, rW) : C_N1_I2(r, r, r); 3777 3778 case INDEX_op_clz_i32: 3779 case INDEX_op_clz_i64: 3780 return have_lzcnt ? C_N1_I2(r, r, rW) : C_N1_I2(r, r, r); 3781 3782 case INDEX_op_qemu_ld_i32: 3783 return C_O1_I1(r, L); 3784 3785 case INDEX_op_qemu_st_i32: 3786 return C_O0_I2(L, L); 3787 case INDEX_op_qemu_st8_i32: 3788 return C_O0_I2(s, L); 3789 3790 case INDEX_op_qemu_ld_i64: 3791 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L) : C_O2_I1(r, r, L); 3792 3793 case INDEX_op_qemu_st_i64: 3794 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(L, L) : C_O0_I3(L, L, L); 3795 3796 case INDEX_op_qemu_ld_i128: 3797 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 3798 return C_O2_I1(r, r, L); 3799 case INDEX_op_qemu_st_i128: 3800 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 3801 return C_O0_I3(L, L, L); 3802 3803 case INDEX_op_brcond2_i32: 3804 return C_O0_I4(r, r, ri, ri); 3805 3806 case INDEX_op_setcond2_i32: 3807 return C_O1_I4(r, r, r, ri, ri); 3808 3809 case INDEX_op_ld_vec: 3810 case INDEX_op_dupm_vec: 3811 return C_O1_I1(x, r); 3812 3813 case INDEX_op_st_vec: 3814 return C_O0_I2(x, r); 3815 3816 case INDEX_op_add_vec: 3817 case INDEX_op_sub_vec: 3818 case INDEX_op_mul_vec: 3819 case INDEX_op_and_vec: 3820 case INDEX_op_or_vec: 3821 case INDEX_op_xor_vec: 3822 case INDEX_op_andc_vec: 3823 case INDEX_op_orc_vec: 3824 case INDEX_op_nand_vec: 3825 case INDEX_op_nor_vec: 3826 case INDEX_op_eqv_vec: 3827 case INDEX_op_ssadd_vec: 3828 case INDEX_op_usadd_vec: 3829 case INDEX_op_sssub_vec: 3830 case INDEX_op_ussub_vec: 3831 case INDEX_op_smin_vec: 3832 case INDEX_op_umin_vec: 3833 case INDEX_op_smax_vec: 3834 case INDEX_op_umax_vec: 3835 case INDEX_op_shlv_vec: 3836 case INDEX_op_shrv_vec: 3837 case INDEX_op_sarv_vec: 3838 case INDEX_op_rotlv_vec: 3839 case INDEX_op_rotrv_vec: 3840 case INDEX_op_shls_vec: 3841 case INDEX_op_shrs_vec: 3842 case INDEX_op_sars_vec: 3843 case INDEX_op_cmp_vec: 3844 case INDEX_op_x86_shufps_vec: 3845 case INDEX_op_x86_blend_vec: 3846 case INDEX_op_x86_packss_vec: 3847 case INDEX_op_x86_packus_vec: 3848 case INDEX_op_x86_vperm2i128_vec: 3849 case INDEX_op_x86_punpckl_vec: 3850 case INDEX_op_x86_punpckh_vec: 3851 case INDEX_op_x86_vpshldi_vec: 3852#if TCG_TARGET_REG_BITS == 32 3853 case INDEX_op_dup2_vec: 3854#endif 3855 return C_O1_I2(x, x, x); 3856 3857 case INDEX_op_abs_vec: 3858 case INDEX_op_dup_vec: 3859 case INDEX_op_not_vec: 3860 case INDEX_op_shli_vec: 3861 case INDEX_op_shri_vec: 3862 case INDEX_op_sari_vec: 3863 case INDEX_op_rotli_vec: 3864 case INDEX_op_x86_psrldq_vec: 3865 return C_O1_I1(x, x); 3866 3867 case INDEX_op_x86_vpshldv_vec: 3868 case INDEX_op_x86_vpshrdv_vec: 3869 return C_O1_I3(x, 0, x, x); 3870 3871 case INDEX_op_bitsel_vec: 3872 return C_O1_I3(x, x, x, x); 3873 case INDEX_op_cmpsel_vec: 3874 return C_O1_I4(x, x, x, xO, x); 3875 3876 default: 3877 return C_NotImplemented; 3878 } 3879} 3880 3881int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 3882{ 3883 switch (opc) { 3884 case INDEX_op_add_vec: 3885 case INDEX_op_sub_vec: 3886 case INDEX_op_and_vec: 3887 case INDEX_op_or_vec: 3888 case INDEX_op_xor_vec: 3889 case INDEX_op_andc_vec: 3890 case INDEX_op_orc_vec: 3891 case INDEX_op_nand_vec: 3892 case INDEX_op_nor_vec: 3893 case INDEX_op_eqv_vec: 3894 case INDEX_op_not_vec: 3895 case INDEX_op_bitsel_vec: 3896 return 1; 3897 case INDEX_op_cmp_vec: 3898 case INDEX_op_cmpsel_vec: 3899 return -1; 3900 3901 case INDEX_op_rotli_vec: 3902 return have_avx512vl && vece >= MO_32 ? 1 : -1; 3903 3904 case INDEX_op_shli_vec: 3905 case INDEX_op_shri_vec: 3906 /* We must expand the operation for MO_8. */ 3907 return vece == MO_8 ? -1 : 1; 3908 3909 case INDEX_op_sari_vec: 3910 switch (vece) { 3911 case MO_8: 3912 return -1; 3913 case MO_16: 3914 case MO_32: 3915 return 1; 3916 case MO_64: 3917 if (have_avx512vl) { 3918 return 1; 3919 } 3920 /* 3921 * We can emulate this for MO_64, but it does not pay off 3922 * unless we're producing at least 4 values. 3923 */ 3924 return type >= TCG_TYPE_V256 ? -1 : 0; 3925 } 3926 return 0; 3927 3928 case INDEX_op_shls_vec: 3929 case INDEX_op_shrs_vec: 3930 return vece >= MO_16; 3931 case INDEX_op_sars_vec: 3932 switch (vece) { 3933 case MO_16: 3934 case MO_32: 3935 return 1; 3936 case MO_64: 3937 return have_avx512vl; 3938 } 3939 return 0; 3940 case INDEX_op_rotls_vec: 3941 return vece >= MO_16 ? -1 : 0; 3942 3943 case INDEX_op_shlv_vec: 3944 case INDEX_op_shrv_vec: 3945 switch (vece) { 3946 case MO_16: 3947 return have_avx512bw; 3948 case MO_32: 3949 case MO_64: 3950 return have_avx2; 3951 } 3952 return 0; 3953 case INDEX_op_sarv_vec: 3954 switch (vece) { 3955 case MO_16: 3956 return have_avx512bw; 3957 case MO_32: 3958 return have_avx2; 3959 case MO_64: 3960 return have_avx512vl; 3961 } 3962 return 0; 3963 case INDEX_op_rotlv_vec: 3964 case INDEX_op_rotrv_vec: 3965 switch (vece) { 3966 case MO_16: 3967 return have_avx512vbmi2 ? -1 : 0; 3968 case MO_32: 3969 case MO_64: 3970 return have_avx512vl ? 1 : have_avx2 ? -1 : 0; 3971 } 3972 return 0; 3973 3974 case INDEX_op_mul_vec: 3975 switch (vece) { 3976 case MO_8: 3977 return -1; 3978 case MO_64: 3979 return have_avx512dq; 3980 } 3981 return 1; 3982 3983 case INDEX_op_ssadd_vec: 3984 case INDEX_op_usadd_vec: 3985 case INDEX_op_sssub_vec: 3986 case INDEX_op_ussub_vec: 3987 return vece <= MO_16; 3988 case INDEX_op_smin_vec: 3989 case INDEX_op_smax_vec: 3990 case INDEX_op_umin_vec: 3991 case INDEX_op_umax_vec: 3992 case INDEX_op_abs_vec: 3993 return vece <= MO_32 || have_avx512vl; 3994 3995 default: 3996 return 0; 3997 } 3998} 3999 4000static void expand_vec_shi(TCGType type, unsigned vece, bool right, 4001 TCGv_vec v0, TCGv_vec v1, TCGArg imm) 4002{ 4003 uint8_t mask; 4004 4005 tcg_debug_assert(vece == MO_8); 4006 if (right) { 4007 mask = 0xff >> imm; 4008 tcg_gen_shri_vec(MO_16, v0, v1, imm); 4009 } else { 4010 mask = 0xff << imm; 4011 tcg_gen_shli_vec(MO_16, v0, v1, imm); 4012 } 4013 tcg_gen_and_vec(MO_8, v0, v0, tcg_constant_vec(type, MO_8, mask)); 4014} 4015 4016static void expand_vec_sari(TCGType type, unsigned vece, 4017 TCGv_vec v0, TCGv_vec v1, TCGArg imm) 4018{ 4019 TCGv_vec t1, t2; 4020 4021 switch (vece) { 4022 case MO_8: 4023 /* Unpack to 16-bit, shift, and repack. */ 4024 t1 = tcg_temp_new_vec(type); 4025 t2 = tcg_temp_new_vec(type); 4026 vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8, 4027 tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(v1)); 4028 vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8, 4029 tcgv_vec_arg(t2), tcgv_vec_arg(v1), tcgv_vec_arg(v1)); 4030 tcg_gen_sari_vec(MO_16, t1, t1, imm + 8); 4031 tcg_gen_sari_vec(MO_16, t2, t2, imm + 8); 4032 vec_gen_3(INDEX_op_x86_packss_vec, type, MO_8, 4033 tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t2)); 4034 tcg_temp_free_vec(t1); 4035 tcg_temp_free_vec(t2); 4036 break; 4037 4038 case MO_64: 4039 t1 = tcg_temp_new_vec(type); 4040 if (imm <= 32) { 4041 /* 4042 * We can emulate a small sign extend by performing an arithmetic 4043 * 32-bit shift and overwriting the high half of a 64-bit logical 4044 * shift. Note that the ISA says shift of 32 is valid, but TCG 4045 * does not, so we have to bound the smaller shift -- we get the 4046 * same result in the high half either way. 4047 */ 4048 tcg_gen_sari_vec(MO_32, t1, v1, MIN(imm, 31)); 4049 tcg_gen_shri_vec(MO_64, v0, v1, imm); 4050 vec_gen_4(INDEX_op_x86_blend_vec, type, MO_32, 4051 tcgv_vec_arg(v0), tcgv_vec_arg(v0), 4052 tcgv_vec_arg(t1), 0xaa); 4053 } else { 4054 /* Otherwise we will need to use a compare vs 0 to produce 4055 * the sign-extend, shift and merge. 4056 */ 4057 tcg_gen_cmp_vec(TCG_COND_GT, MO_64, t1, 4058 tcg_constant_vec(type, MO_64, 0), v1); 4059 tcg_gen_shri_vec(MO_64, v0, v1, imm); 4060 tcg_gen_shli_vec(MO_64, t1, t1, 64 - imm); 4061 tcg_gen_or_vec(MO_64, v0, v0, t1); 4062 } 4063 tcg_temp_free_vec(t1); 4064 break; 4065 4066 default: 4067 g_assert_not_reached(); 4068 } 4069} 4070 4071static void expand_vec_rotli(TCGType type, unsigned vece, 4072 TCGv_vec v0, TCGv_vec v1, TCGArg imm) 4073{ 4074 TCGv_vec t; 4075 4076 if (vece != MO_8 && have_avx512vbmi2) { 4077 vec_gen_4(INDEX_op_x86_vpshldi_vec, type, vece, 4078 tcgv_vec_arg(v0), tcgv_vec_arg(v1), tcgv_vec_arg(v1), imm); 4079 return; 4080 } 4081 4082 t = tcg_temp_new_vec(type); 4083 tcg_gen_shli_vec(vece, t, v1, imm); 4084 tcg_gen_shri_vec(vece, v0, v1, (8 << vece) - imm); 4085 tcg_gen_or_vec(vece, v0, v0, t); 4086 tcg_temp_free_vec(t); 4087} 4088 4089static void expand_vec_rotv(TCGType type, unsigned vece, TCGv_vec v0, 4090 TCGv_vec v1, TCGv_vec sh, bool right) 4091{ 4092 TCGv_vec t; 4093 4094 if (have_avx512vbmi2) { 4095 vec_gen_4(right ? INDEX_op_x86_vpshrdv_vec : INDEX_op_x86_vpshldv_vec, 4096 type, vece, tcgv_vec_arg(v0), tcgv_vec_arg(v1), 4097 tcgv_vec_arg(v1), tcgv_vec_arg(sh)); 4098 return; 4099 } 4100 4101 t = tcg_temp_new_vec(type); 4102 tcg_gen_dupi_vec(vece, t, 8 << vece); 4103 tcg_gen_sub_vec(vece, t, t, sh); 4104 if (right) { 4105 tcg_gen_shlv_vec(vece, t, v1, t); 4106 tcg_gen_shrv_vec(vece, v0, v1, sh); 4107 } else { 4108 tcg_gen_shrv_vec(vece, t, v1, t); 4109 tcg_gen_shlv_vec(vece, v0, v1, sh); 4110 } 4111 tcg_gen_or_vec(vece, v0, v0, t); 4112 tcg_temp_free_vec(t); 4113} 4114 4115static void expand_vec_rotls(TCGType type, unsigned vece, 4116 TCGv_vec v0, TCGv_vec v1, TCGv_i32 lsh) 4117{ 4118 TCGv_vec t = tcg_temp_new_vec(type); 4119 4120 tcg_debug_assert(vece != MO_8); 4121 4122 if (vece >= MO_32 ? have_avx512vl : have_avx512vbmi2) { 4123 tcg_gen_dup_i32_vec(vece, t, lsh); 4124 if (vece >= MO_32) { 4125 tcg_gen_rotlv_vec(vece, v0, v1, t); 4126 } else { 4127 expand_vec_rotv(type, vece, v0, v1, t, false); 4128 } 4129 } else { 4130 TCGv_i32 rsh = tcg_temp_new_i32(); 4131 4132 tcg_gen_neg_i32(rsh, lsh); 4133 tcg_gen_andi_i32(rsh, rsh, (8 << vece) - 1); 4134 tcg_gen_shls_vec(vece, t, v1, lsh); 4135 tcg_gen_shrs_vec(vece, v0, v1, rsh); 4136 tcg_gen_or_vec(vece, v0, v0, t); 4137 4138 tcg_temp_free_i32(rsh); 4139 } 4140 4141 tcg_temp_free_vec(t); 4142} 4143 4144static void expand_vec_mul(TCGType type, unsigned vece, 4145 TCGv_vec v0, TCGv_vec v1, TCGv_vec v2) 4146{ 4147 TCGv_vec t1, t2, t3, t4, zero; 4148 4149 tcg_debug_assert(vece == MO_8); 4150 4151 /* 4152 * Unpack v1 bytes to words, 0 | x. 4153 * Unpack v2 bytes to words, y | 0. 4154 * This leaves the 8-bit result, x * y, with 8 bits of right padding. 4155 * Shift logical right by 8 bits to clear the high 8 bytes before 4156 * using an unsigned saturated pack. 4157 * 4158 * The difference between the V64, V128 and V256 cases is merely how 4159 * we distribute the expansion between temporaries. 4160 */ 4161 switch (type) { 4162 case TCG_TYPE_V64: 4163 t1 = tcg_temp_new_vec(TCG_TYPE_V128); 4164 t2 = tcg_temp_new_vec(TCG_TYPE_V128); 4165 zero = tcg_constant_vec(TCG_TYPE_V128, MO_8, 0); 4166 vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_8, 4167 tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(zero)); 4168 vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_8, 4169 tcgv_vec_arg(t2), tcgv_vec_arg(zero), tcgv_vec_arg(v2)); 4170 tcg_gen_mul_vec(MO_16, t1, t1, t2); 4171 tcg_gen_shri_vec(MO_16, t1, t1, 8); 4172 vec_gen_3(INDEX_op_x86_packus_vec, TCG_TYPE_V128, MO_8, 4173 tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t1)); 4174 tcg_temp_free_vec(t1); 4175 tcg_temp_free_vec(t2); 4176 break; 4177 4178 case TCG_TYPE_V128: 4179 case TCG_TYPE_V256: 4180 t1 = tcg_temp_new_vec(type); 4181 t2 = tcg_temp_new_vec(type); 4182 t3 = tcg_temp_new_vec(type); 4183 t4 = tcg_temp_new_vec(type); 4184 zero = tcg_constant_vec(TCG_TYPE_V128, MO_8, 0); 4185 vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8, 4186 tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(zero)); 4187 vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8, 4188 tcgv_vec_arg(t2), tcgv_vec_arg(zero), tcgv_vec_arg(v2)); 4189 vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8, 4190 tcgv_vec_arg(t3), tcgv_vec_arg(v1), tcgv_vec_arg(zero)); 4191 vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8, 4192 tcgv_vec_arg(t4), tcgv_vec_arg(zero), tcgv_vec_arg(v2)); 4193 tcg_gen_mul_vec(MO_16, t1, t1, t2); 4194 tcg_gen_mul_vec(MO_16, t3, t3, t4); 4195 tcg_gen_shri_vec(MO_16, t1, t1, 8); 4196 tcg_gen_shri_vec(MO_16, t3, t3, 8); 4197 vec_gen_3(INDEX_op_x86_packus_vec, type, MO_8, 4198 tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t3)); 4199 tcg_temp_free_vec(t1); 4200 tcg_temp_free_vec(t2); 4201 tcg_temp_free_vec(t3); 4202 tcg_temp_free_vec(t4); 4203 break; 4204 4205 default: 4206 g_assert_not_reached(); 4207 } 4208} 4209 4210static TCGCond expand_vec_cond(TCGType type, unsigned vece, 4211 TCGArg *a1, TCGArg *a2, TCGCond cond) 4212{ 4213 /* 4214 * Without AVX512, there are no 64-bit unsigned comparisons. 4215 * We must bias the inputs so that they become signed. 4216 * All other swapping and inversion are handled during code generation. 4217 */ 4218 if (vece == MO_64 && !have_avx512dq && is_unsigned_cond(cond)) { 4219 TCGv_vec v1 = temp_tcgv_vec(arg_temp(*a1)); 4220 TCGv_vec v2 = temp_tcgv_vec(arg_temp(*a2)); 4221 TCGv_vec t1 = tcg_temp_new_vec(type); 4222 TCGv_vec t2 = tcg_temp_new_vec(type); 4223 TCGv_vec t3 = tcg_constant_vec(type, vece, 1ull << ((8 << vece) - 1)); 4224 4225 tcg_gen_sub_vec(vece, t1, v1, t3); 4226 tcg_gen_sub_vec(vece, t2, v2, t3); 4227 *a1 = tcgv_vec_arg(t1); 4228 *a2 = tcgv_vec_arg(t2); 4229 cond = tcg_signed_cond(cond); 4230 } 4231 return cond; 4232} 4233 4234static void expand_vec_cmp(TCGType type, unsigned vece, TCGArg a0, 4235 TCGArg a1, TCGArg a2, TCGCond cond) 4236{ 4237 cond = expand_vec_cond(type, vece, &a1, &a2, cond); 4238 /* Expand directly; do not recurse. */ 4239 vec_gen_4(INDEX_op_cmp_vec, type, vece, a0, a1, a2, cond); 4240} 4241 4242static void expand_vec_cmpsel(TCGType type, unsigned vece, TCGArg a0, 4243 TCGArg a1, TCGArg a2, 4244 TCGArg a3, TCGArg a4, TCGCond cond) 4245{ 4246 cond = expand_vec_cond(type, vece, &a1, &a2, cond); 4247 /* Expand directly; do not recurse. */ 4248 vec_gen_6(INDEX_op_cmpsel_vec, type, vece, a0, a1, a2, a3, a4, cond); 4249} 4250 4251void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 4252 TCGArg a0, ...) 4253{ 4254 va_list va; 4255 TCGArg a1, a2, a3, a4, a5; 4256 TCGv_vec v0, v1, v2; 4257 4258 va_start(va, a0); 4259 a1 = va_arg(va, TCGArg); 4260 a2 = va_arg(va, TCGArg); 4261 v0 = temp_tcgv_vec(arg_temp(a0)); 4262 v1 = temp_tcgv_vec(arg_temp(a1)); 4263 4264 switch (opc) { 4265 case INDEX_op_shli_vec: 4266 expand_vec_shi(type, vece, false, v0, v1, a2); 4267 break; 4268 case INDEX_op_shri_vec: 4269 expand_vec_shi(type, vece, true, v0, v1, a2); 4270 break; 4271 case INDEX_op_sari_vec: 4272 expand_vec_sari(type, vece, v0, v1, a2); 4273 break; 4274 4275 case INDEX_op_rotli_vec: 4276 expand_vec_rotli(type, vece, v0, v1, a2); 4277 break; 4278 4279 case INDEX_op_rotls_vec: 4280 expand_vec_rotls(type, vece, v0, v1, temp_tcgv_i32(arg_temp(a2))); 4281 break; 4282 4283 case INDEX_op_rotlv_vec: 4284 v2 = temp_tcgv_vec(arg_temp(a2)); 4285 expand_vec_rotv(type, vece, v0, v1, v2, false); 4286 break; 4287 case INDEX_op_rotrv_vec: 4288 v2 = temp_tcgv_vec(arg_temp(a2)); 4289 expand_vec_rotv(type, vece, v0, v1, v2, true); 4290 break; 4291 4292 case INDEX_op_mul_vec: 4293 v2 = temp_tcgv_vec(arg_temp(a2)); 4294 expand_vec_mul(type, vece, v0, v1, v2); 4295 break; 4296 4297 case INDEX_op_cmp_vec: 4298 a3 = va_arg(va, TCGArg); 4299 expand_vec_cmp(type, vece, a0, a1, a2, a3); 4300 break; 4301 4302 case INDEX_op_cmpsel_vec: 4303 a3 = va_arg(va, TCGArg); 4304 a4 = va_arg(va, TCGArg); 4305 a5 = va_arg(va, TCGArg); 4306 expand_vec_cmpsel(type, vece, a0, a1, a2, a3, a4, a5); 4307 break; 4308 4309 default: 4310 break; 4311 } 4312 4313 va_end(va); 4314} 4315 4316static const int tcg_target_callee_save_regs[] = { 4317#if TCG_TARGET_REG_BITS == 64 4318 TCG_REG_RBP, 4319 TCG_REG_RBX, 4320#if defined(_WIN64) 4321 TCG_REG_RDI, 4322 TCG_REG_RSI, 4323#endif 4324 TCG_REG_R12, 4325 TCG_REG_R13, 4326 TCG_REG_R14, /* Currently used for the global env. */ 4327 TCG_REG_R15, 4328#else 4329 TCG_REG_EBP, /* Currently used for the global env. */ 4330 TCG_REG_EBX, 4331 TCG_REG_ESI, 4332 TCG_REG_EDI, 4333#endif 4334}; 4335 4336/* Compute frame size via macros, to share between tcg_target_qemu_prologue 4337 and tcg_register_jit. */ 4338 4339#define PUSH_SIZE \ 4340 ((1 + ARRAY_SIZE(tcg_target_callee_save_regs)) \ 4341 * (TCG_TARGET_REG_BITS / 8)) 4342 4343#define FRAME_SIZE \ 4344 ((PUSH_SIZE \ 4345 + TCG_STATIC_CALL_ARGS_SIZE \ 4346 + CPU_TEMP_BUF_NLONGS * sizeof(long) \ 4347 + TCG_TARGET_STACK_ALIGN - 1) \ 4348 & ~(TCG_TARGET_STACK_ALIGN - 1)) 4349 4350/* Generate global QEMU prologue and epilogue code */ 4351static void tcg_target_qemu_prologue(TCGContext *s) 4352{ 4353 int i, stack_addend; 4354 4355 /* TB prologue */ 4356 4357 /* Reserve some stack space, also for TCG temps. */ 4358 stack_addend = FRAME_SIZE - PUSH_SIZE; 4359 tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE, 4360 CPU_TEMP_BUF_NLONGS * sizeof(long)); 4361 4362 /* Save all callee saved registers. */ 4363 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 4364 tcg_out_push(s, tcg_target_callee_save_regs[i]); 4365 } 4366 4367 if (!tcg_use_softmmu && guest_base) { 4368 int seg = setup_guest_base_seg(); 4369 if (seg != 0) { 4370 x86_guest_base.seg = seg; 4371 } else if (guest_base == (int32_t)guest_base) { 4372 x86_guest_base.ofs = guest_base; 4373 } else { 4374 assert(TCG_TARGET_REG_BITS == 64); 4375 /* Choose R12 because, as a base, it requires a SIB byte. */ 4376 x86_guest_base.index = TCG_REG_R12; 4377 tcg_out_movi(s, TCG_TYPE_PTR, x86_guest_base.index, guest_base); 4378 tcg_regset_set_reg(s->reserved_regs, x86_guest_base.index); 4379 } 4380 } 4381 4382 if (TCG_TARGET_REG_BITS == 32) { 4383 tcg_out_ld(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, 4384 (ARRAY_SIZE(tcg_target_callee_save_regs) + 1) * 4); 4385 tcg_out_addi(s, TCG_REG_ESP, -stack_addend); 4386 /* jmp *tb. */ 4387 tcg_out_modrm_offset(s, OPC_GRP5, EXT5_JMPN_Ev, TCG_REG_ESP, 4388 (ARRAY_SIZE(tcg_target_callee_save_regs) + 2) * 4 4389 + stack_addend); 4390 } else { 4391 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 4392 tcg_out_addi(s, TCG_REG_ESP, -stack_addend); 4393 /* jmp *tb. */ 4394 tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, tcg_target_call_iarg_regs[1]); 4395 } 4396 4397 /* 4398 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 4399 * and fall through to the rest of the epilogue. 4400 */ 4401 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 4402 tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_EAX, 0); 4403 4404 /* TB epilogue */ 4405 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 4406 4407 tcg_out_addi(s, TCG_REG_CALL_STACK, stack_addend); 4408 4409 if (have_avx2) { 4410 tcg_out_vex_opc(s, OPC_VZEROUPPER, 0, 0, 0, 0); 4411 } 4412 for (i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) { 4413 tcg_out_pop(s, tcg_target_callee_save_regs[i]); 4414 } 4415 tcg_out_opc(s, OPC_RET, 0, 0, 0); 4416} 4417 4418static void tcg_out_tb_start(TCGContext *s) 4419{ 4420 /* nothing to do */ 4421} 4422 4423static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 4424{ 4425 memset(p, 0x90, count); 4426} 4427 4428static void tcg_target_init(TCGContext *s) 4429{ 4430 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS; 4431 if (TCG_TARGET_REG_BITS == 64) { 4432 tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS; 4433 } 4434 if (have_avx1) { 4435 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS; 4436 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS; 4437 } 4438 if (have_avx2) { 4439 tcg_target_available_regs[TCG_TYPE_V256] = ALL_VECTOR_REGS; 4440 } 4441 4442 tcg_target_call_clobber_regs = ALL_VECTOR_REGS; 4443 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_EAX); 4444 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_EDX); 4445 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_ECX); 4446 if (TCG_TARGET_REG_BITS == 64) { 4447#if !defined(_WIN64) 4448 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_RDI); 4449 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_RSI); 4450#endif 4451 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8); 4452 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9); 4453 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10); 4454 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11); 4455 } 4456 4457 s->reserved_regs = 0; 4458 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); 4459 tcg_regset_set_reg(s->reserved_regs, TCG_TMP_VEC); 4460#ifdef _WIN64 4461 /* These are call saved, and we don't save them, so don't use them. */ 4462 tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM6); 4463 tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM7); 4464 tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM8); 4465 tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM9); 4466 tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM10); 4467 tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM11); 4468 tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM12); 4469 tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM13); 4470 tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM14); 4471 tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM15); 4472#endif 4473} 4474 4475typedef struct { 4476 DebugFrameHeader h; 4477 uint8_t fde_def_cfa[4]; 4478 uint8_t fde_reg_ofs[14]; 4479} DebugFrame; 4480 4481/* We're expecting a 2 byte uleb128 encoded value. */ 4482QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); 4483 4484#if !defined(__ELF__) 4485 /* Host machine without ELF. */ 4486#elif TCG_TARGET_REG_BITS == 64 4487#define ELF_HOST_MACHINE EM_X86_64 4488static const DebugFrame debug_frame = { 4489 .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ 4490 .h.cie.id = -1, 4491 .h.cie.version = 1, 4492 .h.cie.code_align = 1, 4493 .h.cie.data_align = 0x78, /* sleb128 -8 */ 4494 .h.cie.return_column = 16, 4495 4496 /* Total FDE size does not include the "len" member. */ 4497 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 4498 4499 .fde_def_cfa = { 4500 12, 7, /* DW_CFA_def_cfa %rsp, ... */ 4501 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 4502 (FRAME_SIZE >> 7) 4503 }, 4504 .fde_reg_ofs = { 4505 0x90, 1, /* DW_CFA_offset, %rip, -8 */ 4506 /* The following ordering must match tcg_target_callee_save_regs. */ 4507 0x86, 2, /* DW_CFA_offset, %rbp, -16 */ 4508 0x83, 3, /* DW_CFA_offset, %rbx, -24 */ 4509 0x8c, 4, /* DW_CFA_offset, %r12, -32 */ 4510 0x8d, 5, /* DW_CFA_offset, %r13, -40 */ 4511 0x8e, 6, /* DW_CFA_offset, %r14, -48 */ 4512 0x8f, 7, /* DW_CFA_offset, %r15, -56 */ 4513 } 4514}; 4515#else 4516#define ELF_HOST_MACHINE EM_386 4517static const DebugFrame debug_frame = { 4518 .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ 4519 .h.cie.id = -1, 4520 .h.cie.version = 1, 4521 .h.cie.code_align = 1, 4522 .h.cie.data_align = 0x7c, /* sleb128 -4 */ 4523 .h.cie.return_column = 8, 4524 4525 /* Total FDE size does not include the "len" member. */ 4526 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 4527 4528 .fde_def_cfa = { 4529 12, 4, /* DW_CFA_def_cfa %esp, ... */ 4530 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 4531 (FRAME_SIZE >> 7) 4532 }, 4533 .fde_reg_ofs = { 4534 0x88, 1, /* DW_CFA_offset, %eip, -4 */ 4535 /* The following ordering must match tcg_target_callee_save_regs. */ 4536 0x85, 2, /* DW_CFA_offset, %ebp, -8 */ 4537 0x83, 3, /* DW_CFA_offset, %ebx, -12 */ 4538 0x86, 4, /* DW_CFA_offset, %esi, -16 */ 4539 0x87, 5, /* DW_CFA_offset, %edi, -20 */ 4540 } 4541}; 4542#endif 4543 4544#if defined(ELF_HOST_MACHINE) 4545void tcg_register_jit(const void *buf, size_t buf_size) 4546{ 4547 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 4548} 4549#endif 4550