1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Define target-specific opcode support 4 * Copyright (c) 2008 Fabrice Bellard 5 */ 6 7 #ifndef TCG_TARGET_HAS_H 8 #define TCG_TARGET_HAS_H 9 10 #include "host/cpuinfo.h" 11 12 #define have_bmi1 (cpuinfo & CPUINFO_BMI1) 13 #define have_popcnt (cpuinfo & CPUINFO_POPCNT) 14 #define have_avx1 (cpuinfo & CPUINFO_AVX1) 15 #define have_avx2 (cpuinfo & CPUINFO_AVX2) 16 #define have_movbe (cpuinfo & CPUINFO_MOVBE) 17 18 /* 19 * There are interesting instructions in AVX512, so long as we have AVX512VL, 20 * which indicates support for EVEX on sizes smaller than 512 bits. 21 */ 22 #define have_avx512vl ((cpuinfo & CPUINFO_AVX512VL) && \ 23 (cpuinfo & CPUINFO_AVX512F)) 24 #define have_avx512bw ((cpuinfo & CPUINFO_AVX512BW) && have_avx512vl) 25 #define have_avx512dq ((cpuinfo & CPUINFO_AVX512DQ) && have_avx512vl) 26 #define have_avx512vbmi2 ((cpuinfo & CPUINFO_AVX512VBMI2) && have_avx512vl) 27 28 /* optional instructions */ 29 #define TCG_TARGET_HAS_div2_i32 1 30 #define TCG_TARGET_HAS_rot_i32 1 31 #define TCG_TARGET_HAS_bswap16_i32 1 32 #define TCG_TARGET_HAS_bswap32_i32 1 33 #define TCG_TARGET_HAS_not_i32 1 34 #define TCG_TARGET_HAS_clz_i32 1 35 #define TCG_TARGET_HAS_ctz_i32 1 36 #define TCG_TARGET_HAS_ctpop_i32 have_popcnt 37 #define TCG_TARGET_HAS_extract2_i32 1 38 #define TCG_TARGET_HAS_negsetcond_i32 1 39 #define TCG_TARGET_HAS_add2_i32 1 40 #define TCG_TARGET_HAS_sub2_i32 1 41 #define TCG_TARGET_HAS_mulu2_i32 1 42 #define TCG_TARGET_HAS_muls2_i32 1 43 #define TCG_TARGET_HAS_muluh_i32 0 44 #define TCG_TARGET_HAS_mulsh_i32 0 45 46 #if TCG_TARGET_REG_BITS == 64 47 /* Keep 32-bit values zero-extended in a register. */ 48 #define TCG_TARGET_HAS_extr_i64_i32 1 49 #define TCG_TARGET_HAS_div2_i64 1 50 #define TCG_TARGET_HAS_rot_i64 1 51 #define TCG_TARGET_HAS_bswap16_i64 1 52 #define TCG_TARGET_HAS_bswap32_i64 1 53 #define TCG_TARGET_HAS_bswap64_i64 1 54 #define TCG_TARGET_HAS_not_i64 1 55 #define TCG_TARGET_HAS_clz_i64 1 56 #define TCG_TARGET_HAS_ctz_i64 1 57 #define TCG_TARGET_HAS_ctpop_i64 have_popcnt 58 #define TCG_TARGET_HAS_extract2_i64 1 59 #define TCG_TARGET_HAS_negsetcond_i64 1 60 #define TCG_TARGET_HAS_add2_i64 1 61 #define TCG_TARGET_HAS_sub2_i64 1 62 #define TCG_TARGET_HAS_mulu2_i64 1 63 #define TCG_TARGET_HAS_muls2_i64 1 64 #define TCG_TARGET_HAS_muluh_i64 0 65 #define TCG_TARGET_HAS_mulsh_i64 0 66 #define TCG_TARGET_HAS_qemu_st8_i32 0 67 #else 68 #define TCG_TARGET_HAS_qemu_st8_i32 1 69 #endif 70 71 #define TCG_TARGET_HAS_qemu_ldst_i128 \ 72 (TCG_TARGET_REG_BITS == 64 && (cpuinfo & CPUINFO_ATOMIC_VMOVDQA)) 73 74 #define TCG_TARGET_HAS_tst 1 75 76 /* We do not support older SSE systems, only beginning with AVX1. */ 77 #define TCG_TARGET_HAS_v64 have_avx1 78 #define TCG_TARGET_HAS_v128 have_avx1 79 #define TCG_TARGET_HAS_v256 have_avx2 80 81 #define TCG_TARGET_HAS_andc_vec 1 82 #define TCG_TARGET_HAS_orc_vec have_avx512vl 83 #define TCG_TARGET_HAS_nand_vec have_avx512vl 84 #define TCG_TARGET_HAS_nor_vec have_avx512vl 85 #define TCG_TARGET_HAS_eqv_vec have_avx512vl 86 #define TCG_TARGET_HAS_not_vec have_avx512vl 87 #define TCG_TARGET_HAS_neg_vec 0 88 #define TCG_TARGET_HAS_abs_vec 1 89 #define TCG_TARGET_HAS_roti_vec have_avx512vl 90 #define TCG_TARGET_HAS_rots_vec 0 91 #define TCG_TARGET_HAS_rotv_vec have_avx512vl 92 #define TCG_TARGET_HAS_shi_vec 1 93 #define TCG_TARGET_HAS_shs_vec 1 94 #define TCG_TARGET_HAS_shv_vec have_avx2 95 #define TCG_TARGET_HAS_mul_vec 1 96 #define TCG_TARGET_HAS_sat_vec 1 97 #define TCG_TARGET_HAS_minmax_vec 1 98 #define TCG_TARGET_HAS_bitsel_vec have_avx512vl 99 #define TCG_TARGET_HAS_cmpsel_vec 1 100 #define TCG_TARGET_HAS_tst_vec have_avx512bw 101 102 #define TCG_TARGET_deposit_valid(type, ofs, len) \ 103 (((ofs) == 0 && ((len) == 8 || (len) == 16)) || \ 104 (TCG_TARGET_REG_BITS == 32 && (ofs) == 8 && (len) == 8)) 105 106 /* 107 * Check for the possibility of low byte/word extraction, high-byte extraction 108 * and zero-extending 32-bit right-shift. 109 * 110 * We cannot sign-extend from high byte to 64-bits without using the 111 * REX prefix that explicitly excludes access to the high-byte registers. 112 */ 113 static inline bool 114 tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len) 115 { 116 switch (ofs) { 117 case 0: 118 switch (len) { 119 case 8: 120 case 16: 121 return true; 122 case 32: 123 return type == TCG_TYPE_I64; 124 } 125 return false; 126 case 8: 127 return len == 8 && type == TCG_TYPE_I32; 128 } 129 return false; 130 } 131 #define TCG_TARGET_sextract_valid tcg_target_sextract_valid 132 133 static inline bool 134 tcg_target_extract_valid(TCGType type, unsigned ofs, unsigned len) 135 { 136 if (type == TCG_TYPE_I64 && ofs + len == 32) { 137 return true; 138 } 139 switch (ofs) { 140 case 0: 141 return len == 8 || len == 16; 142 case 8: 143 return len == 8; 144 } 145 return false; 146 } 147 #define TCG_TARGET_extract_valid tcg_target_extract_valid 148 149 #endif 150