1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Define i386 target-specific operand constraints. 4 * Copyright (c) 2021 Linaro 5 * 6 */ 7 8 /* 9 * Define constraint letters for register sets: 10 * REGS(letter, register_mask) 11 */ 12 REGS('a', 1u << TCG_REG_EAX) 13 REGS('b', 1u << TCG_REG_EBX) 14 REGS('c', 1u << TCG_REG_ECX) 15 REGS('d', 1u << TCG_REG_EDX) 16 REGS('S', 1u << TCG_REG_ESI) 17 REGS('D', 1u << TCG_REG_EDI) 18 19 REGS('r', ALL_GENERAL_REGS) 20 REGS('x', ALL_VECTOR_REGS) 21 REGS('q', ALL_BYTEL_REGS) /* regs that can be used as a byte operand */ 22 REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) /* qemu_ld/st */ 23 REGS('s', ALL_BYTEL_REGS & ~SOFTMMU_RESERVE_REGS) /* qemu_st8_i32 data */ 24 25 /* 26 * Define constraint letters for constants: 27 * CONST(letter, TCG_CT_CONST_* bit set) 28 */ 29 CONST('e', TCG_CT_CONST_S32) 30 CONST('I', TCG_CT_CONST_I32) 31 CONST('O', TCG_CT_CONST_ZERO) 32 CONST('T', TCG_CT_CONST_TST) 33 CONST('W', TCG_CT_CONST_WSZ) 34 CONST('Z', TCG_CT_CONST_U32) 35