1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * Copyright (c) 2008 Andrzej Zaborowski 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #ifndef ARM_TCG_TARGET_H 27 #define ARM_TCG_TARGET_H 28 29 extern int arm_arch; 30 31 #define use_armv7_instructions (__ARM_ARCH >= 7 || arm_arch >= 7) 32 33 #define TCG_TARGET_INSN_UNIT_SIZE 4 34 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 16 35 #define MAX_CODE_GEN_BUFFER_SIZE UINT32_MAX 36 37 typedef enum { 38 TCG_REG_R0 = 0, 39 TCG_REG_R1, 40 TCG_REG_R2, 41 TCG_REG_R3, 42 TCG_REG_R4, 43 TCG_REG_R5, 44 TCG_REG_R6, 45 TCG_REG_R7, 46 TCG_REG_R8, 47 TCG_REG_R9, 48 TCG_REG_R10, 49 TCG_REG_R11, 50 TCG_REG_R12, 51 TCG_REG_R13, 52 TCG_REG_R14, 53 TCG_REG_PC, 54 55 TCG_REG_Q0, 56 TCG_REG_Q1, 57 TCG_REG_Q2, 58 TCG_REG_Q3, 59 TCG_REG_Q4, 60 TCG_REG_Q5, 61 TCG_REG_Q6, 62 TCG_REG_Q7, 63 TCG_REG_Q8, 64 TCG_REG_Q9, 65 TCG_REG_Q10, 66 TCG_REG_Q11, 67 TCG_REG_Q12, 68 TCG_REG_Q13, 69 TCG_REG_Q14, 70 TCG_REG_Q15, 71 72 TCG_AREG0 = TCG_REG_R6, 73 TCG_REG_CALL_STACK = TCG_REG_R13, 74 } TCGReg; 75 76 #define TCG_TARGET_NB_REGS 32 77 78 #ifdef __ARM_ARCH_EXT_IDIV__ 79 #define use_idiv_instructions 1 80 #else 81 extern bool use_idiv_instructions; 82 #endif 83 #ifdef __ARM_NEON__ 84 #define use_neon_instructions 1 85 #else 86 extern bool use_neon_instructions; 87 #endif 88 89 /* used for function call generation */ 90 #define TCG_TARGET_STACK_ALIGN 8 91 #define TCG_TARGET_CALL_STACK_OFFSET 0 92 #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL 93 #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN 94 95 /* optional instructions */ 96 #define TCG_TARGET_HAS_ext8s_i32 1 97 #define TCG_TARGET_HAS_ext16s_i32 1 98 #define TCG_TARGET_HAS_ext8u_i32 0 /* and r0, r1, #0xff */ 99 #define TCG_TARGET_HAS_ext16u_i32 1 100 #define TCG_TARGET_HAS_bswap16_i32 1 101 #define TCG_TARGET_HAS_bswap32_i32 1 102 #define TCG_TARGET_HAS_not_i32 1 103 #define TCG_TARGET_HAS_neg_i32 1 104 #define TCG_TARGET_HAS_rot_i32 1 105 #define TCG_TARGET_HAS_andc_i32 1 106 #define TCG_TARGET_HAS_orc_i32 0 107 #define TCG_TARGET_HAS_eqv_i32 0 108 #define TCG_TARGET_HAS_nand_i32 0 109 #define TCG_TARGET_HAS_nor_i32 0 110 #define TCG_TARGET_HAS_clz_i32 1 111 #define TCG_TARGET_HAS_ctz_i32 use_armv7_instructions 112 #define TCG_TARGET_HAS_ctpop_i32 0 113 #define TCG_TARGET_HAS_deposit_i32 use_armv7_instructions 114 #define TCG_TARGET_HAS_extract_i32 use_armv7_instructions 115 #define TCG_TARGET_HAS_sextract_i32 use_armv7_instructions 116 #define TCG_TARGET_HAS_extract2_i32 1 117 #define TCG_TARGET_HAS_movcond_i32 1 118 #define TCG_TARGET_HAS_mulu2_i32 1 119 #define TCG_TARGET_HAS_muls2_i32 1 120 #define TCG_TARGET_HAS_muluh_i32 0 121 #define TCG_TARGET_HAS_mulsh_i32 0 122 #define TCG_TARGET_HAS_div_i32 use_idiv_instructions 123 #define TCG_TARGET_HAS_rem_i32 0 124 #define TCG_TARGET_HAS_qemu_st8_i32 0 125 126 #define TCG_TARGET_HAS_v64 use_neon_instructions 127 #define TCG_TARGET_HAS_v128 use_neon_instructions 128 #define TCG_TARGET_HAS_v256 0 129 130 #define TCG_TARGET_HAS_andc_vec 1 131 #define TCG_TARGET_HAS_orc_vec 1 132 #define TCG_TARGET_HAS_nand_vec 0 133 #define TCG_TARGET_HAS_nor_vec 0 134 #define TCG_TARGET_HAS_eqv_vec 0 135 #define TCG_TARGET_HAS_not_vec 1 136 #define TCG_TARGET_HAS_neg_vec 1 137 #define TCG_TARGET_HAS_abs_vec 1 138 #define TCG_TARGET_HAS_roti_vec 0 139 #define TCG_TARGET_HAS_rots_vec 0 140 #define TCG_TARGET_HAS_rotv_vec 0 141 #define TCG_TARGET_HAS_shi_vec 1 142 #define TCG_TARGET_HAS_shs_vec 0 143 #define TCG_TARGET_HAS_shv_vec 0 144 #define TCG_TARGET_HAS_mul_vec 1 145 #define TCG_TARGET_HAS_sat_vec 1 146 #define TCG_TARGET_HAS_minmax_vec 1 147 #define TCG_TARGET_HAS_bitsel_vec 1 148 #define TCG_TARGET_HAS_cmpsel_vec 0 149 150 #define TCG_TARGET_DEFAULT_MO (0) 151 #define TCG_TARGET_HAS_MEMORY_BSWAP 0 152 #define TCG_TARGET_NEED_LDST_LABELS 153 #define TCG_TARGET_NEED_POOL_LABELS 154 155 #endif 156