1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * Copyright (c) 2008 Andrzej Zaborowski 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #ifndef ARM_TCG_TARGET_H 27 #define ARM_TCG_TARGET_H 28 29 /* The __ARM_ARCH define is provided by gcc 4.8. Construct it otherwise. */ 30 #ifndef __ARM_ARCH 31 # if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) \ 32 || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) \ 33 || defined(__ARM_ARCH_7EM__) 34 # define __ARM_ARCH 7 35 # elif defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) \ 36 || defined(__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6ZK__) \ 37 || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6T2__) 38 # define __ARM_ARCH 6 39 # elif defined(__ARM_ARCH_5__) || defined(__ARM_ARCH_5E__) \ 40 || defined(__ARM_ARCH_5T__) || defined(__ARM_ARCH_5TE__) \ 41 || defined(__ARM_ARCH_5TEJ__) 42 # define __ARM_ARCH 5 43 # else 44 # define __ARM_ARCH 4 45 # endif 46 #endif 47 48 extern int arm_arch; 49 50 #if defined(__ARM_ARCH_5T__) \ 51 || defined(__ARM_ARCH_5TE__) || defined(__ARM_ARCH_5TEJ__) 52 # define use_armv5t_instructions 1 53 #else 54 # define use_armv5t_instructions use_armv6_instructions 55 #endif 56 57 #define use_armv6_instructions (__ARM_ARCH >= 6 || arm_arch >= 6) 58 #define use_armv7_instructions (__ARM_ARCH >= 7 || arm_arch >= 7) 59 60 #undef TCG_TARGET_STACK_GROWSUP 61 #define TCG_TARGET_INSN_UNIT_SIZE 4 62 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 16 63 #define MAX_CODE_GEN_BUFFER_SIZE UINT32_MAX 64 65 typedef enum { 66 TCG_REG_R0 = 0, 67 TCG_REG_R1, 68 TCG_REG_R2, 69 TCG_REG_R3, 70 TCG_REG_R4, 71 TCG_REG_R5, 72 TCG_REG_R6, 73 TCG_REG_R7, 74 TCG_REG_R8, 75 TCG_REG_R9, 76 TCG_REG_R10, 77 TCG_REG_R11, 78 TCG_REG_R12, 79 TCG_REG_R13, 80 TCG_REG_R14, 81 TCG_REG_PC, 82 83 TCG_REG_Q0, 84 TCG_REG_Q1, 85 TCG_REG_Q2, 86 TCG_REG_Q3, 87 TCG_REG_Q4, 88 TCG_REG_Q5, 89 TCG_REG_Q6, 90 TCG_REG_Q7, 91 TCG_REG_Q8, 92 TCG_REG_Q9, 93 TCG_REG_Q10, 94 TCG_REG_Q11, 95 TCG_REG_Q12, 96 TCG_REG_Q13, 97 TCG_REG_Q14, 98 TCG_REG_Q15, 99 100 TCG_AREG0 = TCG_REG_R6, 101 TCG_REG_CALL_STACK = TCG_REG_R13, 102 } TCGReg; 103 104 #define TCG_TARGET_NB_REGS 32 105 106 #ifdef __ARM_ARCH_EXT_IDIV__ 107 #define use_idiv_instructions 1 108 #else 109 extern bool use_idiv_instructions; 110 #endif 111 #ifdef __ARM_NEON__ 112 #define use_neon_instructions 1 113 #else 114 extern bool use_neon_instructions; 115 #endif 116 117 /* used for function call generation */ 118 #define TCG_TARGET_STACK_ALIGN 8 119 #define TCG_TARGET_CALL_ALIGN_ARGS 1 120 #define TCG_TARGET_CALL_STACK_OFFSET 0 121 122 /* optional instructions */ 123 #define TCG_TARGET_HAS_ext8s_i32 1 124 #define TCG_TARGET_HAS_ext16s_i32 1 125 #define TCG_TARGET_HAS_ext8u_i32 0 /* and r0, r1, #0xff */ 126 #define TCG_TARGET_HAS_ext16u_i32 1 127 #define TCG_TARGET_HAS_bswap16_i32 1 128 #define TCG_TARGET_HAS_bswap32_i32 1 129 #define TCG_TARGET_HAS_not_i32 1 130 #define TCG_TARGET_HAS_neg_i32 1 131 #define TCG_TARGET_HAS_rot_i32 1 132 #define TCG_TARGET_HAS_andc_i32 1 133 #define TCG_TARGET_HAS_orc_i32 0 134 #define TCG_TARGET_HAS_eqv_i32 0 135 #define TCG_TARGET_HAS_nand_i32 0 136 #define TCG_TARGET_HAS_nor_i32 0 137 #define TCG_TARGET_HAS_clz_i32 use_armv5t_instructions 138 #define TCG_TARGET_HAS_ctz_i32 use_armv7_instructions 139 #define TCG_TARGET_HAS_ctpop_i32 0 140 #define TCG_TARGET_HAS_deposit_i32 use_armv7_instructions 141 #define TCG_TARGET_HAS_extract_i32 use_armv7_instructions 142 #define TCG_TARGET_HAS_sextract_i32 use_armv7_instructions 143 #define TCG_TARGET_HAS_extract2_i32 1 144 #define TCG_TARGET_HAS_movcond_i32 1 145 #define TCG_TARGET_HAS_mulu2_i32 1 146 #define TCG_TARGET_HAS_muls2_i32 1 147 #define TCG_TARGET_HAS_muluh_i32 0 148 #define TCG_TARGET_HAS_mulsh_i32 0 149 #define TCG_TARGET_HAS_div_i32 use_idiv_instructions 150 #define TCG_TARGET_HAS_rem_i32 0 151 #define TCG_TARGET_HAS_direct_jump 0 152 #define TCG_TARGET_HAS_qemu_st8_i32 0 153 154 #define TCG_TARGET_HAS_v64 use_neon_instructions 155 #define TCG_TARGET_HAS_v128 use_neon_instructions 156 #define TCG_TARGET_HAS_v256 0 157 158 #define TCG_TARGET_HAS_andc_vec 1 159 #define TCG_TARGET_HAS_orc_vec 1 160 #define TCG_TARGET_HAS_not_vec 1 161 #define TCG_TARGET_HAS_neg_vec 1 162 #define TCG_TARGET_HAS_abs_vec 1 163 #define TCG_TARGET_HAS_roti_vec 0 164 #define TCG_TARGET_HAS_rots_vec 0 165 #define TCG_TARGET_HAS_rotv_vec 0 166 #define TCG_TARGET_HAS_shi_vec 1 167 #define TCG_TARGET_HAS_shs_vec 0 168 #define TCG_TARGET_HAS_shv_vec 0 169 #define TCG_TARGET_HAS_mul_vec 1 170 #define TCG_TARGET_HAS_sat_vec 1 171 #define TCG_TARGET_HAS_minmax_vec 1 172 #define TCG_TARGET_HAS_bitsel_vec 1 173 #define TCG_TARGET_HAS_cmpsel_vec 0 174 175 #define TCG_TARGET_DEFAULT_MO (0) 176 #define TCG_TARGET_HAS_MEMORY_BSWAP 0 177 178 /* not defined -- call should be eliminated at compile time */ 179 void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); 180 181 #ifdef CONFIG_SOFTMMU 182 #define TCG_TARGET_NEED_LDST_LABELS 183 #endif 184 #define TCG_TARGET_NEED_POOL_LABELS 185 186 #endif 187