1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Andrzej Zaborowski 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25#include "elf.h" 26 27int arm_arch = __ARM_ARCH; 28 29#ifndef use_idiv_instructions 30bool use_idiv_instructions; 31#endif 32#ifndef use_neon_instructions 33bool use_neon_instructions; 34#endif 35 36/* Used for function call generation. */ 37#define TCG_TARGET_STACK_ALIGN 8 38#define TCG_TARGET_CALL_STACK_OFFSET 0 39#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL 40#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN 41#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN 42#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF 43 44#ifdef CONFIG_DEBUG_TCG 45static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 46 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", 47 "%r8", "%r9", "%r10", "%r11", "%r12", "%sp", "%r14", "%pc", 48 "%q0", "%q1", "%q2", "%q3", "%q4", "%q5", "%q6", "%q7", 49 "%q8", "%q9", "%q10", "%q11", "%q12", "%q13", "%q14", "%q15", 50}; 51#endif 52 53static const int tcg_target_reg_alloc_order[] = { 54 TCG_REG_R4, 55 TCG_REG_R5, 56 TCG_REG_R6, 57 TCG_REG_R7, 58 TCG_REG_R8, 59 TCG_REG_R9, 60 TCG_REG_R10, 61 TCG_REG_R11, 62 TCG_REG_R13, 63 TCG_REG_R0, 64 TCG_REG_R1, 65 TCG_REG_R2, 66 TCG_REG_R3, 67 TCG_REG_R12, 68 TCG_REG_R14, 69 70 TCG_REG_Q0, 71 TCG_REG_Q1, 72 TCG_REG_Q2, 73 TCG_REG_Q3, 74 /* Q4 - Q7 are call-saved, and skipped. */ 75 TCG_REG_Q8, 76 TCG_REG_Q9, 77 TCG_REG_Q10, 78 TCG_REG_Q11, 79 TCG_REG_Q12, 80 TCG_REG_Q13, 81 TCG_REG_Q14, 82 TCG_REG_Q15, 83}; 84 85static const int tcg_target_call_iarg_regs[4] = { 86 TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3 87}; 88 89static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 90{ 91 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 92 tcg_debug_assert(slot >= 0 && slot <= 3); 93 return TCG_REG_R0 + slot; 94} 95 96#define TCG_REG_TMP TCG_REG_R12 97#define TCG_VEC_TMP TCG_REG_Q15 98#define TCG_REG_GUEST_BASE TCG_REG_R11 99 100typedef enum { 101 COND_EQ = 0x0, 102 COND_NE = 0x1, 103 COND_CS = 0x2, /* Unsigned greater or equal */ 104 COND_CC = 0x3, /* Unsigned less than */ 105 COND_MI = 0x4, /* Negative */ 106 COND_PL = 0x5, /* Zero or greater */ 107 COND_VS = 0x6, /* Overflow */ 108 COND_VC = 0x7, /* No overflow */ 109 COND_HI = 0x8, /* Unsigned greater than */ 110 COND_LS = 0x9, /* Unsigned less or equal */ 111 COND_GE = 0xa, 112 COND_LT = 0xb, 113 COND_GT = 0xc, 114 COND_LE = 0xd, 115 COND_AL = 0xe, 116} ARMCond; 117 118#define TO_CPSR (1 << 20) 119 120#define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00) 121#define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20) 122#define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40) 123#define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60) 124#define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10) 125#define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30) 126#define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50) 127#define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70) 128 129typedef enum { 130 ARITH_AND = 0x0 << 21, 131 ARITH_EOR = 0x1 << 21, 132 ARITH_SUB = 0x2 << 21, 133 ARITH_RSB = 0x3 << 21, 134 ARITH_ADD = 0x4 << 21, 135 ARITH_ADC = 0x5 << 21, 136 ARITH_SBC = 0x6 << 21, 137 ARITH_RSC = 0x7 << 21, 138 ARITH_TST = 0x8 << 21 | TO_CPSR, 139 ARITH_CMP = 0xa << 21 | TO_CPSR, 140 ARITH_CMN = 0xb << 21 | TO_CPSR, 141 ARITH_ORR = 0xc << 21, 142 ARITH_MOV = 0xd << 21, 143 ARITH_BIC = 0xe << 21, 144 ARITH_MVN = 0xf << 21, 145 146 INSN_B = 0x0a000000, 147 148 INSN_CLZ = 0x016f0f10, 149 INSN_RBIT = 0x06ff0f30, 150 151 INSN_LDMIA = 0x08b00000, 152 INSN_STMDB = 0x09200000, 153 154 INSN_LDR_IMM = 0x04100000, 155 INSN_LDR_REG = 0x06100000, 156 INSN_STR_IMM = 0x04000000, 157 INSN_STR_REG = 0x06000000, 158 159 INSN_LDRH_IMM = 0x005000b0, 160 INSN_LDRH_REG = 0x001000b0, 161 INSN_LDRSH_IMM = 0x005000f0, 162 INSN_LDRSH_REG = 0x001000f0, 163 INSN_STRH_IMM = 0x004000b0, 164 INSN_STRH_REG = 0x000000b0, 165 166 INSN_LDRB_IMM = 0x04500000, 167 INSN_LDRB_REG = 0x06500000, 168 INSN_LDRSB_IMM = 0x005000d0, 169 INSN_LDRSB_REG = 0x001000d0, 170 INSN_STRB_IMM = 0x04400000, 171 INSN_STRB_REG = 0x06400000, 172 173 INSN_LDRD_IMM = 0x004000d0, 174 INSN_LDRD_REG = 0x000000d0, 175 INSN_STRD_IMM = 0x004000f0, 176 INSN_STRD_REG = 0x000000f0, 177 178 INSN_DMB_ISH = 0xf57ff05b, 179 INSN_DMB_MCR = 0xee070fba, 180 181 /* Architected nop introduced in v6k. */ 182 /* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this 183 also Just So Happened to do nothing on pre-v6k so that we 184 don't need to conditionalize it? */ 185 INSN_NOP_v6k = 0xe320f000, 186 /* Otherwise the assembler uses mov r0,r0 */ 187 INSN_NOP_v4 = (COND_AL << 28) | ARITH_MOV, 188 189 INSN_VADD = 0xf2000800, 190 INSN_VAND = 0xf2000110, 191 INSN_VBIC = 0xf2100110, 192 INSN_VEOR = 0xf3000110, 193 INSN_VORN = 0xf2300110, 194 INSN_VORR = 0xf2200110, 195 INSN_VSUB = 0xf3000800, 196 INSN_VMUL = 0xf2000910, 197 INSN_VQADD = 0xf2000010, 198 INSN_VQADD_U = 0xf3000010, 199 INSN_VQSUB = 0xf2000210, 200 INSN_VQSUB_U = 0xf3000210, 201 INSN_VMAX = 0xf2000600, 202 INSN_VMAX_U = 0xf3000600, 203 INSN_VMIN = 0xf2000610, 204 INSN_VMIN_U = 0xf3000610, 205 206 INSN_VABS = 0xf3b10300, 207 INSN_VMVN = 0xf3b00580, 208 INSN_VNEG = 0xf3b10380, 209 210 INSN_VCEQ0 = 0xf3b10100, 211 INSN_VCGT0 = 0xf3b10000, 212 INSN_VCGE0 = 0xf3b10080, 213 INSN_VCLE0 = 0xf3b10180, 214 INSN_VCLT0 = 0xf3b10200, 215 216 INSN_VCEQ = 0xf3000810, 217 INSN_VCGE = 0xf2000310, 218 INSN_VCGT = 0xf2000300, 219 INSN_VCGE_U = 0xf3000310, 220 INSN_VCGT_U = 0xf3000300, 221 222 INSN_VSHLI = 0xf2800510, /* VSHL (immediate) */ 223 INSN_VSARI = 0xf2800010, /* VSHR.S */ 224 INSN_VSHRI = 0xf3800010, /* VSHR.U */ 225 INSN_VSLI = 0xf3800510, 226 INSN_VSHL_S = 0xf2000400, /* VSHL.S (register) */ 227 INSN_VSHL_U = 0xf3000400, /* VSHL.U (register) */ 228 229 INSN_VBSL = 0xf3100110, 230 INSN_VBIT = 0xf3200110, 231 INSN_VBIF = 0xf3300110, 232 233 INSN_VTST = 0xf2000810, 234 235 INSN_VDUP_G = 0xee800b10, /* VDUP (ARM core register) */ 236 INSN_VDUP_S = 0xf3b00c00, /* VDUP (scalar) */ 237 INSN_VLDR_D = 0xed100b00, /* VLDR.64 */ 238 INSN_VLD1 = 0xf4200000, /* VLD1 (multiple single elements) */ 239 INSN_VLD1R = 0xf4a00c00, /* VLD1 (single element to all lanes) */ 240 INSN_VST1 = 0xf4000000, /* VST1 (multiple single elements) */ 241 INSN_VMOVI = 0xf2800010, /* VMOV (immediate) */ 242} ARMInsn; 243 244#define INSN_NOP (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4) 245 246static const uint8_t tcg_cond_to_arm_cond[] = { 247 [TCG_COND_EQ] = COND_EQ, 248 [TCG_COND_NE] = COND_NE, 249 [TCG_COND_LT] = COND_LT, 250 [TCG_COND_GE] = COND_GE, 251 [TCG_COND_LE] = COND_LE, 252 [TCG_COND_GT] = COND_GT, 253 /* unsigned */ 254 [TCG_COND_LTU] = COND_CC, 255 [TCG_COND_GEU] = COND_CS, 256 [TCG_COND_LEU] = COND_LS, 257 [TCG_COND_GTU] = COND_HI, 258}; 259 260static int encode_imm(uint32_t imm); 261 262/* TCG private relocation type: add with pc+imm8 */ 263#define R_ARM_PC8 11 264 265/* TCG private relocation type: vldr with imm8 << 2 */ 266#define R_ARM_PC11 12 267 268static bool reloc_pc24(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 269{ 270 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 271 ptrdiff_t offset = (tcg_ptr_byte_diff(target, src_rx) - 8) >> 2; 272 273 if (offset == sextract32(offset, 0, 24)) { 274 *src_rw = deposit32(*src_rw, 0, 24, offset); 275 return true; 276 } 277 return false; 278} 279 280static bool reloc_pc13(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 281{ 282 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 283 ptrdiff_t offset = tcg_ptr_byte_diff(target, src_rx) - 8; 284 285 if (offset >= -0xfff && offset <= 0xfff) { 286 tcg_insn_unit insn = *src_rw; 287 bool u = (offset >= 0); 288 if (!u) { 289 offset = -offset; 290 } 291 insn = deposit32(insn, 23, 1, u); 292 insn = deposit32(insn, 0, 12, offset); 293 *src_rw = insn; 294 return true; 295 } 296 return false; 297} 298 299static bool reloc_pc11(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 300{ 301 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 302 ptrdiff_t offset = (tcg_ptr_byte_diff(target, src_rx) - 8) / 4; 303 304 if (offset >= -0xff && offset <= 0xff) { 305 tcg_insn_unit insn = *src_rw; 306 bool u = (offset >= 0); 307 if (!u) { 308 offset = -offset; 309 } 310 insn = deposit32(insn, 23, 1, u); 311 insn = deposit32(insn, 0, 8, offset); 312 *src_rw = insn; 313 return true; 314 } 315 return false; 316} 317 318static bool reloc_pc8(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 319{ 320 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 321 ptrdiff_t offset = tcg_ptr_byte_diff(target, src_rx) - 8; 322 int imm12 = encode_imm(offset); 323 324 if (imm12 >= 0) { 325 *src_rw = deposit32(*src_rw, 0, 12, imm12); 326 return true; 327 } 328 return false; 329} 330 331static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 332 intptr_t value, intptr_t addend) 333{ 334 tcg_debug_assert(addend == 0); 335 switch (type) { 336 case R_ARM_PC24: 337 return reloc_pc24(code_ptr, (const tcg_insn_unit *)value); 338 case R_ARM_PC13: 339 return reloc_pc13(code_ptr, (const tcg_insn_unit *)value); 340 case R_ARM_PC11: 341 return reloc_pc11(code_ptr, (const tcg_insn_unit *)value); 342 case R_ARM_PC8: 343 return reloc_pc8(code_ptr, (const tcg_insn_unit *)value); 344 default: 345 g_assert_not_reached(); 346 } 347} 348 349#define TCG_CT_CONST_ARM 0x100 350#define TCG_CT_CONST_INV 0x200 351#define TCG_CT_CONST_NEG 0x400 352#define TCG_CT_CONST_ZERO 0x800 353#define TCG_CT_CONST_ORRI 0x1000 354#define TCG_CT_CONST_ANDI 0x2000 355 356#define ALL_GENERAL_REGS 0xffffu 357#define ALL_VECTOR_REGS 0xffff0000u 358 359/* 360 * r0-r3 will be overwritten when reading the tlb entry (system-mode only); 361 * r14 will be overwritten by the BLNE branching to the slow path. 362 */ 363#define ALL_QLDST_REGS \ 364 (ALL_GENERAL_REGS & ~((tcg_use_softmmu ? 0xf : 0) | (1 << TCG_REG_R14))) 365 366/* 367 * ARM immediates for ALU instructions are made of an unsigned 8-bit 368 * right-rotated by an even amount between 0 and 30. 369 * 370 * Return < 0 if @imm cannot be encoded, else the entire imm12 field. 371 */ 372static int encode_imm(uint32_t imm) 373{ 374 uint32_t rot, imm8; 375 376 /* Simple case, no rotation required. */ 377 if ((imm & ~0xff) == 0) { 378 return imm; 379 } 380 381 /* Next, try a simple even shift. */ 382 rot = ctz32(imm) & ~1; 383 imm8 = imm >> rot; 384 rot = 32 - rot; 385 if ((imm8 & ~0xff) == 0) { 386 goto found; 387 } 388 389 /* 390 * Finally, try harder with rotations. 391 * The ctz test above will have taken care of rotates >= 8. 392 */ 393 for (rot = 2; rot < 8; rot += 2) { 394 imm8 = rol32(imm, rot); 395 if ((imm8 & ~0xff) == 0) { 396 goto found; 397 } 398 } 399 /* Fail: imm cannot be encoded. */ 400 return -1; 401 402 found: 403 /* Note that rot is even, and we discard bit 0 by shifting by 7. */ 404 return rot << 7 | imm8; 405} 406 407static int encode_imm_nofail(uint32_t imm) 408{ 409 int ret = encode_imm(imm); 410 tcg_debug_assert(ret >= 0); 411 return ret; 412} 413 414static bool check_fit_imm(uint32_t imm) 415{ 416 return encode_imm(imm) >= 0; 417} 418 419/* Return true if v16 is a valid 16-bit shifted immediate. */ 420static bool is_shimm16(uint16_t v16, int *cmode, int *imm8) 421{ 422 if (v16 == (v16 & 0xff)) { 423 *cmode = 0x8; 424 *imm8 = v16 & 0xff; 425 return true; 426 } else if (v16 == (v16 & 0xff00)) { 427 *cmode = 0xa; 428 *imm8 = v16 >> 8; 429 return true; 430 } 431 return false; 432} 433 434/* Return true if v32 is a valid 32-bit shifted immediate. */ 435static bool is_shimm32(uint32_t v32, int *cmode, int *imm8) 436{ 437 if (v32 == (v32 & 0xff)) { 438 *cmode = 0x0; 439 *imm8 = v32 & 0xff; 440 return true; 441 } else if (v32 == (v32 & 0xff00)) { 442 *cmode = 0x2; 443 *imm8 = (v32 >> 8) & 0xff; 444 return true; 445 } else if (v32 == (v32 & 0xff0000)) { 446 *cmode = 0x4; 447 *imm8 = (v32 >> 16) & 0xff; 448 return true; 449 } else if (v32 == (v32 & 0xff000000)) { 450 *cmode = 0x6; 451 *imm8 = v32 >> 24; 452 return true; 453 } 454 return false; 455} 456 457/* Return true if v32 is a valid 32-bit shifting ones immediate. */ 458static bool is_soimm32(uint32_t v32, int *cmode, int *imm8) 459{ 460 if ((v32 & 0xffff00ff) == 0xff) { 461 *cmode = 0xc; 462 *imm8 = (v32 >> 8) & 0xff; 463 return true; 464 } else if ((v32 & 0xff00ffff) == 0xffff) { 465 *cmode = 0xd; 466 *imm8 = (v32 >> 16) & 0xff; 467 return true; 468 } 469 return false; 470} 471 472/* 473 * Return non-zero if v32 can be formed by MOVI+ORR. 474 * Place the parameters for MOVI in (cmode, imm8). 475 * Return the cmode for ORR; the imm8 can be had via extraction from v32. 476 */ 477static int is_shimm32_pair(uint32_t v32, int *cmode, int *imm8) 478{ 479 int i; 480 481 for (i = 6; i > 0; i -= 2) { 482 /* Mask out one byte we can add with ORR. */ 483 uint32_t tmp = v32 & ~(0xffu << (i * 4)); 484 if (is_shimm32(tmp, cmode, imm8) || 485 is_soimm32(tmp, cmode, imm8)) { 486 break; 487 } 488 } 489 return i; 490} 491 492/* Return true if V is a valid 16-bit or 32-bit shifted immediate. */ 493static bool is_shimm1632(uint32_t v32, int *cmode, int *imm8) 494{ 495 if (v32 == deposit32(v32, 16, 16, v32)) { 496 return is_shimm16(v32, cmode, imm8); 497 } else { 498 return is_shimm32(v32, cmode, imm8); 499 } 500} 501 502/* Test if a constant matches the constraint. 503 * TODO: define constraints for: 504 * 505 * ldr/str offset: between -0xfff and 0xfff 506 * ldrh/strh offset: between -0xff and 0xff 507 * mov operand2: values represented with x << (2 * y), x < 0x100 508 * add, sub, eor...: ditto 509 */ 510static bool tcg_target_const_match(int64_t val, int ct, 511 TCGType type, TCGCond cond, int vece) 512{ 513 if (ct & TCG_CT_CONST) { 514 return 1; 515 } else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val)) { 516 return 1; 517 } else if ((ct & TCG_CT_CONST_INV) && check_fit_imm(~val)) { 518 return 1; 519 } else if ((ct & TCG_CT_CONST_NEG) && check_fit_imm(-val)) { 520 return 1; 521 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 522 return 1; 523 } 524 525 switch (ct & (TCG_CT_CONST_ORRI | TCG_CT_CONST_ANDI)) { 526 case 0: 527 break; 528 case TCG_CT_CONST_ANDI: 529 val = ~val; 530 /* fallthru */ 531 case TCG_CT_CONST_ORRI: 532 if (val == deposit64(val, 32, 32, val)) { 533 int cmode, imm8; 534 return is_shimm1632(val, &cmode, &imm8); 535 } 536 break; 537 default: 538 /* Both bits should not be set for the same insn. */ 539 g_assert_not_reached(); 540 } 541 542 return 0; 543} 544 545static void tcg_out_b_imm(TCGContext *s, ARMCond cond, int32_t offset) 546{ 547 tcg_out32(s, (cond << 28) | INSN_B | 548 (((offset - 8) >> 2) & 0x00ffffff)); 549} 550 551static void tcg_out_bl_imm(TCGContext *s, ARMCond cond, int32_t offset) 552{ 553 tcg_out32(s, (cond << 28) | 0x0b000000 | 554 (((offset - 8) >> 2) & 0x00ffffff)); 555} 556 557static void tcg_out_blx_reg(TCGContext *s, ARMCond cond, TCGReg rn) 558{ 559 tcg_out32(s, (cond << 28) | 0x012fff30 | rn); 560} 561 562static void tcg_out_blx_imm(TCGContext *s, int32_t offset) 563{ 564 tcg_out32(s, 0xfa000000 | ((offset & 2) << 23) | 565 (((offset - 8) >> 2) & 0x00ffffff)); 566} 567 568static void tcg_out_dat_reg(TCGContext *s, ARMCond cond, ARMInsn opc, 569 TCGReg rd, TCGReg rn, TCGReg rm, int shift) 570{ 571 tcg_out32(s, (cond << 28) | (0 << 25) | opc | 572 (rn << 16) | (rd << 12) | shift | rm); 573} 574 575static void tcg_out_mov_reg(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rm) 576{ 577 /* Simple reg-reg move, optimising out the 'do nothing' case */ 578 if (rd != rm) { 579 tcg_out_dat_reg(s, cond, ARITH_MOV, rd, 0, rm, SHIFT_IMM_LSL(0)); 580 } 581} 582 583static void tcg_out_bx_reg(TCGContext *s, ARMCond cond, TCGReg rn) 584{ 585 tcg_out32(s, (cond << 28) | 0x012fff10 | rn); 586} 587 588static void tcg_out_b_reg(TCGContext *s, ARMCond cond, TCGReg rn) 589{ 590 /* 591 * Unless the C portion of QEMU is compiled as thumb, we don't need 592 * true BX semantics; merely a branch to an address held in a register. 593 */ 594 tcg_out_bx_reg(s, cond, rn); 595} 596 597static void tcg_out_dat_imm(TCGContext *s, ARMCond cond, ARMInsn opc, 598 TCGReg rd, TCGReg rn, int im) 599{ 600 tcg_out32(s, (cond << 28) | (1 << 25) | opc | 601 (rn << 16) | (rd << 12) | im); 602} 603 604static void tcg_out_ldstm(TCGContext *s, ARMCond cond, ARMInsn opc, 605 TCGReg rn, uint16_t mask) 606{ 607 tcg_out32(s, (cond << 28) | opc | (rn << 16) | mask); 608} 609 610/* Note that this routine is used for both LDR and LDRH formats, so we do 611 not wish to include an immediate shift at this point. */ 612static void tcg_out_memop_r(TCGContext *s, ARMCond cond, ARMInsn opc, TCGReg rt, 613 TCGReg rn, TCGReg rm, bool u, bool p, bool w) 614{ 615 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) 616 | (w << 21) | (rn << 16) | (rt << 12) | rm); 617} 618 619static void tcg_out_memop_8(TCGContext *s, ARMCond cond, ARMInsn opc, TCGReg rt, 620 TCGReg rn, int imm8, bool p, bool w) 621{ 622 bool u = 1; 623 if (imm8 < 0) { 624 imm8 = -imm8; 625 u = 0; 626 } 627 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | 628 (rn << 16) | (rt << 12) | ((imm8 & 0xf0) << 4) | (imm8 & 0xf)); 629} 630 631static void tcg_out_memop_12(TCGContext *s, ARMCond cond, ARMInsn opc, 632 TCGReg rt, TCGReg rn, int imm12, bool p, bool w) 633{ 634 bool u = 1; 635 if (imm12 < 0) { 636 imm12 = -imm12; 637 u = 0; 638 } 639 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | 640 (rn << 16) | (rt << 12) | imm12); 641} 642 643static void tcg_out_ld32_12(TCGContext *s, ARMCond cond, TCGReg rt, 644 TCGReg rn, int imm12) 645{ 646 tcg_out_memop_12(s, cond, INSN_LDR_IMM, rt, rn, imm12, 1, 0); 647} 648 649static void tcg_out_st32_12(TCGContext *s, ARMCond cond, TCGReg rt, 650 TCGReg rn, int imm12) 651{ 652 tcg_out_memop_12(s, cond, INSN_STR_IMM, rt, rn, imm12, 1, 0); 653} 654 655static void tcg_out_ld32_r(TCGContext *s, ARMCond cond, TCGReg rt, 656 TCGReg rn, TCGReg rm) 657{ 658 tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 0); 659} 660 661static void tcg_out_st32_r(TCGContext *s, ARMCond cond, TCGReg rt, 662 TCGReg rn, TCGReg rm) 663{ 664 tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 0); 665} 666 667static void tcg_out_ldrd_8(TCGContext *s, ARMCond cond, TCGReg rt, 668 TCGReg rn, int imm8) 669{ 670 tcg_out_memop_8(s, cond, INSN_LDRD_IMM, rt, rn, imm8, 1, 0); 671} 672 673static void tcg_out_ldrd_r(TCGContext *s, ARMCond cond, TCGReg rt, 674 TCGReg rn, TCGReg rm) 675{ 676 tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 0); 677} 678 679static void tcg_out_strd_8(TCGContext *s, ARMCond cond, TCGReg rt, 680 TCGReg rn, int imm8) 681{ 682 tcg_out_memop_8(s, cond, INSN_STRD_IMM, rt, rn, imm8, 1, 0); 683} 684 685static void tcg_out_strd_r(TCGContext *s, ARMCond cond, TCGReg rt, 686 TCGReg rn, TCGReg rm) 687{ 688 tcg_out_memop_r(s, cond, INSN_STRD_REG, rt, rn, rm, 1, 1, 0); 689} 690 691/* Register pre-increment with base writeback. */ 692static void tcg_out_ld32_rwb(TCGContext *s, ARMCond cond, TCGReg rt, 693 TCGReg rn, TCGReg rm) 694{ 695 tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 1); 696} 697 698static void tcg_out_st32_rwb(TCGContext *s, ARMCond cond, TCGReg rt, 699 TCGReg rn, TCGReg rm) 700{ 701 tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 1); 702} 703 704static void tcg_out_ld16u_8(TCGContext *s, ARMCond cond, TCGReg rt, 705 TCGReg rn, int imm8) 706{ 707 tcg_out_memop_8(s, cond, INSN_LDRH_IMM, rt, rn, imm8, 1, 0); 708} 709 710static void tcg_out_st16_8(TCGContext *s, ARMCond cond, TCGReg rt, 711 TCGReg rn, int imm8) 712{ 713 tcg_out_memop_8(s, cond, INSN_STRH_IMM, rt, rn, imm8, 1, 0); 714} 715 716static void tcg_out_ld16u_r(TCGContext *s, ARMCond cond, TCGReg rt, 717 TCGReg rn, TCGReg rm) 718{ 719 tcg_out_memop_r(s, cond, INSN_LDRH_REG, rt, rn, rm, 1, 1, 0); 720} 721 722static void tcg_out_st16_r(TCGContext *s, ARMCond cond, TCGReg rt, 723 TCGReg rn, TCGReg rm) 724{ 725 tcg_out_memop_r(s, cond, INSN_STRH_REG, rt, rn, rm, 1, 1, 0); 726} 727 728static void tcg_out_ld16s_8(TCGContext *s, ARMCond cond, TCGReg rt, 729 TCGReg rn, int imm8) 730{ 731 tcg_out_memop_8(s, cond, INSN_LDRSH_IMM, rt, rn, imm8, 1, 0); 732} 733 734static void tcg_out_ld16s_r(TCGContext *s, ARMCond cond, TCGReg rt, 735 TCGReg rn, TCGReg rm) 736{ 737 tcg_out_memop_r(s, cond, INSN_LDRSH_REG, rt, rn, rm, 1, 1, 0); 738} 739 740static void tcg_out_ld8_12(TCGContext *s, ARMCond cond, TCGReg rt, 741 TCGReg rn, int imm12) 742{ 743 tcg_out_memop_12(s, cond, INSN_LDRB_IMM, rt, rn, imm12, 1, 0); 744} 745 746static void tcg_out_st8_12(TCGContext *s, ARMCond cond, TCGReg rt, 747 TCGReg rn, int imm12) 748{ 749 tcg_out_memop_12(s, cond, INSN_STRB_IMM, rt, rn, imm12, 1, 0); 750} 751 752static void tcg_out_ld8_r(TCGContext *s, ARMCond cond, TCGReg rt, 753 TCGReg rn, TCGReg rm) 754{ 755 tcg_out_memop_r(s, cond, INSN_LDRB_REG, rt, rn, rm, 1, 1, 0); 756} 757 758static void tcg_out_st8_r(TCGContext *s, ARMCond cond, TCGReg rt, 759 TCGReg rn, TCGReg rm) 760{ 761 tcg_out_memop_r(s, cond, INSN_STRB_REG, rt, rn, rm, 1, 1, 0); 762} 763 764static void tcg_out_ld8s_8(TCGContext *s, ARMCond cond, TCGReg rt, 765 TCGReg rn, int imm8) 766{ 767 tcg_out_memop_8(s, cond, INSN_LDRSB_IMM, rt, rn, imm8, 1, 0); 768} 769 770static void tcg_out_ld8s_r(TCGContext *s, ARMCond cond, TCGReg rt, 771 TCGReg rn, TCGReg rm) 772{ 773 tcg_out_memop_r(s, cond, INSN_LDRSB_REG, rt, rn, rm, 1, 1, 0); 774} 775 776static void tcg_out_movi_pool(TCGContext *s, ARMCond cond, 777 TCGReg rd, uint32_t arg) 778{ 779 new_pool_label(s, arg, R_ARM_PC13, s->code_ptr, 0); 780 tcg_out_ld32_12(s, cond, rd, TCG_REG_PC, 0); 781} 782 783static void tcg_out_movi32(TCGContext *s, ARMCond cond, 784 TCGReg rd, uint32_t arg) 785{ 786 int imm12, diff, opc, sh1, sh2; 787 uint32_t tt0, tt1, tt2; 788 789 /* Check a single MOV/MVN before anything else. */ 790 imm12 = encode_imm(arg); 791 if (imm12 >= 0) { 792 tcg_out_dat_imm(s, cond, ARITH_MOV, rd, 0, imm12); 793 return; 794 } 795 imm12 = encode_imm(~arg); 796 if (imm12 >= 0) { 797 tcg_out_dat_imm(s, cond, ARITH_MVN, rd, 0, imm12); 798 return; 799 } 800 801 /* Check for a pc-relative address. This will usually be the TB, 802 or within the TB, which is immediately before the code block. */ 803 diff = tcg_pcrel_diff(s, (void *)arg) - 8; 804 if (diff >= 0) { 805 imm12 = encode_imm(diff); 806 if (imm12 >= 0) { 807 tcg_out_dat_imm(s, cond, ARITH_ADD, rd, TCG_REG_PC, imm12); 808 return; 809 } 810 } else { 811 imm12 = encode_imm(-diff); 812 if (imm12 >= 0) { 813 tcg_out_dat_imm(s, cond, ARITH_SUB, rd, TCG_REG_PC, imm12); 814 return; 815 } 816 } 817 818 /* Use movw + movt. */ 819 if (use_armv7_instructions) { 820 /* movw */ 821 tcg_out32(s, (cond << 28) | 0x03000000 | (rd << 12) 822 | ((arg << 4) & 0x000f0000) | (arg & 0xfff)); 823 if (arg & 0xffff0000) { 824 /* movt */ 825 tcg_out32(s, (cond << 28) | 0x03400000 | (rd << 12) 826 | ((arg >> 12) & 0x000f0000) | ((arg >> 16) & 0xfff)); 827 } 828 return; 829 } 830 831 /* Look for sequences of two insns. If we have lots of 1's, we can 832 shorten the sequence by beginning with mvn and then clearing 833 higher bits with eor. */ 834 tt0 = arg; 835 opc = ARITH_MOV; 836 if (ctpop32(arg) > 16) { 837 tt0 = ~arg; 838 opc = ARITH_MVN; 839 } 840 sh1 = ctz32(tt0) & ~1; 841 tt1 = tt0 & ~(0xff << sh1); 842 sh2 = ctz32(tt1) & ~1; 843 tt2 = tt1 & ~(0xff << sh2); 844 if (tt2 == 0) { 845 int rot; 846 847 rot = ((32 - sh1) << 7) & 0xf00; 848 tcg_out_dat_imm(s, cond, opc, rd, 0, ((tt0 >> sh1) & 0xff) | rot); 849 rot = ((32 - sh2) << 7) & 0xf00; 850 tcg_out_dat_imm(s, cond, ARITH_EOR, rd, rd, 851 ((tt0 >> sh2) & 0xff) | rot); 852 return; 853 } 854 855 /* Otherwise, drop it into the constant pool. */ 856 tcg_out_movi_pool(s, cond, rd, arg); 857} 858 859/* 860 * Emit either the reg,imm or reg,reg form of a data-processing insn. 861 * rhs must satisfy the "rI" constraint. 862 */ 863static void tcg_out_dat_rI(TCGContext *s, ARMCond cond, ARMInsn opc, 864 TCGReg dst, TCGReg lhs, TCGArg rhs, int rhs_is_const) 865{ 866 if (rhs_is_const) { 867 tcg_out_dat_imm(s, cond, opc, dst, lhs, encode_imm_nofail(rhs)); 868 } else { 869 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); 870 } 871} 872 873/* 874 * Emit either the reg,imm or reg,reg form of a data-processing insn. 875 * rhs must satisfy the "rIK" constraint. 876 */ 877static void tcg_out_dat_IK(TCGContext *s, ARMCond cond, ARMInsn opc, 878 ARMInsn opinv, TCGReg dst, TCGReg lhs, TCGArg rhs) 879{ 880 int imm12 = encode_imm(rhs); 881 if (imm12 < 0) { 882 imm12 = encode_imm_nofail(~rhs); 883 opc = opinv; 884 } 885 tcg_out_dat_imm(s, cond, opc, dst, lhs, imm12); 886} 887 888static void tcg_out_dat_rIK(TCGContext *s, ARMCond cond, ARMInsn opc, 889 ARMInsn opinv, TCGReg dst, TCGReg lhs, TCGArg rhs, 890 bool rhs_is_const) 891{ 892 if (rhs_is_const) { 893 tcg_out_dat_IK(s, cond, opc, opinv, dst, lhs, rhs); 894 } else { 895 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); 896 } 897} 898 899static void tcg_out_dat_IN(TCGContext *s, ARMCond cond, ARMInsn opc, 900 ARMInsn opneg, TCGReg dst, TCGReg lhs, TCGArg rhs) 901{ 902 int imm12 = encode_imm(rhs); 903 if (imm12 < 0) { 904 imm12 = encode_imm_nofail(-rhs); 905 opc = opneg; 906 } 907 tcg_out_dat_imm(s, cond, opc, dst, lhs, imm12); 908} 909 910static void tcg_out_dat_rIN(TCGContext *s, ARMCond cond, ARMInsn opc, 911 ARMInsn opneg, TCGReg dst, TCGReg lhs, TCGArg rhs, 912 bool rhs_is_const) 913{ 914 /* Emit either the reg,imm or reg,reg form of a data-processing insn. 915 * rhs must satisfy the "rIN" constraint. 916 */ 917 if (rhs_is_const) { 918 tcg_out_dat_IN(s, cond, opc, opneg, dst, lhs, rhs); 919 } else { 920 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); 921 } 922} 923 924static void tcg_out_ext8s(TCGContext *s, TCGType t, TCGReg rd, TCGReg rn) 925{ 926 /* sxtb */ 927 tcg_out32(s, 0x06af0070 | (COND_AL << 28) | (rd << 12) | rn); 928} 929 930static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rn) 931{ 932 tcg_out_dat_imm(s, COND_AL, ARITH_AND, rd, rn, 0xff); 933} 934 935static void tcg_out_ext16s(TCGContext *s, TCGType t, TCGReg rd, TCGReg rn) 936{ 937 /* sxth */ 938 tcg_out32(s, 0x06bf0070 | (COND_AL << 28) | (rd << 12) | rn); 939} 940 941static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rn) 942{ 943 /* uxth */ 944 tcg_out32(s, 0x06ff0070 | (COND_AL << 28) | (rd << 12) | rn); 945} 946 947static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rn) 948{ 949 g_assert_not_reached(); 950} 951 952static void tcg_out_ext32u(TCGContext *s, TCGReg rd, TCGReg rn) 953{ 954 g_assert_not_reached(); 955} 956 957static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rn) 958{ 959 g_assert_not_reached(); 960} 961 962static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rn) 963{ 964 g_assert_not_reached(); 965} 966 967static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rn) 968{ 969 g_assert_not_reached(); 970} 971 972static void tcg_out_deposit(TCGContext *s, ARMCond cond, TCGReg rd, 973 TCGArg a1, int ofs, int len, bool const_a1) 974{ 975 if (const_a1) { 976 /* bfi becomes bfc with rn == 15. */ 977 a1 = 15; 978 } 979 /* bfi/bfc */ 980 tcg_out32(s, 0x07c00010 | (cond << 28) | (rd << 12) | a1 981 | (ofs << 7) | ((ofs + len - 1) << 16)); 982} 983 984static void tgen_extract(TCGContext *s, TCGType type, TCGReg rd, TCGReg rn, 985 unsigned ofs, unsigned len) 986{ 987 /* According to gcc, AND can be faster. */ 988 if (ofs == 0 && len <= 8) { 989 tcg_out_dat_imm(s, COND_AL, ARITH_AND, rd, rn, 990 encode_imm_nofail((1 << len) - 1)); 991 return; 992 } 993 994 if (use_armv7_instructions) { 995 /* ubfx */ 996 tcg_out32(s, 0x07e00050 | (COND_AL << 28) | (rd << 12) | rn 997 | (ofs << 7) | ((len - 1) << 16)); 998 return; 999 } 1000 1001 assert(ofs % 8 == 0); 1002 switch (len) { 1003 case 8: 1004 /* uxtb */ 1005 tcg_out32(s, 0x06ef0070 | (COND_AL << 28) | 1006 (rd << 12) | (ofs << 7) | rn); 1007 break; 1008 case 16: 1009 /* uxth */ 1010 tcg_out32(s, 0x06ff0070 | (COND_AL << 28) | 1011 (rd << 12) | (ofs << 7) | rn); 1012 break; 1013 default: 1014 g_assert_not_reached(); 1015 } 1016} 1017 1018static const TCGOutOpExtract outop_extract = { 1019 .base.static_constraint = C_O1_I1(r, r), 1020 .out_rr = tgen_extract, 1021}; 1022 1023static void tgen_sextract(TCGContext *s, TCGType type, TCGReg rd, TCGReg rn, 1024 unsigned ofs, unsigned len) 1025{ 1026 if (use_armv7_instructions) { 1027 /* sbfx */ 1028 tcg_out32(s, 0x07a00050 | (COND_AL << 28) | (rd << 12) | rn 1029 | (ofs << 7) | ((len - 1) << 16)); 1030 return; 1031 } 1032 1033 assert(ofs % 8 == 0); 1034 switch (len) { 1035 case 8: 1036 /* sxtb */ 1037 tcg_out32(s, 0x06af0070 | (COND_AL << 28) | 1038 (rd << 12) | (ofs << 7) | rn); 1039 break; 1040 case 16: 1041 /* sxth */ 1042 tcg_out32(s, 0x06bf0070 | (COND_AL << 28) | 1043 (rd << 12) | (ofs << 7) | rn); 1044 break; 1045 default: 1046 g_assert_not_reached(); 1047 } 1048} 1049 1050static const TCGOutOpExtract outop_sextract = { 1051 .base.static_constraint = C_O1_I1(r, r), 1052 .out_rr = tgen_sextract, 1053}; 1054 1055 1056static void tcg_out_ld32u(TCGContext *s, ARMCond cond, 1057 TCGReg rd, TCGReg rn, int32_t offset) 1058{ 1059 if (offset > 0xfff || offset < -0xfff) { 1060 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1061 tcg_out_ld32_r(s, cond, rd, rn, TCG_REG_TMP); 1062 } else 1063 tcg_out_ld32_12(s, cond, rd, rn, offset); 1064} 1065 1066static void tcg_out_st32(TCGContext *s, ARMCond cond, 1067 TCGReg rd, TCGReg rn, int32_t offset) 1068{ 1069 if (offset > 0xfff || offset < -0xfff) { 1070 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1071 tcg_out_st32_r(s, cond, rd, rn, TCG_REG_TMP); 1072 } else 1073 tcg_out_st32_12(s, cond, rd, rn, offset); 1074} 1075 1076static void tcg_out_ld16u(TCGContext *s, ARMCond cond, 1077 TCGReg rd, TCGReg rn, int32_t offset) 1078{ 1079 if (offset > 0xff || offset < -0xff) { 1080 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1081 tcg_out_ld16u_r(s, cond, rd, rn, TCG_REG_TMP); 1082 } else 1083 tcg_out_ld16u_8(s, cond, rd, rn, offset); 1084} 1085 1086static void tcg_out_ld16s(TCGContext *s, ARMCond cond, 1087 TCGReg rd, TCGReg rn, int32_t offset) 1088{ 1089 if (offset > 0xff || offset < -0xff) { 1090 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1091 tcg_out_ld16s_r(s, cond, rd, rn, TCG_REG_TMP); 1092 } else 1093 tcg_out_ld16s_8(s, cond, rd, rn, offset); 1094} 1095 1096static void tcg_out_st16(TCGContext *s, ARMCond cond, 1097 TCGReg rd, TCGReg rn, int32_t offset) 1098{ 1099 if (offset > 0xff || offset < -0xff) { 1100 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1101 tcg_out_st16_r(s, cond, rd, rn, TCG_REG_TMP); 1102 } else 1103 tcg_out_st16_8(s, cond, rd, rn, offset); 1104} 1105 1106static void tcg_out_ld8u(TCGContext *s, ARMCond cond, 1107 TCGReg rd, TCGReg rn, int32_t offset) 1108{ 1109 if (offset > 0xfff || offset < -0xfff) { 1110 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1111 tcg_out_ld8_r(s, cond, rd, rn, TCG_REG_TMP); 1112 } else 1113 tcg_out_ld8_12(s, cond, rd, rn, offset); 1114} 1115 1116static void tcg_out_ld8s(TCGContext *s, ARMCond cond, 1117 TCGReg rd, TCGReg rn, int32_t offset) 1118{ 1119 if (offset > 0xff || offset < -0xff) { 1120 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1121 tcg_out_ld8s_r(s, cond, rd, rn, TCG_REG_TMP); 1122 } else 1123 tcg_out_ld8s_8(s, cond, rd, rn, offset); 1124} 1125 1126static void tcg_out_st8(TCGContext *s, ARMCond cond, 1127 TCGReg rd, TCGReg rn, int32_t offset) 1128{ 1129 if (offset > 0xfff || offset < -0xfff) { 1130 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1131 tcg_out_st8_r(s, cond, rd, rn, TCG_REG_TMP); 1132 } else 1133 tcg_out_st8_12(s, cond, rd, rn, offset); 1134} 1135 1136/* 1137 * The _goto case is normally between TBs within the same code buffer, and 1138 * with the code buffer limited to 16MB we wouldn't need the long case. 1139 * But we also use it for the tail-call to the qemu_ld/st helpers, which does. 1140 */ 1141static void tcg_out_goto(TCGContext *s, ARMCond cond, const tcg_insn_unit *addr) 1142{ 1143 intptr_t addri = (intptr_t)addr; 1144 ptrdiff_t disp = tcg_pcrel_diff(s, addr); 1145 bool arm_mode = !(addri & 1); 1146 1147 if (arm_mode && disp - 8 < 0x01fffffd && disp - 8 > -0x01fffffd) { 1148 tcg_out_b_imm(s, cond, disp); 1149 return; 1150 } 1151 1152 /* LDR is interworking from v5t. */ 1153 tcg_out_movi_pool(s, cond, TCG_REG_PC, addri); 1154} 1155 1156/* 1157 * The call case is mostly used for helpers - so it's not unreasonable 1158 * for them to be beyond branch range. 1159 */ 1160static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *addr) 1161{ 1162 intptr_t addri = (intptr_t)addr; 1163 ptrdiff_t disp = tcg_pcrel_diff(s, addr); 1164 bool arm_mode = !(addri & 1); 1165 1166 if (disp - 8 < 0x02000000 && disp - 8 >= -0x02000000) { 1167 if (arm_mode) { 1168 tcg_out_bl_imm(s, COND_AL, disp); 1169 } else { 1170 tcg_out_blx_imm(s, disp); 1171 } 1172 return; 1173 } 1174 1175 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri); 1176 tcg_out_blx_reg(s, COND_AL, TCG_REG_TMP); 1177} 1178 1179static void tcg_out_call(TCGContext *s, const tcg_insn_unit *addr, 1180 const TCGHelperInfo *info) 1181{ 1182 tcg_out_call_int(s, addr); 1183} 1184 1185static void tcg_out_goto_label(TCGContext *s, ARMCond cond, TCGLabel *l) 1186{ 1187 if (l->has_value) { 1188 tcg_out_goto(s, cond, l->u.value_ptr); 1189 } else { 1190 tcg_out_reloc(s, s->code_ptr, R_ARM_PC24, l, 0); 1191 tcg_out_b_imm(s, cond, 0); 1192 } 1193} 1194 1195static void tcg_out_mb(TCGContext *s, TCGArg a0) 1196{ 1197 if (use_armv7_instructions) { 1198 tcg_out32(s, INSN_DMB_ISH); 1199 } else { 1200 tcg_out32(s, INSN_DMB_MCR); 1201 } 1202} 1203 1204static TCGCond tgen_cmp(TCGContext *s, TCGCond cond, TCGReg a, TCGReg b) 1205{ 1206 if (is_tst_cond(cond)) { 1207 tcg_out_dat_reg(s, COND_AL, ARITH_TST, 0, a, b, SHIFT_IMM_LSL(0)); 1208 return tcg_tst_eqne_cond(cond); 1209 } 1210 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, a, b, SHIFT_IMM_LSL(0)); 1211 return cond; 1212} 1213 1214static TCGCond tgen_cmpi(TCGContext *s, TCGCond cond, TCGReg a, TCGArg b) 1215{ 1216 int imm12; 1217 1218 if (!is_tst_cond(cond)) { 1219 tcg_out_dat_IN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, a, b); 1220 return cond; 1221 } 1222 1223 /* 1224 * The compare constraints allow rIN, but TST does not support N. 1225 * Be prepared to load the constant into a scratch register. 1226 */ 1227 imm12 = encode_imm(b); 1228 if (imm12 >= 0) { 1229 tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, a, imm12); 1230 } else { 1231 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, b); 1232 tcg_out_dat_reg(s, COND_AL, ARITH_TST, 0, 1233 a, TCG_REG_TMP, SHIFT_IMM_LSL(0)); 1234 } 1235 return tcg_tst_eqne_cond(cond); 1236} 1237 1238static TCGCond tcg_out_cmp(TCGContext *s, TCGCond cond, TCGReg a, 1239 TCGArg b, int b_const) 1240{ 1241 if (b_const) { 1242 return tgen_cmpi(s, cond, a, b); 1243 } else { 1244 return tgen_cmp(s, cond, a, b); 1245 } 1246} 1247 1248static TCGCond tcg_out_cmp2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, 1249 TCGArg bl, bool const_bl, TCGArg bh, bool const_bh) 1250{ 1251 switch (cond) { 1252 case TCG_COND_EQ: 1253 case TCG_COND_NE: 1254 case TCG_COND_LTU: 1255 case TCG_COND_LEU: 1256 case TCG_COND_GTU: 1257 case TCG_COND_GEU: 1258 /* 1259 * We perform a conditional comparison. If the high half is 1260 * equal, then overwrite the flags with the comparison of the 1261 * low half. The resulting flags cover the whole. 1262 */ 1263 tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, ah, bh, const_bh); 1264 tcg_out_dat_rI(s, COND_EQ, ARITH_CMP, 0, al, bl, const_bl); 1265 return cond; 1266 1267 case TCG_COND_TSTEQ: 1268 case TCG_COND_TSTNE: 1269 /* Similar, but with TST instead of CMP. */ 1270 tcg_out_dat_rI(s, COND_AL, ARITH_TST, 0, ah, bh, const_bh); 1271 tcg_out_dat_rI(s, COND_EQ, ARITH_TST, 0, al, bl, const_bl); 1272 return tcg_tst_eqne_cond(cond); 1273 1274 case TCG_COND_LT: 1275 case TCG_COND_GE: 1276 /* We perform a double-word subtraction and examine the result. 1277 We do not actually need the result of the subtract, so the 1278 low part "subtract" is a compare. For the high half we have 1279 no choice but to compute into a temporary. */ 1280 tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, al, bl, const_bl); 1281 tcg_out_dat_rI(s, COND_AL, ARITH_SBC | TO_CPSR, 1282 TCG_REG_TMP, ah, bh, const_bh); 1283 return cond; 1284 1285 case TCG_COND_LE: 1286 case TCG_COND_GT: 1287 /* Similar, but with swapped arguments, via reversed subtract. */ 1288 tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR, 1289 TCG_REG_TMP, al, bl, const_bl); 1290 tcg_out_dat_rI(s, COND_AL, ARITH_RSC | TO_CPSR, 1291 TCG_REG_TMP, ah, bh, const_bh); 1292 return tcg_swap_cond(cond); 1293 1294 default: 1295 g_assert_not_reached(); 1296 } 1297} 1298 1299/* 1300 * Note that TCGReg references Q-registers. 1301 * Q-regno = 2 * D-regno, so shift left by 1 while inserting. 1302 */ 1303static uint32_t encode_vd(TCGReg rd) 1304{ 1305 tcg_debug_assert(rd >= TCG_REG_Q0); 1306 return (extract32(rd, 3, 1) << 22) | (extract32(rd, 0, 3) << 13); 1307} 1308 1309static uint32_t encode_vn(TCGReg rn) 1310{ 1311 tcg_debug_assert(rn >= TCG_REG_Q0); 1312 return (extract32(rn, 3, 1) << 7) | (extract32(rn, 0, 3) << 17); 1313} 1314 1315static uint32_t encode_vm(TCGReg rm) 1316{ 1317 tcg_debug_assert(rm >= TCG_REG_Q0); 1318 return (extract32(rm, 3, 1) << 5) | (extract32(rm, 0, 3) << 1); 1319} 1320 1321static void tcg_out_vreg2(TCGContext *s, ARMInsn insn, int q, int vece, 1322 TCGReg d, TCGReg m) 1323{ 1324 tcg_out32(s, insn | (vece << 18) | (q << 6) | 1325 encode_vd(d) | encode_vm(m)); 1326} 1327 1328static void tcg_out_vreg3(TCGContext *s, ARMInsn insn, int q, int vece, 1329 TCGReg d, TCGReg n, TCGReg m) 1330{ 1331 tcg_out32(s, insn | (vece << 20) | (q << 6) | 1332 encode_vd(d) | encode_vn(n) | encode_vm(m)); 1333} 1334 1335static void tcg_out_vmovi(TCGContext *s, TCGReg rd, 1336 int q, int op, int cmode, uint8_t imm8) 1337{ 1338 tcg_out32(s, INSN_VMOVI | encode_vd(rd) | (q << 6) | (op << 5) 1339 | (cmode << 8) | extract32(imm8, 0, 4) 1340 | (extract32(imm8, 4, 3) << 16) 1341 | (extract32(imm8, 7, 1) << 24)); 1342} 1343 1344static void tcg_out_vshifti(TCGContext *s, ARMInsn insn, int q, 1345 TCGReg rd, TCGReg rm, int l_imm6) 1346{ 1347 tcg_out32(s, insn | (q << 6) | encode_vd(rd) | encode_vm(rm) | 1348 (extract32(l_imm6, 6, 1) << 7) | 1349 (extract32(l_imm6, 0, 6) << 16)); 1350} 1351 1352static void tcg_out_vldst(TCGContext *s, ARMInsn insn, 1353 TCGReg rd, TCGReg rn, int offset) 1354{ 1355 if (offset != 0) { 1356 if (check_fit_imm(offset) || check_fit_imm(-offset)) { 1357 tcg_out_dat_rIN(s, COND_AL, ARITH_ADD, ARITH_SUB, 1358 TCG_REG_TMP, rn, offset, true); 1359 } else { 1360 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, offset); 1361 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, 1362 TCG_REG_TMP, TCG_REG_TMP, rn, 0); 1363 } 1364 rn = TCG_REG_TMP; 1365 } 1366 tcg_out32(s, insn | (rn << 16) | encode_vd(rd) | 0xf); 1367} 1368 1369typedef struct { 1370 ARMCond cond; 1371 TCGReg base; 1372 int index; 1373 bool index_scratch; 1374 TCGAtomAlign aa; 1375} HostAddress; 1376 1377bool tcg_target_has_memory_bswap(MemOp memop) 1378{ 1379 return false; 1380} 1381 1382static TCGReg ldst_ra_gen(TCGContext *s, const TCGLabelQemuLdst *l, int arg) 1383{ 1384 /* We arrive at the slow path via "BLNE", so R14 contains l->raddr. */ 1385 return TCG_REG_R14; 1386} 1387 1388static const TCGLdstHelperParam ldst_helper_param = { 1389 .ra_gen = ldst_ra_gen, 1390 .ntmp = 1, 1391 .tmp = { TCG_REG_TMP }, 1392}; 1393 1394static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1395{ 1396 MemOp opc = get_memop(lb->oi); 1397 1398 if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1399 return false; 1400 } 1401 1402 tcg_out_ld_helper_args(s, lb, &ldst_helper_param); 1403 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE]); 1404 tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param); 1405 1406 tcg_out_goto(s, COND_AL, lb->raddr); 1407 return true; 1408} 1409 1410static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1411{ 1412 MemOp opc = get_memop(lb->oi); 1413 1414 if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1415 return false; 1416 } 1417 1418 tcg_out_st_helper_args(s, lb, &ldst_helper_param); 1419 1420 /* Tail-call to the helper, which will return to the fast path. */ 1421 tcg_out_goto(s, COND_AL, qemu_st_helpers[opc & MO_SIZE]); 1422 return true; 1423} 1424 1425/* We expect to use an 9-bit sign-magnitude negative offset from ENV. */ 1426#define MIN_TLB_MASK_TABLE_OFS -256 1427 1428static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1429 TCGReg addr, MemOpIdx oi, bool is_ld) 1430{ 1431 TCGLabelQemuLdst *ldst = NULL; 1432 MemOp opc = get_memop(oi); 1433 unsigned a_mask; 1434 1435 if (tcg_use_softmmu) { 1436 *h = (HostAddress){ 1437 .cond = COND_AL, 1438 .base = addr, 1439 .index = TCG_REG_R1, 1440 .index_scratch = true, 1441 }; 1442 } else { 1443 *h = (HostAddress){ 1444 .cond = COND_AL, 1445 .base = addr, 1446 .index = guest_base ? TCG_REG_GUEST_BASE : -1, 1447 .index_scratch = false, 1448 }; 1449 } 1450 1451 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); 1452 a_mask = (1 << h->aa.align) - 1; 1453 1454 if (tcg_use_softmmu) { 1455 int mem_index = get_mmuidx(oi); 1456 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read) 1457 : offsetof(CPUTLBEntry, addr_write); 1458 int fast_off = tlb_mask_table_ofs(s, mem_index); 1459 unsigned s_mask = (1 << (opc & MO_SIZE)) - 1; 1460 TCGReg t_addr; 1461 1462 ldst = new_ldst_label(s); 1463 ldst->is_ld = is_ld; 1464 ldst->oi = oi; 1465 ldst->addr_reg = addr; 1466 1467 /* Load cpu->neg.tlb.f[mmu_idx].{mask,table} into {r0,r1}. */ 1468 QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0); 1469 QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != 4); 1470 tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off); 1471 1472 /* Extract the tlb index from the address into R0. */ 1473 tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, addr, 1474 SHIFT_IMM_LSR(s->page_bits - CPU_TLB_ENTRY_BITS)); 1475 1476 /* 1477 * Add the tlb_table pointer, creating the CPUTLBEntry address in R1. 1478 * Load the tlb comparator into R2 and the fast path addend into R1. 1479 */ 1480 if (cmp_off == 0) { 1481 tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0); 1482 } else { 1483 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, 1484 TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0); 1485 tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); 1486 } 1487 1488 /* Load the tlb addend. */ 1489 tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R1, 1490 offsetof(CPUTLBEntry, addend)); 1491 1492 /* 1493 * Check alignment, check comparators. 1494 * Do this in 2-4 insns. Use MOVW for v7, if possible, 1495 * to reduce the number of sequential conditional instructions. 1496 * Almost all guests have at least 4k pages, which means that we need 1497 * to clear at least 9 bits even for an 8-byte memory, which means it 1498 * isn't worth checking for an immediate operand for BIC. 1499 * 1500 * For unaligned accesses, test the page of the last unit of alignment. 1501 * This leaves the least significant alignment bits unchanged, and of 1502 * course must be zero. 1503 */ 1504 t_addr = addr; 1505 if (a_mask < s_mask) { 1506 t_addr = TCG_REG_R0; 1507 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, t_addr, 1508 addr, s_mask - a_mask); 1509 } 1510 if (use_armv7_instructions && s->page_bits <= 16) { 1511 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, ~(s->page_mask | a_mask)); 1512 tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP, 1513 t_addr, TCG_REG_TMP, 0); 1514 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, 1515 TCG_REG_R2, TCG_REG_TMP, 0); 1516 } else { 1517 if (a_mask) { 1518 tcg_debug_assert(a_mask <= 0xff); 1519 tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addr, a_mask); 1520 } 1521 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, t_addr, 1522 SHIFT_IMM_LSR(s->page_bits)); 1523 tcg_out_dat_reg(s, (a_mask ? COND_EQ : COND_AL), ARITH_CMP, 1524 0, TCG_REG_R2, TCG_REG_TMP, 1525 SHIFT_IMM_LSL(s->page_bits)); 1526 } 1527 } else if (a_mask) { 1528 ldst = new_ldst_label(s); 1529 ldst->is_ld = is_ld; 1530 ldst->oi = oi; 1531 ldst->addr_reg = addr; 1532 1533 /* We are expecting alignment to max out at 7 */ 1534 tcg_debug_assert(a_mask <= 0xff); 1535 /* tst addr, #mask */ 1536 tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addr, a_mask); 1537 } 1538 1539 return ldst; 1540} 1541 1542static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo, 1543 TCGReg datahi, HostAddress h) 1544{ 1545 TCGReg base; 1546 1547 /* Byte swapping is left to middle-end expansion. */ 1548 tcg_debug_assert((opc & MO_BSWAP) == 0); 1549 1550 switch (opc & MO_SSIZE) { 1551 case MO_UB: 1552 if (h.index < 0) { 1553 tcg_out_ld8_12(s, h.cond, datalo, h.base, 0); 1554 } else { 1555 tcg_out_ld8_r(s, h.cond, datalo, h.base, h.index); 1556 } 1557 break; 1558 case MO_SB: 1559 if (h.index < 0) { 1560 tcg_out_ld8s_8(s, h.cond, datalo, h.base, 0); 1561 } else { 1562 tcg_out_ld8s_r(s, h.cond, datalo, h.base, h.index); 1563 } 1564 break; 1565 case MO_UW: 1566 if (h.index < 0) { 1567 tcg_out_ld16u_8(s, h.cond, datalo, h.base, 0); 1568 } else { 1569 tcg_out_ld16u_r(s, h.cond, datalo, h.base, h.index); 1570 } 1571 break; 1572 case MO_SW: 1573 if (h.index < 0) { 1574 tcg_out_ld16s_8(s, h.cond, datalo, h.base, 0); 1575 } else { 1576 tcg_out_ld16s_r(s, h.cond, datalo, h.base, h.index); 1577 } 1578 break; 1579 case MO_UL: 1580 if (h.index < 0) { 1581 tcg_out_ld32_12(s, h.cond, datalo, h.base, 0); 1582 } else { 1583 tcg_out_ld32_r(s, h.cond, datalo, h.base, h.index); 1584 } 1585 break; 1586 case MO_UQ: 1587 /* We used pair allocation for datalo, so already should be aligned. */ 1588 tcg_debug_assert((datalo & 1) == 0); 1589 tcg_debug_assert(datahi == datalo + 1); 1590 /* LDRD requires alignment; double-check that. */ 1591 if (memop_alignment_bits(opc) >= MO_64) { 1592 if (h.index < 0) { 1593 tcg_out_ldrd_8(s, h.cond, datalo, h.base, 0); 1594 break; 1595 } 1596 /* 1597 * Rm (the second address op) must not overlap Rt or Rt + 1. 1598 * Since datalo is aligned, we can simplify the test via alignment. 1599 * Flip the two address arguments if that works. 1600 */ 1601 if ((h.index & ~1) != datalo) { 1602 tcg_out_ldrd_r(s, h.cond, datalo, h.base, h.index); 1603 break; 1604 } 1605 if ((h.base & ~1) != datalo) { 1606 tcg_out_ldrd_r(s, h.cond, datalo, h.index, h.base); 1607 break; 1608 } 1609 } 1610 if (h.index < 0) { 1611 base = h.base; 1612 if (datalo == h.base) { 1613 tcg_out_mov_reg(s, h.cond, TCG_REG_TMP, base); 1614 base = TCG_REG_TMP; 1615 } 1616 } else if (h.index_scratch) { 1617 tcg_out_ld32_rwb(s, h.cond, datalo, h.index, h.base); 1618 tcg_out_ld32_12(s, h.cond, datahi, h.index, 4); 1619 break; 1620 } else { 1621 tcg_out_dat_reg(s, h.cond, ARITH_ADD, TCG_REG_TMP, 1622 h.base, h.index, SHIFT_IMM_LSL(0)); 1623 base = TCG_REG_TMP; 1624 } 1625 tcg_out_ld32_12(s, h.cond, datalo, base, 0); 1626 tcg_out_ld32_12(s, h.cond, datahi, base, 4); 1627 break; 1628 default: 1629 g_assert_not_reached(); 1630 } 1631} 1632 1633static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, 1634 TCGReg addr, MemOpIdx oi, TCGType data_type) 1635{ 1636 MemOp opc = get_memop(oi); 1637 TCGLabelQemuLdst *ldst; 1638 HostAddress h; 1639 1640 ldst = prepare_host_addr(s, &h, addr, oi, true); 1641 if (ldst) { 1642 ldst->type = data_type; 1643 ldst->datalo_reg = datalo; 1644 ldst->datahi_reg = datahi; 1645 1646 /* 1647 * This a conditional BL only to load a pointer within this 1648 * opcode into LR for the slow path. We will not be using 1649 * the value for a tail call. 1650 */ 1651 ldst->label_ptr[0] = s->code_ptr; 1652 tcg_out_bl_imm(s, COND_NE, 0); 1653 1654 tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); 1655 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1656 } else { 1657 tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); 1658 } 1659} 1660 1661static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo, 1662 TCGReg datahi, HostAddress h) 1663{ 1664 /* Byte swapping is left to middle-end expansion. */ 1665 tcg_debug_assert((opc & MO_BSWAP) == 0); 1666 1667 switch (opc & MO_SIZE) { 1668 case MO_8: 1669 if (h.index < 0) { 1670 tcg_out_st8_12(s, h.cond, datalo, h.base, 0); 1671 } else { 1672 tcg_out_st8_r(s, h.cond, datalo, h.base, h.index); 1673 } 1674 break; 1675 case MO_16: 1676 if (h.index < 0) { 1677 tcg_out_st16_8(s, h.cond, datalo, h.base, 0); 1678 } else { 1679 tcg_out_st16_r(s, h.cond, datalo, h.base, h.index); 1680 } 1681 break; 1682 case MO_32: 1683 if (h.index < 0) { 1684 tcg_out_st32_12(s, h.cond, datalo, h.base, 0); 1685 } else { 1686 tcg_out_st32_r(s, h.cond, datalo, h.base, h.index); 1687 } 1688 break; 1689 case MO_64: 1690 /* We used pair allocation for datalo, so already should be aligned. */ 1691 tcg_debug_assert((datalo & 1) == 0); 1692 tcg_debug_assert(datahi == datalo + 1); 1693 /* STRD requires alignment; double-check that. */ 1694 if (memop_alignment_bits(opc) >= MO_64) { 1695 if (h.index < 0) { 1696 tcg_out_strd_8(s, h.cond, datalo, h.base, 0); 1697 } else { 1698 tcg_out_strd_r(s, h.cond, datalo, h.base, h.index); 1699 } 1700 } else if (h.index < 0) { 1701 tcg_out_st32_12(s, h.cond, datalo, h.base, 0); 1702 tcg_out_st32_12(s, h.cond, datahi, h.base, 4); 1703 } else if (h.index_scratch) { 1704 tcg_out_st32_rwb(s, h.cond, datalo, h.index, h.base); 1705 tcg_out_st32_12(s, h.cond, datahi, h.index, 4); 1706 } else { 1707 tcg_out_dat_reg(s, h.cond, ARITH_ADD, TCG_REG_TMP, 1708 h.base, h.index, SHIFT_IMM_LSL(0)); 1709 tcg_out_st32_12(s, h.cond, datalo, TCG_REG_TMP, 0); 1710 tcg_out_st32_12(s, h.cond, datahi, TCG_REG_TMP, 4); 1711 } 1712 break; 1713 default: 1714 g_assert_not_reached(); 1715 } 1716} 1717 1718static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, 1719 TCGReg addr, MemOpIdx oi, TCGType data_type) 1720{ 1721 MemOp opc = get_memop(oi); 1722 TCGLabelQemuLdst *ldst; 1723 HostAddress h; 1724 1725 ldst = prepare_host_addr(s, &h, addr, oi, false); 1726 if (ldst) { 1727 ldst->type = data_type; 1728 ldst->datalo_reg = datalo; 1729 ldst->datahi_reg = datahi; 1730 1731 h.cond = COND_EQ; 1732 tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); 1733 1734 /* The conditional call is last, as we're going to return here. */ 1735 ldst->label_ptr[0] = s->code_ptr; 1736 tcg_out_bl_imm(s, COND_NE, 0); 1737 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1738 } else { 1739 tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); 1740 } 1741} 1742 1743static void tcg_out_epilogue(TCGContext *s); 1744 1745static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg) 1746{ 1747 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, arg); 1748 tcg_out_epilogue(s); 1749} 1750 1751static void tcg_out_goto_tb(TCGContext *s, int which) 1752{ 1753 uintptr_t i_addr; 1754 intptr_t i_disp; 1755 1756 /* Direct branch will be patched by tb_target_set_jmp_target. */ 1757 set_jmp_insn_offset(s, which); 1758 tcg_out32(s, INSN_NOP); 1759 1760 /* When branch is out of range, fall through to indirect. */ 1761 i_addr = get_jmp_target_addr(s, which); 1762 i_disp = tcg_pcrel_diff(s, (void *)i_addr) - 8; 1763 tcg_debug_assert(i_disp < 0); 1764 if (i_disp >= -0xfff) { 1765 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, i_disp); 1766 } else { 1767 /* 1768 * The TB is close, but outside the 12 bits addressable by 1769 * the load. We can extend this to 20 bits with a sub of a 1770 * shifted immediate from pc. 1771 */ 1772 int h = -i_disp; 1773 int l = -(h & 0xfff); 1774 1775 h = encode_imm_nofail(h + l); 1776 tcg_out_dat_imm(s, COND_AL, ARITH_SUB, TCG_REG_R0, TCG_REG_PC, h); 1777 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_R0, l); 1778 } 1779 set_jmp_reset_offset(s, which); 1780} 1781 1782void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1783 uintptr_t jmp_rx, uintptr_t jmp_rw) 1784{ 1785 uintptr_t addr = tb->jmp_target_addr[n]; 1786 ptrdiff_t offset = addr - (jmp_rx + 8); 1787 tcg_insn_unit insn; 1788 1789 /* Either directly branch, or fall through to indirect branch. */ 1790 if (offset == sextract64(offset, 0, 26)) { 1791 /* B <addr> */ 1792 insn = deposit32((COND_AL << 28) | INSN_B, 0, 24, offset >> 2); 1793 } else { 1794 insn = INSN_NOP; 1795 } 1796 1797 qatomic_set((uint32_t *)jmp_rw, insn); 1798 flush_idcache_range(jmp_rx, jmp_rw, 4); 1799} 1800 1801 1802static void tgen_add(TCGContext *s, TCGType type, 1803 TCGReg a0, TCGReg a1, TCGReg a2) 1804{ 1805 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, a0, a1, a2, SHIFT_IMM_LSL(0)); 1806} 1807 1808static void tgen_addi(TCGContext *s, TCGType type, 1809 TCGReg a0, TCGReg a1, tcg_target_long a2) 1810{ 1811 tcg_out_dat_IN(s, COND_AL, ARITH_ADD, ARITH_SUB, a0, a1, a2); 1812} 1813 1814static const TCGOutOpBinary outop_add = { 1815 .base.static_constraint = C_O1_I2(r, r, rIN), 1816 .out_rrr = tgen_add, 1817 .out_rri = tgen_addi, 1818}; 1819 1820static void tgen_and(TCGContext *s, TCGType type, 1821 TCGReg a0, TCGReg a1, TCGReg a2) 1822{ 1823 tcg_out_dat_reg(s, COND_AL, ARITH_AND, a0, a1, a2, SHIFT_IMM_LSL(0)); 1824} 1825 1826static void tgen_andi(TCGContext *s, TCGType type, 1827 TCGReg a0, TCGReg a1, tcg_target_long a2) 1828{ 1829 tcg_out_dat_IK(s, COND_AL, ARITH_AND, ARITH_BIC, a0, a1, a2); 1830} 1831 1832static const TCGOutOpBinary outop_and = { 1833 .base.static_constraint = C_O1_I2(r, r, rIK), 1834 .out_rrr = tgen_and, 1835 .out_rri = tgen_andi, 1836}; 1837 1838static void tgen_andc(TCGContext *s, TCGType type, 1839 TCGReg a0, TCGReg a1, TCGReg a2) 1840{ 1841 tcg_out_dat_reg(s, COND_AL, ARITH_BIC, a0, a1, a2, SHIFT_IMM_LSL(0)); 1842} 1843 1844static const TCGOutOpBinary outop_andc = { 1845 .base.static_constraint = C_O1_I2(r, r, r), 1846 .out_rrr = tgen_andc, 1847}; 1848 1849static void tgen_clz(TCGContext *s, TCGType type, 1850 TCGReg a0, TCGReg a1, TCGReg a2) 1851{ 1852 tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0, a1, 0); 1853 tcg_out_dat_reg(s, COND_NE, INSN_CLZ, a0, 0, a1, 0); 1854 tcg_out_mov_reg(s, COND_EQ, a0, a2); 1855} 1856 1857static void tgen_clzi(TCGContext *s, TCGType type, 1858 TCGReg a0, TCGReg a1, tcg_target_long a2) 1859{ 1860 if (a2 == 32) { 1861 tcg_out_dat_reg(s, COND_AL, INSN_CLZ, a0, 0, a1, 0); 1862 } else { 1863 tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0, a1, 0); 1864 tcg_out_dat_reg(s, COND_NE, INSN_CLZ, a0, 0, a1, 0); 1865 tcg_out_movi32(s, COND_EQ, a0, a2); 1866 } 1867} 1868 1869static const TCGOutOpBinary outop_clz = { 1870 .base.static_constraint = C_O1_I2(r, r, rIK), 1871 .out_rrr = tgen_clz, 1872 .out_rri = tgen_clzi, 1873}; 1874 1875static const TCGOutOpUnary outop_ctpop = { 1876 .base.static_constraint = C_NotImplemented, 1877}; 1878 1879static void tgen_ctz(TCGContext *s, TCGType type, 1880 TCGReg a0, TCGReg a1, TCGReg a2) 1881{ 1882 tcg_out_dat_reg(s, COND_AL, INSN_RBIT, TCG_REG_TMP, 0, a1, 0); 1883 tgen_clz(s, TCG_TYPE_I32, a0, TCG_REG_TMP, a2); 1884} 1885 1886static void tgen_ctzi(TCGContext *s, TCGType type, 1887 TCGReg a0, TCGReg a1, tcg_target_long a2) 1888{ 1889 tcg_out_dat_reg(s, COND_AL, INSN_RBIT, TCG_REG_TMP, 0, a1, 0); 1890 tgen_clzi(s, TCG_TYPE_I32, a0, TCG_REG_TMP, a2); 1891} 1892 1893static TCGConstraintSetIndex cset_ctz(TCGType type, unsigned flags) 1894{ 1895 return use_armv7_instructions ? C_O1_I2(r, r, rIK) : C_NotImplemented; 1896} 1897 1898static const TCGOutOpBinary outop_ctz = { 1899 .base.static_constraint = C_Dynamic, 1900 .base.dynamic_constraint = cset_ctz, 1901 .out_rrr = tgen_ctz, 1902 .out_rri = tgen_ctzi, 1903}; 1904 1905static TCGConstraintSetIndex cset_idiv(TCGType type, unsigned flags) 1906{ 1907 return use_idiv_instructions ? C_O1_I2(r, r, r) : C_NotImplemented; 1908} 1909 1910static void tgen_divs(TCGContext *s, TCGType type, 1911 TCGReg a0, TCGReg a1, TCGReg a2) 1912{ 1913 /* sdiv */ 1914 tcg_out32(s, 0x0710f010 | (COND_AL << 28) | (a0 << 16) | a1 | (a2 << 8)); 1915} 1916 1917static const TCGOutOpBinary outop_divs = { 1918 .base.static_constraint = C_Dynamic, 1919 .base.dynamic_constraint = cset_idiv, 1920 .out_rrr = tgen_divs, 1921}; 1922 1923static const TCGOutOpDivRem outop_divs2 = { 1924 .base.static_constraint = C_NotImplemented, 1925}; 1926 1927static void tgen_divu(TCGContext *s, TCGType type, 1928 TCGReg a0, TCGReg a1, TCGReg a2) 1929{ 1930 /* udiv */ 1931 tcg_out32(s, 0x0730f010 | (COND_AL << 28) | (a0 << 16) | a1 | (a2 << 8)); 1932} 1933 1934static const TCGOutOpBinary outop_divu = { 1935 .base.static_constraint = C_Dynamic, 1936 .base.dynamic_constraint = cset_idiv, 1937 .out_rrr = tgen_divu, 1938}; 1939 1940static const TCGOutOpDivRem outop_divu2 = { 1941 .base.static_constraint = C_NotImplemented, 1942}; 1943 1944static const TCGOutOpBinary outop_eqv = { 1945 .base.static_constraint = C_NotImplemented, 1946}; 1947 1948static void tgen_mul(TCGContext *s, TCGType type, 1949 TCGReg a0, TCGReg a1, TCGReg a2) 1950{ 1951 /* mul */ 1952 tcg_out32(s, (COND_AL << 28) | 0x90 | (a0 << 16) | (a1 << 8) | a2); 1953} 1954 1955static const TCGOutOpBinary outop_mul = { 1956 .base.static_constraint = C_O1_I2(r, r, r), 1957 .out_rrr = tgen_mul, 1958}; 1959 1960static void tgen_muls2(TCGContext *s, TCGType type, 1961 TCGReg rd0, TCGReg rd1, TCGReg rn, TCGReg rm) 1962{ 1963 /* smull */ 1964 tcg_out32(s, (COND_AL << 28) | 0x00c00090 | 1965 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); 1966} 1967 1968static const TCGOutOpMul2 outop_muls2 = { 1969 .base.static_constraint = C_O2_I2(r, r, r, r), 1970 .out_rrrr = tgen_muls2, 1971}; 1972 1973static const TCGOutOpBinary outop_mulsh = { 1974 .base.static_constraint = C_NotImplemented, 1975}; 1976 1977static void tgen_mulu2(TCGContext *s, TCGType type, 1978 TCGReg rd0, TCGReg rd1, TCGReg rn, TCGReg rm) 1979{ 1980 /* umull */ 1981 tcg_out32(s, (COND_AL << 28) | 0x00800090 | 1982 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); 1983} 1984 1985static const TCGOutOpMul2 outop_mulu2 = { 1986 .base.static_constraint = C_O2_I2(r, r, r, r), 1987 .out_rrrr = tgen_mulu2, 1988}; 1989 1990static const TCGOutOpBinary outop_muluh = { 1991 .base.static_constraint = C_NotImplemented, 1992}; 1993 1994static const TCGOutOpBinary outop_nand = { 1995 .base.static_constraint = C_NotImplemented, 1996}; 1997 1998static const TCGOutOpBinary outop_nor = { 1999 .base.static_constraint = C_NotImplemented, 2000}; 2001 2002static void tgen_or(TCGContext *s, TCGType type, 2003 TCGReg a0, TCGReg a1, TCGReg a2) 2004{ 2005 tcg_out_dat_reg(s, COND_AL, ARITH_ORR, a0, a1, a2, SHIFT_IMM_LSL(0)); 2006} 2007 2008static void tgen_ori(TCGContext *s, TCGType type, 2009 TCGReg a0, TCGReg a1, tcg_target_long a2) 2010{ 2011 tcg_out_dat_imm(s, COND_AL, ARITH_ORR, a0, a1, encode_imm_nofail(a2)); 2012} 2013 2014static const TCGOutOpBinary outop_or = { 2015 .base.static_constraint = C_O1_I2(r, r, rI), 2016 .out_rrr = tgen_or, 2017 .out_rri = tgen_ori, 2018}; 2019 2020static const TCGOutOpBinary outop_orc = { 2021 .base.static_constraint = C_NotImplemented, 2022}; 2023 2024static const TCGOutOpBinary outop_rems = { 2025 .base.static_constraint = C_NotImplemented, 2026}; 2027 2028static const TCGOutOpBinary outop_remu = { 2029 .base.static_constraint = C_NotImplemented, 2030}; 2031 2032static const TCGOutOpBinary outop_rotl = { 2033 .base.static_constraint = C_NotImplemented, 2034}; 2035 2036static void tgen_rotr(TCGContext *s, TCGType type, 2037 TCGReg a0, TCGReg a1, TCGReg a2) 2038{ 2039 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, SHIFT_REG_ROR(a2)); 2040} 2041 2042static void tgen_rotri(TCGContext *s, TCGType type, 2043 TCGReg a0, TCGReg a1, tcg_target_long a2) 2044{ 2045 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, SHIFT_IMM_ROR(a2 & 0x1f)); 2046} 2047 2048static const TCGOutOpBinary outop_rotr = { 2049 .base.static_constraint = C_O1_I2(r, r, ri), 2050 .out_rrr = tgen_rotr, 2051 .out_rri = tgen_rotri, 2052}; 2053 2054static void tgen_sar(TCGContext *s, TCGType type, 2055 TCGReg a0, TCGReg a1, TCGReg a2) 2056{ 2057 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, SHIFT_REG_ASR(a2)); 2058} 2059 2060static void tgen_sari(TCGContext *s, TCGType type, 2061 TCGReg a0, TCGReg a1, tcg_target_long a2) 2062{ 2063 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, 2064 SHIFT_IMM_ASR(a2 & 0x1f)); 2065} 2066 2067static const TCGOutOpBinary outop_sar = { 2068 .base.static_constraint = C_O1_I2(r, r, ri), 2069 .out_rrr = tgen_sar, 2070 .out_rri = tgen_sari, 2071}; 2072 2073static void tgen_shl(TCGContext *s, TCGType type, 2074 TCGReg a0, TCGReg a1, TCGReg a2) 2075{ 2076 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, SHIFT_REG_LSL(a2)); 2077} 2078 2079static void tgen_shli(TCGContext *s, TCGType type, 2080 TCGReg a0, TCGReg a1, tcg_target_long a2) 2081{ 2082 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, 2083 SHIFT_IMM_LSL(a2 & 0x1f)); 2084} 2085 2086static const TCGOutOpBinary outop_shl = { 2087 .base.static_constraint = C_O1_I2(r, r, ri), 2088 .out_rrr = tgen_shl, 2089 .out_rri = tgen_shli, 2090}; 2091 2092static void tgen_shr(TCGContext *s, TCGType type, 2093 TCGReg a0, TCGReg a1, TCGReg a2) 2094{ 2095 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, SHIFT_REG_LSR(a2)); 2096} 2097 2098static void tgen_shri(TCGContext *s, TCGType type, 2099 TCGReg a0, TCGReg a1, tcg_target_long a2) 2100{ 2101 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, 2102 SHIFT_IMM_LSR(a2 & 0x1f)); 2103} 2104 2105static const TCGOutOpBinary outop_shr = { 2106 .base.static_constraint = C_O1_I2(r, r, ri), 2107 .out_rrr = tgen_shr, 2108 .out_rri = tgen_shri, 2109}; 2110 2111static void tgen_sub(TCGContext *s, TCGType type, 2112 TCGReg a0, TCGReg a1, TCGReg a2) 2113{ 2114 tcg_out_dat_reg(s, COND_AL, ARITH_SUB, a0, a1, a2, SHIFT_IMM_LSL(0)); 2115} 2116 2117static void tgen_subfi(TCGContext *s, TCGType type, 2118 TCGReg a0, tcg_target_long a1, TCGReg a2) 2119{ 2120 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, a0, a2, encode_imm_nofail(a1)); 2121} 2122 2123static const TCGOutOpSubtract outop_sub = { 2124 .base.static_constraint = C_O1_I2(r, rI, r), 2125 .out_rrr = tgen_sub, 2126 .out_rir = tgen_subfi, 2127}; 2128 2129static void tgen_xor(TCGContext *s, TCGType type, 2130 TCGReg a0, TCGReg a1, TCGReg a2) 2131{ 2132 tcg_out_dat_reg(s, COND_AL, ARITH_EOR, a0, a1, a2, SHIFT_IMM_LSL(0)); 2133} 2134 2135static void tgen_xori(TCGContext *s, TCGType type, 2136 TCGReg a0, TCGReg a1, tcg_target_long a2) 2137{ 2138 tcg_out_dat_imm(s, COND_AL, ARITH_EOR, a0, a1, encode_imm_nofail(a2)); 2139} 2140 2141static const TCGOutOpBinary outop_xor = { 2142 .base.static_constraint = C_O1_I2(r, r, rI), 2143 .out_rrr = tgen_xor, 2144 .out_rri = tgen_xori, 2145}; 2146 2147static void tgen_bswap16(TCGContext *s, TCGType type, 2148 TCGReg rd, TCGReg rn, unsigned flags) 2149{ 2150 if (flags & TCG_BSWAP_OS) { 2151 /* revsh */ 2152 tcg_out32(s, 0x06ff0fb0 | (COND_AL << 28) | (rd << 12) | rn); 2153 return; 2154 } 2155 2156 /* rev16 */ 2157 tcg_out32(s, 0x06bf0fb0 | (COND_AL << 28) | (rd << 12) | rn); 2158 if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 2159 tcg_out_ext16u(s, rd, rd); 2160 } 2161} 2162 2163static const TCGOutOpBswap outop_bswap16 = { 2164 .base.static_constraint = C_O1_I1(r, r), 2165 .out_rr = tgen_bswap16, 2166}; 2167 2168static void tgen_bswap32(TCGContext *s, TCGType type, 2169 TCGReg rd, TCGReg rn, unsigned flags) 2170{ 2171 /* rev */ 2172 tcg_out32(s, 0x06bf0f30 | (COND_AL << 28) | (rd << 12) | rn); 2173} 2174 2175static const TCGOutOpBswap outop_bswap32 = { 2176 .base.static_constraint = C_O1_I1(r, r), 2177 .out_rr = tgen_bswap32, 2178}; 2179 2180static const TCGOutOpUnary outop_bswap64 = { 2181 .base.static_constraint = C_NotImplemented, 2182}; 2183 2184static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2185{ 2186 tgen_subfi(s, type, a0, 0, a1); 2187} 2188 2189static const TCGOutOpUnary outop_neg = { 2190 .base.static_constraint = C_O1_I1(r, r), 2191 .out_rr = tgen_neg, 2192}; 2193 2194static void tgen_not(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2195{ 2196 tcg_out_dat_reg(s, COND_AL, ARITH_MVN, a0, 0, a1, SHIFT_IMM_LSL(0)); 2197} 2198 2199static const TCGOutOpUnary outop_not = { 2200 .base.static_constraint = C_O1_I1(r, r), 2201 .out_rr = tgen_not, 2202}; 2203 2204static void tgen_brcond(TCGContext *s, TCGType type, TCGCond cond, 2205 TCGReg a0, TCGReg a1, TCGLabel *l) 2206{ 2207 cond = tgen_cmp(s, cond, a0, a1); 2208 tcg_out_goto_label(s, tcg_cond_to_arm_cond[cond], l); 2209} 2210 2211static void tgen_brcondi(TCGContext *s, TCGType type, TCGCond cond, 2212 TCGReg a0, tcg_target_long a1, TCGLabel *l) 2213{ 2214 cond = tgen_cmpi(s, cond, a0, a1); 2215 tcg_out_goto_label(s, tcg_cond_to_arm_cond[cond], l); 2216} 2217 2218static const TCGOutOpBrcond outop_brcond = { 2219 .base.static_constraint = C_O0_I2(r, rIN), 2220 .out_rr = tgen_brcond, 2221 .out_ri = tgen_brcondi, 2222}; 2223 2224static void finish_setcond(TCGContext *s, TCGCond cond, TCGReg ret, bool neg) 2225{ 2226 tcg_out_movi32(s, tcg_cond_to_arm_cond[tcg_invert_cond(cond)], ret, 0); 2227 tcg_out_movi32(s, tcg_cond_to_arm_cond[cond], ret, neg ? -1 : 1); 2228} 2229 2230static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, 2231 TCGReg a0, TCGReg a1, TCGReg a2) 2232{ 2233 cond = tgen_cmp(s, cond, a1, a2); 2234 finish_setcond(s, cond, a0, false); 2235} 2236 2237static void tgen_setcondi(TCGContext *s, TCGType type, TCGCond cond, 2238 TCGReg a0, TCGReg a1, tcg_target_long a2) 2239{ 2240 cond = tgen_cmpi(s, cond, a1, a2); 2241 finish_setcond(s, cond, a0, false); 2242} 2243 2244static const TCGOutOpSetcond outop_setcond = { 2245 .base.static_constraint = C_O1_I2(r, r, rIN), 2246 .out_rrr = tgen_setcond, 2247 .out_rri = tgen_setcondi, 2248}; 2249 2250static void tgen_negsetcond(TCGContext *s, TCGType type, TCGCond cond, 2251 TCGReg a0, TCGReg a1, TCGReg a2) 2252{ 2253 cond = tgen_cmp(s, cond, a1, a2); 2254 finish_setcond(s, cond, a0, true); 2255} 2256 2257static void tgen_negsetcondi(TCGContext *s, TCGType type, TCGCond cond, 2258 TCGReg a0, TCGReg a1, tcg_target_long a2) 2259{ 2260 cond = tgen_cmpi(s, cond, a1, a2); 2261 finish_setcond(s, cond, a0, true); 2262} 2263 2264static const TCGOutOpSetcond outop_negsetcond = { 2265 .base.static_constraint = C_O1_I2(r, r, rIN), 2266 .out_rrr = tgen_negsetcond, 2267 .out_rri = tgen_negsetcondi, 2268}; 2269 2270static void tgen_movcond(TCGContext *s, TCGType type, TCGCond cond, 2271 TCGReg ret, TCGReg c1, TCGArg c2, bool const_c2, 2272 TCGArg vt, bool const_vt, TCGArg vf, bool consf_vf) 2273{ 2274 cond = tcg_out_cmp(s, cond, c1, c2, const_c2); 2275 tcg_out_dat_rIK(s, tcg_cond_to_arm_cond[cond], ARITH_MOV, ARITH_MVN, 2276 ret, 0, vt, const_vt); 2277} 2278 2279static const TCGOutOpMovcond outop_movcond = { 2280 .base.static_constraint = C_O1_I4(r, r, rIN, rIK, 0), 2281 .out = tgen_movcond, 2282}; 2283 2284static void tgen_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, 2285 TCGArg bl, bool const_bl, TCGArg bh, bool const_bh, 2286 TCGLabel *l) 2287{ 2288 cond = tcg_out_cmp2(s, cond, al, ah, bl, const_bl, bh, const_bh); 2289 tcg_out_goto_label(s, tcg_cond_to_arm_cond[cond], l); 2290} 2291 2292static const TCGOutOpBrcond2 outop_brcond2 = { 2293 .base.static_constraint = C_O0_I4(r, r, rI, rI), 2294 .out = tgen_brcond2, 2295}; 2296 2297static void tgen_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, 2298 TCGReg al, TCGReg ah, 2299 TCGArg bl, bool const_bl, 2300 TCGArg bh, bool const_bh) 2301{ 2302 cond = tcg_out_cmp2(s, cond, al, ah, bl, const_bl, bh, const_bh); 2303 finish_setcond(s, cond, ret, false); 2304} 2305 2306static const TCGOutOpSetcond2 outop_setcond2 = { 2307 .base.static_constraint = C_O1_I4(r, r, r, rI, rI), 2308 .out = tgen_setcond2, 2309}; 2310 2311static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, 2312 const TCGArg args[TCG_MAX_OP_ARGS], 2313 const int const_args[TCG_MAX_OP_ARGS]) 2314{ 2315 TCGArg a0, a1, a2, a3, a4, a5; 2316 2317 switch (opc) { 2318 case INDEX_op_goto_ptr: 2319 tcg_out_b_reg(s, COND_AL, args[0]); 2320 break; 2321 case INDEX_op_br: 2322 tcg_out_goto_label(s, COND_AL, arg_label(args[0])); 2323 break; 2324 2325 case INDEX_op_ld8u_i32: 2326 tcg_out_ld8u(s, COND_AL, args[0], args[1], args[2]); 2327 break; 2328 case INDEX_op_ld8s_i32: 2329 tcg_out_ld8s(s, COND_AL, args[0], args[1], args[2]); 2330 break; 2331 case INDEX_op_ld16u_i32: 2332 tcg_out_ld16u(s, COND_AL, args[0], args[1], args[2]); 2333 break; 2334 case INDEX_op_ld16s_i32: 2335 tcg_out_ld16s(s, COND_AL, args[0], args[1], args[2]); 2336 break; 2337 case INDEX_op_ld_i32: 2338 tcg_out_ld32u(s, COND_AL, args[0], args[1], args[2]); 2339 break; 2340 case INDEX_op_st8_i32: 2341 tcg_out_st8(s, COND_AL, args[0], args[1], args[2]); 2342 break; 2343 case INDEX_op_st16_i32: 2344 tcg_out_st16(s, COND_AL, args[0], args[1], args[2]); 2345 break; 2346 case INDEX_op_st_i32: 2347 tcg_out_st32(s, COND_AL, args[0], args[1], args[2]); 2348 break; 2349 2350 case INDEX_op_add2_i32: 2351 a0 = args[0], a1 = args[1], a2 = args[2]; 2352 a3 = args[3], a4 = args[4], a5 = args[5]; 2353 if (a0 == a3 || (a0 == a5 && !const_args[5])) { 2354 a0 = TCG_REG_TMP; 2355 } 2356 tcg_out_dat_rIN(s, COND_AL, ARITH_ADD | TO_CPSR, ARITH_SUB | TO_CPSR, 2357 a0, a2, a4, const_args[4]); 2358 tcg_out_dat_rIK(s, COND_AL, ARITH_ADC, ARITH_SBC, 2359 a1, a3, a5, const_args[5]); 2360 tcg_out_mov_reg(s, COND_AL, args[0], a0); 2361 break; 2362 case INDEX_op_sub2_i32: 2363 a0 = args[0], a1 = args[1], a2 = args[2]; 2364 a3 = args[3], a4 = args[4], a5 = args[5]; 2365 if ((a0 == a3 && !const_args[3]) || (a0 == a5 && !const_args[5])) { 2366 a0 = TCG_REG_TMP; 2367 } 2368 if (const_args[2]) { 2369 if (const_args[4]) { 2370 tcg_out_movi32(s, COND_AL, a0, a4); 2371 a4 = a0; 2372 } 2373 tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR, a0, a4, a2, 1); 2374 } else { 2375 tcg_out_dat_rIN(s, COND_AL, ARITH_SUB | TO_CPSR, 2376 ARITH_ADD | TO_CPSR, a0, a2, a4, const_args[4]); 2377 } 2378 if (const_args[3]) { 2379 if (const_args[5]) { 2380 tcg_out_movi32(s, COND_AL, a1, a5); 2381 a5 = a1; 2382 } 2383 tcg_out_dat_rI(s, COND_AL, ARITH_RSC, a1, a5, a3, 1); 2384 } else { 2385 tcg_out_dat_rIK(s, COND_AL, ARITH_SBC, ARITH_ADC, 2386 a1, a3, a5, const_args[5]); 2387 } 2388 tcg_out_mov_reg(s, COND_AL, args[0], a0); 2389 break; 2390 2391 case INDEX_op_qemu_ld_i32: 2392 tcg_out_qemu_ld(s, args[0], -1, args[1], args[2], TCG_TYPE_I32); 2393 break; 2394 case INDEX_op_qemu_ld_i64: 2395 tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3], TCG_TYPE_I64); 2396 break; 2397 2398 case INDEX_op_qemu_st_i32: 2399 tcg_out_qemu_st(s, args[0], -1, args[1], args[2], TCG_TYPE_I32); 2400 break; 2401 case INDEX_op_qemu_st_i64: 2402 tcg_out_qemu_st(s, args[0], args[1], args[2], args[3], TCG_TYPE_I64); 2403 break; 2404 2405 case INDEX_op_deposit_i32: 2406 tcg_out_deposit(s, COND_AL, args[0], args[2], 2407 args[3], args[4], const_args[2]); 2408 break; 2409 case INDEX_op_extract2_i32: 2410 /* ??? These optimization vs zero should be generic. */ 2411 /* ??? But we can't substitute 2 for 1 in the opcode stream yet. */ 2412 if (const_args[1]) { 2413 if (const_args[2]) { 2414 tcg_out_movi(s, TCG_TYPE_REG, args[0], 0); 2415 } else { 2416 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, 2417 args[2], SHIFT_IMM_LSL(32 - args[3])); 2418 } 2419 } else if (const_args[2]) { 2420 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, 2421 args[1], SHIFT_IMM_LSR(args[3])); 2422 } else { 2423 /* We can do extract2 in 2 insns, vs the 3 required otherwise. */ 2424 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, 2425 args[2], SHIFT_IMM_LSL(32 - args[3])); 2426 tcg_out_dat_reg(s, COND_AL, ARITH_ORR, args[0], TCG_REG_TMP, 2427 args[1], SHIFT_IMM_LSR(args[3])); 2428 } 2429 break; 2430 2431 case INDEX_op_mb: 2432 tcg_out_mb(s, args[0]); 2433 break; 2434 2435 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2436 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2437 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2438 default: 2439 g_assert_not_reached(); 2440 } 2441} 2442 2443static TCGConstraintSetIndex 2444tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) 2445{ 2446 switch (op) { 2447 case INDEX_op_goto_ptr: 2448 return C_O0_I1(r); 2449 2450 case INDEX_op_ld8u_i32: 2451 case INDEX_op_ld8s_i32: 2452 case INDEX_op_ld16u_i32: 2453 case INDEX_op_ld16s_i32: 2454 case INDEX_op_ld_i32: 2455 return C_O1_I1(r, r); 2456 2457 case INDEX_op_st8_i32: 2458 case INDEX_op_st16_i32: 2459 case INDEX_op_st_i32: 2460 return C_O0_I2(r, r); 2461 2462 case INDEX_op_deposit_i32: 2463 return C_O1_I2(r, 0, rZ); 2464 case INDEX_op_extract2_i32: 2465 return C_O1_I2(r, rZ, rZ); 2466 case INDEX_op_add2_i32: 2467 return C_O2_I4(r, r, r, r, rIN, rIK); 2468 case INDEX_op_sub2_i32: 2469 return C_O2_I4(r, r, rI, rI, rIN, rIK); 2470 case INDEX_op_qemu_ld_i32: 2471 return C_O1_I1(r, q); 2472 case INDEX_op_qemu_ld_i64: 2473 return C_O2_I1(e, p, q); 2474 case INDEX_op_qemu_st_i32: 2475 return C_O0_I2(q, q); 2476 case INDEX_op_qemu_st_i64: 2477 return C_O0_I3(Q, p, q); 2478 2479 case INDEX_op_st_vec: 2480 return C_O0_I2(w, r); 2481 case INDEX_op_ld_vec: 2482 case INDEX_op_dupm_vec: 2483 return C_O1_I1(w, r); 2484 case INDEX_op_dup_vec: 2485 return C_O1_I1(w, wr); 2486 case INDEX_op_abs_vec: 2487 case INDEX_op_neg_vec: 2488 case INDEX_op_not_vec: 2489 case INDEX_op_shli_vec: 2490 case INDEX_op_shri_vec: 2491 case INDEX_op_sari_vec: 2492 return C_O1_I1(w, w); 2493 case INDEX_op_dup2_vec: 2494 case INDEX_op_add_vec: 2495 case INDEX_op_mul_vec: 2496 case INDEX_op_smax_vec: 2497 case INDEX_op_smin_vec: 2498 case INDEX_op_ssadd_vec: 2499 case INDEX_op_sssub_vec: 2500 case INDEX_op_sub_vec: 2501 case INDEX_op_umax_vec: 2502 case INDEX_op_umin_vec: 2503 case INDEX_op_usadd_vec: 2504 case INDEX_op_ussub_vec: 2505 case INDEX_op_xor_vec: 2506 case INDEX_op_arm_sshl_vec: 2507 case INDEX_op_arm_ushl_vec: 2508 return C_O1_I2(w, w, w); 2509 case INDEX_op_arm_sli_vec: 2510 return C_O1_I2(w, 0, w); 2511 case INDEX_op_or_vec: 2512 case INDEX_op_andc_vec: 2513 return C_O1_I2(w, w, wO); 2514 case INDEX_op_and_vec: 2515 case INDEX_op_orc_vec: 2516 return C_O1_I2(w, w, wV); 2517 case INDEX_op_cmp_vec: 2518 return C_O1_I2(w, w, wZ); 2519 case INDEX_op_bitsel_vec: 2520 return C_O1_I3(w, w, w, w); 2521 default: 2522 return C_NotImplemented; 2523 } 2524} 2525 2526static void tcg_target_init(TCGContext *s) 2527{ 2528 /* 2529 * Only probe for the platform and capabilities if we haven't already 2530 * determined maximum values at compile time. 2531 */ 2532#if !defined(use_idiv_instructions) || !defined(use_neon_instructions) 2533 { 2534 unsigned long hwcap = qemu_getauxval(AT_HWCAP); 2535#ifndef use_idiv_instructions 2536 use_idiv_instructions = (hwcap & HWCAP_ARM_IDIVA) != 0; 2537#endif 2538#ifndef use_neon_instructions 2539 use_neon_instructions = (hwcap & HWCAP_ARM_NEON) != 0; 2540#endif 2541 } 2542#endif 2543 2544 if (__ARM_ARCH < 7) { 2545 const char *pl = (const char *)qemu_getauxval(AT_PLATFORM); 2546 if (pl != NULL && pl[0] == 'v' && pl[1] >= '4' && pl[1] <= '9') { 2547 arm_arch = pl[1] - '0'; 2548 } 2549 2550 if (arm_arch < 6) { 2551 error_report("TCG: ARMv%d is unsupported; exiting", arm_arch); 2552 exit(EXIT_FAILURE); 2553 } 2554 } 2555 2556 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS; 2557 2558 tcg_target_call_clobber_regs = 0; 2559 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); 2560 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1); 2561 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2); 2562 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3); 2563 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12); 2564 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14); 2565 2566 if (use_neon_instructions) { 2567 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS; 2568 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS; 2569 2570 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q0); 2571 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q1); 2572 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q2); 2573 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q3); 2574 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q8); 2575 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q9); 2576 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q10); 2577 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q11); 2578 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q12); 2579 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q13); 2580 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q14); 2581 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q15); 2582 } 2583 2584 s->reserved_regs = 0; 2585 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); 2586 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP); 2587 tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC); 2588 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP); 2589} 2590 2591static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 2592 TCGReg arg1, intptr_t arg2) 2593{ 2594 switch (type) { 2595 case TCG_TYPE_I32: 2596 tcg_out_ld32u(s, COND_AL, arg, arg1, arg2); 2597 return; 2598 case TCG_TYPE_V64: 2599 /* regs 1; size 8; align 8 */ 2600 tcg_out_vldst(s, INSN_VLD1 | 0x7d0, arg, arg1, arg2); 2601 return; 2602 case TCG_TYPE_V128: 2603 /* 2604 * We have only 8-byte alignment for the stack per the ABI. 2605 * Rather than dynamically re-align the stack, it's easier 2606 * to simply not request alignment beyond that. So: 2607 * regs 2; size 8; align 8 2608 */ 2609 tcg_out_vldst(s, INSN_VLD1 | 0xad0, arg, arg1, arg2); 2610 return; 2611 default: 2612 g_assert_not_reached(); 2613 } 2614} 2615 2616static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 2617 TCGReg arg1, intptr_t arg2) 2618{ 2619 switch (type) { 2620 case TCG_TYPE_I32: 2621 tcg_out_st32(s, COND_AL, arg, arg1, arg2); 2622 return; 2623 case TCG_TYPE_V64: 2624 /* regs 1; size 8; align 8 */ 2625 tcg_out_vldst(s, INSN_VST1 | 0x7d0, arg, arg1, arg2); 2626 return; 2627 case TCG_TYPE_V128: 2628 /* See tcg_out_ld re alignment: regs 2; size 8; align 8 */ 2629 tcg_out_vldst(s, INSN_VST1 | 0xad0, arg, arg1, arg2); 2630 return; 2631 default: 2632 g_assert_not_reached(); 2633 } 2634} 2635 2636static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 2637 TCGReg base, intptr_t ofs) 2638{ 2639 return false; 2640} 2641 2642static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 2643{ 2644 if (ret == arg) { 2645 return true; 2646 } 2647 switch (type) { 2648 case TCG_TYPE_I32: 2649 if (ret < TCG_REG_Q0 && arg < TCG_REG_Q0) { 2650 tcg_out_mov_reg(s, COND_AL, ret, arg); 2651 return true; 2652 } 2653 return false; 2654 2655 case TCG_TYPE_V64: 2656 case TCG_TYPE_V128: 2657 /* "VMOV D,N" is an alias for "VORR D,N,N". */ 2658 tcg_out_vreg3(s, INSN_VORR, type - TCG_TYPE_V64, 0, ret, arg, arg); 2659 return true; 2660 2661 default: 2662 g_assert_not_reached(); 2663 } 2664} 2665 2666static void tcg_out_movi(TCGContext *s, TCGType type, 2667 TCGReg ret, tcg_target_long arg) 2668{ 2669 tcg_debug_assert(type == TCG_TYPE_I32); 2670 tcg_debug_assert(ret < TCG_REG_Q0); 2671 tcg_out_movi32(s, COND_AL, ret, arg); 2672} 2673 2674static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 2675{ 2676 return false; 2677} 2678 2679static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 2680 tcg_target_long imm) 2681{ 2682 int enc, opc = ARITH_ADD; 2683 2684 /* All of the easiest immediates to encode are positive. */ 2685 if (imm < 0) { 2686 imm = -imm; 2687 opc = ARITH_SUB; 2688 } 2689 enc = encode_imm(imm); 2690 if (enc >= 0) { 2691 tcg_out_dat_imm(s, COND_AL, opc, rd, rs, enc); 2692 } else { 2693 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, imm); 2694 tcg_out_dat_reg(s, COND_AL, opc, rd, rs, 2695 TCG_REG_TMP, SHIFT_IMM_LSL(0)); 2696 } 2697} 2698 2699/* Type is always V128, with I64 elements. */ 2700static void tcg_out_dup2_vec(TCGContext *s, TCGReg rd, TCGReg rl, TCGReg rh) 2701{ 2702 /* Move high element into place first. */ 2703 /* VMOV Dd+1, Ds */ 2704 tcg_out_vreg3(s, INSN_VORR | (1 << 12), 0, 0, rd, rh, rh); 2705 /* Move low element into place; tcg_out_mov will check for nop. */ 2706 tcg_out_mov(s, TCG_TYPE_V64, rd, rl); 2707} 2708 2709static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 2710 TCGReg rd, TCGReg rs) 2711{ 2712 int q = type - TCG_TYPE_V64; 2713 2714 if (vece == MO_64) { 2715 if (type == TCG_TYPE_V128) { 2716 tcg_out_dup2_vec(s, rd, rs, rs); 2717 } else { 2718 tcg_out_mov(s, TCG_TYPE_V64, rd, rs); 2719 } 2720 } else if (rs < TCG_REG_Q0) { 2721 int b = (vece == MO_8); 2722 int e = (vece == MO_16); 2723 tcg_out32(s, INSN_VDUP_G | (b << 22) | (q << 21) | (e << 5) | 2724 encode_vn(rd) | (rs << 12)); 2725 } else { 2726 int imm4 = 1 << vece; 2727 tcg_out32(s, INSN_VDUP_S | (imm4 << 16) | (q << 6) | 2728 encode_vd(rd) | encode_vm(rs)); 2729 } 2730 return true; 2731} 2732 2733static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 2734 TCGReg rd, TCGReg base, intptr_t offset) 2735{ 2736 if (vece == MO_64) { 2737 tcg_out_ld(s, TCG_TYPE_V64, rd, base, offset); 2738 if (type == TCG_TYPE_V128) { 2739 tcg_out_dup2_vec(s, rd, rd, rd); 2740 } 2741 } else { 2742 int q = type - TCG_TYPE_V64; 2743 tcg_out_vldst(s, INSN_VLD1R | (vece << 6) | (q << 5), 2744 rd, base, offset); 2745 } 2746 return true; 2747} 2748 2749static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 2750 TCGReg rd, int64_t v64) 2751{ 2752 int q = type - TCG_TYPE_V64; 2753 int cmode, imm8, i; 2754 2755 /* Test all bytes equal first. */ 2756 if (vece == MO_8) { 2757 tcg_out_vmovi(s, rd, q, 0, 0xe, v64); 2758 return; 2759 } 2760 2761 /* 2762 * Test all bytes 0x00 or 0xff second. This can match cases that 2763 * might otherwise take 2 or 3 insns for MO_16 or MO_32 below. 2764 */ 2765 for (i = imm8 = 0; i < 8; i++) { 2766 uint8_t byte = v64 >> (i * 8); 2767 if (byte == 0xff) { 2768 imm8 |= 1 << i; 2769 } else if (byte != 0) { 2770 goto fail_bytes; 2771 } 2772 } 2773 tcg_out_vmovi(s, rd, q, 1, 0xe, imm8); 2774 return; 2775 fail_bytes: 2776 2777 /* 2778 * Tests for various replications. For each element width, if we 2779 * cannot find an expansion there's no point checking a larger 2780 * width because we already know by replication it cannot match. 2781 */ 2782 if (vece == MO_16) { 2783 uint16_t v16 = v64; 2784 2785 if (is_shimm16(v16, &cmode, &imm8)) { 2786 tcg_out_vmovi(s, rd, q, 0, cmode, imm8); 2787 return; 2788 } 2789 if (is_shimm16(~v16, &cmode, &imm8)) { 2790 tcg_out_vmovi(s, rd, q, 1, cmode, imm8); 2791 return; 2792 } 2793 2794 /* 2795 * Otherwise, all remaining constants can be loaded in two insns: 2796 * rd = v16 & 0xff, rd |= v16 & 0xff00. 2797 */ 2798 tcg_out_vmovi(s, rd, q, 0, 0x8, v16 & 0xff); 2799 tcg_out_vmovi(s, rd, q, 0, 0xb, v16 >> 8); /* VORRI */ 2800 return; 2801 } 2802 2803 if (vece == MO_32) { 2804 uint32_t v32 = v64; 2805 2806 if (is_shimm32(v32, &cmode, &imm8) || 2807 is_soimm32(v32, &cmode, &imm8)) { 2808 tcg_out_vmovi(s, rd, q, 0, cmode, imm8); 2809 return; 2810 } 2811 if (is_shimm32(~v32, &cmode, &imm8) || 2812 is_soimm32(~v32, &cmode, &imm8)) { 2813 tcg_out_vmovi(s, rd, q, 1, cmode, imm8); 2814 return; 2815 } 2816 2817 /* 2818 * Restrict the set of constants to those we can load with 2819 * two instructions. Others we load from the pool. 2820 */ 2821 i = is_shimm32_pair(v32, &cmode, &imm8); 2822 if (i) { 2823 tcg_out_vmovi(s, rd, q, 0, cmode, imm8); 2824 tcg_out_vmovi(s, rd, q, 0, i | 1, extract32(v32, i * 4, 8)); 2825 return; 2826 } 2827 i = is_shimm32_pair(~v32, &cmode, &imm8); 2828 if (i) { 2829 tcg_out_vmovi(s, rd, q, 1, cmode, imm8); 2830 tcg_out_vmovi(s, rd, q, 1, i | 1, extract32(~v32, i * 4, 8)); 2831 return; 2832 } 2833 } 2834 2835 /* 2836 * As a last resort, load from the constant pool. 2837 */ 2838 if (!q || vece == MO_64) { 2839 new_pool_l2(s, R_ARM_PC11, s->code_ptr, 0, v64, v64 >> 32); 2840 /* VLDR Dd, [pc + offset] */ 2841 tcg_out32(s, INSN_VLDR_D | encode_vd(rd) | (0xf << 16)); 2842 if (q) { 2843 tcg_out_dup2_vec(s, rd, rd, rd); 2844 } 2845 } else { 2846 new_pool_label(s, (uint32_t)v64, R_ARM_PC8, s->code_ptr, 0); 2847 /* add tmp, pc, offset */ 2848 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_TMP, TCG_REG_PC, 0); 2849 tcg_out_dupm_vec(s, type, MO_32, rd, TCG_REG_TMP, 0); 2850 } 2851} 2852 2853static const ARMInsn vec_cmp_insn[16] = { 2854 [TCG_COND_EQ] = INSN_VCEQ, 2855 [TCG_COND_GT] = INSN_VCGT, 2856 [TCG_COND_GE] = INSN_VCGE, 2857 [TCG_COND_GTU] = INSN_VCGT_U, 2858 [TCG_COND_GEU] = INSN_VCGE_U, 2859}; 2860 2861static const ARMInsn vec_cmp0_insn[16] = { 2862 [TCG_COND_EQ] = INSN_VCEQ0, 2863 [TCG_COND_GT] = INSN_VCGT0, 2864 [TCG_COND_GE] = INSN_VCGE0, 2865 [TCG_COND_LT] = INSN_VCLT0, 2866 [TCG_COND_LE] = INSN_VCLE0, 2867}; 2868 2869static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 2870 unsigned vecl, unsigned vece, 2871 const TCGArg args[TCG_MAX_OP_ARGS], 2872 const int const_args[TCG_MAX_OP_ARGS]) 2873{ 2874 TCGType type = vecl + TCG_TYPE_V64; 2875 unsigned q = vecl; 2876 TCGArg a0, a1, a2, a3; 2877 int cmode, imm8; 2878 2879 a0 = args[0]; 2880 a1 = args[1]; 2881 a2 = args[2]; 2882 2883 switch (opc) { 2884 case INDEX_op_ld_vec: 2885 tcg_out_ld(s, type, a0, a1, a2); 2886 return; 2887 case INDEX_op_st_vec: 2888 tcg_out_st(s, type, a0, a1, a2); 2889 return; 2890 case INDEX_op_dupm_vec: 2891 tcg_out_dupm_vec(s, type, vece, a0, a1, a2); 2892 return; 2893 case INDEX_op_dup2_vec: 2894 tcg_out_dup2_vec(s, a0, a1, a2); 2895 return; 2896 case INDEX_op_abs_vec: 2897 tcg_out_vreg2(s, INSN_VABS, q, vece, a0, a1); 2898 return; 2899 case INDEX_op_neg_vec: 2900 tcg_out_vreg2(s, INSN_VNEG, q, vece, a0, a1); 2901 return; 2902 case INDEX_op_not_vec: 2903 tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a1); 2904 return; 2905 case INDEX_op_add_vec: 2906 tcg_out_vreg3(s, INSN_VADD, q, vece, a0, a1, a2); 2907 return; 2908 case INDEX_op_mul_vec: 2909 tcg_out_vreg3(s, INSN_VMUL, q, vece, a0, a1, a2); 2910 return; 2911 case INDEX_op_smax_vec: 2912 tcg_out_vreg3(s, INSN_VMAX, q, vece, a0, a1, a2); 2913 return; 2914 case INDEX_op_smin_vec: 2915 tcg_out_vreg3(s, INSN_VMIN, q, vece, a0, a1, a2); 2916 return; 2917 case INDEX_op_sub_vec: 2918 tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2); 2919 return; 2920 case INDEX_op_ssadd_vec: 2921 tcg_out_vreg3(s, INSN_VQADD, q, vece, a0, a1, a2); 2922 return; 2923 case INDEX_op_sssub_vec: 2924 tcg_out_vreg3(s, INSN_VQSUB, q, vece, a0, a1, a2); 2925 return; 2926 case INDEX_op_umax_vec: 2927 tcg_out_vreg3(s, INSN_VMAX_U, q, vece, a0, a1, a2); 2928 return; 2929 case INDEX_op_umin_vec: 2930 tcg_out_vreg3(s, INSN_VMIN_U, q, vece, a0, a1, a2); 2931 return; 2932 case INDEX_op_usadd_vec: 2933 tcg_out_vreg3(s, INSN_VQADD_U, q, vece, a0, a1, a2); 2934 return; 2935 case INDEX_op_ussub_vec: 2936 tcg_out_vreg3(s, INSN_VQSUB_U, q, vece, a0, a1, a2); 2937 return; 2938 case INDEX_op_xor_vec: 2939 tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2); 2940 return; 2941 case INDEX_op_arm_sshl_vec: 2942 /* 2943 * Note that Vm is the data and Vn is the shift count, 2944 * therefore the arguments appear reversed. 2945 */ 2946 tcg_out_vreg3(s, INSN_VSHL_S, q, vece, a0, a2, a1); 2947 return; 2948 case INDEX_op_arm_ushl_vec: 2949 /* See above. */ 2950 tcg_out_vreg3(s, INSN_VSHL_U, q, vece, a0, a2, a1); 2951 return; 2952 case INDEX_op_shli_vec: 2953 tcg_out_vshifti(s, INSN_VSHLI, q, a0, a1, a2 + (8 << vece)); 2954 return; 2955 case INDEX_op_shri_vec: 2956 tcg_out_vshifti(s, INSN_VSHRI, q, a0, a1, (16 << vece) - a2); 2957 return; 2958 case INDEX_op_sari_vec: 2959 tcg_out_vshifti(s, INSN_VSARI, q, a0, a1, (16 << vece) - a2); 2960 return; 2961 case INDEX_op_arm_sli_vec: 2962 tcg_out_vshifti(s, INSN_VSLI, q, a0, a2, args[3] + (8 << vece)); 2963 return; 2964 2965 case INDEX_op_andc_vec: 2966 if (!const_args[2]) { 2967 tcg_out_vreg3(s, INSN_VBIC, q, 0, a0, a1, a2); 2968 return; 2969 } 2970 a2 = ~a2; 2971 /* fall through */ 2972 case INDEX_op_and_vec: 2973 if (const_args[2]) { 2974 is_shimm1632(~a2, &cmode, &imm8); 2975 if (a0 == a1) { 2976 tcg_out_vmovi(s, a0, q, 1, cmode | 1, imm8); /* VBICI */ 2977 return; 2978 } 2979 tcg_out_vmovi(s, a0, q, 1, cmode, imm8); /* VMVNI */ 2980 a2 = a0; 2981 } 2982 tcg_out_vreg3(s, INSN_VAND, q, 0, a0, a1, a2); 2983 return; 2984 2985 case INDEX_op_orc_vec: 2986 if (!const_args[2]) { 2987 tcg_out_vreg3(s, INSN_VORN, q, 0, a0, a1, a2); 2988 return; 2989 } 2990 a2 = ~a2; 2991 /* fall through */ 2992 case INDEX_op_or_vec: 2993 if (const_args[2]) { 2994 is_shimm1632(a2, &cmode, &imm8); 2995 if (a0 == a1) { 2996 tcg_out_vmovi(s, a0, q, 0, cmode | 1, imm8); /* VORRI */ 2997 return; 2998 } 2999 tcg_out_vmovi(s, a0, q, 0, cmode, imm8); /* VMOVI */ 3000 a2 = a0; 3001 } 3002 tcg_out_vreg3(s, INSN_VORR, q, 0, a0, a1, a2); 3003 return; 3004 3005 case INDEX_op_cmp_vec: 3006 { 3007 TCGCond cond = args[3]; 3008 ARMInsn insn; 3009 3010 switch (cond) { 3011 case TCG_COND_NE: 3012 if (const_args[2]) { 3013 tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a1); 3014 } else { 3015 tcg_out_vreg3(s, INSN_VCEQ, q, vece, a0, a1, a2); 3016 tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0); 3017 } 3018 break; 3019 3020 case TCG_COND_TSTNE: 3021 case TCG_COND_TSTEQ: 3022 if (const_args[2]) { 3023 /* (x & 0) == 0 */ 3024 tcg_out_dupi_vec(s, type, MO_8, a0, 3025 -(cond == TCG_COND_TSTEQ)); 3026 break; 3027 } 3028 tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a2); 3029 if (cond == TCG_COND_TSTEQ) { 3030 tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0); 3031 } 3032 break; 3033 3034 default: 3035 if (const_args[2]) { 3036 insn = vec_cmp0_insn[cond]; 3037 if (insn) { 3038 tcg_out_vreg2(s, insn, q, vece, a0, a1); 3039 return; 3040 } 3041 tcg_out_dupi_vec(s, type, MO_8, TCG_VEC_TMP, 0); 3042 a2 = TCG_VEC_TMP; 3043 } 3044 insn = vec_cmp_insn[cond]; 3045 if (insn == 0) { 3046 TCGArg t; 3047 t = a1, a1 = a2, a2 = t; 3048 cond = tcg_swap_cond(cond); 3049 insn = vec_cmp_insn[cond]; 3050 tcg_debug_assert(insn != 0); 3051 } 3052 tcg_out_vreg3(s, insn, q, vece, a0, a1, a2); 3053 break; 3054 } 3055 } 3056 return; 3057 3058 case INDEX_op_bitsel_vec: 3059 a3 = args[3]; 3060 if (a0 == a3) { 3061 tcg_out_vreg3(s, INSN_VBIT, q, 0, a0, a2, a1); 3062 } else if (a0 == a2) { 3063 tcg_out_vreg3(s, INSN_VBIF, q, 0, a0, a3, a1); 3064 } else { 3065 tcg_out_mov(s, type, a0, a1); 3066 tcg_out_vreg3(s, INSN_VBSL, q, 0, a0, a2, a3); 3067 } 3068 return; 3069 3070 case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ 3071 case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ 3072 default: 3073 g_assert_not_reached(); 3074 } 3075} 3076 3077int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 3078{ 3079 switch (opc) { 3080 case INDEX_op_add_vec: 3081 case INDEX_op_sub_vec: 3082 case INDEX_op_and_vec: 3083 case INDEX_op_andc_vec: 3084 case INDEX_op_or_vec: 3085 case INDEX_op_orc_vec: 3086 case INDEX_op_xor_vec: 3087 case INDEX_op_not_vec: 3088 case INDEX_op_shli_vec: 3089 case INDEX_op_shri_vec: 3090 case INDEX_op_sari_vec: 3091 case INDEX_op_ssadd_vec: 3092 case INDEX_op_sssub_vec: 3093 case INDEX_op_usadd_vec: 3094 case INDEX_op_ussub_vec: 3095 case INDEX_op_bitsel_vec: 3096 return 1; 3097 case INDEX_op_abs_vec: 3098 case INDEX_op_cmp_vec: 3099 case INDEX_op_mul_vec: 3100 case INDEX_op_neg_vec: 3101 case INDEX_op_smax_vec: 3102 case INDEX_op_smin_vec: 3103 case INDEX_op_umax_vec: 3104 case INDEX_op_umin_vec: 3105 return vece < MO_64; 3106 case INDEX_op_shlv_vec: 3107 case INDEX_op_shrv_vec: 3108 case INDEX_op_sarv_vec: 3109 case INDEX_op_rotli_vec: 3110 case INDEX_op_rotlv_vec: 3111 case INDEX_op_rotrv_vec: 3112 return -1; 3113 default: 3114 return 0; 3115 } 3116} 3117 3118void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 3119 TCGArg a0, ...) 3120{ 3121 va_list va; 3122 TCGv_vec v0, v1, v2, t1, t2, c1; 3123 TCGArg a2; 3124 3125 va_start(va, a0); 3126 v0 = temp_tcgv_vec(arg_temp(a0)); 3127 v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 3128 a2 = va_arg(va, TCGArg); 3129 va_end(va); 3130 3131 switch (opc) { 3132 case INDEX_op_shlv_vec: 3133 /* 3134 * Merely propagate shlv_vec to arm_ushl_vec. 3135 * In this way we don't set TCG_TARGET_HAS_shv_vec 3136 * because everything is done via expansion. 3137 */ 3138 v2 = temp_tcgv_vec(arg_temp(a2)); 3139 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0), 3140 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 3141 break; 3142 3143 case INDEX_op_shrv_vec: 3144 case INDEX_op_sarv_vec: 3145 /* Right shifts are negative left shifts for NEON. */ 3146 v2 = temp_tcgv_vec(arg_temp(a2)); 3147 t1 = tcg_temp_new_vec(type); 3148 tcg_gen_neg_vec(vece, t1, v2); 3149 if (opc == INDEX_op_shrv_vec) { 3150 opc = INDEX_op_arm_ushl_vec; 3151 } else { 3152 opc = INDEX_op_arm_sshl_vec; 3153 } 3154 vec_gen_3(opc, type, vece, tcgv_vec_arg(v0), 3155 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 3156 tcg_temp_free_vec(t1); 3157 break; 3158 3159 case INDEX_op_rotli_vec: 3160 t1 = tcg_temp_new_vec(type); 3161 tcg_gen_shri_vec(vece, t1, v1, -a2 & ((8 << vece) - 1)); 3162 vec_gen_4(INDEX_op_arm_sli_vec, type, vece, 3163 tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(v1), a2); 3164 tcg_temp_free_vec(t1); 3165 break; 3166 3167 case INDEX_op_rotlv_vec: 3168 v2 = temp_tcgv_vec(arg_temp(a2)); 3169 t1 = tcg_temp_new_vec(type); 3170 c1 = tcg_constant_vec(type, vece, 8 << vece); 3171 tcg_gen_sub_vec(vece, t1, v2, c1); 3172 /* Right shifts are negative left shifts for NEON. */ 3173 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1), 3174 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 3175 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0), 3176 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 3177 tcg_gen_or_vec(vece, v0, v0, t1); 3178 tcg_temp_free_vec(t1); 3179 break; 3180 3181 case INDEX_op_rotrv_vec: 3182 v2 = temp_tcgv_vec(arg_temp(a2)); 3183 t1 = tcg_temp_new_vec(type); 3184 t2 = tcg_temp_new_vec(type); 3185 c1 = tcg_constant_vec(type, vece, 8 << vece); 3186 tcg_gen_neg_vec(vece, t1, v2); 3187 tcg_gen_sub_vec(vece, t2, c1, v2); 3188 /* Right shifts are negative left shifts for NEON. */ 3189 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1), 3190 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 3191 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t2), 3192 tcgv_vec_arg(v1), tcgv_vec_arg(t2)); 3193 tcg_gen_or_vec(vece, v0, t1, t2); 3194 tcg_temp_free_vec(t1); 3195 tcg_temp_free_vec(t2); 3196 break; 3197 3198 default: 3199 g_assert_not_reached(); 3200 } 3201} 3202 3203static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 3204{ 3205 int i; 3206 for (i = 0; i < count; ++i) { 3207 p[i] = INSN_NOP; 3208 } 3209} 3210 3211/* Compute frame size via macros, to share between tcg_target_qemu_prologue 3212 and tcg_register_jit. */ 3213 3214#define PUSH_SIZE ((11 - 4 + 1 + 1) * sizeof(tcg_target_long)) 3215 3216#define FRAME_SIZE \ 3217 ((PUSH_SIZE \ 3218 + TCG_STATIC_CALL_ARGS_SIZE \ 3219 + CPU_TEMP_BUF_NLONGS * sizeof(long) \ 3220 + TCG_TARGET_STACK_ALIGN - 1) \ 3221 & -TCG_TARGET_STACK_ALIGN) 3222 3223#define STACK_ADDEND (FRAME_SIZE - PUSH_SIZE) 3224 3225static void tcg_target_qemu_prologue(TCGContext *s) 3226{ 3227 /* Calling convention requires us to save r4-r11 and lr. */ 3228 /* stmdb sp!, { r4 - r11, lr } */ 3229 tcg_out_ldstm(s, COND_AL, INSN_STMDB, TCG_REG_CALL_STACK, 3230 (1 << TCG_REG_R4) | (1 << TCG_REG_R5) | (1 << TCG_REG_R6) | 3231 (1 << TCG_REG_R7) | (1 << TCG_REG_R8) | (1 << TCG_REG_R9) | 3232 (1 << TCG_REG_R10) | (1 << TCG_REG_R11) | (1 << TCG_REG_R14)); 3233 3234 /* Reserve callee argument and tcg temp space. */ 3235 tcg_out_dat_rI(s, COND_AL, ARITH_SUB, TCG_REG_CALL_STACK, 3236 TCG_REG_CALL_STACK, STACK_ADDEND, 1); 3237 tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE, 3238 CPU_TEMP_BUF_NLONGS * sizeof(long)); 3239 3240 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 3241 3242 if (!tcg_use_softmmu && guest_base) { 3243 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_GUEST_BASE, guest_base); 3244 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GUEST_BASE); 3245 } 3246 3247 tcg_out_b_reg(s, COND_AL, tcg_target_call_iarg_regs[1]); 3248 3249 /* 3250 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 3251 * and fall through to the rest of the epilogue. 3252 */ 3253 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 3254 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, 0); 3255 tcg_out_epilogue(s); 3256} 3257 3258static void tcg_out_epilogue(TCGContext *s) 3259{ 3260 /* Release local stack frame. */ 3261 tcg_out_dat_rI(s, COND_AL, ARITH_ADD, TCG_REG_CALL_STACK, 3262 TCG_REG_CALL_STACK, STACK_ADDEND, 1); 3263 3264 /* ldmia sp!, { r4 - r11, pc } */ 3265 tcg_out_ldstm(s, COND_AL, INSN_LDMIA, TCG_REG_CALL_STACK, 3266 (1 << TCG_REG_R4) | (1 << TCG_REG_R5) | (1 << TCG_REG_R6) | 3267 (1 << TCG_REG_R7) | (1 << TCG_REG_R8) | (1 << TCG_REG_R9) | 3268 (1 << TCG_REG_R10) | (1 << TCG_REG_R11) | (1 << TCG_REG_PC)); 3269} 3270 3271static void tcg_out_tb_start(TCGContext *s) 3272{ 3273 /* nothing to do */ 3274} 3275 3276typedef struct { 3277 DebugFrameHeader h; 3278 uint8_t fde_def_cfa[4]; 3279 uint8_t fde_reg_ofs[18]; 3280} DebugFrame; 3281 3282#define ELF_HOST_MACHINE EM_ARM 3283 3284/* We're expecting a 2 byte uleb128 encoded value. */ 3285QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); 3286 3287static const DebugFrame debug_frame = { 3288 .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ 3289 .h.cie.id = -1, 3290 .h.cie.version = 1, 3291 .h.cie.code_align = 1, 3292 .h.cie.data_align = 0x7c, /* sleb128 -4 */ 3293 .h.cie.return_column = 14, 3294 3295 /* Total FDE size does not include the "len" member. */ 3296 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 3297 3298 .fde_def_cfa = { 3299 12, 13, /* DW_CFA_def_cfa sp, ... */ 3300 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 3301 (FRAME_SIZE >> 7) 3302 }, 3303 .fde_reg_ofs = { 3304 /* The following must match the stmdb in the prologue. */ 3305 0x8e, 1, /* DW_CFA_offset, lr, -4 */ 3306 0x8b, 2, /* DW_CFA_offset, r11, -8 */ 3307 0x8a, 3, /* DW_CFA_offset, r10, -12 */ 3308 0x89, 4, /* DW_CFA_offset, r9, -16 */ 3309 0x88, 5, /* DW_CFA_offset, r8, -20 */ 3310 0x87, 6, /* DW_CFA_offset, r7, -24 */ 3311 0x86, 7, /* DW_CFA_offset, r6, -28 */ 3312 0x85, 8, /* DW_CFA_offset, r5, -32 */ 3313 0x84, 9, /* DW_CFA_offset, r4, -36 */ 3314 } 3315}; 3316 3317void tcg_register_jit(const void *buf, size_t buf_size) 3318{ 3319 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 3320} 3321