1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Andrzej Zaborowski 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25#include "elf.h" 26 27int arm_arch = __ARM_ARCH; 28 29#ifndef use_idiv_instructions 30bool use_idiv_instructions; 31#endif 32#ifndef use_neon_instructions 33bool use_neon_instructions; 34#endif 35 36/* Used for function call generation. */ 37#define TCG_TARGET_STACK_ALIGN 8 38#define TCG_TARGET_CALL_STACK_OFFSET 0 39#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL 40#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN 41#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN 42#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF 43 44#ifdef CONFIG_DEBUG_TCG 45static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 46 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", 47 "%r8", "%r9", "%r10", "%r11", "%r12", "%sp", "%r14", "%pc", 48 "%q0", "%q1", "%q2", "%q3", "%q4", "%q5", "%q6", "%q7", 49 "%q8", "%q9", "%q10", "%q11", "%q12", "%q13", "%q14", "%q15", 50}; 51#endif 52 53static const int tcg_target_reg_alloc_order[] = { 54 TCG_REG_R4, 55 TCG_REG_R5, 56 TCG_REG_R6, 57 TCG_REG_R7, 58 TCG_REG_R8, 59 TCG_REG_R9, 60 TCG_REG_R10, 61 TCG_REG_R11, 62 TCG_REG_R13, 63 TCG_REG_R0, 64 TCG_REG_R1, 65 TCG_REG_R2, 66 TCG_REG_R3, 67 TCG_REG_R12, 68 TCG_REG_R14, 69 70 TCG_REG_Q0, 71 TCG_REG_Q1, 72 TCG_REG_Q2, 73 TCG_REG_Q3, 74 /* Q4 - Q7 are call-saved, and skipped. */ 75 TCG_REG_Q8, 76 TCG_REG_Q9, 77 TCG_REG_Q10, 78 TCG_REG_Q11, 79 TCG_REG_Q12, 80 TCG_REG_Q13, 81 TCG_REG_Q14, 82 TCG_REG_Q15, 83}; 84 85static const int tcg_target_call_iarg_regs[4] = { 86 TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3 87}; 88 89static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 90{ 91 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 92 tcg_debug_assert(slot >= 0 && slot <= 3); 93 return TCG_REG_R0 + slot; 94} 95 96#define TCG_REG_TMP TCG_REG_R12 97#define TCG_VEC_TMP TCG_REG_Q15 98#define TCG_REG_GUEST_BASE TCG_REG_R11 99 100typedef enum { 101 COND_EQ = 0x0, 102 COND_NE = 0x1, 103 COND_CS = 0x2, /* Unsigned greater or equal */ 104 COND_CC = 0x3, /* Unsigned less than */ 105 COND_MI = 0x4, /* Negative */ 106 COND_PL = 0x5, /* Zero or greater */ 107 COND_VS = 0x6, /* Overflow */ 108 COND_VC = 0x7, /* No overflow */ 109 COND_HI = 0x8, /* Unsigned greater than */ 110 COND_LS = 0x9, /* Unsigned less or equal */ 111 COND_GE = 0xa, 112 COND_LT = 0xb, 113 COND_GT = 0xc, 114 COND_LE = 0xd, 115 COND_AL = 0xe, 116} ARMCond; 117 118#define TO_CPSR (1 << 20) 119 120#define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00) 121#define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20) 122#define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40) 123#define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60) 124#define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10) 125#define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30) 126#define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50) 127#define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70) 128 129typedef enum { 130 ARITH_AND = 0x0 << 21, 131 ARITH_EOR = 0x1 << 21, 132 ARITH_SUB = 0x2 << 21, 133 ARITH_RSB = 0x3 << 21, 134 ARITH_ADD = 0x4 << 21, 135 ARITH_ADC = 0x5 << 21, 136 ARITH_SBC = 0x6 << 21, 137 ARITH_RSC = 0x7 << 21, 138 ARITH_TST = 0x8 << 21 | TO_CPSR, 139 ARITH_CMP = 0xa << 21 | TO_CPSR, 140 ARITH_CMN = 0xb << 21 | TO_CPSR, 141 ARITH_ORR = 0xc << 21, 142 ARITH_MOV = 0xd << 21, 143 ARITH_BIC = 0xe << 21, 144 ARITH_MVN = 0xf << 21, 145 146 INSN_B = 0x0a000000, 147 148 INSN_CLZ = 0x016f0f10, 149 INSN_RBIT = 0x06ff0f30, 150 151 INSN_LDMIA = 0x08b00000, 152 INSN_STMDB = 0x09200000, 153 154 INSN_LDR_IMM = 0x04100000, 155 INSN_LDR_REG = 0x06100000, 156 INSN_STR_IMM = 0x04000000, 157 INSN_STR_REG = 0x06000000, 158 159 INSN_LDRH_IMM = 0x005000b0, 160 INSN_LDRH_REG = 0x001000b0, 161 INSN_LDRSH_IMM = 0x005000f0, 162 INSN_LDRSH_REG = 0x001000f0, 163 INSN_STRH_IMM = 0x004000b0, 164 INSN_STRH_REG = 0x000000b0, 165 166 INSN_LDRB_IMM = 0x04500000, 167 INSN_LDRB_REG = 0x06500000, 168 INSN_LDRSB_IMM = 0x005000d0, 169 INSN_LDRSB_REG = 0x001000d0, 170 INSN_STRB_IMM = 0x04400000, 171 INSN_STRB_REG = 0x06400000, 172 173 INSN_LDRD_IMM = 0x004000d0, 174 INSN_LDRD_REG = 0x000000d0, 175 INSN_STRD_IMM = 0x004000f0, 176 INSN_STRD_REG = 0x000000f0, 177 178 INSN_DMB_ISH = 0xf57ff05b, 179 INSN_DMB_MCR = 0xee070fba, 180 181 /* Architected nop introduced in v6k. */ 182 /* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this 183 also Just So Happened to do nothing on pre-v6k so that we 184 don't need to conditionalize it? */ 185 INSN_NOP_v6k = 0xe320f000, 186 /* Otherwise the assembler uses mov r0,r0 */ 187 INSN_NOP_v4 = (COND_AL << 28) | ARITH_MOV, 188 189 INSN_VADD = 0xf2000800, 190 INSN_VAND = 0xf2000110, 191 INSN_VBIC = 0xf2100110, 192 INSN_VEOR = 0xf3000110, 193 INSN_VORN = 0xf2300110, 194 INSN_VORR = 0xf2200110, 195 INSN_VSUB = 0xf3000800, 196 INSN_VMUL = 0xf2000910, 197 INSN_VQADD = 0xf2000010, 198 INSN_VQADD_U = 0xf3000010, 199 INSN_VQSUB = 0xf2000210, 200 INSN_VQSUB_U = 0xf3000210, 201 INSN_VMAX = 0xf2000600, 202 INSN_VMAX_U = 0xf3000600, 203 INSN_VMIN = 0xf2000610, 204 INSN_VMIN_U = 0xf3000610, 205 206 INSN_VABS = 0xf3b10300, 207 INSN_VMVN = 0xf3b00580, 208 INSN_VNEG = 0xf3b10380, 209 210 INSN_VCEQ0 = 0xf3b10100, 211 INSN_VCGT0 = 0xf3b10000, 212 INSN_VCGE0 = 0xf3b10080, 213 INSN_VCLE0 = 0xf3b10180, 214 INSN_VCLT0 = 0xf3b10200, 215 216 INSN_VCEQ = 0xf3000810, 217 INSN_VCGE = 0xf2000310, 218 INSN_VCGT = 0xf2000300, 219 INSN_VCGE_U = 0xf3000310, 220 INSN_VCGT_U = 0xf3000300, 221 222 INSN_VSHLI = 0xf2800510, /* VSHL (immediate) */ 223 INSN_VSARI = 0xf2800010, /* VSHR.S */ 224 INSN_VSHRI = 0xf3800010, /* VSHR.U */ 225 INSN_VSLI = 0xf3800510, 226 INSN_VSHL_S = 0xf2000400, /* VSHL.S (register) */ 227 INSN_VSHL_U = 0xf3000400, /* VSHL.U (register) */ 228 229 INSN_VBSL = 0xf3100110, 230 INSN_VBIT = 0xf3200110, 231 INSN_VBIF = 0xf3300110, 232 233 INSN_VTST = 0xf2000810, 234 235 INSN_VDUP_G = 0xee800b10, /* VDUP (ARM core register) */ 236 INSN_VDUP_S = 0xf3b00c00, /* VDUP (scalar) */ 237 INSN_VLDR_D = 0xed100b00, /* VLDR.64 */ 238 INSN_VLD1 = 0xf4200000, /* VLD1 (multiple single elements) */ 239 INSN_VLD1R = 0xf4a00c00, /* VLD1 (single element to all lanes) */ 240 INSN_VST1 = 0xf4000000, /* VST1 (multiple single elements) */ 241 INSN_VMOVI = 0xf2800010, /* VMOV (immediate) */ 242} ARMInsn; 243 244#define INSN_NOP (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4) 245 246static const uint8_t tcg_cond_to_arm_cond[] = { 247 [TCG_COND_EQ] = COND_EQ, 248 [TCG_COND_NE] = COND_NE, 249 [TCG_COND_LT] = COND_LT, 250 [TCG_COND_GE] = COND_GE, 251 [TCG_COND_LE] = COND_LE, 252 [TCG_COND_GT] = COND_GT, 253 /* unsigned */ 254 [TCG_COND_LTU] = COND_CC, 255 [TCG_COND_GEU] = COND_CS, 256 [TCG_COND_LEU] = COND_LS, 257 [TCG_COND_GTU] = COND_HI, 258}; 259 260static int encode_imm(uint32_t imm); 261 262/* TCG private relocation type: add with pc+imm8 */ 263#define R_ARM_PC8 11 264 265/* TCG private relocation type: vldr with imm8 << 2 */ 266#define R_ARM_PC11 12 267 268static bool reloc_pc24(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 269{ 270 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 271 ptrdiff_t offset = (tcg_ptr_byte_diff(target, src_rx) - 8) >> 2; 272 273 if (offset == sextract32(offset, 0, 24)) { 274 *src_rw = deposit32(*src_rw, 0, 24, offset); 275 return true; 276 } 277 return false; 278} 279 280static bool reloc_pc13(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 281{ 282 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 283 ptrdiff_t offset = tcg_ptr_byte_diff(target, src_rx) - 8; 284 285 if (offset >= -0xfff && offset <= 0xfff) { 286 tcg_insn_unit insn = *src_rw; 287 bool u = (offset >= 0); 288 if (!u) { 289 offset = -offset; 290 } 291 insn = deposit32(insn, 23, 1, u); 292 insn = deposit32(insn, 0, 12, offset); 293 *src_rw = insn; 294 return true; 295 } 296 return false; 297} 298 299static bool reloc_pc11(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 300{ 301 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 302 ptrdiff_t offset = (tcg_ptr_byte_diff(target, src_rx) - 8) / 4; 303 304 if (offset >= -0xff && offset <= 0xff) { 305 tcg_insn_unit insn = *src_rw; 306 bool u = (offset >= 0); 307 if (!u) { 308 offset = -offset; 309 } 310 insn = deposit32(insn, 23, 1, u); 311 insn = deposit32(insn, 0, 8, offset); 312 *src_rw = insn; 313 return true; 314 } 315 return false; 316} 317 318static bool reloc_pc8(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 319{ 320 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 321 ptrdiff_t offset = tcg_ptr_byte_diff(target, src_rx) - 8; 322 int imm12 = encode_imm(offset); 323 324 if (imm12 >= 0) { 325 *src_rw = deposit32(*src_rw, 0, 12, imm12); 326 return true; 327 } 328 return false; 329} 330 331static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 332 intptr_t value, intptr_t addend) 333{ 334 tcg_debug_assert(addend == 0); 335 switch (type) { 336 case R_ARM_PC24: 337 return reloc_pc24(code_ptr, (const tcg_insn_unit *)value); 338 case R_ARM_PC13: 339 return reloc_pc13(code_ptr, (const tcg_insn_unit *)value); 340 case R_ARM_PC11: 341 return reloc_pc11(code_ptr, (const tcg_insn_unit *)value); 342 case R_ARM_PC8: 343 return reloc_pc8(code_ptr, (const tcg_insn_unit *)value); 344 default: 345 g_assert_not_reached(); 346 } 347} 348 349#define TCG_CT_CONST_ARM 0x100 350#define TCG_CT_CONST_INV 0x200 351#define TCG_CT_CONST_NEG 0x400 352#define TCG_CT_CONST_ZERO 0x800 353#define TCG_CT_CONST_ORRI 0x1000 354#define TCG_CT_CONST_ANDI 0x2000 355 356#define ALL_GENERAL_REGS 0xffffu 357#define ALL_VECTOR_REGS 0xffff0000u 358 359/* 360 * r0-r3 will be overwritten when reading the tlb entry (system-mode only); 361 * r14 will be overwritten by the BLNE branching to the slow path. 362 */ 363#define ALL_QLDST_REGS \ 364 (ALL_GENERAL_REGS & ~((tcg_use_softmmu ? 0xf : 0) | (1 << TCG_REG_R14))) 365 366/* 367 * ARM immediates for ALU instructions are made of an unsigned 8-bit 368 * right-rotated by an even amount between 0 and 30. 369 * 370 * Return < 0 if @imm cannot be encoded, else the entire imm12 field. 371 */ 372static int encode_imm(uint32_t imm) 373{ 374 uint32_t rot, imm8; 375 376 /* Simple case, no rotation required. */ 377 if ((imm & ~0xff) == 0) { 378 return imm; 379 } 380 381 /* Next, try a simple even shift. */ 382 rot = ctz32(imm) & ~1; 383 imm8 = imm >> rot; 384 rot = 32 - rot; 385 if ((imm8 & ~0xff) == 0) { 386 goto found; 387 } 388 389 /* 390 * Finally, try harder with rotations. 391 * The ctz test above will have taken care of rotates >= 8. 392 */ 393 for (rot = 2; rot < 8; rot += 2) { 394 imm8 = rol32(imm, rot); 395 if ((imm8 & ~0xff) == 0) { 396 goto found; 397 } 398 } 399 /* Fail: imm cannot be encoded. */ 400 return -1; 401 402 found: 403 /* Note that rot is even, and we discard bit 0 by shifting by 7. */ 404 return rot << 7 | imm8; 405} 406 407static int encode_imm_nofail(uint32_t imm) 408{ 409 int ret = encode_imm(imm); 410 tcg_debug_assert(ret >= 0); 411 return ret; 412} 413 414static bool check_fit_imm(uint32_t imm) 415{ 416 return encode_imm(imm) >= 0; 417} 418 419/* Return true if v16 is a valid 16-bit shifted immediate. */ 420static bool is_shimm16(uint16_t v16, int *cmode, int *imm8) 421{ 422 if (v16 == (v16 & 0xff)) { 423 *cmode = 0x8; 424 *imm8 = v16 & 0xff; 425 return true; 426 } else if (v16 == (v16 & 0xff00)) { 427 *cmode = 0xa; 428 *imm8 = v16 >> 8; 429 return true; 430 } 431 return false; 432} 433 434/* Return true if v32 is a valid 32-bit shifted immediate. */ 435static bool is_shimm32(uint32_t v32, int *cmode, int *imm8) 436{ 437 if (v32 == (v32 & 0xff)) { 438 *cmode = 0x0; 439 *imm8 = v32 & 0xff; 440 return true; 441 } else if (v32 == (v32 & 0xff00)) { 442 *cmode = 0x2; 443 *imm8 = (v32 >> 8) & 0xff; 444 return true; 445 } else if (v32 == (v32 & 0xff0000)) { 446 *cmode = 0x4; 447 *imm8 = (v32 >> 16) & 0xff; 448 return true; 449 } else if (v32 == (v32 & 0xff000000)) { 450 *cmode = 0x6; 451 *imm8 = v32 >> 24; 452 return true; 453 } 454 return false; 455} 456 457/* Return true if v32 is a valid 32-bit shifting ones immediate. */ 458static bool is_soimm32(uint32_t v32, int *cmode, int *imm8) 459{ 460 if ((v32 & 0xffff00ff) == 0xff) { 461 *cmode = 0xc; 462 *imm8 = (v32 >> 8) & 0xff; 463 return true; 464 } else if ((v32 & 0xff00ffff) == 0xffff) { 465 *cmode = 0xd; 466 *imm8 = (v32 >> 16) & 0xff; 467 return true; 468 } 469 return false; 470} 471 472/* 473 * Return non-zero if v32 can be formed by MOVI+ORR. 474 * Place the parameters for MOVI in (cmode, imm8). 475 * Return the cmode for ORR; the imm8 can be had via extraction from v32. 476 */ 477static int is_shimm32_pair(uint32_t v32, int *cmode, int *imm8) 478{ 479 int i; 480 481 for (i = 6; i > 0; i -= 2) { 482 /* Mask out one byte we can add with ORR. */ 483 uint32_t tmp = v32 & ~(0xffu << (i * 4)); 484 if (is_shimm32(tmp, cmode, imm8) || 485 is_soimm32(tmp, cmode, imm8)) { 486 break; 487 } 488 } 489 return i; 490} 491 492/* Return true if V is a valid 16-bit or 32-bit shifted immediate. */ 493static bool is_shimm1632(uint32_t v32, int *cmode, int *imm8) 494{ 495 if (v32 == deposit32(v32, 16, 16, v32)) { 496 return is_shimm16(v32, cmode, imm8); 497 } else { 498 return is_shimm32(v32, cmode, imm8); 499 } 500} 501 502/* Test if a constant matches the constraint. 503 * TODO: define constraints for: 504 * 505 * ldr/str offset: between -0xfff and 0xfff 506 * ldrh/strh offset: between -0xff and 0xff 507 * mov operand2: values represented with x << (2 * y), x < 0x100 508 * add, sub, eor...: ditto 509 */ 510static bool tcg_target_const_match(int64_t val, int ct, 511 TCGType type, TCGCond cond, int vece) 512{ 513 if (ct & TCG_CT_CONST) { 514 return 1; 515 } else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val)) { 516 return 1; 517 } else if ((ct & TCG_CT_CONST_INV) && check_fit_imm(~val)) { 518 return 1; 519 } else if ((ct & TCG_CT_CONST_NEG) && check_fit_imm(-val)) { 520 return 1; 521 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 522 return 1; 523 } 524 525 switch (ct & (TCG_CT_CONST_ORRI | TCG_CT_CONST_ANDI)) { 526 case 0: 527 break; 528 case TCG_CT_CONST_ANDI: 529 val = ~val; 530 /* fallthru */ 531 case TCG_CT_CONST_ORRI: 532 if (val == deposit64(val, 32, 32, val)) { 533 int cmode, imm8; 534 return is_shimm1632(val, &cmode, &imm8); 535 } 536 break; 537 default: 538 /* Both bits should not be set for the same insn. */ 539 g_assert_not_reached(); 540 } 541 542 return 0; 543} 544 545static void tcg_out_b_imm(TCGContext *s, ARMCond cond, int32_t offset) 546{ 547 tcg_out32(s, (cond << 28) | INSN_B | 548 (((offset - 8) >> 2) & 0x00ffffff)); 549} 550 551static void tcg_out_bl_imm(TCGContext *s, ARMCond cond, int32_t offset) 552{ 553 tcg_out32(s, (cond << 28) | 0x0b000000 | 554 (((offset - 8) >> 2) & 0x00ffffff)); 555} 556 557static void tcg_out_blx_reg(TCGContext *s, ARMCond cond, TCGReg rn) 558{ 559 tcg_out32(s, (cond << 28) | 0x012fff30 | rn); 560} 561 562static void tcg_out_blx_imm(TCGContext *s, int32_t offset) 563{ 564 tcg_out32(s, 0xfa000000 | ((offset & 2) << 23) | 565 (((offset - 8) >> 2) & 0x00ffffff)); 566} 567 568static void tcg_out_dat_reg(TCGContext *s, ARMCond cond, ARMInsn opc, 569 TCGReg rd, TCGReg rn, TCGReg rm, int shift) 570{ 571 tcg_out32(s, (cond << 28) | (0 << 25) | opc | 572 (rn << 16) | (rd << 12) | shift | rm); 573} 574 575static void tcg_out_mov_reg(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rm) 576{ 577 /* Simple reg-reg move, optimising out the 'do nothing' case */ 578 if (rd != rm) { 579 tcg_out_dat_reg(s, cond, ARITH_MOV, rd, 0, rm, SHIFT_IMM_LSL(0)); 580 } 581} 582 583static void tcg_out_bx_reg(TCGContext *s, ARMCond cond, TCGReg rn) 584{ 585 tcg_out32(s, (cond << 28) | 0x012fff10 | rn); 586} 587 588static void tcg_out_b_reg(TCGContext *s, ARMCond cond, TCGReg rn) 589{ 590 /* 591 * Unless the C portion of QEMU is compiled as thumb, we don't need 592 * true BX semantics; merely a branch to an address held in a register. 593 */ 594 tcg_out_bx_reg(s, cond, rn); 595} 596 597static void tcg_out_dat_imm(TCGContext *s, ARMCond cond, ARMInsn opc, 598 TCGReg rd, TCGReg rn, int im) 599{ 600 tcg_out32(s, (cond << 28) | (1 << 25) | opc | 601 (rn << 16) | (rd << 12) | im); 602} 603 604static void tcg_out_ldstm(TCGContext *s, ARMCond cond, ARMInsn opc, 605 TCGReg rn, uint16_t mask) 606{ 607 tcg_out32(s, (cond << 28) | opc | (rn << 16) | mask); 608} 609 610/* Note that this routine is used for both LDR and LDRH formats, so we do 611 not wish to include an immediate shift at this point. */ 612static void tcg_out_memop_r(TCGContext *s, ARMCond cond, ARMInsn opc, TCGReg rt, 613 TCGReg rn, TCGReg rm, bool u, bool p, bool w) 614{ 615 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) 616 | (w << 21) | (rn << 16) | (rt << 12) | rm); 617} 618 619static void tcg_out_memop_8(TCGContext *s, ARMCond cond, ARMInsn opc, TCGReg rt, 620 TCGReg rn, int imm8, bool p, bool w) 621{ 622 bool u = 1; 623 if (imm8 < 0) { 624 imm8 = -imm8; 625 u = 0; 626 } 627 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | 628 (rn << 16) | (rt << 12) | ((imm8 & 0xf0) << 4) | (imm8 & 0xf)); 629} 630 631static void tcg_out_memop_12(TCGContext *s, ARMCond cond, ARMInsn opc, 632 TCGReg rt, TCGReg rn, int imm12, bool p, bool w) 633{ 634 bool u = 1; 635 if (imm12 < 0) { 636 imm12 = -imm12; 637 u = 0; 638 } 639 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | 640 (rn << 16) | (rt << 12) | imm12); 641} 642 643static void tcg_out_ld32_12(TCGContext *s, ARMCond cond, TCGReg rt, 644 TCGReg rn, int imm12) 645{ 646 tcg_out_memop_12(s, cond, INSN_LDR_IMM, rt, rn, imm12, 1, 0); 647} 648 649static void tcg_out_st32_12(TCGContext *s, ARMCond cond, TCGReg rt, 650 TCGReg rn, int imm12) 651{ 652 tcg_out_memop_12(s, cond, INSN_STR_IMM, rt, rn, imm12, 1, 0); 653} 654 655static void tcg_out_ld32_r(TCGContext *s, ARMCond cond, TCGReg rt, 656 TCGReg rn, TCGReg rm) 657{ 658 tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 0); 659} 660 661static void tcg_out_st32_r(TCGContext *s, ARMCond cond, TCGReg rt, 662 TCGReg rn, TCGReg rm) 663{ 664 tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 0); 665} 666 667static void tcg_out_ldrd_8(TCGContext *s, ARMCond cond, TCGReg rt, 668 TCGReg rn, int imm8) 669{ 670 tcg_out_memop_8(s, cond, INSN_LDRD_IMM, rt, rn, imm8, 1, 0); 671} 672 673static void tcg_out_ldrd_r(TCGContext *s, ARMCond cond, TCGReg rt, 674 TCGReg rn, TCGReg rm) 675{ 676 tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 0); 677} 678 679static void tcg_out_strd_8(TCGContext *s, ARMCond cond, TCGReg rt, 680 TCGReg rn, int imm8) 681{ 682 tcg_out_memop_8(s, cond, INSN_STRD_IMM, rt, rn, imm8, 1, 0); 683} 684 685static void tcg_out_strd_r(TCGContext *s, ARMCond cond, TCGReg rt, 686 TCGReg rn, TCGReg rm) 687{ 688 tcg_out_memop_r(s, cond, INSN_STRD_REG, rt, rn, rm, 1, 1, 0); 689} 690 691/* Register pre-increment with base writeback. */ 692static void tcg_out_ld32_rwb(TCGContext *s, ARMCond cond, TCGReg rt, 693 TCGReg rn, TCGReg rm) 694{ 695 tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 1); 696} 697 698static void tcg_out_st32_rwb(TCGContext *s, ARMCond cond, TCGReg rt, 699 TCGReg rn, TCGReg rm) 700{ 701 tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 1); 702} 703 704static void tcg_out_ld16u_8(TCGContext *s, ARMCond cond, TCGReg rt, 705 TCGReg rn, int imm8) 706{ 707 tcg_out_memop_8(s, cond, INSN_LDRH_IMM, rt, rn, imm8, 1, 0); 708} 709 710static void tcg_out_st16_8(TCGContext *s, ARMCond cond, TCGReg rt, 711 TCGReg rn, int imm8) 712{ 713 tcg_out_memop_8(s, cond, INSN_STRH_IMM, rt, rn, imm8, 1, 0); 714} 715 716static void tcg_out_ld16u_r(TCGContext *s, ARMCond cond, TCGReg rt, 717 TCGReg rn, TCGReg rm) 718{ 719 tcg_out_memop_r(s, cond, INSN_LDRH_REG, rt, rn, rm, 1, 1, 0); 720} 721 722static void tcg_out_st16_r(TCGContext *s, ARMCond cond, TCGReg rt, 723 TCGReg rn, TCGReg rm) 724{ 725 tcg_out_memop_r(s, cond, INSN_STRH_REG, rt, rn, rm, 1, 1, 0); 726} 727 728static void tcg_out_ld16s_8(TCGContext *s, ARMCond cond, TCGReg rt, 729 TCGReg rn, int imm8) 730{ 731 tcg_out_memop_8(s, cond, INSN_LDRSH_IMM, rt, rn, imm8, 1, 0); 732} 733 734static void tcg_out_ld16s_r(TCGContext *s, ARMCond cond, TCGReg rt, 735 TCGReg rn, TCGReg rm) 736{ 737 tcg_out_memop_r(s, cond, INSN_LDRSH_REG, rt, rn, rm, 1, 1, 0); 738} 739 740static void tcg_out_ld8_12(TCGContext *s, ARMCond cond, TCGReg rt, 741 TCGReg rn, int imm12) 742{ 743 tcg_out_memop_12(s, cond, INSN_LDRB_IMM, rt, rn, imm12, 1, 0); 744} 745 746static void tcg_out_st8_12(TCGContext *s, ARMCond cond, TCGReg rt, 747 TCGReg rn, int imm12) 748{ 749 tcg_out_memop_12(s, cond, INSN_STRB_IMM, rt, rn, imm12, 1, 0); 750} 751 752static void tcg_out_ld8_r(TCGContext *s, ARMCond cond, TCGReg rt, 753 TCGReg rn, TCGReg rm) 754{ 755 tcg_out_memop_r(s, cond, INSN_LDRB_REG, rt, rn, rm, 1, 1, 0); 756} 757 758static void tcg_out_st8_r(TCGContext *s, ARMCond cond, TCGReg rt, 759 TCGReg rn, TCGReg rm) 760{ 761 tcg_out_memop_r(s, cond, INSN_STRB_REG, rt, rn, rm, 1, 1, 0); 762} 763 764static void tcg_out_ld8s_8(TCGContext *s, ARMCond cond, TCGReg rt, 765 TCGReg rn, int imm8) 766{ 767 tcg_out_memop_8(s, cond, INSN_LDRSB_IMM, rt, rn, imm8, 1, 0); 768} 769 770static void tcg_out_ld8s_r(TCGContext *s, ARMCond cond, TCGReg rt, 771 TCGReg rn, TCGReg rm) 772{ 773 tcg_out_memop_r(s, cond, INSN_LDRSB_REG, rt, rn, rm, 1, 1, 0); 774} 775 776static void tcg_out_movi_pool(TCGContext *s, ARMCond cond, 777 TCGReg rd, uint32_t arg) 778{ 779 new_pool_label(s, arg, R_ARM_PC13, s->code_ptr, 0); 780 tcg_out_ld32_12(s, cond, rd, TCG_REG_PC, 0); 781} 782 783static void tcg_out_movi32(TCGContext *s, ARMCond cond, 784 TCGReg rd, uint32_t arg) 785{ 786 int imm12, diff, opc, sh1, sh2; 787 uint32_t tt0, tt1, tt2; 788 789 /* Check a single MOV/MVN before anything else. */ 790 imm12 = encode_imm(arg); 791 if (imm12 >= 0) { 792 tcg_out_dat_imm(s, cond, ARITH_MOV, rd, 0, imm12); 793 return; 794 } 795 imm12 = encode_imm(~arg); 796 if (imm12 >= 0) { 797 tcg_out_dat_imm(s, cond, ARITH_MVN, rd, 0, imm12); 798 return; 799 } 800 801 /* Check for a pc-relative address. This will usually be the TB, 802 or within the TB, which is immediately before the code block. */ 803 diff = tcg_pcrel_diff(s, (void *)arg) - 8; 804 if (diff >= 0) { 805 imm12 = encode_imm(diff); 806 if (imm12 >= 0) { 807 tcg_out_dat_imm(s, cond, ARITH_ADD, rd, TCG_REG_PC, imm12); 808 return; 809 } 810 } else { 811 imm12 = encode_imm(-diff); 812 if (imm12 >= 0) { 813 tcg_out_dat_imm(s, cond, ARITH_SUB, rd, TCG_REG_PC, imm12); 814 return; 815 } 816 } 817 818 /* Use movw + movt. */ 819 if (use_armv7_instructions) { 820 /* movw */ 821 tcg_out32(s, (cond << 28) | 0x03000000 | (rd << 12) 822 | ((arg << 4) & 0x000f0000) | (arg & 0xfff)); 823 if (arg & 0xffff0000) { 824 /* movt */ 825 tcg_out32(s, (cond << 28) | 0x03400000 | (rd << 12) 826 | ((arg >> 12) & 0x000f0000) | ((arg >> 16) & 0xfff)); 827 } 828 return; 829 } 830 831 /* Look for sequences of two insns. If we have lots of 1's, we can 832 shorten the sequence by beginning with mvn and then clearing 833 higher bits with eor. */ 834 tt0 = arg; 835 opc = ARITH_MOV; 836 if (ctpop32(arg) > 16) { 837 tt0 = ~arg; 838 opc = ARITH_MVN; 839 } 840 sh1 = ctz32(tt0) & ~1; 841 tt1 = tt0 & ~(0xff << sh1); 842 sh2 = ctz32(tt1) & ~1; 843 tt2 = tt1 & ~(0xff << sh2); 844 if (tt2 == 0) { 845 int rot; 846 847 rot = ((32 - sh1) << 7) & 0xf00; 848 tcg_out_dat_imm(s, cond, opc, rd, 0, ((tt0 >> sh1) & 0xff) | rot); 849 rot = ((32 - sh2) << 7) & 0xf00; 850 tcg_out_dat_imm(s, cond, ARITH_EOR, rd, rd, 851 ((tt0 >> sh2) & 0xff) | rot); 852 return; 853 } 854 855 /* Otherwise, drop it into the constant pool. */ 856 tcg_out_movi_pool(s, cond, rd, arg); 857} 858 859/* 860 * Emit either the reg,imm or reg,reg form of a data-processing insn. 861 * rhs must satisfy the "rI" constraint. 862 */ 863static void tcg_out_dat_rI(TCGContext *s, ARMCond cond, ARMInsn opc, 864 TCGReg dst, TCGReg lhs, TCGArg rhs, int rhs_is_const) 865{ 866 if (rhs_is_const) { 867 tcg_out_dat_imm(s, cond, opc, dst, lhs, encode_imm_nofail(rhs)); 868 } else { 869 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); 870 } 871} 872 873/* 874 * Emit either the reg,imm or reg,reg form of a data-processing insn. 875 * rhs must satisfy the "rIK" constraint. 876 */ 877static void tcg_out_dat_IK(TCGContext *s, ARMCond cond, ARMInsn opc, 878 ARMInsn opinv, TCGReg dst, TCGReg lhs, TCGArg rhs) 879{ 880 int imm12 = encode_imm(rhs); 881 if (imm12 < 0) { 882 imm12 = encode_imm_nofail(~rhs); 883 opc = opinv; 884 } 885 tcg_out_dat_imm(s, cond, opc, dst, lhs, imm12); 886} 887 888static void tcg_out_dat_rIK(TCGContext *s, ARMCond cond, ARMInsn opc, 889 ARMInsn opinv, TCGReg dst, TCGReg lhs, TCGArg rhs, 890 bool rhs_is_const) 891{ 892 if (rhs_is_const) { 893 tcg_out_dat_IK(s, cond, opc, opinv, dst, lhs, rhs); 894 } else { 895 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); 896 } 897} 898 899static void tcg_out_dat_IN(TCGContext *s, ARMCond cond, ARMInsn opc, 900 ARMInsn opneg, TCGReg dst, TCGReg lhs, TCGArg rhs) 901{ 902 int imm12 = encode_imm(rhs); 903 if (imm12 < 0) { 904 imm12 = encode_imm_nofail(-rhs); 905 opc = opneg; 906 } 907 tcg_out_dat_imm(s, cond, opc, dst, lhs, imm12); 908} 909 910static void tcg_out_dat_rIN(TCGContext *s, ARMCond cond, ARMInsn opc, 911 ARMInsn opneg, TCGReg dst, TCGReg lhs, TCGArg rhs, 912 bool rhs_is_const) 913{ 914 /* Emit either the reg,imm or reg,reg form of a data-processing insn. 915 * rhs must satisfy the "rIN" constraint. 916 */ 917 if (rhs_is_const) { 918 tcg_out_dat_IN(s, cond, opc, opneg, dst, lhs, rhs); 919 } else { 920 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); 921 } 922} 923 924static void tcg_out_umull32(TCGContext *s, ARMCond cond, TCGReg rd0, 925 TCGReg rd1, TCGReg rn, TCGReg rm) 926{ 927 /* umull */ 928 tcg_out32(s, (cond << 28) | 0x00800090 | 929 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); 930} 931 932static void tcg_out_smull32(TCGContext *s, ARMCond cond, TCGReg rd0, 933 TCGReg rd1, TCGReg rn, TCGReg rm) 934{ 935 /* smull */ 936 tcg_out32(s, (cond << 28) | 0x00c00090 | 937 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); 938} 939 940static void tcg_out_ext8s(TCGContext *s, TCGType t, TCGReg rd, TCGReg rn) 941{ 942 /* sxtb */ 943 tcg_out32(s, 0x06af0070 | (COND_AL << 28) | (rd << 12) | rn); 944} 945 946static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rn) 947{ 948 tcg_out_dat_imm(s, COND_AL, ARITH_AND, rd, rn, 0xff); 949} 950 951static void tcg_out_ext16s(TCGContext *s, TCGType t, TCGReg rd, TCGReg rn) 952{ 953 /* sxth */ 954 tcg_out32(s, 0x06bf0070 | (COND_AL << 28) | (rd << 12) | rn); 955} 956 957static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rn) 958{ 959 /* uxth */ 960 tcg_out32(s, 0x06ff0070 | (COND_AL << 28) | (rd << 12) | rn); 961} 962 963static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rn) 964{ 965 g_assert_not_reached(); 966} 967 968static void tcg_out_ext32u(TCGContext *s, TCGReg rd, TCGReg rn) 969{ 970 g_assert_not_reached(); 971} 972 973static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rn) 974{ 975 g_assert_not_reached(); 976} 977 978static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rn) 979{ 980 g_assert_not_reached(); 981} 982 983static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rn) 984{ 985 g_assert_not_reached(); 986} 987 988static void tcg_out_bswap16(TCGContext *s, ARMCond cond, 989 TCGReg rd, TCGReg rn, int flags) 990{ 991 if (flags & TCG_BSWAP_OS) { 992 /* revsh */ 993 tcg_out32(s, 0x06ff0fb0 | (cond << 28) | (rd << 12) | rn); 994 return; 995 } 996 997 /* rev16 */ 998 tcg_out32(s, 0x06bf0fb0 | (cond << 28) | (rd << 12) | rn); 999 if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 1000 /* uxth */ 1001 tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | rd); 1002 } 1003} 1004 1005static void tcg_out_bswap32(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rn) 1006{ 1007 /* rev */ 1008 tcg_out32(s, 0x06bf0f30 | (cond << 28) | (rd << 12) | rn); 1009} 1010 1011static void tcg_out_deposit(TCGContext *s, ARMCond cond, TCGReg rd, 1012 TCGArg a1, int ofs, int len, bool const_a1) 1013{ 1014 if (const_a1) { 1015 /* bfi becomes bfc with rn == 15. */ 1016 a1 = 15; 1017 } 1018 /* bfi/bfc */ 1019 tcg_out32(s, 0x07c00010 | (cond << 28) | (rd << 12) | a1 1020 | (ofs << 7) | ((ofs + len - 1) << 16)); 1021} 1022 1023static void tcg_out_extract(TCGContext *s, ARMCond cond, TCGReg rd, 1024 TCGReg rn, int ofs, int len) 1025{ 1026 /* According to gcc, AND can be faster. */ 1027 if (ofs == 0 && len <= 8) { 1028 tcg_out_dat_imm(s, cond, ARITH_AND, rd, rn, 1029 encode_imm_nofail((1 << len) - 1)); 1030 return; 1031 } 1032 1033 if (use_armv7_instructions) { 1034 /* ubfx */ 1035 tcg_out32(s, 0x07e00050 | (cond << 28) | (rd << 12) | rn 1036 | (ofs << 7) | ((len - 1) << 16)); 1037 return; 1038 } 1039 1040 assert(ofs % 8 == 0); 1041 switch (len) { 1042 case 8: 1043 /* uxtb */ 1044 tcg_out32(s, 0x06ef0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn); 1045 break; 1046 case 16: 1047 /* uxth */ 1048 tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn); 1049 break; 1050 default: 1051 g_assert_not_reached(); 1052 } 1053} 1054 1055static void tcg_out_sextract(TCGContext *s, ARMCond cond, TCGReg rd, 1056 TCGReg rn, int ofs, int len) 1057{ 1058 if (use_armv7_instructions) { 1059 /* sbfx */ 1060 tcg_out32(s, 0x07a00050 | (cond << 28) | (rd << 12) | rn 1061 | (ofs << 7) | ((len - 1) << 16)); 1062 return; 1063 } 1064 1065 assert(ofs % 8 == 0); 1066 switch (len) { 1067 case 8: 1068 /* sxtb */ 1069 tcg_out32(s, 0x06af0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn); 1070 break; 1071 case 16: 1072 /* sxth */ 1073 tcg_out32(s, 0x06bf0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn); 1074 break; 1075 default: 1076 g_assert_not_reached(); 1077 } 1078} 1079 1080 1081static void tcg_out_ld32u(TCGContext *s, ARMCond cond, 1082 TCGReg rd, TCGReg rn, int32_t offset) 1083{ 1084 if (offset > 0xfff || offset < -0xfff) { 1085 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1086 tcg_out_ld32_r(s, cond, rd, rn, TCG_REG_TMP); 1087 } else 1088 tcg_out_ld32_12(s, cond, rd, rn, offset); 1089} 1090 1091static void tcg_out_st32(TCGContext *s, ARMCond cond, 1092 TCGReg rd, TCGReg rn, int32_t offset) 1093{ 1094 if (offset > 0xfff || offset < -0xfff) { 1095 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1096 tcg_out_st32_r(s, cond, rd, rn, TCG_REG_TMP); 1097 } else 1098 tcg_out_st32_12(s, cond, rd, rn, offset); 1099} 1100 1101static void tcg_out_ld16u(TCGContext *s, ARMCond cond, 1102 TCGReg rd, TCGReg rn, int32_t offset) 1103{ 1104 if (offset > 0xff || offset < -0xff) { 1105 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1106 tcg_out_ld16u_r(s, cond, rd, rn, TCG_REG_TMP); 1107 } else 1108 tcg_out_ld16u_8(s, cond, rd, rn, offset); 1109} 1110 1111static void tcg_out_ld16s(TCGContext *s, ARMCond cond, 1112 TCGReg rd, TCGReg rn, int32_t offset) 1113{ 1114 if (offset > 0xff || offset < -0xff) { 1115 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1116 tcg_out_ld16s_r(s, cond, rd, rn, TCG_REG_TMP); 1117 } else 1118 tcg_out_ld16s_8(s, cond, rd, rn, offset); 1119} 1120 1121static void tcg_out_st16(TCGContext *s, ARMCond cond, 1122 TCGReg rd, TCGReg rn, int32_t offset) 1123{ 1124 if (offset > 0xff || offset < -0xff) { 1125 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1126 tcg_out_st16_r(s, cond, rd, rn, TCG_REG_TMP); 1127 } else 1128 tcg_out_st16_8(s, cond, rd, rn, offset); 1129} 1130 1131static void tcg_out_ld8u(TCGContext *s, ARMCond cond, 1132 TCGReg rd, TCGReg rn, int32_t offset) 1133{ 1134 if (offset > 0xfff || offset < -0xfff) { 1135 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1136 tcg_out_ld8_r(s, cond, rd, rn, TCG_REG_TMP); 1137 } else 1138 tcg_out_ld8_12(s, cond, rd, rn, offset); 1139} 1140 1141static void tcg_out_ld8s(TCGContext *s, ARMCond cond, 1142 TCGReg rd, TCGReg rn, int32_t offset) 1143{ 1144 if (offset > 0xff || offset < -0xff) { 1145 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1146 tcg_out_ld8s_r(s, cond, rd, rn, TCG_REG_TMP); 1147 } else 1148 tcg_out_ld8s_8(s, cond, rd, rn, offset); 1149} 1150 1151static void tcg_out_st8(TCGContext *s, ARMCond cond, 1152 TCGReg rd, TCGReg rn, int32_t offset) 1153{ 1154 if (offset > 0xfff || offset < -0xfff) { 1155 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1156 tcg_out_st8_r(s, cond, rd, rn, TCG_REG_TMP); 1157 } else 1158 tcg_out_st8_12(s, cond, rd, rn, offset); 1159} 1160 1161/* 1162 * The _goto case is normally between TBs within the same code buffer, and 1163 * with the code buffer limited to 16MB we wouldn't need the long case. 1164 * But we also use it for the tail-call to the qemu_ld/st helpers, which does. 1165 */ 1166static void tcg_out_goto(TCGContext *s, ARMCond cond, const tcg_insn_unit *addr) 1167{ 1168 intptr_t addri = (intptr_t)addr; 1169 ptrdiff_t disp = tcg_pcrel_diff(s, addr); 1170 bool arm_mode = !(addri & 1); 1171 1172 if (arm_mode && disp - 8 < 0x01fffffd && disp - 8 > -0x01fffffd) { 1173 tcg_out_b_imm(s, cond, disp); 1174 return; 1175 } 1176 1177 /* LDR is interworking from v5t. */ 1178 tcg_out_movi_pool(s, cond, TCG_REG_PC, addri); 1179} 1180 1181/* 1182 * The call case is mostly used for helpers - so it's not unreasonable 1183 * for them to be beyond branch range. 1184 */ 1185static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *addr) 1186{ 1187 intptr_t addri = (intptr_t)addr; 1188 ptrdiff_t disp = tcg_pcrel_diff(s, addr); 1189 bool arm_mode = !(addri & 1); 1190 1191 if (disp - 8 < 0x02000000 && disp - 8 >= -0x02000000) { 1192 if (arm_mode) { 1193 tcg_out_bl_imm(s, COND_AL, disp); 1194 } else { 1195 tcg_out_blx_imm(s, disp); 1196 } 1197 return; 1198 } 1199 1200 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri); 1201 tcg_out_blx_reg(s, COND_AL, TCG_REG_TMP); 1202} 1203 1204static void tcg_out_call(TCGContext *s, const tcg_insn_unit *addr, 1205 const TCGHelperInfo *info) 1206{ 1207 tcg_out_call_int(s, addr); 1208} 1209 1210static void tcg_out_goto_label(TCGContext *s, ARMCond cond, TCGLabel *l) 1211{ 1212 if (l->has_value) { 1213 tcg_out_goto(s, cond, l->u.value_ptr); 1214 } else { 1215 tcg_out_reloc(s, s->code_ptr, R_ARM_PC24, l, 0); 1216 tcg_out_b_imm(s, cond, 0); 1217 } 1218} 1219 1220static void tcg_out_mb(TCGContext *s, TCGArg a0) 1221{ 1222 if (use_armv7_instructions) { 1223 tcg_out32(s, INSN_DMB_ISH); 1224 } else { 1225 tcg_out32(s, INSN_DMB_MCR); 1226 } 1227} 1228 1229static TCGCond tcg_out_cmp(TCGContext *s, TCGCond cond, TCGReg a, 1230 TCGArg b, int b_const) 1231{ 1232 if (!is_tst_cond(cond)) { 1233 tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, a, b, b_const); 1234 return cond; 1235 } 1236 1237 cond = tcg_tst_eqne_cond(cond); 1238 if (b_const) { 1239 int imm12 = encode_imm(b); 1240 1241 /* 1242 * The compare constraints allow rIN, but TST does not support N. 1243 * Be prepared to load the constant into a scratch register. 1244 */ 1245 if (imm12 >= 0) { 1246 tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, a, imm12); 1247 return cond; 1248 } 1249 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, b); 1250 b = TCG_REG_TMP; 1251 } 1252 tcg_out_dat_reg(s, COND_AL, ARITH_TST, 0, a, b, SHIFT_IMM_LSL(0)); 1253 return cond; 1254} 1255 1256static TCGCond tcg_out_cmp2(TCGContext *s, const TCGArg *args, 1257 const int *const_args) 1258{ 1259 TCGReg al = args[0]; 1260 TCGReg ah = args[1]; 1261 TCGArg bl = args[2]; 1262 TCGArg bh = args[3]; 1263 TCGCond cond = args[4]; 1264 int const_bl = const_args[2]; 1265 int const_bh = const_args[3]; 1266 1267 switch (cond) { 1268 case TCG_COND_EQ: 1269 case TCG_COND_NE: 1270 case TCG_COND_LTU: 1271 case TCG_COND_LEU: 1272 case TCG_COND_GTU: 1273 case TCG_COND_GEU: 1274 /* 1275 * We perform a conditional comparison. If the high half is 1276 * equal, then overwrite the flags with the comparison of the 1277 * low half. The resulting flags cover the whole. 1278 */ 1279 tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, ah, bh, const_bh); 1280 tcg_out_dat_rI(s, COND_EQ, ARITH_CMP, 0, al, bl, const_bl); 1281 return cond; 1282 1283 case TCG_COND_TSTEQ: 1284 case TCG_COND_TSTNE: 1285 /* Similar, but with TST instead of CMP. */ 1286 tcg_out_dat_rI(s, COND_AL, ARITH_TST, 0, ah, bh, const_bh); 1287 tcg_out_dat_rI(s, COND_EQ, ARITH_TST, 0, al, bl, const_bl); 1288 return tcg_tst_eqne_cond(cond); 1289 1290 case TCG_COND_LT: 1291 case TCG_COND_GE: 1292 /* We perform a double-word subtraction and examine the result. 1293 We do not actually need the result of the subtract, so the 1294 low part "subtract" is a compare. For the high half we have 1295 no choice but to compute into a temporary. */ 1296 tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, al, bl, const_bl); 1297 tcg_out_dat_rI(s, COND_AL, ARITH_SBC | TO_CPSR, 1298 TCG_REG_TMP, ah, bh, const_bh); 1299 return cond; 1300 1301 case TCG_COND_LE: 1302 case TCG_COND_GT: 1303 /* Similar, but with swapped arguments, via reversed subtract. */ 1304 tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR, 1305 TCG_REG_TMP, al, bl, const_bl); 1306 tcg_out_dat_rI(s, COND_AL, ARITH_RSC | TO_CPSR, 1307 TCG_REG_TMP, ah, bh, const_bh); 1308 return tcg_swap_cond(cond); 1309 1310 default: 1311 g_assert_not_reached(); 1312 } 1313} 1314 1315/* 1316 * Note that TCGReg references Q-registers. 1317 * Q-regno = 2 * D-regno, so shift left by 1 while inserting. 1318 */ 1319static uint32_t encode_vd(TCGReg rd) 1320{ 1321 tcg_debug_assert(rd >= TCG_REG_Q0); 1322 return (extract32(rd, 3, 1) << 22) | (extract32(rd, 0, 3) << 13); 1323} 1324 1325static uint32_t encode_vn(TCGReg rn) 1326{ 1327 tcg_debug_assert(rn >= TCG_REG_Q0); 1328 return (extract32(rn, 3, 1) << 7) | (extract32(rn, 0, 3) << 17); 1329} 1330 1331static uint32_t encode_vm(TCGReg rm) 1332{ 1333 tcg_debug_assert(rm >= TCG_REG_Q0); 1334 return (extract32(rm, 3, 1) << 5) | (extract32(rm, 0, 3) << 1); 1335} 1336 1337static void tcg_out_vreg2(TCGContext *s, ARMInsn insn, int q, int vece, 1338 TCGReg d, TCGReg m) 1339{ 1340 tcg_out32(s, insn | (vece << 18) | (q << 6) | 1341 encode_vd(d) | encode_vm(m)); 1342} 1343 1344static void tcg_out_vreg3(TCGContext *s, ARMInsn insn, int q, int vece, 1345 TCGReg d, TCGReg n, TCGReg m) 1346{ 1347 tcg_out32(s, insn | (vece << 20) | (q << 6) | 1348 encode_vd(d) | encode_vn(n) | encode_vm(m)); 1349} 1350 1351static void tcg_out_vmovi(TCGContext *s, TCGReg rd, 1352 int q, int op, int cmode, uint8_t imm8) 1353{ 1354 tcg_out32(s, INSN_VMOVI | encode_vd(rd) | (q << 6) | (op << 5) 1355 | (cmode << 8) | extract32(imm8, 0, 4) 1356 | (extract32(imm8, 4, 3) << 16) 1357 | (extract32(imm8, 7, 1) << 24)); 1358} 1359 1360static void tcg_out_vshifti(TCGContext *s, ARMInsn insn, int q, 1361 TCGReg rd, TCGReg rm, int l_imm6) 1362{ 1363 tcg_out32(s, insn | (q << 6) | encode_vd(rd) | encode_vm(rm) | 1364 (extract32(l_imm6, 6, 1) << 7) | 1365 (extract32(l_imm6, 0, 6) << 16)); 1366} 1367 1368static void tcg_out_vldst(TCGContext *s, ARMInsn insn, 1369 TCGReg rd, TCGReg rn, int offset) 1370{ 1371 if (offset != 0) { 1372 if (check_fit_imm(offset) || check_fit_imm(-offset)) { 1373 tcg_out_dat_rIN(s, COND_AL, ARITH_ADD, ARITH_SUB, 1374 TCG_REG_TMP, rn, offset, true); 1375 } else { 1376 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, offset); 1377 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, 1378 TCG_REG_TMP, TCG_REG_TMP, rn, 0); 1379 } 1380 rn = TCG_REG_TMP; 1381 } 1382 tcg_out32(s, insn | (rn << 16) | encode_vd(rd) | 0xf); 1383} 1384 1385typedef struct { 1386 ARMCond cond; 1387 TCGReg base; 1388 int index; 1389 bool index_scratch; 1390 TCGAtomAlign aa; 1391} HostAddress; 1392 1393bool tcg_target_has_memory_bswap(MemOp memop) 1394{ 1395 return false; 1396} 1397 1398static TCGReg ldst_ra_gen(TCGContext *s, const TCGLabelQemuLdst *l, int arg) 1399{ 1400 /* We arrive at the slow path via "BLNE", so R14 contains l->raddr. */ 1401 return TCG_REG_R14; 1402} 1403 1404static const TCGLdstHelperParam ldst_helper_param = { 1405 .ra_gen = ldst_ra_gen, 1406 .ntmp = 1, 1407 .tmp = { TCG_REG_TMP }, 1408}; 1409 1410static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1411{ 1412 MemOp opc = get_memop(lb->oi); 1413 1414 if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1415 return false; 1416 } 1417 1418 tcg_out_ld_helper_args(s, lb, &ldst_helper_param); 1419 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE]); 1420 tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param); 1421 1422 tcg_out_goto(s, COND_AL, lb->raddr); 1423 return true; 1424} 1425 1426static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1427{ 1428 MemOp opc = get_memop(lb->oi); 1429 1430 if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1431 return false; 1432 } 1433 1434 tcg_out_st_helper_args(s, lb, &ldst_helper_param); 1435 1436 /* Tail-call to the helper, which will return to the fast path. */ 1437 tcg_out_goto(s, COND_AL, qemu_st_helpers[opc & MO_SIZE]); 1438 return true; 1439} 1440 1441/* We expect to use an 9-bit sign-magnitude negative offset from ENV. */ 1442#define MIN_TLB_MASK_TABLE_OFS -256 1443 1444static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1445 TCGReg addr, MemOpIdx oi, bool is_ld) 1446{ 1447 TCGLabelQemuLdst *ldst = NULL; 1448 MemOp opc = get_memop(oi); 1449 unsigned a_mask; 1450 1451 if (tcg_use_softmmu) { 1452 *h = (HostAddress){ 1453 .cond = COND_AL, 1454 .base = addr, 1455 .index = TCG_REG_R1, 1456 .index_scratch = true, 1457 }; 1458 } else { 1459 *h = (HostAddress){ 1460 .cond = COND_AL, 1461 .base = addr, 1462 .index = guest_base ? TCG_REG_GUEST_BASE : -1, 1463 .index_scratch = false, 1464 }; 1465 } 1466 1467 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); 1468 a_mask = (1 << h->aa.align) - 1; 1469 1470 if (tcg_use_softmmu) { 1471 int mem_index = get_mmuidx(oi); 1472 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read) 1473 : offsetof(CPUTLBEntry, addr_write); 1474 int fast_off = tlb_mask_table_ofs(s, mem_index); 1475 unsigned s_mask = (1 << (opc & MO_SIZE)) - 1; 1476 TCGReg t_addr; 1477 1478 ldst = new_ldst_label(s); 1479 ldst->is_ld = is_ld; 1480 ldst->oi = oi; 1481 ldst->addr_reg = addr; 1482 1483 /* Load cpu->neg.tlb.f[mmu_idx].{mask,table} into {r0,r1}. */ 1484 QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0); 1485 QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != 4); 1486 tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off); 1487 1488 /* Extract the tlb index from the address into R0. */ 1489 tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, addr, 1490 SHIFT_IMM_LSR(s->page_bits - CPU_TLB_ENTRY_BITS)); 1491 1492 /* 1493 * Add the tlb_table pointer, creating the CPUTLBEntry address in R1. 1494 * Load the tlb comparator into R2 and the fast path addend into R1. 1495 */ 1496 if (cmp_off == 0) { 1497 tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0); 1498 } else { 1499 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, 1500 TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0); 1501 tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); 1502 } 1503 1504 /* Load the tlb addend. */ 1505 tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R1, 1506 offsetof(CPUTLBEntry, addend)); 1507 1508 /* 1509 * Check alignment, check comparators. 1510 * Do this in 2-4 insns. Use MOVW for v7, if possible, 1511 * to reduce the number of sequential conditional instructions. 1512 * Almost all guests have at least 4k pages, which means that we need 1513 * to clear at least 9 bits even for an 8-byte memory, which means it 1514 * isn't worth checking for an immediate operand for BIC. 1515 * 1516 * For unaligned accesses, test the page of the last unit of alignment. 1517 * This leaves the least significant alignment bits unchanged, and of 1518 * course must be zero. 1519 */ 1520 t_addr = addr; 1521 if (a_mask < s_mask) { 1522 t_addr = TCG_REG_R0; 1523 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, t_addr, 1524 addr, s_mask - a_mask); 1525 } 1526 if (use_armv7_instructions && s->page_bits <= 16) { 1527 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, ~(s->page_mask | a_mask)); 1528 tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP, 1529 t_addr, TCG_REG_TMP, 0); 1530 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, 1531 TCG_REG_R2, TCG_REG_TMP, 0); 1532 } else { 1533 if (a_mask) { 1534 tcg_debug_assert(a_mask <= 0xff); 1535 tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addr, a_mask); 1536 } 1537 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, t_addr, 1538 SHIFT_IMM_LSR(s->page_bits)); 1539 tcg_out_dat_reg(s, (a_mask ? COND_EQ : COND_AL), ARITH_CMP, 1540 0, TCG_REG_R2, TCG_REG_TMP, 1541 SHIFT_IMM_LSL(s->page_bits)); 1542 } 1543 } else if (a_mask) { 1544 ldst = new_ldst_label(s); 1545 ldst->is_ld = is_ld; 1546 ldst->oi = oi; 1547 ldst->addr_reg = addr; 1548 1549 /* We are expecting alignment to max out at 7 */ 1550 tcg_debug_assert(a_mask <= 0xff); 1551 /* tst addr, #mask */ 1552 tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addr, a_mask); 1553 } 1554 1555 return ldst; 1556} 1557 1558static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo, 1559 TCGReg datahi, HostAddress h) 1560{ 1561 TCGReg base; 1562 1563 /* Byte swapping is left to middle-end expansion. */ 1564 tcg_debug_assert((opc & MO_BSWAP) == 0); 1565 1566 switch (opc & MO_SSIZE) { 1567 case MO_UB: 1568 if (h.index < 0) { 1569 tcg_out_ld8_12(s, h.cond, datalo, h.base, 0); 1570 } else { 1571 tcg_out_ld8_r(s, h.cond, datalo, h.base, h.index); 1572 } 1573 break; 1574 case MO_SB: 1575 if (h.index < 0) { 1576 tcg_out_ld8s_8(s, h.cond, datalo, h.base, 0); 1577 } else { 1578 tcg_out_ld8s_r(s, h.cond, datalo, h.base, h.index); 1579 } 1580 break; 1581 case MO_UW: 1582 if (h.index < 0) { 1583 tcg_out_ld16u_8(s, h.cond, datalo, h.base, 0); 1584 } else { 1585 tcg_out_ld16u_r(s, h.cond, datalo, h.base, h.index); 1586 } 1587 break; 1588 case MO_SW: 1589 if (h.index < 0) { 1590 tcg_out_ld16s_8(s, h.cond, datalo, h.base, 0); 1591 } else { 1592 tcg_out_ld16s_r(s, h.cond, datalo, h.base, h.index); 1593 } 1594 break; 1595 case MO_UL: 1596 if (h.index < 0) { 1597 tcg_out_ld32_12(s, h.cond, datalo, h.base, 0); 1598 } else { 1599 tcg_out_ld32_r(s, h.cond, datalo, h.base, h.index); 1600 } 1601 break; 1602 case MO_UQ: 1603 /* We used pair allocation for datalo, so already should be aligned. */ 1604 tcg_debug_assert((datalo & 1) == 0); 1605 tcg_debug_assert(datahi == datalo + 1); 1606 /* LDRD requires alignment; double-check that. */ 1607 if (memop_alignment_bits(opc) >= MO_64) { 1608 if (h.index < 0) { 1609 tcg_out_ldrd_8(s, h.cond, datalo, h.base, 0); 1610 break; 1611 } 1612 /* 1613 * Rm (the second address op) must not overlap Rt or Rt + 1. 1614 * Since datalo is aligned, we can simplify the test via alignment. 1615 * Flip the two address arguments if that works. 1616 */ 1617 if ((h.index & ~1) != datalo) { 1618 tcg_out_ldrd_r(s, h.cond, datalo, h.base, h.index); 1619 break; 1620 } 1621 if ((h.base & ~1) != datalo) { 1622 tcg_out_ldrd_r(s, h.cond, datalo, h.index, h.base); 1623 break; 1624 } 1625 } 1626 if (h.index < 0) { 1627 base = h.base; 1628 if (datalo == h.base) { 1629 tcg_out_mov_reg(s, h.cond, TCG_REG_TMP, base); 1630 base = TCG_REG_TMP; 1631 } 1632 } else if (h.index_scratch) { 1633 tcg_out_ld32_rwb(s, h.cond, datalo, h.index, h.base); 1634 tcg_out_ld32_12(s, h.cond, datahi, h.index, 4); 1635 break; 1636 } else { 1637 tcg_out_dat_reg(s, h.cond, ARITH_ADD, TCG_REG_TMP, 1638 h.base, h.index, SHIFT_IMM_LSL(0)); 1639 base = TCG_REG_TMP; 1640 } 1641 tcg_out_ld32_12(s, h.cond, datalo, base, 0); 1642 tcg_out_ld32_12(s, h.cond, datahi, base, 4); 1643 break; 1644 default: 1645 g_assert_not_reached(); 1646 } 1647} 1648 1649static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, 1650 TCGReg addr, MemOpIdx oi, TCGType data_type) 1651{ 1652 MemOp opc = get_memop(oi); 1653 TCGLabelQemuLdst *ldst; 1654 HostAddress h; 1655 1656 ldst = prepare_host_addr(s, &h, addr, oi, true); 1657 if (ldst) { 1658 ldst->type = data_type; 1659 ldst->datalo_reg = datalo; 1660 ldst->datahi_reg = datahi; 1661 1662 /* 1663 * This a conditional BL only to load a pointer within this 1664 * opcode into LR for the slow path. We will not be using 1665 * the value for a tail call. 1666 */ 1667 ldst->label_ptr[0] = s->code_ptr; 1668 tcg_out_bl_imm(s, COND_NE, 0); 1669 1670 tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); 1671 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1672 } else { 1673 tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); 1674 } 1675} 1676 1677static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo, 1678 TCGReg datahi, HostAddress h) 1679{ 1680 /* Byte swapping is left to middle-end expansion. */ 1681 tcg_debug_assert((opc & MO_BSWAP) == 0); 1682 1683 switch (opc & MO_SIZE) { 1684 case MO_8: 1685 if (h.index < 0) { 1686 tcg_out_st8_12(s, h.cond, datalo, h.base, 0); 1687 } else { 1688 tcg_out_st8_r(s, h.cond, datalo, h.base, h.index); 1689 } 1690 break; 1691 case MO_16: 1692 if (h.index < 0) { 1693 tcg_out_st16_8(s, h.cond, datalo, h.base, 0); 1694 } else { 1695 tcg_out_st16_r(s, h.cond, datalo, h.base, h.index); 1696 } 1697 break; 1698 case MO_32: 1699 if (h.index < 0) { 1700 tcg_out_st32_12(s, h.cond, datalo, h.base, 0); 1701 } else { 1702 tcg_out_st32_r(s, h.cond, datalo, h.base, h.index); 1703 } 1704 break; 1705 case MO_64: 1706 /* We used pair allocation for datalo, so already should be aligned. */ 1707 tcg_debug_assert((datalo & 1) == 0); 1708 tcg_debug_assert(datahi == datalo + 1); 1709 /* STRD requires alignment; double-check that. */ 1710 if (memop_alignment_bits(opc) >= MO_64) { 1711 if (h.index < 0) { 1712 tcg_out_strd_8(s, h.cond, datalo, h.base, 0); 1713 } else { 1714 tcg_out_strd_r(s, h.cond, datalo, h.base, h.index); 1715 } 1716 } else if (h.index < 0) { 1717 tcg_out_st32_12(s, h.cond, datalo, h.base, 0); 1718 tcg_out_st32_12(s, h.cond, datahi, h.base, 4); 1719 } else if (h.index_scratch) { 1720 tcg_out_st32_rwb(s, h.cond, datalo, h.index, h.base); 1721 tcg_out_st32_12(s, h.cond, datahi, h.index, 4); 1722 } else { 1723 tcg_out_dat_reg(s, h.cond, ARITH_ADD, TCG_REG_TMP, 1724 h.base, h.index, SHIFT_IMM_LSL(0)); 1725 tcg_out_st32_12(s, h.cond, datalo, TCG_REG_TMP, 0); 1726 tcg_out_st32_12(s, h.cond, datahi, TCG_REG_TMP, 4); 1727 } 1728 break; 1729 default: 1730 g_assert_not_reached(); 1731 } 1732} 1733 1734static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, 1735 TCGReg addr, MemOpIdx oi, TCGType data_type) 1736{ 1737 MemOp opc = get_memop(oi); 1738 TCGLabelQemuLdst *ldst; 1739 HostAddress h; 1740 1741 ldst = prepare_host_addr(s, &h, addr, oi, false); 1742 if (ldst) { 1743 ldst->type = data_type; 1744 ldst->datalo_reg = datalo; 1745 ldst->datahi_reg = datahi; 1746 1747 h.cond = COND_EQ; 1748 tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); 1749 1750 /* The conditional call is last, as we're going to return here. */ 1751 ldst->label_ptr[0] = s->code_ptr; 1752 tcg_out_bl_imm(s, COND_NE, 0); 1753 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1754 } else { 1755 tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); 1756 } 1757} 1758 1759static void tcg_out_epilogue(TCGContext *s); 1760 1761static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg) 1762{ 1763 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, arg); 1764 tcg_out_epilogue(s); 1765} 1766 1767static void tcg_out_goto_tb(TCGContext *s, int which) 1768{ 1769 uintptr_t i_addr; 1770 intptr_t i_disp; 1771 1772 /* Direct branch will be patched by tb_target_set_jmp_target. */ 1773 set_jmp_insn_offset(s, which); 1774 tcg_out32(s, INSN_NOP); 1775 1776 /* When branch is out of range, fall through to indirect. */ 1777 i_addr = get_jmp_target_addr(s, which); 1778 i_disp = tcg_pcrel_diff(s, (void *)i_addr) - 8; 1779 tcg_debug_assert(i_disp < 0); 1780 if (i_disp >= -0xfff) { 1781 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, i_disp); 1782 } else { 1783 /* 1784 * The TB is close, but outside the 12 bits addressable by 1785 * the load. We can extend this to 20 bits with a sub of a 1786 * shifted immediate from pc. 1787 */ 1788 int h = -i_disp; 1789 int l = -(h & 0xfff); 1790 1791 h = encode_imm_nofail(h + l); 1792 tcg_out_dat_imm(s, COND_AL, ARITH_SUB, TCG_REG_R0, TCG_REG_PC, h); 1793 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_R0, l); 1794 } 1795 set_jmp_reset_offset(s, which); 1796} 1797 1798void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1799 uintptr_t jmp_rx, uintptr_t jmp_rw) 1800{ 1801 uintptr_t addr = tb->jmp_target_addr[n]; 1802 ptrdiff_t offset = addr - (jmp_rx + 8); 1803 tcg_insn_unit insn; 1804 1805 /* Either directly branch, or fall through to indirect branch. */ 1806 if (offset == sextract64(offset, 0, 26)) { 1807 /* B <addr> */ 1808 insn = deposit32((COND_AL << 28) | INSN_B, 0, 24, offset >> 2); 1809 } else { 1810 insn = INSN_NOP; 1811 } 1812 1813 qatomic_set((uint32_t *)jmp_rw, insn); 1814 flush_idcache_range(jmp_rx, jmp_rw, 4); 1815} 1816 1817 1818static void tgen_add(TCGContext *s, TCGType type, 1819 TCGReg a0, TCGReg a1, TCGReg a2) 1820{ 1821 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, a0, a1, a2, SHIFT_IMM_LSL(0)); 1822} 1823 1824static void tgen_addi(TCGContext *s, TCGType type, 1825 TCGReg a0, TCGReg a1, tcg_target_long a2) 1826{ 1827 tcg_out_dat_IN(s, COND_AL, ARITH_ADD, ARITH_SUB, a0, a1, a2); 1828} 1829 1830static const TCGOutOpBinary outop_add = { 1831 .base.static_constraint = C_O1_I2(r, r, rIN), 1832 .out_rrr = tgen_add, 1833 .out_rri = tgen_addi, 1834}; 1835 1836static void tgen_and(TCGContext *s, TCGType type, 1837 TCGReg a0, TCGReg a1, TCGReg a2) 1838{ 1839 tcg_out_dat_reg(s, COND_AL, ARITH_AND, a0, a1, a2, SHIFT_IMM_LSL(0)); 1840} 1841 1842static void tgen_andi(TCGContext *s, TCGType type, 1843 TCGReg a0, TCGReg a1, tcg_target_long a2) 1844{ 1845 tcg_out_dat_IK(s, COND_AL, ARITH_AND, ARITH_BIC, a0, a1, a2); 1846} 1847 1848static const TCGOutOpBinary outop_and = { 1849 .base.static_constraint = C_O1_I2(r, r, rIK), 1850 .out_rrr = tgen_and, 1851 .out_rri = tgen_andi, 1852}; 1853 1854static void tgen_andc(TCGContext *s, TCGType type, 1855 TCGReg a0, TCGReg a1, TCGReg a2) 1856{ 1857 tcg_out_dat_reg(s, COND_AL, ARITH_BIC, a0, a1, a2, SHIFT_IMM_LSL(0)); 1858} 1859 1860static const TCGOutOpBinary outop_andc = { 1861 .base.static_constraint = C_O1_I2(r, r, r), 1862 .out_rrr = tgen_andc, 1863}; 1864 1865static void tgen_clz(TCGContext *s, TCGType type, 1866 TCGReg a0, TCGReg a1, TCGReg a2) 1867{ 1868 tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0, a1, 0); 1869 tcg_out_dat_reg(s, COND_NE, INSN_CLZ, a0, 0, a1, 0); 1870 tcg_out_mov_reg(s, COND_EQ, a0, a2); 1871} 1872 1873static void tgen_clzi(TCGContext *s, TCGType type, 1874 TCGReg a0, TCGReg a1, tcg_target_long a2) 1875{ 1876 if (a2 == 32) { 1877 tcg_out_dat_reg(s, COND_AL, INSN_CLZ, a0, 0, a1, 0); 1878 } else { 1879 tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0, a1, 0); 1880 tcg_out_dat_reg(s, COND_NE, INSN_CLZ, a0, 0, a1, 0); 1881 tcg_out_movi32(s, COND_EQ, a0, a2); 1882 } 1883} 1884 1885static const TCGOutOpBinary outop_clz = { 1886 .base.static_constraint = C_O1_I2(r, r, rIK), 1887 .out_rrr = tgen_clz, 1888 .out_rri = tgen_clzi, 1889}; 1890 1891static void tgen_ctz(TCGContext *s, TCGType type, 1892 TCGReg a0, TCGReg a1, TCGReg a2) 1893{ 1894 tcg_out_dat_reg(s, COND_AL, INSN_RBIT, TCG_REG_TMP, 0, a1, 0); 1895 tgen_clz(s, TCG_TYPE_I32, a0, TCG_REG_TMP, a2); 1896} 1897 1898static void tgen_ctzi(TCGContext *s, TCGType type, 1899 TCGReg a0, TCGReg a1, tcg_target_long a2) 1900{ 1901 tcg_out_dat_reg(s, COND_AL, INSN_RBIT, TCG_REG_TMP, 0, a1, 0); 1902 tgen_clzi(s, TCG_TYPE_I32, a0, TCG_REG_TMP, a2); 1903} 1904 1905static TCGConstraintSetIndex cset_ctz(TCGType type, unsigned flags) 1906{ 1907 return use_armv7_instructions ? C_O1_I2(r, r, rIK) : C_NotImplemented; 1908} 1909 1910static const TCGOutOpBinary outop_ctz = { 1911 .base.static_constraint = C_Dynamic, 1912 .base.dynamic_constraint = cset_ctz, 1913 .out_rrr = tgen_ctz, 1914 .out_rri = tgen_ctzi, 1915}; 1916 1917static TCGConstraintSetIndex cset_idiv(TCGType type, unsigned flags) 1918{ 1919 return use_idiv_instructions ? C_O1_I2(r, r, r) : C_NotImplemented; 1920} 1921 1922static void tgen_divs(TCGContext *s, TCGType type, 1923 TCGReg a0, TCGReg a1, TCGReg a2) 1924{ 1925 /* sdiv */ 1926 tcg_out32(s, 0x0710f010 | (COND_AL << 28) | (a0 << 16) | a1 | (a2 << 8)); 1927} 1928 1929static const TCGOutOpBinary outop_divs = { 1930 .base.static_constraint = C_Dynamic, 1931 .base.dynamic_constraint = cset_idiv, 1932 .out_rrr = tgen_divs, 1933}; 1934 1935static const TCGOutOpDivRem outop_divs2 = { 1936 .base.static_constraint = C_NotImplemented, 1937}; 1938 1939static void tgen_divu(TCGContext *s, TCGType type, 1940 TCGReg a0, TCGReg a1, TCGReg a2) 1941{ 1942 /* udiv */ 1943 tcg_out32(s, 0x0730f010 | (COND_AL << 28) | (a0 << 16) | a1 | (a2 << 8)); 1944} 1945 1946static const TCGOutOpBinary outop_divu = { 1947 .base.static_constraint = C_Dynamic, 1948 .base.dynamic_constraint = cset_idiv, 1949 .out_rrr = tgen_divu, 1950}; 1951 1952static const TCGOutOpDivRem outop_divu2 = { 1953 .base.static_constraint = C_NotImplemented, 1954}; 1955 1956static const TCGOutOpBinary outop_eqv = { 1957 .base.static_constraint = C_NotImplemented, 1958}; 1959 1960static void tgen_mul(TCGContext *s, TCGType type, 1961 TCGReg a0, TCGReg a1, TCGReg a2) 1962{ 1963 /* mul */ 1964 tcg_out32(s, (COND_AL << 28) | 0x90 | (a0 << 16) | (a1 << 8) | a2); 1965} 1966 1967static const TCGOutOpBinary outop_mul = { 1968 .base.static_constraint = C_O1_I2(r, r, r), 1969 .out_rrr = tgen_mul, 1970}; 1971 1972static const TCGOutOpBinary outop_mulsh = { 1973 .base.static_constraint = C_NotImplemented, 1974}; 1975 1976static const TCGOutOpBinary outop_muluh = { 1977 .base.static_constraint = C_NotImplemented, 1978}; 1979 1980static const TCGOutOpBinary outop_nand = { 1981 .base.static_constraint = C_NotImplemented, 1982}; 1983 1984static const TCGOutOpBinary outop_nor = { 1985 .base.static_constraint = C_NotImplemented, 1986}; 1987 1988static void tgen_or(TCGContext *s, TCGType type, 1989 TCGReg a0, TCGReg a1, TCGReg a2) 1990{ 1991 tcg_out_dat_reg(s, COND_AL, ARITH_ORR, a0, a1, a2, SHIFT_IMM_LSL(0)); 1992} 1993 1994static void tgen_ori(TCGContext *s, TCGType type, 1995 TCGReg a0, TCGReg a1, tcg_target_long a2) 1996{ 1997 tcg_out_dat_imm(s, COND_AL, ARITH_ORR, a0, a1, encode_imm_nofail(a2)); 1998} 1999 2000static const TCGOutOpBinary outop_or = { 2001 .base.static_constraint = C_O1_I2(r, r, rI), 2002 .out_rrr = tgen_or, 2003 .out_rri = tgen_ori, 2004}; 2005 2006static const TCGOutOpBinary outop_orc = { 2007 .base.static_constraint = C_NotImplemented, 2008}; 2009 2010static const TCGOutOpBinary outop_rems = { 2011 .base.static_constraint = C_NotImplemented, 2012}; 2013 2014static const TCGOutOpBinary outop_remu = { 2015 .base.static_constraint = C_NotImplemented, 2016}; 2017 2018static const TCGOutOpBinary outop_rotl = { 2019 .base.static_constraint = C_NotImplemented, 2020}; 2021 2022static void tgen_rotr(TCGContext *s, TCGType type, 2023 TCGReg a0, TCGReg a1, TCGReg a2) 2024{ 2025 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, SHIFT_REG_ROR(a2)); 2026} 2027 2028static void tgen_rotri(TCGContext *s, TCGType type, 2029 TCGReg a0, TCGReg a1, tcg_target_long a2) 2030{ 2031 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, SHIFT_IMM_ROR(a2 & 0x1f)); 2032} 2033 2034static const TCGOutOpBinary outop_rotr = { 2035 .base.static_constraint = C_O1_I2(r, r, ri), 2036 .out_rrr = tgen_rotr, 2037 .out_rri = tgen_rotri, 2038}; 2039 2040static void tgen_sar(TCGContext *s, TCGType type, 2041 TCGReg a0, TCGReg a1, TCGReg a2) 2042{ 2043 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, SHIFT_REG_ASR(a2)); 2044} 2045 2046static void tgen_sari(TCGContext *s, TCGType type, 2047 TCGReg a0, TCGReg a1, tcg_target_long a2) 2048{ 2049 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, 2050 SHIFT_IMM_ASR(a2 & 0x1f)); 2051} 2052 2053static const TCGOutOpBinary outop_sar = { 2054 .base.static_constraint = C_O1_I2(r, r, ri), 2055 .out_rrr = tgen_sar, 2056 .out_rri = tgen_sari, 2057}; 2058 2059static void tgen_shl(TCGContext *s, TCGType type, 2060 TCGReg a0, TCGReg a1, TCGReg a2) 2061{ 2062 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, SHIFT_REG_LSL(a2)); 2063} 2064 2065static void tgen_shli(TCGContext *s, TCGType type, 2066 TCGReg a0, TCGReg a1, tcg_target_long a2) 2067{ 2068 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, 2069 SHIFT_IMM_LSL(a2 & 0x1f)); 2070} 2071 2072static const TCGOutOpBinary outop_shl = { 2073 .base.static_constraint = C_O1_I2(r, r, ri), 2074 .out_rrr = tgen_shl, 2075 .out_rri = tgen_shli, 2076}; 2077 2078static void tgen_shr(TCGContext *s, TCGType type, 2079 TCGReg a0, TCGReg a1, TCGReg a2) 2080{ 2081 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, SHIFT_REG_LSR(a2)); 2082} 2083 2084static void tgen_shri(TCGContext *s, TCGType type, 2085 TCGReg a0, TCGReg a1, tcg_target_long a2) 2086{ 2087 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, 2088 SHIFT_IMM_LSR(a2 & 0x1f)); 2089} 2090 2091static const TCGOutOpBinary outop_shr = { 2092 .base.static_constraint = C_O1_I2(r, r, ri), 2093 .out_rrr = tgen_shr, 2094 .out_rri = tgen_shri, 2095}; 2096 2097static void tgen_sub(TCGContext *s, TCGType type, 2098 TCGReg a0, TCGReg a1, TCGReg a2) 2099{ 2100 tcg_out_dat_reg(s, COND_AL, ARITH_SUB, a0, a1, a2, SHIFT_IMM_LSL(0)); 2101} 2102 2103static void tgen_subfi(TCGContext *s, TCGType type, 2104 TCGReg a0, tcg_target_long a1, TCGReg a2) 2105{ 2106 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, a0, a2, encode_imm_nofail(a1)); 2107} 2108 2109static const TCGOutOpSubtract outop_sub = { 2110 .base.static_constraint = C_O1_I2(r, rI, r), 2111 .out_rrr = tgen_sub, 2112 .out_rir = tgen_subfi, 2113}; 2114 2115static void tgen_xor(TCGContext *s, TCGType type, 2116 TCGReg a0, TCGReg a1, TCGReg a2) 2117{ 2118 tcg_out_dat_reg(s, COND_AL, ARITH_EOR, a0, a1, a2, SHIFT_IMM_LSL(0)); 2119} 2120 2121static void tgen_xori(TCGContext *s, TCGType type, 2122 TCGReg a0, TCGReg a1, tcg_target_long a2) 2123{ 2124 tcg_out_dat_imm(s, COND_AL, ARITH_EOR, a0, a1, encode_imm_nofail(a2)); 2125} 2126 2127static const TCGOutOpBinary outop_xor = { 2128 .base.static_constraint = C_O1_I2(r, r, rI), 2129 .out_rrr = tgen_xor, 2130 .out_rri = tgen_xori, 2131}; 2132 2133static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2134{ 2135 tgen_subfi(s, type, a0, 0, a1); 2136} 2137 2138static const TCGOutOpUnary outop_neg = { 2139 .base.static_constraint = C_O1_I1(r, r), 2140 .out_rr = tgen_neg, 2141}; 2142 2143static void tgen_not(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2144{ 2145 tcg_out_dat_reg(s, COND_AL, ARITH_MVN, a0, 0, a1, SHIFT_IMM_LSL(0)); 2146} 2147 2148static const TCGOutOpUnary outop_not = { 2149 .base.static_constraint = C_O1_I1(r, r), 2150 .out_rr = tgen_not, 2151}; 2152 2153 2154static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, 2155 const TCGArg args[TCG_MAX_OP_ARGS], 2156 const int const_args[TCG_MAX_OP_ARGS]) 2157{ 2158 TCGArg a0, a1, a2, a3, a4, a5; 2159 int c; 2160 2161 switch (opc) { 2162 case INDEX_op_goto_ptr: 2163 tcg_out_b_reg(s, COND_AL, args[0]); 2164 break; 2165 case INDEX_op_br: 2166 tcg_out_goto_label(s, COND_AL, arg_label(args[0])); 2167 break; 2168 2169 case INDEX_op_ld8u_i32: 2170 tcg_out_ld8u(s, COND_AL, args[0], args[1], args[2]); 2171 break; 2172 case INDEX_op_ld8s_i32: 2173 tcg_out_ld8s(s, COND_AL, args[0], args[1], args[2]); 2174 break; 2175 case INDEX_op_ld16u_i32: 2176 tcg_out_ld16u(s, COND_AL, args[0], args[1], args[2]); 2177 break; 2178 case INDEX_op_ld16s_i32: 2179 tcg_out_ld16s(s, COND_AL, args[0], args[1], args[2]); 2180 break; 2181 case INDEX_op_ld_i32: 2182 tcg_out_ld32u(s, COND_AL, args[0], args[1], args[2]); 2183 break; 2184 case INDEX_op_st8_i32: 2185 tcg_out_st8(s, COND_AL, args[0], args[1], args[2]); 2186 break; 2187 case INDEX_op_st16_i32: 2188 tcg_out_st16(s, COND_AL, args[0], args[1], args[2]); 2189 break; 2190 case INDEX_op_st_i32: 2191 tcg_out_st32(s, COND_AL, args[0], args[1], args[2]); 2192 break; 2193 2194 case INDEX_op_movcond_i32: 2195 /* Constraints mean that v2 is always in the same register as dest, 2196 * so we only need to do "if condition passed, move v1 to dest". 2197 */ 2198 c = tcg_out_cmp(s, args[5], args[1], args[2], const_args[2]); 2199 tcg_out_dat_rIK(s, tcg_cond_to_arm_cond[c], ARITH_MOV, 2200 ARITH_MVN, args[0], 0, args[3], const_args[3]); 2201 break; 2202 case INDEX_op_add2_i32: 2203 a0 = args[0], a1 = args[1], a2 = args[2]; 2204 a3 = args[3], a4 = args[4], a5 = args[5]; 2205 if (a0 == a3 || (a0 == a5 && !const_args[5])) { 2206 a0 = TCG_REG_TMP; 2207 } 2208 tcg_out_dat_rIN(s, COND_AL, ARITH_ADD | TO_CPSR, ARITH_SUB | TO_CPSR, 2209 a0, a2, a4, const_args[4]); 2210 tcg_out_dat_rIK(s, COND_AL, ARITH_ADC, ARITH_SBC, 2211 a1, a3, a5, const_args[5]); 2212 tcg_out_mov_reg(s, COND_AL, args[0], a0); 2213 break; 2214 case INDEX_op_sub2_i32: 2215 a0 = args[0], a1 = args[1], a2 = args[2]; 2216 a3 = args[3], a4 = args[4], a5 = args[5]; 2217 if ((a0 == a3 && !const_args[3]) || (a0 == a5 && !const_args[5])) { 2218 a0 = TCG_REG_TMP; 2219 } 2220 if (const_args[2]) { 2221 if (const_args[4]) { 2222 tcg_out_movi32(s, COND_AL, a0, a4); 2223 a4 = a0; 2224 } 2225 tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR, a0, a4, a2, 1); 2226 } else { 2227 tcg_out_dat_rIN(s, COND_AL, ARITH_SUB | TO_CPSR, 2228 ARITH_ADD | TO_CPSR, a0, a2, a4, const_args[4]); 2229 } 2230 if (const_args[3]) { 2231 if (const_args[5]) { 2232 tcg_out_movi32(s, COND_AL, a1, a5); 2233 a5 = a1; 2234 } 2235 tcg_out_dat_rI(s, COND_AL, ARITH_RSC, a1, a5, a3, 1); 2236 } else { 2237 tcg_out_dat_rIK(s, COND_AL, ARITH_SBC, ARITH_ADC, 2238 a1, a3, a5, const_args[5]); 2239 } 2240 tcg_out_mov_reg(s, COND_AL, args[0], a0); 2241 break; 2242 case INDEX_op_mulu2_i32: 2243 tcg_out_umull32(s, COND_AL, args[0], args[1], args[2], args[3]); 2244 break; 2245 case INDEX_op_muls2_i32: 2246 tcg_out_smull32(s, COND_AL, args[0], args[1], args[2], args[3]); 2247 break; 2248 2249 case INDEX_op_brcond_i32: 2250 c = tcg_out_cmp(s, args[2], args[0], args[1], const_args[1]); 2251 tcg_out_goto_label(s, tcg_cond_to_arm_cond[c], arg_label(args[3])); 2252 break; 2253 case INDEX_op_setcond_i32: 2254 c = tcg_out_cmp(s, args[3], args[1], args[2], const_args[2]); 2255 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[c], 2256 ARITH_MOV, args[0], 0, 1); 2257 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(c)], 2258 ARITH_MOV, args[0], 0, 0); 2259 break; 2260 case INDEX_op_negsetcond_i32: 2261 c = tcg_out_cmp(s, args[3], args[1], args[2], const_args[2]); 2262 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[c], 2263 ARITH_MVN, args[0], 0, 0); 2264 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(c)], 2265 ARITH_MOV, args[0], 0, 0); 2266 break; 2267 2268 case INDEX_op_brcond2_i32: 2269 c = tcg_out_cmp2(s, args, const_args); 2270 tcg_out_goto_label(s, tcg_cond_to_arm_cond[c], arg_label(args[5])); 2271 break; 2272 case INDEX_op_setcond2_i32: 2273 c = tcg_out_cmp2(s, args + 1, const_args + 1); 2274 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[c], ARITH_MOV, args[0], 0, 1); 2275 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(c)], 2276 ARITH_MOV, args[0], 0, 0); 2277 break; 2278 2279 case INDEX_op_qemu_ld_i32: 2280 tcg_out_qemu_ld(s, args[0], -1, args[1], args[2], TCG_TYPE_I32); 2281 break; 2282 case INDEX_op_qemu_ld_i64: 2283 tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3], TCG_TYPE_I64); 2284 break; 2285 2286 case INDEX_op_qemu_st_i32: 2287 tcg_out_qemu_st(s, args[0], -1, args[1], args[2], TCG_TYPE_I32); 2288 break; 2289 case INDEX_op_qemu_st_i64: 2290 tcg_out_qemu_st(s, args[0], args[1], args[2], args[3], TCG_TYPE_I64); 2291 break; 2292 2293 case INDEX_op_bswap16_i32: 2294 tcg_out_bswap16(s, COND_AL, args[0], args[1], args[2]); 2295 break; 2296 case INDEX_op_bswap32_i32: 2297 tcg_out_bswap32(s, COND_AL, args[0], args[1]); 2298 break; 2299 2300 case INDEX_op_deposit_i32: 2301 tcg_out_deposit(s, COND_AL, args[0], args[2], 2302 args[3], args[4], const_args[2]); 2303 break; 2304 case INDEX_op_extract_i32: 2305 tcg_out_extract(s, COND_AL, args[0], args[1], args[2], args[3]); 2306 break; 2307 case INDEX_op_sextract_i32: 2308 tcg_out_sextract(s, COND_AL, args[0], args[1], args[2], args[3]); 2309 break; 2310 case INDEX_op_extract2_i32: 2311 /* ??? These optimization vs zero should be generic. */ 2312 /* ??? But we can't substitute 2 for 1 in the opcode stream yet. */ 2313 if (const_args[1]) { 2314 if (const_args[2]) { 2315 tcg_out_movi(s, TCG_TYPE_REG, args[0], 0); 2316 } else { 2317 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, 2318 args[2], SHIFT_IMM_LSL(32 - args[3])); 2319 } 2320 } else if (const_args[2]) { 2321 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, 2322 args[1], SHIFT_IMM_LSR(args[3])); 2323 } else { 2324 /* We can do extract2 in 2 insns, vs the 3 required otherwise. */ 2325 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, 2326 args[2], SHIFT_IMM_LSL(32 - args[3])); 2327 tcg_out_dat_reg(s, COND_AL, ARITH_ORR, args[0], TCG_REG_TMP, 2328 args[1], SHIFT_IMM_LSR(args[3])); 2329 } 2330 break; 2331 2332 case INDEX_op_mb: 2333 tcg_out_mb(s, args[0]); 2334 break; 2335 2336 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2337 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2338 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2339 default: 2340 g_assert_not_reached(); 2341 } 2342} 2343 2344static TCGConstraintSetIndex 2345tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) 2346{ 2347 switch (op) { 2348 case INDEX_op_goto_ptr: 2349 return C_O0_I1(r); 2350 2351 case INDEX_op_ld8u_i32: 2352 case INDEX_op_ld8s_i32: 2353 case INDEX_op_ld16u_i32: 2354 case INDEX_op_ld16s_i32: 2355 case INDEX_op_ld_i32: 2356 case INDEX_op_bswap16_i32: 2357 case INDEX_op_bswap32_i32: 2358 case INDEX_op_extract_i32: 2359 case INDEX_op_sextract_i32: 2360 return C_O1_I1(r, r); 2361 2362 case INDEX_op_st8_i32: 2363 case INDEX_op_st16_i32: 2364 case INDEX_op_st_i32: 2365 return C_O0_I2(r, r); 2366 2367 case INDEX_op_setcond_i32: 2368 case INDEX_op_negsetcond_i32: 2369 return C_O1_I2(r, r, rIN); 2370 2371 case INDEX_op_mulu2_i32: 2372 case INDEX_op_muls2_i32: 2373 return C_O2_I2(r, r, r, r); 2374 2375 case INDEX_op_brcond_i32: 2376 return C_O0_I2(r, rIN); 2377 case INDEX_op_deposit_i32: 2378 return C_O1_I2(r, 0, rZ); 2379 case INDEX_op_extract2_i32: 2380 return C_O1_I2(r, rZ, rZ); 2381 case INDEX_op_movcond_i32: 2382 return C_O1_I4(r, r, rIN, rIK, 0); 2383 case INDEX_op_add2_i32: 2384 return C_O2_I4(r, r, r, r, rIN, rIK); 2385 case INDEX_op_sub2_i32: 2386 return C_O2_I4(r, r, rI, rI, rIN, rIK); 2387 case INDEX_op_brcond2_i32: 2388 return C_O0_I4(r, r, rI, rI); 2389 case INDEX_op_setcond2_i32: 2390 return C_O1_I4(r, r, r, rI, rI); 2391 2392 case INDEX_op_qemu_ld_i32: 2393 return C_O1_I1(r, q); 2394 case INDEX_op_qemu_ld_i64: 2395 return C_O2_I1(e, p, q); 2396 case INDEX_op_qemu_st_i32: 2397 return C_O0_I2(q, q); 2398 case INDEX_op_qemu_st_i64: 2399 return C_O0_I3(Q, p, q); 2400 2401 case INDEX_op_st_vec: 2402 return C_O0_I2(w, r); 2403 case INDEX_op_ld_vec: 2404 case INDEX_op_dupm_vec: 2405 return C_O1_I1(w, r); 2406 case INDEX_op_dup_vec: 2407 return C_O1_I1(w, wr); 2408 case INDEX_op_abs_vec: 2409 case INDEX_op_neg_vec: 2410 case INDEX_op_not_vec: 2411 case INDEX_op_shli_vec: 2412 case INDEX_op_shri_vec: 2413 case INDEX_op_sari_vec: 2414 return C_O1_I1(w, w); 2415 case INDEX_op_dup2_vec: 2416 case INDEX_op_add_vec: 2417 case INDEX_op_mul_vec: 2418 case INDEX_op_smax_vec: 2419 case INDEX_op_smin_vec: 2420 case INDEX_op_ssadd_vec: 2421 case INDEX_op_sssub_vec: 2422 case INDEX_op_sub_vec: 2423 case INDEX_op_umax_vec: 2424 case INDEX_op_umin_vec: 2425 case INDEX_op_usadd_vec: 2426 case INDEX_op_ussub_vec: 2427 case INDEX_op_xor_vec: 2428 case INDEX_op_arm_sshl_vec: 2429 case INDEX_op_arm_ushl_vec: 2430 return C_O1_I2(w, w, w); 2431 case INDEX_op_arm_sli_vec: 2432 return C_O1_I2(w, 0, w); 2433 case INDEX_op_or_vec: 2434 case INDEX_op_andc_vec: 2435 return C_O1_I2(w, w, wO); 2436 case INDEX_op_and_vec: 2437 case INDEX_op_orc_vec: 2438 return C_O1_I2(w, w, wV); 2439 case INDEX_op_cmp_vec: 2440 return C_O1_I2(w, w, wZ); 2441 case INDEX_op_bitsel_vec: 2442 return C_O1_I3(w, w, w, w); 2443 default: 2444 return C_NotImplemented; 2445 } 2446} 2447 2448static void tcg_target_init(TCGContext *s) 2449{ 2450 /* 2451 * Only probe for the platform and capabilities if we haven't already 2452 * determined maximum values at compile time. 2453 */ 2454#if !defined(use_idiv_instructions) || !defined(use_neon_instructions) 2455 { 2456 unsigned long hwcap = qemu_getauxval(AT_HWCAP); 2457#ifndef use_idiv_instructions 2458 use_idiv_instructions = (hwcap & HWCAP_ARM_IDIVA) != 0; 2459#endif 2460#ifndef use_neon_instructions 2461 use_neon_instructions = (hwcap & HWCAP_ARM_NEON) != 0; 2462#endif 2463 } 2464#endif 2465 2466 if (__ARM_ARCH < 7) { 2467 const char *pl = (const char *)qemu_getauxval(AT_PLATFORM); 2468 if (pl != NULL && pl[0] == 'v' && pl[1] >= '4' && pl[1] <= '9') { 2469 arm_arch = pl[1] - '0'; 2470 } 2471 2472 if (arm_arch < 6) { 2473 error_report("TCG: ARMv%d is unsupported; exiting", arm_arch); 2474 exit(EXIT_FAILURE); 2475 } 2476 } 2477 2478 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS; 2479 2480 tcg_target_call_clobber_regs = 0; 2481 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); 2482 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1); 2483 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2); 2484 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3); 2485 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12); 2486 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14); 2487 2488 if (use_neon_instructions) { 2489 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS; 2490 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS; 2491 2492 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q0); 2493 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q1); 2494 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q2); 2495 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q3); 2496 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q8); 2497 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q9); 2498 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q10); 2499 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q11); 2500 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q12); 2501 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q13); 2502 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q14); 2503 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q15); 2504 } 2505 2506 s->reserved_regs = 0; 2507 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); 2508 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP); 2509 tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC); 2510 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP); 2511} 2512 2513static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 2514 TCGReg arg1, intptr_t arg2) 2515{ 2516 switch (type) { 2517 case TCG_TYPE_I32: 2518 tcg_out_ld32u(s, COND_AL, arg, arg1, arg2); 2519 return; 2520 case TCG_TYPE_V64: 2521 /* regs 1; size 8; align 8 */ 2522 tcg_out_vldst(s, INSN_VLD1 | 0x7d0, arg, arg1, arg2); 2523 return; 2524 case TCG_TYPE_V128: 2525 /* 2526 * We have only 8-byte alignment for the stack per the ABI. 2527 * Rather than dynamically re-align the stack, it's easier 2528 * to simply not request alignment beyond that. So: 2529 * regs 2; size 8; align 8 2530 */ 2531 tcg_out_vldst(s, INSN_VLD1 | 0xad0, arg, arg1, arg2); 2532 return; 2533 default: 2534 g_assert_not_reached(); 2535 } 2536} 2537 2538static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 2539 TCGReg arg1, intptr_t arg2) 2540{ 2541 switch (type) { 2542 case TCG_TYPE_I32: 2543 tcg_out_st32(s, COND_AL, arg, arg1, arg2); 2544 return; 2545 case TCG_TYPE_V64: 2546 /* regs 1; size 8; align 8 */ 2547 tcg_out_vldst(s, INSN_VST1 | 0x7d0, arg, arg1, arg2); 2548 return; 2549 case TCG_TYPE_V128: 2550 /* See tcg_out_ld re alignment: regs 2; size 8; align 8 */ 2551 tcg_out_vldst(s, INSN_VST1 | 0xad0, arg, arg1, arg2); 2552 return; 2553 default: 2554 g_assert_not_reached(); 2555 } 2556} 2557 2558static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 2559 TCGReg base, intptr_t ofs) 2560{ 2561 return false; 2562} 2563 2564static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 2565{ 2566 if (ret == arg) { 2567 return true; 2568 } 2569 switch (type) { 2570 case TCG_TYPE_I32: 2571 if (ret < TCG_REG_Q0 && arg < TCG_REG_Q0) { 2572 tcg_out_mov_reg(s, COND_AL, ret, arg); 2573 return true; 2574 } 2575 return false; 2576 2577 case TCG_TYPE_V64: 2578 case TCG_TYPE_V128: 2579 /* "VMOV D,N" is an alias for "VORR D,N,N". */ 2580 tcg_out_vreg3(s, INSN_VORR, type - TCG_TYPE_V64, 0, ret, arg, arg); 2581 return true; 2582 2583 default: 2584 g_assert_not_reached(); 2585 } 2586} 2587 2588static void tcg_out_movi(TCGContext *s, TCGType type, 2589 TCGReg ret, tcg_target_long arg) 2590{ 2591 tcg_debug_assert(type == TCG_TYPE_I32); 2592 tcg_debug_assert(ret < TCG_REG_Q0); 2593 tcg_out_movi32(s, COND_AL, ret, arg); 2594} 2595 2596static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 2597{ 2598 return false; 2599} 2600 2601static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 2602 tcg_target_long imm) 2603{ 2604 int enc, opc = ARITH_ADD; 2605 2606 /* All of the easiest immediates to encode are positive. */ 2607 if (imm < 0) { 2608 imm = -imm; 2609 opc = ARITH_SUB; 2610 } 2611 enc = encode_imm(imm); 2612 if (enc >= 0) { 2613 tcg_out_dat_imm(s, COND_AL, opc, rd, rs, enc); 2614 } else { 2615 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, imm); 2616 tcg_out_dat_reg(s, COND_AL, opc, rd, rs, 2617 TCG_REG_TMP, SHIFT_IMM_LSL(0)); 2618 } 2619} 2620 2621/* Type is always V128, with I64 elements. */ 2622static void tcg_out_dup2_vec(TCGContext *s, TCGReg rd, TCGReg rl, TCGReg rh) 2623{ 2624 /* Move high element into place first. */ 2625 /* VMOV Dd+1, Ds */ 2626 tcg_out_vreg3(s, INSN_VORR | (1 << 12), 0, 0, rd, rh, rh); 2627 /* Move low element into place; tcg_out_mov will check for nop. */ 2628 tcg_out_mov(s, TCG_TYPE_V64, rd, rl); 2629} 2630 2631static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 2632 TCGReg rd, TCGReg rs) 2633{ 2634 int q = type - TCG_TYPE_V64; 2635 2636 if (vece == MO_64) { 2637 if (type == TCG_TYPE_V128) { 2638 tcg_out_dup2_vec(s, rd, rs, rs); 2639 } else { 2640 tcg_out_mov(s, TCG_TYPE_V64, rd, rs); 2641 } 2642 } else if (rs < TCG_REG_Q0) { 2643 int b = (vece == MO_8); 2644 int e = (vece == MO_16); 2645 tcg_out32(s, INSN_VDUP_G | (b << 22) | (q << 21) | (e << 5) | 2646 encode_vn(rd) | (rs << 12)); 2647 } else { 2648 int imm4 = 1 << vece; 2649 tcg_out32(s, INSN_VDUP_S | (imm4 << 16) | (q << 6) | 2650 encode_vd(rd) | encode_vm(rs)); 2651 } 2652 return true; 2653} 2654 2655static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 2656 TCGReg rd, TCGReg base, intptr_t offset) 2657{ 2658 if (vece == MO_64) { 2659 tcg_out_ld(s, TCG_TYPE_V64, rd, base, offset); 2660 if (type == TCG_TYPE_V128) { 2661 tcg_out_dup2_vec(s, rd, rd, rd); 2662 } 2663 } else { 2664 int q = type - TCG_TYPE_V64; 2665 tcg_out_vldst(s, INSN_VLD1R | (vece << 6) | (q << 5), 2666 rd, base, offset); 2667 } 2668 return true; 2669} 2670 2671static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 2672 TCGReg rd, int64_t v64) 2673{ 2674 int q = type - TCG_TYPE_V64; 2675 int cmode, imm8, i; 2676 2677 /* Test all bytes equal first. */ 2678 if (vece == MO_8) { 2679 tcg_out_vmovi(s, rd, q, 0, 0xe, v64); 2680 return; 2681 } 2682 2683 /* 2684 * Test all bytes 0x00 or 0xff second. This can match cases that 2685 * might otherwise take 2 or 3 insns for MO_16 or MO_32 below. 2686 */ 2687 for (i = imm8 = 0; i < 8; i++) { 2688 uint8_t byte = v64 >> (i * 8); 2689 if (byte == 0xff) { 2690 imm8 |= 1 << i; 2691 } else if (byte != 0) { 2692 goto fail_bytes; 2693 } 2694 } 2695 tcg_out_vmovi(s, rd, q, 1, 0xe, imm8); 2696 return; 2697 fail_bytes: 2698 2699 /* 2700 * Tests for various replications. For each element width, if we 2701 * cannot find an expansion there's no point checking a larger 2702 * width because we already know by replication it cannot match. 2703 */ 2704 if (vece == MO_16) { 2705 uint16_t v16 = v64; 2706 2707 if (is_shimm16(v16, &cmode, &imm8)) { 2708 tcg_out_vmovi(s, rd, q, 0, cmode, imm8); 2709 return; 2710 } 2711 if (is_shimm16(~v16, &cmode, &imm8)) { 2712 tcg_out_vmovi(s, rd, q, 1, cmode, imm8); 2713 return; 2714 } 2715 2716 /* 2717 * Otherwise, all remaining constants can be loaded in two insns: 2718 * rd = v16 & 0xff, rd |= v16 & 0xff00. 2719 */ 2720 tcg_out_vmovi(s, rd, q, 0, 0x8, v16 & 0xff); 2721 tcg_out_vmovi(s, rd, q, 0, 0xb, v16 >> 8); /* VORRI */ 2722 return; 2723 } 2724 2725 if (vece == MO_32) { 2726 uint32_t v32 = v64; 2727 2728 if (is_shimm32(v32, &cmode, &imm8) || 2729 is_soimm32(v32, &cmode, &imm8)) { 2730 tcg_out_vmovi(s, rd, q, 0, cmode, imm8); 2731 return; 2732 } 2733 if (is_shimm32(~v32, &cmode, &imm8) || 2734 is_soimm32(~v32, &cmode, &imm8)) { 2735 tcg_out_vmovi(s, rd, q, 1, cmode, imm8); 2736 return; 2737 } 2738 2739 /* 2740 * Restrict the set of constants to those we can load with 2741 * two instructions. Others we load from the pool. 2742 */ 2743 i = is_shimm32_pair(v32, &cmode, &imm8); 2744 if (i) { 2745 tcg_out_vmovi(s, rd, q, 0, cmode, imm8); 2746 tcg_out_vmovi(s, rd, q, 0, i | 1, extract32(v32, i * 4, 8)); 2747 return; 2748 } 2749 i = is_shimm32_pair(~v32, &cmode, &imm8); 2750 if (i) { 2751 tcg_out_vmovi(s, rd, q, 1, cmode, imm8); 2752 tcg_out_vmovi(s, rd, q, 1, i | 1, extract32(~v32, i * 4, 8)); 2753 return; 2754 } 2755 } 2756 2757 /* 2758 * As a last resort, load from the constant pool. 2759 */ 2760 if (!q || vece == MO_64) { 2761 new_pool_l2(s, R_ARM_PC11, s->code_ptr, 0, v64, v64 >> 32); 2762 /* VLDR Dd, [pc + offset] */ 2763 tcg_out32(s, INSN_VLDR_D | encode_vd(rd) | (0xf << 16)); 2764 if (q) { 2765 tcg_out_dup2_vec(s, rd, rd, rd); 2766 } 2767 } else { 2768 new_pool_label(s, (uint32_t)v64, R_ARM_PC8, s->code_ptr, 0); 2769 /* add tmp, pc, offset */ 2770 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_TMP, TCG_REG_PC, 0); 2771 tcg_out_dupm_vec(s, type, MO_32, rd, TCG_REG_TMP, 0); 2772 } 2773} 2774 2775static const ARMInsn vec_cmp_insn[16] = { 2776 [TCG_COND_EQ] = INSN_VCEQ, 2777 [TCG_COND_GT] = INSN_VCGT, 2778 [TCG_COND_GE] = INSN_VCGE, 2779 [TCG_COND_GTU] = INSN_VCGT_U, 2780 [TCG_COND_GEU] = INSN_VCGE_U, 2781}; 2782 2783static const ARMInsn vec_cmp0_insn[16] = { 2784 [TCG_COND_EQ] = INSN_VCEQ0, 2785 [TCG_COND_GT] = INSN_VCGT0, 2786 [TCG_COND_GE] = INSN_VCGE0, 2787 [TCG_COND_LT] = INSN_VCLT0, 2788 [TCG_COND_LE] = INSN_VCLE0, 2789}; 2790 2791static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 2792 unsigned vecl, unsigned vece, 2793 const TCGArg args[TCG_MAX_OP_ARGS], 2794 const int const_args[TCG_MAX_OP_ARGS]) 2795{ 2796 TCGType type = vecl + TCG_TYPE_V64; 2797 unsigned q = vecl; 2798 TCGArg a0, a1, a2, a3; 2799 int cmode, imm8; 2800 2801 a0 = args[0]; 2802 a1 = args[1]; 2803 a2 = args[2]; 2804 2805 switch (opc) { 2806 case INDEX_op_ld_vec: 2807 tcg_out_ld(s, type, a0, a1, a2); 2808 return; 2809 case INDEX_op_st_vec: 2810 tcg_out_st(s, type, a0, a1, a2); 2811 return; 2812 case INDEX_op_dupm_vec: 2813 tcg_out_dupm_vec(s, type, vece, a0, a1, a2); 2814 return; 2815 case INDEX_op_dup2_vec: 2816 tcg_out_dup2_vec(s, a0, a1, a2); 2817 return; 2818 case INDEX_op_abs_vec: 2819 tcg_out_vreg2(s, INSN_VABS, q, vece, a0, a1); 2820 return; 2821 case INDEX_op_neg_vec: 2822 tcg_out_vreg2(s, INSN_VNEG, q, vece, a0, a1); 2823 return; 2824 case INDEX_op_not_vec: 2825 tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a1); 2826 return; 2827 case INDEX_op_add_vec: 2828 tcg_out_vreg3(s, INSN_VADD, q, vece, a0, a1, a2); 2829 return; 2830 case INDEX_op_mul_vec: 2831 tcg_out_vreg3(s, INSN_VMUL, q, vece, a0, a1, a2); 2832 return; 2833 case INDEX_op_smax_vec: 2834 tcg_out_vreg3(s, INSN_VMAX, q, vece, a0, a1, a2); 2835 return; 2836 case INDEX_op_smin_vec: 2837 tcg_out_vreg3(s, INSN_VMIN, q, vece, a0, a1, a2); 2838 return; 2839 case INDEX_op_sub_vec: 2840 tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2); 2841 return; 2842 case INDEX_op_ssadd_vec: 2843 tcg_out_vreg3(s, INSN_VQADD, q, vece, a0, a1, a2); 2844 return; 2845 case INDEX_op_sssub_vec: 2846 tcg_out_vreg3(s, INSN_VQSUB, q, vece, a0, a1, a2); 2847 return; 2848 case INDEX_op_umax_vec: 2849 tcg_out_vreg3(s, INSN_VMAX_U, q, vece, a0, a1, a2); 2850 return; 2851 case INDEX_op_umin_vec: 2852 tcg_out_vreg3(s, INSN_VMIN_U, q, vece, a0, a1, a2); 2853 return; 2854 case INDEX_op_usadd_vec: 2855 tcg_out_vreg3(s, INSN_VQADD_U, q, vece, a0, a1, a2); 2856 return; 2857 case INDEX_op_ussub_vec: 2858 tcg_out_vreg3(s, INSN_VQSUB_U, q, vece, a0, a1, a2); 2859 return; 2860 case INDEX_op_xor_vec: 2861 tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2); 2862 return; 2863 case INDEX_op_arm_sshl_vec: 2864 /* 2865 * Note that Vm is the data and Vn is the shift count, 2866 * therefore the arguments appear reversed. 2867 */ 2868 tcg_out_vreg3(s, INSN_VSHL_S, q, vece, a0, a2, a1); 2869 return; 2870 case INDEX_op_arm_ushl_vec: 2871 /* See above. */ 2872 tcg_out_vreg3(s, INSN_VSHL_U, q, vece, a0, a2, a1); 2873 return; 2874 case INDEX_op_shli_vec: 2875 tcg_out_vshifti(s, INSN_VSHLI, q, a0, a1, a2 + (8 << vece)); 2876 return; 2877 case INDEX_op_shri_vec: 2878 tcg_out_vshifti(s, INSN_VSHRI, q, a0, a1, (16 << vece) - a2); 2879 return; 2880 case INDEX_op_sari_vec: 2881 tcg_out_vshifti(s, INSN_VSARI, q, a0, a1, (16 << vece) - a2); 2882 return; 2883 case INDEX_op_arm_sli_vec: 2884 tcg_out_vshifti(s, INSN_VSLI, q, a0, a2, args[3] + (8 << vece)); 2885 return; 2886 2887 case INDEX_op_andc_vec: 2888 if (!const_args[2]) { 2889 tcg_out_vreg3(s, INSN_VBIC, q, 0, a0, a1, a2); 2890 return; 2891 } 2892 a2 = ~a2; 2893 /* fall through */ 2894 case INDEX_op_and_vec: 2895 if (const_args[2]) { 2896 is_shimm1632(~a2, &cmode, &imm8); 2897 if (a0 == a1) { 2898 tcg_out_vmovi(s, a0, q, 1, cmode | 1, imm8); /* VBICI */ 2899 return; 2900 } 2901 tcg_out_vmovi(s, a0, q, 1, cmode, imm8); /* VMVNI */ 2902 a2 = a0; 2903 } 2904 tcg_out_vreg3(s, INSN_VAND, q, 0, a0, a1, a2); 2905 return; 2906 2907 case INDEX_op_orc_vec: 2908 if (!const_args[2]) { 2909 tcg_out_vreg3(s, INSN_VORN, q, 0, a0, a1, a2); 2910 return; 2911 } 2912 a2 = ~a2; 2913 /* fall through */ 2914 case INDEX_op_or_vec: 2915 if (const_args[2]) { 2916 is_shimm1632(a2, &cmode, &imm8); 2917 if (a0 == a1) { 2918 tcg_out_vmovi(s, a0, q, 0, cmode | 1, imm8); /* VORRI */ 2919 return; 2920 } 2921 tcg_out_vmovi(s, a0, q, 0, cmode, imm8); /* VMOVI */ 2922 a2 = a0; 2923 } 2924 tcg_out_vreg3(s, INSN_VORR, q, 0, a0, a1, a2); 2925 return; 2926 2927 case INDEX_op_cmp_vec: 2928 { 2929 TCGCond cond = args[3]; 2930 ARMInsn insn; 2931 2932 switch (cond) { 2933 case TCG_COND_NE: 2934 if (const_args[2]) { 2935 tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a1); 2936 } else { 2937 tcg_out_vreg3(s, INSN_VCEQ, q, vece, a0, a1, a2); 2938 tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0); 2939 } 2940 break; 2941 2942 case TCG_COND_TSTNE: 2943 case TCG_COND_TSTEQ: 2944 if (const_args[2]) { 2945 /* (x & 0) == 0 */ 2946 tcg_out_dupi_vec(s, type, MO_8, a0, 2947 -(cond == TCG_COND_TSTEQ)); 2948 break; 2949 } 2950 tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a2); 2951 if (cond == TCG_COND_TSTEQ) { 2952 tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0); 2953 } 2954 break; 2955 2956 default: 2957 if (const_args[2]) { 2958 insn = vec_cmp0_insn[cond]; 2959 if (insn) { 2960 tcg_out_vreg2(s, insn, q, vece, a0, a1); 2961 return; 2962 } 2963 tcg_out_dupi_vec(s, type, MO_8, TCG_VEC_TMP, 0); 2964 a2 = TCG_VEC_TMP; 2965 } 2966 insn = vec_cmp_insn[cond]; 2967 if (insn == 0) { 2968 TCGArg t; 2969 t = a1, a1 = a2, a2 = t; 2970 cond = tcg_swap_cond(cond); 2971 insn = vec_cmp_insn[cond]; 2972 tcg_debug_assert(insn != 0); 2973 } 2974 tcg_out_vreg3(s, insn, q, vece, a0, a1, a2); 2975 break; 2976 } 2977 } 2978 return; 2979 2980 case INDEX_op_bitsel_vec: 2981 a3 = args[3]; 2982 if (a0 == a3) { 2983 tcg_out_vreg3(s, INSN_VBIT, q, 0, a0, a2, a1); 2984 } else if (a0 == a2) { 2985 tcg_out_vreg3(s, INSN_VBIF, q, 0, a0, a3, a1); 2986 } else { 2987 tcg_out_mov(s, type, a0, a1); 2988 tcg_out_vreg3(s, INSN_VBSL, q, 0, a0, a2, a3); 2989 } 2990 return; 2991 2992 case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ 2993 case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ 2994 default: 2995 g_assert_not_reached(); 2996 } 2997} 2998 2999int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 3000{ 3001 switch (opc) { 3002 case INDEX_op_add_vec: 3003 case INDEX_op_sub_vec: 3004 case INDEX_op_and_vec: 3005 case INDEX_op_andc_vec: 3006 case INDEX_op_or_vec: 3007 case INDEX_op_orc_vec: 3008 case INDEX_op_xor_vec: 3009 case INDEX_op_not_vec: 3010 case INDEX_op_shli_vec: 3011 case INDEX_op_shri_vec: 3012 case INDEX_op_sari_vec: 3013 case INDEX_op_ssadd_vec: 3014 case INDEX_op_sssub_vec: 3015 case INDEX_op_usadd_vec: 3016 case INDEX_op_ussub_vec: 3017 case INDEX_op_bitsel_vec: 3018 return 1; 3019 case INDEX_op_abs_vec: 3020 case INDEX_op_cmp_vec: 3021 case INDEX_op_mul_vec: 3022 case INDEX_op_neg_vec: 3023 case INDEX_op_smax_vec: 3024 case INDEX_op_smin_vec: 3025 case INDEX_op_umax_vec: 3026 case INDEX_op_umin_vec: 3027 return vece < MO_64; 3028 case INDEX_op_shlv_vec: 3029 case INDEX_op_shrv_vec: 3030 case INDEX_op_sarv_vec: 3031 case INDEX_op_rotli_vec: 3032 case INDEX_op_rotlv_vec: 3033 case INDEX_op_rotrv_vec: 3034 return -1; 3035 default: 3036 return 0; 3037 } 3038} 3039 3040void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 3041 TCGArg a0, ...) 3042{ 3043 va_list va; 3044 TCGv_vec v0, v1, v2, t1, t2, c1; 3045 TCGArg a2; 3046 3047 va_start(va, a0); 3048 v0 = temp_tcgv_vec(arg_temp(a0)); 3049 v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 3050 a2 = va_arg(va, TCGArg); 3051 va_end(va); 3052 3053 switch (opc) { 3054 case INDEX_op_shlv_vec: 3055 /* 3056 * Merely propagate shlv_vec to arm_ushl_vec. 3057 * In this way we don't set TCG_TARGET_HAS_shv_vec 3058 * because everything is done via expansion. 3059 */ 3060 v2 = temp_tcgv_vec(arg_temp(a2)); 3061 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0), 3062 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 3063 break; 3064 3065 case INDEX_op_shrv_vec: 3066 case INDEX_op_sarv_vec: 3067 /* Right shifts are negative left shifts for NEON. */ 3068 v2 = temp_tcgv_vec(arg_temp(a2)); 3069 t1 = tcg_temp_new_vec(type); 3070 tcg_gen_neg_vec(vece, t1, v2); 3071 if (opc == INDEX_op_shrv_vec) { 3072 opc = INDEX_op_arm_ushl_vec; 3073 } else { 3074 opc = INDEX_op_arm_sshl_vec; 3075 } 3076 vec_gen_3(opc, type, vece, tcgv_vec_arg(v0), 3077 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 3078 tcg_temp_free_vec(t1); 3079 break; 3080 3081 case INDEX_op_rotli_vec: 3082 t1 = tcg_temp_new_vec(type); 3083 tcg_gen_shri_vec(vece, t1, v1, -a2 & ((8 << vece) - 1)); 3084 vec_gen_4(INDEX_op_arm_sli_vec, type, vece, 3085 tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(v1), a2); 3086 tcg_temp_free_vec(t1); 3087 break; 3088 3089 case INDEX_op_rotlv_vec: 3090 v2 = temp_tcgv_vec(arg_temp(a2)); 3091 t1 = tcg_temp_new_vec(type); 3092 c1 = tcg_constant_vec(type, vece, 8 << vece); 3093 tcg_gen_sub_vec(vece, t1, v2, c1); 3094 /* Right shifts are negative left shifts for NEON. */ 3095 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1), 3096 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 3097 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0), 3098 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 3099 tcg_gen_or_vec(vece, v0, v0, t1); 3100 tcg_temp_free_vec(t1); 3101 break; 3102 3103 case INDEX_op_rotrv_vec: 3104 v2 = temp_tcgv_vec(arg_temp(a2)); 3105 t1 = tcg_temp_new_vec(type); 3106 t2 = tcg_temp_new_vec(type); 3107 c1 = tcg_constant_vec(type, vece, 8 << vece); 3108 tcg_gen_neg_vec(vece, t1, v2); 3109 tcg_gen_sub_vec(vece, t2, c1, v2); 3110 /* Right shifts are negative left shifts for NEON. */ 3111 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1), 3112 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 3113 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t2), 3114 tcgv_vec_arg(v1), tcgv_vec_arg(t2)); 3115 tcg_gen_or_vec(vece, v0, t1, t2); 3116 tcg_temp_free_vec(t1); 3117 tcg_temp_free_vec(t2); 3118 break; 3119 3120 default: 3121 g_assert_not_reached(); 3122 } 3123} 3124 3125static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 3126{ 3127 int i; 3128 for (i = 0; i < count; ++i) { 3129 p[i] = INSN_NOP; 3130 } 3131} 3132 3133/* Compute frame size via macros, to share between tcg_target_qemu_prologue 3134 and tcg_register_jit. */ 3135 3136#define PUSH_SIZE ((11 - 4 + 1 + 1) * sizeof(tcg_target_long)) 3137 3138#define FRAME_SIZE \ 3139 ((PUSH_SIZE \ 3140 + TCG_STATIC_CALL_ARGS_SIZE \ 3141 + CPU_TEMP_BUF_NLONGS * sizeof(long) \ 3142 + TCG_TARGET_STACK_ALIGN - 1) \ 3143 & -TCG_TARGET_STACK_ALIGN) 3144 3145#define STACK_ADDEND (FRAME_SIZE - PUSH_SIZE) 3146 3147static void tcg_target_qemu_prologue(TCGContext *s) 3148{ 3149 /* Calling convention requires us to save r4-r11 and lr. */ 3150 /* stmdb sp!, { r4 - r11, lr } */ 3151 tcg_out_ldstm(s, COND_AL, INSN_STMDB, TCG_REG_CALL_STACK, 3152 (1 << TCG_REG_R4) | (1 << TCG_REG_R5) | (1 << TCG_REG_R6) | 3153 (1 << TCG_REG_R7) | (1 << TCG_REG_R8) | (1 << TCG_REG_R9) | 3154 (1 << TCG_REG_R10) | (1 << TCG_REG_R11) | (1 << TCG_REG_R14)); 3155 3156 /* Reserve callee argument and tcg temp space. */ 3157 tcg_out_dat_rI(s, COND_AL, ARITH_SUB, TCG_REG_CALL_STACK, 3158 TCG_REG_CALL_STACK, STACK_ADDEND, 1); 3159 tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE, 3160 CPU_TEMP_BUF_NLONGS * sizeof(long)); 3161 3162 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 3163 3164 if (!tcg_use_softmmu && guest_base) { 3165 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_GUEST_BASE, guest_base); 3166 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GUEST_BASE); 3167 } 3168 3169 tcg_out_b_reg(s, COND_AL, tcg_target_call_iarg_regs[1]); 3170 3171 /* 3172 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 3173 * and fall through to the rest of the epilogue. 3174 */ 3175 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 3176 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, 0); 3177 tcg_out_epilogue(s); 3178} 3179 3180static void tcg_out_epilogue(TCGContext *s) 3181{ 3182 /* Release local stack frame. */ 3183 tcg_out_dat_rI(s, COND_AL, ARITH_ADD, TCG_REG_CALL_STACK, 3184 TCG_REG_CALL_STACK, STACK_ADDEND, 1); 3185 3186 /* ldmia sp!, { r4 - r11, pc } */ 3187 tcg_out_ldstm(s, COND_AL, INSN_LDMIA, TCG_REG_CALL_STACK, 3188 (1 << TCG_REG_R4) | (1 << TCG_REG_R5) | (1 << TCG_REG_R6) | 3189 (1 << TCG_REG_R7) | (1 << TCG_REG_R8) | (1 << TCG_REG_R9) | 3190 (1 << TCG_REG_R10) | (1 << TCG_REG_R11) | (1 << TCG_REG_PC)); 3191} 3192 3193static void tcg_out_tb_start(TCGContext *s) 3194{ 3195 /* nothing to do */ 3196} 3197 3198typedef struct { 3199 DebugFrameHeader h; 3200 uint8_t fde_def_cfa[4]; 3201 uint8_t fde_reg_ofs[18]; 3202} DebugFrame; 3203 3204#define ELF_HOST_MACHINE EM_ARM 3205 3206/* We're expecting a 2 byte uleb128 encoded value. */ 3207QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); 3208 3209static const DebugFrame debug_frame = { 3210 .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ 3211 .h.cie.id = -1, 3212 .h.cie.version = 1, 3213 .h.cie.code_align = 1, 3214 .h.cie.data_align = 0x7c, /* sleb128 -4 */ 3215 .h.cie.return_column = 14, 3216 3217 /* Total FDE size does not include the "len" member. */ 3218 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 3219 3220 .fde_def_cfa = { 3221 12, 13, /* DW_CFA_def_cfa sp, ... */ 3222 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 3223 (FRAME_SIZE >> 7) 3224 }, 3225 .fde_reg_ofs = { 3226 /* The following must match the stmdb in the prologue. */ 3227 0x8e, 1, /* DW_CFA_offset, lr, -4 */ 3228 0x8b, 2, /* DW_CFA_offset, r11, -8 */ 3229 0x8a, 3, /* DW_CFA_offset, r10, -12 */ 3230 0x89, 4, /* DW_CFA_offset, r9, -16 */ 3231 0x88, 5, /* DW_CFA_offset, r8, -20 */ 3232 0x87, 6, /* DW_CFA_offset, r7, -24 */ 3233 0x86, 7, /* DW_CFA_offset, r6, -28 */ 3234 0x85, 8, /* DW_CFA_offset, r5, -32 */ 3235 0x84, 9, /* DW_CFA_offset, r4, -36 */ 3236 } 3237}; 3238 3239void tcg_register_jit(const void *buf, size_t buf_size) 3240{ 3241 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 3242} 3243