1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Andrzej Zaborowski 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25#include "elf.h" 26 27int arm_arch = __ARM_ARCH; 28 29#ifndef use_idiv_instructions 30bool use_idiv_instructions; 31#endif 32#ifndef use_neon_instructions 33bool use_neon_instructions; 34#endif 35 36/* Used for function call generation. */ 37#define TCG_TARGET_STACK_ALIGN 8 38#define TCG_TARGET_CALL_STACK_OFFSET 0 39#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL 40#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN 41#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN 42#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF 43 44#ifdef CONFIG_DEBUG_TCG 45static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 46 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", 47 "%r8", "%r9", "%r10", "%r11", "%r12", "%sp", "%r14", "%pc", 48 "%q0", "%q1", "%q2", "%q3", "%q4", "%q5", "%q6", "%q7", 49 "%q8", "%q9", "%q10", "%q11", "%q12", "%q13", "%q14", "%q15", 50}; 51#endif 52 53static const int tcg_target_reg_alloc_order[] = { 54 TCG_REG_R4, 55 TCG_REG_R5, 56 TCG_REG_R6, 57 TCG_REG_R7, 58 TCG_REG_R8, 59 TCG_REG_R9, 60 TCG_REG_R10, 61 TCG_REG_R11, 62 TCG_REG_R13, 63 TCG_REG_R0, 64 TCG_REG_R1, 65 TCG_REG_R2, 66 TCG_REG_R3, 67 TCG_REG_R12, 68 TCG_REG_R14, 69 70 TCG_REG_Q0, 71 TCG_REG_Q1, 72 TCG_REG_Q2, 73 TCG_REG_Q3, 74 /* Q4 - Q7 are call-saved, and skipped. */ 75 TCG_REG_Q8, 76 TCG_REG_Q9, 77 TCG_REG_Q10, 78 TCG_REG_Q11, 79 TCG_REG_Q12, 80 TCG_REG_Q13, 81 TCG_REG_Q14, 82 TCG_REG_Q15, 83}; 84 85static const int tcg_target_call_iarg_regs[4] = { 86 TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3 87}; 88 89static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 90{ 91 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 92 tcg_debug_assert(slot >= 0 && slot <= 3); 93 return TCG_REG_R0 + slot; 94} 95 96#define TCG_REG_TMP TCG_REG_R12 97#define TCG_VEC_TMP TCG_REG_Q15 98#define TCG_REG_GUEST_BASE TCG_REG_R11 99 100typedef enum { 101 COND_EQ = 0x0, 102 COND_NE = 0x1, 103 COND_CS = 0x2, /* Unsigned greater or equal */ 104 COND_CC = 0x3, /* Unsigned less than */ 105 COND_MI = 0x4, /* Negative */ 106 COND_PL = 0x5, /* Zero or greater */ 107 COND_VS = 0x6, /* Overflow */ 108 COND_VC = 0x7, /* No overflow */ 109 COND_HI = 0x8, /* Unsigned greater than */ 110 COND_LS = 0x9, /* Unsigned less or equal */ 111 COND_GE = 0xa, 112 COND_LT = 0xb, 113 COND_GT = 0xc, 114 COND_LE = 0xd, 115 COND_AL = 0xe, 116} ARMCond; 117 118#define TO_CPSR (1 << 20) 119 120#define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00) 121#define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20) 122#define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40) 123#define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60) 124#define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10) 125#define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30) 126#define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50) 127#define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70) 128 129typedef enum { 130 ARITH_AND = 0x0 << 21, 131 ARITH_EOR = 0x1 << 21, 132 ARITH_SUB = 0x2 << 21, 133 ARITH_RSB = 0x3 << 21, 134 ARITH_ADD = 0x4 << 21, 135 ARITH_ADC = 0x5 << 21, 136 ARITH_SBC = 0x6 << 21, 137 ARITH_RSC = 0x7 << 21, 138 ARITH_TST = 0x8 << 21 | TO_CPSR, 139 ARITH_CMP = 0xa << 21 | TO_CPSR, 140 ARITH_CMN = 0xb << 21 | TO_CPSR, 141 ARITH_ORR = 0xc << 21, 142 ARITH_MOV = 0xd << 21, 143 ARITH_BIC = 0xe << 21, 144 ARITH_MVN = 0xf << 21, 145 146 INSN_B = 0x0a000000, 147 148 INSN_CLZ = 0x016f0f10, 149 INSN_RBIT = 0x06ff0f30, 150 151 INSN_LDMIA = 0x08b00000, 152 INSN_STMDB = 0x09200000, 153 154 INSN_LDR_IMM = 0x04100000, 155 INSN_LDR_REG = 0x06100000, 156 INSN_STR_IMM = 0x04000000, 157 INSN_STR_REG = 0x06000000, 158 159 INSN_LDRH_IMM = 0x005000b0, 160 INSN_LDRH_REG = 0x001000b0, 161 INSN_LDRSH_IMM = 0x005000f0, 162 INSN_LDRSH_REG = 0x001000f0, 163 INSN_STRH_IMM = 0x004000b0, 164 INSN_STRH_REG = 0x000000b0, 165 166 INSN_LDRB_IMM = 0x04500000, 167 INSN_LDRB_REG = 0x06500000, 168 INSN_LDRSB_IMM = 0x005000d0, 169 INSN_LDRSB_REG = 0x001000d0, 170 INSN_STRB_IMM = 0x04400000, 171 INSN_STRB_REG = 0x06400000, 172 173 INSN_LDRD_IMM = 0x004000d0, 174 INSN_LDRD_REG = 0x000000d0, 175 INSN_STRD_IMM = 0x004000f0, 176 INSN_STRD_REG = 0x000000f0, 177 178 INSN_DMB_ISH = 0xf57ff05b, 179 INSN_DMB_MCR = 0xee070fba, 180 181 /* Architected nop introduced in v6k. */ 182 /* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this 183 also Just So Happened to do nothing on pre-v6k so that we 184 don't need to conditionalize it? */ 185 INSN_NOP_v6k = 0xe320f000, 186 /* Otherwise the assembler uses mov r0,r0 */ 187 INSN_NOP_v4 = (COND_AL << 28) | ARITH_MOV, 188 189 INSN_VADD = 0xf2000800, 190 INSN_VAND = 0xf2000110, 191 INSN_VBIC = 0xf2100110, 192 INSN_VEOR = 0xf3000110, 193 INSN_VORN = 0xf2300110, 194 INSN_VORR = 0xf2200110, 195 INSN_VSUB = 0xf3000800, 196 INSN_VMUL = 0xf2000910, 197 INSN_VQADD = 0xf2000010, 198 INSN_VQADD_U = 0xf3000010, 199 INSN_VQSUB = 0xf2000210, 200 INSN_VQSUB_U = 0xf3000210, 201 INSN_VMAX = 0xf2000600, 202 INSN_VMAX_U = 0xf3000600, 203 INSN_VMIN = 0xf2000610, 204 INSN_VMIN_U = 0xf3000610, 205 206 INSN_VABS = 0xf3b10300, 207 INSN_VMVN = 0xf3b00580, 208 INSN_VNEG = 0xf3b10380, 209 210 INSN_VCEQ0 = 0xf3b10100, 211 INSN_VCGT0 = 0xf3b10000, 212 INSN_VCGE0 = 0xf3b10080, 213 INSN_VCLE0 = 0xf3b10180, 214 INSN_VCLT0 = 0xf3b10200, 215 216 INSN_VCEQ = 0xf3000810, 217 INSN_VCGE = 0xf2000310, 218 INSN_VCGT = 0xf2000300, 219 INSN_VCGE_U = 0xf3000310, 220 INSN_VCGT_U = 0xf3000300, 221 222 INSN_VSHLI = 0xf2800510, /* VSHL (immediate) */ 223 INSN_VSARI = 0xf2800010, /* VSHR.S */ 224 INSN_VSHRI = 0xf3800010, /* VSHR.U */ 225 INSN_VSLI = 0xf3800510, 226 INSN_VSHL_S = 0xf2000400, /* VSHL.S (register) */ 227 INSN_VSHL_U = 0xf3000400, /* VSHL.U (register) */ 228 229 INSN_VBSL = 0xf3100110, 230 INSN_VBIT = 0xf3200110, 231 INSN_VBIF = 0xf3300110, 232 233 INSN_VTST = 0xf2000810, 234 235 INSN_VDUP_G = 0xee800b10, /* VDUP (ARM core register) */ 236 INSN_VDUP_S = 0xf3b00c00, /* VDUP (scalar) */ 237 INSN_VLDR_D = 0xed100b00, /* VLDR.64 */ 238 INSN_VLD1 = 0xf4200000, /* VLD1 (multiple single elements) */ 239 INSN_VLD1R = 0xf4a00c00, /* VLD1 (single element to all lanes) */ 240 INSN_VST1 = 0xf4000000, /* VST1 (multiple single elements) */ 241 INSN_VMOVI = 0xf2800010, /* VMOV (immediate) */ 242} ARMInsn; 243 244#define INSN_NOP (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4) 245 246static const uint8_t tcg_cond_to_arm_cond[] = { 247 [TCG_COND_EQ] = COND_EQ, 248 [TCG_COND_NE] = COND_NE, 249 [TCG_COND_LT] = COND_LT, 250 [TCG_COND_GE] = COND_GE, 251 [TCG_COND_LE] = COND_LE, 252 [TCG_COND_GT] = COND_GT, 253 /* unsigned */ 254 [TCG_COND_LTU] = COND_CC, 255 [TCG_COND_GEU] = COND_CS, 256 [TCG_COND_LEU] = COND_LS, 257 [TCG_COND_GTU] = COND_HI, 258}; 259 260static int encode_imm(uint32_t imm); 261 262/* TCG private relocation type: add with pc+imm8 */ 263#define R_ARM_PC8 11 264 265/* TCG private relocation type: vldr with imm8 << 2 */ 266#define R_ARM_PC11 12 267 268static bool reloc_pc24(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 269{ 270 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 271 ptrdiff_t offset = (tcg_ptr_byte_diff(target, src_rx) - 8) >> 2; 272 273 if (offset == sextract32(offset, 0, 24)) { 274 *src_rw = deposit32(*src_rw, 0, 24, offset); 275 return true; 276 } 277 return false; 278} 279 280static bool reloc_pc13(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 281{ 282 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 283 ptrdiff_t offset = tcg_ptr_byte_diff(target, src_rx) - 8; 284 285 if (offset >= -0xfff && offset <= 0xfff) { 286 tcg_insn_unit insn = *src_rw; 287 bool u = (offset >= 0); 288 if (!u) { 289 offset = -offset; 290 } 291 insn = deposit32(insn, 23, 1, u); 292 insn = deposit32(insn, 0, 12, offset); 293 *src_rw = insn; 294 return true; 295 } 296 return false; 297} 298 299static bool reloc_pc11(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 300{ 301 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 302 ptrdiff_t offset = (tcg_ptr_byte_diff(target, src_rx) - 8) / 4; 303 304 if (offset >= -0xff && offset <= 0xff) { 305 tcg_insn_unit insn = *src_rw; 306 bool u = (offset >= 0); 307 if (!u) { 308 offset = -offset; 309 } 310 insn = deposit32(insn, 23, 1, u); 311 insn = deposit32(insn, 0, 8, offset); 312 *src_rw = insn; 313 return true; 314 } 315 return false; 316} 317 318static bool reloc_pc8(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 319{ 320 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 321 ptrdiff_t offset = tcg_ptr_byte_diff(target, src_rx) - 8; 322 int imm12 = encode_imm(offset); 323 324 if (imm12 >= 0) { 325 *src_rw = deposit32(*src_rw, 0, 12, imm12); 326 return true; 327 } 328 return false; 329} 330 331static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 332 intptr_t value, intptr_t addend) 333{ 334 tcg_debug_assert(addend == 0); 335 switch (type) { 336 case R_ARM_PC24: 337 return reloc_pc24(code_ptr, (const tcg_insn_unit *)value); 338 case R_ARM_PC13: 339 return reloc_pc13(code_ptr, (const tcg_insn_unit *)value); 340 case R_ARM_PC11: 341 return reloc_pc11(code_ptr, (const tcg_insn_unit *)value); 342 case R_ARM_PC8: 343 return reloc_pc8(code_ptr, (const tcg_insn_unit *)value); 344 default: 345 g_assert_not_reached(); 346 } 347} 348 349#define TCG_CT_CONST_ARM 0x100 350#define TCG_CT_CONST_INV 0x200 351#define TCG_CT_CONST_NEG 0x400 352#define TCG_CT_CONST_ZERO 0x800 353#define TCG_CT_CONST_ORRI 0x1000 354#define TCG_CT_CONST_ANDI 0x2000 355 356#define ALL_GENERAL_REGS 0xffffu 357#define ALL_VECTOR_REGS 0xffff0000u 358 359/* 360 * r0-r3 will be overwritten when reading the tlb entry (system-mode only); 361 * r14 will be overwritten by the BLNE branching to the slow path. 362 */ 363#define ALL_QLDST_REGS \ 364 (ALL_GENERAL_REGS & ~((tcg_use_softmmu ? 0xf : 0) | (1 << TCG_REG_R14))) 365 366/* 367 * ARM immediates for ALU instructions are made of an unsigned 8-bit 368 * right-rotated by an even amount between 0 and 30. 369 * 370 * Return < 0 if @imm cannot be encoded, else the entire imm12 field. 371 */ 372static int encode_imm(uint32_t imm) 373{ 374 uint32_t rot, imm8; 375 376 /* Simple case, no rotation required. */ 377 if ((imm & ~0xff) == 0) { 378 return imm; 379 } 380 381 /* Next, try a simple even shift. */ 382 rot = ctz32(imm) & ~1; 383 imm8 = imm >> rot; 384 rot = 32 - rot; 385 if ((imm8 & ~0xff) == 0) { 386 goto found; 387 } 388 389 /* 390 * Finally, try harder with rotations. 391 * The ctz test above will have taken care of rotates >= 8. 392 */ 393 for (rot = 2; rot < 8; rot += 2) { 394 imm8 = rol32(imm, rot); 395 if ((imm8 & ~0xff) == 0) { 396 goto found; 397 } 398 } 399 /* Fail: imm cannot be encoded. */ 400 return -1; 401 402 found: 403 /* Note that rot is even, and we discard bit 0 by shifting by 7. */ 404 return rot << 7 | imm8; 405} 406 407static int encode_imm_nofail(uint32_t imm) 408{ 409 int ret = encode_imm(imm); 410 tcg_debug_assert(ret >= 0); 411 return ret; 412} 413 414static bool check_fit_imm(uint32_t imm) 415{ 416 return encode_imm(imm) >= 0; 417} 418 419/* Return true if v16 is a valid 16-bit shifted immediate. */ 420static bool is_shimm16(uint16_t v16, int *cmode, int *imm8) 421{ 422 if (v16 == (v16 & 0xff)) { 423 *cmode = 0x8; 424 *imm8 = v16 & 0xff; 425 return true; 426 } else if (v16 == (v16 & 0xff00)) { 427 *cmode = 0xa; 428 *imm8 = v16 >> 8; 429 return true; 430 } 431 return false; 432} 433 434/* Return true if v32 is a valid 32-bit shifted immediate. */ 435static bool is_shimm32(uint32_t v32, int *cmode, int *imm8) 436{ 437 if (v32 == (v32 & 0xff)) { 438 *cmode = 0x0; 439 *imm8 = v32 & 0xff; 440 return true; 441 } else if (v32 == (v32 & 0xff00)) { 442 *cmode = 0x2; 443 *imm8 = (v32 >> 8) & 0xff; 444 return true; 445 } else if (v32 == (v32 & 0xff0000)) { 446 *cmode = 0x4; 447 *imm8 = (v32 >> 16) & 0xff; 448 return true; 449 } else if (v32 == (v32 & 0xff000000)) { 450 *cmode = 0x6; 451 *imm8 = v32 >> 24; 452 return true; 453 } 454 return false; 455} 456 457/* Return true if v32 is a valid 32-bit shifting ones immediate. */ 458static bool is_soimm32(uint32_t v32, int *cmode, int *imm8) 459{ 460 if ((v32 & 0xffff00ff) == 0xff) { 461 *cmode = 0xc; 462 *imm8 = (v32 >> 8) & 0xff; 463 return true; 464 } else if ((v32 & 0xff00ffff) == 0xffff) { 465 *cmode = 0xd; 466 *imm8 = (v32 >> 16) & 0xff; 467 return true; 468 } 469 return false; 470} 471 472/* 473 * Return non-zero if v32 can be formed by MOVI+ORR. 474 * Place the parameters for MOVI in (cmode, imm8). 475 * Return the cmode for ORR; the imm8 can be had via extraction from v32. 476 */ 477static int is_shimm32_pair(uint32_t v32, int *cmode, int *imm8) 478{ 479 int i; 480 481 for (i = 6; i > 0; i -= 2) { 482 /* Mask out one byte we can add with ORR. */ 483 uint32_t tmp = v32 & ~(0xffu << (i * 4)); 484 if (is_shimm32(tmp, cmode, imm8) || 485 is_soimm32(tmp, cmode, imm8)) { 486 break; 487 } 488 } 489 return i; 490} 491 492/* Return true if V is a valid 16-bit or 32-bit shifted immediate. */ 493static bool is_shimm1632(uint32_t v32, int *cmode, int *imm8) 494{ 495 if (v32 == deposit32(v32, 16, 16, v32)) { 496 return is_shimm16(v32, cmode, imm8); 497 } else { 498 return is_shimm32(v32, cmode, imm8); 499 } 500} 501 502/* Test if a constant matches the constraint. 503 * TODO: define constraints for: 504 * 505 * ldr/str offset: between -0xfff and 0xfff 506 * ldrh/strh offset: between -0xff and 0xff 507 * mov operand2: values represented with x << (2 * y), x < 0x100 508 * add, sub, eor...: ditto 509 */ 510static bool tcg_target_const_match(int64_t val, int ct, 511 TCGType type, TCGCond cond, int vece) 512{ 513 if (ct & TCG_CT_CONST) { 514 return 1; 515 } else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val)) { 516 return 1; 517 } else if ((ct & TCG_CT_CONST_INV) && check_fit_imm(~val)) { 518 return 1; 519 } else if ((ct & TCG_CT_CONST_NEG) && check_fit_imm(-val)) { 520 return 1; 521 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 522 return 1; 523 } 524 525 switch (ct & (TCG_CT_CONST_ORRI | TCG_CT_CONST_ANDI)) { 526 case 0: 527 break; 528 case TCG_CT_CONST_ANDI: 529 val = ~val; 530 /* fallthru */ 531 case TCG_CT_CONST_ORRI: 532 if (val == deposit64(val, 32, 32, val)) { 533 int cmode, imm8; 534 return is_shimm1632(val, &cmode, &imm8); 535 } 536 break; 537 default: 538 /* Both bits should not be set for the same insn. */ 539 g_assert_not_reached(); 540 } 541 542 return 0; 543} 544 545static void tcg_out_b_imm(TCGContext *s, ARMCond cond, int32_t offset) 546{ 547 tcg_out32(s, (cond << 28) | INSN_B | 548 (((offset - 8) >> 2) & 0x00ffffff)); 549} 550 551static void tcg_out_bl_imm(TCGContext *s, ARMCond cond, int32_t offset) 552{ 553 tcg_out32(s, (cond << 28) | 0x0b000000 | 554 (((offset - 8) >> 2) & 0x00ffffff)); 555} 556 557static void tcg_out_blx_reg(TCGContext *s, ARMCond cond, TCGReg rn) 558{ 559 tcg_out32(s, (cond << 28) | 0x012fff30 | rn); 560} 561 562static void tcg_out_blx_imm(TCGContext *s, int32_t offset) 563{ 564 tcg_out32(s, 0xfa000000 | ((offset & 2) << 23) | 565 (((offset - 8) >> 2) & 0x00ffffff)); 566} 567 568static void tcg_out_dat_reg(TCGContext *s, ARMCond cond, ARMInsn opc, 569 TCGReg rd, TCGReg rn, TCGReg rm, int shift) 570{ 571 tcg_out32(s, (cond << 28) | (0 << 25) | opc | 572 (rn << 16) | (rd << 12) | shift | rm); 573} 574 575static void tcg_out_mov_reg(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rm) 576{ 577 /* Simple reg-reg move, optimising out the 'do nothing' case */ 578 if (rd != rm) { 579 tcg_out_dat_reg(s, cond, ARITH_MOV, rd, 0, rm, SHIFT_IMM_LSL(0)); 580 } 581} 582 583static void tcg_out_bx_reg(TCGContext *s, ARMCond cond, TCGReg rn) 584{ 585 tcg_out32(s, (cond << 28) | 0x012fff10 | rn); 586} 587 588static void tcg_out_b_reg(TCGContext *s, ARMCond cond, TCGReg rn) 589{ 590 /* 591 * Unless the C portion of QEMU is compiled as thumb, we don't need 592 * true BX semantics; merely a branch to an address held in a register. 593 */ 594 tcg_out_bx_reg(s, cond, rn); 595} 596 597static void tcg_out_dat_imm(TCGContext *s, ARMCond cond, ARMInsn opc, 598 TCGReg rd, TCGReg rn, int im) 599{ 600 tcg_out32(s, (cond << 28) | (1 << 25) | opc | 601 (rn << 16) | (rd << 12) | im); 602} 603 604static void tcg_out_ldstm(TCGContext *s, ARMCond cond, ARMInsn opc, 605 TCGReg rn, uint16_t mask) 606{ 607 tcg_out32(s, (cond << 28) | opc | (rn << 16) | mask); 608} 609 610/* Note that this routine is used for both LDR and LDRH formats, so we do 611 not wish to include an immediate shift at this point. */ 612static void tcg_out_memop_r(TCGContext *s, ARMCond cond, ARMInsn opc, TCGReg rt, 613 TCGReg rn, TCGReg rm, bool u, bool p, bool w) 614{ 615 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) 616 | (w << 21) | (rn << 16) | (rt << 12) | rm); 617} 618 619static void tcg_out_memop_8(TCGContext *s, ARMCond cond, ARMInsn opc, TCGReg rt, 620 TCGReg rn, int imm8, bool p, bool w) 621{ 622 bool u = 1; 623 if (imm8 < 0) { 624 imm8 = -imm8; 625 u = 0; 626 } 627 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | 628 (rn << 16) | (rt << 12) | ((imm8 & 0xf0) << 4) | (imm8 & 0xf)); 629} 630 631static void tcg_out_memop_12(TCGContext *s, ARMCond cond, ARMInsn opc, 632 TCGReg rt, TCGReg rn, int imm12, bool p, bool w) 633{ 634 bool u = 1; 635 if (imm12 < 0) { 636 imm12 = -imm12; 637 u = 0; 638 } 639 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | 640 (rn << 16) | (rt << 12) | imm12); 641} 642 643static void tcg_out_ld32_12(TCGContext *s, ARMCond cond, TCGReg rt, 644 TCGReg rn, int imm12) 645{ 646 tcg_out_memop_12(s, cond, INSN_LDR_IMM, rt, rn, imm12, 1, 0); 647} 648 649static void tcg_out_st32_12(TCGContext *s, ARMCond cond, TCGReg rt, 650 TCGReg rn, int imm12) 651{ 652 tcg_out_memop_12(s, cond, INSN_STR_IMM, rt, rn, imm12, 1, 0); 653} 654 655static void tcg_out_ld32_r(TCGContext *s, ARMCond cond, TCGReg rt, 656 TCGReg rn, TCGReg rm) 657{ 658 tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 0); 659} 660 661static void tcg_out_st32_r(TCGContext *s, ARMCond cond, TCGReg rt, 662 TCGReg rn, TCGReg rm) 663{ 664 tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 0); 665} 666 667static void tcg_out_ldrd_8(TCGContext *s, ARMCond cond, TCGReg rt, 668 TCGReg rn, int imm8) 669{ 670 tcg_out_memop_8(s, cond, INSN_LDRD_IMM, rt, rn, imm8, 1, 0); 671} 672 673static void tcg_out_ldrd_r(TCGContext *s, ARMCond cond, TCGReg rt, 674 TCGReg rn, TCGReg rm) 675{ 676 tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 0); 677} 678 679static void tcg_out_strd_8(TCGContext *s, ARMCond cond, TCGReg rt, 680 TCGReg rn, int imm8) 681{ 682 tcg_out_memop_8(s, cond, INSN_STRD_IMM, rt, rn, imm8, 1, 0); 683} 684 685static void tcg_out_strd_r(TCGContext *s, ARMCond cond, TCGReg rt, 686 TCGReg rn, TCGReg rm) 687{ 688 tcg_out_memop_r(s, cond, INSN_STRD_REG, rt, rn, rm, 1, 1, 0); 689} 690 691/* Register pre-increment with base writeback. */ 692static void tcg_out_ld32_rwb(TCGContext *s, ARMCond cond, TCGReg rt, 693 TCGReg rn, TCGReg rm) 694{ 695 tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 1); 696} 697 698static void tcg_out_st32_rwb(TCGContext *s, ARMCond cond, TCGReg rt, 699 TCGReg rn, TCGReg rm) 700{ 701 tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 1); 702} 703 704static void tcg_out_ld16u_8(TCGContext *s, ARMCond cond, TCGReg rt, 705 TCGReg rn, int imm8) 706{ 707 tcg_out_memop_8(s, cond, INSN_LDRH_IMM, rt, rn, imm8, 1, 0); 708} 709 710static void tcg_out_st16_8(TCGContext *s, ARMCond cond, TCGReg rt, 711 TCGReg rn, int imm8) 712{ 713 tcg_out_memop_8(s, cond, INSN_STRH_IMM, rt, rn, imm8, 1, 0); 714} 715 716static void tcg_out_ld16u_r(TCGContext *s, ARMCond cond, TCGReg rt, 717 TCGReg rn, TCGReg rm) 718{ 719 tcg_out_memop_r(s, cond, INSN_LDRH_REG, rt, rn, rm, 1, 1, 0); 720} 721 722static void tcg_out_st16_r(TCGContext *s, ARMCond cond, TCGReg rt, 723 TCGReg rn, TCGReg rm) 724{ 725 tcg_out_memop_r(s, cond, INSN_STRH_REG, rt, rn, rm, 1, 1, 0); 726} 727 728static void tcg_out_ld16s_8(TCGContext *s, ARMCond cond, TCGReg rt, 729 TCGReg rn, int imm8) 730{ 731 tcg_out_memop_8(s, cond, INSN_LDRSH_IMM, rt, rn, imm8, 1, 0); 732} 733 734static void tcg_out_ld16s_r(TCGContext *s, ARMCond cond, TCGReg rt, 735 TCGReg rn, TCGReg rm) 736{ 737 tcg_out_memop_r(s, cond, INSN_LDRSH_REG, rt, rn, rm, 1, 1, 0); 738} 739 740static void tcg_out_ld8_12(TCGContext *s, ARMCond cond, TCGReg rt, 741 TCGReg rn, int imm12) 742{ 743 tcg_out_memop_12(s, cond, INSN_LDRB_IMM, rt, rn, imm12, 1, 0); 744} 745 746static void tcg_out_st8_12(TCGContext *s, ARMCond cond, TCGReg rt, 747 TCGReg rn, int imm12) 748{ 749 tcg_out_memop_12(s, cond, INSN_STRB_IMM, rt, rn, imm12, 1, 0); 750} 751 752static void tcg_out_ld8_r(TCGContext *s, ARMCond cond, TCGReg rt, 753 TCGReg rn, TCGReg rm) 754{ 755 tcg_out_memop_r(s, cond, INSN_LDRB_REG, rt, rn, rm, 1, 1, 0); 756} 757 758static void tcg_out_st8_r(TCGContext *s, ARMCond cond, TCGReg rt, 759 TCGReg rn, TCGReg rm) 760{ 761 tcg_out_memop_r(s, cond, INSN_STRB_REG, rt, rn, rm, 1, 1, 0); 762} 763 764static void tcg_out_ld8s_8(TCGContext *s, ARMCond cond, TCGReg rt, 765 TCGReg rn, int imm8) 766{ 767 tcg_out_memop_8(s, cond, INSN_LDRSB_IMM, rt, rn, imm8, 1, 0); 768} 769 770static void tcg_out_ld8s_r(TCGContext *s, ARMCond cond, TCGReg rt, 771 TCGReg rn, TCGReg rm) 772{ 773 tcg_out_memop_r(s, cond, INSN_LDRSB_REG, rt, rn, rm, 1, 1, 0); 774} 775 776static void tcg_out_movi_pool(TCGContext *s, ARMCond cond, 777 TCGReg rd, uint32_t arg) 778{ 779 new_pool_label(s, arg, R_ARM_PC13, s->code_ptr, 0); 780 tcg_out_ld32_12(s, cond, rd, TCG_REG_PC, 0); 781} 782 783static void tcg_out_movi32(TCGContext *s, ARMCond cond, 784 TCGReg rd, uint32_t arg) 785{ 786 int imm12, diff, opc, sh1, sh2; 787 uint32_t tt0, tt1, tt2; 788 789 /* Check a single MOV/MVN before anything else. */ 790 imm12 = encode_imm(arg); 791 if (imm12 >= 0) { 792 tcg_out_dat_imm(s, cond, ARITH_MOV, rd, 0, imm12); 793 return; 794 } 795 imm12 = encode_imm(~arg); 796 if (imm12 >= 0) { 797 tcg_out_dat_imm(s, cond, ARITH_MVN, rd, 0, imm12); 798 return; 799 } 800 801 /* Check for a pc-relative address. This will usually be the TB, 802 or within the TB, which is immediately before the code block. */ 803 diff = tcg_pcrel_diff(s, (void *)arg) - 8; 804 if (diff >= 0) { 805 imm12 = encode_imm(diff); 806 if (imm12 >= 0) { 807 tcg_out_dat_imm(s, cond, ARITH_ADD, rd, TCG_REG_PC, imm12); 808 return; 809 } 810 } else { 811 imm12 = encode_imm(-diff); 812 if (imm12 >= 0) { 813 tcg_out_dat_imm(s, cond, ARITH_SUB, rd, TCG_REG_PC, imm12); 814 return; 815 } 816 } 817 818 /* Use movw + movt. */ 819 if (use_armv7_instructions) { 820 /* movw */ 821 tcg_out32(s, (cond << 28) | 0x03000000 | (rd << 12) 822 | ((arg << 4) & 0x000f0000) | (arg & 0xfff)); 823 if (arg & 0xffff0000) { 824 /* movt */ 825 tcg_out32(s, (cond << 28) | 0x03400000 | (rd << 12) 826 | ((arg >> 12) & 0x000f0000) | ((arg >> 16) & 0xfff)); 827 } 828 return; 829 } 830 831 /* Look for sequences of two insns. If we have lots of 1's, we can 832 shorten the sequence by beginning with mvn and then clearing 833 higher bits with eor. */ 834 tt0 = arg; 835 opc = ARITH_MOV; 836 if (ctpop32(arg) > 16) { 837 tt0 = ~arg; 838 opc = ARITH_MVN; 839 } 840 sh1 = ctz32(tt0) & ~1; 841 tt1 = tt0 & ~(0xff << sh1); 842 sh2 = ctz32(tt1) & ~1; 843 tt2 = tt1 & ~(0xff << sh2); 844 if (tt2 == 0) { 845 int rot; 846 847 rot = ((32 - sh1) << 7) & 0xf00; 848 tcg_out_dat_imm(s, cond, opc, rd, 0, ((tt0 >> sh1) & 0xff) | rot); 849 rot = ((32 - sh2) << 7) & 0xf00; 850 tcg_out_dat_imm(s, cond, ARITH_EOR, rd, rd, 851 ((tt0 >> sh2) & 0xff) | rot); 852 return; 853 } 854 855 /* Otherwise, drop it into the constant pool. */ 856 tcg_out_movi_pool(s, cond, rd, arg); 857} 858 859/* 860 * Emit either the reg,imm or reg,reg form of a data-processing insn. 861 * rhs must satisfy the "rI" constraint. 862 */ 863static void tcg_out_dat_rI(TCGContext *s, ARMCond cond, ARMInsn opc, 864 TCGReg dst, TCGReg lhs, TCGArg rhs, int rhs_is_const) 865{ 866 if (rhs_is_const) { 867 tcg_out_dat_imm(s, cond, opc, dst, lhs, encode_imm_nofail(rhs)); 868 } else { 869 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); 870 } 871} 872 873/* 874 * Emit either the reg,imm or reg,reg form of a data-processing insn. 875 * rhs must satisfy the "rIK" constraint. 876 */ 877static void tcg_out_dat_IK(TCGContext *s, ARMCond cond, ARMInsn opc, 878 ARMInsn opinv, TCGReg dst, TCGReg lhs, TCGArg rhs) 879{ 880 int imm12 = encode_imm(rhs); 881 if (imm12 < 0) { 882 imm12 = encode_imm_nofail(~rhs); 883 opc = opinv; 884 } 885 tcg_out_dat_imm(s, cond, opc, dst, lhs, imm12); 886} 887 888static void tcg_out_dat_rIK(TCGContext *s, ARMCond cond, ARMInsn opc, 889 ARMInsn opinv, TCGReg dst, TCGReg lhs, TCGArg rhs, 890 bool rhs_is_const) 891{ 892 if (rhs_is_const) { 893 tcg_out_dat_IK(s, cond, opc, opinv, dst, lhs, rhs); 894 } else { 895 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); 896 } 897} 898 899static void tcg_out_dat_IN(TCGContext *s, ARMCond cond, ARMInsn opc, 900 ARMInsn opneg, TCGReg dst, TCGReg lhs, TCGArg rhs) 901{ 902 int imm12 = encode_imm(rhs); 903 if (imm12 < 0) { 904 imm12 = encode_imm_nofail(-rhs); 905 opc = opneg; 906 } 907 tcg_out_dat_imm(s, cond, opc, dst, lhs, imm12); 908} 909 910static void tcg_out_dat_rIN(TCGContext *s, ARMCond cond, ARMInsn opc, 911 ARMInsn opneg, TCGReg dst, TCGReg lhs, TCGArg rhs, 912 bool rhs_is_const) 913{ 914 /* Emit either the reg,imm or reg,reg form of a data-processing insn. 915 * rhs must satisfy the "rIN" constraint. 916 */ 917 if (rhs_is_const) { 918 tcg_out_dat_IN(s, cond, opc, opneg, dst, lhs, rhs); 919 } else { 920 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); 921 } 922} 923 924static void tcg_out_umull32(TCGContext *s, ARMCond cond, TCGReg rd0, 925 TCGReg rd1, TCGReg rn, TCGReg rm) 926{ 927 /* umull */ 928 tcg_out32(s, (cond << 28) | 0x00800090 | 929 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); 930} 931 932static void tcg_out_smull32(TCGContext *s, ARMCond cond, TCGReg rd0, 933 TCGReg rd1, TCGReg rn, TCGReg rm) 934{ 935 /* smull */ 936 tcg_out32(s, (cond << 28) | 0x00c00090 | 937 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); 938} 939 940static void tcg_out_sdiv(TCGContext *s, ARMCond cond, 941 TCGReg rd, TCGReg rn, TCGReg rm) 942{ 943 tcg_out32(s, 0x0710f010 | (cond << 28) | (rd << 16) | rn | (rm << 8)); 944} 945 946static void tcg_out_udiv(TCGContext *s, ARMCond cond, 947 TCGReg rd, TCGReg rn, TCGReg rm) 948{ 949 tcg_out32(s, 0x0730f010 | (cond << 28) | (rd << 16) | rn | (rm << 8)); 950} 951 952static void tcg_out_ext8s(TCGContext *s, TCGType t, TCGReg rd, TCGReg rn) 953{ 954 /* sxtb */ 955 tcg_out32(s, 0x06af0070 | (COND_AL << 28) | (rd << 12) | rn); 956} 957 958static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rn) 959{ 960 tcg_out_dat_imm(s, COND_AL, ARITH_AND, rd, rn, 0xff); 961} 962 963static void tcg_out_ext16s(TCGContext *s, TCGType t, TCGReg rd, TCGReg rn) 964{ 965 /* sxth */ 966 tcg_out32(s, 0x06bf0070 | (COND_AL << 28) | (rd << 12) | rn); 967} 968 969static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rn) 970{ 971 /* uxth */ 972 tcg_out32(s, 0x06ff0070 | (COND_AL << 28) | (rd << 12) | rn); 973} 974 975static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rn) 976{ 977 g_assert_not_reached(); 978} 979 980static void tcg_out_ext32u(TCGContext *s, TCGReg rd, TCGReg rn) 981{ 982 g_assert_not_reached(); 983} 984 985static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rn) 986{ 987 g_assert_not_reached(); 988} 989 990static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rn) 991{ 992 g_assert_not_reached(); 993} 994 995static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rn) 996{ 997 g_assert_not_reached(); 998} 999 1000static void tcg_out_bswap16(TCGContext *s, ARMCond cond, 1001 TCGReg rd, TCGReg rn, int flags) 1002{ 1003 if (flags & TCG_BSWAP_OS) { 1004 /* revsh */ 1005 tcg_out32(s, 0x06ff0fb0 | (cond << 28) | (rd << 12) | rn); 1006 return; 1007 } 1008 1009 /* rev16 */ 1010 tcg_out32(s, 0x06bf0fb0 | (cond << 28) | (rd << 12) | rn); 1011 if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 1012 /* uxth */ 1013 tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | rd); 1014 } 1015} 1016 1017static void tcg_out_bswap32(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rn) 1018{ 1019 /* rev */ 1020 tcg_out32(s, 0x06bf0f30 | (cond << 28) | (rd << 12) | rn); 1021} 1022 1023static void tcg_out_deposit(TCGContext *s, ARMCond cond, TCGReg rd, 1024 TCGArg a1, int ofs, int len, bool const_a1) 1025{ 1026 if (const_a1) { 1027 /* bfi becomes bfc with rn == 15. */ 1028 a1 = 15; 1029 } 1030 /* bfi/bfc */ 1031 tcg_out32(s, 0x07c00010 | (cond << 28) | (rd << 12) | a1 1032 | (ofs << 7) | ((ofs + len - 1) << 16)); 1033} 1034 1035static void tcg_out_extract(TCGContext *s, ARMCond cond, TCGReg rd, 1036 TCGReg rn, int ofs, int len) 1037{ 1038 /* According to gcc, AND can be faster. */ 1039 if (ofs == 0 && len <= 8) { 1040 tcg_out_dat_imm(s, cond, ARITH_AND, rd, rn, 1041 encode_imm_nofail((1 << len) - 1)); 1042 return; 1043 } 1044 1045 if (use_armv7_instructions) { 1046 /* ubfx */ 1047 tcg_out32(s, 0x07e00050 | (cond << 28) | (rd << 12) | rn 1048 | (ofs << 7) | ((len - 1) << 16)); 1049 return; 1050 } 1051 1052 assert(ofs % 8 == 0); 1053 switch (len) { 1054 case 8: 1055 /* uxtb */ 1056 tcg_out32(s, 0x06ef0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn); 1057 break; 1058 case 16: 1059 /* uxth */ 1060 tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn); 1061 break; 1062 default: 1063 g_assert_not_reached(); 1064 } 1065} 1066 1067static void tcg_out_sextract(TCGContext *s, ARMCond cond, TCGReg rd, 1068 TCGReg rn, int ofs, int len) 1069{ 1070 if (use_armv7_instructions) { 1071 /* sbfx */ 1072 tcg_out32(s, 0x07a00050 | (cond << 28) | (rd << 12) | rn 1073 | (ofs << 7) | ((len - 1) << 16)); 1074 return; 1075 } 1076 1077 assert(ofs % 8 == 0); 1078 switch (len) { 1079 case 8: 1080 /* sxtb */ 1081 tcg_out32(s, 0x06af0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn); 1082 break; 1083 case 16: 1084 /* sxth */ 1085 tcg_out32(s, 0x06bf0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn); 1086 break; 1087 default: 1088 g_assert_not_reached(); 1089 } 1090} 1091 1092 1093static void tcg_out_ld32u(TCGContext *s, ARMCond cond, 1094 TCGReg rd, TCGReg rn, int32_t offset) 1095{ 1096 if (offset > 0xfff || offset < -0xfff) { 1097 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1098 tcg_out_ld32_r(s, cond, rd, rn, TCG_REG_TMP); 1099 } else 1100 tcg_out_ld32_12(s, cond, rd, rn, offset); 1101} 1102 1103static void tcg_out_st32(TCGContext *s, ARMCond cond, 1104 TCGReg rd, TCGReg rn, int32_t offset) 1105{ 1106 if (offset > 0xfff || offset < -0xfff) { 1107 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1108 tcg_out_st32_r(s, cond, rd, rn, TCG_REG_TMP); 1109 } else 1110 tcg_out_st32_12(s, cond, rd, rn, offset); 1111} 1112 1113static void tcg_out_ld16u(TCGContext *s, ARMCond cond, 1114 TCGReg rd, TCGReg rn, int32_t offset) 1115{ 1116 if (offset > 0xff || offset < -0xff) { 1117 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1118 tcg_out_ld16u_r(s, cond, rd, rn, TCG_REG_TMP); 1119 } else 1120 tcg_out_ld16u_8(s, cond, rd, rn, offset); 1121} 1122 1123static void tcg_out_ld16s(TCGContext *s, ARMCond cond, 1124 TCGReg rd, TCGReg rn, int32_t offset) 1125{ 1126 if (offset > 0xff || offset < -0xff) { 1127 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1128 tcg_out_ld16s_r(s, cond, rd, rn, TCG_REG_TMP); 1129 } else 1130 tcg_out_ld16s_8(s, cond, rd, rn, offset); 1131} 1132 1133static void tcg_out_st16(TCGContext *s, ARMCond cond, 1134 TCGReg rd, TCGReg rn, int32_t offset) 1135{ 1136 if (offset > 0xff || offset < -0xff) { 1137 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1138 tcg_out_st16_r(s, cond, rd, rn, TCG_REG_TMP); 1139 } else 1140 tcg_out_st16_8(s, cond, rd, rn, offset); 1141} 1142 1143static void tcg_out_ld8u(TCGContext *s, ARMCond cond, 1144 TCGReg rd, TCGReg rn, int32_t offset) 1145{ 1146 if (offset > 0xfff || offset < -0xfff) { 1147 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1148 tcg_out_ld8_r(s, cond, rd, rn, TCG_REG_TMP); 1149 } else 1150 tcg_out_ld8_12(s, cond, rd, rn, offset); 1151} 1152 1153static void tcg_out_ld8s(TCGContext *s, ARMCond cond, 1154 TCGReg rd, TCGReg rn, int32_t offset) 1155{ 1156 if (offset > 0xff || offset < -0xff) { 1157 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1158 tcg_out_ld8s_r(s, cond, rd, rn, TCG_REG_TMP); 1159 } else 1160 tcg_out_ld8s_8(s, cond, rd, rn, offset); 1161} 1162 1163static void tcg_out_st8(TCGContext *s, ARMCond cond, 1164 TCGReg rd, TCGReg rn, int32_t offset) 1165{ 1166 if (offset > 0xfff || offset < -0xfff) { 1167 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1168 tcg_out_st8_r(s, cond, rd, rn, TCG_REG_TMP); 1169 } else 1170 tcg_out_st8_12(s, cond, rd, rn, offset); 1171} 1172 1173/* 1174 * The _goto case is normally between TBs within the same code buffer, and 1175 * with the code buffer limited to 16MB we wouldn't need the long case. 1176 * But we also use it for the tail-call to the qemu_ld/st helpers, which does. 1177 */ 1178static void tcg_out_goto(TCGContext *s, ARMCond cond, const tcg_insn_unit *addr) 1179{ 1180 intptr_t addri = (intptr_t)addr; 1181 ptrdiff_t disp = tcg_pcrel_diff(s, addr); 1182 bool arm_mode = !(addri & 1); 1183 1184 if (arm_mode && disp - 8 < 0x01fffffd && disp - 8 > -0x01fffffd) { 1185 tcg_out_b_imm(s, cond, disp); 1186 return; 1187 } 1188 1189 /* LDR is interworking from v5t. */ 1190 tcg_out_movi_pool(s, cond, TCG_REG_PC, addri); 1191} 1192 1193/* 1194 * The call case is mostly used for helpers - so it's not unreasonable 1195 * for them to be beyond branch range. 1196 */ 1197static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *addr) 1198{ 1199 intptr_t addri = (intptr_t)addr; 1200 ptrdiff_t disp = tcg_pcrel_diff(s, addr); 1201 bool arm_mode = !(addri & 1); 1202 1203 if (disp - 8 < 0x02000000 && disp - 8 >= -0x02000000) { 1204 if (arm_mode) { 1205 tcg_out_bl_imm(s, COND_AL, disp); 1206 } else { 1207 tcg_out_blx_imm(s, disp); 1208 } 1209 return; 1210 } 1211 1212 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri); 1213 tcg_out_blx_reg(s, COND_AL, TCG_REG_TMP); 1214} 1215 1216static void tcg_out_call(TCGContext *s, const tcg_insn_unit *addr, 1217 const TCGHelperInfo *info) 1218{ 1219 tcg_out_call_int(s, addr); 1220} 1221 1222static void tcg_out_goto_label(TCGContext *s, ARMCond cond, TCGLabel *l) 1223{ 1224 if (l->has_value) { 1225 tcg_out_goto(s, cond, l->u.value_ptr); 1226 } else { 1227 tcg_out_reloc(s, s->code_ptr, R_ARM_PC24, l, 0); 1228 tcg_out_b_imm(s, cond, 0); 1229 } 1230} 1231 1232static void tcg_out_mb(TCGContext *s, TCGArg a0) 1233{ 1234 if (use_armv7_instructions) { 1235 tcg_out32(s, INSN_DMB_ISH); 1236 } else { 1237 tcg_out32(s, INSN_DMB_MCR); 1238 } 1239} 1240 1241static TCGCond tcg_out_cmp(TCGContext *s, TCGCond cond, TCGReg a, 1242 TCGArg b, int b_const) 1243{ 1244 if (!is_tst_cond(cond)) { 1245 tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, a, b, b_const); 1246 return cond; 1247 } 1248 1249 cond = tcg_tst_eqne_cond(cond); 1250 if (b_const) { 1251 int imm12 = encode_imm(b); 1252 1253 /* 1254 * The compare constraints allow rIN, but TST does not support N. 1255 * Be prepared to load the constant into a scratch register. 1256 */ 1257 if (imm12 >= 0) { 1258 tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, a, imm12); 1259 return cond; 1260 } 1261 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, b); 1262 b = TCG_REG_TMP; 1263 } 1264 tcg_out_dat_reg(s, COND_AL, ARITH_TST, 0, a, b, SHIFT_IMM_LSL(0)); 1265 return cond; 1266} 1267 1268static TCGCond tcg_out_cmp2(TCGContext *s, const TCGArg *args, 1269 const int *const_args) 1270{ 1271 TCGReg al = args[0]; 1272 TCGReg ah = args[1]; 1273 TCGArg bl = args[2]; 1274 TCGArg bh = args[3]; 1275 TCGCond cond = args[4]; 1276 int const_bl = const_args[2]; 1277 int const_bh = const_args[3]; 1278 1279 switch (cond) { 1280 case TCG_COND_EQ: 1281 case TCG_COND_NE: 1282 case TCG_COND_LTU: 1283 case TCG_COND_LEU: 1284 case TCG_COND_GTU: 1285 case TCG_COND_GEU: 1286 /* 1287 * We perform a conditional comparison. If the high half is 1288 * equal, then overwrite the flags with the comparison of the 1289 * low half. The resulting flags cover the whole. 1290 */ 1291 tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, ah, bh, const_bh); 1292 tcg_out_dat_rI(s, COND_EQ, ARITH_CMP, 0, al, bl, const_bl); 1293 return cond; 1294 1295 case TCG_COND_TSTEQ: 1296 case TCG_COND_TSTNE: 1297 /* Similar, but with TST instead of CMP. */ 1298 tcg_out_dat_rI(s, COND_AL, ARITH_TST, 0, ah, bh, const_bh); 1299 tcg_out_dat_rI(s, COND_EQ, ARITH_TST, 0, al, bl, const_bl); 1300 return tcg_tst_eqne_cond(cond); 1301 1302 case TCG_COND_LT: 1303 case TCG_COND_GE: 1304 /* We perform a double-word subtraction and examine the result. 1305 We do not actually need the result of the subtract, so the 1306 low part "subtract" is a compare. For the high half we have 1307 no choice but to compute into a temporary. */ 1308 tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, al, bl, const_bl); 1309 tcg_out_dat_rI(s, COND_AL, ARITH_SBC | TO_CPSR, 1310 TCG_REG_TMP, ah, bh, const_bh); 1311 return cond; 1312 1313 case TCG_COND_LE: 1314 case TCG_COND_GT: 1315 /* Similar, but with swapped arguments, via reversed subtract. */ 1316 tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR, 1317 TCG_REG_TMP, al, bl, const_bl); 1318 tcg_out_dat_rI(s, COND_AL, ARITH_RSC | TO_CPSR, 1319 TCG_REG_TMP, ah, bh, const_bh); 1320 return tcg_swap_cond(cond); 1321 1322 default: 1323 g_assert_not_reached(); 1324 } 1325} 1326 1327/* 1328 * Note that TCGReg references Q-registers. 1329 * Q-regno = 2 * D-regno, so shift left by 1 while inserting. 1330 */ 1331static uint32_t encode_vd(TCGReg rd) 1332{ 1333 tcg_debug_assert(rd >= TCG_REG_Q0); 1334 return (extract32(rd, 3, 1) << 22) | (extract32(rd, 0, 3) << 13); 1335} 1336 1337static uint32_t encode_vn(TCGReg rn) 1338{ 1339 tcg_debug_assert(rn >= TCG_REG_Q0); 1340 return (extract32(rn, 3, 1) << 7) | (extract32(rn, 0, 3) << 17); 1341} 1342 1343static uint32_t encode_vm(TCGReg rm) 1344{ 1345 tcg_debug_assert(rm >= TCG_REG_Q0); 1346 return (extract32(rm, 3, 1) << 5) | (extract32(rm, 0, 3) << 1); 1347} 1348 1349static void tcg_out_vreg2(TCGContext *s, ARMInsn insn, int q, int vece, 1350 TCGReg d, TCGReg m) 1351{ 1352 tcg_out32(s, insn | (vece << 18) | (q << 6) | 1353 encode_vd(d) | encode_vm(m)); 1354} 1355 1356static void tcg_out_vreg3(TCGContext *s, ARMInsn insn, int q, int vece, 1357 TCGReg d, TCGReg n, TCGReg m) 1358{ 1359 tcg_out32(s, insn | (vece << 20) | (q << 6) | 1360 encode_vd(d) | encode_vn(n) | encode_vm(m)); 1361} 1362 1363static void tcg_out_vmovi(TCGContext *s, TCGReg rd, 1364 int q, int op, int cmode, uint8_t imm8) 1365{ 1366 tcg_out32(s, INSN_VMOVI | encode_vd(rd) | (q << 6) | (op << 5) 1367 | (cmode << 8) | extract32(imm8, 0, 4) 1368 | (extract32(imm8, 4, 3) << 16) 1369 | (extract32(imm8, 7, 1) << 24)); 1370} 1371 1372static void tcg_out_vshifti(TCGContext *s, ARMInsn insn, int q, 1373 TCGReg rd, TCGReg rm, int l_imm6) 1374{ 1375 tcg_out32(s, insn | (q << 6) | encode_vd(rd) | encode_vm(rm) | 1376 (extract32(l_imm6, 6, 1) << 7) | 1377 (extract32(l_imm6, 0, 6) << 16)); 1378} 1379 1380static void tcg_out_vldst(TCGContext *s, ARMInsn insn, 1381 TCGReg rd, TCGReg rn, int offset) 1382{ 1383 if (offset != 0) { 1384 if (check_fit_imm(offset) || check_fit_imm(-offset)) { 1385 tcg_out_dat_rIN(s, COND_AL, ARITH_ADD, ARITH_SUB, 1386 TCG_REG_TMP, rn, offset, true); 1387 } else { 1388 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, offset); 1389 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, 1390 TCG_REG_TMP, TCG_REG_TMP, rn, 0); 1391 } 1392 rn = TCG_REG_TMP; 1393 } 1394 tcg_out32(s, insn | (rn << 16) | encode_vd(rd) | 0xf); 1395} 1396 1397typedef struct { 1398 ARMCond cond; 1399 TCGReg base; 1400 int index; 1401 bool index_scratch; 1402 TCGAtomAlign aa; 1403} HostAddress; 1404 1405bool tcg_target_has_memory_bswap(MemOp memop) 1406{ 1407 return false; 1408} 1409 1410static TCGReg ldst_ra_gen(TCGContext *s, const TCGLabelQemuLdst *l, int arg) 1411{ 1412 /* We arrive at the slow path via "BLNE", so R14 contains l->raddr. */ 1413 return TCG_REG_R14; 1414} 1415 1416static const TCGLdstHelperParam ldst_helper_param = { 1417 .ra_gen = ldst_ra_gen, 1418 .ntmp = 1, 1419 .tmp = { TCG_REG_TMP }, 1420}; 1421 1422static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1423{ 1424 MemOp opc = get_memop(lb->oi); 1425 1426 if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1427 return false; 1428 } 1429 1430 tcg_out_ld_helper_args(s, lb, &ldst_helper_param); 1431 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE]); 1432 tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param); 1433 1434 tcg_out_goto(s, COND_AL, lb->raddr); 1435 return true; 1436} 1437 1438static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1439{ 1440 MemOp opc = get_memop(lb->oi); 1441 1442 if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1443 return false; 1444 } 1445 1446 tcg_out_st_helper_args(s, lb, &ldst_helper_param); 1447 1448 /* Tail-call to the helper, which will return to the fast path. */ 1449 tcg_out_goto(s, COND_AL, qemu_st_helpers[opc & MO_SIZE]); 1450 return true; 1451} 1452 1453/* We expect to use an 9-bit sign-magnitude negative offset from ENV. */ 1454#define MIN_TLB_MASK_TABLE_OFS -256 1455 1456static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1457 TCGReg addr, MemOpIdx oi, bool is_ld) 1458{ 1459 TCGLabelQemuLdst *ldst = NULL; 1460 MemOp opc = get_memop(oi); 1461 unsigned a_mask; 1462 1463 if (tcg_use_softmmu) { 1464 *h = (HostAddress){ 1465 .cond = COND_AL, 1466 .base = addr, 1467 .index = TCG_REG_R1, 1468 .index_scratch = true, 1469 }; 1470 } else { 1471 *h = (HostAddress){ 1472 .cond = COND_AL, 1473 .base = addr, 1474 .index = guest_base ? TCG_REG_GUEST_BASE : -1, 1475 .index_scratch = false, 1476 }; 1477 } 1478 1479 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); 1480 a_mask = (1 << h->aa.align) - 1; 1481 1482 if (tcg_use_softmmu) { 1483 int mem_index = get_mmuidx(oi); 1484 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read) 1485 : offsetof(CPUTLBEntry, addr_write); 1486 int fast_off = tlb_mask_table_ofs(s, mem_index); 1487 unsigned s_mask = (1 << (opc & MO_SIZE)) - 1; 1488 TCGReg t_addr; 1489 1490 ldst = new_ldst_label(s); 1491 ldst->is_ld = is_ld; 1492 ldst->oi = oi; 1493 ldst->addr_reg = addr; 1494 1495 /* Load cpu->neg.tlb.f[mmu_idx].{mask,table} into {r0,r1}. */ 1496 QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0); 1497 QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != 4); 1498 tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off); 1499 1500 /* Extract the tlb index from the address into R0. */ 1501 tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, addr, 1502 SHIFT_IMM_LSR(s->page_bits - CPU_TLB_ENTRY_BITS)); 1503 1504 /* 1505 * Add the tlb_table pointer, creating the CPUTLBEntry address in R1. 1506 * Load the tlb comparator into R2 and the fast path addend into R1. 1507 */ 1508 if (cmp_off == 0) { 1509 tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0); 1510 } else { 1511 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, 1512 TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0); 1513 tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); 1514 } 1515 1516 /* Load the tlb addend. */ 1517 tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R1, 1518 offsetof(CPUTLBEntry, addend)); 1519 1520 /* 1521 * Check alignment, check comparators. 1522 * Do this in 2-4 insns. Use MOVW for v7, if possible, 1523 * to reduce the number of sequential conditional instructions. 1524 * Almost all guests have at least 4k pages, which means that we need 1525 * to clear at least 9 bits even for an 8-byte memory, which means it 1526 * isn't worth checking for an immediate operand for BIC. 1527 * 1528 * For unaligned accesses, test the page of the last unit of alignment. 1529 * This leaves the least significant alignment bits unchanged, and of 1530 * course must be zero. 1531 */ 1532 t_addr = addr; 1533 if (a_mask < s_mask) { 1534 t_addr = TCG_REG_R0; 1535 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, t_addr, 1536 addr, s_mask - a_mask); 1537 } 1538 if (use_armv7_instructions && s->page_bits <= 16) { 1539 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, ~(s->page_mask | a_mask)); 1540 tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP, 1541 t_addr, TCG_REG_TMP, 0); 1542 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, 1543 TCG_REG_R2, TCG_REG_TMP, 0); 1544 } else { 1545 if (a_mask) { 1546 tcg_debug_assert(a_mask <= 0xff); 1547 tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addr, a_mask); 1548 } 1549 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, t_addr, 1550 SHIFT_IMM_LSR(s->page_bits)); 1551 tcg_out_dat_reg(s, (a_mask ? COND_EQ : COND_AL), ARITH_CMP, 1552 0, TCG_REG_R2, TCG_REG_TMP, 1553 SHIFT_IMM_LSL(s->page_bits)); 1554 } 1555 } else if (a_mask) { 1556 ldst = new_ldst_label(s); 1557 ldst->is_ld = is_ld; 1558 ldst->oi = oi; 1559 ldst->addr_reg = addr; 1560 1561 /* We are expecting alignment to max out at 7 */ 1562 tcg_debug_assert(a_mask <= 0xff); 1563 /* tst addr, #mask */ 1564 tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addr, a_mask); 1565 } 1566 1567 return ldst; 1568} 1569 1570static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo, 1571 TCGReg datahi, HostAddress h) 1572{ 1573 TCGReg base; 1574 1575 /* Byte swapping is left to middle-end expansion. */ 1576 tcg_debug_assert((opc & MO_BSWAP) == 0); 1577 1578 switch (opc & MO_SSIZE) { 1579 case MO_UB: 1580 if (h.index < 0) { 1581 tcg_out_ld8_12(s, h.cond, datalo, h.base, 0); 1582 } else { 1583 tcg_out_ld8_r(s, h.cond, datalo, h.base, h.index); 1584 } 1585 break; 1586 case MO_SB: 1587 if (h.index < 0) { 1588 tcg_out_ld8s_8(s, h.cond, datalo, h.base, 0); 1589 } else { 1590 tcg_out_ld8s_r(s, h.cond, datalo, h.base, h.index); 1591 } 1592 break; 1593 case MO_UW: 1594 if (h.index < 0) { 1595 tcg_out_ld16u_8(s, h.cond, datalo, h.base, 0); 1596 } else { 1597 tcg_out_ld16u_r(s, h.cond, datalo, h.base, h.index); 1598 } 1599 break; 1600 case MO_SW: 1601 if (h.index < 0) { 1602 tcg_out_ld16s_8(s, h.cond, datalo, h.base, 0); 1603 } else { 1604 tcg_out_ld16s_r(s, h.cond, datalo, h.base, h.index); 1605 } 1606 break; 1607 case MO_UL: 1608 if (h.index < 0) { 1609 tcg_out_ld32_12(s, h.cond, datalo, h.base, 0); 1610 } else { 1611 tcg_out_ld32_r(s, h.cond, datalo, h.base, h.index); 1612 } 1613 break; 1614 case MO_UQ: 1615 /* We used pair allocation for datalo, so already should be aligned. */ 1616 tcg_debug_assert((datalo & 1) == 0); 1617 tcg_debug_assert(datahi == datalo + 1); 1618 /* LDRD requires alignment; double-check that. */ 1619 if (memop_alignment_bits(opc) >= MO_64) { 1620 if (h.index < 0) { 1621 tcg_out_ldrd_8(s, h.cond, datalo, h.base, 0); 1622 break; 1623 } 1624 /* 1625 * Rm (the second address op) must not overlap Rt or Rt + 1. 1626 * Since datalo is aligned, we can simplify the test via alignment. 1627 * Flip the two address arguments if that works. 1628 */ 1629 if ((h.index & ~1) != datalo) { 1630 tcg_out_ldrd_r(s, h.cond, datalo, h.base, h.index); 1631 break; 1632 } 1633 if ((h.base & ~1) != datalo) { 1634 tcg_out_ldrd_r(s, h.cond, datalo, h.index, h.base); 1635 break; 1636 } 1637 } 1638 if (h.index < 0) { 1639 base = h.base; 1640 if (datalo == h.base) { 1641 tcg_out_mov_reg(s, h.cond, TCG_REG_TMP, base); 1642 base = TCG_REG_TMP; 1643 } 1644 } else if (h.index_scratch) { 1645 tcg_out_ld32_rwb(s, h.cond, datalo, h.index, h.base); 1646 tcg_out_ld32_12(s, h.cond, datahi, h.index, 4); 1647 break; 1648 } else { 1649 tcg_out_dat_reg(s, h.cond, ARITH_ADD, TCG_REG_TMP, 1650 h.base, h.index, SHIFT_IMM_LSL(0)); 1651 base = TCG_REG_TMP; 1652 } 1653 tcg_out_ld32_12(s, h.cond, datalo, base, 0); 1654 tcg_out_ld32_12(s, h.cond, datahi, base, 4); 1655 break; 1656 default: 1657 g_assert_not_reached(); 1658 } 1659} 1660 1661static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, 1662 TCGReg addr, MemOpIdx oi, TCGType data_type) 1663{ 1664 MemOp opc = get_memop(oi); 1665 TCGLabelQemuLdst *ldst; 1666 HostAddress h; 1667 1668 ldst = prepare_host_addr(s, &h, addr, oi, true); 1669 if (ldst) { 1670 ldst->type = data_type; 1671 ldst->datalo_reg = datalo; 1672 ldst->datahi_reg = datahi; 1673 1674 /* 1675 * This a conditional BL only to load a pointer within this 1676 * opcode into LR for the slow path. We will not be using 1677 * the value for a tail call. 1678 */ 1679 ldst->label_ptr[0] = s->code_ptr; 1680 tcg_out_bl_imm(s, COND_NE, 0); 1681 1682 tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); 1683 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1684 } else { 1685 tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); 1686 } 1687} 1688 1689static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo, 1690 TCGReg datahi, HostAddress h) 1691{ 1692 /* Byte swapping is left to middle-end expansion. */ 1693 tcg_debug_assert((opc & MO_BSWAP) == 0); 1694 1695 switch (opc & MO_SIZE) { 1696 case MO_8: 1697 if (h.index < 0) { 1698 tcg_out_st8_12(s, h.cond, datalo, h.base, 0); 1699 } else { 1700 tcg_out_st8_r(s, h.cond, datalo, h.base, h.index); 1701 } 1702 break; 1703 case MO_16: 1704 if (h.index < 0) { 1705 tcg_out_st16_8(s, h.cond, datalo, h.base, 0); 1706 } else { 1707 tcg_out_st16_r(s, h.cond, datalo, h.base, h.index); 1708 } 1709 break; 1710 case MO_32: 1711 if (h.index < 0) { 1712 tcg_out_st32_12(s, h.cond, datalo, h.base, 0); 1713 } else { 1714 tcg_out_st32_r(s, h.cond, datalo, h.base, h.index); 1715 } 1716 break; 1717 case MO_64: 1718 /* We used pair allocation for datalo, so already should be aligned. */ 1719 tcg_debug_assert((datalo & 1) == 0); 1720 tcg_debug_assert(datahi == datalo + 1); 1721 /* STRD requires alignment; double-check that. */ 1722 if (memop_alignment_bits(opc) >= MO_64) { 1723 if (h.index < 0) { 1724 tcg_out_strd_8(s, h.cond, datalo, h.base, 0); 1725 } else { 1726 tcg_out_strd_r(s, h.cond, datalo, h.base, h.index); 1727 } 1728 } else if (h.index < 0) { 1729 tcg_out_st32_12(s, h.cond, datalo, h.base, 0); 1730 tcg_out_st32_12(s, h.cond, datahi, h.base, 4); 1731 } else if (h.index_scratch) { 1732 tcg_out_st32_rwb(s, h.cond, datalo, h.index, h.base); 1733 tcg_out_st32_12(s, h.cond, datahi, h.index, 4); 1734 } else { 1735 tcg_out_dat_reg(s, h.cond, ARITH_ADD, TCG_REG_TMP, 1736 h.base, h.index, SHIFT_IMM_LSL(0)); 1737 tcg_out_st32_12(s, h.cond, datalo, TCG_REG_TMP, 0); 1738 tcg_out_st32_12(s, h.cond, datahi, TCG_REG_TMP, 4); 1739 } 1740 break; 1741 default: 1742 g_assert_not_reached(); 1743 } 1744} 1745 1746static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, 1747 TCGReg addr, MemOpIdx oi, TCGType data_type) 1748{ 1749 MemOp opc = get_memop(oi); 1750 TCGLabelQemuLdst *ldst; 1751 HostAddress h; 1752 1753 ldst = prepare_host_addr(s, &h, addr, oi, false); 1754 if (ldst) { 1755 ldst->type = data_type; 1756 ldst->datalo_reg = datalo; 1757 ldst->datahi_reg = datahi; 1758 1759 h.cond = COND_EQ; 1760 tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); 1761 1762 /* The conditional call is last, as we're going to return here. */ 1763 ldst->label_ptr[0] = s->code_ptr; 1764 tcg_out_bl_imm(s, COND_NE, 0); 1765 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1766 } else { 1767 tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); 1768 } 1769} 1770 1771static void tcg_out_epilogue(TCGContext *s); 1772 1773static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg) 1774{ 1775 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, arg); 1776 tcg_out_epilogue(s); 1777} 1778 1779static void tcg_out_goto_tb(TCGContext *s, int which) 1780{ 1781 uintptr_t i_addr; 1782 intptr_t i_disp; 1783 1784 /* Direct branch will be patched by tb_target_set_jmp_target. */ 1785 set_jmp_insn_offset(s, which); 1786 tcg_out32(s, INSN_NOP); 1787 1788 /* When branch is out of range, fall through to indirect. */ 1789 i_addr = get_jmp_target_addr(s, which); 1790 i_disp = tcg_pcrel_diff(s, (void *)i_addr) - 8; 1791 tcg_debug_assert(i_disp < 0); 1792 if (i_disp >= -0xfff) { 1793 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, i_disp); 1794 } else { 1795 /* 1796 * The TB is close, but outside the 12 bits addressable by 1797 * the load. We can extend this to 20 bits with a sub of a 1798 * shifted immediate from pc. 1799 */ 1800 int h = -i_disp; 1801 int l = -(h & 0xfff); 1802 1803 h = encode_imm_nofail(h + l); 1804 tcg_out_dat_imm(s, COND_AL, ARITH_SUB, TCG_REG_R0, TCG_REG_PC, h); 1805 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_R0, l); 1806 } 1807 set_jmp_reset_offset(s, which); 1808} 1809 1810void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1811 uintptr_t jmp_rx, uintptr_t jmp_rw) 1812{ 1813 uintptr_t addr = tb->jmp_target_addr[n]; 1814 ptrdiff_t offset = addr - (jmp_rx + 8); 1815 tcg_insn_unit insn; 1816 1817 /* Either directly branch, or fall through to indirect branch. */ 1818 if (offset == sextract64(offset, 0, 26)) { 1819 /* B <addr> */ 1820 insn = deposit32((COND_AL << 28) | INSN_B, 0, 24, offset >> 2); 1821 } else { 1822 insn = INSN_NOP; 1823 } 1824 1825 qatomic_set((uint32_t *)jmp_rw, insn); 1826 flush_idcache_range(jmp_rx, jmp_rw, 4); 1827} 1828 1829 1830static void tgen_add(TCGContext *s, TCGType type, 1831 TCGReg a0, TCGReg a1, TCGReg a2) 1832{ 1833 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, a0, a1, a2, SHIFT_IMM_LSL(0)); 1834} 1835 1836static void tgen_addi(TCGContext *s, TCGType type, 1837 TCGReg a0, TCGReg a1, tcg_target_long a2) 1838{ 1839 tcg_out_dat_IN(s, COND_AL, ARITH_ADD, ARITH_SUB, a0, a1, a2); 1840} 1841 1842static const TCGOutOpBinary outop_add = { 1843 .base.static_constraint = C_O1_I2(r, r, rIN), 1844 .out_rrr = tgen_add, 1845 .out_rri = tgen_addi, 1846}; 1847 1848static void tgen_and(TCGContext *s, TCGType type, 1849 TCGReg a0, TCGReg a1, TCGReg a2) 1850{ 1851 tcg_out_dat_reg(s, COND_AL, ARITH_AND, a0, a1, a2, SHIFT_IMM_LSL(0)); 1852} 1853 1854static void tgen_andi(TCGContext *s, TCGType type, 1855 TCGReg a0, TCGReg a1, tcg_target_long a2) 1856{ 1857 tcg_out_dat_IK(s, COND_AL, ARITH_AND, ARITH_BIC, a0, a1, a2); 1858} 1859 1860static const TCGOutOpBinary outop_and = { 1861 .base.static_constraint = C_O1_I2(r, r, rIK), 1862 .out_rrr = tgen_and, 1863 .out_rri = tgen_andi, 1864}; 1865 1866static void tgen_andc(TCGContext *s, TCGType type, 1867 TCGReg a0, TCGReg a1, TCGReg a2) 1868{ 1869 tcg_out_dat_reg(s, COND_AL, ARITH_BIC, a0, a1, a2, SHIFT_IMM_LSL(0)); 1870} 1871 1872static const TCGOutOpBinary outop_andc = { 1873 .base.static_constraint = C_O1_I2(r, r, r), 1874 .out_rrr = tgen_andc, 1875}; 1876 1877static const TCGOutOpBinary outop_eqv = { 1878 .base.static_constraint = C_NotImplemented, 1879}; 1880 1881static void tgen_mul(TCGContext *s, TCGType type, 1882 TCGReg a0, TCGReg a1, TCGReg a2) 1883{ 1884 /* mul */ 1885 tcg_out32(s, (COND_AL << 28) | 0x90 | (a0 << 16) | (a1 << 8) | a2); 1886} 1887 1888static const TCGOutOpBinary outop_mul = { 1889 .base.static_constraint = C_O1_I2(r, r, r), 1890 .out_rrr = tgen_mul, 1891}; 1892 1893static const TCGOutOpBinary outop_mulsh = { 1894 .base.static_constraint = C_NotImplemented, 1895}; 1896 1897static const TCGOutOpBinary outop_muluh = { 1898 .base.static_constraint = C_NotImplemented, 1899}; 1900 1901static const TCGOutOpBinary outop_nand = { 1902 .base.static_constraint = C_NotImplemented, 1903}; 1904 1905static const TCGOutOpBinary outop_nor = { 1906 .base.static_constraint = C_NotImplemented, 1907}; 1908 1909static void tgen_or(TCGContext *s, TCGType type, 1910 TCGReg a0, TCGReg a1, TCGReg a2) 1911{ 1912 tcg_out_dat_reg(s, COND_AL, ARITH_ORR, a0, a1, a2, SHIFT_IMM_LSL(0)); 1913} 1914 1915static void tgen_ori(TCGContext *s, TCGType type, 1916 TCGReg a0, TCGReg a1, tcg_target_long a2) 1917{ 1918 tcg_out_dat_imm(s, COND_AL, ARITH_ORR, a0, a1, encode_imm_nofail(a2)); 1919} 1920 1921static const TCGOutOpBinary outop_or = { 1922 .base.static_constraint = C_O1_I2(r, r, rI), 1923 .out_rrr = tgen_or, 1924 .out_rri = tgen_ori, 1925}; 1926 1927static const TCGOutOpBinary outop_orc = { 1928 .base.static_constraint = C_NotImplemented, 1929}; 1930 1931static void tgen_sub(TCGContext *s, TCGType type, 1932 TCGReg a0, TCGReg a1, TCGReg a2) 1933{ 1934 tcg_out_dat_reg(s, COND_AL, ARITH_SUB, a0, a1, a2, SHIFT_IMM_LSL(0)); 1935} 1936 1937static void tgen_subfi(TCGContext *s, TCGType type, 1938 TCGReg a0, tcg_target_long a1, TCGReg a2) 1939{ 1940 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, a0, a2, encode_imm_nofail(a1)); 1941} 1942 1943static const TCGOutOpSubtract outop_sub = { 1944 .base.static_constraint = C_O1_I2(r, rI, r), 1945 .out_rrr = tgen_sub, 1946 .out_rir = tgen_subfi, 1947}; 1948 1949static void tgen_xor(TCGContext *s, TCGType type, 1950 TCGReg a0, TCGReg a1, TCGReg a2) 1951{ 1952 tcg_out_dat_reg(s, COND_AL, ARITH_EOR, a0, a1, a2, SHIFT_IMM_LSL(0)); 1953} 1954 1955static void tgen_xori(TCGContext *s, TCGType type, 1956 TCGReg a0, TCGReg a1, tcg_target_long a2) 1957{ 1958 tcg_out_dat_imm(s, COND_AL, ARITH_EOR, a0, a1, encode_imm_nofail(a2)); 1959} 1960 1961static const TCGOutOpBinary outop_xor = { 1962 .base.static_constraint = C_O1_I2(r, r, rI), 1963 .out_rrr = tgen_xor, 1964 .out_rri = tgen_xori, 1965}; 1966 1967static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 1968{ 1969 tgen_subfi(s, type, a0, 0, a1); 1970} 1971 1972static const TCGOutOpUnary outop_neg = { 1973 .base.static_constraint = C_O1_I1(r, r), 1974 .out_rr = tgen_neg, 1975}; 1976 1977static void tgen_not(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 1978{ 1979 tcg_out_dat_reg(s, COND_AL, ARITH_MVN, a0, 0, a1, SHIFT_IMM_LSL(0)); 1980} 1981 1982static const TCGOutOpUnary outop_not = { 1983 .base.static_constraint = C_O1_I1(r, r), 1984 .out_rr = tgen_not, 1985}; 1986 1987 1988static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, 1989 const TCGArg args[TCG_MAX_OP_ARGS], 1990 const int const_args[TCG_MAX_OP_ARGS]) 1991{ 1992 TCGArg a0, a1, a2, a3, a4, a5; 1993 int c; 1994 1995 switch (opc) { 1996 case INDEX_op_goto_ptr: 1997 tcg_out_b_reg(s, COND_AL, args[0]); 1998 break; 1999 case INDEX_op_br: 2000 tcg_out_goto_label(s, COND_AL, arg_label(args[0])); 2001 break; 2002 2003 case INDEX_op_ld8u_i32: 2004 tcg_out_ld8u(s, COND_AL, args[0], args[1], args[2]); 2005 break; 2006 case INDEX_op_ld8s_i32: 2007 tcg_out_ld8s(s, COND_AL, args[0], args[1], args[2]); 2008 break; 2009 case INDEX_op_ld16u_i32: 2010 tcg_out_ld16u(s, COND_AL, args[0], args[1], args[2]); 2011 break; 2012 case INDEX_op_ld16s_i32: 2013 tcg_out_ld16s(s, COND_AL, args[0], args[1], args[2]); 2014 break; 2015 case INDEX_op_ld_i32: 2016 tcg_out_ld32u(s, COND_AL, args[0], args[1], args[2]); 2017 break; 2018 case INDEX_op_st8_i32: 2019 tcg_out_st8(s, COND_AL, args[0], args[1], args[2]); 2020 break; 2021 case INDEX_op_st16_i32: 2022 tcg_out_st16(s, COND_AL, args[0], args[1], args[2]); 2023 break; 2024 case INDEX_op_st_i32: 2025 tcg_out_st32(s, COND_AL, args[0], args[1], args[2]); 2026 break; 2027 2028 case INDEX_op_movcond_i32: 2029 /* Constraints mean that v2 is always in the same register as dest, 2030 * so we only need to do "if condition passed, move v1 to dest". 2031 */ 2032 c = tcg_out_cmp(s, args[5], args[1], args[2], const_args[2]); 2033 tcg_out_dat_rIK(s, tcg_cond_to_arm_cond[c], ARITH_MOV, 2034 ARITH_MVN, args[0], 0, args[3], const_args[3]); 2035 break; 2036 case INDEX_op_add2_i32: 2037 a0 = args[0], a1 = args[1], a2 = args[2]; 2038 a3 = args[3], a4 = args[4], a5 = args[5]; 2039 if (a0 == a3 || (a0 == a5 && !const_args[5])) { 2040 a0 = TCG_REG_TMP; 2041 } 2042 tcg_out_dat_rIN(s, COND_AL, ARITH_ADD | TO_CPSR, ARITH_SUB | TO_CPSR, 2043 a0, a2, a4, const_args[4]); 2044 tcg_out_dat_rIK(s, COND_AL, ARITH_ADC, ARITH_SBC, 2045 a1, a3, a5, const_args[5]); 2046 tcg_out_mov_reg(s, COND_AL, args[0], a0); 2047 break; 2048 case INDEX_op_sub2_i32: 2049 a0 = args[0], a1 = args[1], a2 = args[2]; 2050 a3 = args[3], a4 = args[4], a5 = args[5]; 2051 if ((a0 == a3 && !const_args[3]) || (a0 == a5 && !const_args[5])) { 2052 a0 = TCG_REG_TMP; 2053 } 2054 if (const_args[2]) { 2055 if (const_args[4]) { 2056 tcg_out_movi32(s, COND_AL, a0, a4); 2057 a4 = a0; 2058 } 2059 tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR, a0, a4, a2, 1); 2060 } else { 2061 tcg_out_dat_rIN(s, COND_AL, ARITH_SUB | TO_CPSR, 2062 ARITH_ADD | TO_CPSR, a0, a2, a4, const_args[4]); 2063 } 2064 if (const_args[3]) { 2065 if (const_args[5]) { 2066 tcg_out_movi32(s, COND_AL, a1, a5); 2067 a5 = a1; 2068 } 2069 tcg_out_dat_rI(s, COND_AL, ARITH_RSC, a1, a5, a3, 1); 2070 } else { 2071 tcg_out_dat_rIK(s, COND_AL, ARITH_SBC, ARITH_ADC, 2072 a1, a3, a5, const_args[5]); 2073 } 2074 tcg_out_mov_reg(s, COND_AL, args[0], a0); 2075 break; 2076 case INDEX_op_mulu2_i32: 2077 tcg_out_umull32(s, COND_AL, args[0], args[1], args[2], args[3]); 2078 break; 2079 case INDEX_op_muls2_i32: 2080 tcg_out_smull32(s, COND_AL, args[0], args[1], args[2], args[3]); 2081 break; 2082 /* XXX: Perhaps args[2] & 0x1f is wrong */ 2083 case INDEX_op_shl_i32: 2084 c = const_args[2] ? 2085 SHIFT_IMM_LSL(args[2] & 0x1f) : SHIFT_REG_LSL(args[2]); 2086 goto gen_shift32; 2087 case INDEX_op_shr_i32: 2088 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_LSR(args[2] & 0x1f) : 2089 SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args[2]); 2090 goto gen_shift32; 2091 case INDEX_op_sar_i32: 2092 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ASR(args[2] & 0x1f) : 2093 SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args[2]); 2094 goto gen_shift32; 2095 case INDEX_op_rotr_i32: 2096 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ROR(args[2] & 0x1f) : 2097 SHIFT_IMM_LSL(0) : SHIFT_REG_ROR(args[2]); 2098 /* Fall through. */ 2099 gen_shift32: 2100 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], c); 2101 break; 2102 2103 case INDEX_op_rotl_i32: 2104 if (const_args[2]) { 2105 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], 2106 ((0x20 - args[2]) & 0x1f) ? 2107 SHIFT_IMM_ROR((0x20 - args[2]) & 0x1f) : 2108 SHIFT_IMM_LSL(0)); 2109 } else { 2110 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, TCG_REG_TMP, args[2], 0x20); 2111 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], 2112 SHIFT_REG_ROR(TCG_REG_TMP)); 2113 } 2114 break; 2115 2116 case INDEX_op_ctz_i32: 2117 tcg_out_dat_reg(s, COND_AL, INSN_RBIT, TCG_REG_TMP, 0, args[1], 0); 2118 a1 = TCG_REG_TMP; 2119 goto do_clz; 2120 2121 case INDEX_op_clz_i32: 2122 a1 = args[1]; 2123 do_clz: 2124 a0 = args[0]; 2125 a2 = args[2]; 2126 c = const_args[2]; 2127 if (c && a2 == 32) { 2128 tcg_out_dat_reg(s, COND_AL, INSN_CLZ, a0, 0, a1, 0); 2129 break; 2130 } 2131 tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0, a1, 0); 2132 tcg_out_dat_reg(s, COND_NE, INSN_CLZ, a0, 0, a1, 0); 2133 if (c || a0 != a2) { 2134 tcg_out_dat_rIK(s, COND_EQ, ARITH_MOV, ARITH_MVN, a0, 0, a2, c); 2135 } 2136 break; 2137 2138 case INDEX_op_brcond_i32: 2139 c = tcg_out_cmp(s, args[2], args[0], args[1], const_args[1]); 2140 tcg_out_goto_label(s, tcg_cond_to_arm_cond[c], arg_label(args[3])); 2141 break; 2142 case INDEX_op_setcond_i32: 2143 c = tcg_out_cmp(s, args[3], args[1], args[2], const_args[2]); 2144 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[c], 2145 ARITH_MOV, args[0], 0, 1); 2146 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(c)], 2147 ARITH_MOV, args[0], 0, 0); 2148 break; 2149 case INDEX_op_negsetcond_i32: 2150 c = tcg_out_cmp(s, args[3], args[1], args[2], const_args[2]); 2151 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[c], 2152 ARITH_MVN, args[0], 0, 0); 2153 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(c)], 2154 ARITH_MOV, args[0], 0, 0); 2155 break; 2156 2157 case INDEX_op_brcond2_i32: 2158 c = tcg_out_cmp2(s, args, const_args); 2159 tcg_out_goto_label(s, tcg_cond_to_arm_cond[c], arg_label(args[5])); 2160 break; 2161 case INDEX_op_setcond2_i32: 2162 c = tcg_out_cmp2(s, args + 1, const_args + 1); 2163 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[c], ARITH_MOV, args[0], 0, 1); 2164 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(c)], 2165 ARITH_MOV, args[0], 0, 0); 2166 break; 2167 2168 case INDEX_op_qemu_ld_i32: 2169 tcg_out_qemu_ld(s, args[0], -1, args[1], args[2], TCG_TYPE_I32); 2170 break; 2171 case INDEX_op_qemu_ld_i64: 2172 tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3], TCG_TYPE_I64); 2173 break; 2174 2175 case INDEX_op_qemu_st_i32: 2176 tcg_out_qemu_st(s, args[0], -1, args[1], args[2], TCG_TYPE_I32); 2177 break; 2178 case INDEX_op_qemu_st_i64: 2179 tcg_out_qemu_st(s, args[0], args[1], args[2], args[3], TCG_TYPE_I64); 2180 break; 2181 2182 case INDEX_op_bswap16_i32: 2183 tcg_out_bswap16(s, COND_AL, args[0], args[1], args[2]); 2184 break; 2185 case INDEX_op_bswap32_i32: 2186 tcg_out_bswap32(s, COND_AL, args[0], args[1]); 2187 break; 2188 2189 case INDEX_op_deposit_i32: 2190 tcg_out_deposit(s, COND_AL, args[0], args[2], 2191 args[3], args[4], const_args[2]); 2192 break; 2193 case INDEX_op_extract_i32: 2194 tcg_out_extract(s, COND_AL, args[0], args[1], args[2], args[3]); 2195 break; 2196 case INDEX_op_sextract_i32: 2197 tcg_out_sextract(s, COND_AL, args[0], args[1], args[2], args[3]); 2198 break; 2199 case INDEX_op_extract2_i32: 2200 /* ??? These optimization vs zero should be generic. */ 2201 /* ??? But we can't substitute 2 for 1 in the opcode stream yet. */ 2202 if (const_args[1]) { 2203 if (const_args[2]) { 2204 tcg_out_movi(s, TCG_TYPE_REG, args[0], 0); 2205 } else { 2206 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, 2207 args[2], SHIFT_IMM_LSL(32 - args[3])); 2208 } 2209 } else if (const_args[2]) { 2210 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, 2211 args[1], SHIFT_IMM_LSR(args[3])); 2212 } else { 2213 /* We can do extract2 in 2 insns, vs the 3 required otherwise. */ 2214 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, 2215 args[2], SHIFT_IMM_LSL(32 - args[3])); 2216 tcg_out_dat_reg(s, COND_AL, ARITH_ORR, args[0], TCG_REG_TMP, 2217 args[1], SHIFT_IMM_LSR(args[3])); 2218 } 2219 break; 2220 2221 case INDEX_op_div_i32: 2222 tcg_out_sdiv(s, COND_AL, args[0], args[1], args[2]); 2223 break; 2224 case INDEX_op_divu_i32: 2225 tcg_out_udiv(s, COND_AL, args[0], args[1], args[2]); 2226 break; 2227 2228 case INDEX_op_mb: 2229 tcg_out_mb(s, args[0]); 2230 break; 2231 2232 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2233 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2234 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2235 default: 2236 g_assert_not_reached(); 2237 } 2238} 2239 2240static TCGConstraintSetIndex 2241tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) 2242{ 2243 switch (op) { 2244 case INDEX_op_goto_ptr: 2245 return C_O0_I1(r); 2246 2247 case INDEX_op_ld8u_i32: 2248 case INDEX_op_ld8s_i32: 2249 case INDEX_op_ld16u_i32: 2250 case INDEX_op_ld16s_i32: 2251 case INDEX_op_ld_i32: 2252 case INDEX_op_bswap16_i32: 2253 case INDEX_op_bswap32_i32: 2254 case INDEX_op_extract_i32: 2255 case INDEX_op_sextract_i32: 2256 return C_O1_I1(r, r); 2257 2258 case INDEX_op_st8_i32: 2259 case INDEX_op_st16_i32: 2260 case INDEX_op_st_i32: 2261 return C_O0_I2(r, r); 2262 2263 case INDEX_op_setcond_i32: 2264 case INDEX_op_negsetcond_i32: 2265 return C_O1_I2(r, r, rIN); 2266 2267 case INDEX_op_clz_i32: 2268 case INDEX_op_ctz_i32: 2269 return C_O1_I2(r, r, rIK); 2270 2271 case INDEX_op_div_i32: 2272 case INDEX_op_divu_i32: 2273 return C_O1_I2(r, r, r); 2274 2275 case INDEX_op_mulu2_i32: 2276 case INDEX_op_muls2_i32: 2277 return C_O2_I2(r, r, r, r); 2278 2279 case INDEX_op_shl_i32: 2280 case INDEX_op_shr_i32: 2281 case INDEX_op_sar_i32: 2282 case INDEX_op_rotl_i32: 2283 case INDEX_op_rotr_i32: 2284 return C_O1_I2(r, r, ri); 2285 2286 case INDEX_op_brcond_i32: 2287 return C_O0_I2(r, rIN); 2288 case INDEX_op_deposit_i32: 2289 return C_O1_I2(r, 0, rZ); 2290 case INDEX_op_extract2_i32: 2291 return C_O1_I2(r, rZ, rZ); 2292 case INDEX_op_movcond_i32: 2293 return C_O1_I4(r, r, rIN, rIK, 0); 2294 case INDEX_op_add2_i32: 2295 return C_O2_I4(r, r, r, r, rIN, rIK); 2296 case INDEX_op_sub2_i32: 2297 return C_O2_I4(r, r, rI, rI, rIN, rIK); 2298 case INDEX_op_brcond2_i32: 2299 return C_O0_I4(r, r, rI, rI); 2300 case INDEX_op_setcond2_i32: 2301 return C_O1_I4(r, r, r, rI, rI); 2302 2303 case INDEX_op_qemu_ld_i32: 2304 return C_O1_I1(r, q); 2305 case INDEX_op_qemu_ld_i64: 2306 return C_O2_I1(e, p, q); 2307 case INDEX_op_qemu_st_i32: 2308 return C_O0_I2(q, q); 2309 case INDEX_op_qemu_st_i64: 2310 return C_O0_I3(Q, p, q); 2311 2312 case INDEX_op_st_vec: 2313 return C_O0_I2(w, r); 2314 case INDEX_op_ld_vec: 2315 case INDEX_op_dupm_vec: 2316 return C_O1_I1(w, r); 2317 case INDEX_op_dup_vec: 2318 return C_O1_I1(w, wr); 2319 case INDEX_op_abs_vec: 2320 case INDEX_op_neg_vec: 2321 case INDEX_op_not_vec: 2322 case INDEX_op_shli_vec: 2323 case INDEX_op_shri_vec: 2324 case INDEX_op_sari_vec: 2325 return C_O1_I1(w, w); 2326 case INDEX_op_dup2_vec: 2327 case INDEX_op_add_vec: 2328 case INDEX_op_mul_vec: 2329 case INDEX_op_smax_vec: 2330 case INDEX_op_smin_vec: 2331 case INDEX_op_ssadd_vec: 2332 case INDEX_op_sssub_vec: 2333 case INDEX_op_sub_vec: 2334 case INDEX_op_umax_vec: 2335 case INDEX_op_umin_vec: 2336 case INDEX_op_usadd_vec: 2337 case INDEX_op_ussub_vec: 2338 case INDEX_op_xor_vec: 2339 case INDEX_op_arm_sshl_vec: 2340 case INDEX_op_arm_ushl_vec: 2341 return C_O1_I2(w, w, w); 2342 case INDEX_op_arm_sli_vec: 2343 return C_O1_I2(w, 0, w); 2344 case INDEX_op_or_vec: 2345 case INDEX_op_andc_vec: 2346 return C_O1_I2(w, w, wO); 2347 case INDEX_op_and_vec: 2348 case INDEX_op_orc_vec: 2349 return C_O1_I2(w, w, wV); 2350 case INDEX_op_cmp_vec: 2351 return C_O1_I2(w, w, wZ); 2352 case INDEX_op_bitsel_vec: 2353 return C_O1_I3(w, w, w, w); 2354 default: 2355 return C_NotImplemented; 2356 } 2357} 2358 2359static void tcg_target_init(TCGContext *s) 2360{ 2361 /* 2362 * Only probe for the platform and capabilities if we haven't already 2363 * determined maximum values at compile time. 2364 */ 2365#if !defined(use_idiv_instructions) || !defined(use_neon_instructions) 2366 { 2367 unsigned long hwcap = qemu_getauxval(AT_HWCAP); 2368#ifndef use_idiv_instructions 2369 use_idiv_instructions = (hwcap & HWCAP_ARM_IDIVA) != 0; 2370#endif 2371#ifndef use_neon_instructions 2372 use_neon_instructions = (hwcap & HWCAP_ARM_NEON) != 0; 2373#endif 2374 } 2375#endif 2376 2377 if (__ARM_ARCH < 7) { 2378 const char *pl = (const char *)qemu_getauxval(AT_PLATFORM); 2379 if (pl != NULL && pl[0] == 'v' && pl[1] >= '4' && pl[1] <= '9') { 2380 arm_arch = pl[1] - '0'; 2381 } 2382 2383 if (arm_arch < 6) { 2384 error_report("TCG: ARMv%d is unsupported; exiting", arm_arch); 2385 exit(EXIT_FAILURE); 2386 } 2387 } 2388 2389 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS; 2390 2391 tcg_target_call_clobber_regs = 0; 2392 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); 2393 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1); 2394 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2); 2395 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3); 2396 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12); 2397 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14); 2398 2399 if (use_neon_instructions) { 2400 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS; 2401 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS; 2402 2403 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q0); 2404 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q1); 2405 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q2); 2406 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q3); 2407 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q8); 2408 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q9); 2409 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q10); 2410 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q11); 2411 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q12); 2412 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q13); 2413 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q14); 2414 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q15); 2415 } 2416 2417 s->reserved_regs = 0; 2418 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); 2419 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP); 2420 tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC); 2421 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP); 2422} 2423 2424static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 2425 TCGReg arg1, intptr_t arg2) 2426{ 2427 switch (type) { 2428 case TCG_TYPE_I32: 2429 tcg_out_ld32u(s, COND_AL, arg, arg1, arg2); 2430 return; 2431 case TCG_TYPE_V64: 2432 /* regs 1; size 8; align 8 */ 2433 tcg_out_vldst(s, INSN_VLD1 | 0x7d0, arg, arg1, arg2); 2434 return; 2435 case TCG_TYPE_V128: 2436 /* 2437 * We have only 8-byte alignment for the stack per the ABI. 2438 * Rather than dynamically re-align the stack, it's easier 2439 * to simply not request alignment beyond that. So: 2440 * regs 2; size 8; align 8 2441 */ 2442 tcg_out_vldst(s, INSN_VLD1 | 0xad0, arg, arg1, arg2); 2443 return; 2444 default: 2445 g_assert_not_reached(); 2446 } 2447} 2448 2449static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 2450 TCGReg arg1, intptr_t arg2) 2451{ 2452 switch (type) { 2453 case TCG_TYPE_I32: 2454 tcg_out_st32(s, COND_AL, arg, arg1, arg2); 2455 return; 2456 case TCG_TYPE_V64: 2457 /* regs 1; size 8; align 8 */ 2458 tcg_out_vldst(s, INSN_VST1 | 0x7d0, arg, arg1, arg2); 2459 return; 2460 case TCG_TYPE_V128: 2461 /* See tcg_out_ld re alignment: regs 2; size 8; align 8 */ 2462 tcg_out_vldst(s, INSN_VST1 | 0xad0, arg, arg1, arg2); 2463 return; 2464 default: 2465 g_assert_not_reached(); 2466 } 2467} 2468 2469static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 2470 TCGReg base, intptr_t ofs) 2471{ 2472 return false; 2473} 2474 2475static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 2476{ 2477 if (ret == arg) { 2478 return true; 2479 } 2480 switch (type) { 2481 case TCG_TYPE_I32: 2482 if (ret < TCG_REG_Q0 && arg < TCG_REG_Q0) { 2483 tcg_out_mov_reg(s, COND_AL, ret, arg); 2484 return true; 2485 } 2486 return false; 2487 2488 case TCG_TYPE_V64: 2489 case TCG_TYPE_V128: 2490 /* "VMOV D,N" is an alias for "VORR D,N,N". */ 2491 tcg_out_vreg3(s, INSN_VORR, type - TCG_TYPE_V64, 0, ret, arg, arg); 2492 return true; 2493 2494 default: 2495 g_assert_not_reached(); 2496 } 2497} 2498 2499static void tcg_out_movi(TCGContext *s, TCGType type, 2500 TCGReg ret, tcg_target_long arg) 2501{ 2502 tcg_debug_assert(type == TCG_TYPE_I32); 2503 tcg_debug_assert(ret < TCG_REG_Q0); 2504 tcg_out_movi32(s, COND_AL, ret, arg); 2505} 2506 2507static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 2508{ 2509 return false; 2510} 2511 2512static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 2513 tcg_target_long imm) 2514{ 2515 int enc, opc = ARITH_ADD; 2516 2517 /* All of the easiest immediates to encode are positive. */ 2518 if (imm < 0) { 2519 imm = -imm; 2520 opc = ARITH_SUB; 2521 } 2522 enc = encode_imm(imm); 2523 if (enc >= 0) { 2524 tcg_out_dat_imm(s, COND_AL, opc, rd, rs, enc); 2525 } else { 2526 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, imm); 2527 tcg_out_dat_reg(s, COND_AL, opc, rd, rs, 2528 TCG_REG_TMP, SHIFT_IMM_LSL(0)); 2529 } 2530} 2531 2532/* Type is always V128, with I64 elements. */ 2533static void tcg_out_dup2_vec(TCGContext *s, TCGReg rd, TCGReg rl, TCGReg rh) 2534{ 2535 /* Move high element into place first. */ 2536 /* VMOV Dd+1, Ds */ 2537 tcg_out_vreg3(s, INSN_VORR | (1 << 12), 0, 0, rd, rh, rh); 2538 /* Move low element into place; tcg_out_mov will check for nop. */ 2539 tcg_out_mov(s, TCG_TYPE_V64, rd, rl); 2540} 2541 2542static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 2543 TCGReg rd, TCGReg rs) 2544{ 2545 int q = type - TCG_TYPE_V64; 2546 2547 if (vece == MO_64) { 2548 if (type == TCG_TYPE_V128) { 2549 tcg_out_dup2_vec(s, rd, rs, rs); 2550 } else { 2551 tcg_out_mov(s, TCG_TYPE_V64, rd, rs); 2552 } 2553 } else if (rs < TCG_REG_Q0) { 2554 int b = (vece == MO_8); 2555 int e = (vece == MO_16); 2556 tcg_out32(s, INSN_VDUP_G | (b << 22) | (q << 21) | (e << 5) | 2557 encode_vn(rd) | (rs << 12)); 2558 } else { 2559 int imm4 = 1 << vece; 2560 tcg_out32(s, INSN_VDUP_S | (imm4 << 16) | (q << 6) | 2561 encode_vd(rd) | encode_vm(rs)); 2562 } 2563 return true; 2564} 2565 2566static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 2567 TCGReg rd, TCGReg base, intptr_t offset) 2568{ 2569 if (vece == MO_64) { 2570 tcg_out_ld(s, TCG_TYPE_V64, rd, base, offset); 2571 if (type == TCG_TYPE_V128) { 2572 tcg_out_dup2_vec(s, rd, rd, rd); 2573 } 2574 } else { 2575 int q = type - TCG_TYPE_V64; 2576 tcg_out_vldst(s, INSN_VLD1R | (vece << 6) | (q << 5), 2577 rd, base, offset); 2578 } 2579 return true; 2580} 2581 2582static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 2583 TCGReg rd, int64_t v64) 2584{ 2585 int q = type - TCG_TYPE_V64; 2586 int cmode, imm8, i; 2587 2588 /* Test all bytes equal first. */ 2589 if (vece == MO_8) { 2590 tcg_out_vmovi(s, rd, q, 0, 0xe, v64); 2591 return; 2592 } 2593 2594 /* 2595 * Test all bytes 0x00 or 0xff second. This can match cases that 2596 * might otherwise take 2 or 3 insns for MO_16 or MO_32 below. 2597 */ 2598 for (i = imm8 = 0; i < 8; i++) { 2599 uint8_t byte = v64 >> (i * 8); 2600 if (byte == 0xff) { 2601 imm8 |= 1 << i; 2602 } else if (byte != 0) { 2603 goto fail_bytes; 2604 } 2605 } 2606 tcg_out_vmovi(s, rd, q, 1, 0xe, imm8); 2607 return; 2608 fail_bytes: 2609 2610 /* 2611 * Tests for various replications. For each element width, if we 2612 * cannot find an expansion there's no point checking a larger 2613 * width because we already know by replication it cannot match. 2614 */ 2615 if (vece == MO_16) { 2616 uint16_t v16 = v64; 2617 2618 if (is_shimm16(v16, &cmode, &imm8)) { 2619 tcg_out_vmovi(s, rd, q, 0, cmode, imm8); 2620 return; 2621 } 2622 if (is_shimm16(~v16, &cmode, &imm8)) { 2623 tcg_out_vmovi(s, rd, q, 1, cmode, imm8); 2624 return; 2625 } 2626 2627 /* 2628 * Otherwise, all remaining constants can be loaded in two insns: 2629 * rd = v16 & 0xff, rd |= v16 & 0xff00. 2630 */ 2631 tcg_out_vmovi(s, rd, q, 0, 0x8, v16 & 0xff); 2632 tcg_out_vmovi(s, rd, q, 0, 0xb, v16 >> 8); /* VORRI */ 2633 return; 2634 } 2635 2636 if (vece == MO_32) { 2637 uint32_t v32 = v64; 2638 2639 if (is_shimm32(v32, &cmode, &imm8) || 2640 is_soimm32(v32, &cmode, &imm8)) { 2641 tcg_out_vmovi(s, rd, q, 0, cmode, imm8); 2642 return; 2643 } 2644 if (is_shimm32(~v32, &cmode, &imm8) || 2645 is_soimm32(~v32, &cmode, &imm8)) { 2646 tcg_out_vmovi(s, rd, q, 1, cmode, imm8); 2647 return; 2648 } 2649 2650 /* 2651 * Restrict the set of constants to those we can load with 2652 * two instructions. Others we load from the pool. 2653 */ 2654 i = is_shimm32_pair(v32, &cmode, &imm8); 2655 if (i) { 2656 tcg_out_vmovi(s, rd, q, 0, cmode, imm8); 2657 tcg_out_vmovi(s, rd, q, 0, i | 1, extract32(v32, i * 4, 8)); 2658 return; 2659 } 2660 i = is_shimm32_pair(~v32, &cmode, &imm8); 2661 if (i) { 2662 tcg_out_vmovi(s, rd, q, 1, cmode, imm8); 2663 tcg_out_vmovi(s, rd, q, 1, i | 1, extract32(~v32, i * 4, 8)); 2664 return; 2665 } 2666 } 2667 2668 /* 2669 * As a last resort, load from the constant pool. 2670 */ 2671 if (!q || vece == MO_64) { 2672 new_pool_l2(s, R_ARM_PC11, s->code_ptr, 0, v64, v64 >> 32); 2673 /* VLDR Dd, [pc + offset] */ 2674 tcg_out32(s, INSN_VLDR_D | encode_vd(rd) | (0xf << 16)); 2675 if (q) { 2676 tcg_out_dup2_vec(s, rd, rd, rd); 2677 } 2678 } else { 2679 new_pool_label(s, (uint32_t)v64, R_ARM_PC8, s->code_ptr, 0); 2680 /* add tmp, pc, offset */ 2681 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_TMP, TCG_REG_PC, 0); 2682 tcg_out_dupm_vec(s, type, MO_32, rd, TCG_REG_TMP, 0); 2683 } 2684} 2685 2686static const ARMInsn vec_cmp_insn[16] = { 2687 [TCG_COND_EQ] = INSN_VCEQ, 2688 [TCG_COND_GT] = INSN_VCGT, 2689 [TCG_COND_GE] = INSN_VCGE, 2690 [TCG_COND_GTU] = INSN_VCGT_U, 2691 [TCG_COND_GEU] = INSN_VCGE_U, 2692}; 2693 2694static const ARMInsn vec_cmp0_insn[16] = { 2695 [TCG_COND_EQ] = INSN_VCEQ0, 2696 [TCG_COND_GT] = INSN_VCGT0, 2697 [TCG_COND_GE] = INSN_VCGE0, 2698 [TCG_COND_LT] = INSN_VCLT0, 2699 [TCG_COND_LE] = INSN_VCLE0, 2700}; 2701 2702static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 2703 unsigned vecl, unsigned vece, 2704 const TCGArg args[TCG_MAX_OP_ARGS], 2705 const int const_args[TCG_MAX_OP_ARGS]) 2706{ 2707 TCGType type = vecl + TCG_TYPE_V64; 2708 unsigned q = vecl; 2709 TCGArg a0, a1, a2, a3; 2710 int cmode, imm8; 2711 2712 a0 = args[0]; 2713 a1 = args[1]; 2714 a2 = args[2]; 2715 2716 switch (opc) { 2717 case INDEX_op_ld_vec: 2718 tcg_out_ld(s, type, a0, a1, a2); 2719 return; 2720 case INDEX_op_st_vec: 2721 tcg_out_st(s, type, a0, a1, a2); 2722 return; 2723 case INDEX_op_dupm_vec: 2724 tcg_out_dupm_vec(s, type, vece, a0, a1, a2); 2725 return; 2726 case INDEX_op_dup2_vec: 2727 tcg_out_dup2_vec(s, a0, a1, a2); 2728 return; 2729 case INDEX_op_abs_vec: 2730 tcg_out_vreg2(s, INSN_VABS, q, vece, a0, a1); 2731 return; 2732 case INDEX_op_neg_vec: 2733 tcg_out_vreg2(s, INSN_VNEG, q, vece, a0, a1); 2734 return; 2735 case INDEX_op_not_vec: 2736 tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a1); 2737 return; 2738 case INDEX_op_add_vec: 2739 tcg_out_vreg3(s, INSN_VADD, q, vece, a0, a1, a2); 2740 return; 2741 case INDEX_op_mul_vec: 2742 tcg_out_vreg3(s, INSN_VMUL, q, vece, a0, a1, a2); 2743 return; 2744 case INDEX_op_smax_vec: 2745 tcg_out_vreg3(s, INSN_VMAX, q, vece, a0, a1, a2); 2746 return; 2747 case INDEX_op_smin_vec: 2748 tcg_out_vreg3(s, INSN_VMIN, q, vece, a0, a1, a2); 2749 return; 2750 case INDEX_op_sub_vec: 2751 tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2); 2752 return; 2753 case INDEX_op_ssadd_vec: 2754 tcg_out_vreg3(s, INSN_VQADD, q, vece, a0, a1, a2); 2755 return; 2756 case INDEX_op_sssub_vec: 2757 tcg_out_vreg3(s, INSN_VQSUB, q, vece, a0, a1, a2); 2758 return; 2759 case INDEX_op_umax_vec: 2760 tcg_out_vreg3(s, INSN_VMAX_U, q, vece, a0, a1, a2); 2761 return; 2762 case INDEX_op_umin_vec: 2763 tcg_out_vreg3(s, INSN_VMIN_U, q, vece, a0, a1, a2); 2764 return; 2765 case INDEX_op_usadd_vec: 2766 tcg_out_vreg3(s, INSN_VQADD_U, q, vece, a0, a1, a2); 2767 return; 2768 case INDEX_op_ussub_vec: 2769 tcg_out_vreg3(s, INSN_VQSUB_U, q, vece, a0, a1, a2); 2770 return; 2771 case INDEX_op_xor_vec: 2772 tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2); 2773 return; 2774 case INDEX_op_arm_sshl_vec: 2775 /* 2776 * Note that Vm is the data and Vn is the shift count, 2777 * therefore the arguments appear reversed. 2778 */ 2779 tcg_out_vreg3(s, INSN_VSHL_S, q, vece, a0, a2, a1); 2780 return; 2781 case INDEX_op_arm_ushl_vec: 2782 /* See above. */ 2783 tcg_out_vreg3(s, INSN_VSHL_U, q, vece, a0, a2, a1); 2784 return; 2785 case INDEX_op_shli_vec: 2786 tcg_out_vshifti(s, INSN_VSHLI, q, a0, a1, a2 + (8 << vece)); 2787 return; 2788 case INDEX_op_shri_vec: 2789 tcg_out_vshifti(s, INSN_VSHRI, q, a0, a1, (16 << vece) - a2); 2790 return; 2791 case INDEX_op_sari_vec: 2792 tcg_out_vshifti(s, INSN_VSARI, q, a0, a1, (16 << vece) - a2); 2793 return; 2794 case INDEX_op_arm_sli_vec: 2795 tcg_out_vshifti(s, INSN_VSLI, q, a0, a2, args[3] + (8 << vece)); 2796 return; 2797 2798 case INDEX_op_andc_vec: 2799 if (!const_args[2]) { 2800 tcg_out_vreg3(s, INSN_VBIC, q, 0, a0, a1, a2); 2801 return; 2802 } 2803 a2 = ~a2; 2804 /* fall through */ 2805 case INDEX_op_and_vec: 2806 if (const_args[2]) { 2807 is_shimm1632(~a2, &cmode, &imm8); 2808 if (a0 == a1) { 2809 tcg_out_vmovi(s, a0, q, 1, cmode | 1, imm8); /* VBICI */ 2810 return; 2811 } 2812 tcg_out_vmovi(s, a0, q, 1, cmode, imm8); /* VMVNI */ 2813 a2 = a0; 2814 } 2815 tcg_out_vreg3(s, INSN_VAND, q, 0, a0, a1, a2); 2816 return; 2817 2818 case INDEX_op_orc_vec: 2819 if (!const_args[2]) { 2820 tcg_out_vreg3(s, INSN_VORN, q, 0, a0, a1, a2); 2821 return; 2822 } 2823 a2 = ~a2; 2824 /* fall through */ 2825 case INDEX_op_or_vec: 2826 if (const_args[2]) { 2827 is_shimm1632(a2, &cmode, &imm8); 2828 if (a0 == a1) { 2829 tcg_out_vmovi(s, a0, q, 0, cmode | 1, imm8); /* VORRI */ 2830 return; 2831 } 2832 tcg_out_vmovi(s, a0, q, 0, cmode, imm8); /* VMOVI */ 2833 a2 = a0; 2834 } 2835 tcg_out_vreg3(s, INSN_VORR, q, 0, a0, a1, a2); 2836 return; 2837 2838 case INDEX_op_cmp_vec: 2839 { 2840 TCGCond cond = args[3]; 2841 ARMInsn insn; 2842 2843 switch (cond) { 2844 case TCG_COND_NE: 2845 if (const_args[2]) { 2846 tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a1); 2847 } else { 2848 tcg_out_vreg3(s, INSN_VCEQ, q, vece, a0, a1, a2); 2849 tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0); 2850 } 2851 break; 2852 2853 case TCG_COND_TSTNE: 2854 case TCG_COND_TSTEQ: 2855 if (const_args[2]) { 2856 /* (x & 0) == 0 */ 2857 tcg_out_dupi_vec(s, type, MO_8, a0, 2858 -(cond == TCG_COND_TSTEQ)); 2859 break; 2860 } 2861 tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a2); 2862 if (cond == TCG_COND_TSTEQ) { 2863 tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0); 2864 } 2865 break; 2866 2867 default: 2868 if (const_args[2]) { 2869 insn = vec_cmp0_insn[cond]; 2870 if (insn) { 2871 tcg_out_vreg2(s, insn, q, vece, a0, a1); 2872 return; 2873 } 2874 tcg_out_dupi_vec(s, type, MO_8, TCG_VEC_TMP, 0); 2875 a2 = TCG_VEC_TMP; 2876 } 2877 insn = vec_cmp_insn[cond]; 2878 if (insn == 0) { 2879 TCGArg t; 2880 t = a1, a1 = a2, a2 = t; 2881 cond = tcg_swap_cond(cond); 2882 insn = vec_cmp_insn[cond]; 2883 tcg_debug_assert(insn != 0); 2884 } 2885 tcg_out_vreg3(s, insn, q, vece, a0, a1, a2); 2886 break; 2887 } 2888 } 2889 return; 2890 2891 case INDEX_op_bitsel_vec: 2892 a3 = args[3]; 2893 if (a0 == a3) { 2894 tcg_out_vreg3(s, INSN_VBIT, q, 0, a0, a2, a1); 2895 } else if (a0 == a2) { 2896 tcg_out_vreg3(s, INSN_VBIF, q, 0, a0, a3, a1); 2897 } else { 2898 tcg_out_mov(s, type, a0, a1); 2899 tcg_out_vreg3(s, INSN_VBSL, q, 0, a0, a2, a3); 2900 } 2901 return; 2902 2903 case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ 2904 case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ 2905 default: 2906 g_assert_not_reached(); 2907 } 2908} 2909 2910int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 2911{ 2912 switch (opc) { 2913 case INDEX_op_add_vec: 2914 case INDEX_op_sub_vec: 2915 case INDEX_op_and_vec: 2916 case INDEX_op_andc_vec: 2917 case INDEX_op_or_vec: 2918 case INDEX_op_orc_vec: 2919 case INDEX_op_xor_vec: 2920 case INDEX_op_not_vec: 2921 case INDEX_op_shli_vec: 2922 case INDEX_op_shri_vec: 2923 case INDEX_op_sari_vec: 2924 case INDEX_op_ssadd_vec: 2925 case INDEX_op_sssub_vec: 2926 case INDEX_op_usadd_vec: 2927 case INDEX_op_ussub_vec: 2928 case INDEX_op_bitsel_vec: 2929 return 1; 2930 case INDEX_op_abs_vec: 2931 case INDEX_op_cmp_vec: 2932 case INDEX_op_mul_vec: 2933 case INDEX_op_neg_vec: 2934 case INDEX_op_smax_vec: 2935 case INDEX_op_smin_vec: 2936 case INDEX_op_umax_vec: 2937 case INDEX_op_umin_vec: 2938 return vece < MO_64; 2939 case INDEX_op_shlv_vec: 2940 case INDEX_op_shrv_vec: 2941 case INDEX_op_sarv_vec: 2942 case INDEX_op_rotli_vec: 2943 case INDEX_op_rotlv_vec: 2944 case INDEX_op_rotrv_vec: 2945 return -1; 2946 default: 2947 return 0; 2948 } 2949} 2950 2951void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 2952 TCGArg a0, ...) 2953{ 2954 va_list va; 2955 TCGv_vec v0, v1, v2, t1, t2, c1; 2956 TCGArg a2; 2957 2958 va_start(va, a0); 2959 v0 = temp_tcgv_vec(arg_temp(a0)); 2960 v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 2961 a2 = va_arg(va, TCGArg); 2962 va_end(va); 2963 2964 switch (opc) { 2965 case INDEX_op_shlv_vec: 2966 /* 2967 * Merely propagate shlv_vec to arm_ushl_vec. 2968 * In this way we don't set TCG_TARGET_HAS_shv_vec 2969 * because everything is done via expansion. 2970 */ 2971 v2 = temp_tcgv_vec(arg_temp(a2)); 2972 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0), 2973 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 2974 break; 2975 2976 case INDEX_op_shrv_vec: 2977 case INDEX_op_sarv_vec: 2978 /* Right shifts are negative left shifts for NEON. */ 2979 v2 = temp_tcgv_vec(arg_temp(a2)); 2980 t1 = tcg_temp_new_vec(type); 2981 tcg_gen_neg_vec(vece, t1, v2); 2982 if (opc == INDEX_op_shrv_vec) { 2983 opc = INDEX_op_arm_ushl_vec; 2984 } else { 2985 opc = INDEX_op_arm_sshl_vec; 2986 } 2987 vec_gen_3(opc, type, vece, tcgv_vec_arg(v0), 2988 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 2989 tcg_temp_free_vec(t1); 2990 break; 2991 2992 case INDEX_op_rotli_vec: 2993 t1 = tcg_temp_new_vec(type); 2994 tcg_gen_shri_vec(vece, t1, v1, -a2 & ((8 << vece) - 1)); 2995 vec_gen_4(INDEX_op_arm_sli_vec, type, vece, 2996 tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(v1), a2); 2997 tcg_temp_free_vec(t1); 2998 break; 2999 3000 case INDEX_op_rotlv_vec: 3001 v2 = temp_tcgv_vec(arg_temp(a2)); 3002 t1 = tcg_temp_new_vec(type); 3003 c1 = tcg_constant_vec(type, vece, 8 << vece); 3004 tcg_gen_sub_vec(vece, t1, v2, c1); 3005 /* Right shifts are negative left shifts for NEON. */ 3006 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1), 3007 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 3008 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0), 3009 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 3010 tcg_gen_or_vec(vece, v0, v0, t1); 3011 tcg_temp_free_vec(t1); 3012 break; 3013 3014 case INDEX_op_rotrv_vec: 3015 v2 = temp_tcgv_vec(arg_temp(a2)); 3016 t1 = tcg_temp_new_vec(type); 3017 t2 = tcg_temp_new_vec(type); 3018 c1 = tcg_constant_vec(type, vece, 8 << vece); 3019 tcg_gen_neg_vec(vece, t1, v2); 3020 tcg_gen_sub_vec(vece, t2, c1, v2); 3021 /* Right shifts are negative left shifts for NEON. */ 3022 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1), 3023 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 3024 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t2), 3025 tcgv_vec_arg(v1), tcgv_vec_arg(t2)); 3026 tcg_gen_or_vec(vece, v0, t1, t2); 3027 tcg_temp_free_vec(t1); 3028 tcg_temp_free_vec(t2); 3029 break; 3030 3031 default: 3032 g_assert_not_reached(); 3033 } 3034} 3035 3036static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 3037{ 3038 int i; 3039 for (i = 0; i < count; ++i) { 3040 p[i] = INSN_NOP; 3041 } 3042} 3043 3044/* Compute frame size via macros, to share between tcg_target_qemu_prologue 3045 and tcg_register_jit. */ 3046 3047#define PUSH_SIZE ((11 - 4 + 1 + 1) * sizeof(tcg_target_long)) 3048 3049#define FRAME_SIZE \ 3050 ((PUSH_SIZE \ 3051 + TCG_STATIC_CALL_ARGS_SIZE \ 3052 + CPU_TEMP_BUF_NLONGS * sizeof(long) \ 3053 + TCG_TARGET_STACK_ALIGN - 1) \ 3054 & -TCG_TARGET_STACK_ALIGN) 3055 3056#define STACK_ADDEND (FRAME_SIZE - PUSH_SIZE) 3057 3058static void tcg_target_qemu_prologue(TCGContext *s) 3059{ 3060 /* Calling convention requires us to save r4-r11 and lr. */ 3061 /* stmdb sp!, { r4 - r11, lr } */ 3062 tcg_out_ldstm(s, COND_AL, INSN_STMDB, TCG_REG_CALL_STACK, 3063 (1 << TCG_REG_R4) | (1 << TCG_REG_R5) | (1 << TCG_REG_R6) | 3064 (1 << TCG_REG_R7) | (1 << TCG_REG_R8) | (1 << TCG_REG_R9) | 3065 (1 << TCG_REG_R10) | (1 << TCG_REG_R11) | (1 << TCG_REG_R14)); 3066 3067 /* Reserve callee argument and tcg temp space. */ 3068 tcg_out_dat_rI(s, COND_AL, ARITH_SUB, TCG_REG_CALL_STACK, 3069 TCG_REG_CALL_STACK, STACK_ADDEND, 1); 3070 tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE, 3071 CPU_TEMP_BUF_NLONGS * sizeof(long)); 3072 3073 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 3074 3075 if (!tcg_use_softmmu && guest_base) { 3076 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_GUEST_BASE, guest_base); 3077 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GUEST_BASE); 3078 } 3079 3080 tcg_out_b_reg(s, COND_AL, tcg_target_call_iarg_regs[1]); 3081 3082 /* 3083 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 3084 * and fall through to the rest of the epilogue. 3085 */ 3086 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 3087 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, 0); 3088 tcg_out_epilogue(s); 3089} 3090 3091static void tcg_out_epilogue(TCGContext *s) 3092{ 3093 /* Release local stack frame. */ 3094 tcg_out_dat_rI(s, COND_AL, ARITH_ADD, TCG_REG_CALL_STACK, 3095 TCG_REG_CALL_STACK, STACK_ADDEND, 1); 3096 3097 /* ldmia sp!, { r4 - r11, pc } */ 3098 tcg_out_ldstm(s, COND_AL, INSN_LDMIA, TCG_REG_CALL_STACK, 3099 (1 << TCG_REG_R4) | (1 << TCG_REG_R5) | (1 << TCG_REG_R6) | 3100 (1 << TCG_REG_R7) | (1 << TCG_REG_R8) | (1 << TCG_REG_R9) | 3101 (1 << TCG_REG_R10) | (1 << TCG_REG_R11) | (1 << TCG_REG_PC)); 3102} 3103 3104static void tcg_out_tb_start(TCGContext *s) 3105{ 3106 /* nothing to do */ 3107} 3108 3109typedef struct { 3110 DebugFrameHeader h; 3111 uint8_t fde_def_cfa[4]; 3112 uint8_t fde_reg_ofs[18]; 3113} DebugFrame; 3114 3115#define ELF_HOST_MACHINE EM_ARM 3116 3117/* We're expecting a 2 byte uleb128 encoded value. */ 3118QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); 3119 3120static const DebugFrame debug_frame = { 3121 .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ 3122 .h.cie.id = -1, 3123 .h.cie.version = 1, 3124 .h.cie.code_align = 1, 3125 .h.cie.data_align = 0x7c, /* sleb128 -4 */ 3126 .h.cie.return_column = 14, 3127 3128 /* Total FDE size does not include the "len" member. */ 3129 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 3130 3131 .fde_def_cfa = { 3132 12, 13, /* DW_CFA_def_cfa sp, ... */ 3133 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 3134 (FRAME_SIZE >> 7) 3135 }, 3136 .fde_reg_ofs = { 3137 /* The following must match the stmdb in the prologue. */ 3138 0x8e, 1, /* DW_CFA_offset, lr, -4 */ 3139 0x8b, 2, /* DW_CFA_offset, r11, -8 */ 3140 0x8a, 3, /* DW_CFA_offset, r10, -12 */ 3141 0x89, 4, /* DW_CFA_offset, r9, -16 */ 3142 0x88, 5, /* DW_CFA_offset, r8, -20 */ 3143 0x87, 6, /* DW_CFA_offset, r7, -24 */ 3144 0x86, 7, /* DW_CFA_offset, r6, -28 */ 3145 0x85, 8, /* DW_CFA_offset, r5, -32 */ 3146 0x84, 9, /* DW_CFA_offset, r4, -36 */ 3147 } 3148}; 3149 3150void tcg_register_jit(const void *buf, size_t buf_size) 3151{ 3152 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 3153} 3154