1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Andrzej Zaborowski 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25#include "elf.h" 26 27int arm_arch = __ARM_ARCH; 28 29#ifndef use_idiv_instructions 30bool use_idiv_instructions; 31#endif 32#ifndef use_neon_instructions 33bool use_neon_instructions; 34#endif 35 36/* Used for function call generation. */ 37#define TCG_TARGET_STACK_ALIGN 8 38#define TCG_TARGET_CALL_STACK_OFFSET 0 39#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL 40#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN 41#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN 42#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF 43 44#ifdef CONFIG_DEBUG_TCG 45static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 46 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", 47 "%r8", "%r9", "%r10", "%r11", "%r12", "%sp", "%r14", "%pc", 48 "%q0", "%q1", "%q2", "%q3", "%q4", "%q5", "%q6", "%q7", 49 "%q8", "%q9", "%q10", "%q11", "%q12", "%q13", "%q14", "%q15", 50}; 51#endif 52 53static const int tcg_target_reg_alloc_order[] = { 54 TCG_REG_R4, 55 TCG_REG_R5, 56 TCG_REG_R6, 57 TCG_REG_R7, 58 TCG_REG_R8, 59 TCG_REG_R9, 60 TCG_REG_R10, 61 TCG_REG_R11, 62 TCG_REG_R13, 63 TCG_REG_R0, 64 TCG_REG_R1, 65 TCG_REG_R2, 66 TCG_REG_R3, 67 TCG_REG_R12, 68 TCG_REG_R14, 69 70 TCG_REG_Q0, 71 TCG_REG_Q1, 72 TCG_REG_Q2, 73 TCG_REG_Q3, 74 /* Q4 - Q7 are call-saved, and skipped. */ 75 TCG_REG_Q8, 76 TCG_REG_Q9, 77 TCG_REG_Q10, 78 TCG_REG_Q11, 79 TCG_REG_Q12, 80 TCG_REG_Q13, 81 TCG_REG_Q14, 82 TCG_REG_Q15, 83}; 84 85static const int tcg_target_call_iarg_regs[4] = { 86 TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3 87}; 88 89static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 90{ 91 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 92 tcg_debug_assert(slot >= 0 && slot <= 3); 93 return TCG_REG_R0 + slot; 94} 95 96#define TCG_REG_TMP TCG_REG_R12 97#define TCG_VEC_TMP TCG_REG_Q15 98#define TCG_REG_GUEST_BASE TCG_REG_R11 99 100typedef enum { 101 COND_EQ = 0x0, 102 COND_NE = 0x1, 103 COND_CS = 0x2, /* Unsigned greater or equal */ 104 COND_CC = 0x3, /* Unsigned less than */ 105 COND_MI = 0x4, /* Negative */ 106 COND_PL = 0x5, /* Zero or greater */ 107 COND_VS = 0x6, /* Overflow */ 108 COND_VC = 0x7, /* No overflow */ 109 COND_HI = 0x8, /* Unsigned greater than */ 110 COND_LS = 0x9, /* Unsigned less or equal */ 111 COND_GE = 0xa, 112 COND_LT = 0xb, 113 COND_GT = 0xc, 114 COND_LE = 0xd, 115 COND_AL = 0xe, 116} ARMCond; 117 118#define TO_CPSR (1 << 20) 119 120#define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00) 121#define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20) 122#define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40) 123#define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60) 124#define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10) 125#define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30) 126#define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50) 127#define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70) 128 129typedef enum { 130 ARITH_AND = 0x0 << 21, 131 ARITH_EOR = 0x1 << 21, 132 ARITH_SUB = 0x2 << 21, 133 ARITH_RSB = 0x3 << 21, 134 ARITH_ADD = 0x4 << 21, 135 ARITH_ADC = 0x5 << 21, 136 ARITH_SBC = 0x6 << 21, 137 ARITH_RSC = 0x7 << 21, 138 ARITH_TST = 0x8 << 21 | TO_CPSR, 139 ARITH_CMP = 0xa << 21 | TO_CPSR, 140 ARITH_CMN = 0xb << 21 | TO_CPSR, 141 ARITH_ORR = 0xc << 21, 142 ARITH_MOV = 0xd << 21, 143 ARITH_BIC = 0xe << 21, 144 ARITH_MVN = 0xf << 21, 145 146 INSN_B = 0x0a000000, 147 148 INSN_CLZ = 0x016f0f10, 149 INSN_RBIT = 0x06ff0f30, 150 151 INSN_LDMIA = 0x08b00000, 152 INSN_STMDB = 0x09200000, 153 154 INSN_LDR_IMM = 0x04100000, 155 INSN_LDR_REG = 0x06100000, 156 INSN_STR_IMM = 0x04000000, 157 INSN_STR_REG = 0x06000000, 158 159 INSN_LDRH_IMM = 0x005000b0, 160 INSN_LDRH_REG = 0x001000b0, 161 INSN_LDRSH_IMM = 0x005000f0, 162 INSN_LDRSH_REG = 0x001000f0, 163 INSN_STRH_IMM = 0x004000b0, 164 INSN_STRH_REG = 0x000000b0, 165 166 INSN_LDRB_IMM = 0x04500000, 167 INSN_LDRB_REG = 0x06500000, 168 INSN_LDRSB_IMM = 0x005000d0, 169 INSN_LDRSB_REG = 0x001000d0, 170 INSN_STRB_IMM = 0x04400000, 171 INSN_STRB_REG = 0x06400000, 172 173 INSN_LDRD_IMM = 0x004000d0, 174 INSN_LDRD_REG = 0x000000d0, 175 INSN_STRD_IMM = 0x004000f0, 176 INSN_STRD_REG = 0x000000f0, 177 178 INSN_DMB_ISH = 0xf57ff05b, 179 INSN_DMB_MCR = 0xee070fba, 180 181 /* Architected nop introduced in v6k. */ 182 /* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this 183 also Just So Happened to do nothing on pre-v6k so that we 184 don't need to conditionalize it? */ 185 INSN_NOP_v6k = 0xe320f000, 186 /* Otherwise the assembler uses mov r0,r0 */ 187 INSN_NOP_v4 = (COND_AL << 28) | ARITH_MOV, 188 189 INSN_VADD = 0xf2000800, 190 INSN_VAND = 0xf2000110, 191 INSN_VBIC = 0xf2100110, 192 INSN_VEOR = 0xf3000110, 193 INSN_VORN = 0xf2300110, 194 INSN_VORR = 0xf2200110, 195 INSN_VSUB = 0xf3000800, 196 INSN_VMUL = 0xf2000910, 197 INSN_VQADD = 0xf2000010, 198 INSN_VQADD_U = 0xf3000010, 199 INSN_VQSUB = 0xf2000210, 200 INSN_VQSUB_U = 0xf3000210, 201 INSN_VMAX = 0xf2000600, 202 INSN_VMAX_U = 0xf3000600, 203 INSN_VMIN = 0xf2000610, 204 INSN_VMIN_U = 0xf3000610, 205 206 INSN_VABS = 0xf3b10300, 207 INSN_VMVN = 0xf3b00580, 208 INSN_VNEG = 0xf3b10380, 209 210 INSN_VCEQ0 = 0xf3b10100, 211 INSN_VCGT0 = 0xf3b10000, 212 INSN_VCGE0 = 0xf3b10080, 213 INSN_VCLE0 = 0xf3b10180, 214 INSN_VCLT0 = 0xf3b10200, 215 216 INSN_VCEQ = 0xf3000810, 217 INSN_VCGE = 0xf2000310, 218 INSN_VCGT = 0xf2000300, 219 INSN_VCGE_U = 0xf3000310, 220 INSN_VCGT_U = 0xf3000300, 221 222 INSN_VSHLI = 0xf2800510, /* VSHL (immediate) */ 223 INSN_VSARI = 0xf2800010, /* VSHR.S */ 224 INSN_VSHRI = 0xf3800010, /* VSHR.U */ 225 INSN_VSLI = 0xf3800510, 226 INSN_VSHL_S = 0xf2000400, /* VSHL.S (register) */ 227 INSN_VSHL_U = 0xf3000400, /* VSHL.U (register) */ 228 229 INSN_VBSL = 0xf3100110, 230 INSN_VBIT = 0xf3200110, 231 INSN_VBIF = 0xf3300110, 232 233 INSN_VTST = 0xf2000810, 234 235 INSN_VDUP_G = 0xee800b10, /* VDUP (ARM core register) */ 236 INSN_VDUP_S = 0xf3b00c00, /* VDUP (scalar) */ 237 INSN_VLDR_D = 0xed100b00, /* VLDR.64 */ 238 INSN_VLD1 = 0xf4200000, /* VLD1 (multiple single elements) */ 239 INSN_VLD1R = 0xf4a00c00, /* VLD1 (single element to all lanes) */ 240 INSN_VST1 = 0xf4000000, /* VST1 (multiple single elements) */ 241 INSN_VMOVI = 0xf2800010, /* VMOV (immediate) */ 242} ARMInsn; 243 244#define INSN_NOP (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4) 245 246static const uint8_t tcg_cond_to_arm_cond[] = { 247 [TCG_COND_EQ] = COND_EQ, 248 [TCG_COND_NE] = COND_NE, 249 [TCG_COND_LT] = COND_LT, 250 [TCG_COND_GE] = COND_GE, 251 [TCG_COND_LE] = COND_LE, 252 [TCG_COND_GT] = COND_GT, 253 /* unsigned */ 254 [TCG_COND_LTU] = COND_CC, 255 [TCG_COND_GEU] = COND_CS, 256 [TCG_COND_LEU] = COND_LS, 257 [TCG_COND_GTU] = COND_HI, 258}; 259 260static int encode_imm(uint32_t imm); 261 262/* TCG private relocation type: add with pc+imm8 */ 263#define R_ARM_PC8 11 264 265/* TCG private relocation type: vldr with imm8 << 2 */ 266#define R_ARM_PC11 12 267 268static bool reloc_pc24(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 269{ 270 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 271 ptrdiff_t offset = (tcg_ptr_byte_diff(target, src_rx) - 8) >> 2; 272 273 if (offset == sextract32(offset, 0, 24)) { 274 *src_rw = deposit32(*src_rw, 0, 24, offset); 275 return true; 276 } 277 return false; 278} 279 280static bool reloc_pc13(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 281{ 282 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 283 ptrdiff_t offset = tcg_ptr_byte_diff(target, src_rx) - 8; 284 285 if (offset >= -0xfff && offset <= 0xfff) { 286 tcg_insn_unit insn = *src_rw; 287 bool u = (offset >= 0); 288 if (!u) { 289 offset = -offset; 290 } 291 insn = deposit32(insn, 23, 1, u); 292 insn = deposit32(insn, 0, 12, offset); 293 *src_rw = insn; 294 return true; 295 } 296 return false; 297} 298 299static bool reloc_pc11(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 300{ 301 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 302 ptrdiff_t offset = (tcg_ptr_byte_diff(target, src_rx) - 8) / 4; 303 304 if (offset >= -0xff && offset <= 0xff) { 305 tcg_insn_unit insn = *src_rw; 306 bool u = (offset >= 0); 307 if (!u) { 308 offset = -offset; 309 } 310 insn = deposit32(insn, 23, 1, u); 311 insn = deposit32(insn, 0, 8, offset); 312 *src_rw = insn; 313 return true; 314 } 315 return false; 316} 317 318static bool reloc_pc8(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 319{ 320 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 321 ptrdiff_t offset = tcg_ptr_byte_diff(target, src_rx) - 8; 322 int imm12 = encode_imm(offset); 323 324 if (imm12 >= 0) { 325 *src_rw = deposit32(*src_rw, 0, 12, imm12); 326 return true; 327 } 328 return false; 329} 330 331static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 332 intptr_t value, intptr_t addend) 333{ 334 tcg_debug_assert(addend == 0); 335 switch (type) { 336 case R_ARM_PC24: 337 return reloc_pc24(code_ptr, (const tcg_insn_unit *)value); 338 case R_ARM_PC13: 339 return reloc_pc13(code_ptr, (const tcg_insn_unit *)value); 340 case R_ARM_PC11: 341 return reloc_pc11(code_ptr, (const tcg_insn_unit *)value); 342 case R_ARM_PC8: 343 return reloc_pc8(code_ptr, (const tcg_insn_unit *)value); 344 default: 345 g_assert_not_reached(); 346 } 347} 348 349#define TCG_CT_CONST_ARM 0x100 350#define TCG_CT_CONST_INV 0x200 351#define TCG_CT_CONST_NEG 0x400 352#define TCG_CT_CONST_ZERO 0x800 353#define TCG_CT_CONST_ORRI 0x1000 354#define TCG_CT_CONST_ANDI 0x2000 355 356#define ALL_GENERAL_REGS 0xffffu 357#define ALL_VECTOR_REGS 0xffff0000u 358 359/* 360 * r0-r3 will be overwritten when reading the tlb entry (system-mode only); 361 * r14 will be overwritten by the BLNE branching to the slow path. 362 */ 363#define ALL_QLDST_REGS \ 364 (ALL_GENERAL_REGS & ~((tcg_use_softmmu ? 0xf : 0) | (1 << TCG_REG_R14))) 365 366/* 367 * ARM immediates for ALU instructions are made of an unsigned 8-bit 368 * right-rotated by an even amount between 0 and 30. 369 * 370 * Return < 0 if @imm cannot be encoded, else the entire imm12 field. 371 */ 372static int encode_imm(uint32_t imm) 373{ 374 uint32_t rot, imm8; 375 376 /* Simple case, no rotation required. */ 377 if ((imm & ~0xff) == 0) { 378 return imm; 379 } 380 381 /* Next, try a simple even shift. */ 382 rot = ctz32(imm) & ~1; 383 imm8 = imm >> rot; 384 rot = 32 - rot; 385 if ((imm8 & ~0xff) == 0) { 386 goto found; 387 } 388 389 /* 390 * Finally, try harder with rotations. 391 * The ctz test above will have taken care of rotates >= 8. 392 */ 393 for (rot = 2; rot < 8; rot += 2) { 394 imm8 = rol32(imm, rot); 395 if ((imm8 & ~0xff) == 0) { 396 goto found; 397 } 398 } 399 /* Fail: imm cannot be encoded. */ 400 return -1; 401 402 found: 403 /* Note that rot is even, and we discard bit 0 by shifting by 7. */ 404 return rot << 7 | imm8; 405} 406 407static int encode_imm_nofail(uint32_t imm) 408{ 409 int ret = encode_imm(imm); 410 tcg_debug_assert(ret >= 0); 411 return ret; 412} 413 414static bool check_fit_imm(uint32_t imm) 415{ 416 return encode_imm(imm) >= 0; 417} 418 419/* Return true if v16 is a valid 16-bit shifted immediate. */ 420static bool is_shimm16(uint16_t v16, int *cmode, int *imm8) 421{ 422 if (v16 == (v16 & 0xff)) { 423 *cmode = 0x8; 424 *imm8 = v16 & 0xff; 425 return true; 426 } else if (v16 == (v16 & 0xff00)) { 427 *cmode = 0xa; 428 *imm8 = v16 >> 8; 429 return true; 430 } 431 return false; 432} 433 434/* Return true if v32 is a valid 32-bit shifted immediate. */ 435static bool is_shimm32(uint32_t v32, int *cmode, int *imm8) 436{ 437 if (v32 == (v32 & 0xff)) { 438 *cmode = 0x0; 439 *imm8 = v32 & 0xff; 440 return true; 441 } else if (v32 == (v32 & 0xff00)) { 442 *cmode = 0x2; 443 *imm8 = (v32 >> 8) & 0xff; 444 return true; 445 } else if (v32 == (v32 & 0xff0000)) { 446 *cmode = 0x4; 447 *imm8 = (v32 >> 16) & 0xff; 448 return true; 449 } else if (v32 == (v32 & 0xff000000)) { 450 *cmode = 0x6; 451 *imm8 = v32 >> 24; 452 return true; 453 } 454 return false; 455} 456 457/* Return true if v32 is a valid 32-bit shifting ones immediate. */ 458static bool is_soimm32(uint32_t v32, int *cmode, int *imm8) 459{ 460 if ((v32 & 0xffff00ff) == 0xff) { 461 *cmode = 0xc; 462 *imm8 = (v32 >> 8) & 0xff; 463 return true; 464 } else if ((v32 & 0xff00ffff) == 0xffff) { 465 *cmode = 0xd; 466 *imm8 = (v32 >> 16) & 0xff; 467 return true; 468 } 469 return false; 470} 471 472/* 473 * Return non-zero if v32 can be formed by MOVI+ORR. 474 * Place the parameters for MOVI in (cmode, imm8). 475 * Return the cmode for ORR; the imm8 can be had via extraction from v32. 476 */ 477static int is_shimm32_pair(uint32_t v32, int *cmode, int *imm8) 478{ 479 int i; 480 481 for (i = 6; i > 0; i -= 2) { 482 /* Mask out one byte we can add with ORR. */ 483 uint32_t tmp = v32 & ~(0xffu << (i * 4)); 484 if (is_shimm32(tmp, cmode, imm8) || 485 is_soimm32(tmp, cmode, imm8)) { 486 break; 487 } 488 } 489 return i; 490} 491 492/* Return true if V is a valid 16-bit or 32-bit shifted immediate. */ 493static bool is_shimm1632(uint32_t v32, int *cmode, int *imm8) 494{ 495 if (v32 == deposit32(v32, 16, 16, v32)) { 496 return is_shimm16(v32, cmode, imm8); 497 } else { 498 return is_shimm32(v32, cmode, imm8); 499 } 500} 501 502/* Test if a constant matches the constraint. 503 * TODO: define constraints for: 504 * 505 * ldr/str offset: between -0xfff and 0xfff 506 * ldrh/strh offset: between -0xff and 0xff 507 * mov operand2: values represented with x << (2 * y), x < 0x100 508 * add, sub, eor...: ditto 509 */ 510static bool tcg_target_const_match(int64_t val, int ct, 511 TCGType type, TCGCond cond, int vece) 512{ 513 if (ct & TCG_CT_CONST) { 514 return 1; 515 } else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val)) { 516 return 1; 517 } else if ((ct & TCG_CT_CONST_INV) && check_fit_imm(~val)) { 518 return 1; 519 } else if ((ct & TCG_CT_CONST_NEG) && check_fit_imm(-val)) { 520 return 1; 521 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 522 return 1; 523 } 524 525 switch (ct & (TCG_CT_CONST_ORRI | TCG_CT_CONST_ANDI)) { 526 case 0: 527 break; 528 case TCG_CT_CONST_ANDI: 529 val = ~val; 530 /* fallthru */ 531 case TCG_CT_CONST_ORRI: 532 if (val == deposit64(val, 32, 32, val)) { 533 int cmode, imm8; 534 return is_shimm1632(val, &cmode, &imm8); 535 } 536 break; 537 default: 538 /* Both bits should not be set for the same insn. */ 539 g_assert_not_reached(); 540 } 541 542 return 0; 543} 544 545static void tcg_out_b_imm(TCGContext *s, ARMCond cond, int32_t offset) 546{ 547 tcg_out32(s, (cond << 28) | INSN_B | 548 (((offset - 8) >> 2) & 0x00ffffff)); 549} 550 551static void tcg_out_bl_imm(TCGContext *s, ARMCond cond, int32_t offset) 552{ 553 tcg_out32(s, (cond << 28) | 0x0b000000 | 554 (((offset - 8) >> 2) & 0x00ffffff)); 555} 556 557static void tcg_out_blx_reg(TCGContext *s, ARMCond cond, TCGReg rn) 558{ 559 tcg_out32(s, (cond << 28) | 0x012fff30 | rn); 560} 561 562static void tcg_out_blx_imm(TCGContext *s, int32_t offset) 563{ 564 tcg_out32(s, 0xfa000000 | ((offset & 2) << 23) | 565 (((offset - 8) >> 2) & 0x00ffffff)); 566} 567 568static void tcg_out_dat_reg(TCGContext *s, ARMCond cond, ARMInsn opc, 569 TCGReg rd, TCGReg rn, TCGReg rm, int shift) 570{ 571 tcg_out32(s, (cond << 28) | (0 << 25) | opc | 572 (rn << 16) | (rd << 12) | shift | rm); 573} 574 575static void tcg_out_mov_reg(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rm) 576{ 577 /* Simple reg-reg move, optimising out the 'do nothing' case */ 578 if (rd != rm) { 579 tcg_out_dat_reg(s, cond, ARITH_MOV, rd, 0, rm, SHIFT_IMM_LSL(0)); 580 } 581} 582 583static void tcg_out_bx_reg(TCGContext *s, ARMCond cond, TCGReg rn) 584{ 585 tcg_out32(s, (cond << 28) | 0x012fff10 | rn); 586} 587 588static void tcg_out_b_reg(TCGContext *s, ARMCond cond, TCGReg rn) 589{ 590 /* 591 * Unless the C portion of QEMU is compiled as thumb, we don't need 592 * true BX semantics; merely a branch to an address held in a register. 593 */ 594 tcg_out_bx_reg(s, cond, rn); 595} 596 597static void tcg_out_dat_imm(TCGContext *s, ARMCond cond, ARMInsn opc, 598 TCGReg rd, TCGReg rn, int im) 599{ 600 tcg_out32(s, (cond << 28) | (1 << 25) | opc | 601 (rn << 16) | (rd << 12) | im); 602} 603 604static void tcg_out_ldstm(TCGContext *s, ARMCond cond, ARMInsn opc, 605 TCGReg rn, uint16_t mask) 606{ 607 tcg_out32(s, (cond << 28) | opc | (rn << 16) | mask); 608} 609 610/* Note that this routine is used for both LDR and LDRH formats, so we do 611 not wish to include an immediate shift at this point. */ 612static void tcg_out_memop_r(TCGContext *s, ARMCond cond, ARMInsn opc, TCGReg rt, 613 TCGReg rn, TCGReg rm, bool u, bool p, bool w) 614{ 615 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) 616 | (w << 21) | (rn << 16) | (rt << 12) | rm); 617} 618 619static void tcg_out_memop_8(TCGContext *s, ARMCond cond, ARMInsn opc, TCGReg rt, 620 TCGReg rn, int imm8, bool p, bool w) 621{ 622 bool u = 1; 623 if (imm8 < 0) { 624 imm8 = -imm8; 625 u = 0; 626 } 627 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | 628 (rn << 16) | (rt << 12) | ((imm8 & 0xf0) << 4) | (imm8 & 0xf)); 629} 630 631static void tcg_out_memop_12(TCGContext *s, ARMCond cond, ARMInsn opc, 632 TCGReg rt, TCGReg rn, int imm12, bool p, bool w) 633{ 634 bool u = 1; 635 if (imm12 < 0) { 636 imm12 = -imm12; 637 u = 0; 638 } 639 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | 640 (rn << 16) | (rt << 12) | imm12); 641} 642 643static void tcg_out_ld32_12(TCGContext *s, ARMCond cond, TCGReg rt, 644 TCGReg rn, int imm12) 645{ 646 tcg_out_memop_12(s, cond, INSN_LDR_IMM, rt, rn, imm12, 1, 0); 647} 648 649static void tcg_out_st32_12(TCGContext *s, ARMCond cond, TCGReg rt, 650 TCGReg rn, int imm12) 651{ 652 tcg_out_memop_12(s, cond, INSN_STR_IMM, rt, rn, imm12, 1, 0); 653} 654 655static void tcg_out_ld32_r(TCGContext *s, ARMCond cond, TCGReg rt, 656 TCGReg rn, TCGReg rm) 657{ 658 tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 0); 659} 660 661static void tcg_out_st32_r(TCGContext *s, ARMCond cond, TCGReg rt, 662 TCGReg rn, TCGReg rm) 663{ 664 tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 0); 665} 666 667static void tcg_out_ldrd_8(TCGContext *s, ARMCond cond, TCGReg rt, 668 TCGReg rn, int imm8) 669{ 670 tcg_out_memop_8(s, cond, INSN_LDRD_IMM, rt, rn, imm8, 1, 0); 671} 672 673static void tcg_out_ldrd_r(TCGContext *s, ARMCond cond, TCGReg rt, 674 TCGReg rn, TCGReg rm) 675{ 676 tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 0); 677} 678 679static void tcg_out_strd_8(TCGContext *s, ARMCond cond, TCGReg rt, 680 TCGReg rn, int imm8) 681{ 682 tcg_out_memop_8(s, cond, INSN_STRD_IMM, rt, rn, imm8, 1, 0); 683} 684 685static void tcg_out_strd_r(TCGContext *s, ARMCond cond, TCGReg rt, 686 TCGReg rn, TCGReg rm) 687{ 688 tcg_out_memop_r(s, cond, INSN_STRD_REG, rt, rn, rm, 1, 1, 0); 689} 690 691/* Register pre-increment with base writeback. */ 692static void tcg_out_ld32_rwb(TCGContext *s, ARMCond cond, TCGReg rt, 693 TCGReg rn, TCGReg rm) 694{ 695 tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 1); 696} 697 698static void tcg_out_st32_rwb(TCGContext *s, ARMCond cond, TCGReg rt, 699 TCGReg rn, TCGReg rm) 700{ 701 tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 1); 702} 703 704static void tcg_out_ld16u_8(TCGContext *s, ARMCond cond, TCGReg rt, 705 TCGReg rn, int imm8) 706{ 707 tcg_out_memop_8(s, cond, INSN_LDRH_IMM, rt, rn, imm8, 1, 0); 708} 709 710static void tcg_out_st16_8(TCGContext *s, ARMCond cond, TCGReg rt, 711 TCGReg rn, int imm8) 712{ 713 tcg_out_memop_8(s, cond, INSN_STRH_IMM, rt, rn, imm8, 1, 0); 714} 715 716static void tcg_out_ld16u_r(TCGContext *s, ARMCond cond, TCGReg rt, 717 TCGReg rn, TCGReg rm) 718{ 719 tcg_out_memop_r(s, cond, INSN_LDRH_REG, rt, rn, rm, 1, 1, 0); 720} 721 722static void tcg_out_st16_r(TCGContext *s, ARMCond cond, TCGReg rt, 723 TCGReg rn, TCGReg rm) 724{ 725 tcg_out_memop_r(s, cond, INSN_STRH_REG, rt, rn, rm, 1, 1, 0); 726} 727 728static void tcg_out_ld16s_8(TCGContext *s, ARMCond cond, TCGReg rt, 729 TCGReg rn, int imm8) 730{ 731 tcg_out_memop_8(s, cond, INSN_LDRSH_IMM, rt, rn, imm8, 1, 0); 732} 733 734static void tcg_out_ld16s_r(TCGContext *s, ARMCond cond, TCGReg rt, 735 TCGReg rn, TCGReg rm) 736{ 737 tcg_out_memop_r(s, cond, INSN_LDRSH_REG, rt, rn, rm, 1, 1, 0); 738} 739 740static void tcg_out_ld8_12(TCGContext *s, ARMCond cond, TCGReg rt, 741 TCGReg rn, int imm12) 742{ 743 tcg_out_memop_12(s, cond, INSN_LDRB_IMM, rt, rn, imm12, 1, 0); 744} 745 746static void tcg_out_st8_12(TCGContext *s, ARMCond cond, TCGReg rt, 747 TCGReg rn, int imm12) 748{ 749 tcg_out_memop_12(s, cond, INSN_STRB_IMM, rt, rn, imm12, 1, 0); 750} 751 752static void tcg_out_ld8_r(TCGContext *s, ARMCond cond, TCGReg rt, 753 TCGReg rn, TCGReg rm) 754{ 755 tcg_out_memop_r(s, cond, INSN_LDRB_REG, rt, rn, rm, 1, 1, 0); 756} 757 758static void tcg_out_st8_r(TCGContext *s, ARMCond cond, TCGReg rt, 759 TCGReg rn, TCGReg rm) 760{ 761 tcg_out_memop_r(s, cond, INSN_STRB_REG, rt, rn, rm, 1, 1, 0); 762} 763 764static void tcg_out_ld8s_8(TCGContext *s, ARMCond cond, TCGReg rt, 765 TCGReg rn, int imm8) 766{ 767 tcg_out_memop_8(s, cond, INSN_LDRSB_IMM, rt, rn, imm8, 1, 0); 768} 769 770static void tcg_out_ld8s_r(TCGContext *s, ARMCond cond, TCGReg rt, 771 TCGReg rn, TCGReg rm) 772{ 773 tcg_out_memop_r(s, cond, INSN_LDRSB_REG, rt, rn, rm, 1, 1, 0); 774} 775 776static void tcg_out_movi_pool(TCGContext *s, ARMCond cond, 777 TCGReg rd, uint32_t arg) 778{ 779 new_pool_label(s, arg, R_ARM_PC13, s->code_ptr, 0); 780 tcg_out_ld32_12(s, cond, rd, TCG_REG_PC, 0); 781} 782 783static void tcg_out_movi32(TCGContext *s, ARMCond cond, 784 TCGReg rd, uint32_t arg) 785{ 786 int imm12, diff, opc, sh1, sh2; 787 uint32_t tt0, tt1, tt2; 788 789 /* Check a single MOV/MVN before anything else. */ 790 imm12 = encode_imm(arg); 791 if (imm12 >= 0) { 792 tcg_out_dat_imm(s, cond, ARITH_MOV, rd, 0, imm12); 793 return; 794 } 795 imm12 = encode_imm(~arg); 796 if (imm12 >= 0) { 797 tcg_out_dat_imm(s, cond, ARITH_MVN, rd, 0, imm12); 798 return; 799 } 800 801 /* Check for a pc-relative address. This will usually be the TB, 802 or within the TB, which is immediately before the code block. */ 803 diff = tcg_pcrel_diff(s, (void *)arg) - 8; 804 if (diff >= 0) { 805 imm12 = encode_imm(diff); 806 if (imm12 >= 0) { 807 tcg_out_dat_imm(s, cond, ARITH_ADD, rd, TCG_REG_PC, imm12); 808 return; 809 } 810 } else { 811 imm12 = encode_imm(-diff); 812 if (imm12 >= 0) { 813 tcg_out_dat_imm(s, cond, ARITH_SUB, rd, TCG_REG_PC, imm12); 814 return; 815 } 816 } 817 818 /* Use movw + movt. */ 819 if (use_armv7_instructions) { 820 /* movw */ 821 tcg_out32(s, (cond << 28) | 0x03000000 | (rd << 12) 822 | ((arg << 4) & 0x000f0000) | (arg & 0xfff)); 823 if (arg & 0xffff0000) { 824 /* movt */ 825 tcg_out32(s, (cond << 28) | 0x03400000 | (rd << 12) 826 | ((arg >> 12) & 0x000f0000) | ((arg >> 16) & 0xfff)); 827 } 828 return; 829 } 830 831 /* Look for sequences of two insns. If we have lots of 1's, we can 832 shorten the sequence by beginning with mvn and then clearing 833 higher bits with eor. */ 834 tt0 = arg; 835 opc = ARITH_MOV; 836 if (ctpop32(arg) > 16) { 837 tt0 = ~arg; 838 opc = ARITH_MVN; 839 } 840 sh1 = ctz32(tt0) & ~1; 841 tt1 = tt0 & ~(0xff << sh1); 842 sh2 = ctz32(tt1) & ~1; 843 tt2 = tt1 & ~(0xff << sh2); 844 if (tt2 == 0) { 845 int rot; 846 847 rot = ((32 - sh1) << 7) & 0xf00; 848 tcg_out_dat_imm(s, cond, opc, rd, 0, ((tt0 >> sh1) & 0xff) | rot); 849 rot = ((32 - sh2) << 7) & 0xf00; 850 tcg_out_dat_imm(s, cond, ARITH_EOR, rd, rd, 851 ((tt0 >> sh2) & 0xff) | rot); 852 return; 853 } 854 855 /* Otherwise, drop it into the constant pool. */ 856 tcg_out_movi_pool(s, cond, rd, arg); 857} 858 859/* 860 * Emit either the reg,imm or reg,reg form of a data-processing insn. 861 * rhs must satisfy the "rI" constraint. 862 */ 863static void tcg_out_dat_rI(TCGContext *s, ARMCond cond, ARMInsn opc, 864 TCGReg dst, TCGReg lhs, TCGArg rhs, int rhs_is_const) 865{ 866 if (rhs_is_const) { 867 tcg_out_dat_imm(s, cond, opc, dst, lhs, encode_imm_nofail(rhs)); 868 } else { 869 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); 870 } 871} 872 873/* 874 * Emit either the reg,imm or reg,reg form of a data-processing insn. 875 * rhs must satisfy the "rIK" constraint. 876 */ 877static void tcg_out_dat_IK(TCGContext *s, ARMCond cond, ARMInsn opc, 878 ARMInsn opinv, TCGReg dst, TCGReg lhs, TCGArg rhs) 879{ 880 int imm12 = encode_imm(rhs); 881 if (imm12 < 0) { 882 imm12 = encode_imm_nofail(~rhs); 883 opc = opinv; 884 } 885 tcg_out_dat_imm(s, cond, opc, dst, lhs, imm12); 886} 887 888static void tcg_out_dat_rIK(TCGContext *s, ARMCond cond, ARMInsn opc, 889 ARMInsn opinv, TCGReg dst, TCGReg lhs, TCGArg rhs, 890 bool rhs_is_const) 891{ 892 if (rhs_is_const) { 893 tcg_out_dat_IK(s, cond, opc, opinv, dst, lhs, rhs); 894 } else { 895 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); 896 } 897} 898 899static void tcg_out_dat_IN(TCGContext *s, ARMCond cond, ARMInsn opc, 900 ARMInsn opneg, TCGReg dst, TCGReg lhs, TCGArg rhs) 901{ 902 int imm12 = encode_imm(rhs); 903 if (imm12 < 0) { 904 imm12 = encode_imm_nofail(-rhs); 905 opc = opneg; 906 } 907 tcg_out_dat_imm(s, cond, opc, dst, lhs, imm12); 908} 909 910static void tcg_out_dat_rIN(TCGContext *s, ARMCond cond, ARMInsn opc, 911 ARMInsn opneg, TCGReg dst, TCGReg lhs, TCGArg rhs, 912 bool rhs_is_const) 913{ 914 /* Emit either the reg,imm or reg,reg form of a data-processing insn. 915 * rhs must satisfy the "rIN" constraint. 916 */ 917 if (rhs_is_const) { 918 tcg_out_dat_IN(s, cond, opc, opneg, dst, lhs, rhs); 919 } else { 920 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); 921 } 922} 923 924static void tcg_out_umull32(TCGContext *s, ARMCond cond, TCGReg rd0, 925 TCGReg rd1, TCGReg rn, TCGReg rm) 926{ 927 /* umull */ 928 tcg_out32(s, (cond << 28) | 0x00800090 | 929 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); 930} 931 932static void tcg_out_smull32(TCGContext *s, ARMCond cond, TCGReg rd0, 933 TCGReg rd1, TCGReg rn, TCGReg rm) 934{ 935 /* smull */ 936 tcg_out32(s, (cond << 28) | 0x00c00090 | 937 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); 938} 939 940static void tcg_out_udiv(TCGContext *s, ARMCond cond, 941 TCGReg rd, TCGReg rn, TCGReg rm) 942{ 943 tcg_out32(s, 0x0730f010 | (cond << 28) | (rd << 16) | rn | (rm << 8)); 944} 945 946static void tcg_out_ext8s(TCGContext *s, TCGType t, TCGReg rd, TCGReg rn) 947{ 948 /* sxtb */ 949 tcg_out32(s, 0x06af0070 | (COND_AL << 28) | (rd << 12) | rn); 950} 951 952static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rn) 953{ 954 tcg_out_dat_imm(s, COND_AL, ARITH_AND, rd, rn, 0xff); 955} 956 957static void tcg_out_ext16s(TCGContext *s, TCGType t, TCGReg rd, TCGReg rn) 958{ 959 /* sxth */ 960 tcg_out32(s, 0x06bf0070 | (COND_AL << 28) | (rd << 12) | rn); 961} 962 963static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rn) 964{ 965 /* uxth */ 966 tcg_out32(s, 0x06ff0070 | (COND_AL << 28) | (rd << 12) | rn); 967} 968 969static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rn) 970{ 971 g_assert_not_reached(); 972} 973 974static void tcg_out_ext32u(TCGContext *s, TCGReg rd, TCGReg rn) 975{ 976 g_assert_not_reached(); 977} 978 979static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rn) 980{ 981 g_assert_not_reached(); 982} 983 984static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rn) 985{ 986 g_assert_not_reached(); 987} 988 989static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rn) 990{ 991 g_assert_not_reached(); 992} 993 994static void tcg_out_bswap16(TCGContext *s, ARMCond cond, 995 TCGReg rd, TCGReg rn, int flags) 996{ 997 if (flags & TCG_BSWAP_OS) { 998 /* revsh */ 999 tcg_out32(s, 0x06ff0fb0 | (cond << 28) | (rd << 12) | rn); 1000 return; 1001 } 1002 1003 /* rev16 */ 1004 tcg_out32(s, 0x06bf0fb0 | (cond << 28) | (rd << 12) | rn); 1005 if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 1006 /* uxth */ 1007 tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | rd); 1008 } 1009} 1010 1011static void tcg_out_bswap32(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rn) 1012{ 1013 /* rev */ 1014 tcg_out32(s, 0x06bf0f30 | (cond << 28) | (rd << 12) | rn); 1015} 1016 1017static void tcg_out_deposit(TCGContext *s, ARMCond cond, TCGReg rd, 1018 TCGArg a1, int ofs, int len, bool const_a1) 1019{ 1020 if (const_a1) { 1021 /* bfi becomes bfc with rn == 15. */ 1022 a1 = 15; 1023 } 1024 /* bfi/bfc */ 1025 tcg_out32(s, 0x07c00010 | (cond << 28) | (rd << 12) | a1 1026 | (ofs << 7) | ((ofs + len - 1) << 16)); 1027} 1028 1029static void tcg_out_extract(TCGContext *s, ARMCond cond, TCGReg rd, 1030 TCGReg rn, int ofs, int len) 1031{ 1032 /* According to gcc, AND can be faster. */ 1033 if (ofs == 0 && len <= 8) { 1034 tcg_out_dat_imm(s, cond, ARITH_AND, rd, rn, 1035 encode_imm_nofail((1 << len) - 1)); 1036 return; 1037 } 1038 1039 if (use_armv7_instructions) { 1040 /* ubfx */ 1041 tcg_out32(s, 0x07e00050 | (cond << 28) | (rd << 12) | rn 1042 | (ofs << 7) | ((len - 1) << 16)); 1043 return; 1044 } 1045 1046 assert(ofs % 8 == 0); 1047 switch (len) { 1048 case 8: 1049 /* uxtb */ 1050 tcg_out32(s, 0x06ef0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn); 1051 break; 1052 case 16: 1053 /* uxth */ 1054 tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn); 1055 break; 1056 default: 1057 g_assert_not_reached(); 1058 } 1059} 1060 1061static void tcg_out_sextract(TCGContext *s, ARMCond cond, TCGReg rd, 1062 TCGReg rn, int ofs, int len) 1063{ 1064 if (use_armv7_instructions) { 1065 /* sbfx */ 1066 tcg_out32(s, 0x07a00050 | (cond << 28) | (rd << 12) | rn 1067 | (ofs << 7) | ((len - 1) << 16)); 1068 return; 1069 } 1070 1071 assert(ofs % 8 == 0); 1072 switch (len) { 1073 case 8: 1074 /* sxtb */ 1075 tcg_out32(s, 0x06af0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn); 1076 break; 1077 case 16: 1078 /* sxth */ 1079 tcg_out32(s, 0x06bf0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn); 1080 break; 1081 default: 1082 g_assert_not_reached(); 1083 } 1084} 1085 1086 1087static void tcg_out_ld32u(TCGContext *s, ARMCond cond, 1088 TCGReg rd, TCGReg rn, int32_t offset) 1089{ 1090 if (offset > 0xfff || offset < -0xfff) { 1091 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1092 tcg_out_ld32_r(s, cond, rd, rn, TCG_REG_TMP); 1093 } else 1094 tcg_out_ld32_12(s, cond, rd, rn, offset); 1095} 1096 1097static void tcg_out_st32(TCGContext *s, ARMCond cond, 1098 TCGReg rd, TCGReg rn, int32_t offset) 1099{ 1100 if (offset > 0xfff || offset < -0xfff) { 1101 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1102 tcg_out_st32_r(s, cond, rd, rn, TCG_REG_TMP); 1103 } else 1104 tcg_out_st32_12(s, cond, rd, rn, offset); 1105} 1106 1107static void tcg_out_ld16u(TCGContext *s, ARMCond cond, 1108 TCGReg rd, TCGReg rn, int32_t offset) 1109{ 1110 if (offset > 0xff || offset < -0xff) { 1111 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1112 tcg_out_ld16u_r(s, cond, rd, rn, TCG_REG_TMP); 1113 } else 1114 tcg_out_ld16u_8(s, cond, rd, rn, offset); 1115} 1116 1117static void tcg_out_ld16s(TCGContext *s, ARMCond cond, 1118 TCGReg rd, TCGReg rn, int32_t offset) 1119{ 1120 if (offset > 0xff || offset < -0xff) { 1121 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1122 tcg_out_ld16s_r(s, cond, rd, rn, TCG_REG_TMP); 1123 } else 1124 tcg_out_ld16s_8(s, cond, rd, rn, offset); 1125} 1126 1127static void tcg_out_st16(TCGContext *s, ARMCond cond, 1128 TCGReg rd, TCGReg rn, int32_t offset) 1129{ 1130 if (offset > 0xff || offset < -0xff) { 1131 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1132 tcg_out_st16_r(s, cond, rd, rn, TCG_REG_TMP); 1133 } else 1134 tcg_out_st16_8(s, cond, rd, rn, offset); 1135} 1136 1137static void tcg_out_ld8u(TCGContext *s, ARMCond cond, 1138 TCGReg rd, TCGReg rn, int32_t offset) 1139{ 1140 if (offset > 0xfff || offset < -0xfff) { 1141 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1142 tcg_out_ld8_r(s, cond, rd, rn, TCG_REG_TMP); 1143 } else 1144 tcg_out_ld8_12(s, cond, rd, rn, offset); 1145} 1146 1147static void tcg_out_ld8s(TCGContext *s, ARMCond cond, 1148 TCGReg rd, TCGReg rn, int32_t offset) 1149{ 1150 if (offset > 0xff || offset < -0xff) { 1151 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1152 tcg_out_ld8s_r(s, cond, rd, rn, TCG_REG_TMP); 1153 } else 1154 tcg_out_ld8s_8(s, cond, rd, rn, offset); 1155} 1156 1157static void tcg_out_st8(TCGContext *s, ARMCond cond, 1158 TCGReg rd, TCGReg rn, int32_t offset) 1159{ 1160 if (offset > 0xfff || offset < -0xfff) { 1161 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1162 tcg_out_st8_r(s, cond, rd, rn, TCG_REG_TMP); 1163 } else 1164 tcg_out_st8_12(s, cond, rd, rn, offset); 1165} 1166 1167/* 1168 * The _goto case is normally between TBs within the same code buffer, and 1169 * with the code buffer limited to 16MB we wouldn't need the long case. 1170 * But we also use it for the tail-call to the qemu_ld/st helpers, which does. 1171 */ 1172static void tcg_out_goto(TCGContext *s, ARMCond cond, const tcg_insn_unit *addr) 1173{ 1174 intptr_t addri = (intptr_t)addr; 1175 ptrdiff_t disp = tcg_pcrel_diff(s, addr); 1176 bool arm_mode = !(addri & 1); 1177 1178 if (arm_mode && disp - 8 < 0x01fffffd && disp - 8 > -0x01fffffd) { 1179 tcg_out_b_imm(s, cond, disp); 1180 return; 1181 } 1182 1183 /* LDR is interworking from v5t. */ 1184 tcg_out_movi_pool(s, cond, TCG_REG_PC, addri); 1185} 1186 1187/* 1188 * The call case is mostly used for helpers - so it's not unreasonable 1189 * for them to be beyond branch range. 1190 */ 1191static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *addr) 1192{ 1193 intptr_t addri = (intptr_t)addr; 1194 ptrdiff_t disp = tcg_pcrel_diff(s, addr); 1195 bool arm_mode = !(addri & 1); 1196 1197 if (disp - 8 < 0x02000000 && disp - 8 >= -0x02000000) { 1198 if (arm_mode) { 1199 tcg_out_bl_imm(s, COND_AL, disp); 1200 } else { 1201 tcg_out_blx_imm(s, disp); 1202 } 1203 return; 1204 } 1205 1206 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri); 1207 tcg_out_blx_reg(s, COND_AL, TCG_REG_TMP); 1208} 1209 1210static void tcg_out_call(TCGContext *s, const tcg_insn_unit *addr, 1211 const TCGHelperInfo *info) 1212{ 1213 tcg_out_call_int(s, addr); 1214} 1215 1216static void tcg_out_goto_label(TCGContext *s, ARMCond cond, TCGLabel *l) 1217{ 1218 if (l->has_value) { 1219 tcg_out_goto(s, cond, l->u.value_ptr); 1220 } else { 1221 tcg_out_reloc(s, s->code_ptr, R_ARM_PC24, l, 0); 1222 tcg_out_b_imm(s, cond, 0); 1223 } 1224} 1225 1226static void tcg_out_mb(TCGContext *s, TCGArg a0) 1227{ 1228 if (use_armv7_instructions) { 1229 tcg_out32(s, INSN_DMB_ISH); 1230 } else { 1231 tcg_out32(s, INSN_DMB_MCR); 1232 } 1233} 1234 1235static TCGCond tcg_out_cmp(TCGContext *s, TCGCond cond, TCGReg a, 1236 TCGArg b, int b_const) 1237{ 1238 if (!is_tst_cond(cond)) { 1239 tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, a, b, b_const); 1240 return cond; 1241 } 1242 1243 cond = tcg_tst_eqne_cond(cond); 1244 if (b_const) { 1245 int imm12 = encode_imm(b); 1246 1247 /* 1248 * The compare constraints allow rIN, but TST does not support N. 1249 * Be prepared to load the constant into a scratch register. 1250 */ 1251 if (imm12 >= 0) { 1252 tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, a, imm12); 1253 return cond; 1254 } 1255 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, b); 1256 b = TCG_REG_TMP; 1257 } 1258 tcg_out_dat_reg(s, COND_AL, ARITH_TST, 0, a, b, SHIFT_IMM_LSL(0)); 1259 return cond; 1260} 1261 1262static TCGCond tcg_out_cmp2(TCGContext *s, const TCGArg *args, 1263 const int *const_args) 1264{ 1265 TCGReg al = args[0]; 1266 TCGReg ah = args[1]; 1267 TCGArg bl = args[2]; 1268 TCGArg bh = args[3]; 1269 TCGCond cond = args[4]; 1270 int const_bl = const_args[2]; 1271 int const_bh = const_args[3]; 1272 1273 switch (cond) { 1274 case TCG_COND_EQ: 1275 case TCG_COND_NE: 1276 case TCG_COND_LTU: 1277 case TCG_COND_LEU: 1278 case TCG_COND_GTU: 1279 case TCG_COND_GEU: 1280 /* 1281 * We perform a conditional comparison. If the high half is 1282 * equal, then overwrite the flags with the comparison of the 1283 * low half. The resulting flags cover the whole. 1284 */ 1285 tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, ah, bh, const_bh); 1286 tcg_out_dat_rI(s, COND_EQ, ARITH_CMP, 0, al, bl, const_bl); 1287 return cond; 1288 1289 case TCG_COND_TSTEQ: 1290 case TCG_COND_TSTNE: 1291 /* Similar, but with TST instead of CMP. */ 1292 tcg_out_dat_rI(s, COND_AL, ARITH_TST, 0, ah, bh, const_bh); 1293 tcg_out_dat_rI(s, COND_EQ, ARITH_TST, 0, al, bl, const_bl); 1294 return tcg_tst_eqne_cond(cond); 1295 1296 case TCG_COND_LT: 1297 case TCG_COND_GE: 1298 /* We perform a double-word subtraction and examine the result. 1299 We do not actually need the result of the subtract, so the 1300 low part "subtract" is a compare. For the high half we have 1301 no choice but to compute into a temporary. */ 1302 tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, al, bl, const_bl); 1303 tcg_out_dat_rI(s, COND_AL, ARITH_SBC | TO_CPSR, 1304 TCG_REG_TMP, ah, bh, const_bh); 1305 return cond; 1306 1307 case TCG_COND_LE: 1308 case TCG_COND_GT: 1309 /* Similar, but with swapped arguments, via reversed subtract. */ 1310 tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR, 1311 TCG_REG_TMP, al, bl, const_bl); 1312 tcg_out_dat_rI(s, COND_AL, ARITH_RSC | TO_CPSR, 1313 TCG_REG_TMP, ah, bh, const_bh); 1314 return tcg_swap_cond(cond); 1315 1316 default: 1317 g_assert_not_reached(); 1318 } 1319} 1320 1321/* 1322 * Note that TCGReg references Q-registers. 1323 * Q-regno = 2 * D-regno, so shift left by 1 while inserting. 1324 */ 1325static uint32_t encode_vd(TCGReg rd) 1326{ 1327 tcg_debug_assert(rd >= TCG_REG_Q0); 1328 return (extract32(rd, 3, 1) << 22) | (extract32(rd, 0, 3) << 13); 1329} 1330 1331static uint32_t encode_vn(TCGReg rn) 1332{ 1333 tcg_debug_assert(rn >= TCG_REG_Q0); 1334 return (extract32(rn, 3, 1) << 7) | (extract32(rn, 0, 3) << 17); 1335} 1336 1337static uint32_t encode_vm(TCGReg rm) 1338{ 1339 tcg_debug_assert(rm >= TCG_REG_Q0); 1340 return (extract32(rm, 3, 1) << 5) | (extract32(rm, 0, 3) << 1); 1341} 1342 1343static void tcg_out_vreg2(TCGContext *s, ARMInsn insn, int q, int vece, 1344 TCGReg d, TCGReg m) 1345{ 1346 tcg_out32(s, insn | (vece << 18) | (q << 6) | 1347 encode_vd(d) | encode_vm(m)); 1348} 1349 1350static void tcg_out_vreg3(TCGContext *s, ARMInsn insn, int q, int vece, 1351 TCGReg d, TCGReg n, TCGReg m) 1352{ 1353 tcg_out32(s, insn | (vece << 20) | (q << 6) | 1354 encode_vd(d) | encode_vn(n) | encode_vm(m)); 1355} 1356 1357static void tcg_out_vmovi(TCGContext *s, TCGReg rd, 1358 int q, int op, int cmode, uint8_t imm8) 1359{ 1360 tcg_out32(s, INSN_VMOVI | encode_vd(rd) | (q << 6) | (op << 5) 1361 | (cmode << 8) | extract32(imm8, 0, 4) 1362 | (extract32(imm8, 4, 3) << 16) 1363 | (extract32(imm8, 7, 1) << 24)); 1364} 1365 1366static void tcg_out_vshifti(TCGContext *s, ARMInsn insn, int q, 1367 TCGReg rd, TCGReg rm, int l_imm6) 1368{ 1369 tcg_out32(s, insn | (q << 6) | encode_vd(rd) | encode_vm(rm) | 1370 (extract32(l_imm6, 6, 1) << 7) | 1371 (extract32(l_imm6, 0, 6) << 16)); 1372} 1373 1374static void tcg_out_vldst(TCGContext *s, ARMInsn insn, 1375 TCGReg rd, TCGReg rn, int offset) 1376{ 1377 if (offset != 0) { 1378 if (check_fit_imm(offset) || check_fit_imm(-offset)) { 1379 tcg_out_dat_rIN(s, COND_AL, ARITH_ADD, ARITH_SUB, 1380 TCG_REG_TMP, rn, offset, true); 1381 } else { 1382 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, offset); 1383 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, 1384 TCG_REG_TMP, TCG_REG_TMP, rn, 0); 1385 } 1386 rn = TCG_REG_TMP; 1387 } 1388 tcg_out32(s, insn | (rn << 16) | encode_vd(rd) | 0xf); 1389} 1390 1391typedef struct { 1392 ARMCond cond; 1393 TCGReg base; 1394 int index; 1395 bool index_scratch; 1396 TCGAtomAlign aa; 1397} HostAddress; 1398 1399bool tcg_target_has_memory_bswap(MemOp memop) 1400{ 1401 return false; 1402} 1403 1404static TCGReg ldst_ra_gen(TCGContext *s, const TCGLabelQemuLdst *l, int arg) 1405{ 1406 /* We arrive at the slow path via "BLNE", so R14 contains l->raddr. */ 1407 return TCG_REG_R14; 1408} 1409 1410static const TCGLdstHelperParam ldst_helper_param = { 1411 .ra_gen = ldst_ra_gen, 1412 .ntmp = 1, 1413 .tmp = { TCG_REG_TMP }, 1414}; 1415 1416static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1417{ 1418 MemOp opc = get_memop(lb->oi); 1419 1420 if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1421 return false; 1422 } 1423 1424 tcg_out_ld_helper_args(s, lb, &ldst_helper_param); 1425 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE]); 1426 tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param); 1427 1428 tcg_out_goto(s, COND_AL, lb->raddr); 1429 return true; 1430} 1431 1432static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1433{ 1434 MemOp opc = get_memop(lb->oi); 1435 1436 if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1437 return false; 1438 } 1439 1440 tcg_out_st_helper_args(s, lb, &ldst_helper_param); 1441 1442 /* Tail-call to the helper, which will return to the fast path. */ 1443 tcg_out_goto(s, COND_AL, qemu_st_helpers[opc & MO_SIZE]); 1444 return true; 1445} 1446 1447/* We expect to use an 9-bit sign-magnitude negative offset from ENV. */ 1448#define MIN_TLB_MASK_TABLE_OFS -256 1449 1450static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1451 TCGReg addr, MemOpIdx oi, bool is_ld) 1452{ 1453 TCGLabelQemuLdst *ldst = NULL; 1454 MemOp opc = get_memop(oi); 1455 unsigned a_mask; 1456 1457 if (tcg_use_softmmu) { 1458 *h = (HostAddress){ 1459 .cond = COND_AL, 1460 .base = addr, 1461 .index = TCG_REG_R1, 1462 .index_scratch = true, 1463 }; 1464 } else { 1465 *h = (HostAddress){ 1466 .cond = COND_AL, 1467 .base = addr, 1468 .index = guest_base ? TCG_REG_GUEST_BASE : -1, 1469 .index_scratch = false, 1470 }; 1471 } 1472 1473 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); 1474 a_mask = (1 << h->aa.align) - 1; 1475 1476 if (tcg_use_softmmu) { 1477 int mem_index = get_mmuidx(oi); 1478 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read) 1479 : offsetof(CPUTLBEntry, addr_write); 1480 int fast_off = tlb_mask_table_ofs(s, mem_index); 1481 unsigned s_mask = (1 << (opc & MO_SIZE)) - 1; 1482 TCGReg t_addr; 1483 1484 ldst = new_ldst_label(s); 1485 ldst->is_ld = is_ld; 1486 ldst->oi = oi; 1487 ldst->addr_reg = addr; 1488 1489 /* Load cpu->neg.tlb.f[mmu_idx].{mask,table} into {r0,r1}. */ 1490 QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0); 1491 QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != 4); 1492 tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off); 1493 1494 /* Extract the tlb index from the address into R0. */ 1495 tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, addr, 1496 SHIFT_IMM_LSR(s->page_bits - CPU_TLB_ENTRY_BITS)); 1497 1498 /* 1499 * Add the tlb_table pointer, creating the CPUTLBEntry address in R1. 1500 * Load the tlb comparator into R2 and the fast path addend into R1. 1501 */ 1502 if (cmp_off == 0) { 1503 tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0); 1504 } else { 1505 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, 1506 TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0); 1507 tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); 1508 } 1509 1510 /* Load the tlb addend. */ 1511 tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R1, 1512 offsetof(CPUTLBEntry, addend)); 1513 1514 /* 1515 * Check alignment, check comparators. 1516 * Do this in 2-4 insns. Use MOVW for v7, if possible, 1517 * to reduce the number of sequential conditional instructions. 1518 * Almost all guests have at least 4k pages, which means that we need 1519 * to clear at least 9 bits even for an 8-byte memory, which means it 1520 * isn't worth checking for an immediate operand for BIC. 1521 * 1522 * For unaligned accesses, test the page of the last unit of alignment. 1523 * This leaves the least significant alignment bits unchanged, and of 1524 * course must be zero. 1525 */ 1526 t_addr = addr; 1527 if (a_mask < s_mask) { 1528 t_addr = TCG_REG_R0; 1529 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, t_addr, 1530 addr, s_mask - a_mask); 1531 } 1532 if (use_armv7_instructions && s->page_bits <= 16) { 1533 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, ~(s->page_mask | a_mask)); 1534 tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP, 1535 t_addr, TCG_REG_TMP, 0); 1536 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, 1537 TCG_REG_R2, TCG_REG_TMP, 0); 1538 } else { 1539 if (a_mask) { 1540 tcg_debug_assert(a_mask <= 0xff); 1541 tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addr, a_mask); 1542 } 1543 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, t_addr, 1544 SHIFT_IMM_LSR(s->page_bits)); 1545 tcg_out_dat_reg(s, (a_mask ? COND_EQ : COND_AL), ARITH_CMP, 1546 0, TCG_REG_R2, TCG_REG_TMP, 1547 SHIFT_IMM_LSL(s->page_bits)); 1548 } 1549 } else if (a_mask) { 1550 ldst = new_ldst_label(s); 1551 ldst->is_ld = is_ld; 1552 ldst->oi = oi; 1553 ldst->addr_reg = addr; 1554 1555 /* We are expecting alignment to max out at 7 */ 1556 tcg_debug_assert(a_mask <= 0xff); 1557 /* tst addr, #mask */ 1558 tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addr, a_mask); 1559 } 1560 1561 return ldst; 1562} 1563 1564static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo, 1565 TCGReg datahi, HostAddress h) 1566{ 1567 TCGReg base; 1568 1569 /* Byte swapping is left to middle-end expansion. */ 1570 tcg_debug_assert((opc & MO_BSWAP) == 0); 1571 1572 switch (opc & MO_SSIZE) { 1573 case MO_UB: 1574 if (h.index < 0) { 1575 tcg_out_ld8_12(s, h.cond, datalo, h.base, 0); 1576 } else { 1577 tcg_out_ld8_r(s, h.cond, datalo, h.base, h.index); 1578 } 1579 break; 1580 case MO_SB: 1581 if (h.index < 0) { 1582 tcg_out_ld8s_8(s, h.cond, datalo, h.base, 0); 1583 } else { 1584 tcg_out_ld8s_r(s, h.cond, datalo, h.base, h.index); 1585 } 1586 break; 1587 case MO_UW: 1588 if (h.index < 0) { 1589 tcg_out_ld16u_8(s, h.cond, datalo, h.base, 0); 1590 } else { 1591 tcg_out_ld16u_r(s, h.cond, datalo, h.base, h.index); 1592 } 1593 break; 1594 case MO_SW: 1595 if (h.index < 0) { 1596 tcg_out_ld16s_8(s, h.cond, datalo, h.base, 0); 1597 } else { 1598 tcg_out_ld16s_r(s, h.cond, datalo, h.base, h.index); 1599 } 1600 break; 1601 case MO_UL: 1602 if (h.index < 0) { 1603 tcg_out_ld32_12(s, h.cond, datalo, h.base, 0); 1604 } else { 1605 tcg_out_ld32_r(s, h.cond, datalo, h.base, h.index); 1606 } 1607 break; 1608 case MO_UQ: 1609 /* We used pair allocation for datalo, so already should be aligned. */ 1610 tcg_debug_assert((datalo & 1) == 0); 1611 tcg_debug_assert(datahi == datalo + 1); 1612 /* LDRD requires alignment; double-check that. */ 1613 if (memop_alignment_bits(opc) >= MO_64) { 1614 if (h.index < 0) { 1615 tcg_out_ldrd_8(s, h.cond, datalo, h.base, 0); 1616 break; 1617 } 1618 /* 1619 * Rm (the second address op) must not overlap Rt or Rt + 1. 1620 * Since datalo is aligned, we can simplify the test via alignment. 1621 * Flip the two address arguments if that works. 1622 */ 1623 if ((h.index & ~1) != datalo) { 1624 tcg_out_ldrd_r(s, h.cond, datalo, h.base, h.index); 1625 break; 1626 } 1627 if ((h.base & ~1) != datalo) { 1628 tcg_out_ldrd_r(s, h.cond, datalo, h.index, h.base); 1629 break; 1630 } 1631 } 1632 if (h.index < 0) { 1633 base = h.base; 1634 if (datalo == h.base) { 1635 tcg_out_mov_reg(s, h.cond, TCG_REG_TMP, base); 1636 base = TCG_REG_TMP; 1637 } 1638 } else if (h.index_scratch) { 1639 tcg_out_ld32_rwb(s, h.cond, datalo, h.index, h.base); 1640 tcg_out_ld32_12(s, h.cond, datahi, h.index, 4); 1641 break; 1642 } else { 1643 tcg_out_dat_reg(s, h.cond, ARITH_ADD, TCG_REG_TMP, 1644 h.base, h.index, SHIFT_IMM_LSL(0)); 1645 base = TCG_REG_TMP; 1646 } 1647 tcg_out_ld32_12(s, h.cond, datalo, base, 0); 1648 tcg_out_ld32_12(s, h.cond, datahi, base, 4); 1649 break; 1650 default: 1651 g_assert_not_reached(); 1652 } 1653} 1654 1655static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, 1656 TCGReg addr, MemOpIdx oi, TCGType data_type) 1657{ 1658 MemOp opc = get_memop(oi); 1659 TCGLabelQemuLdst *ldst; 1660 HostAddress h; 1661 1662 ldst = prepare_host_addr(s, &h, addr, oi, true); 1663 if (ldst) { 1664 ldst->type = data_type; 1665 ldst->datalo_reg = datalo; 1666 ldst->datahi_reg = datahi; 1667 1668 /* 1669 * This a conditional BL only to load a pointer within this 1670 * opcode into LR for the slow path. We will not be using 1671 * the value for a tail call. 1672 */ 1673 ldst->label_ptr[0] = s->code_ptr; 1674 tcg_out_bl_imm(s, COND_NE, 0); 1675 1676 tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); 1677 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1678 } else { 1679 tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); 1680 } 1681} 1682 1683static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo, 1684 TCGReg datahi, HostAddress h) 1685{ 1686 /* Byte swapping is left to middle-end expansion. */ 1687 tcg_debug_assert((opc & MO_BSWAP) == 0); 1688 1689 switch (opc & MO_SIZE) { 1690 case MO_8: 1691 if (h.index < 0) { 1692 tcg_out_st8_12(s, h.cond, datalo, h.base, 0); 1693 } else { 1694 tcg_out_st8_r(s, h.cond, datalo, h.base, h.index); 1695 } 1696 break; 1697 case MO_16: 1698 if (h.index < 0) { 1699 tcg_out_st16_8(s, h.cond, datalo, h.base, 0); 1700 } else { 1701 tcg_out_st16_r(s, h.cond, datalo, h.base, h.index); 1702 } 1703 break; 1704 case MO_32: 1705 if (h.index < 0) { 1706 tcg_out_st32_12(s, h.cond, datalo, h.base, 0); 1707 } else { 1708 tcg_out_st32_r(s, h.cond, datalo, h.base, h.index); 1709 } 1710 break; 1711 case MO_64: 1712 /* We used pair allocation for datalo, so already should be aligned. */ 1713 tcg_debug_assert((datalo & 1) == 0); 1714 tcg_debug_assert(datahi == datalo + 1); 1715 /* STRD requires alignment; double-check that. */ 1716 if (memop_alignment_bits(opc) >= MO_64) { 1717 if (h.index < 0) { 1718 tcg_out_strd_8(s, h.cond, datalo, h.base, 0); 1719 } else { 1720 tcg_out_strd_r(s, h.cond, datalo, h.base, h.index); 1721 } 1722 } else if (h.index < 0) { 1723 tcg_out_st32_12(s, h.cond, datalo, h.base, 0); 1724 tcg_out_st32_12(s, h.cond, datahi, h.base, 4); 1725 } else if (h.index_scratch) { 1726 tcg_out_st32_rwb(s, h.cond, datalo, h.index, h.base); 1727 tcg_out_st32_12(s, h.cond, datahi, h.index, 4); 1728 } else { 1729 tcg_out_dat_reg(s, h.cond, ARITH_ADD, TCG_REG_TMP, 1730 h.base, h.index, SHIFT_IMM_LSL(0)); 1731 tcg_out_st32_12(s, h.cond, datalo, TCG_REG_TMP, 0); 1732 tcg_out_st32_12(s, h.cond, datahi, TCG_REG_TMP, 4); 1733 } 1734 break; 1735 default: 1736 g_assert_not_reached(); 1737 } 1738} 1739 1740static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, 1741 TCGReg addr, MemOpIdx oi, TCGType data_type) 1742{ 1743 MemOp opc = get_memop(oi); 1744 TCGLabelQemuLdst *ldst; 1745 HostAddress h; 1746 1747 ldst = prepare_host_addr(s, &h, addr, oi, false); 1748 if (ldst) { 1749 ldst->type = data_type; 1750 ldst->datalo_reg = datalo; 1751 ldst->datahi_reg = datahi; 1752 1753 h.cond = COND_EQ; 1754 tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); 1755 1756 /* The conditional call is last, as we're going to return here. */ 1757 ldst->label_ptr[0] = s->code_ptr; 1758 tcg_out_bl_imm(s, COND_NE, 0); 1759 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1760 } else { 1761 tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); 1762 } 1763} 1764 1765static void tcg_out_epilogue(TCGContext *s); 1766 1767static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg) 1768{ 1769 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, arg); 1770 tcg_out_epilogue(s); 1771} 1772 1773static void tcg_out_goto_tb(TCGContext *s, int which) 1774{ 1775 uintptr_t i_addr; 1776 intptr_t i_disp; 1777 1778 /* Direct branch will be patched by tb_target_set_jmp_target. */ 1779 set_jmp_insn_offset(s, which); 1780 tcg_out32(s, INSN_NOP); 1781 1782 /* When branch is out of range, fall through to indirect. */ 1783 i_addr = get_jmp_target_addr(s, which); 1784 i_disp = tcg_pcrel_diff(s, (void *)i_addr) - 8; 1785 tcg_debug_assert(i_disp < 0); 1786 if (i_disp >= -0xfff) { 1787 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, i_disp); 1788 } else { 1789 /* 1790 * The TB is close, but outside the 12 bits addressable by 1791 * the load. We can extend this to 20 bits with a sub of a 1792 * shifted immediate from pc. 1793 */ 1794 int h = -i_disp; 1795 int l = -(h & 0xfff); 1796 1797 h = encode_imm_nofail(h + l); 1798 tcg_out_dat_imm(s, COND_AL, ARITH_SUB, TCG_REG_R0, TCG_REG_PC, h); 1799 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_R0, l); 1800 } 1801 set_jmp_reset_offset(s, which); 1802} 1803 1804void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1805 uintptr_t jmp_rx, uintptr_t jmp_rw) 1806{ 1807 uintptr_t addr = tb->jmp_target_addr[n]; 1808 ptrdiff_t offset = addr - (jmp_rx + 8); 1809 tcg_insn_unit insn; 1810 1811 /* Either directly branch, or fall through to indirect branch. */ 1812 if (offset == sextract64(offset, 0, 26)) { 1813 /* B <addr> */ 1814 insn = deposit32((COND_AL << 28) | INSN_B, 0, 24, offset >> 2); 1815 } else { 1816 insn = INSN_NOP; 1817 } 1818 1819 qatomic_set((uint32_t *)jmp_rw, insn); 1820 flush_idcache_range(jmp_rx, jmp_rw, 4); 1821} 1822 1823 1824static void tgen_add(TCGContext *s, TCGType type, 1825 TCGReg a0, TCGReg a1, TCGReg a2) 1826{ 1827 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, a0, a1, a2, SHIFT_IMM_LSL(0)); 1828} 1829 1830static void tgen_addi(TCGContext *s, TCGType type, 1831 TCGReg a0, TCGReg a1, tcg_target_long a2) 1832{ 1833 tcg_out_dat_IN(s, COND_AL, ARITH_ADD, ARITH_SUB, a0, a1, a2); 1834} 1835 1836static const TCGOutOpBinary outop_add = { 1837 .base.static_constraint = C_O1_I2(r, r, rIN), 1838 .out_rrr = tgen_add, 1839 .out_rri = tgen_addi, 1840}; 1841 1842static void tgen_and(TCGContext *s, TCGType type, 1843 TCGReg a0, TCGReg a1, TCGReg a2) 1844{ 1845 tcg_out_dat_reg(s, COND_AL, ARITH_AND, a0, a1, a2, SHIFT_IMM_LSL(0)); 1846} 1847 1848static void tgen_andi(TCGContext *s, TCGType type, 1849 TCGReg a0, TCGReg a1, tcg_target_long a2) 1850{ 1851 tcg_out_dat_IK(s, COND_AL, ARITH_AND, ARITH_BIC, a0, a1, a2); 1852} 1853 1854static const TCGOutOpBinary outop_and = { 1855 .base.static_constraint = C_O1_I2(r, r, rIK), 1856 .out_rrr = tgen_and, 1857 .out_rri = tgen_andi, 1858}; 1859 1860static void tgen_andc(TCGContext *s, TCGType type, 1861 TCGReg a0, TCGReg a1, TCGReg a2) 1862{ 1863 tcg_out_dat_reg(s, COND_AL, ARITH_BIC, a0, a1, a2, SHIFT_IMM_LSL(0)); 1864} 1865 1866static const TCGOutOpBinary outop_andc = { 1867 .base.static_constraint = C_O1_I2(r, r, r), 1868 .out_rrr = tgen_andc, 1869}; 1870 1871static TCGConstraintSetIndex cset_idiv(TCGType type, unsigned flags) 1872{ 1873 return use_idiv_instructions ? C_O1_I2(r, r, r) : C_NotImplemented; 1874} 1875 1876static void tgen_divs(TCGContext *s, TCGType type, 1877 TCGReg a0, TCGReg a1, TCGReg a2) 1878{ 1879 /* sdiv */ 1880 tcg_out32(s, 0x0710f010 | (COND_AL << 28) | (a0 << 16) | a1 | (a2 << 8)); 1881} 1882 1883static const TCGOutOpBinary outop_divs = { 1884 .base.static_constraint = C_Dynamic, 1885 .base.dynamic_constraint = cset_idiv, 1886 .out_rrr = tgen_divs, 1887}; 1888 1889static const TCGOutOpBinary outop_eqv = { 1890 .base.static_constraint = C_NotImplemented, 1891}; 1892 1893static void tgen_mul(TCGContext *s, TCGType type, 1894 TCGReg a0, TCGReg a1, TCGReg a2) 1895{ 1896 /* mul */ 1897 tcg_out32(s, (COND_AL << 28) | 0x90 | (a0 << 16) | (a1 << 8) | a2); 1898} 1899 1900static const TCGOutOpBinary outop_mul = { 1901 .base.static_constraint = C_O1_I2(r, r, r), 1902 .out_rrr = tgen_mul, 1903}; 1904 1905static const TCGOutOpBinary outop_mulsh = { 1906 .base.static_constraint = C_NotImplemented, 1907}; 1908 1909static const TCGOutOpBinary outop_muluh = { 1910 .base.static_constraint = C_NotImplemented, 1911}; 1912 1913static const TCGOutOpBinary outop_nand = { 1914 .base.static_constraint = C_NotImplemented, 1915}; 1916 1917static const TCGOutOpBinary outop_nor = { 1918 .base.static_constraint = C_NotImplemented, 1919}; 1920 1921static void tgen_or(TCGContext *s, TCGType type, 1922 TCGReg a0, TCGReg a1, TCGReg a2) 1923{ 1924 tcg_out_dat_reg(s, COND_AL, ARITH_ORR, a0, a1, a2, SHIFT_IMM_LSL(0)); 1925} 1926 1927static void tgen_ori(TCGContext *s, TCGType type, 1928 TCGReg a0, TCGReg a1, tcg_target_long a2) 1929{ 1930 tcg_out_dat_imm(s, COND_AL, ARITH_ORR, a0, a1, encode_imm_nofail(a2)); 1931} 1932 1933static const TCGOutOpBinary outop_or = { 1934 .base.static_constraint = C_O1_I2(r, r, rI), 1935 .out_rrr = tgen_or, 1936 .out_rri = tgen_ori, 1937}; 1938 1939static const TCGOutOpBinary outop_orc = { 1940 .base.static_constraint = C_NotImplemented, 1941}; 1942 1943static void tgen_sub(TCGContext *s, TCGType type, 1944 TCGReg a0, TCGReg a1, TCGReg a2) 1945{ 1946 tcg_out_dat_reg(s, COND_AL, ARITH_SUB, a0, a1, a2, SHIFT_IMM_LSL(0)); 1947} 1948 1949static void tgen_subfi(TCGContext *s, TCGType type, 1950 TCGReg a0, tcg_target_long a1, TCGReg a2) 1951{ 1952 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, a0, a2, encode_imm_nofail(a1)); 1953} 1954 1955static const TCGOutOpSubtract outop_sub = { 1956 .base.static_constraint = C_O1_I2(r, rI, r), 1957 .out_rrr = tgen_sub, 1958 .out_rir = tgen_subfi, 1959}; 1960 1961static void tgen_xor(TCGContext *s, TCGType type, 1962 TCGReg a0, TCGReg a1, TCGReg a2) 1963{ 1964 tcg_out_dat_reg(s, COND_AL, ARITH_EOR, a0, a1, a2, SHIFT_IMM_LSL(0)); 1965} 1966 1967static void tgen_xori(TCGContext *s, TCGType type, 1968 TCGReg a0, TCGReg a1, tcg_target_long a2) 1969{ 1970 tcg_out_dat_imm(s, COND_AL, ARITH_EOR, a0, a1, encode_imm_nofail(a2)); 1971} 1972 1973static const TCGOutOpBinary outop_xor = { 1974 .base.static_constraint = C_O1_I2(r, r, rI), 1975 .out_rrr = tgen_xor, 1976 .out_rri = tgen_xori, 1977}; 1978 1979static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 1980{ 1981 tgen_subfi(s, type, a0, 0, a1); 1982} 1983 1984static const TCGOutOpUnary outop_neg = { 1985 .base.static_constraint = C_O1_I1(r, r), 1986 .out_rr = tgen_neg, 1987}; 1988 1989static void tgen_not(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 1990{ 1991 tcg_out_dat_reg(s, COND_AL, ARITH_MVN, a0, 0, a1, SHIFT_IMM_LSL(0)); 1992} 1993 1994static const TCGOutOpUnary outop_not = { 1995 .base.static_constraint = C_O1_I1(r, r), 1996 .out_rr = tgen_not, 1997}; 1998 1999 2000static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, 2001 const TCGArg args[TCG_MAX_OP_ARGS], 2002 const int const_args[TCG_MAX_OP_ARGS]) 2003{ 2004 TCGArg a0, a1, a2, a3, a4, a5; 2005 int c; 2006 2007 switch (opc) { 2008 case INDEX_op_goto_ptr: 2009 tcg_out_b_reg(s, COND_AL, args[0]); 2010 break; 2011 case INDEX_op_br: 2012 tcg_out_goto_label(s, COND_AL, arg_label(args[0])); 2013 break; 2014 2015 case INDEX_op_ld8u_i32: 2016 tcg_out_ld8u(s, COND_AL, args[0], args[1], args[2]); 2017 break; 2018 case INDEX_op_ld8s_i32: 2019 tcg_out_ld8s(s, COND_AL, args[0], args[1], args[2]); 2020 break; 2021 case INDEX_op_ld16u_i32: 2022 tcg_out_ld16u(s, COND_AL, args[0], args[1], args[2]); 2023 break; 2024 case INDEX_op_ld16s_i32: 2025 tcg_out_ld16s(s, COND_AL, args[0], args[1], args[2]); 2026 break; 2027 case INDEX_op_ld_i32: 2028 tcg_out_ld32u(s, COND_AL, args[0], args[1], args[2]); 2029 break; 2030 case INDEX_op_st8_i32: 2031 tcg_out_st8(s, COND_AL, args[0], args[1], args[2]); 2032 break; 2033 case INDEX_op_st16_i32: 2034 tcg_out_st16(s, COND_AL, args[0], args[1], args[2]); 2035 break; 2036 case INDEX_op_st_i32: 2037 tcg_out_st32(s, COND_AL, args[0], args[1], args[2]); 2038 break; 2039 2040 case INDEX_op_movcond_i32: 2041 /* Constraints mean that v2 is always in the same register as dest, 2042 * so we only need to do "if condition passed, move v1 to dest". 2043 */ 2044 c = tcg_out_cmp(s, args[5], args[1], args[2], const_args[2]); 2045 tcg_out_dat_rIK(s, tcg_cond_to_arm_cond[c], ARITH_MOV, 2046 ARITH_MVN, args[0], 0, args[3], const_args[3]); 2047 break; 2048 case INDEX_op_add2_i32: 2049 a0 = args[0], a1 = args[1], a2 = args[2]; 2050 a3 = args[3], a4 = args[4], a5 = args[5]; 2051 if (a0 == a3 || (a0 == a5 && !const_args[5])) { 2052 a0 = TCG_REG_TMP; 2053 } 2054 tcg_out_dat_rIN(s, COND_AL, ARITH_ADD | TO_CPSR, ARITH_SUB | TO_CPSR, 2055 a0, a2, a4, const_args[4]); 2056 tcg_out_dat_rIK(s, COND_AL, ARITH_ADC, ARITH_SBC, 2057 a1, a3, a5, const_args[5]); 2058 tcg_out_mov_reg(s, COND_AL, args[0], a0); 2059 break; 2060 case INDEX_op_sub2_i32: 2061 a0 = args[0], a1 = args[1], a2 = args[2]; 2062 a3 = args[3], a4 = args[4], a5 = args[5]; 2063 if ((a0 == a3 && !const_args[3]) || (a0 == a5 && !const_args[5])) { 2064 a0 = TCG_REG_TMP; 2065 } 2066 if (const_args[2]) { 2067 if (const_args[4]) { 2068 tcg_out_movi32(s, COND_AL, a0, a4); 2069 a4 = a0; 2070 } 2071 tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR, a0, a4, a2, 1); 2072 } else { 2073 tcg_out_dat_rIN(s, COND_AL, ARITH_SUB | TO_CPSR, 2074 ARITH_ADD | TO_CPSR, a0, a2, a4, const_args[4]); 2075 } 2076 if (const_args[3]) { 2077 if (const_args[5]) { 2078 tcg_out_movi32(s, COND_AL, a1, a5); 2079 a5 = a1; 2080 } 2081 tcg_out_dat_rI(s, COND_AL, ARITH_RSC, a1, a5, a3, 1); 2082 } else { 2083 tcg_out_dat_rIK(s, COND_AL, ARITH_SBC, ARITH_ADC, 2084 a1, a3, a5, const_args[5]); 2085 } 2086 tcg_out_mov_reg(s, COND_AL, args[0], a0); 2087 break; 2088 case INDEX_op_mulu2_i32: 2089 tcg_out_umull32(s, COND_AL, args[0], args[1], args[2], args[3]); 2090 break; 2091 case INDEX_op_muls2_i32: 2092 tcg_out_smull32(s, COND_AL, args[0], args[1], args[2], args[3]); 2093 break; 2094 /* XXX: Perhaps args[2] & 0x1f is wrong */ 2095 case INDEX_op_shl_i32: 2096 c = const_args[2] ? 2097 SHIFT_IMM_LSL(args[2] & 0x1f) : SHIFT_REG_LSL(args[2]); 2098 goto gen_shift32; 2099 case INDEX_op_shr_i32: 2100 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_LSR(args[2] & 0x1f) : 2101 SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args[2]); 2102 goto gen_shift32; 2103 case INDEX_op_sar_i32: 2104 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ASR(args[2] & 0x1f) : 2105 SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args[2]); 2106 goto gen_shift32; 2107 case INDEX_op_rotr_i32: 2108 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ROR(args[2] & 0x1f) : 2109 SHIFT_IMM_LSL(0) : SHIFT_REG_ROR(args[2]); 2110 /* Fall through. */ 2111 gen_shift32: 2112 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], c); 2113 break; 2114 2115 case INDEX_op_rotl_i32: 2116 if (const_args[2]) { 2117 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], 2118 ((0x20 - args[2]) & 0x1f) ? 2119 SHIFT_IMM_ROR((0x20 - args[2]) & 0x1f) : 2120 SHIFT_IMM_LSL(0)); 2121 } else { 2122 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, TCG_REG_TMP, args[2], 0x20); 2123 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], 2124 SHIFT_REG_ROR(TCG_REG_TMP)); 2125 } 2126 break; 2127 2128 case INDEX_op_ctz_i32: 2129 tcg_out_dat_reg(s, COND_AL, INSN_RBIT, TCG_REG_TMP, 0, args[1], 0); 2130 a1 = TCG_REG_TMP; 2131 goto do_clz; 2132 2133 case INDEX_op_clz_i32: 2134 a1 = args[1]; 2135 do_clz: 2136 a0 = args[0]; 2137 a2 = args[2]; 2138 c = const_args[2]; 2139 if (c && a2 == 32) { 2140 tcg_out_dat_reg(s, COND_AL, INSN_CLZ, a0, 0, a1, 0); 2141 break; 2142 } 2143 tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0, a1, 0); 2144 tcg_out_dat_reg(s, COND_NE, INSN_CLZ, a0, 0, a1, 0); 2145 if (c || a0 != a2) { 2146 tcg_out_dat_rIK(s, COND_EQ, ARITH_MOV, ARITH_MVN, a0, 0, a2, c); 2147 } 2148 break; 2149 2150 case INDEX_op_brcond_i32: 2151 c = tcg_out_cmp(s, args[2], args[0], args[1], const_args[1]); 2152 tcg_out_goto_label(s, tcg_cond_to_arm_cond[c], arg_label(args[3])); 2153 break; 2154 case INDEX_op_setcond_i32: 2155 c = tcg_out_cmp(s, args[3], args[1], args[2], const_args[2]); 2156 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[c], 2157 ARITH_MOV, args[0], 0, 1); 2158 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(c)], 2159 ARITH_MOV, args[0], 0, 0); 2160 break; 2161 case INDEX_op_negsetcond_i32: 2162 c = tcg_out_cmp(s, args[3], args[1], args[2], const_args[2]); 2163 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[c], 2164 ARITH_MVN, args[0], 0, 0); 2165 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(c)], 2166 ARITH_MOV, args[0], 0, 0); 2167 break; 2168 2169 case INDEX_op_brcond2_i32: 2170 c = tcg_out_cmp2(s, args, const_args); 2171 tcg_out_goto_label(s, tcg_cond_to_arm_cond[c], arg_label(args[5])); 2172 break; 2173 case INDEX_op_setcond2_i32: 2174 c = tcg_out_cmp2(s, args + 1, const_args + 1); 2175 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[c], ARITH_MOV, args[0], 0, 1); 2176 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(c)], 2177 ARITH_MOV, args[0], 0, 0); 2178 break; 2179 2180 case INDEX_op_qemu_ld_i32: 2181 tcg_out_qemu_ld(s, args[0], -1, args[1], args[2], TCG_TYPE_I32); 2182 break; 2183 case INDEX_op_qemu_ld_i64: 2184 tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3], TCG_TYPE_I64); 2185 break; 2186 2187 case INDEX_op_qemu_st_i32: 2188 tcg_out_qemu_st(s, args[0], -1, args[1], args[2], TCG_TYPE_I32); 2189 break; 2190 case INDEX_op_qemu_st_i64: 2191 tcg_out_qemu_st(s, args[0], args[1], args[2], args[3], TCG_TYPE_I64); 2192 break; 2193 2194 case INDEX_op_bswap16_i32: 2195 tcg_out_bswap16(s, COND_AL, args[0], args[1], args[2]); 2196 break; 2197 case INDEX_op_bswap32_i32: 2198 tcg_out_bswap32(s, COND_AL, args[0], args[1]); 2199 break; 2200 2201 case INDEX_op_deposit_i32: 2202 tcg_out_deposit(s, COND_AL, args[0], args[2], 2203 args[3], args[4], const_args[2]); 2204 break; 2205 case INDEX_op_extract_i32: 2206 tcg_out_extract(s, COND_AL, args[0], args[1], args[2], args[3]); 2207 break; 2208 case INDEX_op_sextract_i32: 2209 tcg_out_sextract(s, COND_AL, args[0], args[1], args[2], args[3]); 2210 break; 2211 case INDEX_op_extract2_i32: 2212 /* ??? These optimization vs zero should be generic. */ 2213 /* ??? But we can't substitute 2 for 1 in the opcode stream yet. */ 2214 if (const_args[1]) { 2215 if (const_args[2]) { 2216 tcg_out_movi(s, TCG_TYPE_REG, args[0], 0); 2217 } else { 2218 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, 2219 args[2], SHIFT_IMM_LSL(32 - args[3])); 2220 } 2221 } else if (const_args[2]) { 2222 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, 2223 args[1], SHIFT_IMM_LSR(args[3])); 2224 } else { 2225 /* We can do extract2 in 2 insns, vs the 3 required otherwise. */ 2226 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, 2227 args[2], SHIFT_IMM_LSL(32 - args[3])); 2228 tcg_out_dat_reg(s, COND_AL, ARITH_ORR, args[0], TCG_REG_TMP, 2229 args[1], SHIFT_IMM_LSR(args[3])); 2230 } 2231 break; 2232 2233 case INDEX_op_divu_i32: 2234 tcg_out_udiv(s, COND_AL, args[0], args[1], args[2]); 2235 break; 2236 2237 case INDEX_op_mb: 2238 tcg_out_mb(s, args[0]); 2239 break; 2240 2241 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2242 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2243 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2244 default: 2245 g_assert_not_reached(); 2246 } 2247} 2248 2249static TCGConstraintSetIndex 2250tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) 2251{ 2252 switch (op) { 2253 case INDEX_op_goto_ptr: 2254 return C_O0_I1(r); 2255 2256 case INDEX_op_ld8u_i32: 2257 case INDEX_op_ld8s_i32: 2258 case INDEX_op_ld16u_i32: 2259 case INDEX_op_ld16s_i32: 2260 case INDEX_op_ld_i32: 2261 case INDEX_op_bswap16_i32: 2262 case INDEX_op_bswap32_i32: 2263 case INDEX_op_extract_i32: 2264 case INDEX_op_sextract_i32: 2265 return C_O1_I1(r, r); 2266 2267 case INDEX_op_st8_i32: 2268 case INDEX_op_st16_i32: 2269 case INDEX_op_st_i32: 2270 return C_O0_I2(r, r); 2271 2272 case INDEX_op_setcond_i32: 2273 case INDEX_op_negsetcond_i32: 2274 return C_O1_I2(r, r, rIN); 2275 2276 case INDEX_op_clz_i32: 2277 case INDEX_op_ctz_i32: 2278 return C_O1_I2(r, r, rIK); 2279 2280 case INDEX_op_divu_i32: 2281 return C_O1_I2(r, r, r); 2282 2283 case INDEX_op_mulu2_i32: 2284 case INDEX_op_muls2_i32: 2285 return C_O2_I2(r, r, r, r); 2286 2287 case INDEX_op_shl_i32: 2288 case INDEX_op_shr_i32: 2289 case INDEX_op_sar_i32: 2290 case INDEX_op_rotl_i32: 2291 case INDEX_op_rotr_i32: 2292 return C_O1_I2(r, r, ri); 2293 2294 case INDEX_op_brcond_i32: 2295 return C_O0_I2(r, rIN); 2296 case INDEX_op_deposit_i32: 2297 return C_O1_I2(r, 0, rZ); 2298 case INDEX_op_extract2_i32: 2299 return C_O1_I2(r, rZ, rZ); 2300 case INDEX_op_movcond_i32: 2301 return C_O1_I4(r, r, rIN, rIK, 0); 2302 case INDEX_op_add2_i32: 2303 return C_O2_I4(r, r, r, r, rIN, rIK); 2304 case INDEX_op_sub2_i32: 2305 return C_O2_I4(r, r, rI, rI, rIN, rIK); 2306 case INDEX_op_brcond2_i32: 2307 return C_O0_I4(r, r, rI, rI); 2308 case INDEX_op_setcond2_i32: 2309 return C_O1_I4(r, r, r, rI, rI); 2310 2311 case INDEX_op_qemu_ld_i32: 2312 return C_O1_I1(r, q); 2313 case INDEX_op_qemu_ld_i64: 2314 return C_O2_I1(e, p, q); 2315 case INDEX_op_qemu_st_i32: 2316 return C_O0_I2(q, q); 2317 case INDEX_op_qemu_st_i64: 2318 return C_O0_I3(Q, p, q); 2319 2320 case INDEX_op_st_vec: 2321 return C_O0_I2(w, r); 2322 case INDEX_op_ld_vec: 2323 case INDEX_op_dupm_vec: 2324 return C_O1_I1(w, r); 2325 case INDEX_op_dup_vec: 2326 return C_O1_I1(w, wr); 2327 case INDEX_op_abs_vec: 2328 case INDEX_op_neg_vec: 2329 case INDEX_op_not_vec: 2330 case INDEX_op_shli_vec: 2331 case INDEX_op_shri_vec: 2332 case INDEX_op_sari_vec: 2333 return C_O1_I1(w, w); 2334 case INDEX_op_dup2_vec: 2335 case INDEX_op_add_vec: 2336 case INDEX_op_mul_vec: 2337 case INDEX_op_smax_vec: 2338 case INDEX_op_smin_vec: 2339 case INDEX_op_ssadd_vec: 2340 case INDEX_op_sssub_vec: 2341 case INDEX_op_sub_vec: 2342 case INDEX_op_umax_vec: 2343 case INDEX_op_umin_vec: 2344 case INDEX_op_usadd_vec: 2345 case INDEX_op_ussub_vec: 2346 case INDEX_op_xor_vec: 2347 case INDEX_op_arm_sshl_vec: 2348 case INDEX_op_arm_ushl_vec: 2349 return C_O1_I2(w, w, w); 2350 case INDEX_op_arm_sli_vec: 2351 return C_O1_I2(w, 0, w); 2352 case INDEX_op_or_vec: 2353 case INDEX_op_andc_vec: 2354 return C_O1_I2(w, w, wO); 2355 case INDEX_op_and_vec: 2356 case INDEX_op_orc_vec: 2357 return C_O1_I2(w, w, wV); 2358 case INDEX_op_cmp_vec: 2359 return C_O1_I2(w, w, wZ); 2360 case INDEX_op_bitsel_vec: 2361 return C_O1_I3(w, w, w, w); 2362 default: 2363 return C_NotImplemented; 2364 } 2365} 2366 2367static void tcg_target_init(TCGContext *s) 2368{ 2369 /* 2370 * Only probe for the platform and capabilities if we haven't already 2371 * determined maximum values at compile time. 2372 */ 2373#if !defined(use_idiv_instructions) || !defined(use_neon_instructions) 2374 { 2375 unsigned long hwcap = qemu_getauxval(AT_HWCAP); 2376#ifndef use_idiv_instructions 2377 use_idiv_instructions = (hwcap & HWCAP_ARM_IDIVA) != 0; 2378#endif 2379#ifndef use_neon_instructions 2380 use_neon_instructions = (hwcap & HWCAP_ARM_NEON) != 0; 2381#endif 2382 } 2383#endif 2384 2385 if (__ARM_ARCH < 7) { 2386 const char *pl = (const char *)qemu_getauxval(AT_PLATFORM); 2387 if (pl != NULL && pl[0] == 'v' && pl[1] >= '4' && pl[1] <= '9') { 2388 arm_arch = pl[1] - '0'; 2389 } 2390 2391 if (arm_arch < 6) { 2392 error_report("TCG: ARMv%d is unsupported; exiting", arm_arch); 2393 exit(EXIT_FAILURE); 2394 } 2395 } 2396 2397 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS; 2398 2399 tcg_target_call_clobber_regs = 0; 2400 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); 2401 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1); 2402 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2); 2403 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3); 2404 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12); 2405 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14); 2406 2407 if (use_neon_instructions) { 2408 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS; 2409 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS; 2410 2411 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q0); 2412 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q1); 2413 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q2); 2414 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q3); 2415 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q8); 2416 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q9); 2417 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q10); 2418 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q11); 2419 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q12); 2420 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q13); 2421 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q14); 2422 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q15); 2423 } 2424 2425 s->reserved_regs = 0; 2426 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); 2427 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP); 2428 tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC); 2429 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP); 2430} 2431 2432static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 2433 TCGReg arg1, intptr_t arg2) 2434{ 2435 switch (type) { 2436 case TCG_TYPE_I32: 2437 tcg_out_ld32u(s, COND_AL, arg, arg1, arg2); 2438 return; 2439 case TCG_TYPE_V64: 2440 /* regs 1; size 8; align 8 */ 2441 tcg_out_vldst(s, INSN_VLD1 | 0x7d0, arg, arg1, arg2); 2442 return; 2443 case TCG_TYPE_V128: 2444 /* 2445 * We have only 8-byte alignment for the stack per the ABI. 2446 * Rather than dynamically re-align the stack, it's easier 2447 * to simply not request alignment beyond that. So: 2448 * regs 2; size 8; align 8 2449 */ 2450 tcg_out_vldst(s, INSN_VLD1 | 0xad0, arg, arg1, arg2); 2451 return; 2452 default: 2453 g_assert_not_reached(); 2454 } 2455} 2456 2457static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 2458 TCGReg arg1, intptr_t arg2) 2459{ 2460 switch (type) { 2461 case TCG_TYPE_I32: 2462 tcg_out_st32(s, COND_AL, arg, arg1, arg2); 2463 return; 2464 case TCG_TYPE_V64: 2465 /* regs 1; size 8; align 8 */ 2466 tcg_out_vldst(s, INSN_VST1 | 0x7d0, arg, arg1, arg2); 2467 return; 2468 case TCG_TYPE_V128: 2469 /* See tcg_out_ld re alignment: regs 2; size 8; align 8 */ 2470 tcg_out_vldst(s, INSN_VST1 | 0xad0, arg, arg1, arg2); 2471 return; 2472 default: 2473 g_assert_not_reached(); 2474 } 2475} 2476 2477static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 2478 TCGReg base, intptr_t ofs) 2479{ 2480 return false; 2481} 2482 2483static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 2484{ 2485 if (ret == arg) { 2486 return true; 2487 } 2488 switch (type) { 2489 case TCG_TYPE_I32: 2490 if (ret < TCG_REG_Q0 && arg < TCG_REG_Q0) { 2491 tcg_out_mov_reg(s, COND_AL, ret, arg); 2492 return true; 2493 } 2494 return false; 2495 2496 case TCG_TYPE_V64: 2497 case TCG_TYPE_V128: 2498 /* "VMOV D,N" is an alias for "VORR D,N,N". */ 2499 tcg_out_vreg3(s, INSN_VORR, type - TCG_TYPE_V64, 0, ret, arg, arg); 2500 return true; 2501 2502 default: 2503 g_assert_not_reached(); 2504 } 2505} 2506 2507static void tcg_out_movi(TCGContext *s, TCGType type, 2508 TCGReg ret, tcg_target_long arg) 2509{ 2510 tcg_debug_assert(type == TCG_TYPE_I32); 2511 tcg_debug_assert(ret < TCG_REG_Q0); 2512 tcg_out_movi32(s, COND_AL, ret, arg); 2513} 2514 2515static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 2516{ 2517 return false; 2518} 2519 2520static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 2521 tcg_target_long imm) 2522{ 2523 int enc, opc = ARITH_ADD; 2524 2525 /* All of the easiest immediates to encode are positive. */ 2526 if (imm < 0) { 2527 imm = -imm; 2528 opc = ARITH_SUB; 2529 } 2530 enc = encode_imm(imm); 2531 if (enc >= 0) { 2532 tcg_out_dat_imm(s, COND_AL, opc, rd, rs, enc); 2533 } else { 2534 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, imm); 2535 tcg_out_dat_reg(s, COND_AL, opc, rd, rs, 2536 TCG_REG_TMP, SHIFT_IMM_LSL(0)); 2537 } 2538} 2539 2540/* Type is always V128, with I64 elements. */ 2541static void tcg_out_dup2_vec(TCGContext *s, TCGReg rd, TCGReg rl, TCGReg rh) 2542{ 2543 /* Move high element into place first. */ 2544 /* VMOV Dd+1, Ds */ 2545 tcg_out_vreg3(s, INSN_VORR | (1 << 12), 0, 0, rd, rh, rh); 2546 /* Move low element into place; tcg_out_mov will check for nop. */ 2547 tcg_out_mov(s, TCG_TYPE_V64, rd, rl); 2548} 2549 2550static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 2551 TCGReg rd, TCGReg rs) 2552{ 2553 int q = type - TCG_TYPE_V64; 2554 2555 if (vece == MO_64) { 2556 if (type == TCG_TYPE_V128) { 2557 tcg_out_dup2_vec(s, rd, rs, rs); 2558 } else { 2559 tcg_out_mov(s, TCG_TYPE_V64, rd, rs); 2560 } 2561 } else if (rs < TCG_REG_Q0) { 2562 int b = (vece == MO_8); 2563 int e = (vece == MO_16); 2564 tcg_out32(s, INSN_VDUP_G | (b << 22) | (q << 21) | (e << 5) | 2565 encode_vn(rd) | (rs << 12)); 2566 } else { 2567 int imm4 = 1 << vece; 2568 tcg_out32(s, INSN_VDUP_S | (imm4 << 16) | (q << 6) | 2569 encode_vd(rd) | encode_vm(rs)); 2570 } 2571 return true; 2572} 2573 2574static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 2575 TCGReg rd, TCGReg base, intptr_t offset) 2576{ 2577 if (vece == MO_64) { 2578 tcg_out_ld(s, TCG_TYPE_V64, rd, base, offset); 2579 if (type == TCG_TYPE_V128) { 2580 tcg_out_dup2_vec(s, rd, rd, rd); 2581 } 2582 } else { 2583 int q = type - TCG_TYPE_V64; 2584 tcg_out_vldst(s, INSN_VLD1R | (vece << 6) | (q << 5), 2585 rd, base, offset); 2586 } 2587 return true; 2588} 2589 2590static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 2591 TCGReg rd, int64_t v64) 2592{ 2593 int q = type - TCG_TYPE_V64; 2594 int cmode, imm8, i; 2595 2596 /* Test all bytes equal first. */ 2597 if (vece == MO_8) { 2598 tcg_out_vmovi(s, rd, q, 0, 0xe, v64); 2599 return; 2600 } 2601 2602 /* 2603 * Test all bytes 0x00 or 0xff second. This can match cases that 2604 * might otherwise take 2 or 3 insns for MO_16 or MO_32 below. 2605 */ 2606 for (i = imm8 = 0; i < 8; i++) { 2607 uint8_t byte = v64 >> (i * 8); 2608 if (byte == 0xff) { 2609 imm8 |= 1 << i; 2610 } else if (byte != 0) { 2611 goto fail_bytes; 2612 } 2613 } 2614 tcg_out_vmovi(s, rd, q, 1, 0xe, imm8); 2615 return; 2616 fail_bytes: 2617 2618 /* 2619 * Tests for various replications. For each element width, if we 2620 * cannot find an expansion there's no point checking a larger 2621 * width because we already know by replication it cannot match. 2622 */ 2623 if (vece == MO_16) { 2624 uint16_t v16 = v64; 2625 2626 if (is_shimm16(v16, &cmode, &imm8)) { 2627 tcg_out_vmovi(s, rd, q, 0, cmode, imm8); 2628 return; 2629 } 2630 if (is_shimm16(~v16, &cmode, &imm8)) { 2631 tcg_out_vmovi(s, rd, q, 1, cmode, imm8); 2632 return; 2633 } 2634 2635 /* 2636 * Otherwise, all remaining constants can be loaded in two insns: 2637 * rd = v16 & 0xff, rd |= v16 & 0xff00. 2638 */ 2639 tcg_out_vmovi(s, rd, q, 0, 0x8, v16 & 0xff); 2640 tcg_out_vmovi(s, rd, q, 0, 0xb, v16 >> 8); /* VORRI */ 2641 return; 2642 } 2643 2644 if (vece == MO_32) { 2645 uint32_t v32 = v64; 2646 2647 if (is_shimm32(v32, &cmode, &imm8) || 2648 is_soimm32(v32, &cmode, &imm8)) { 2649 tcg_out_vmovi(s, rd, q, 0, cmode, imm8); 2650 return; 2651 } 2652 if (is_shimm32(~v32, &cmode, &imm8) || 2653 is_soimm32(~v32, &cmode, &imm8)) { 2654 tcg_out_vmovi(s, rd, q, 1, cmode, imm8); 2655 return; 2656 } 2657 2658 /* 2659 * Restrict the set of constants to those we can load with 2660 * two instructions. Others we load from the pool. 2661 */ 2662 i = is_shimm32_pair(v32, &cmode, &imm8); 2663 if (i) { 2664 tcg_out_vmovi(s, rd, q, 0, cmode, imm8); 2665 tcg_out_vmovi(s, rd, q, 0, i | 1, extract32(v32, i * 4, 8)); 2666 return; 2667 } 2668 i = is_shimm32_pair(~v32, &cmode, &imm8); 2669 if (i) { 2670 tcg_out_vmovi(s, rd, q, 1, cmode, imm8); 2671 tcg_out_vmovi(s, rd, q, 1, i | 1, extract32(~v32, i * 4, 8)); 2672 return; 2673 } 2674 } 2675 2676 /* 2677 * As a last resort, load from the constant pool. 2678 */ 2679 if (!q || vece == MO_64) { 2680 new_pool_l2(s, R_ARM_PC11, s->code_ptr, 0, v64, v64 >> 32); 2681 /* VLDR Dd, [pc + offset] */ 2682 tcg_out32(s, INSN_VLDR_D | encode_vd(rd) | (0xf << 16)); 2683 if (q) { 2684 tcg_out_dup2_vec(s, rd, rd, rd); 2685 } 2686 } else { 2687 new_pool_label(s, (uint32_t)v64, R_ARM_PC8, s->code_ptr, 0); 2688 /* add tmp, pc, offset */ 2689 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_TMP, TCG_REG_PC, 0); 2690 tcg_out_dupm_vec(s, type, MO_32, rd, TCG_REG_TMP, 0); 2691 } 2692} 2693 2694static const ARMInsn vec_cmp_insn[16] = { 2695 [TCG_COND_EQ] = INSN_VCEQ, 2696 [TCG_COND_GT] = INSN_VCGT, 2697 [TCG_COND_GE] = INSN_VCGE, 2698 [TCG_COND_GTU] = INSN_VCGT_U, 2699 [TCG_COND_GEU] = INSN_VCGE_U, 2700}; 2701 2702static const ARMInsn vec_cmp0_insn[16] = { 2703 [TCG_COND_EQ] = INSN_VCEQ0, 2704 [TCG_COND_GT] = INSN_VCGT0, 2705 [TCG_COND_GE] = INSN_VCGE0, 2706 [TCG_COND_LT] = INSN_VCLT0, 2707 [TCG_COND_LE] = INSN_VCLE0, 2708}; 2709 2710static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 2711 unsigned vecl, unsigned vece, 2712 const TCGArg args[TCG_MAX_OP_ARGS], 2713 const int const_args[TCG_MAX_OP_ARGS]) 2714{ 2715 TCGType type = vecl + TCG_TYPE_V64; 2716 unsigned q = vecl; 2717 TCGArg a0, a1, a2, a3; 2718 int cmode, imm8; 2719 2720 a0 = args[0]; 2721 a1 = args[1]; 2722 a2 = args[2]; 2723 2724 switch (opc) { 2725 case INDEX_op_ld_vec: 2726 tcg_out_ld(s, type, a0, a1, a2); 2727 return; 2728 case INDEX_op_st_vec: 2729 tcg_out_st(s, type, a0, a1, a2); 2730 return; 2731 case INDEX_op_dupm_vec: 2732 tcg_out_dupm_vec(s, type, vece, a0, a1, a2); 2733 return; 2734 case INDEX_op_dup2_vec: 2735 tcg_out_dup2_vec(s, a0, a1, a2); 2736 return; 2737 case INDEX_op_abs_vec: 2738 tcg_out_vreg2(s, INSN_VABS, q, vece, a0, a1); 2739 return; 2740 case INDEX_op_neg_vec: 2741 tcg_out_vreg2(s, INSN_VNEG, q, vece, a0, a1); 2742 return; 2743 case INDEX_op_not_vec: 2744 tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a1); 2745 return; 2746 case INDEX_op_add_vec: 2747 tcg_out_vreg3(s, INSN_VADD, q, vece, a0, a1, a2); 2748 return; 2749 case INDEX_op_mul_vec: 2750 tcg_out_vreg3(s, INSN_VMUL, q, vece, a0, a1, a2); 2751 return; 2752 case INDEX_op_smax_vec: 2753 tcg_out_vreg3(s, INSN_VMAX, q, vece, a0, a1, a2); 2754 return; 2755 case INDEX_op_smin_vec: 2756 tcg_out_vreg3(s, INSN_VMIN, q, vece, a0, a1, a2); 2757 return; 2758 case INDEX_op_sub_vec: 2759 tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2); 2760 return; 2761 case INDEX_op_ssadd_vec: 2762 tcg_out_vreg3(s, INSN_VQADD, q, vece, a0, a1, a2); 2763 return; 2764 case INDEX_op_sssub_vec: 2765 tcg_out_vreg3(s, INSN_VQSUB, q, vece, a0, a1, a2); 2766 return; 2767 case INDEX_op_umax_vec: 2768 tcg_out_vreg3(s, INSN_VMAX_U, q, vece, a0, a1, a2); 2769 return; 2770 case INDEX_op_umin_vec: 2771 tcg_out_vreg3(s, INSN_VMIN_U, q, vece, a0, a1, a2); 2772 return; 2773 case INDEX_op_usadd_vec: 2774 tcg_out_vreg3(s, INSN_VQADD_U, q, vece, a0, a1, a2); 2775 return; 2776 case INDEX_op_ussub_vec: 2777 tcg_out_vreg3(s, INSN_VQSUB_U, q, vece, a0, a1, a2); 2778 return; 2779 case INDEX_op_xor_vec: 2780 tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2); 2781 return; 2782 case INDEX_op_arm_sshl_vec: 2783 /* 2784 * Note that Vm is the data and Vn is the shift count, 2785 * therefore the arguments appear reversed. 2786 */ 2787 tcg_out_vreg3(s, INSN_VSHL_S, q, vece, a0, a2, a1); 2788 return; 2789 case INDEX_op_arm_ushl_vec: 2790 /* See above. */ 2791 tcg_out_vreg3(s, INSN_VSHL_U, q, vece, a0, a2, a1); 2792 return; 2793 case INDEX_op_shli_vec: 2794 tcg_out_vshifti(s, INSN_VSHLI, q, a0, a1, a2 + (8 << vece)); 2795 return; 2796 case INDEX_op_shri_vec: 2797 tcg_out_vshifti(s, INSN_VSHRI, q, a0, a1, (16 << vece) - a2); 2798 return; 2799 case INDEX_op_sari_vec: 2800 tcg_out_vshifti(s, INSN_VSARI, q, a0, a1, (16 << vece) - a2); 2801 return; 2802 case INDEX_op_arm_sli_vec: 2803 tcg_out_vshifti(s, INSN_VSLI, q, a0, a2, args[3] + (8 << vece)); 2804 return; 2805 2806 case INDEX_op_andc_vec: 2807 if (!const_args[2]) { 2808 tcg_out_vreg3(s, INSN_VBIC, q, 0, a0, a1, a2); 2809 return; 2810 } 2811 a2 = ~a2; 2812 /* fall through */ 2813 case INDEX_op_and_vec: 2814 if (const_args[2]) { 2815 is_shimm1632(~a2, &cmode, &imm8); 2816 if (a0 == a1) { 2817 tcg_out_vmovi(s, a0, q, 1, cmode | 1, imm8); /* VBICI */ 2818 return; 2819 } 2820 tcg_out_vmovi(s, a0, q, 1, cmode, imm8); /* VMVNI */ 2821 a2 = a0; 2822 } 2823 tcg_out_vreg3(s, INSN_VAND, q, 0, a0, a1, a2); 2824 return; 2825 2826 case INDEX_op_orc_vec: 2827 if (!const_args[2]) { 2828 tcg_out_vreg3(s, INSN_VORN, q, 0, a0, a1, a2); 2829 return; 2830 } 2831 a2 = ~a2; 2832 /* fall through */ 2833 case INDEX_op_or_vec: 2834 if (const_args[2]) { 2835 is_shimm1632(a2, &cmode, &imm8); 2836 if (a0 == a1) { 2837 tcg_out_vmovi(s, a0, q, 0, cmode | 1, imm8); /* VORRI */ 2838 return; 2839 } 2840 tcg_out_vmovi(s, a0, q, 0, cmode, imm8); /* VMOVI */ 2841 a2 = a0; 2842 } 2843 tcg_out_vreg3(s, INSN_VORR, q, 0, a0, a1, a2); 2844 return; 2845 2846 case INDEX_op_cmp_vec: 2847 { 2848 TCGCond cond = args[3]; 2849 ARMInsn insn; 2850 2851 switch (cond) { 2852 case TCG_COND_NE: 2853 if (const_args[2]) { 2854 tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a1); 2855 } else { 2856 tcg_out_vreg3(s, INSN_VCEQ, q, vece, a0, a1, a2); 2857 tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0); 2858 } 2859 break; 2860 2861 case TCG_COND_TSTNE: 2862 case TCG_COND_TSTEQ: 2863 if (const_args[2]) { 2864 /* (x & 0) == 0 */ 2865 tcg_out_dupi_vec(s, type, MO_8, a0, 2866 -(cond == TCG_COND_TSTEQ)); 2867 break; 2868 } 2869 tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a2); 2870 if (cond == TCG_COND_TSTEQ) { 2871 tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0); 2872 } 2873 break; 2874 2875 default: 2876 if (const_args[2]) { 2877 insn = vec_cmp0_insn[cond]; 2878 if (insn) { 2879 tcg_out_vreg2(s, insn, q, vece, a0, a1); 2880 return; 2881 } 2882 tcg_out_dupi_vec(s, type, MO_8, TCG_VEC_TMP, 0); 2883 a2 = TCG_VEC_TMP; 2884 } 2885 insn = vec_cmp_insn[cond]; 2886 if (insn == 0) { 2887 TCGArg t; 2888 t = a1, a1 = a2, a2 = t; 2889 cond = tcg_swap_cond(cond); 2890 insn = vec_cmp_insn[cond]; 2891 tcg_debug_assert(insn != 0); 2892 } 2893 tcg_out_vreg3(s, insn, q, vece, a0, a1, a2); 2894 break; 2895 } 2896 } 2897 return; 2898 2899 case INDEX_op_bitsel_vec: 2900 a3 = args[3]; 2901 if (a0 == a3) { 2902 tcg_out_vreg3(s, INSN_VBIT, q, 0, a0, a2, a1); 2903 } else if (a0 == a2) { 2904 tcg_out_vreg3(s, INSN_VBIF, q, 0, a0, a3, a1); 2905 } else { 2906 tcg_out_mov(s, type, a0, a1); 2907 tcg_out_vreg3(s, INSN_VBSL, q, 0, a0, a2, a3); 2908 } 2909 return; 2910 2911 case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ 2912 case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ 2913 default: 2914 g_assert_not_reached(); 2915 } 2916} 2917 2918int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 2919{ 2920 switch (opc) { 2921 case INDEX_op_add_vec: 2922 case INDEX_op_sub_vec: 2923 case INDEX_op_and_vec: 2924 case INDEX_op_andc_vec: 2925 case INDEX_op_or_vec: 2926 case INDEX_op_orc_vec: 2927 case INDEX_op_xor_vec: 2928 case INDEX_op_not_vec: 2929 case INDEX_op_shli_vec: 2930 case INDEX_op_shri_vec: 2931 case INDEX_op_sari_vec: 2932 case INDEX_op_ssadd_vec: 2933 case INDEX_op_sssub_vec: 2934 case INDEX_op_usadd_vec: 2935 case INDEX_op_ussub_vec: 2936 case INDEX_op_bitsel_vec: 2937 return 1; 2938 case INDEX_op_abs_vec: 2939 case INDEX_op_cmp_vec: 2940 case INDEX_op_mul_vec: 2941 case INDEX_op_neg_vec: 2942 case INDEX_op_smax_vec: 2943 case INDEX_op_smin_vec: 2944 case INDEX_op_umax_vec: 2945 case INDEX_op_umin_vec: 2946 return vece < MO_64; 2947 case INDEX_op_shlv_vec: 2948 case INDEX_op_shrv_vec: 2949 case INDEX_op_sarv_vec: 2950 case INDEX_op_rotli_vec: 2951 case INDEX_op_rotlv_vec: 2952 case INDEX_op_rotrv_vec: 2953 return -1; 2954 default: 2955 return 0; 2956 } 2957} 2958 2959void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 2960 TCGArg a0, ...) 2961{ 2962 va_list va; 2963 TCGv_vec v0, v1, v2, t1, t2, c1; 2964 TCGArg a2; 2965 2966 va_start(va, a0); 2967 v0 = temp_tcgv_vec(arg_temp(a0)); 2968 v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 2969 a2 = va_arg(va, TCGArg); 2970 va_end(va); 2971 2972 switch (opc) { 2973 case INDEX_op_shlv_vec: 2974 /* 2975 * Merely propagate shlv_vec to arm_ushl_vec. 2976 * In this way we don't set TCG_TARGET_HAS_shv_vec 2977 * because everything is done via expansion. 2978 */ 2979 v2 = temp_tcgv_vec(arg_temp(a2)); 2980 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0), 2981 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 2982 break; 2983 2984 case INDEX_op_shrv_vec: 2985 case INDEX_op_sarv_vec: 2986 /* Right shifts are negative left shifts for NEON. */ 2987 v2 = temp_tcgv_vec(arg_temp(a2)); 2988 t1 = tcg_temp_new_vec(type); 2989 tcg_gen_neg_vec(vece, t1, v2); 2990 if (opc == INDEX_op_shrv_vec) { 2991 opc = INDEX_op_arm_ushl_vec; 2992 } else { 2993 opc = INDEX_op_arm_sshl_vec; 2994 } 2995 vec_gen_3(opc, type, vece, tcgv_vec_arg(v0), 2996 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 2997 tcg_temp_free_vec(t1); 2998 break; 2999 3000 case INDEX_op_rotli_vec: 3001 t1 = tcg_temp_new_vec(type); 3002 tcg_gen_shri_vec(vece, t1, v1, -a2 & ((8 << vece) - 1)); 3003 vec_gen_4(INDEX_op_arm_sli_vec, type, vece, 3004 tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(v1), a2); 3005 tcg_temp_free_vec(t1); 3006 break; 3007 3008 case INDEX_op_rotlv_vec: 3009 v2 = temp_tcgv_vec(arg_temp(a2)); 3010 t1 = tcg_temp_new_vec(type); 3011 c1 = tcg_constant_vec(type, vece, 8 << vece); 3012 tcg_gen_sub_vec(vece, t1, v2, c1); 3013 /* Right shifts are negative left shifts for NEON. */ 3014 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1), 3015 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 3016 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0), 3017 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 3018 tcg_gen_or_vec(vece, v0, v0, t1); 3019 tcg_temp_free_vec(t1); 3020 break; 3021 3022 case INDEX_op_rotrv_vec: 3023 v2 = temp_tcgv_vec(arg_temp(a2)); 3024 t1 = tcg_temp_new_vec(type); 3025 t2 = tcg_temp_new_vec(type); 3026 c1 = tcg_constant_vec(type, vece, 8 << vece); 3027 tcg_gen_neg_vec(vece, t1, v2); 3028 tcg_gen_sub_vec(vece, t2, c1, v2); 3029 /* Right shifts are negative left shifts for NEON. */ 3030 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1), 3031 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 3032 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t2), 3033 tcgv_vec_arg(v1), tcgv_vec_arg(t2)); 3034 tcg_gen_or_vec(vece, v0, t1, t2); 3035 tcg_temp_free_vec(t1); 3036 tcg_temp_free_vec(t2); 3037 break; 3038 3039 default: 3040 g_assert_not_reached(); 3041 } 3042} 3043 3044static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 3045{ 3046 int i; 3047 for (i = 0; i < count; ++i) { 3048 p[i] = INSN_NOP; 3049 } 3050} 3051 3052/* Compute frame size via macros, to share between tcg_target_qemu_prologue 3053 and tcg_register_jit. */ 3054 3055#define PUSH_SIZE ((11 - 4 + 1 + 1) * sizeof(tcg_target_long)) 3056 3057#define FRAME_SIZE \ 3058 ((PUSH_SIZE \ 3059 + TCG_STATIC_CALL_ARGS_SIZE \ 3060 + CPU_TEMP_BUF_NLONGS * sizeof(long) \ 3061 + TCG_TARGET_STACK_ALIGN - 1) \ 3062 & -TCG_TARGET_STACK_ALIGN) 3063 3064#define STACK_ADDEND (FRAME_SIZE - PUSH_SIZE) 3065 3066static void tcg_target_qemu_prologue(TCGContext *s) 3067{ 3068 /* Calling convention requires us to save r4-r11 and lr. */ 3069 /* stmdb sp!, { r4 - r11, lr } */ 3070 tcg_out_ldstm(s, COND_AL, INSN_STMDB, TCG_REG_CALL_STACK, 3071 (1 << TCG_REG_R4) | (1 << TCG_REG_R5) | (1 << TCG_REG_R6) | 3072 (1 << TCG_REG_R7) | (1 << TCG_REG_R8) | (1 << TCG_REG_R9) | 3073 (1 << TCG_REG_R10) | (1 << TCG_REG_R11) | (1 << TCG_REG_R14)); 3074 3075 /* Reserve callee argument and tcg temp space. */ 3076 tcg_out_dat_rI(s, COND_AL, ARITH_SUB, TCG_REG_CALL_STACK, 3077 TCG_REG_CALL_STACK, STACK_ADDEND, 1); 3078 tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE, 3079 CPU_TEMP_BUF_NLONGS * sizeof(long)); 3080 3081 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 3082 3083 if (!tcg_use_softmmu && guest_base) { 3084 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_GUEST_BASE, guest_base); 3085 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GUEST_BASE); 3086 } 3087 3088 tcg_out_b_reg(s, COND_AL, tcg_target_call_iarg_regs[1]); 3089 3090 /* 3091 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 3092 * and fall through to the rest of the epilogue. 3093 */ 3094 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 3095 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, 0); 3096 tcg_out_epilogue(s); 3097} 3098 3099static void tcg_out_epilogue(TCGContext *s) 3100{ 3101 /* Release local stack frame. */ 3102 tcg_out_dat_rI(s, COND_AL, ARITH_ADD, TCG_REG_CALL_STACK, 3103 TCG_REG_CALL_STACK, STACK_ADDEND, 1); 3104 3105 /* ldmia sp!, { r4 - r11, pc } */ 3106 tcg_out_ldstm(s, COND_AL, INSN_LDMIA, TCG_REG_CALL_STACK, 3107 (1 << TCG_REG_R4) | (1 << TCG_REG_R5) | (1 << TCG_REG_R6) | 3108 (1 << TCG_REG_R7) | (1 << TCG_REG_R8) | (1 << TCG_REG_R9) | 3109 (1 << TCG_REG_R10) | (1 << TCG_REG_R11) | (1 << TCG_REG_PC)); 3110} 3111 3112static void tcg_out_tb_start(TCGContext *s) 3113{ 3114 /* nothing to do */ 3115} 3116 3117typedef struct { 3118 DebugFrameHeader h; 3119 uint8_t fde_def_cfa[4]; 3120 uint8_t fde_reg_ofs[18]; 3121} DebugFrame; 3122 3123#define ELF_HOST_MACHINE EM_ARM 3124 3125/* We're expecting a 2 byte uleb128 encoded value. */ 3126QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); 3127 3128static const DebugFrame debug_frame = { 3129 .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ 3130 .h.cie.id = -1, 3131 .h.cie.version = 1, 3132 .h.cie.code_align = 1, 3133 .h.cie.data_align = 0x7c, /* sleb128 -4 */ 3134 .h.cie.return_column = 14, 3135 3136 /* Total FDE size does not include the "len" member. */ 3137 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 3138 3139 .fde_def_cfa = { 3140 12, 13, /* DW_CFA_def_cfa sp, ... */ 3141 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 3142 (FRAME_SIZE >> 7) 3143 }, 3144 .fde_reg_ofs = { 3145 /* The following must match the stmdb in the prologue. */ 3146 0x8e, 1, /* DW_CFA_offset, lr, -4 */ 3147 0x8b, 2, /* DW_CFA_offset, r11, -8 */ 3148 0x8a, 3, /* DW_CFA_offset, r10, -12 */ 3149 0x89, 4, /* DW_CFA_offset, r9, -16 */ 3150 0x88, 5, /* DW_CFA_offset, r8, -20 */ 3151 0x87, 6, /* DW_CFA_offset, r7, -24 */ 3152 0x86, 7, /* DW_CFA_offset, r6, -28 */ 3153 0x85, 8, /* DW_CFA_offset, r5, -32 */ 3154 0x84, 9, /* DW_CFA_offset, r4, -36 */ 3155 } 3156}; 3157 3158void tcg_register_jit(const void *buf, size_t buf_size) 3159{ 3160 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 3161} 3162