1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Andrzej Zaborowski 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25#include "elf.h" 26 27int arm_arch = __ARM_ARCH; 28 29#ifndef use_idiv_instructions 30bool use_idiv_instructions; 31#endif 32#ifndef use_neon_instructions 33bool use_neon_instructions; 34#endif 35 36/* Used for function call generation. */ 37#define TCG_TARGET_STACK_ALIGN 8 38#define TCG_TARGET_CALL_STACK_OFFSET 0 39#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL 40#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN 41#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN 42#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF 43 44#ifdef CONFIG_DEBUG_TCG 45static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 46 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", 47 "%r8", "%r9", "%r10", "%r11", "%r12", "%sp", "%r14", "%pc", 48 "%q0", "%q1", "%q2", "%q3", "%q4", "%q5", "%q6", "%q7", 49 "%q8", "%q9", "%q10", "%q11", "%q12", "%q13", "%q14", "%q15", 50}; 51#endif 52 53static const int tcg_target_reg_alloc_order[] = { 54 TCG_REG_R4, 55 TCG_REG_R5, 56 TCG_REG_R6, 57 TCG_REG_R7, 58 TCG_REG_R8, 59 TCG_REG_R9, 60 TCG_REG_R10, 61 TCG_REG_R11, 62 TCG_REG_R13, 63 TCG_REG_R0, 64 TCG_REG_R1, 65 TCG_REG_R2, 66 TCG_REG_R3, 67 TCG_REG_R12, 68 TCG_REG_R14, 69 70 TCG_REG_Q0, 71 TCG_REG_Q1, 72 TCG_REG_Q2, 73 TCG_REG_Q3, 74 /* Q4 - Q7 are call-saved, and skipped. */ 75 TCG_REG_Q8, 76 TCG_REG_Q9, 77 TCG_REG_Q10, 78 TCG_REG_Q11, 79 TCG_REG_Q12, 80 TCG_REG_Q13, 81 TCG_REG_Q14, 82 TCG_REG_Q15, 83}; 84 85static const int tcg_target_call_iarg_regs[4] = { 86 TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3 87}; 88 89static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 90{ 91 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 92 tcg_debug_assert(slot >= 0 && slot <= 3); 93 return TCG_REG_R0 + slot; 94} 95 96#define TCG_REG_TMP TCG_REG_R12 97#define TCG_VEC_TMP TCG_REG_Q15 98#define TCG_REG_GUEST_BASE TCG_REG_R11 99 100typedef enum { 101 COND_EQ = 0x0, 102 COND_NE = 0x1, 103 COND_CS = 0x2, /* Unsigned greater or equal */ 104 COND_CC = 0x3, /* Unsigned less than */ 105 COND_MI = 0x4, /* Negative */ 106 COND_PL = 0x5, /* Zero or greater */ 107 COND_VS = 0x6, /* Overflow */ 108 COND_VC = 0x7, /* No overflow */ 109 COND_HI = 0x8, /* Unsigned greater than */ 110 COND_LS = 0x9, /* Unsigned less or equal */ 111 COND_GE = 0xa, 112 COND_LT = 0xb, 113 COND_GT = 0xc, 114 COND_LE = 0xd, 115 COND_AL = 0xe, 116} ARMCond; 117 118#define TO_CPSR (1 << 20) 119 120#define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00) 121#define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20) 122#define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40) 123#define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60) 124#define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10) 125#define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30) 126#define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50) 127#define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70) 128 129typedef enum { 130 ARITH_AND = 0x0 << 21, 131 ARITH_EOR = 0x1 << 21, 132 ARITH_SUB = 0x2 << 21, 133 ARITH_RSB = 0x3 << 21, 134 ARITH_ADD = 0x4 << 21, 135 ARITH_ADC = 0x5 << 21, 136 ARITH_SBC = 0x6 << 21, 137 ARITH_RSC = 0x7 << 21, 138 ARITH_TST = 0x8 << 21 | TO_CPSR, 139 ARITH_CMP = 0xa << 21 | TO_CPSR, 140 ARITH_CMN = 0xb << 21 | TO_CPSR, 141 ARITH_ORR = 0xc << 21, 142 ARITH_MOV = 0xd << 21, 143 ARITH_BIC = 0xe << 21, 144 ARITH_MVN = 0xf << 21, 145 146 INSN_B = 0x0a000000, 147 148 INSN_CLZ = 0x016f0f10, 149 INSN_RBIT = 0x06ff0f30, 150 151 INSN_LDMIA = 0x08b00000, 152 INSN_STMDB = 0x09200000, 153 154 INSN_LDR_IMM = 0x04100000, 155 INSN_LDR_REG = 0x06100000, 156 INSN_STR_IMM = 0x04000000, 157 INSN_STR_REG = 0x06000000, 158 159 INSN_LDRH_IMM = 0x005000b0, 160 INSN_LDRH_REG = 0x001000b0, 161 INSN_LDRSH_IMM = 0x005000f0, 162 INSN_LDRSH_REG = 0x001000f0, 163 INSN_STRH_IMM = 0x004000b0, 164 INSN_STRH_REG = 0x000000b0, 165 166 INSN_LDRB_IMM = 0x04500000, 167 INSN_LDRB_REG = 0x06500000, 168 INSN_LDRSB_IMM = 0x005000d0, 169 INSN_LDRSB_REG = 0x001000d0, 170 INSN_STRB_IMM = 0x04400000, 171 INSN_STRB_REG = 0x06400000, 172 173 INSN_LDRD_IMM = 0x004000d0, 174 INSN_LDRD_REG = 0x000000d0, 175 INSN_STRD_IMM = 0x004000f0, 176 INSN_STRD_REG = 0x000000f0, 177 178 INSN_DMB_ISH = 0xf57ff05b, 179 INSN_DMB_MCR = 0xee070fba, 180 181 /* Architected nop introduced in v6k. */ 182 /* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this 183 also Just So Happened to do nothing on pre-v6k so that we 184 don't need to conditionalize it? */ 185 INSN_NOP_v6k = 0xe320f000, 186 /* Otherwise the assembler uses mov r0,r0 */ 187 INSN_NOP_v4 = (COND_AL << 28) | ARITH_MOV, 188 189 INSN_VADD = 0xf2000800, 190 INSN_VAND = 0xf2000110, 191 INSN_VBIC = 0xf2100110, 192 INSN_VEOR = 0xf3000110, 193 INSN_VORN = 0xf2300110, 194 INSN_VORR = 0xf2200110, 195 INSN_VSUB = 0xf3000800, 196 INSN_VMUL = 0xf2000910, 197 INSN_VQADD = 0xf2000010, 198 INSN_VQADD_U = 0xf3000010, 199 INSN_VQSUB = 0xf2000210, 200 INSN_VQSUB_U = 0xf3000210, 201 INSN_VMAX = 0xf2000600, 202 INSN_VMAX_U = 0xf3000600, 203 INSN_VMIN = 0xf2000610, 204 INSN_VMIN_U = 0xf3000610, 205 206 INSN_VABS = 0xf3b10300, 207 INSN_VMVN = 0xf3b00580, 208 INSN_VNEG = 0xf3b10380, 209 210 INSN_VCEQ0 = 0xf3b10100, 211 INSN_VCGT0 = 0xf3b10000, 212 INSN_VCGE0 = 0xf3b10080, 213 INSN_VCLE0 = 0xf3b10180, 214 INSN_VCLT0 = 0xf3b10200, 215 216 INSN_VCEQ = 0xf3000810, 217 INSN_VCGE = 0xf2000310, 218 INSN_VCGT = 0xf2000300, 219 INSN_VCGE_U = 0xf3000310, 220 INSN_VCGT_U = 0xf3000300, 221 222 INSN_VSHLI = 0xf2800510, /* VSHL (immediate) */ 223 INSN_VSARI = 0xf2800010, /* VSHR.S */ 224 INSN_VSHRI = 0xf3800010, /* VSHR.U */ 225 INSN_VSLI = 0xf3800510, 226 INSN_VSHL_S = 0xf2000400, /* VSHL.S (register) */ 227 INSN_VSHL_U = 0xf3000400, /* VSHL.U (register) */ 228 229 INSN_VBSL = 0xf3100110, 230 INSN_VBIT = 0xf3200110, 231 INSN_VBIF = 0xf3300110, 232 233 INSN_VTST = 0xf2000810, 234 235 INSN_VDUP_G = 0xee800b10, /* VDUP (ARM core register) */ 236 INSN_VDUP_S = 0xf3b00c00, /* VDUP (scalar) */ 237 INSN_VLDR_D = 0xed100b00, /* VLDR.64 */ 238 INSN_VLD1 = 0xf4200000, /* VLD1 (multiple single elements) */ 239 INSN_VLD1R = 0xf4a00c00, /* VLD1 (single element to all lanes) */ 240 INSN_VST1 = 0xf4000000, /* VST1 (multiple single elements) */ 241 INSN_VMOVI = 0xf2800010, /* VMOV (immediate) */ 242} ARMInsn; 243 244#define INSN_NOP (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4) 245 246static const uint8_t tcg_cond_to_arm_cond[] = { 247 [TCG_COND_EQ] = COND_EQ, 248 [TCG_COND_NE] = COND_NE, 249 [TCG_COND_LT] = COND_LT, 250 [TCG_COND_GE] = COND_GE, 251 [TCG_COND_LE] = COND_LE, 252 [TCG_COND_GT] = COND_GT, 253 /* unsigned */ 254 [TCG_COND_LTU] = COND_CC, 255 [TCG_COND_GEU] = COND_CS, 256 [TCG_COND_LEU] = COND_LS, 257 [TCG_COND_GTU] = COND_HI, 258}; 259 260static int encode_imm(uint32_t imm); 261 262/* TCG private relocation type: add with pc+imm8 */ 263#define R_ARM_PC8 11 264 265/* TCG private relocation type: vldr with imm8 << 2 */ 266#define R_ARM_PC11 12 267 268static bool reloc_pc24(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 269{ 270 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 271 ptrdiff_t offset = (tcg_ptr_byte_diff(target, src_rx) - 8) >> 2; 272 273 if (offset == sextract32(offset, 0, 24)) { 274 *src_rw = deposit32(*src_rw, 0, 24, offset); 275 return true; 276 } 277 return false; 278} 279 280static bool reloc_pc13(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 281{ 282 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 283 ptrdiff_t offset = tcg_ptr_byte_diff(target, src_rx) - 8; 284 285 if (offset >= -0xfff && offset <= 0xfff) { 286 tcg_insn_unit insn = *src_rw; 287 bool u = (offset >= 0); 288 if (!u) { 289 offset = -offset; 290 } 291 insn = deposit32(insn, 23, 1, u); 292 insn = deposit32(insn, 0, 12, offset); 293 *src_rw = insn; 294 return true; 295 } 296 return false; 297} 298 299static bool reloc_pc11(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 300{ 301 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 302 ptrdiff_t offset = (tcg_ptr_byte_diff(target, src_rx) - 8) / 4; 303 304 if (offset >= -0xff && offset <= 0xff) { 305 tcg_insn_unit insn = *src_rw; 306 bool u = (offset >= 0); 307 if (!u) { 308 offset = -offset; 309 } 310 insn = deposit32(insn, 23, 1, u); 311 insn = deposit32(insn, 0, 8, offset); 312 *src_rw = insn; 313 return true; 314 } 315 return false; 316} 317 318static bool reloc_pc8(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 319{ 320 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 321 ptrdiff_t offset = tcg_ptr_byte_diff(target, src_rx) - 8; 322 int imm12 = encode_imm(offset); 323 324 if (imm12 >= 0) { 325 *src_rw = deposit32(*src_rw, 0, 12, imm12); 326 return true; 327 } 328 return false; 329} 330 331static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 332 intptr_t value, intptr_t addend) 333{ 334 tcg_debug_assert(addend == 0); 335 switch (type) { 336 case R_ARM_PC24: 337 return reloc_pc24(code_ptr, (const tcg_insn_unit *)value); 338 case R_ARM_PC13: 339 return reloc_pc13(code_ptr, (const tcg_insn_unit *)value); 340 case R_ARM_PC11: 341 return reloc_pc11(code_ptr, (const tcg_insn_unit *)value); 342 case R_ARM_PC8: 343 return reloc_pc8(code_ptr, (const tcg_insn_unit *)value); 344 default: 345 g_assert_not_reached(); 346 } 347} 348 349#define TCG_CT_CONST_ARM 0x100 350#define TCG_CT_CONST_INV 0x200 351#define TCG_CT_CONST_NEG 0x400 352#define TCG_CT_CONST_ZERO 0x800 353#define TCG_CT_CONST_ORRI 0x1000 354#define TCG_CT_CONST_ANDI 0x2000 355 356#define ALL_GENERAL_REGS 0xffffu 357#define ALL_VECTOR_REGS 0xffff0000u 358 359/* 360 * r0-r3 will be overwritten when reading the tlb entry (system-mode only); 361 * r14 will be overwritten by the BLNE branching to the slow path. 362 */ 363#define ALL_QLDST_REGS \ 364 (ALL_GENERAL_REGS & ~((tcg_use_softmmu ? 0xf : 0) | (1 << TCG_REG_R14))) 365 366/* 367 * ARM immediates for ALU instructions are made of an unsigned 8-bit 368 * right-rotated by an even amount between 0 and 30. 369 * 370 * Return < 0 if @imm cannot be encoded, else the entire imm12 field. 371 */ 372static int encode_imm(uint32_t imm) 373{ 374 uint32_t rot, imm8; 375 376 /* Simple case, no rotation required. */ 377 if ((imm & ~0xff) == 0) { 378 return imm; 379 } 380 381 /* Next, try a simple even shift. */ 382 rot = ctz32(imm) & ~1; 383 imm8 = imm >> rot; 384 rot = 32 - rot; 385 if ((imm8 & ~0xff) == 0) { 386 goto found; 387 } 388 389 /* 390 * Finally, try harder with rotations. 391 * The ctz test above will have taken care of rotates >= 8. 392 */ 393 for (rot = 2; rot < 8; rot += 2) { 394 imm8 = rol32(imm, rot); 395 if ((imm8 & ~0xff) == 0) { 396 goto found; 397 } 398 } 399 /* Fail: imm cannot be encoded. */ 400 return -1; 401 402 found: 403 /* Note that rot is even, and we discard bit 0 by shifting by 7. */ 404 return rot << 7 | imm8; 405} 406 407static int encode_imm_nofail(uint32_t imm) 408{ 409 int ret = encode_imm(imm); 410 tcg_debug_assert(ret >= 0); 411 return ret; 412} 413 414static bool check_fit_imm(uint32_t imm) 415{ 416 return encode_imm(imm) >= 0; 417} 418 419/* Return true if v16 is a valid 16-bit shifted immediate. */ 420static bool is_shimm16(uint16_t v16, int *cmode, int *imm8) 421{ 422 if (v16 == (v16 & 0xff)) { 423 *cmode = 0x8; 424 *imm8 = v16 & 0xff; 425 return true; 426 } else if (v16 == (v16 & 0xff00)) { 427 *cmode = 0xa; 428 *imm8 = v16 >> 8; 429 return true; 430 } 431 return false; 432} 433 434/* Return true if v32 is a valid 32-bit shifted immediate. */ 435static bool is_shimm32(uint32_t v32, int *cmode, int *imm8) 436{ 437 if (v32 == (v32 & 0xff)) { 438 *cmode = 0x0; 439 *imm8 = v32 & 0xff; 440 return true; 441 } else if (v32 == (v32 & 0xff00)) { 442 *cmode = 0x2; 443 *imm8 = (v32 >> 8) & 0xff; 444 return true; 445 } else if (v32 == (v32 & 0xff0000)) { 446 *cmode = 0x4; 447 *imm8 = (v32 >> 16) & 0xff; 448 return true; 449 } else if (v32 == (v32 & 0xff000000)) { 450 *cmode = 0x6; 451 *imm8 = v32 >> 24; 452 return true; 453 } 454 return false; 455} 456 457/* Return true if v32 is a valid 32-bit shifting ones immediate. */ 458static bool is_soimm32(uint32_t v32, int *cmode, int *imm8) 459{ 460 if ((v32 & 0xffff00ff) == 0xff) { 461 *cmode = 0xc; 462 *imm8 = (v32 >> 8) & 0xff; 463 return true; 464 } else if ((v32 & 0xff00ffff) == 0xffff) { 465 *cmode = 0xd; 466 *imm8 = (v32 >> 16) & 0xff; 467 return true; 468 } 469 return false; 470} 471 472/* 473 * Return non-zero if v32 can be formed by MOVI+ORR. 474 * Place the parameters for MOVI in (cmode, imm8). 475 * Return the cmode for ORR; the imm8 can be had via extraction from v32. 476 */ 477static int is_shimm32_pair(uint32_t v32, int *cmode, int *imm8) 478{ 479 int i; 480 481 for (i = 6; i > 0; i -= 2) { 482 /* Mask out one byte we can add with ORR. */ 483 uint32_t tmp = v32 & ~(0xffu << (i * 4)); 484 if (is_shimm32(tmp, cmode, imm8) || 485 is_soimm32(tmp, cmode, imm8)) { 486 break; 487 } 488 } 489 return i; 490} 491 492/* Return true if V is a valid 16-bit or 32-bit shifted immediate. */ 493static bool is_shimm1632(uint32_t v32, int *cmode, int *imm8) 494{ 495 if (v32 == deposit32(v32, 16, 16, v32)) { 496 return is_shimm16(v32, cmode, imm8); 497 } else { 498 return is_shimm32(v32, cmode, imm8); 499 } 500} 501 502/* Test if a constant matches the constraint. 503 * TODO: define constraints for: 504 * 505 * ldr/str offset: between -0xfff and 0xfff 506 * ldrh/strh offset: between -0xff and 0xff 507 * mov operand2: values represented with x << (2 * y), x < 0x100 508 * add, sub, eor...: ditto 509 */ 510static bool tcg_target_const_match(int64_t val, int ct, 511 TCGType type, TCGCond cond, int vece) 512{ 513 if (ct & TCG_CT_CONST) { 514 return 1; 515 } else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val)) { 516 return 1; 517 } else if ((ct & TCG_CT_CONST_INV) && check_fit_imm(~val)) { 518 return 1; 519 } else if ((ct & TCG_CT_CONST_NEG) && check_fit_imm(-val)) { 520 return 1; 521 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 522 return 1; 523 } 524 525 switch (ct & (TCG_CT_CONST_ORRI | TCG_CT_CONST_ANDI)) { 526 case 0: 527 break; 528 case TCG_CT_CONST_ANDI: 529 val = ~val; 530 /* fallthru */ 531 case TCG_CT_CONST_ORRI: 532 if (val == deposit64(val, 32, 32, val)) { 533 int cmode, imm8; 534 return is_shimm1632(val, &cmode, &imm8); 535 } 536 break; 537 default: 538 /* Both bits should not be set for the same insn. */ 539 g_assert_not_reached(); 540 } 541 542 return 0; 543} 544 545static void tcg_out_b_imm(TCGContext *s, ARMCond cond, int32_t offset) 546{ 547 tcg_out32(s, (cond << 28) | INSN_B | 548 (((offset - 8) >> 2) & 0x00ffffff)); 549} 550 551static void tcg_out_bl_imm(TCGContext *s, ARMCond cond, int32_t offset) 552{ 553 tcg_out32(s, (cond << 28) | 0x0b000000 | 554 (((offset - 8) >> 2) & 0x00ffffff)); 555} 556 557static void tcg_out_blx_reg(TCGContext *s, ARMCond cond, TCGReg rn) 558{ 559 tcg_out32(s, (cond << 28) | 0x012fff30 | rn); 560} 561 562static void tcg_out_blx_imm(TCGContext *s, int32_t offset) 563{ 564 tcg_out32(s, 0xfa000000 | ((offset & 2) << 23) | 565 (((offset - 8) >> 2) & 0x00ffffff)); 566} 567 568static void tcg_out_dat_reg(TCGContext *s, ARMCond cond, ARMInsn opc, 569 TCGReg rd, TCGReg rn, TCGReg rm, int shift) 570{ 571 tcg_out32(s, (cond << 28) | (0 << 25) | opc | 572 (rn << 16) | (rd << 12) | shift | rm); 573} 574 575static void tcg_out_mov_reg(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rm) 576{ 577 /* Simple reg-reg move, optimising out the 'do nothing' case */ 578 if (rd != rm) { 579 tcg_out_dat_reg(s, cond, ARITH_MOV, rd, 0, rm, SHIFT_IMM_LSL(0)); 580 } 581} 582 583static void tcg_out_bx_reg(TCGContext *s, ARMCond cond, TCGReg rn) 584{ 585 tcg_out32(s, (cond << 28) | 0x012fff10 | rn); 586} 587 588static void tcg_out_b_reg(TCGContext *s, ARMCond cond, TCGReg rn) 589{ 590 /* 591 * Unless the C portion of QEMU is compiled as thumb, we don't need 592 * true BX semantics; merely a branch to an address held in a register. 593 */ 594 tcg_out_bx_reg(s, cond, rn); 595} 596 597static void tcg_out_dat_imm(TCGContext *s, ARMCond cond, ARMInsn opc, 598 TCGReg rd, TCGReg rn, int im) 599{ 600 tcg_out32(s, (cond << 28) | (1 << 25) | opc | 601 (rn << 16) | (rd << 12) | im); 602} 603 604static void tcg_out_ldstm(TCGContext *s, ARMCond cond, ARMInsn opc, 605 TCGReg rn, uint16_t mask) 606{ 607 tcg_out32(s, (cond << 28) | opc | (rn << 16) | mask); 608} 609 610/* Note that this routine is used for both LDR and LDRH formats, so we do 611 not wish to include an immediate shift at this point. */ 612static void tcg_out_memop_r(TCGContext *s, ARMCond cond, ARMInsn opc, TCGReg rt, 613 TCGReg rn, TCGReg rm, bool u, bool p, bool w) 614{ 615 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) 616 | (w << 21) | (rn << 16) | (rt << 12) | rm); 617} 618 619static void tcg_out_memop_8(TCGContext *s, ARMCond cond, ARMInsn opc, TCGReg rt, 620 TCGReg rn, int imm8, bool p, bool w) 621{ 622 bool u = 1; 623 if (imm8 < 0) { 624 imm8 = -imm8; 625 u = 0; 626 } 627 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | 628 (rn << 16) | (rt << 12) | ((imm8 & 0xf0) << 4) | (imm8 & 0xf)); 629} 630 631static void tcg_out_memop_12(TCGContext *s, ARMCond cond, ARMInsn opc, 632 TCGReg rt, TCGReg rn, int imm12, bool p, bool w) 633{ 634 bool u = 1; 635 if (imm12 < 0) { 636 imm12 = -imm12; 637 u = 0; 638 } 639 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | 640 (rn << 16) | (rt << 12) | imm12); 641} 642 643static void tcg_out_ld32_12(TCGContext *s, ARMCond cond, TCGReg rt, 644 TCGReg rn, int imm12) 645{ 646 tcg_out_memop_12(s, cond, INSN_LDR_IMM, rt, rn, imm12, 1, 0); 647} 648 649static void tcg_out_st32_12(TCGContext *s, ARMCond cond, TCGReg rt, 650 TCGReg rn, int imm12) 651{ 652 tcg_out_memop_12(s, cond, INSN_STR_IMM, rt, rn, imm12, 1, 0); 653} 654 655static void tcg_out_ld32_r(TCGContext *s, ARMCond cond, TCGReg rt, 656 TCGReg rn, TCGReg rm) 657{ 658 tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 0); 659} 660 661static void tcg_out_st32_r(TCGContext *s, ARMCond cond, TCGReg rt, 662 TCGReg rn, TCGReg rm) 663{ 664 tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 0); 665} 666 667static void tcg_out_ldrd_8(TCGContext *s, ARMCond cond, TCGReg rt, 668 TCGReg rn, int imm8) 669{ 670 tcg_out_memop_8(s, cond, INSN_LDRD_IMM, rt, rn, imm8, 1, 0); 671} 672 673static void tcg_out_ldrd_r(TCGContext *s, ARMCond cond, TCGReg rt, 674 TCGReg rn, TCGReg rm) 675{ 676 tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 0); 677} 678 679static void tcg_out_strd_8(TCGContext *s, ARMCond cond, TCGReg rt, 680 TCGReg rn, int imm8) 681{ 682 tcg_out_memop_8(s, cond, INSN_STRD_IMM, rt, rn, imm8, 1, 0); 683} 684 685static void tcg_out_strd_r(TCGContext *s, ARMCond cond, TCGReg rt, 686 TCGReg rn, TCGReg rm) 687{ 688 tcg_out_memop_r(s, cond, INSN_STRD_REG, rt, rn, rm, 1, 1, 0); 689} 690 691/* Register pre-increment with base writeback. */ 692static void tcg_out_ld32_rwb(TCGContext *s, ARMCond cond, TCGReg rt, 693 TCGReg rn, TCGReg rm) 694{ 695 tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 1); 696} 697 698static void tcg_out_st32_rwb(TCGContext *s, ARMCond cond, TCGReg rt, 699 TCGReg rn, TCGReg rm) 700{ 701 tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 1); 702} 703 704static void tcg_out_ld16u_8(TCGContext *s, ARMCond cond, TCGReg rt, 705 TCGReg rn, int imm8) 706{ 707 tcg_out_memop_8(s, cond, INSN_LDRH_IMM, rt, rn, imm8, 1, 0); 708} 709 710static void tcg_out_st16_8(TCGContext *s, ARMCond cond, TCGReg rt, 711 TCGReg rn, int imm8) 712{ 713 tcg_out_memop_8(s, cond, INSN_STRH_IMM, rt, rn, imm8, 1, 0); 714} 715 716static void tcg_out_ld16u_r(TCGContext *s, ARMCond cond, TCGReg rt, 717 TCGReg rn, TCGReg rm) 718{ 719 tcg_out_memop_r(s, cond, INSN_LDRH_REG, rt, rn, rm, 1, 1, 0); 720} 721 722static void tcg_out_st16_r(TCGContext *s, ARMCond cond, TCGReg rt, 723 TCGReg rn, TCGReg rm) 724{ 725 tcg_out_memop_r(s, cond, INSN_STRH_REG, rt, rn, rm, 1, 1, 0); 726} 727 728static void tcg_out_ld16s_8(TCGContext *s, ARMCond cond, TCGReg rt, 729 TCGReg rn, int imm8) 730{ 731 tcg_out_memop_8(s, cond, INSN_LDRSH_IMM, rt, rn, imm8, 1, 0); 732} 733 734static void tcg_out_ld16s_r(TCGContext *s, ARMCond cond, TCGReg rt, 735 TCGReg rn, TCGReg rm) 736{ 737 tcg_out_memop_r(s, cond, INSN_LDRSH_REG, rt, rn, rm, 1, 1, 0); 738} 739 740static void tcg_out_ld8_12(TCGContext *s, ARMCond cond, TCGReg rt, 741 TCGReg rn, int imm12) 742{ 743 tcg_out_memop_12(s, cond, INSN_LDRB_IMM, rt, rn, imm12, 1, 0); 744} 745 746static void tcg_out_st8_12(TCGContext *s, ARMCond cond, TCGReg rt, 747 TCGReg rn, int imm12) 748{ 749 tcg_out_memop_12(s, cond, INSN_STRB_IMM, rt, rn, imm12, 1, 0); 750} 751 752static void tcg_out_ld8_r(TCGContext *s, ARMCond cond, TCGReg rt, 753 TCGReg rn, TCGReg rm) 754{ 755 tcg_out_memop_r(s, cond, INSN_LDRB_REG, rt, rn, rm, 1, 1, 0); 756} 757 758static void tcg_out_st8_r(TCGContext *s, ARMCond cond, TCGReg rt, 759 TCGReg rn, TCGReg rm) 760{ 761 tcg_out_memop_r(s, cond, INSN_STRB_REG, rt, rn, rm, 1, 1, 0); 762} 763 764static void tcg_out_ld8s_8(TCGContext *s, ARMCond cond, TCGReg rt, 765 TCGReg rn, int imm8) 766{ 767 tcg_out_memop_8(s, cond, INSN_LDRSB_IMM, rt, rn, imm8, 1, 0); 768} 769 770static void tcg_out_ld8s_r(TCGContext *s, ARMCond cond, TCGReg rt, 771 TCGReg rn, TCGReg rm) 772{ 773 tcg_out_memop_r(s, cond, INSN_LDRSB_REG, rt, rn, rm, 1, 1, 0); 774} 775 776static void tcg_out_movi_pool(TCGContext *s, ARMCond cond, 777 TCGReg rd, uint32_t arg) 778{ 779 new_pool_label(s, arg, R_ARM_PC13, s->code_ptr, 0); 780 tcg_out_ld32_12(s, cond, rd, TCG_REG_PC, 0); 781} 782 783static void tcg_out_movi32(TCGContext *s, ARMCond cond, 784 TCGReg rd, uint32_t arg) 785{ 786 int imm12, diff, opc, sh1, sh2; 787 uint32_t tt0, tt1, tt2; 788 789 /* Check a single MOV/MVN before anything else. */ 790 imm12 = encode_imm(arg); 791 if (imm12 >= 0) { 792 tcg_out_dat_imm(s, cond, ARITH_MOV, rd, 0, imm12); 793 return; 794 } 795 imm12 = encode_imm(~arg); 796 if (imm12 >= 0) { 797 tcg_out_dat_imm(s, cond, ARITH_MVN, rd, 0, imm12); 798 return; 799 } 800 801 /* Check for a pc-relative address. This will usually be the TB, 802 or within the TB, which is immediately before the code block. */ 803 diff = tcg_pcrel_diff(s, (void *)arg) - 8; 804 if (diff >= 0) { 805 imm12 = encode_imm(diff); 806 if (imm12 >= 0) { 807 tcg_out_dat_imm(s, cond, ARITH_ADD, rd, TCG_REG_PC, imm12); 808 return; 809 } 810 } else { 811 imm12 = encode_imm(-diff); 812 if (imm12 >= 0) { 813 tcg_out_dat_imm(s, cond, ARITH_SUB, rd, TCG_REG_PC, imm12); 814 return; 815 } 816 } 817 818 /* Use movw + movt. */ 819 if (use_armv7_instructions) { 820 /* movw */ 821 tcg_out32(s, (cond << 28) | 0x03000000 | (rd << 12) 822 | ((arg << 4) & 0x000f0000) | (arg & 0xfff)); 823 if (arg & 0xffff0000) { 824 /* movt */ 825 tcg_out32(s, (cond << 28) | 0x03400000 | (rd << 12) 826 | ((arg >> 12) & 0x000f0000) | ((arg >> 16) & 0xfff)); 827 } 828 return; 829 } 830 831 /* Look for sequences of two insns. If we have lots of 1's, we can 832 shorten the sequence by beginning with mvn and then clearing 833 higher bits with eor. */ 834 tt0 = arg; 835 opc = ARITH_MOV; 836 if (ctpop32(arg) > 16) { 837 tt0 = ~arg; 838 opc = ARITH_MVN; 839 } 840 sh1 = ctz32(tt0) & ~1; 841 tt1 = tt0 & ~(0xff << sh1); 842 sh2 = ctz32(tt1) & ~1; 843 tt2 = tt1 & ~(0xff << sh2); 844 if (tt2 == 0) { 845 int rot; 846 847 rot = ((32 - sh1) << 7) & 0xf00; 848 tcg_out_dat_imm(s, cond, opc, rd, 0, ((tt0 >> sh1) & 0xff) | rot); 849 rot = ((32 - sh2) << 7) & 0xf00; 850 tcg_out_dat_imm(s, cond, ARITH_EOR, rd, rd, 851 ((tt0 >> sh2) & 0xff) | rot); 852 return; 853 } 854 855 /* Otherwise, drop it into the constant pool. */ 856 tcg_out_movi_pool(s, cond, rd, arg); 857} 858 859/* 860 * Emit either the reg,imm or reg,reg form of a data-processing insn. 861 * rhs must satisfy the "rI" constraint. 862 */ 863static void tcg_out_dat_rI(TCGContext *s, ARMCond cond, ARMInsn opc, 864 TCGReg dst, TCGReg lhs, TCGArg rhs, int rhs_is_const) 865{ 866 if (rhs_is_const) { 867 tcg_out_dat_imm(s, cond, opc, dst, lhs, encode_imm_nofail(rhs)); 868 } else { 869 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); 870 } 871} 872 873/* 874 * Emit either the reg,imm or reg,reg form of a data-processing insn. 875 * rhs must satisfy the "rIK" constraint. 876 */ 877static void tcg_out_dat_IK(TCGContext *s, ARMCond cond, ARMInsn opc, 878 ARMInsn opinv, TCGReg dst, TCGReg lhs, TCGArg rhs) 879{ 880 int imm12 = encode_imm(rhs); 881 if (imm12 < 0) { 882 imm12 = encode_imm_nofail(~rhs); 883 opc = opinv; 884 } 885 tcg_out_dat_imm(s, cond, opc, dst, lhs, imm12); 886} 887 888static void tcg_out_dat_rIK(TCGContext *s, ARMCond cond, ARMInsn opc, 889 ARMInsn opinv, TCGReg dst, TCGReg lhs, TCGArg rhs, 890 bool rhs_is_const) 891{ 892 if (rhs_is_const) { 893 tcg_out_dat_IK(s, cond, opc, opinv, dst, lhs, rhs); 894 } else { 895 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); 896 } 897} 898 899static void tcg_out_dat_IN(TCGContext *s, ARMCond cond, ARMInsn opc, 900 ARMInsn opneg, TCGReg dst, TCGReg lhs, TCGArg rhs) 901{ 902 int imm12 = encode_imm(rhs); 903 if (imm12 < 0) { 904 imm12 = encode_imm_nofail(-rhs); 905 opc = opneg; 906 } 907 tcg_out_dat_imm(s, cond, opc, dst, lhs, imm12); 908} 909 910static void tcg_out_dat_rIN(TCGContext *s, ARMCond cond, ARMInsn opc, 911 ARMInsn opneg, TCGReg dst, TCGReg lhs, TCGArg rhs, 912 bool rhs_is_const) 913{ 914 /* Emit either the reg,imm or reg,reg form of a data-processing insn. 915 * rhs must satisfy the "rIN" constraint. 916 */ 917 if (rhs_is_const) { 918 tcg_out_dat_IN(s, cond, opc, opneg, dst, lhs, rhs); 919 } else { 920 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); 921 } 922} 923 924static void tcg_out_ext8s(TCGContext *s, TCGType t, TCGReg rd, TCGReg rn) 925{ 926 /* sxtb */ 927 tcg_out32(s, 0x06af0070 | (COND_AL << 28) | (rd << 12) | rn); 928} 929 930static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rn) 931{ 932 tcg_out_dat_imm(s, COND_AL, ARITH_AND, rd, rn, 0xff); 933} 934 935static void tcg_out_ext16s(TCGContext *s, TCGType t, TCGReg rd, TCGReg rn) 936{ 937 /* sxth */ 938 tcg_out32(s, 0x06bf0070 | (COND_AL << 28) | (rd << 12) | rn); 939} 940 941static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rn) 942{ 943 /* uxth */ 944 tcg_out32(s, 0x06ff0070 | (COND_AL << 28) | (rd << 12) | rn); 945} 946 947static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rn) 948{ 949 g_assert_not_reached(); 950} 951 952static void tcg_out_ext32u(TCGContext *s, TCGReg rd, TCGReg rn) 953{ 954 g_assert_not_reached(); 955} 956 957static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rn) 958{ 959 g_assert_not_reached(); 960} 961 962static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rn) 963{ 964 g_assert_not_reached(); 965} 966 967static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rn) 968{ 969 g_assert_not_reached(); 970} 971 972static void tcg_out_bswap16(TCGContext *s, ARMCond cond, 973 TCGReg rd, TCGReg rn, int flags) 974{ 975 if (flags & TCG_BSWAP_OS) { 976 /* revsh */ 977 tcg_out32(s, 0x06ff0fb0 | (cond << 28) | (rd << 12) | rn); 978 return; 979 } 980 981 /* rev16 */ 982 tcg_out32(s, 0x06bf0fb0 | (cond << 28) | (rd << 12) | rn); 983 if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 984 /* uxth */ 985 tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | rd); 986 } 987} 988 989static void tcg_out_bswap32(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rn) 990{ 991 /* rev */ 992 tcg_out32(s, 0x06bf0f30 | (cond << 28) | (rd << 12) | rn); 993} 994 995static void tcg_out_deposit(TCGContext *s, ARMCond cond, TCGReg rd, 996 TCGArg a1, int ofs, int len, bool const_a1) 997{ 998 if (const_a1) { 999 /* bfi becomes bfc with rn == 15. */ 1000 a1 = 15; 1001 } 1002 /* bfi/bfc */ 1003 tcg_out32(s, 0x07c00010 | (cond << 28) | (rd << 12) | a1 1004 | (ofs << 7) | ((ofs + len - 1) << 16)); 1005} 1006 1007static void tcg_out_extract(TCGContext *s, ARMCond cond, TCGReg rd, 1008 TCGReg rn, int ofs, int len) 1009{ 1010 /* According to gcc, AND can be faster. */ 1011 if (ofs == 0 && len <= 8) { 1012 tcg_out_dat_imm(s, cond, ARITH_AND, rd, rn, 1013 encode_imm_nofail((1 << len) - 1)); 1014 return; 1015 } 1016 1017 if (use_armv7_instructions) { 1018 /* ubfx */ 1019 tcg_out32(s, 0x07e00050 | (cond << 28) | (rd << 12) | rn 1020 | (ofs << 7) | ((len - 1) << 16)); 1021 return; 1022 } 1023 1024 assert(ofs % 8 == 0); 1025 switch (len) { 1026 case 8: 1027 /* uxtb */ 1028 tcg_out32(s, 0x06ef0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn); 1029 break; 1030 case 16: 1031 /* uxth */ 1032 tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn); 1033 break; 1034 default: 1035 g_assert_not_reached(); 1036 } 1037} 1038 1039static void tcg_out_sextract(TCGContext *s, ARMCond cond, TCGReg rd, 1040 TCGReg rn, int ofs, int len) 1041{ 1042 if (use_armv7_instructions) { 1043 /* sbfx */ 1044 tcg_out32(s, 0x07a00050 | (cond << 28) | (rd << 12) | rn 1045 | (ofs << 7) | ((len - 1) << 16)); 1046 return; 1047 } 1048 1049 assert(ofs % 8 == 0); 1050 switch (len) { 1051 case 8: 1052 /* sxtb */ 1053 tcg_out32(s, 0x06af0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn); 1054 break; 1055 case 16: 1056 /* sxth */ 1057 tcg_out32(s, 0x06bf0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn); 1058 break; 1059 default: 1060 g_assert_not_reached(); 1061 } 1062} 1063 1064 1065static void tcg_out_ld32u(TCGContext *s, ARMCond cond, 1066 TCGReg rd, TCGReg rn, int32_t offset) 1067{ 1068 if (offset > 0xfff || offset < -0xfff) { 1069 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1070 tcg_out_ld32_r(s, cond, rd, rn, TCG_REG_TMP); 1071 } else 1072 tcg_out_ld32_12(s, cond, rd, rn, offset); 1073} 1074 1075static void tcg_out_st32(TCGContext *s, ARMCond cond, 1076 TCGReg rd, TCGReg rn, int32_t offset) 1077{ 1078 if (offset > 0xfff || offset < -0xfff) { 1079 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1080 tcg_out_st32_r(s, cond, rd, rn, TCG_REG_TMP); 1081 } else 1082 tcg_out_st32_12(s, cond, rd, rn, offset); 1083} 1084 1085static void tcg_out_ld16u(TCGContext *s, ARMCond cond, 1086 TCGReg rd, TCGReg rn, int32_t offset) 1087{ 1088 if (offset > 0xff || offset < -0xff) { 1089 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1090 tcg_out_ld16u_r(s, cond, rd, rn, TCG_REG_TMP); 1091 } else 1092 tcg_out_ld16u_8(s, cond, rd, rn, offset); 1093} 1094 1095static void tcg_out_ld16s(TCGContext *s, ARMCond cond, 1096 TCGReg rd, TCGReg rn, int32_t offset) 1097{ 1098 if (offset > 0xff || offset < -0xff) { 1099 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1100 tcg_out_ld16s_r(s, cond, rd, rn, TCG_REG_TMP); 1101 } else 1102 tcg_out_ld16s_8(s, cond, rd, rn, offset); 1103} 1104 1105static void tcg_out_st16(TCGContext *s, ARMCond cond, 1106 TCGReg rd, TCGReg rn, int32_t offset) 1107{ 1108 if (offset > 0xff || offset < -0xff) { 1109 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1110 tcg_out_st16_r(s, cond, rd, rn, TCG_REG_TMP); 1111 } else 1112 tcg_out_st16_8(s, cond, rd, rn, offset); 1113} 1114 1115static void tcg_out_ld8u(TCGContext *s, ARMCond cond, 1116 TCGReg rd, TCGReg rn, int32_t offset) 1117{ 1118 if (offset > 0xfff || offset < -0xfff) { 1119 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1120 tcg_out_ld8_r(s, cond, rd, rn, TCG_REG_TMP); 1121 } else 1122 tcg_out_ld8_12(s, cond, rd, rn, offset); 1123} 1124 1125static void tcg_out_ld8s(TCGContext *s, ARMCond cond, 1126 TCGReg rd, TCGReg rn, int32_t offset) 1127{ 1128 if (offset > 0xff || offset < -0xff) { 1129 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1130 tcg_out_ld8s_r(s, cond, rd, rn, TCG_REG_TMP); 1131 } else 1132 tcg_out_ld8s_8(s, cond, rd, rn, offset); 1133} 1134 1135static void tcg_out_st8(TCGContext *s, ARMCond cond, 1136 TCGReg rd, TCGReg rn, int32_t offset) 1137{ 1138 if (offset > 0xfff || offset < -0xfff) { 1139 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1140 tcg_out_st8_r(s, cond, rd, rn, TCG_REG_TMP); 1141 } else 1142 tcg_out_st8_12(s, cond, rd, rn, offset); 1143} 1144 1145/* 1146 * The _goto case is normally between TBs within the same code buffer, and 1147 * with the code buffer limited to 16MB we wouldn't need the long case. 1148 * But we also use it for the tail-call to the qemu_ld/st helpers, which does. 1149 */ 1150static void tcg_out_goto(TCGContext *s, ARMCond cond, const tcg_insn_unit *addr) 1151{ 1152 intptr_t addri = (intptr_t)addr; 1153 ptrdiff_t disp = tcg_pcrel_diff(s, addr); 1154 bool arm_mode = !(addri & 1); 1155 1156 if (arm_mode && disp - 8 < 0x01fffffd && disp - 8 > -0x01fffffd) { 1157 tcg_out_b_imm(s, cond, disp); 1158 return; 1159 } 1160 1161 /* LDR is interworking from v5t. */ 1162 tcg_out_movi_pool(s, cond, TCG_REG_PC, addri); 1163} 1164 1165/* 1166 * The call case is mostly used for helpers - so it's not unreasonable 1167 * for them to be beyond branch range. 1168 */ 1169static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *addr) 1170{ 1171 intptr_t addri = (intptr_t)addr; 1172 ptrdiff_t disp = tcg_pcrel_diff(s, addr); 1173 bool arm_mode = !(addri & 1); 1174 1175 if (disp - 8 < 0x02000000 && disp - 8 >= -0x02000000) { 1176 if (arm_mode) { 1177 tcg_out_bl_imm(s, COND_AL, disp); 1178 } else { 1179 tcg_out_blx_imm(s, disp); 1180 } 1181 return; 1182 } 1183 1184 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri); 1185 tcg_out_blx_reg(s, COND_AL, TCG_REG_TMP); 1186} 1187 1188static void tcg_out_call(TCGContext *s, const tcg_insn_unit *addr, 1189 const TCGHelperInfo *info) 1190{ 1191 tcg_out_call_int(s, addr); 1192} 1193 1194static void tcg_out_goto_label(TCGContext *s, ARMCond cond, TCGLabel *l) 1195{ 1196 if (l->has_value) { 1197 tcg_out_goto(s, cond, l->u.value_ptr); 1198 } else { 1199 tcg_out_reloc(s, s->code_ptr, R_ARM_PC24, l, 0); 1200 tcg_out_b_imm(s, cond, 0); 1201 } 1202} 1203 1204static void tcg_out_mb(TCGContext *s, TCGArg a0) 1205{ 1206 if (use_armv7_instructions) { 1207 tcg_out32(s, INSN_DMB_ISH); 1208 } else { 1209 tcg_out32(s, INSN_DMB_MCR); 1210 } 1211} 1212 1213static TCGCond tgen_cmp(TCGContext *s, TCGCond cond, TCGReg a, TCGReg b) 1214{ 1215 if (is_tst_cond(cond)) { 1216 tcg_out_dat_reg(s, COND_AL, ARITH_TST, 0, a, b, SHIFT_IMM_LSL(0)); 1217 return tcg_tst_eqne_cond(cond); 1218 } 1219 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, a, b, SHIFT_IMM_LSL(0)); 1220 return cond; 1221} 1222 1223static TCGCond tgen_cmpi(TCGContext *s, TCGCond cond, TCGReg a, TCGArg b) 1224{ 1225 int imm12; 1226 1227 if (!is_tst_cond(cond)) { 1228 tcg_out_dat_IN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, a, b); 1229 return cond; 1230 } 1231 1232 /* 1233 * The compare constraints allow rIN, but TST does not support N. 1234 * Be prepared to load the constant into a scratch register. 1235 */ 1236 imm12 = encode_imm(b); 1237 if (imm12 >= 0) { 1238 tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, a, imm12); 1239 } else { 1240 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, b); 1241 tcg_out_dat_reg(s, COND_AL, ARITH_TST, 0, 1242 a, TCG_REG_TMP, SHIFT_IMM_LSL(0)); 1243 } 1244 return tcg_tst_eqne_cond(cond); 1245} 1246 1247static TCGCond tcg_out_cmp(TCGContext *s, TCGCond cond, TCGReg a, 1248 TCGArg b, int b_const) 1249{ 1250 if (b_const) { 1251 return tgen_cmpi(s, cond, a, b); 1252 } else { 1253 return tgen_cmp(s, cond, a, b); 1254 } 1255} 1256 1257static TCGCond tcg_out_cmp2(TCGContext *s, const TCGArg *args, 1258 const int *const_args) 1259{ 1260 TCGReg al = args[0]; 1261 TCGReg ah = args[1]; 1262 TCGArg bl = args[2]; 1263 TCGArg bh = args[3]; 1264 TCGCond cond = args[4]; 1265 int const_bl = const_args[2]; 1266 int const_bh = const_args[3]; 1267 1268 switch (cond) { 1269 case TCG_COND_EQ: 1270 case TCG_COND_NE: 1271 case TCG_COND_LTU: 1272 case TCG_COND_LEU: 1273 case TCG_COND_GTU: 1274 case TCG_COND_GEU: 1275 /* 1276 * We perform a conditional comparison. If the high half is 1277 * equal, then overwrite the flags with the comparison of the 1278 * low half. The resulting flags cover the whole. 1279 */ 1280 tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, ah, bh, const_bh); 1281 tcg_out_dat_rI(s, COND_EQ, ARITH_CMP, 0, al, bl, const_bl); 1282 return cond; 1283 1284 case TCG_COND_TSTEQ: 1285 case TCG_COND_TSTNE: 1286 /* Similar, but with TST instead of CMP. */ 1287 tcg_out_dat_rI(s, COND_AL, ARITH_TST, 0, ah, bh, const_bh); 1288 tcg_out_dat_rI(s, COND_EQ, ARITH_TST, 0, al, bl, const_bl); 1289 return tcg_tst_eqne_cond(cond); 1290 1291 case TCG_COND_LT: 1292 case TCG_COND_GE: 1293 /* We perform a double-word subtraction and examine the result. 1294 We do not actually need the result of the subtract, so the 1295 low part "subtract" is a compare. For the high half we have 1296 no choice but to compute into a temporary. */ 1297 tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, al, bl, const_bl); 1298 tcg_out_dat_rI(s, COND_AL, ARITH_SBC | TO_CPSR, 1299 TCG_REG_TMP, ah, bh, const_bh); 1300 return cond; 1301 1302 case TCG_COND_LE: 1303 case TCG_COND_GT: 1304 /* Similar, but with swapped arguments, via reversed subtract. */ 1305 tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR, 1306 TCG_REG_TMP, al, bl, const_bl); 1307 tcg_out_dat_rI(s, COND_AL, ARITH_RSC | TO_CPSR, 1308 TCG_REG_TMP, ah, bh, const_bh); 1309 return tcg_swap_cond(cond); 1310 1311 default: 1312 g_assert_not_reached(); 1313 } 1314} 1315 1316/* 1317 * Note that TCGReg references Q-registers. 1318 * Q-regno = 2 * D-regno, so shift left by 1 while inserting. 1319 */ 1320static uint32_t encode_vd(TCGReg rd) 1321{ 1322 tcg_debug_assert(rd >= TCG_REG_Q0); 1323 return (extract32(rd, 3, 1) << 22) | (extract32(rd, 0, 3) << 13); 1324} 1325 1326static uint32_t encode_vn(TCGReg rn) 1327{ 1328 tcg_debug_assert(rn >= TCG_REG_Q0); 1329 return (extract32(rn, 3, 1) << 7) | (extract32(rn, 0, 3) << 17); 1330} 1331 1332static uint32_t encode_vm(TCGReg rm) 1333{ 1334 tcg_debug_assert(rm >= TCG_REG_Q0); 1335 return (extract32(rm, 3, 1) << 5) | (extract32(rm, 0, 3) << 1); 1336} 1337 1338static void tcg_out_vreg2(TCGContext *s, ARMInsn insn, int q, int vece, 1339 TCGReg d, TCGReg m) 1340{ 1341 tcg_out32(s, insn | (vece << 18) | (q << 6) | 1342 encode_vd(d) | encode_vm(m)); 1343} 1344 1345static void tcg_out_vreg3(TCGContext *s, ARMInsn insn, int q, int vece, 1346 TCGReg d, TCGReg n, TCGReg m) 1347{ 1348 tcg_out32(s, insn | (vece << 20) | (q << 6) | 1349 encode_vd(d) | encode_vn(n) | encode_vm(m)); 1350} 1351 1352static void tcg_out_vmovi(TCGContext *s, TCGReg rd, 1353 int q, int op, int cmode, uint8_t imm8) 1354{ 1355 tcg_out32(s, INSN_VMOVI | encode_vd(rd) | (q << 6) | (op << 5) 1356 | (cmode << 8) | extract32(imm8, 0, 4) 1357 | (extract32(imm8, 4, 3) << 16) 1358 | (extract32(imm8, 7, 1) << 24)); 1359} 1360 1361static void tcg_out_vshifti(TCGContext *s, ARMInsn insn, int q, 1362 TCGReg rd, TCGReg rm, int l_imm6) 1363{ 1364 tcg_out32(s, insn | (q << 6) | encode_vd(rd) | encode_vm(rm) | 1365 (extract32(l_imm6, 6, 1) << 7) | 1366 (extract32(l_imm6, 0, 6) << 16)); 1367} 1368 1369static void tcg_out_vldst(TCGContext *s, ARMInsn insn, 1370 TCGReg rd, TCGReg rn, int offset) 1371{ 1372 if (offset != 0) { 1373 if (check_fit_imm(offset) || check_fit_imm(-offset)) { 1374 tcg_out_dat_rIN(s, COND_AL, ARITH_ADD, ARITH_SUB, 1375 TCG_REG_TMP, rn, offset, true); 1376 } else { 1377 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, offset); 1378 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, 1379 TCG_REG_TMP, TCG_REG_TMP, rn, 0); 1380 } 1381 rn = TCG_REG_TMP; 1382 } 1383 tcg_out32(s, insn | (rn << 16) | encode_vd(rd) | 0xf); 1384} 1385 1386typedef struct { 1387 ARMCond cond; 1388 TCGReg base; 1389 int index; 1390 bool index_scratch; 1391 TCGAtomAlign aa; 1392} HostAddress; 1393 1394bool tcg_target_has_memory_bswap(MemOp memop) 1395{ 1396 return false; 1397} 1398 1399static TCGReg ldst_ra_gen(TCGContext *s, const TCGLabelQemuLdst *l, int arg) 1400{ 1401 /* We arrive at the slow path via "BLNE", so R14 contains l->raddr. */ 1402 return TCG_REG_R14; 1403} 1404 1405static const TCGLdstHelperParam ldst_helper_param = { 1406 .ra_gen = ldst_ra_gen, 1407 .ntmp = 1, 1408 .tmp = { TCG_REG_TMP }, 1409}; 1410 1411static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1412{ 1413 MemOp opc = get_memop(lb->oi); 1414 1415 if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1416 return false; 1417 } 1418 1419 tcg_out_ld_helper_args(s, lb, &ldst_helper_param); 1420 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE]); 1421 tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param); 1422 1423 tcg_out_goto(s, COND_AL, lb->raddr); 1424 return true; 1425} 1426 1427static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1428{ 1429 MemOp opc = get_memop(lb->oi); 1430 1431 if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1432 return false; 1433 } 1434 1435 tcg_out_st_helper_args(s, lb, &ldst_helper_param); 1436 1437 /* Tail-call to the helper, which will return to the fast path. */ 1438 tcg_out_goto(s, COND_AL, qemu_st_helpers[opc & MO_SIZE]); 1439 return true; 1440} 1441 1442/* We expect to use an 9-bit sign-magnitude negative offset from ENV. */ 1443#define MIN_TLB_MASK_TABLE_OFS -256 1444 1445static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1446 TCGReg addr, MemOpIdx oi, bool is_ld) 1447{ 1448 TCGLabelQemuLdst *ldst = NULL; 1449 MemOp opc = get_memop(oi); 1450 unsigned a_mask; 1451 1452 if (tcg_use_softmmu) { 1453 *h = (HostAddress){ 1454 .cond = COND_AL, 1455 .base = addr, 1456 .index = TCG_REG_R1, 1457 .index_scratch = true, 1458 }; 1459 } else { 1460 *h = (HostAddress){ 1461 .cond = COND_AL, 1462 .base = addr, 1463 .index = guest_base ? TCG_REG_GUEST_BASE : -1, 1464 .index_scratch = false, 1465 }; 1466 } 1467 1468 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); 1469 a_mask = (1 << h->aa.align) - 1; 1470 1471 if (tcg_use_softmmu) { 1472 int mem_index = get_mmuidx(oi); 1473 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read) 1474 : offsetof(CPUTLBEntry, addr_write); 1475 int fast_off = tlb_mask_table_ofs(s, mem_index); 1476 unsigned s_mask = (1 << (opc & MO_SIZE)) - 1; 1477 TCGReg t_addr; 1478 1479 ldst = new_ldst_label(s); 1480 ldst->is_ld = is_ld; 1481 ldst->oi = oi; 1482 ldst->addr_reg = addr; 1483 1484 /* Load cpu->neg.tlb.f[mmu_idx].{mask,table} into {r0,r1}. */ 1485 QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0); 1486 QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != 4); 1487 tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off); 1488 1489 /* Extract the tlb index from the address into R0. */ 1490 tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, addr, 1491 SHIFT_IMM_LSR(s->page_bits - CPU_TLB_ENTRY_BITS)); 1492 1493 /* 1494 * Add the tlb_table pointer, creating the CPUTLBEntry address in R1. 1495 * Load the tlb comparator into R2 and the fast path addend into R1. 1496 */ 1497 if (cmp_off == 0) { 1498 tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0); 1499 } else { 1500 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, 1501 TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0); 1502 tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); 1503 } 1504 1505 /* Load the tlb addend. */ 1506 tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R1, 1507 offsetof(CPUTLBEntry, addend)); 1508 1509 /* 1510 * Check alignment, check comparators. 1511 * Do this in 2-4 insns. Use MOVW for v7, if possible, 1512 * to reduce the number of sequential conditional instructions. 1513 * Almost all guests have at least 4k pages, which means that we need 1514 * to clear at least 9 bits even for an 8-byte memory, which means it 1515 * isn't worth checking for an immediate operand for BIC. 1516 * 1517 * For unaligned accesses, test the page of the last unit of alignment. 1518 * This leaves the least significant alignment bits unchanged, and of 1519 * course must be zero. 1520 */ 1521 t_addr = addr; 1522 if (a_mask < s_mask) { 1523 t_addr = TCG_REG_R0; 1524 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, t_addr, 1525 addr, s_mask - a_mask); 1526 } 1527 if (use_armv7_instructions && s->page_bits <= 16) { 1528 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, ~(s->page_mask | a_mask)); 1529 tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP, 1530 t_addr, TCG_REG_TMP, 0); 1531 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, 1532 TCG_REG_R2, TCG_REG_TMP, 0); 1533 } else { 1534 if (a_mask) { 1535 tcg_debug_assert(a_mask <= 0xff); 1536 tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addr, a_mask); 1537 } 1538 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, t_addr, 1539 SHIFT_IMM_LSR(s->page_bits)); 1540 tcg_out_dat_reg(s, (a_mask ? COND_EQ : COND_AL), ARITH_CMP, 1541 0, TCG_REG_R2, TCG_REG_TMP, 1542 SHIFT_IMM_LSL(s->page_bits)); 1543 } 1544 } else if (a_mask) { 1545 ldst = new_ldst_label(s); 1546 ldst->is_ld = is_ld; 1547 ldst->oi = oi; 1548 ldst->addr_reg = addr; 1549 1550 /* We are expecting alignment to max out at 7 */ 1551 tcg_debug_assert(a_mask <= 0xff); 1552 /* tst addr, #mask */ 1553 tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addr, a_mask); 1554 } 1555 1556 return ldst; 1557} 1558 1559static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo, 1560 TCGReg datahi, HostAddress h) 1561{ 1562 TCGReg base; 1563 1564 /* Byte swapping is left to middle-end expansion. */ 1565 tcg_debug_assert((opc & MO_BSWAP) == 0); 1566 1567 switch (opc & MO_SSIZE) { 1568 case MO_UB: 1569 if (h.index < 0) { 1570 tcg_out_ld8_12(s, h.cond, datalo, h.base, 0); 1571 } else { 1572 tcg_out_ld8_r(s, h.cond, datalo, h.base, h.index); 1573 } 1574 break; 1575 case MO_SB: 1576 if (h.index < 0) { 1577 tcg_out_ld8s_8(s, h.cond, datalo, h.base, 0); 1578 } else { 1579 tcg_out_ld8s_r(s, h.cond, datalo, h.base, h.index); 1580 } 1581 break; 1582 case MO_UW: 1583 if (h.index < 0) { 1584 tcg_out_ld16u_8(s, h.cond, datalo, h.base, 0); 1585 } else { 1586 tcg_out_ld16u_r(s, h.cond, datalo, h.base, h.index); 1587 } 1588 break; 1589 case MO_SW: 1590 if (h.index < 0) { 1591 tcg_out_ld16s_8(s, h.cond, datalo, h.base, 0); 1592 } else { 1593 tcg_out_ld16s_r(s, h.cond, datalo, h.base, h.index); 1594 } 1595 break; 1596 case MO_UL: 1597 if (h.index < 0) { 1598 tcg_out_ld32_12(s, h.cond, datalo, h.base, 0); 1599 } else { 1600 tcg_out_ld32_r(s, h.cond, datalo, h.base, h.index); 1601 } 1602 break; 1603 case MO_UQ: 1604 /* We used pair allocation for datalo, so already should be aligned. */ 1605 tcg_debug_assert((datalo & 1) == 0); 1606 tcg_debug_assert(datahi == datalo + 1); 1607 /* LDRD requires alignment; double-check that. */ 1608 if (memop_alignment_bits(opc) >= MO_64) { 1609 if (h.index < 0) { 1610 tcg_out_ldrd_8(s, h.cond, datalo, h.base, 0); 1611 break; 1612 } 1613 /* 1614 * Rm (the second address op) must not overlap Rt or Rt + 1. 1615 * Since datalo is aligned, we can simplify the test via alignment. 1616 * Flip the two address arguments if that works. 1617 */ 1618 if ((h.index & ~1) != datalo) { 1619 tcg_out_ldrd_r(s, h.cond, datalo, h.base, h.index); 1620 break; 1621 } 1622 if ((h.base & ~1) != datalo) { 1623 tcg_out_ldrd_r(s, h.cond, datalo, h.index, h.base); 1624 break; 1625 } 1626 } 1627 if (h.index < 0) { 1628 base = h.base; 1629 if (datalo == h.base) { 1630 tcg_out_mov_reg(s, h.cond, TCG_REG_TMP, base); 1631 base = TCG_REG_TMP; 1632 } 1633 } else if (h.index_scratch) { 1634 tcg_out_ld32_rwb(s, h.cond, datalo, h.index, h.base); 1635 tcg_out_ld32_12(s, h.cond, datahi, h.index, 4); 1636 break; 1637 } else { 1638 tcg_out_dat_reg(s, h.cond, ARITH_ADD, TCG_REG_TMP, 1639 h.base, h.index, SHIFT_IMM_LSL(0)); 1640 base = TCG_REG_TMP; 1641 } 1642 tcg_out_ld32_12(s, h.cond, datalo, base, 0); 1643 tcg_out_ld32_12(s, h.cond, datahi, base, 4); 1644 break; 1645 default: 1646 g_assert_not_reached(); 1647 } 1648} 1649 1650static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, 1651 TCGReg addr, MemOpIdx oi, TCGType data_type) 1652{ 1653 MemOp opc = get_memop(oi); 1654 TCGLabelQemuLdst *ldst; 1655 HostAddress h; 1656 1657 ldst = prepare_host_addr(s, &h, addr, oi, true); 1658 if (ldst) { 1659 ldst->type = data_type; 1660 ldst->datalo_reg = datalo; 1661 ldst->datahi_reg = datahi; 1662 1663 /* 1664 * This a conditional BL only to load a pointer within this 1665 * opcode into LR for the slow path. We will not be using 1666 * the value for a tail call. 1667 */ 1668 ldst->label_ptr[0] = s->code_ptr; 1669 tcg_out_bl_imm(s, COND_NE, 0); 1670 1671 tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); 1672 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1673 } else { 1674 tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); 1675 } 1676} 1677 1678static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo, 1679 TCGReg datahi, HostAddress h) 1680{ 1681 /* Byte swapping is left to middle-end expansion. */ 1682 tcg_debug_assert((opc & MO_BSWAP) == 0); 1683 1684 switch (opc & MO_SIZE) { 1685 case MO_8: 1686 if (h.index < 0) { 1687 tcg_out_st8_12(s, h.cond, datalo, h.base, 0); 1688 } else { 1689 tcg_out_st8_r(s, h.cond, datalo, h.base, h.index); 1690 } 1691 break; 1692 case MO_16: 1693 if (h.index < 0) { 1694 tcg_out_st16_8(s, h.cond, datalo, h.base, 0); 1695 } else { 1696 tcg_out_st16_r(s, h.cond, datalo, h.base, h.index); 1697 } 1698 break; 1699 case MO_32: 1700 if (h.index < 0) { 1701 tcg_out_st32_12(s, h.cond, datalo, h.base, 0); 1702 } else { 1703 tcg_out_st32_r(s, h.cond, datalo, h.base, h.index); 1704 } 1705 break; 1706 case MO_64: 1707 /* We used pair allocation for datalo, so already should be aligned. */ 1708 tcg_debug_assert((datalo & 1) == 0); 1709 tcg_debug_assert(datahi == datalo + 1); 1710 /* STRD requires alignment; double-check that. */ 1711 if (memop_alignment_bits(opc) >= MO_64) { 1712 if (h.index < 0) { 1713 tcg_out_strd_8(s, h.cond, datalo, h.base, 0); 1714 } else { 1715 tcg_out_strd_r(s, h.cond, datalo, h.base, h.index); 1716 } 1717 } else if (h.index < 0) { 1718 tcg_out_st32_12(s, h.cond, datalo, h.base, 0); 1719 tcg_out_st32_12(s, h.cond, datahi, h.base, 4); 1720 } else if (h.index_scratch) { 1721 tcg_out_st32_rwb(s, h.cond, datalo, h.index, h.base); 1722 tcg_out_st32_12(s, h.cond, datahi, h.index, 4); 1723 } else { 1724 tcg_out_dat_reg(s, h.cond, ARITH_ADD, TCG_REG_TMP, 1725 h.base, h.index, SHIFT_IMM_LSL(0)); 1726 tcg_out_st32_12(s, h.cond, datalo, TCG_REG_TMP, 0); 1727 tcg_out_st32_12(s, h.cond, datahi, TCG_REG_TMP, 4); 1728 } 1729 break; 1730 default: 1731 g_assert_not_reached(); 1732 } 1733} 1734 1735static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, 1736 TCGReg addr, MemOpIdx oi, TCGType data_type) 1737{ 1738 MemOp opc = get_memop(oi); 1739 TCGLabelQemuLdst *ldst; 1740 HostAddress h; 1741 1742 ldst = prepare_host_addr(s, &h, addr, oi, false); 1743 if (ldst) { 1744 ldst->type = data_type; 1745 ldst->datalo_reg = datalo; 1746 ldst->datahi_reg = datahi; 1747 1748 h.cond = COND_EQ; 1749 tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); 1750 1751 /* The conditional call is last, as we're going to return here. */ 1752 ldst->label_ptr[0] = s->code_ptr; 1753 tcg_out_bl_imm(s, COND_NE, 0); 1754 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1755 } else { 1756 tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); 1757 } 1758} 1759 1760static void tcg_out_epilogue(TCGContext *s); 1761 1762static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg) 1763{ 1764 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, arg); 1765 tcg_out_epilogue(s); 1766} 1767 1768static void tcg_out_goto_tb(TCGContext *s, int which) 1769{ 1770 uintptr_t i_addr; 1771 intptr_t i_disp; 1772 1773 /* Direct branch will be patched by tb_target_set_jmp_target. */ 1774 set_jmp_insn_offset(s, which); 1775 tcg_out32(s, INSN_NOP); 1776 1777 /* When branch is out of range, fall through to indirect. */ 1778 i_addr = get_jmp_target_addr(s, which); 1779 i_disp = tcg_pcrel_diff(s, (void *)i_addr) - 8; 1780 tcg_debug_assert(i_disp < 0); 1781 if (i_disp >= -0xfff) { 1782 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, i_disp); 1783 } else { 1784 /* 1785 * The TB is close, but outside the 12 bits addressable by 1786 * the load. We can extend this to 20 bits with a sub of a 1787 * shifted immediate from pc. 1788 */ 1789 int h = -i_disp; 1790 int l = -(h & 0xfff); 1791 1792 h = encode_imm_nofail(h + l); 1793 tcg_out_dat_imm(s, COND_AL, ARITH_SUB, TCG_REG_R0, TCG_REG_PC, h); 1794 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_R0, l); 1795 } 1796 set_jmp_reset_offset(s, which); 1797} 1798 1799void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1800 uintptr_t jmp_rx, uintptr_t jmp_rw) 1801{ 1802 uintptr_t addr = tb->jmp_target_addr[n]; 1803 ptrdiff_t offset = addr - (jmp_rx + 8); 1804 tcg_insn_unit insn; 1805 1806 /* Either directly branch, or fall through to indirect branch. */ 1807 if (offset == sextract64(offset, 0, 26)) { 1808 /* B <addr> */ 1809 insn = deposit32((COND_AL << 28) | INSN_B, 0, 24, offset >> 2); 1810 } else { 1811 insn = INSN_NOP; 1812 } 1813 1814 qatomic_set((uint32_t *)jmp_rw, insn); 1815 flush_idcache_range(jmp_rx, jmp_rw, 4); 1816} 1817 1818 1819static void tgen_add(TCGContext *s, TCGType type, 1820 TCGReg a0, TCGReg a1, TCGReg a2) 1821{ 1822 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, a0, a1, a2, SHIFT_IMM_LSL(0)); 1823} 1824 1825static void tgen_addi(TCGContext *s, TCGType type, 1826 TCGReg a0, TCGReg a1, tcg_target_long a2) 1827{ 1828 tcg_out_dat_IN(s, COND_AL, ARITH_ADD, ARITH_SUB, a0, a1, a2); 1829} 1830 1831static const TCGOutOpBinary outop_add = { 1832 .base.static_constraint = C_O1_I2(r, r, rIN), 1833 .out_rrr = tgen_add, 1834 .out_rri = tgen_addi, 1835}; 1836 1837static void tgen_and(TCGContext *s, TCGType type, 1838 TCGReg a0, TCGReg a1, TCGReg a2) 1839{ 1840 tcg_out_dat_reg(s, COND_AL, ARITH_AND, a0, a1, a2, SHIFT_IMM_LSL(0)); 1841} 1842 1843static void tgen_andi(TCGContext *s, TCGType type, 1844 TCGReg a0, TCGReg a1, tcg_target_long a2) 1845{ 1846 tcg_out_dat_IK(s, COND_AL, ARITH_AND, ARITH_BIC, a0, a1, a2); 1847} 1848 1849static const TCGOutOpBinary outop_and = { 1850 .base.static_constraint = C_O1_I2(r, r, rIK), 1851 .out_rrr = tgen_and, 1852 .out_rri = tgen_andi, 1853}; 1854 1855static void tgen_andc(TCGContext *s, TCGType type, 1856 TCGReg a0, TCGReg a1, TCGReg a2) 1857{ 1858 tcg_out_dat_reg(s, COND_AL, ARITH_BIC, a0, a1, a2, SHIFT_IMM_LSL(0)); 1859} 1860 1861static const TCGOutOpBinary outop_andc = { 1862 .base.static_constraint = C_O1_I2(r, r, r), 1863 .out_rrr = tgen_andc, 1864}; 1865 1866static void tgen_clz(TCGContext *s, TCGType type, 1867 TCGReg a0, TCGReg a1, TCGReg a2) 1868{ 1869 tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0, a1, 0); 1870 tcg_out_dat_reg(s, COND_NE, INSN_CLZ, a0, 0, a1, 0); 1871 tcg_out_mov_reg(s, COND_EQ, a0, a2); 1872} 1873 1874static void tgen_clzi(TCGContext *s, TCGType type, 1875 TCGReg a0, TCGReg a1, tcg_target_long a2) 1876{ 1877 if (a2 == 32) { 1878 tcg_out_dat_reg(s, COND_AL, INSN_CLZ, a0, 0, a1, 0); 1879 } else { 1880 tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0, a1, 0); 1881 tcg_out_dat_reg(s, COND_NE, INSN_CLZ, a0, 0, a1, 0); 1882 tcg_out_movi32(s, COND_EQ, a0, a2); 1883 } 1884} 1885 1886static const TCGOutOpBinary outop_clz = { 1887 .base.static_constraint = C_O1_I2(r, r, rIK), 1888 .out_rrr = tgen_clz, 1889 .out_rri = tgen_clzi, 1890}; 1891 1892static const TCGOutOpUnary outop_ctpop = { 1893 .base.static_constraint = C_NotImplemented, 1894}; 1895 1896static void tgen_ctz(TCGContext *s, TCGType type, 1897 TCGReg a0, TCGReg a1, TCGReg a2) 1898{ 1899 tcg_out_dat_reg(s, COND_AL, INSN_RBIT, TCG_REG_TMP, 0, a1, 0); 1900 tgen_clz(s, TCG_TYPE_I32, a0, TCG_REG_TMP, a2); 1901} 1902 1903static void tgen_ctzi(TCGContext *s, TCGType type, 1904 TCGReg a0, TCGReg a1, tcg_target_long a2) 1905{ 1906 tcg_out_dat_reg(s, COND_AL, INSN_RBIT, TCG_REG_TMP, 0, a1, 0); 1907 tgen_clzi(s, TCG_TYPE_I32, a0, TCG_REG_TMP, a2); 1908} 1909 1910static TCGConstraintSetIndex cset_ctz(TCGType type, unsigned flags) 1911{ 1912 return use_armv7_instructions ? C_O1_I2(r, r, rIK) : C_NotImplemented; 1913} 1914 1915static const TCGOutOpBinary outop_ctz = { 1916 .base.static_constraint = C_Dynamic, 1917 .base.dynamic_constraint = cset_ctz, 1918 .out_rrr = tgen_ctz, 1919 .out_rri = tgen_ctzi, 1920}; 1921 1922static TCGConstraintSetIndex cset_idiv(TCGType type, unsigned flags) 1923{ 1924 return use_idiv_instructions ? C_O1_I2(r, r, r) : C_NotImplemented; 1925} 1926 1927static void tgen_divs(TCGContext *s, TCGType type, 1928 TCGReg a0, TCGReg a1, TCGReg a2) 1929{ 1930 /* sdiv */ 1931 tcg_out32(s, 0x0710f010 | (COND_AL << 28) | (a0 << 16) | a1 | (a2 << 8)); 1932} 1933 1934static const TCGOutOpBinary outop_divs = { 1935 .base.static_constraint = C_Dynamic, 1936 .base.dynamic_constraint = cset_idiv, 1937 .out_rrr = tgen_divs, 1938}; 1939 1940static const TCGOutOpDivRem outop_divs2 = { 1941 .base.static_constraint = C_NotImplemented, 1942}; 1943 1944static void tgen_divu(TCGContext *s, TCGType type, 1945 TCGReg a0, TCGReg a1, TCGReg a2) 1946{ 1947 /* udiv */ 1948 tcg_out32(s, 0x0730f010 | (COND_AL << 28) | (a0 << 16) | a1 | (a2 << 8)); 1949} 1950 1951static const TCGOutOpBinary outop_divu = { 1952 .base.static_constraint = C_Dynamic, 1953 .base.dynamic_constraint = cset_idiv, 1954 .out_rrr = tgen_divu, 1955}; 1956 1957static const TCGOutOpDivRem outop_divu2 = { 1958 .base.static_constraint = C_NotImplemented, 1959}; 1960 1961static const TCGOutOpBinary outop_eqv = { 1962 .base.static_constraint = C_NotImplemented, 1963}; 1964 1965static void tgen_mul(TCGContext *s, TCGType type, 1966 TCGReg a0, TCGReg a1, TCGReg a2) 1967{ 1968 /* mul */ 1969 tcg_out32(s, (COND_AL << 28) | 0x90 | (a0 << 16) | (a1 << 8) | a2); 1970} 1971 1972static const TCGOutOpBinary outop_mul = { 1973 .base.static_constraint = C_O1_I2(r, r, r), 1974 .out_rrr = tgen_mul, 1975}; 1976 1977static void tgen_muls2(TCGContext *s, TCGType type, 1978 TCGReg rd0, TCGReg rd1, TCGReg rn, TCGReg rm) 1979{ 1980 /* smull */ 1981 tcg_out32(s, (COND_AL << 28) | 0x00c00090 | 1982 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); 1983} 1984 1985static const TCGOutOpMul2 outop_muls2 = { 1986 .base.static_constraint = C_O2_I2(r, r, r, r), 1987 .out_rrrr = tgen_muls2, 1988}; 1989 1990static const TCGOutOpBinary outop_mulsh = { 1991 .base.static_constraint = C_NotImplemented, 1992}; 1993 1994static void tgen_mulu2(TCGContext *s, TCGType type, 1995 TCGReg rd0, TCGReg rd1, TCGReg rn, TCGReg rm) 1996{ 1997 /* umull */ 1998 tcg_out32(s, (COND_AL << 28) | 0x00800090 | 1999 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); 2000} 2001 2002static const TCGOutOpMul2 outop_mulu2 = { 2003 .base.static_constraint = C_O2_I2(r, r, r, r), 2004 .out_rrrr = tgen_mulu2, 2005}; 2006 2007static const TCGOutOpBinary outop_muluh = { 2008 .base.static_constraint = C_NotImplemented, 2009}; 2010 2011static const TCGOutOpBinary outop_nand = { 2012 .base.static_constraint = C_NotImplemented, 2013}; 2014 2015static const TCGOutOpBinary outop_nor = { 2016 .base.static_constraint = C_NotImplemented, 2017}; 2018 2019static void tgen_or(TCGContext *s, TCGType type, 2020 TCGReg a0, TCGReg a1, TCGReg a2) 2021{ 2022 tcg_out_dat_reg(s, COND_AL, ARITH_ORR, a0, a1, a2, SHIFT_IMM_LSL(0)); 2023} 2024 2025static void tgen_ori(TCGContext *s, TCGType type, 2026 TCGReg a0, TCGReg a1, tcg_target_long a2) 2027{ 2028 tcg_out_dat_imm(s, COND_AL, ARITH_ORR, a0, a1, encode_imm_nofail(a2)); 2029} 2030 2031static const TCGOutOpBinary outop_or = { 2032 .base.static_constraint = C_O1_I2(r, r, rI), 2033 .out_rrr = tgen_or, 2034 .out_rri = tgen_ori, 2035}; 2036 2037static const TCGOutOpBinary outop_orc = { 2038 .base.static_constraint = C_NotImplemented, 2039}; 2040 2041static const TCGOutOpBinary outop_rems = { 2042 .base.static_constraint = C_NotImplemented, 2043}; 2044 2045static const TCGOutOpBinary outop_remu = { 2046 .base.static_constraint = C_NotImplemented, 2047}; 2048 2049static const TCGOutOpBinary outop_rotl = { 2050 .base.static_constraint = C_NotImplemented, 2051}; 2052 2053static void tgen_rotr(TCGContext *s, TCGType type, 2054 TCGReg a0, TCGReg a1, TCGReg a2) 2055{ 2056 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, SHIFT_REG_ROR(a2)); 2057} 2058 2059static void tgen_rotri(TCGContext *s, TCGType type, 2060 TCGReg a0, TCGReg a1, tcg_target_long a2) 2061{ 2062 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, SHIFT_IMM_ROR(a2 & 0x1f)); 2063} 2064 2065static const TCGOutOpBinary outop_rotr = { 2066 .base.static_constraint = C_O1_I2(r, r, ri), 2067 .out_rrr = tgen_rotr, 2068 .out_rri = tgen_rotri, 2069}; 2070 2071static void tgen_sar(TCGContext *s, TCGType type, 2072 TCGReg a0, TCGReg a1, TCGReg a2) 2073{ 2074 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, SHIFT_REG_ASR(a2)); 2075} 2076 2077static void tgen_sari(TCGContext *s, TCGType type, 2078 TCGReg a0, TCGReg a1, tcg_target_long a2) 2079{ 2080 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, 2081 SHIFT_IMM_ASR(a2 & 0x1f)); 2082} 2083 2084static const TCGOutOpBinary outop_sar = { 2085 .base.static_constraint = C_O1_I2(r, r, ri), 2086 .out_rrr = tgen_sar, 2087 .out_rri = tgen_sari, 2088}; 2089 2090static void tgen_shl(TCGContext *s, TCGType type, 2091 TCGReg a0, TCGReg a1, TCGReg a2) 2092{ 2093 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, SHIFT_REG_LSL(a2)); 2094} 2095 2096static void tgen_shli(TCGContext *s, TCGType type, 2097 TCGReg a0, TCGReg a1, tcg_target_long a2) 2098{ 2099 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, 2100 SHIFT_IMM_LSL(a2 & 0x1f)); 2101} 2102 2103static const TCGOutOpBinary outop_shl = { 2104 .base.static_constraint = C_O1_I2(r, r, ri), 2105 .out_rrr = tgen_shl, 2106 .out_rri = tgen_shli, 2107}; 2108 2109static void tgen_shr(TCGContext *s, TCGType type, 2110 TCGReg a0, TCGReg a1, TCGReg a2) 2111{ 2112 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, SHIFT_REG_LSR(a2)); 2113} 2114 2115static void tgen_shri(TCGContext *s, TCGType type, 2116 TCGReg a0, TCGReg a1, tcg_target_long a2) 2117{ 2118 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, 2119 SHIFT_IMM_LSR(a2 & 0x1f)); 2120} 2121 2122static const TCGOutOpBinary outop_shr = { 2123 .base.static_constraint = C_O1_I2(r, r, ri), 2124 .out_rrr = tgen_shr, 2125 .out_rri = tgen_shri, 2126}; 2127 2128static void tgen_sub(TCGContext *s, TCGType type, 2129 TCGReg a0, TCGReg a1, TCGReg a2) 2130{ 2131 tcg_out_dat_reg(s, COND_AL, ARITH_SUB, a0, a1, a2, SHIFT_IMM_LSL(0)); 2132} 2133 2134static void tgen_subfi(TCGContext *s, TCGType type, 2135 TCGReg a0, tcg_target_long a1, TCGReg a2) 2136{ 2137 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, a0, a2, encode_imm_nofail(a1)); 2138} 2139 2140static const TCGOutOpSubtract outop_sub = { 2141 .base.static_constraint = C_O1_I2(r, rI, r), 2142 .out_rrr = tgen_sub, 2143 .out_rir = tgen_subfi, 2144}; 2145 2146static void tgen_xor(TCGContext *s, TCGType type, 2147 TCGReg a0, TCGReg a1, TCGReg a2) 2148{ 2149 tcg_out_dat_reg(s, COND_AL, ARITH_EOR, a0, a1, a2, SHIFT_IMM_LSL(0)); 2150} 2151 2152static void tgen_xori(TCGContext *s, TCGType type, 2153 TCGReg a0, TCGReg a1, tcg_target_long a2) 2154{ 2155 tcg_out_dat_imm(s, COND_AL, ARITH_EOR, a0, a1, encode_imm_nofail(a2)); 2156} 2157 2158static const TCGOutOpBinary outop_xor = { 2159 .base.static_constraint = C_O1_I2(r, r, rI), 2160 .out_rrr = tgen_xor, 2161 .out_rri = tgen_xori, 2162}; 2163 2164static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2165{ 2166 tgen_subfi(s, type, a0, 0, a1); 2167} 2168 2169static const TCGOutOpUnary outop_neg = { 2170 .base.static_constraint = C_O1_I1(r, r), 2171 .out_rr = tgen_neg, 2172}; 2173 2174static void tgen_not(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2175{ 2176 tcg_out_dat_reg(s, COND_AL, ARITH_MVN, a0, 0, a1, SHIFT_IMM_LSL(0)); 2177} 2178 2179static const TCGOutOpUnary outop_not = { 2180 .base.static_constraint = C_O1_I1(r, r), 2181 .out_rr = tgen_not, 2182}; 2183 2184static void finish_setcond(TCGContext *s, TCGCond cond, TCGReg ret, bool neg) 2185{ 2186 tcg_out_movi32(s, tcg_cond_to_arm_cond[tcg_invert_cond(cond)], ret, 0); 2187 tcg_out_movi32(s, tcg_cond_to_arm_cond[cond], ret, neg ? -1 : 1); 2188} 2189 2190static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, 2191 TCGReg a0, TCGReg a1, TCGReg a2) 2192{ 2193 cond = tgen_cmp(s, cond, a1, a2); 2194 finish_setcond(s, cond, a0, false); 2195} 2196 2197static void tgen_setcondi(TCGContext *s, TCGType type, TCGCond cond, 2198 TCGReg a0, TCGReg a1, tcg_target_long a2) 2199{ 2200 cond = tgen_cmpi(s, cond, a1, a2); 2201 finish_setcond(s, cond, a0, false); 2202} 2203 2204static const TCGOutOpSetcond outop_setcond = { 2205 .base.static_constraint = C_O1_I2(r, r, rIN), 2206 .out_rrr = tgen_setcond, 2207 .out_rri = tgen_setcondi, 2208}; 2209 2210static void tgen_negsetcond(TCGContext *s, TCGType type, TCGCond cond, 2211 TCGReg a0, TCGReg a1, TCGReg a2) 2212{ 2213 cond = tgen_cmp(s, cond, a1, a2); 2214 finish_setcond(s, cond, a0, true); 2215} 2216 2217static void tgen_negsetcondi(TCGContext *s, TCGType type, TCGCond cond, 2218 TCGReg a0, TCGReg a1, tcg_target_long a2) 2219{ 2220 cond = tgen_cmpi(s, cond, a1, a2); 2221 finish_setcond(s, cond, a0, true); 2222} 2223 2224static const TCGOutOpSetcond outop_negsetcond = { 2225 .base.static_constraint = C_O1_I2(r, r, rIN), 2226 .out_rrr = tgen_negsetcond, 2227 .out_rri = tgen_negsetcondi, 2228}; 2229 2230 2231static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, 2232 const TCGArg args[TCG_MAX_OP_ARGS], 2233 const int const_args[TCG_MAX_OP_ARGS]) 2234{ 2235 TCGArg a0, a1, a2, a3, a4, a5; 2236 int c; 2237 2238 switch (opc) { 2239 case INDEX_op_goto_ptr: 2240 tcg_out_b_reg(s, COND_AL, args[0]); 2241 break; 2242 case INDEX_op_br: 2243 tcg_out_goto_label(s, COND_AL, arg_label(args[0])); 2244 break; 2245 2246 case INDEX_op_ld8u_i32: 2247 tcg_out_ld8u(s, COND_AL, args[0], args[1], args[2]); 2248 break; 2249 case INDEX_op_ld8s_i32: 2250 tcg_out_ld8s(s, COND_AL, args[0], args[1], args[2]); 2251 break; 2252 case INDEX_op_ld16u_i32: 2253 tcg_out_ld16u(s, COND_AL, args[0], args[1], args[2]); 2254 break; 2255 case INDEX_op_ld16s_i32: 2256 tcg_out_ld16s(s, COND_AL, args[0], args[1], args[2]); 2257 break; 2258 case INDEX_op_ld_i32: 2259 tcg_out_ld32u(s, COND_AL, args[0], args[1], args[2]); 2260 break; 2261 case INDEX_op_st8_i32: 2262 tcg_out_st8(s, COND_AL, args[0], args[1], args[2]); 2263 break; 2264 case INDEX_op_st16_i32: 2265 tcg_out_st16(s, COND_AL, args[0], args[1], args[2]); 2266 break; 2267 case INDEX_op_st_i32: 2268 tcg_out_st32(s, COND_AL, args[0], args[1], args[2]); 2269 break; 2270 2271 case INDEX_op_movcond_i32: 2272 /* Constraints mean that v2 is always in the same register as dest, 2273 * so we only need to do "if condition passed, move v1 to dest". 2274 */ 2275 c = tcg_out_cmp(s, args[5], args[1], args[2], const_args[2]); 2276 tcg_out_dat_rIK(s, tcg_cond_to_arm_cond[c], ARITH_MOV, 2277 ARITH_MVN, args[0], 0, args[3], const_args[3]); 2278 break; 2279 case INDEX_op_add2_i32: 2280 a0 = args[0], a1 = args[1], a2 = args[2]; 2281 a3 = args[3], a4 = args[4], a5 = args[5]; 2282 if (a0 == a3 || (a0 == a5 && !const_args[5])) { 2283 a0 = TCG_REG_TMP; 2284 } 2285 tcg_out_dat_rIN(s, COND_AL, ARITH_ADD | TO_CPSR, ARITH_SUB | TO_CPSR, 2286 a0, a2, a4, const_args[4]); 2287 tcg_out_dat_rIK(s, COND_AL, ARITH_ADC, ARITH_SBC, 2288 a1, a3, a5, const_args[5]); 2289 tcg_out_mov_reg(s, COND_AL, args[0], a0); 2290 break; 2291 case INDEX_op_sub2_i32: 2292 a0 = args[0], a1 = args[1], a2 = args[2]; 2293 a3 = args[3], a4 = args[4], a5 = args[5]; 2294 if ((a0 == a3 && !const_args[3]) || (a0 == a5 && !const_args[5])) { 2295 a0 = TCG_REG_TMP; 2296 } 2297 if (const_args[2]) { 2298 if (const_args[4]) { 2299 tcg_out_movi32(s, COND_AL, a0, a4); 2300 a4 = a0; 2301 } 2302 tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR, a0, a4, a2, 1); 2303 } else { 2304 tcg_out_dat_rIN(s, COND_AL, ARITH_SUB | TO_CPSR, 2305 ARITH_ADD | TO_CPSR, a0, a2, a4, const_args[4]); 2306 } 2307 if (const_args[3]) { 2308 if (const_args[5]) { 2309 tcg_out_movi32(s, COND_AL, a1, a5); 2310 a5 = a1; 2311 } 2312 tcg_out_dat_rI(s, COND_AL, ARITH_RSC, a1, a5, a3, 1); 2313 } else { 2314 tcg_out_dat_rIK(s, COND_AL, ARITH_SBC, ARITH_ADC, 2315 a1, a3, a5, const_args[5]); 2316 } 2317 tcg_out_mov_reg(s, COND_AL, args[0], a0); 2318 break; 2319 2320 case INDEX_op_brcond_i32: 2321 c = tcg_out_cmp(s, args[2], args[0], args[1], const_args[1]); 2322 tcg_out_goto_label(s, tcg_cond_to_arm_cond[c], arg_label(args[3])); 2323 break; 2324 2325 case INDEX_op_brcond2_i32: 2326 c = tcg_out_cmp2(s, args, const_args); 2327 tcg_out_goto_label(s, tcg_cond_to_arm_cond[c], arg_label(args[5])); 2328 break; 2329 case INDEX_op_setcond2_i32: 2330 c = tcg_out_cmp2(s, args + 1, const_args + 1); 2331 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[c], ARITH_MOV, args[0], 0, 1); 2332 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(c)], 2333 ARITH_MOV, args[0], 0, 0); 2334 break; 2335 2336 case INDEX_op_qemu_ld_i32: 2337 tcg_out_qemu_ld(s, args[0], -1, args[1], args[2], TCG_TYPE_I32); 2338 break; 2339 case INDEX_op_qemu_ld_i64: 2340 tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3], TCG_TYPE_I64); 2341 break; 2342 2343 case INDEX_op_qemu_st_i32: 2344 tcg_out_qemu_st(s, args[0], -1, args[1], args[2], TCG_TYPE_I32); 2345 break; 2346 case INDEX_op_qemu_st_i64: 2347 tcg_out_qemu_st(s, args[0], args[1], args[2], args[3], TCG_TYPE_I64); 2348 break; 2349 2350 case INDEX_op_bswap16_i32: 2351 tcg_out_bswap16(s, COND_AL, args[0], args[1], args[2]); 2352 break; 2353 case INDEX_op_bswap32_i32: 2354 tcg_out_bswap32(s, COND_AL, args[0], args[1]); 2355 break; 2356 2357 case INDEX_op_deposit_i32: 2358 tcg_out_deposit(s, COND_AL, args[0], args[2], 2359 args[3], args[4], const_args[2]); 2360 break; 2361 case INDEX_op_extract_i32: 2362 tcg_out_extract(s, COND_AL, args[0], args[1], args[2], args[3]); 2363 break; 2364 case INDEX_op_sextract_i32: 2365 tcg_out_sextract(s, COND_AL, args[0], args[1], args[2], args[3]); 2366 break; 2367 case INDEX_op_extract2_i32: 2368 /* ??? These optimization vs zero should be generic. */ 2369 /* ??? But we can't substitute 2 for 1 in the opcode stream yet. */ 2370 if (const_args[1]) { 2371 if (const_args[2]) { 2372 tcg_out_movi(s, TCG_TYPE_REG, args[0], 0); 2373 } else { 2374 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, 2375 args[2], SHIFT_IMM_LSL(32 - args[3])); 2376 } 2377 } else if (const_args[2]) { 2378 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, 2379 args[1], SHIFT_IMM_LSR(args[3])); 2380 } else { 2381 /* We can do extract2 in 2 insns, vs the 3 required otherwise. */ 2382 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, 2383 args[2], SHIFT_IMM_LSL(32 - args[3])); 2384 tcg_out_dat_reg(s, COND_AL, ARITH_ORR, args[0], TCG_REG_TMP, 2385 args[1], SHIFT_IMM_LSR(args[3])); 2386 } 2387 break; 2388 2389 case INDEX_op_mb: 2390 tcg_out_mb(s, args[0]); 2391 break; 2392 2393 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2394 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2395 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2396 default: 2397 g_assert_not_reached(); 2398 } 2399} 2400 2401static TCGConstraintSetIndex 2402tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) 2403{ 2404 switch (op) { 2405 case INDEX_op_goto_ptr: 2406 return C_O0_I1(r); 2407 2408 case INDEX_op_ld8u_i32: 2409 case INDEX_op_ld8s_i32: 2410 case INDEX_op_ld16u_i32: 2411 case INDEX_op_ld16s_i32: 2412 case INDEX_op_ld_i32: 2413 case INDEX_op_bswap16_i32: 2414 case INDEX_op_bswap32_i32: 2415 case INDEX_op_extract_i32: 2416 case INDEX_op_sextract_i32: 2417 return C_O1_I1(r, r); 2418 2419 case INDEX_op_st8_i32: 2420 case INDEX_op_st16_i32: 2421 case INDEX_op_st_i32: 2422 return C_O0_I2(r, r); 2423 2424 case INDEX_op_brcond_i32: 2425 return C_O0_I2(r, rIN); 2426 case INDEX_op_deposit_i32: 2427 return C_O1_I2(r, 0, rZ); 2428 case INDEX_op_extract2_i32: 2429 return C_O1_I2(r, rZ, rZ); 2430 case INDEX_op_movcond_i32: 2431 return C_O1_I4(r, r, rIN, rIK, 0); 2432 case INDEX_op_add2_i32: 2433 return C_O2_I4(r, r, r, r, rIN, rIK); 2434 case INDEX_op_sub2_i32: 2435 return C_O2_I4(r, r, rI, rI, rIN, rIK); 2436 case INDEX_op_brcond2_i32: 2437 return C_O0_I4(r, r, rI, rI); 2438 case INDEX_op_setcond2_i32: 2439 return C_O1_I4(r, r, r, rI, rI); 2440 2441 case INDEX_op_qemu_ld_i32: 2442 return C_O1_I1(r, q); 2443 case INDEX_op_qemu_ld_i64: 2444 return C_O2_I1(e, p, q); 2445 case INDEX_op_qemu_st_i32: 2446 return C_O0_I2(q, q); 2447 case INDEX_op_qemu_st_i64: 2448 return C_O0_I3(Q, p, q); 2449 2450 case INDEX_op_st_vec: 2451 return C_O0_I2(w, r); 2452 case INDEX_op_ld_vec: 2453 case INDEX_op_dupm_vec: 2454 return C_O1_I1(w, r); 2455 case INDEX_op_dup_vec: 2456 return C_O1_I1(w, wr); 2457 case INDEX_op_abs_vec: 2458 case INDEX_op_neg_vec: 2459 case INDEX_op_not_vec: 2460 case INDEX_op_shli_vec: 2461 case INDEX_op_shri_vec: 2462 case INDEX_op_sari_vec: 2463 return C_O1_I1(w, w); 2464 case INDEX_op_dup2_vec: 2465 case INDEX_op_add_vec: 2466 case INDEX_op_mul_vec: 2467 case INDEX_op_smax_vec: 2468 case INDEX_op_smin_vec: 2469 case INDEX_op_ssadd_vec: 2470 case INDEX_op_sssub_vec: 2471 case INDEX_op_sub_vec: 2472 case INDEX_op_umax_vec: 2473 case INDEX_op_umin_vec: 2474 case INDEX_op_usadd_vec: 2475 case INDEX_op_ussub_vec: 2476 case INDEX_op_xor_vec: 2477 case INDEX_op_arm_sshl_vec: 2478 case INDEX_op_arm_ushl_vec: 2479 return C_O1_I2(w, w, w); 2480 case INDEX_op_arm_sli_vec: 2481 return C_O1_I2(w, 0, w); 2482 case INDEX_op_or_vec: 2483 case INDEX_op_andc_vec: 2484 return C_O1_I2(w, w, wO); 2485 case INDEX_op_and_vec: 2486 case INDEX_op_orc_vec: 2487 return C_O1_I2(w, w, wV); 2488 case INDEX_op_cmp_vec: 2489 return C_O1_I2(w, w, wZ); 2490 case INDEX_op_bitsel_vec: 2491 return C_O1_I3(w, w, w, w); 2492 default: 2493 return C_NotImplemented; 2494 } 2495} 2496 2497static void tcg_target_init(TCGContext *s) 2498{ 2499 /* 2500 * Only probe for the platform and capabilities if we haven't already 2501 * determined maximum values at compile time. 2502 */ 2503#if !defined(use_idiv_instructions) || !defined(use_neon_instructions) 2504 { 2505 unsigned long hwcap = qemu_getauxval(AT_HWCAP); 2506#ifndef use_idiv_instructions 2507 use_idiv_instructions = (hwcap & HWCAP_ARM_IDIVA) != 0; 2508#endif 2509#ifndef use_neon_instructions 2510 use_neon_instructions = (hwcap & HWCAP_ARM_NEON) != 0; 2511#endif 2512 } 2513#endif 2514 2515 if (__ARM_ARCH < 7) { 2516 const char *pl = (const char *)qemu_getauxval(AT_PLATFORM); 2517 if (pl != NULL && pl[0] == 'v' && pl[1] >= '4' && pl[1] <= '9') { 2518 arm_arch = pl[1] - '0'; 2519 } 2520 2521 if (arm_arch < 6) { 2522 error_report("TCG: ARMv%d is unsupported; exiting", arm_arch); 2523 exit(EXIT_FAILURE); 2524 } 2525 } 2526 2527 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS; 2528 2529 tcg_target_call_clobber_regs = 0; 2530 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); 2531 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1); 2532 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2); 2533 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3); 2534 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12); 2535 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14); 2536 2537 if (use_neon_instructions) { 2538 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS; 2539 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS; 2540 2541 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q0); 2542 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q1); 2543 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q2); 2544 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q3); 2545 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q8); 2546 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q9); 2547 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q10); 2548 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q11); 2549 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q12); 2550 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q13); 2551 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q14); 2552 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q15); 2553 } 2554 2555 s->reserved_regs = 0; 2556 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); 2557 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP); 2558 tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC); 2559 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP); 2560} 2561 2562static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 2563 TCGReg arg1, intptr_t arg2) 2564{ 2565 switch (type) { 2566 case TCG_TYPE_I32: 2567 tcg_out_ld32u(s, COND_AL, arg, arg1, arg2); 2568 return; 2569 case TCG_TYPE_V64: 2570 /* regs 1; size 8; align 8 */ 2571 tcg_out_vldst(s, INSN_VLD1 | 0x7d0, arg, arg1, arg2); 2572 return; 2573 case TCG_TYPE_V128: 2574 /* 2575 * We have only 8-byte alignment for the stack per the ABI. 2576 * Rather than dynamically re-align the stack, it's easier 2577 * to simply not request alignment beyond that. So: 2578 * regs 2; size 8; align 8 2579 */ 2580 tcg_out_vldst(s, INSN_VLD1 | 0xad0, arg, arg1, arg2); 2581 return; 2582 default: 2583 g_assert_not_reached(); 2584 } 2585} 2586 2587static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 2588 TCGReg arg1, intptr_t arg2) 2589{ 2590 switch (type) { 2591 case TCG_TYPE_I32: 2592 tcg_out_st32(s, COND_AL, arg, arg1, arg2); 2593 return; 2594 case TCG_TYPE_V64: 2595 /* regs 1; size 8; align 8 */ 2596 tcg_out_vldst(s, INSN_VST1 | 0x7d0, arg, arg1, arg2); 2597 return; 2598 case TCG_TYPE_V128: 2599 /* See tcg_out_ld re alignment: regs 2; size 8; align 8 */ 2600 tcg_out_vldst(s, INSN_VST1 | 0xad0, arg, arg1, arg2); 2601 return; 2602 default: 2603 g_assert_not_reached(); 2604 } 2605} 2606 2607static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 2608 TCGReg base, intptr_t ofs) 2609{ 2610 return false; 2611} 2612 2613static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 2614{ 2615 if (ret == arg) { 2616 return true; 2617 } 2618 switch (type) { 2619 case TCG_TYPE_I32: 2620 if (ret < TCG_REG_Q0 && arg < TCG_REG_Q0) { 2621 tcg_out_mov_reg(s, COND_AL, ret, arg); 2622 return true; 2623 } 2624 return false; 2625 2626 case TCG_TYPE_V64: 2627 case TCG_TYPE_V128: 2628 /* "VMOV D,N" is an alias for "VORR D,N,N". */ 2629 tcg_out_vreg3(s, INSN_VORR, type - TCG_TYPE_V64, 0, ret, arg, arg); 2630 return true; 2631 2632 default: 2633 g_assert_not_reached(); 2634 } 2635} 2636 2637static void tcg_out_movi(TCGContext *s, TCGType type, 2638 TCGReg ret, tcg_target_long arg) 2639{ 2640 tcg_debug_assert(type == TCG_TYPE_I32); 2641 tcg_debug_assert(ret < TCG_REG_Q0); 2642 tcg_out_movi32(s, COND_AL, ret, arg); 2643} 2644 2645static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 2646{ 2647 return false; 2648} 2649 2650static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 2651 tcg_target_long imm) 2652{ 2653 int enc, opc = ARITH_ADD; 2654 2655 /* All of the easiest immediates to encode are positive. */ 2656 if (imm < 0) { 2657 imm = -imm; 2658 opc = ARITH_SUB; 2659 } 2660 enc = encode_imm(imm); 2661 if (enc >= 0) { 2662 tcg_out_dat_imm(s, COND_AL, opc, rd, rs, enc); 2663 } else { 2664 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, imm); 2665 tcg_out_dat_reg(s, COND_AL, opc, rd, rs, 2666 TCG_REG_TMP, SHIFT_IMM_LSL(0)); 2667 } 2668} 2669 2670/* Type is always V128, with I64 elements. */ 2671static void tcg_out_dup2_vec(TCGContext *s, TCGReg rd, TCGReg rl, TCGReg rh) 2672{ 2673 /* Move high element into place first. */ 2674 /* VMOV Dd+1, Ds */ 2675 tcg_out_vreg3(s, INSN_VORR | (1 << 12), 0, 0, rd, rh, rh); 2676 /* Move low element into place; tcg_out_mov will check for nop. */ 2677 tcg_out_mov(s, TCG_TYPE_V64, rd, rl); 2678} 2679 2680static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 2681 TCGReg rd, TCGReg rs) 2682{ 2683 int q = type - TCG_TYPE_V64; 2684 2685 if (vece == MO_64) { 2686 if (type == TCG_TYPE_V128) { 2687 tcg_out_dup2_vec(s, rd, rs, rs); 2688 } else { 2689 tcg_out_mov(s, TCG_TYPE_V64, rd, rs); 2690 } 2691 } else if (rs < TCG_REG_Q0) { 2692 int b = (vece == MO_8); 2693 int e = (vece == MO_16); 2694 tcg_out32(s, INSN_VDUP_G | (b << 22) | (q << 21) | (e << 5) | 2695 encode_vn(rd) | (rs << 12)); 2696 } else { 2697 int imm4 = 1 << vece; 2698 tcg_out32(s, INSN_VDUP_S | (imm4 << 16) | (q << 6) | 2699 encode_vd(rd) | encode_vm(rs)); 2700 } 2701 return true; 2702} 2703 2704static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 2705 TCGReg rd, TCGReg base, intptr_t offset) 2706{ 2707 if (vece == MO_64) { 2708 tcg_out_ld(s, TCG_TYPE_V64, rd, base, offset); 2709 if (type == TCG_TYPE_V128) { 2710 tcg_out_dup2_vec(s, rd, rd, rd); 2711 } 2712 } else { 2713 int q = type - TCG_TYPE_V64; 2714 tcg_out_vldst(s, INSN_VLD1R | (vece << 6) | (q << 5), 2715 rd, base, offset); 2716 } 2717 return true; 2718} 2719 2720static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 2721 TCGReg rd, int64_t v64) 2722{ 2723 int q = type - TCG_TYPE_V64; 2724 int cmode, imm8, i; 2725 2726 /* Test all bytes equal first. */ 2727 if (vece == MO_8) { 2728 tcg_out_vmovi(s, rd, q, 0, 0xe, v64); 2729 return; 2730 } 2731 2732 /* 2733 * Test all bytes 0x00 or 0xff second. This can match cases that 2734 * might otherwise take 2 or 3 insns for MO_16 or MO_32 below. 2735 */ 2736 for (i = imm8 = 0; i < 8; i++) { 2737 uint8_t byte = v64 >> (i * 8); 2738 if (byte == 0xff) { 2739 imm8 |= 1 << i; 2740 } else if (byte != 0) { 2741 goto fail_bytes; 2742 } 2743 } 2744 tcg_out_vmovi(s, rd, q, 1, 0xe, imm8); 2745 return; 2746 fail_bytes: 2747 2748 /* 2749 * Tests for various replications. For each element width, if we 2750 * cannot find an expansion there's no point checking a larger 2751 * width because we already know by replication it cannot match. 2752 */ 2753 if (vece == MO_16) { 2754 uint16_t v16 = v64; 2755 2756 if (is_shimm16(v16, &cmode, &imm8)) { 2757 tcg_out_vmovi(s, rd, q, 0, cmode, imm8); 2758 return; 2759 } 2760 if (is_shimm16(~v16, &cmode, &imm8)) { 2761 tcg_out_vmovi(s, rd, q, 1, cmode, imm8); 2762 return; 2763 } 2764 2765 /* 2766 * Otherwise, all remaining constants can be loaded in two insns: 2767 * rd = v16 & 0xff, rd |= v16 & 0xff00. 2768 */ 2769 tcg_out_vmovi(s, rd, q, 0, 0x8, v16 & 0xff); 2770 tcg_out_vmovi(s, rd, q, 0, 0xb, v16 >> 8); /* VORRI */ 2771 return; 2772 } 2773 2774 if (vece == MO_32) { 2775 uint32_t v32 = v64; 2776 2777 if (is_shimm32(v32, &cmode, &imm8) || 2778 is_soimm32(v32, &cmode, &imm8)) { 2779 tcg_out_vmovi(s, rd, q, 0, cmode, imm8); 2780 return; 2781 } 2782 if (is_shimm32(~v32, &cmode, &imm8) || 2783 is_soimm32(~v32, &cmode, &imm8)) { 2784 tcg_out_vmovi(s, rd, q, 1, cmode, imm8); 2785 return; 2786 } 2787 2788 /* 2789 * Restrict the set of constants to those we can load with 2790 * two instructions. Others we load from the pool. 2791 */ 2792 i = is_shimm32_pair(v32, &cmode, &imm8); 2793 if (i) { 2794 tcg_out_vmovi(s, rd, q, 0, cmode, imm8); 2795 tcg_out_vmovi(s, rd, q, 0, i | 1, extract32(v32, i * 4, 8)); 2796 return; 2797 } 2798 i = is_shimm32_pair(~v32, &cmode, &imm8); 2799 if (i) { 2800 tcg_out_vmovi(s, rd, q, 1, cmode, imm8); 2801 tcg_out_vmovi(s, rd, q, 1, i | 1, extract32(~v32, i * 4, 8)); 2802 return; 2803 } 2804 } 2805 2806 /* 2807 * As a last resort, load from the constant pool. 2808 */ 2809 if (!q || vece == MO_64) { 2810 new_pool_l2(s, R_ARM_PC11, s->code_ptr, 0, v64, v64 >> 32); 2811 /* VLDR Dd, [pc + offset] */ 2812 tcg_out32(s, INSN_VLDR_D | encode_vd(rd) | (0xf << 16)); 2813 if (q) { 2814 tcg_out_dup2_vec(s, rd, rd, rd); 2815 } 2816 } else { 2817 new_pool_label(s, (uint32_t)v64, R_ARM_PC8, s->code_ptr, 0); 2818 /* add tmp, pc, offset */ 2819 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_TMP, TCG_REG_PC, 0); 2820 tcg_out_dupm_vec(s, type, MO_32, rd, TCG_REG_TMP, 0); 2821 } 2822} 2823 2824static const ARMInsn vec_cmp_insn[16] = { 2825 [TCG_COND_EQ] = INSN_VCEQ, 2826 [TCG_COND_GT] = INSN_VCGT, 2827 [TCG_COND_GE] = INSN_VCGE, 2828 [TCG_COND_GTU] = INSN_VCGT_U, 2829 [TCG_COND_GEU] = INSN_VCGE_U, 2830}; 2831 2832static const ARMInsn vec_cmp0_insn[16] = { 2833 [TCG_COND_EQ] = INSN_VCEQ0, 2834 [TCG_COND_GT] = INSN_VCGT0, 2835 [TCG_COND_GE] = INSN_VCGE0, 2836 [TCG_COND_LT] = INSN_VCLT0, 2837 [TCG_COND_LE] = INSN_VCLE0, 2838}; 2839 2840static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 2841 unsigned vecl, unsigned vece, 2842 const TCGArg args[TCG_MAX_OP_ARGS], 2843 const int const_args[TCG_MAX_OP_ARGS]) 2844{ 2845 TCGType type = vecl + TCG_TYPE_V64; 2846 unsigned q = vecl; 2847 TCGArg a0, a1, a2, a3; 2848 int cmode, imm8; 2849 2850 a0 = args[0]; 2851 a1 = args[1]; 2852 a2 = args[2]; 2853 2854 switch (opc) { 2855 case INDEX_op_ld_vec: 2856 tcg_out_ld(s, type, a0, a1, a2); 2857 return; 2858 case INDEX_op_st_vec: 2859 tcg_out_st(s, type, a0, a1, a2); 2860 return; 2861 case INDEX_op_dupm_vec: 2862 tcg_out_dupm_vec(s, type, vece, a0, a1, a2); 2863 return; 2864 case INDEX_op_dup2_vec: 2865 tcg_out_dup2_vec(s, a0, a1, a2); 2866 return; 2867 case INDEX_op_abs_vec: 2868 tcg_out_vreg2(s, INSN_VABS, q, vece, a0, a1); 2869 return; 2870 case INDEX_op_neg_vec: 2871 tcg_out_vreg2(s, INSN_VNEG, q, vece, a0, a1); 2872 return; 2873 case INDEX_op_not_vec: 2874 tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a1); 2875 return; 2876 case INDEX_op_add_vec: 2877 tcg_out_vreg3(s, INSN_VADD, q, vece, a0, a1, a2); 2878 return; 2879 case INDEX_op_mul_vec: 2880 tcg_out_vreg3(s, INSN_VMUL, q, vece, a0, a1, a2); 2881 return; 2882 case INDEX_op_smax_vec: 2883 tcg_out_vreg3(s, INSN_VMAX, q, vece, a0, a1, a2); 2884 return; 2885 case INDEX_op_smin_vec: 2886 tcg_out_vreg3(s, INSN_VMIN, q, vece, a0, a1, a2); 2887 return; 2888 case INDEX_op_sub_vec: 2889 tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2); 2890 return; 2891 case INDEX_op_ssadd_vec: 2892 tcg_out_vreg3(s, INSN_VQADD, q, vece, a0, a1, a2); 2893 return; 2894 case INDEX_op_sssub_vec: 2895 tcg_out_vreg3(s, INSN_VQSUB, q, vece, a0, a1, a2); 2896 return; 2897 case INDEX_op_umax_vec: 2898 tcg_out_vreg3(s, INSN_VMAX_U, q, vece, a0, a1, a2); 2899 return; 2900 case INDEX_op_umin_vec: 2901 tcg_out_vreg3(s, INSN_VMIN_U, q, vece, a0, a1, a2); 2902 return; 2903 case INDEX_op_usadd_vec: 2904 tcg_out_vreg3(s, INSN_VQADD_U, q, vece, a0, a1, a2); 2905 return; 2906 case INDEX_op_ussub_vec: 2907 tcg_out_vreg3(s, INSN_VQSUB_U, q, vece, a0, a1, a2); 2908 return; 2909 case INDEX_op_xor_vec: 2910 tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2); 2911 return; 2912 case INDEX_op_arm_sshl_vec: 2913 /* 2914 * Note that Vm is the data and Vn is the shift count, 2915 * therefore the arguments appear reversed. 2916 */ 2917 tcg_out_vreg3(s, INSN_VSHL_S, q, vece, a0, a2, a1); 2918 return; 2919 case INDEX_op_arm_ushl_vec: 2920 /* See above. */ 2921 tcg_out_vreg3(s, INSN_VSHL_U, q, vece, a0, a2, a1); 2922 return; 2923 case INDEX_op_shli_vec: 2924 tcg_out_vshifti(s, INSN_VSHLI, q, a0, a1, a2 + (8 << vece)); 2925 return; 2926 case INDEX_op_shri_vec: 2927 tcg_out_vshifti(s, INSN_VSHRI, q, a0, a1, (16 << vece) - a2); 2928 return; 2929 case INDEX_op_sari_vec: 2930 tcg_out_vshifti(s, INSN_VSARI, q, a0, a1, (16 << vece) - a2); 2931 return; 2932 case INDEX_op_arm_sli_vec: 2933 tcg_out_vshifti(s, INSN_VSLI, q, a0, a2, args[3] + (8 << vece)); 2934 return; 2935 2936 case INDEX_op_andc_vec: 2937 if (!const_args[2]) { 2938 tcg_out_vreg3(s, INSN_VBIC, q, 0, a0, a1, a2); 2939 return; 2940 } 2941 a2 = ~a2; 2942 /* fall through */ 2943 case INDEX_op_and_vec: 2944 if (const_args[2]) { 2945 is_shimm1632(~a2, &cmode, &imm8); 2946 if (a0 == a1) { 2947 tcg_out_vmovi(s, a0, q, 1, cmode | 1, imm8); /* VBICI */ 2948 return; 2949 } 2950 tcg_out_vmovi(s, a0, q, 1, cmode, imm8); /* VMVNI */ 2951 a2 = a0; 2952 } 2953 tcg_out_vreg3(s, INSN_VAND, q, 0, a0, a1, a2); 2954 return; 2955 2956 case INDEX_op_orc_vec: 2957 if (!const_args[2]) { 2958 tcg_out_vreg3(s, INSN_VORN, q, 0, a0, a1, a2); 2959 return; 2960 } 2961 a2 = ~a2; 2962 /* fall through */ 2963 case INDEX_op_or_vec: 2964 if (const_args[2]) { 2965 is_shimm1632(a2, &cmode, &imm8); 2966 if (a0 == a1) { 2967 tcg_out_vmovi(s, a0, q, 0, cmode | 1, imm8); /* VORRI */ 2968 return; 2969 } 2970 tcg_out_vmovi(s, a0, q, 0, cmode, imm8); /* VMOVI */ 2971 a2 = a0; 2972 } 2973 tcg_out_vreg3(s, INSN_VORR, q, 0, a0, a1, a2); 2974 return; 2975 2976 case INDEX_op_cmp_vec: 2977 { 2978 TCGCond cond = args[3]; 2979 ARMInsn insn; 2980 2981 switch (cond) { 2982 case TCG_COND_NE: 2983 if (const_args[2]) { 2984 tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a1); 2985 } else { 2986 tcg_out_vreg3(s, INSN_VCEQ, q, vece, a0, a1, a2); 2987 tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0); 2988 } 2989 break; 2990 2991 case TCG_COND_TSTNE: 2992 case TCG_COND_TSTEQ: 2993 if (const_args[2]) { 2994 /* (x & 0) == 0 */ 2995 tcg_out_dupi_vec(s, type, MO_8, a0, 2996 -(cond == TCG_COND_TSTEQ)); 2997 break; 2998 } 2999 tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a2); 3000 if (cond == TCG_COND_TSTEQ) { 3001 tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0); 3002 } 3003 break; 3004 3005 default: 3006 if (const_args[2]) { 3007 insn = vec_cmp0_insn[cond]; 3008 if (insn) { 3009 tcg_out_vreg2(s, insn, q, vece, a0, a1); 3010 return; 3011 } 3012 tcg_out_dupi_vec(s, type, MO_8, TCG_VEC_TMP, 0); 3013 a2 = TCG_VEC_TMP; 3014 } 3015 insn = vec_cmp_insn[cond]; 3016 if (insn == 0) { 3017 TCGArg t; 3018 t = a1, a1 = a2, a2 = t; 3019 cond = tcg_swap_cond(cond); 3020 insn = vec_cmp_insn[cond]; 3021 tcg_debug_assert(insn != 0); 3022 } 3023 tcg_out_vreg3(s, insn, q, vece, a0, a1, a2); 3024 break; 3025 } 3026 } 3027 return; 3028 3029 case INDEX_op_bitsel_vec: 3030 a3 = args[3]; 3031 if (a0 == a3) { 3032 tcg_out_vreg3(s, INSN_VBIT, q, 0, a0, a2, a1); 3033 } else if (a0 == a2) { 3034 tcg_out_vreg3(s, INSN_VBIF, q, 0, a0, a3, a1); 3035 } else { 3036 tcg_out_mov(s, type, a0, a1); 3037 tcg_out_vreg3(s, INSN_VBSL, q, 0, a0, a2, a3); 3038 } 3039 return; 3040 3041 case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ 3042 case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ 3043 default: 3044 g_assert_not_reached(); 3045 } 3046} 3047 3048int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 3049{ 3050 switch (opc) { 3051 case INDEX_op_add_vec: 3052 case INDEX_op_sub_vec: 3053 case INDEX_op_and_vec: 3054 case INDEX_op_andc_vec: 3055 case INDEX_op_or_vec: 3056 case INDEX_op_orc_vec: 3057 case INDEX_op_xor_vec: 3058 case INDEX_op_not_vec: 3059 case INDEX_op_shli_vec: 3060 case INDEX_op_shri_vec: 3061 case INDEX_op_sari_vec: 3062 case INDEX_op_ssadd_vec: 3063 case INDEX_op_sssub_vec: 3064 case INDEX_op_usadd_vec: 3065 case INDEX_op_ussub_vec: 3066 case INDEX_op_bitsel_vec: 3067 return 1; 3068 case INDEX_op_abs_vec: 3069 case INDEX_op_cmp_vec: 3070 case INDEX_op_mul_vec: 3071 case INDEX_op_neg_vec: 3072 case INDEX_op_smax_vec: 3073 case INDEX_op_smin_vec: 3074 case INDEX_op_umax_vec: 3075 case INDEX_op_umin_vec: 3076 return vece < MO_64; 3077 case INDEX_op_shlv_vec: 3078 case INDEX_op_shrv_vec: 3079 case INDEX_op_sarv_vec: 3080 case INDEX_op_rotli_vec: 3081 case INDEX_op_rotlv_vec: 3082 case INDEX_op_rotrv_vec: 3083 return -1; 3084 default: 3085 return 0; 3086 } 3087} 3088 3089void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 3090 TCGArg a0, ...) 3091{ 3092 va_list va; 3093 TCGv_vec v0, v1, v2, t1, t2, c1; 3094 TCGArg a2; 3095 3096 va_start(va, a0); 3097 v0 = temp_tcgv_vec(arg_temp(a0)); 3098 v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 3099 a2 = va_arg(va, TCGArg); 3100 va_end(va); 3101 3102 switch (opc) { 3103 case INDEX_op_shlv_vec: 3104 /* 3105 * Merely propagate shlv_vec to arm_ushl_vec. 3106 * In this way we don't set TCG_TARGET_HAS_shv_vec 3107 * because everything is done via expansion. 3108 */ 3109 v2 = temp_tcgv_vec(arg_temp(a2)); 3110 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0), 3111 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 3112 break; 3113 3114 case INDEX_op_shrv_vec: 3115 case INDEX_op_sarv_vec: 3116 /* Right shifts are negative left shifts for NEON. */ 3117 v2 = temp_tcgv_vec(arg_temp(a2)); 3118 t1 = tcg_temp_new_vec(type); 3119 tcg_gen_neg_vec(vece, t1, v2); 3120 if (opc == INDEX_op_shrv_vec) { 3121 opc = INDEX_op_arm_ushl_vec; 3122 } else { 3123 opc = INDEX_op_arm_sshl_vec; 3124 } 3125 vec_gen_3(opc, type, vece, tcgv_vec_arg(v0), 3126 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 3127 tcg_temp_free_vec(t1); 3128 break; 3129 3130 case INDEX_op_rotli_vec: 3131 t1 = tcg_temp_new_vec(type); 3132 tcg_gen_shri_vec(vece, t1, v1, -a2 & ((8 << vece) - 1)); 3133 vec_gen_4(INDEX_op_arm_sli_vec, type, vece, 3134 tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(v1), a2); 3135 tcg_temp_free_vec(t1); 3136 break; 3137 3138 case INDEX_op_rotlv_vec: 3139 v2 = temp_tcgv_vec(arg_temp(a2)); 3140 t1 = tcg_temp_new_vec(type); 3141 c1 = tcg_constant_vec(type, vece, 8 << vece); 3142 tcg_gen_sub_vec(vece, t1, v2, c1); 3143 /* Right shifts are negative left shifts for NEON. */ 3144 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1), 3145 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 3146 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0), 3147 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 3148 tcg_gen_or_vec(vece, v0, v0, t1); 3149 tcg_temp_free_vec(t1); 3150 break; 3151 3152 case INDEX_op_rotrv_vec: 3153 v2 = temp_tcgv_vec(arg_temp(a2)); 3154 t1 = tcg_temp_new_vec(type); 3155 t2 = tcg_temp_new_vec(type); 3156 c1 = tcg_constant_vec(type, vece, 8 << vece); 3157 tcg_gen_neg_vec(vece, t1, v2); 3158 tcg_gen_sub_vec(vece, t2, c1, v2); 3159 /* Right shifts are negative left shifts for NEON. */ 3160 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1), 3161 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 3162 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t2), 3163 tcgv_vec_arg(v1), tcgv_vec_arg(t2)); 3164 tcg_gen_or_vec(vece, v0, t1, t2); 3165 tcg_temp_free_vec(t1); 3166 tcg_temp_free_vec(t2); 3167 break; 3168 3169 default: 3170 g_assert_not_reached(); 3171 } 3172} 3173 3174static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 3175{ 3176 int i; 3177 for (i = 0; i < count; ++i) { 3178 p[i] = INSN_NOP; 3179 } 3180} 3181 3182/* Compute frame size via macros, to share between tcg_target_qemu_prologue 3183 and tcg_register_jit. */ 3184 3185#define PUSH_SIZE ((11 - 4 + 1 + 1) * sizeof(tcg_target_long)) 3186 3187#define FRAME_SIZE \ 3188 ((PUSH_SIZE \ 3189 + TCG_STATIC_CALL_ARGS_SIZE \ 3190 + CPU_TEMP_BUF_NLONGS * sizeof(long) \ 3191 + TCG_TARGET_STACK_ALIGN - 1) \ 3192 & -TCG_TARGET_STACK_ALIGN) 3193 3194#define STACK_ADDEND (FRAME_SIZE - PUSH_SIZE) 3195 3196static void tcg_target_qemu_prologue(TCGContext *s) 3197{ 3198 /* Calling convention requires us to save r4-r11 and lr. */ 3199 /* stmdb sp!, { r4 - r11, lr } */ 3200 tcg_out_ldstm(s, COND_AL, INSN_STMDB, TCG_REG_CALL_STACK, 3201 (1 << TCG_REG_R4) | (1 << TCG_REG_R5) | (1 << TCG_REG_R6) | 3202 (1 << TCG_REG_R7) | (1 << TCG_REG_R8) | (1 << TCG_REG_R9) | 3203 (1 << TCG_REG_R10) | (1 << TCG_REG_R11) | (1 << TCG_REG_R14)); 3204 3205 /* Reserve callee argument and tcg temp space. */ 3206 tcg_out_dat_rI(s, COND_AL, ARITH_SUB, TCG_REG_CALL_STACK, 3207 TCG_REG_CALL_STACK, STACK_ADDEND, 1); 3208 tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE, 3209 CPU_TEMP_BUF_NLONGS * sizeof(long)); 3210 3211 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 3212 3213 if (!tcg_use_softmmu && guest_base) { 3214 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_GUEST_BASE, guest_base); 3215 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GUEST_BASE); 3216 } 3217 3218 tcg_out_b_reg(s, COND_AL, tcg_target_call_iarg_regs[1]); 3219 3220 /* 3221 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 3222 * and fall through to the rest of the epilogue. 3223 */ 3224 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 3225 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, 0); 3226 tcg_out_epilogue(s); 3227} 3228 3229static void tcg_out_epilogue(TCGContext *s) 3230{ 3231 /* Release local stack frame. */ 3232 tcg_out_dat_rI(s, COND_AL, ARITH_ADD, TCG_REG_CALL_STACK, 3233 TCG_REG_CALL_STACK, STACK_ADDEND, 1); 3234 3235 /* ldmia sp!, { r4 - r11, pc } */ 3236 tcg_out_ldstm(s, COND_AL, INSN_LDMIA, TCG_REG_CALL_STACK, 3237 (1 << TCG_REG_R4) | (1 << TCG_REG_R5) | (1 << TCG_REG_R6) | 3238 (1 << TCG_REG_R7) | (1 << TCG_REG_R8) | (1 << TCG_REG_R9) | 3239 (1 << TCG_REG_R10) | (1 << TCG_REG_R11) | (1 << TCG_REG_PC)); 3240} 3241 3242static void tcg_out_tb_start(TCGContext *s) 3243{ 3244 /* nothing to do */ 3245} 3246 3247typedef struct { 3248 DebugFrameHeader h; 3249 uint8_t fde_def_cfa[4]; 3250 uint8_t fde_reg_ofs[18]; 3251} DebugFrame; 3252 3253#define ELF_HOST_MACHINE EM_ARM 3254 3255/* We're expecting a 2 byte uleb128 encoded value. */ 3256QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); 3257 3258static const DebugFrame debug_frame = { 3259 .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ 3260 .h.cie.id = -1, 3261 .h.cie.version = 1, 3262 .h.cie.code_align = 1, 3263 .h.cie.data_align = 0x7c, /* sleb128 -4 */ 3264 .h.cie.return_column = 14, 3265 3266 /* Total FDE size does not include the "len" member. */ 3267 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 3268 3269 .fde_def_cfa = { 3270 12, 13, /* DW_CFA_def_cfa sp, ... */ 3271 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 3272 (FRAME_SIZE >> 7) 3273 }, 3274 .fde_reg_ofs = { 3275 /* The following must match the stmdb in the prologue. */ 3276 0x8e, 1, /* DW_CFA_offset, lr, -4 */ 3277 0x8b, 2, /* DW_CFA_offset, r11, -8 */ 3278 0x8a, 3, /* DW_CFA_offset, r10, -12 */ 3279 0x89, 4, /* DW_CFA_offset, r9, -16 */ 3280 0x88, 5, /* DW_CFA_offset, r8, -20 */ 3281 0x87, 6, /* DW_CFA_offset, r7, -24 */ 3282 0x86, 7, /* DW_CFA_offset, r6, -28 */ 3283 0x85, 8, /* DW_CFA_offset, r5, -32 */ 3284 0x84, 9, /* DW_CFA_offset, r4, -36 */ 3285 } 3286}; 3287 3288void tcg_register_jit(const void *buf, size_t buf_size) 3289{ 3290 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 3291} 3292