1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Andrzej Zaborowski 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25#include "elf.h" 26 27int arm_arch = __ARM_ARCH; 28 29#ifndef use_idiv_instructions 30bool use_idiv_instructions; 31#endif 32#ifndef use_neon_instructions 33bool use_neon_instructions; 34#endif 35 36/* Used for function call generation. */ 37#define TCG_TARGET_STACK_ALIGN 8 38#define TCG_TARGET_CALL_STACK_OFFSET 0 39#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL 40#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN 41#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN 42#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF 43 44#ifdef CONFIG_DEBUG_TCG 45static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 46 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", 47 "%r8", "%r9", "%r10", "%r11", "%r12", "%sp", "%r14", "%pc", 48 "%q0", "%q1", "%q2", "%q3", "%q4", "%q5", "%q6", "%q7", 49 "%q8", "%q9", "%q10", "%q11", "%q12", "%q13", "%q14", "%q15", 50}; 51#endif 52 53static const int tcg_target_reg_alloc_order[] = { 54 TCG_REG_R4, 55 TCG_REG_R5, 56 TCG_REG_R6, 57 TCG_REG_R7, 58 TCG_REG_R8, 59 TCG_REG_R9, 60 TCG_REG_R10, 61 TCG_REG_R11, 62 TCG_REG_R13, 63 TCG_REG_R0, 64 TCG_REG_R1, 65 TCG_REG_R2, 66 TCG_REG_R3, 67 TCG_REG_R12, 68 TCG_REG_R14, 69 70 TCG_REG_Q0, 71 TCG_REG_Q1, 72 TCG_REG_Q2, 73 TCG_REG_Q3, 74 /* Q4 - Q7 are call-saved, and skipped. */ 75 TCG_REG_Q8, 76 TCG_REG_Q9, 77 TCG_REG_Q10, 78 TCG_REG_Q11, 79 TCG_REG_Q12, 80 TCG_REG_Q13, 81 TCG_REG_Q14, 82 TCG_REG_Q15, 83}; 84 85static const int tcg_target_call_iarg_regs[4] = { 86 TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3 87}; 88 89static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 90{ 91 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 92 tcg_debug_assert(slot >= 0 && slot <= 3); 93 return TCG_REG_R0 + slot; 94} 95 96#define TCG_REG_TMP TCG_REG_R12 97#define TCG_VEC_TMP TCG_REG_Q15 98#define TCG_REG_GUEST_BASE TCG_REG_R11 99 100typedef enum { 101 COND_EQ = 0x0, 102 COND_NE = 0x1, 103 COND_CS = 0x2, /* Unsigned greater or equal */ 104 COND_CC = 0x3, /* Unsigned less than */ 105 COND_MI = 0x4, /* Negative */ 106 COND_PL = 0x5, /* Zero or greater */ 107 COND_VS = 0x6, /* Overflow */ 108 COND_VC = 0x7, /* No overflow */ 109 COND_HI = 0x8, /* Unsigned greater than */ 110 COND_LS = 0x9, /* Unsigned less or equal */ 111 COND_GE = 0xa, 112 COND_LT = 0xb, 113 COND_GT = 0xc, 114 COND_LE = 0xd, 115 COND_AL = 0xe, 116} ARMCond; 117 118#define TO_CPSR (1 << 20) 119 120#define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00) 121#define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20) 122#define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40) 123#define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60) 124#define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10) 125#define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30) 126#define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50) 127#define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70) 128 129typedef enum { 130 ARITH_AND = 0x0 << 21, 131 ARITH_EOR = 0x1 << 21, 132 ARITH_SUB = 0x2 << 21, 133 ARITH_RSB = 0x3 << 21, 134 ARITH_ADD = 0x4 << 21, 135 ARITH_ADC = 0x5 << 21, 136 ARITH_SBC = 0x6 << 21, 137 ARITH_RSC = 0x7 << 21, 138 ARITH_TST = 0x8 << 21 | TO_CPSR, 139 ARITH_CMP = 0xa << 21 | TO_CPSR, 140 ARITH_CMN = 0xb << 21 | TO_CPSR, 141 ARITH_ORR = 0xc << 21, 142 ARITH_MOV = 0xd << 21, 143 ARITH_BIC = 0xe << 21, 144 ARITH_MVN = 0xf << 21, 145 146 INSN_B = 0x0a000000, 147 148 INSN_CLZ = 0x016f0f10, 149 INSN_RBIT = 0x06ff0f30, 150 151 INSN_LDMIA = 0x08b00000, 152 INSN_STMDB = 0x09200000, 153 154 INSN_LDR_IMM = 0x04100000, 155 INSN_LDR_REG = 0x06100000, 156 INSN_STR_IMM = 0x04000000, 157 INSN_STR_REG = 0x06000000, 158 159 INSN_LDRH_IMM = 0x005000b0, 160 INSN_LDRH_REG = 0x001000b0, 161 INSN_LDRSH_IMM = 0x005000f0, 162 INSN_LDRSH_REG = 0x001000f0, 163 INSN_STRH_IMM = 0x004000b0, 164 INSN_STRH_REG = 0x000000b0, 165 166 INSN_LDRB_IMM = 0x04500000, 167 INSN_LDRB_REG = 0x06500000, 168 INSN_LDRSB_IMM = 0x005000d0, 169 INSN_LDRSB_REG = 0x001000d0, 170 INSN_STRB_IMM = 0x04400000, 171 INSN_STRB_REG = 0x06400000, 172 173 INSN_LDRD_IMM = 0x004000d0, 174 INSN_LDRD_REG = 0x000000d0, 175 INSN_STRD_IMM = 0x004000f0, 176 INSN_STRD_REG = 0x000000f0, 177 178 INSN_DMB_ISH = 0xf57ff05b, 179 INSN_DMB_MCR = 0xee070fba, 180 181 /* Architected nop introduced in v6k. */ 182 /* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this 183 also Just So Happened to do nothing on pre-v6k so that we 184 don't need to conditionalize it? */ 185 INSN_NOP_v6k = 0xe320f000, 186 /* Otherwise the assembler uses mov r0,r0 */ 187 INSN_NOP_v4 = (COND_AL << 28) | ARITH_MOV, 188 189 INSN_VADD = 0xf2000800, 190 INSN_VAND = 0xf2000110, 191 INSN_VBIC = 0xf2100110, 192 INSN_VEOR = 0xf3000110, 193 INSN_VORN = 0xf2300110, 194 INSN_VORR = 0xf2200110, 195 INSN_VSUB = 0xf3000800, 196 INSN_VMUL = 0xf2000910, 197 INSN_VQADD = 0xf2000010, 198 INSN_VQADD_U = 0xf3000010, 199 INSN_VQSUB = 0xf2000210, 200 INSN_VQSUB_U = 0xf3000210, 201 INSN_VMAX = 0xf2000600, 202 INSN_VMAX_U = 0xf3000600, 203 INSN_VMIN = 0xf2000610, 204 INSN_VMIN_U = 0xf3000610, 205 206 INSN_VABS = 0xf3b10300, 207 INSN_VMVN = 0xf3b00580, 208 INSN_VNEG = 0xf3b10380, 209 210 INSN_VCEQ0 = 0xf3b10100, 211 INSN_VCGT0 = 0xf3b10000, 212 INSN_VCGE0 = 0xf3b10080, 213 INSN_VCLE0 = 0xf3b10180, 214 INSN_VCLT0 = 0xf3b10200, 215 216 INSN_VCEQ = 0xf3000810, 217 INSN_VCGE = 0xf2000310, 218 INSN_VCGT = 0xf2000300, 219 INSN_VCGE_U = 0xf3000310, 220 INSN_VCGT_U = 0xf3000300, 221 222 INSN_VSHLI = 0xf2800510, /* VSHL (immediate) */ 223 INSN_VSARI = 0xf2800010, /* VSHR.S */ 224 INSN_VSHRI = 0xf3800010, /* VSHR.U */ 225 INSN_VSLI = 0xf3800510, 226 INSN_VSHL_S = 0xf2000400, /* VSHL.S (register) */ 227 INSN_VSHL_U = 0xf3000400, /* VSHL.U (register) */ 228 229 INSN_VBSL = 0xf3100110, 230 INSN_VBIT = 0xf3200110, 231 INSN_VBIF = 0xf3300110, 232 233 INSN_VTST = 0xf2000810, 234 235 INSN_VDUP_G = 0xee800b10, /* VDUP (ARM core register) */ 236 INSN_VDUP_S = 0xf3b00c00, /* VDUP (scalar) */ 237 INSN_VLDR_D = 0xed100b00, /* VLDR.64 */ 238 INSN_VLD1 = 0xf4200000, /* VLD1 (multiple single elements) */ 239 INSN_VLD1R = 0xf4a00c00, /* VLD1 (single element to all lanes) */ 240 INSN_VST1 = 0xf4000000, /* VST1 (multiple single elements) */ 241 INSN_VMOVI = 0xf2800010, /* VMOV (immediate) */ 242} ARMInsn; 243 244#define INSN_NOP (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4) 245 246static const uint8_t tcg_cond_to_arm_cond[] = { 247 [TCG_COND_EQ] = COND_EQ, 248 [TCG_COND_NE] = COND_NE, 249 [TCG_COND_LT] = COND_LT, 250 [TCG_COND_GE] = COND_GE, 251 [TCG_COND_LE] = COND_LE, 252 [TCG_COND_GT] = COND_GT, 253 /* unsigned */ 254 [TCG_COND_LTU] = COND_CC, 255 [TCG_COND_GEU] = COND_CS, 256 [TCG_COND_LEU] = COND_LS, 257 [TCG_COND_GTU] = COND_HI, 258}; 259 260static int encode_imm(uint32_t imm); 261 262/* TCG private relocation type: add with pc+imm8 */ 263#define R_ARM_PC8 11 264 265/* TCG private relocation type: vldr with imm8 << 2 */ 266#define R_ARM_PC11 12 267 268static bool reloc_pc24(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 269{ 270 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 271 ptrdiff_t offset = (tcg_ptr_byte_diff(target, src_rx) - 8) >> 2; 272 273 if (offset == sextract32(offset, 0, 24)) { 274 *src_rw = deposit32(*src_rw, 0, 24, offset); 275 return true; 276 } 277 return false; 278} 279 280static bool reloc_pc13(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 281{ 282 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 283 ptrdiff_t offset = tcg_ptr_byte_diff(target, src_rx) - 8; 284 285 if (offset >= -0xfff && offset <= 0xfff) { 286 tcg_insn_unit insn = *src_rw; 287 bool u = (offset >= 0); 288 if (!u) { 289 offset = -offset; 290 } 291 insn = deposit32(insn, 23, 1, u); 292 insn = deposit32(insn, 0, 12, offset); 293 *src_rw = insn; 294 return true; 295 } 296 return false; 297} 298 299static bool reloc_pc11(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 300{ 301 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 302 ptrdiff_t offset = (tcg_ptr_byte_diff(target, src_rx) - 8) / 4; 303 304 if (offset >= -0xff && offset <= 0xff) { 305 tcg_insn_unit insn = *src_rw; 306 bool u = (offset >= 0); 307 if (!u) { 308 offset = -offset; 309 } 310 insn = deposit32(insn, 23, 1, u); 311 insn = deposit32(insn, 0, 8, offset); 312 *src_rw = insn; 313 return true; 314 } 315 return false; 316} 317 318static bool reloc_pc8(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 319{ 320 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 321 ptrdiff_t offset = tcg_ptr_byte_diff(target, src_rx) - 8; 322 int imm12 = encode_imm(offset); 323 324 if (imm12 >= 0) { 325 *src_rw = deposit32(*src_rw, 0, 12, imm12); 326 return true; 327 } 328 return false; 329} 330 331static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 332 intptr_t value, intptr_t addend) 333{ 334 tcg_debug_assert(addend == 0); 335 switch (type) { 336 case R_ARM_PC24: 337 return reloc_pc24(code_ptr, (const tcg_insn_unit *)value); 338 case R_ARM_PC13: 339 return reloc_pc13(code_ptr, (const tcg_insn_unit *)value); 340 case R_ARM_PC11: 341 return reloc_pc11(code_ptr, (const tcg_insn_unit *)value); 342 case R_ARM_PC8: 343 return reloc_pc8(code_ptr, (const tcg_insn_unit *)value); 344 default: 345 g_assert_not_reached(); 346 } 347} 348 349#define TCG_CT_CONST_ARM 0x100 350#define TCG_CT_CONST_INV 0x200 351#define TCG_CT_CONST_NEG 0x400 352#define TCG_CT_CONST_ZERO 0x800 353#define TCG_CT_CONST_ORRI 0x1000 354#define TCG_CT_CONST_ANDI 0x2000 355 356#define ALL_GENERAL_REGS 0xffffu 357#define ALL_VECTOR_REGS 0xffff0000u 358 359/* 360 * r0-r3 will be overwritten when reading the tlb entry (system-mode only); 361 * r14 will be overwritten by the BLNE branching to the slow path. 362 */ 363#define ALL_QLDST_REGS \ 364 (ALL_GENERAL_REGS & ~((tcg_use_softmmu ? 0xf : 0) | (1 << TCG_REG_R14))) 365 366/* 367 * ARM immediates for ALU instructions are made of an unsigned 8-bit 368 * right-rotated by an even amount between 0 and 30. 369 * 370 * Return < 0 if @imm cannot be encoded, else the entire imm12 field. 371 */ 372static int encode_imm(uint32_t imm) 373{ 374 uint32_t rot, imm8; 375 376 /* Simple case, no rotation required. */ 377 if ((imm & ~0xff) == 0) { 378 return imm; 379 } 380 381 /* Next, try a simple even shift. */ 382 rot = ctz32(imm) & ~1; 383 imm8 = imm >> rot; 384 rot = 32 - rot; 385 if ((imm8 & ~0xff) == 0) { 386 goto found; 387 } 388 389 /* 390 * Finally, try harder with rotations. 391 * The ctz test above will have taken care of rotates >= 8. 392 */ 393 for (rot = 2; rot < 8; rot += 2) { 394 imm8 = rol32(imm, rot); 395 if ((imm8 & ~0xff) == 0) { 396 goto found; 397 } 398 } 399 /* Fail: imm cannot be encoded. */ 400 return -1; 401 402 found: 403 /* Note that rot is even, and we discard bit 0 by shifting by 7. */ 404 return rot << 7 | imm8; 405} 406 407static int encode_imm_nofail(uint32_t imm) 408{ 409 int ret = encode_imm(imm); 410 tcg_debug_assert(ret >= 0); 411 return ret; 412} 413 414static bool check_fit_imm(uint32_t imm) 415{ 416 return encode_imm(imm) >= 0; 417} 418 419/* Return true if v16 is a valid 16-bit shifted immediate. */ 420static bool is_shimm16(uint16_t v16, int *cmode, int *imm8) 421{ 422 if (v16 == (v16 & 0xff)) { 423 *cmode = 0x8; 424 *imm8 = v16 & 0xff; 425 return true; 426 } else if (v16 == (v16 & 0xff00)) { 427 *cmode = 0xa; 428 *imm8 = v16 >> 8; 429 return true; 430 } 431 return false; 432} 433 434/* Return true if v32 is a valid 32-bit shifted immediate. */ 435static bool is_shimm32(uint32_t v32, int *cmode, int *imm8) 436{ 437 if (v32 == (v32 & 0xff)) { 438 *cmode = 0x0; 439 *imm8 = v32 & 0xff; 440 return true; 441 } else if (v32 == (v32 & 0xff00)) { 442 *cmode = 0x2; 443 *imm8 = (v32 >> 8) & 0xff; 444 return true; 445 } else if (v32 == (v32 & 0xff0000)) { 446 *cmode = 0x4; 447 *imm8 = (v32 >> 16) & 0xff; 448 return true; 449 } else if (v32 == (v32 & 0xff000000)) { 450 *cmode = 0x6; 451 *imm8 = v32 >> 24; 452 return true; 453 } 454 return false; 455} 456 457/* Return true if v32 is a valid 32-bit shifting ones immediate. */ 458static bool is_soimm32(uint32_t v32, int *cmode, int *imm8) 459{ 460 if ((v32 & 0xffff00ff) == 0xff) { 461 *cmode = 0xc; 462 *imm8 = (v32 >> 8) & 0xff; 463 return true; 464 } else if ((v32 & 0xff00ffff) == 0xffff) { 465 *cmode = 0xd; 466 *imm8 = (v32 >> 16) & 0xff; 467 return true; 468 } 469 return false; 470} 471 472/* 473 * Return non-zero if v32 can be formed by MOVI+ORR. 474 * Place the parameters for MOVI in (cmode, imm8). 475 * Return the cmode for ORR; the imm8 can be had via extraction from v32. 476 */ 477static int is_shimm32_pair(uint32_t v32, int *cmode, int *imm8) 478{ 479 int i; 480 481 for (i = 6; i > 0; i -= 2) { 482 /* Mask out one byte we can add with ORR. */ 483 uint32_t tmp = v32 & ~(0xffu << (i * 4)); 484 if (is_shimm32(tmp, cmode, imm8) || 485 is_soimm32(tmp, cmode, imm8)) { 486 break; 487 } 488 } 489 return i; 490} 491 492/* Return true if V is a valid 16-bit or 32-bit shifted immediate. */ 493static bool is_shimm1632(uint32_t v32, int *cmode, int *imm8) 494{ 495 if (v32 == deposit32(v32, 16, 16, v32)) { 496 return is_shimm16(v32, cmode, imm8); 497 } else { 498 return is_shimm32(v32, cmode, imm8); 499 } 500} 501 502/* Test if a constant matches the constraint. 503 * TODO: define constraints for: 504 * 505 * ldr/str offset: between -0xfff and 0xfff 506 * ldrh/strh offset: between -0xff and 0xff 507 * mov operand2: values represented with x << (2 * y), x < 0x100 508 * add, sub, eor...: ditto 509 */ 510static bool tcg_target_const_match(int64_t val, int ct, 511 TCGType type, TCGCond cond, int vece) 512{ 513 if (ct & TCG_CT_CONST) { 514 return 1; 515 } else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val)) { 516 return 1; 517 } else if ((ct & TCG_CT_CONST_INV) && check_fit_imm(~val)) { 518 return 1; 519 } else if ((ct & TCG_CT_CONST_NEG) && check_fit_imm(-val)) { 520 return 1; 521 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 522 return 1; 523 } 524 525 switch (ct & (TCG_CT_CONST_ORRI | TCG_CT_CONST_ANDI)) { 526 case 0: 527 break; 528 case TCG_CT_CONST_ANDI: 529 val = ~val; 530 /* fallthru */ 531 case TCG_CT_CONST_ORRI: 532 if (val == deposit64(val, 32, 32, val)) { 533 int cmode, imm8; 534 return is_shimm1632(val, &cmode, &imm8); 535 } 536 break; 537 default: 538 /* Both bits should not be set for the same insn. */ 539 g_assert_not_reached(); 540 } 541 542 return 0; 543} 544 545static void tcg_out_b_imm(TCGContext *s, ARMCond cond, int32_t offset) 546{ 547 tcg_out32(s, (cond << 28) | INSN_B | 548 (((offset - 8) >> 2) & 0x00ffffff)); 549} 550 551static void tcg_out_bl_imm(TCGContext *s, ARMCond cond, int32_t offset) 552{ 553 tcg_out32(s, (cond << 28) | 0x0b000000 | 554 (((offset - 8) >> 2) & 0x00ffffff)); 555} 556 557static void tcg_out_blx_reg(TCGContext *s, ARMCond cond, TCGReg rn) 558{ 559 tcg_out32(s, (cond << 28) | 0x012fff30 | rn); 560} 561 562static void tcg_out_blx_imm(TCGContext *s, int32_t offset) 563{ 564 tcg_out32(s, 0xfa000000 | ((offset & 2) << 23) | 565 (((offset - 8) >> 2) & 0x00ffffff)); 566} 567 568static void tcg_out_dat_reg(TCGContext *s, ARMCond cond, ARMInsn opc, 569 TCGReg rd, TCGReg rn, TCGReg rm, int shift) 570{ 571 tcg_out32(s, (cond << 28) | (0 << 25) | opc | 572 (rn << 16) | (rd << 12) | shift | rm); 573} 574 575static void tcg_out_mov_reg(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rm) 576{ 577 /* Simple reg-reg move, optimising out the 'do nothing' case */ 578 if (rd != rm) { 579 tcg_out_dat_reg(s, cond, ARITH_MOV, rd, 0, rm, SHIFT_IMM_LSL(0)); 580 } 581} 582 583static void tcg_out_bx_reg(TCGContext *s, ARMCond cond, TCGReg rn) 584{ 585 tcg_out32(s, (cond << 28) | 0x012fff10 | rn); 586} 587 588static void tcg_out_b_reg(TCGContext *s, ARMCond cond, TCGReg rn) 589{ 590 /* 591 * Unless the C portion of QEMU is compiled as thumb, we don't need 592 * true BX semantics; merely a branch to an address held in a register. 593 */ 594 tcg_out_bx_reg(s, cond, rn); 595} 596 597static void tcg_out_dat_imm(TCGContext *s, ARMCond cond, ARMInsn opc, 598 TCGReg rd, TCGReg rn, int im) 599{ 600 tcg_out32(s, (cond << 28) | (1 << 25) | opc | 601 (rn << 16) | (rd << 12) | im); 602} 603 604static void tcg_out_ldstm(TCGContext *s, ARMCond cond, ARMInsn opc, 605 TCGReg rn, uint16_t mask) 606{ 607 tcg_out32(s, (cond << 28) | opc | (rn << 16) | mask); 608} 609 610/* Note that this routine is used for both LDR and LDRH formats, so we do 611 not wish to include an immediate shift at this point. */ 612static void tcg_out_memop_r(TCGContext *s, ARMCond cond, ARMInsn opc, TCGReg rt, 613 TCGReg rn, TCGReg rm, bool u, bool p, bool w) 614{ 615 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) 616 | (w << 21) | (rn << 16) | (rt << 12) | rm); 617} 618 619static void tcg_out_memop_8(TCGContext *s, ARMCond cond, ARMInsn opc, TCGReg rt, 620 TCGReg rn, int imm8, bool p, bool w) 621{ 622 bool u = 1; 623 if (imm8 < 0) { 624 imm8 = -imm8; 625 u = 0; 626 } 627 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | 628 (rn << 16) | (rt << 12) | ((imm8 & 0xf0) << 4) | (imm8 & 0xf)); 629} 630 631static void tcg_out_memop_12(TCGContext *s, ARMCond cond, ARMInsn opc, 632 TCGReg rt, TCGReg rn, int imm12, bool p, bool w) 633{ 634 bool u = 1; 635 if (imm12 < 0) { 636 imm12 = -imm12; 637 u = 0; 638 } 639 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | 640 (rn << 16) | (rt << 12) | imm12); 641} 642 643static void tcg_out_ld32_12(TCGContext *s, ARMCond cond, TCGReg rt, 644 TCGReg rn, int imm12) 645{ 646 tcg_out_memop_12(s, cond, INSN_LDR_IMM, rt, rn, imm12, 1, 0); 647} 648 649static void tcg_out_st32_12(TCGContext *s, ARMCond cond, TCGReg rt, 650 TCGReg rn, int imm12) 651{ 652 tcg_out_memop_12(s, cond, INSN_STR_IMM, rt, rn, imm12, 1, 0); 653} 654 655static void tcg_out_ld32_r(TCGContext *s, ARMCond cond, TCGReg rt, 656 TCGReg rn, TCGReg rm) 657{ 658 tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 0); 659} 660 661static void tcg_out_st32_r(TCGContext *s, ARMCond cond, TCGReg rt, 662 TCGReg rn, TCGReg rm) 663{ 664 tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 0); 665} 666 667static void tcg_out_ldrd_8(TCGContext *s, ARMCond cond, TCGReg rt, 668 TCGReg rn, int imm8) 669{ 670 tcg_out_memop_8(s, cond, INSN_LDRD_IMM, rt, rn, imm8, 1, 0); 671} 672 673static void tcg_out_ldrd_r(TCGContext *s, ARMCond cond, TCGReg rt, 674 TCGReg rn, TCGReg rm) 675{ 676 tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 0); 677} 678 679static void tcg_out_strd_8(TCGContext *s, ARMCond cond, TCGReg rt, 680 TCGReg rn, int imm8) 681{ 682 tcg_out_memop_8(s, cond, INSN_STRD_IMM, rt, rn, imm8, 1, 0); 683} 684 685static void tcg_out_strd_r(TCGContext *s, ARMCond cond, TCGReg rt, 686 TCGReg rn, TCGReg rm) 687{ 688 tcg_out_memop_r(s, cond, INSN_STRD_REG, rt, rn, rm, 1, 1, 0); 689} 690 691/* Register pre-increment with base writeback. */ 692static void tcg_out_ld32_rwb(TCGContext *s, ARMCond cond, TCGReg rt, 693 TCGReg rn, TCGReg rm) 694{ 695 tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 1); 696} 697 698static void tcg_out_st32_rwb(TCGContext *s, ARMCond cond, TCGReg rt, 699 TCGReg rn, TCGReg rm) 700{ 701 tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 1); 702} 703 704static void tcg_out_ld16u_8(TCGContext *s, ARMCond cond, TCGReg rt, 705 TCGReg rn, int imm8) 706{ 707 tcg_out_memop_8(s, cond, INSN_LDRH_IMM, rt, rn, imm8, 1, 0); 708} 709 710static void tcg_out_st16_8(TCGContext *s, ARMCond cond, TCGReg rt, 711 TCGReg rn, int imm8) 712{ 713 tcg_out_memop_8(s, cond, INSN_STRH_IMM, rt, rn, imm8, 1, 0); 714} 715 716static void tcg_out_ld16u_r(TCGContext *s, ARMCond cond, TCGReg rt, 717 TCGReg rn, TCGReg rm) 718{ 719 tcg_out_memop_r(s, cond, INSN_LDRH_REG, rt, rn, rm, 1, 1, 0); 720} 721 722static void tcg_out_st16_r(TCGContext *s, ARMCond cond, TCGReg rt, 723 TCGReg rn, TCGReg rm) 724{ 725 tcg_out_memop_r(s, cond, INSN_STRH_REG, rt, rn, rm, 1, 1, 0); 726} 727 728static void tcg_out_ld16s_8(TCGContext *s, ARMCond cond, TCGReg rt, 729 TCGReg rn, int imm8) 730{ 731 tcg_out_memop_8(s, cond, INSN_LDRSH_IMM, rt, rn, imm8, 1, 0); 732} 733 734static void tcg_out_ld16s_r(TCGContext *s, ARMCond cond, TCGReg rt, 735 TCGReg rn, TCGReg rm) 736{ 737 tcg_out_memop_r(s, cond, INSN_LDRSH_REG, rt, rn, rm, 1, 1, 0); 738} 739 740static void tcg_out_ld8_12(TCGContext *s, ARMCond cond, TCGReg rt, 741 TCGReg rn, int imm12) 742{ 743 tcg_out_memop_12(s, cond, INSN_LDRB_IMM, rt, rn, imm12, 1, 0); 744} 745 746static void tcg_out_st8_12(TCGContext *s, ARMCond cond, TCGReg rt, 747 TCGReg rn, int imm12) 748{ 749 tcg_out_memop_12(s, cond, INSN_STRB_IMM, rt, rn, imm12, 1, 0); 750} 751 752static void tcg_out_ld8_r(TCGContext *s, ARMCond cond, TCGReg rt, 753 TCGReg rn, TCGReg rm) 754{ 755 tcg_out_memop_r(s, cond, INSN_LDRB_REG, rt, rn, rm, 1, 1, 0); 756} 757 758static void tcg_out_st8_r(TCGContext *s, ARMCond cond, TCGReg rt, 759 TCGReg rn, TCGReg rm) 760{ 761 tcg_out_memop_r(s, cond, INSN_STRB_REG, rt, rn, rm, 1, 1, 0); 762} 763 764static void tcg_out_ld8s_8(TCGContext *s, ARMCond cond, TCGReg rt, 765 TCGReg rn, int imm8) 766{ 767 tcg_out_memop_8(s, cond, INSN_LDRSB_IMM, rt, rn, imm8, 1, 0); 768} 769 770static void tcg_out_ld8s_r(TCGContext *s, ARMCond cond, TCGReg rt, 771 TCGReg rn, TCGReg rm) 772{ 773 tcg_out_memop_r(s, cond, INSN_LDRSB_REG, rt, rn, rm, 1, 1, 0); 774} 775 776static void tcg_out_movi_pool(TCGContext *s, ARMCond cond, 777 TCGReg rd, uint32_t arg) 778{ 779 new_pool_label(s, arg, R_ARM_PC13, s->code_ptr, 0); 780 tcg_out_ld32_12(s, cond, rd, TCG_REG_PC, 0); 781} 782 783static void tcg_out_movi32(TCGContext *s, ARMCond cond, 784 TCGReg rd, uint32_t arg) 785{ 786 int imm12, diff, opc, sh1, sh2; 787 uint32_t tt0, tt1, tt2; 788 789 /* Check a single MOV/MVN before anything else. */ 790 imm12 = encode_imm(arg); 791 if (imm12 >= 0) { 792 tcg_out_dat_imm(s, cond, ARITH_MOV, rd, 0, imm12); 793 return; 794 } 795 imm12 = encode_imm(~arg); 796 if (imm12 >= 0) { 797 tcg_out_dat_imm(s, cond, ARITH_MVN, rd, 0, imm12); 798 return; 799 } 800 801 /* Check for a pc-relative address. This will usually be the TB, 802 or within the TB, which is immediately before the code block. */ 803 diff = tcg_pcrel_diff(s, (void *)arg) - 8; 804 if (diff >= 0) { 805 imm12 = encode_imm(diff); 806 if (imm12 >= 0) { 807 tcg_out_dat_imm(s, cond, ARITH_ADD, rd, TCG_REG_PC, imm12); 808 return; 809 } 810 } else { 811 imm12 = encode_imm(-diff); 812 if (imm12 >= 0) { 813 tcg_out_dat_imm(s, cond, ARITH_SUB, rd, TCG_REG_PC, imm12); 814 return; 815 } 816 } 817 818 /* Use movw + movt. */ 819 if (use_armv7_instructions) { 820 /* movw */ 821 tcg_out32(s, (cond << 28) | 0x03000000 | (rd << 12) 822 | ((arg << 4) & 0x000f0000) | (arg & 0xfff)); 823 if (arg & 0xffff0000) { 824 /* movt */ 825 tcg_out32(s, (cond << 28) | 0x03400000 | (rd << 12) 826 | ((arg >> 12) & 0x000f0000) | ((arg >> 16) & 0xfff)); 827 } 828 return; 829 } 830 831 /* Look for sequences of two insns. If we have lots of 1's, we can 832 shorten the sequence by beginning with mvn and then clearing 833 higher bits with eor. */ 834 tt0 = arg; 835 opc = ARITH_MOV; 836 if (ctpop32(arg) > 16) { 837 tt0 = ~arg; 838 opc = ARITH_MVN; 839 } 840 sh1 = ctz32(tt0) & ~1; 841 tt1 = tt0 & ~(0xff << sh1); 842 sh2 = ctz32(tt1) & ~1; 843 tt2 = tt1 & ~(0xff << sh2); 844 if (tt2 == 0) { 845 int rot; 846 847 rot = ((32 - sh1) << 7) & 0xf00; 848 tcg_out_dat_imm(s, cond, opc, rd, 0, ((tt0 >> sh1) & 0xff) | rot); 849 rot = ((32 - sh2) << 7) & 0xf00; 850 tcg_out_dat_imm(s, cond, ARITH_EOR, rd, rd, 851 ((tt0 >> sh2) & 0xff) | rot); 852 return; 853 } 854 855 /* Otherwise, drop it into the constant pool. */ 856 tcg_out_movi_pool(s, cond, rd, arg); 857} 858 859/* 860 * Emit either the reg,imm or reg,reg form of a data-processing insn. 861 * rhs must satisfy the "rI" constraint. 862 */ 863static void tcg_out_dat_rI(TCGContext *s, ARMCond cond, ARMInsn opc, 864 TCGReg dst, TCGReg lhs, TCGArg rhs, int rhs_is_const) 865{ 866 if (rhs_is_const) { 867 tcg_out_dat_imm(s, cond, opc, dst, lhs, encode_imm_nofail(rhs)); 868 } else { 869 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); 870 } 871} 872 873/* 874 * Emit either the reg,imm or reg,reg form of a data-processing insn. 875 * rhs must satisfy the "rIK" constraint. 876 */ 877static void tcg_out_dat_rIK(TCGContext *s, ARMCond cond, ARMInsn opc, 878 ARMInsn opinv, TCGReg dst, TCGReg lhs, TCGArg rhs, 879 bool rhs_is_const) 880{ 881 if (rhs_is_const) { 882 int imm12 = encode_imm(rhs); 883 if (imm12 < 0) { 884 imm12 = encode_imm_nofail(~rhs); 885 opc = opinv; 886 } 887 tcg_out_dat_imm(s, cond, opc, dst, lhs, imm12); 888 } else { 889 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); 890 } 891} 892 893static void tcg_out_dat_IN(TCGContext *s, ARMCond cond, ARMInsn opc, 894 ARMInsn opneg, TCGReg dst, TCGReg lhs, TCGArg rhs) 895{ 896 int imm12 = encode_imm(rhs); 897 if (imm12 < 0) { 898 imm12 = encode_imm_nofail(-rhs); 899 opc = opneg; 900 } 901 tcg_out_dat_imm(s, cond, opc, dst, lhs, imm12); 902} 903 904static void tcg_out_dat_rIN(TCGContext *s, ARMCond cond, ARMInsn opc, 905 ARMInsn opneg, TCGReg dst, TCGReg lhs, TCGArg rhs, 906 bool rhs_is_const) 907{ 908 /* Emit either the reg,imm or reg,reg form of a data-processing insn. 909 * rhs must satisfy the "rIN" constraint. 910 */ 911 if (rhs_is_const) { 912 tcg_out_dat_IN(s, cond, opc, opneg, dst, lhs, rhs); 913 } else { 914 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); 915 } 916} 917 918static void tcg_out_mul32(TCGContext *s, ARMCond cond, TCGReg rd, 919 TCGReg rn, TCGReg rm) 920{ 921 /* mul */ 922 tcg_out32(s, (cond << 28) | 0x90 | (rd << 16) | (rm << 8) | rn); 923} 924 925static void tcg_out_umull32(TCGContext *s, ARMCond cond, TCGReg rd0, 926 TCGReg rd1, TCGReg rn, TCGReg rm) 927{ 928 /* umull */ 929 tcg_out32(s, (cond << 28) | 0x00800090 | 930 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); 931} 932 933static void tcg_out_smull32(TCGContext *s, ARMCond cond, TCGReg rd0, 934 TCGReg rd1, TCGReg rn, TCGReg rm) 935{ 936 /* smull */ 937 tcg_out32(s, (cond << 28) | 0x00c00090 | 938 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); 939} 940 941static void tcg_out_sdiv(TCGContext *s, ARMCond cond, 942 TCGReg rd, TCGReg rn, TCGReg rm) 943{ 944 tcg_out32(s, 0x0710f010 | (cond << 28) | (rd << 16) | rn | (rm << 8)); 945} 946 947static void tcg_out_udiv(TCGContext *s, ARMCond cond, 948 TCGReg rd, TCGReg rn, TCGReg rm) 949{ 950 tcg_out32(s, 0x0730f010 | (cond << 28) | (rd << 16) | rn | (rm << 8)); 951} 952 953static void tcg_out_ext8s(TCGContext *s, TCGType t, TCGReg rd, TCGReg rn) 954{ 955 /* sxtb */ 956 tcg_out32(s, 0x06af0070 | (COND_AL << 28) | (rd << 12) | rn); 957} 958 959static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rn) 960{ 961 tcg_out_dat_imm(s, COND_AL, ARITH_AND, rd, rn, 0xff); 962} 963 964static void tcg_out_ext16s(TCGContext *s, TCGType t, TCGReg rd, TCGReg rn) 965{ 966 /* sxth */ 967 tcg_out32(s, 0x06bf0070 | (COND_AL << 28) | (rd << 12) | rn); 968} 969 970static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rn) 971{ 972 /* uxth */ 973 tcg_out32(s, 0x06ff0070 | (COND_AL << 28) | (rd << 12) | rn); 974} 975 976static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rn) 977{ 978 g_assert_not_reached(); 979} 980 981static void tcg_out_ext32u(TCGContext *s, TCGReg rd, TCGReg rn) 982{ 983 g_assert_not_reached(); 984} 985 986static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rn) 987{ 988 g_assert_not_reached(); 989} 990 991static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rn) 992{ 993 g_assert_not_reached(); 994} 995 996static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rn) 997{ 998 g_assert_not_reached(); 999} 1000 1001static void tcg_out_bswap16(TCGContext *s, ARMCond cond, 1002 TCGReg rd, TCGReg rn, int flags) 1003{ 1004 if (flags & TCG_BSWAP_OS) { 1005 /* revsh */ 1006 tcg_out32(s, 0x06ff0fb0 | (cond << 28) | (rd << 12) | rn); 1007 return; 1008 } 1009 1010 /* rev16 */ 1011 tcg_out32(s, 0x06bf0fb0 | (cond << 28) | (rd << 12) | rn); 1012 if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 1013 /* uxth */ 1014 tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | rd); 1015 } 1016} 1017 1018static void tcg_out_bswap32(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rn) 1019{ 1020 /* rev */ 1021 tcg_out32(s, 0x06bf0f30 | (cond << 28) | (rd << 12) | rn); 1022} 1023 1024static void tcg_out_deposit(TCGContext *s, ARMCond cond, TCGReg rd, 1025 TCGArg a1, int ofs, int len, bool const_a1) 1026{ 1027 if (const_a1) { 1028 /* bfi becomes bfc with rn == 15. */ 1029 a1 = 15; 1030 } 1031 /* bfi/bfc */ 1032 tcg_out32(s, 0x07c00010 | (cond << 28) | (rd << 12) | a1 1033 | (ofs << 7) | ((ofs + len - 1) << 16)); 1034} 1035 1036static void tcg_out_extract(TCGContext *s, ARMCond cond, TCGReg rd, 1037 TCGReg rn, int ofs, int len) 1038{ 1039 /* According to gcc, AND can be faster. */ 1040 if (ofs == 0 && len <= 8) { 1041 tcg_out_dat_imm(s, cond, ARITH_AND, rd, rn, 1042 encode_imm_nofail((1 << len) - 1)); 1043 return; 1044 } 1045 1046 if (use_armv7_instructions) { 1047 /* ubfx */ 1048 tcg_out32(s, 0x07e00050 | (cond << 28) | (rd << 12) | rn 1049 | (ofs << 7) | ((len - 1) << 16)); 1050 return; 1051 } 1052 1053 assert(ofs % 8 == 0); 1054 switch (len) { 1055 case 8: 1056 /* uxtb */ 1057 tcg_out32(s, 0x06ef0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn); 1058 break; 1059 case 16: 1060 /* uxth */ 1061 tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn); 1062 break; 1063 default: 1064 g_assert_not_reached(); 1065 } 1066} 1067 1068static void tcg_out_sextract(TCGContext *s, ARMCond cond, TCGReg rd, 1069 TCGReg rn, int ofs, int len) 1070{ 1071 if (use_armv7_instructions) { 1072 /* sbfx */ 1073 tcg_out32(s, 0x07a00050 | (cond << 28) | (rd << 12) | rn 1074 | (ofs << 7) | ((len - 1) << 16)); 1075 return; 1076 } 1077 1078 assert(ofs % 8 == 0); 1079 switch (len) { 1080 case 8: 1081 /* sxtb */ 1082 tcg_out32(s, 0x06af0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn); 1083 break; 1084 case 16: 1085 /* sxth */ 1086 tcg_out32(s, 0x06bf0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn); 1087 break; 1088 default: 1089 g_assert_not_reached(); 1090 } 1091} 1092 1093 1094static void tcg_out_ld32u(TCGContext *s, ARMCond cond, 1095 TCGReg rd, TCGReg rn, int32_t offset) 1096{ 1097 if (offset > 0xfff || offset < -0xfff) { 1098 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1099 tcg_out_ld32_r(s, cond, rd, rn, TCG_REG_TMP); 1100 } else 1101 tcg_out_ld32_12(s, cond, rd, rn, offset); 1102} 1103 1104static void tcg_out_st32(TCGContext *s, ARMCond cond, 1105 TCGReg rd, TCGReg rn, int32_t offset) 1106{ 1107 if (offset > 0xfff || offset < -0xfff) { 1108 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1109 tcg_out_st32_r(s, cond, rd, rn, TCG_REG_TMP); 1110 } else 1111 tcg_out_st32_12(s, cond, rd, rn, offset); 1112} 1113 1114static void tcg_out_ld16u(TCGContext *s, ARMCond cond, 1115 TCGReg rd, TCGReg rn, int32_t offset) 1116{ 1117 if (offset > 0xff || offset < -0xff) { 1118 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1119 tcg_out_ld16u_r(s, cond, rd, rn, TCG_REG_TMP); 1120 } else 1121 tcg_out_ld16u_8(s, cond, rd, rn, offset); 1122} 1123 1124static void tcg_out_ld16s(TCGContext *s, ARMCond cond, 1125 TCGReg rd, TCGReg rn, int32_t offset) 1126{ 1127 if (offset > 0xff || offset < -0xff) { 1128 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1129 tcg_out_ld16s_r(s, cond, rd, rn, TCG_REG_TMP); 1130 } else 1131 tcg_out_ld16s_8(s, cond, rd, rn, offset); 1132} 1133 1134static void tcg_out_st16(TCGContext *s, ARMCond cond, 1135 TCGReg rd, TCGReg rn, int32_t offset) 1136{ 1137 if (offset > 0xff || offset < -0xff) { 1138 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1139 tcg_out_st16_r(s, cond, rd, rn, TCG_REG_TMP); 1140 } else 1141 tcg_out_st16_8(s, cond, rd, rn, offset); 1142} 1143 1144static void tcg_out_ld8u(TCGContext *s, ARMCond cond, 1145 TCGReg rd, TCGReg rn, int32_t offset) 1146{ 1147 if (offset > 0xfff || offset < -0xfff) { 1148 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1149 tcg_out_ld8_r(s, cond, rd, rn, TCG_REG_TMP); 1150 } else 1151 tcg_out_ld8_12(s, cond, rd, rn, offset); 1152} 1153 1154static void tcg_out_ld8s(TCGContext *s, ARMCond cond, 1155 TCGReg rd, TCGReg rn, int32_t offset) 1156{ 1157 if (offset > 0xff || offset < -0xff) { 1158 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1159 tcg_out_ld8s_r(s, cond, rd, rn, TCG_REG_TMP); 1160 } else 1161 tcg_out_ld8s_8(s, cond, rd, rn, offset); 1162} 1163 1164static void tcg_out_st8(TCGContext *s, ARMCond cond, 1165 TCGReg rd, TCGReg rn, int32_t offset) 1166{ 1167 if (offset > 0xfff || offset < -0xfff) { 1168 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1169 tcg_out_st8_r(s, cond, rd, rn, TCG_REG_TMP); 1170 } else 1171 tcg_out_st8_12(s, cond, rd, rn, offset); 1172} 1173 1174/* 1175 * The _goto case is normally between TBs within the same code buffer, and 1176 * with the code buffer limited to 16MB we wouldn't need the long case. 1177 * But we also use it for the tail-call to the qemu_ld/st helpers, which does. 1178 */ 1179static void tcg_out_goto(TCGContext *s, ARMCond cond, const tcg_insn_unit *addr) 1180{ 1181 intptr_t addri = (intptr_t)addr; 1182 ptrdiff_t disp = tcg_pcrel_diff(s, addr); 1183 bool arm_mode = !(addri & 1); 1184 1185 if (arm_mode && disp - 8 < 0x01fffffd && disp - 8 > -0x01fffffd) { 1186 tcg_out_b_imm(s, cond, disp); 1187 return; 1188 } 1189 1190 /* LDR is interworking from v5t. */ 1191 tcg_out_movi_pool(s, cond, TCG_REG_PC, addri); 1192} 1193 1194/* 1195 * The call case is mostly used for helpers - so it's not unreasonable 1196 * for them to be beyond branch range. 1197 */ 1198static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *addr) 1199{ 1200 intptr_t addri = (intptr_t)addr; 1201 ptrdiff_t disp = tcg_pcrel_diff(s, addr); 1202 bool arm_mode = !(addri & 1); 1203 1204 if (disp - 8 < 0x02000000 && disp - 8 >= -0x02000000) { 1205 if (arm_mode) { 1206 tcg_out_bl_imm(s, COND_AL, disp); 1207 } else { 1208 tcg_out_blx_imm(s, disp); 1209 } 1210 return; 1211 } 1212 1213 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri); 1214 tcg_out_blx_reg(s, COND_AL, TCG_REG_TMP); 1215} 1216 1217static void tcg_out_call(TCGContext *s, const tcg_insn_unit *addr, 1218 const TCGHelperInfo *info) 1219{ 1220 tcg_out_call_int(s, addr); 1221} 1222 1223static void tcg_out_goto_label(TCGContext *s, ARMCond cond, TCGLabel *l) 1224{ 1225 if (l->has_value) { 1226 tcg_out_goto(s, cond, l->u.value_ptr); 1227 } else { 1228 tcg_out_reloc(s, s->code_ptr, R_ARM_PC24, l, 0); 1229 tcg_out_b_imm(s, cond, 0); 1230 } 1231} 1232 1233static void tcg_out_mb(TCGContext *s, TCGArg a0) 1234{ 1235 if (use_armv7_instructions) { 1236 tcg_out32(s, INSN_DMB_ISH); 1237 } else { 1238 tcg_out32(s, INSN_DMB_MCR); 1239 } 1240} 1241 1242static TCGCond tcg_out_cmp(TCGContext *s, TCGCond cond, TCGReg a, 1243 TCGArg b, int b_const) 1244{ 1245 if (!is_tst_cond(cond)) { 1246 tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, a, b, b_const); 1247 return cond; 1248 } 1249 1250 cond = tcg_tst_eqne_cond(cond); 1251 if (b_const) { 1252 int imm12 = encode_imm(b); 1253 1254 /* 1255 * The compare constraints allow rIN, but TST does not support N. 1256 * Be prepared to load the constant into a scratch register. 1257 */ 1258 if (imm12 >= 0) { 1259 tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, a, imm12); 1260 return cond; 1261 } 1262 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, b); 1263 b = TCG_REG_TMP; 1264 } 1265 tcg_out_dat_reg(s, COND_AL, ARITH_TST, 0, a, b, SHIFT_IMM_LSL(0)); 1266 return cond; 1267} 1268 1269static TCGCond tcg_out_cmp2(TCGContext *s, const TCGArg *args, 1270 const int *const_args) 1271{ 1272 TCGReg al = args[0]; 1273 TCGReg ah = args[1]; 1274 TCGArg bl = args[2]; 1275 TCGArg bh = args[3]; 1276 TCGCond cond = args[4]; 1277 int const_bl = const_args[2]; 1278 int const_bh = const_args[3]; 1279 1280 switch (cond) { 1281 case TCG_COND_EQ: 1282 case TCG_COND_NE: 1283 case TCG_COND_LTU: 1284 case TCG_COND_LEU: 1285 case TCG_COND_GTU: 1286 case TCG_COND_GEU: 1287 /* 1288 * We perform a conditional comparison. If the high half is 1289 * equal, then overwrite the flags with the comparison of the 1290 * low half. The resulting flags cover the whole. 1291 */ 1292 tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, ah, bh, const_bh); 1293 tcg_out_dat_rI(s, COND_EQ, ARITH_CMP, 0, al, bl, const_bl); 1294 return cond; 1295 1296 case TCG_COND_TSTEQ: 1297 case TCG_COND_TSTNE: 1298 /* Similar, but with TST instead of CMP. */ 1299 tcg_out_dat_rI(s, COND_AL, ARITH_TST, 0, ah, bh, const_bh); 1300 tcg_out_dat_rI(s, COND_EQ, ARITH_TST, 0, al, bl, const_bl); 1301 return tcg_tst_eqne_cond(cond); 1302 1303 case TCG_COND_LT: 1304 case TCG_COND_GE: 1305 /* We perform a double-word subtraction and examine the result. 1306 We do not actually need the result of the subtract, so the 1307 low part "subtract" is a compare. For the high half we have 1308 no choice but to compute into a temporary. */ 1309 tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, al, bl, const_bl); 1310 tcg_out_dat_rI(s, COND_AL, ARITH_SBC | TO_CPSR, 1311 TCG_REG_TMP, ah, bh, const_bh); 1312 return cond; 1313 1314 case TCG_COND_LE: 1315 case TCG_COND_GT: 1316 /* Similar, but with swapped arguments, via reversed subtract. */ 1317 tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR, 1318 TCG_REG_TMP, al, bl, const_bl); 1319 tcg_out_dat_rI(s, COND_AL, ARITH_RSC | TO_CPSR, 1320 TCG_REG_TMP, ah, bh, const_bh); 1321 return tcg_swap_cond(cond); 1322 1323 default: 1324 g_assert_not_reached(); 1325 } 1326} 1327 1328/* 1329 * Note that TCGReg references Q-registers. 1330 * Q-regno = 2 * D-regno, so shift left by 1 while inserting. 1331 */ 1332static uint32_t encode_vd(TCGReg rd) 1333{ 1334 tcg_debug_assert(rd >= TCG_REG_Q0); 1335 return (extract32(rd, 3, 1) << 22) | (extract32(rd, 0, 3) << 13); 1336} 1337 1338static uint32_t encode_vn(TCGReg rn) 1339{ 1340 tcg_debug_assert(rn >= TCG_REG_Q0); 1341 return (extract32(rn, 3, 1) << 7) | (extract32(rn, 0, 3) << 17); 1342} 1343 1344static uint32_t encode_vm(TCGReg rm) 1345{ 1346 tcg_debug_assert(rm >= TCG_REG_Q0); 1347 return (extract32(rm, 3, 1) << 5) | (extract32(rm, 0, 3) << 1); 1348} 1349 1350static void tcg_out_vreg2(TCGContext *s, ARMInsn insn, int q, int vece, 1351 TCGReg d, TCGReg m) 1352{ 1353 tcg_out32(s, insn | (vece << 18) | (q << 6) | 1354 encode_vd(d) | encode_vm(m)); 1355} 1356 1357static void tcg_out_vreg3(TCGContext *s, ARMInsn insn, int q, int vece, 1358 TCGReg d, TCGReg n, TCGReg m) 1359{ 1360 tcg_out32(s, insn | (vece << 20) | (q << 6) | 1361 encode_vd(d) | encode_vn(n) | encode_vm(m)); 1362} 1363 1364static void tcg_out_vmovi(TCGContext *s, TCGReg rd, 1365 int q, int op, int cmode, uint8_t imm8) 1366{ 1367 tcg_out32(s, INSN_VMOVI | encode_vd(rd) | (q << 6) | (op << 5) 1368 | (cmode << 8) | extract32(imm8, 0, 4) 1369 | (extract32(imm8, 4, 3) << 16) 1370 | (extract32(imm8, 7, 1) << 24)); 1371} 1372 1373static void tcg_out_vshifti(TCGContext *s, ARMInsn insn, int q, 1374 TCGReg rd, TCGReg rm, int l_imm6) 1375{ 1376 tcg_out32(s, insn | (q << 6) | encode_vd(rd) | encode_vm(rm) | 1377 (extract32(l_imm6, 6, 1) << 7) | 1378 (extract32(l_imm6, 0, 6) << 16)); 1379} 1380 1381static void tcg_out_vldst(TCGContext *s, ARMInsn insn, 1382 TCGReg rd, TCGReg rn, int offset) 1383{ 1384 if (offset != 0) { 1385 if (check_fit_imm(offset) || check_fit_imm(-offset)) { 1386 tcg_out_dat_rIN(s, COND_AL, ARITH_ADD, ARITH_SUB, 1387 TCG_REG_TMP, rn, offset, true); 1388 } else { 1389 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, offset); 1390 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, 1391 TCG_REG_TMP, TCG_REG_TMP, rn, 0); 1392 } 1393 rn = TCG_REG_TMP; 1394 } 1395 tcg_out32(s, insn | (rn << 16) | encode_vd(rd) | 0xf); 1396} 1397 1398typedef struct { 1399 ARMCond cond; 1400 TCGReg base; 1401 int index; 1402 bool index_scratch; 1403 TCGAtomAlign aa; 1404} HostAddress; 1405 1406bool tcg_target_has_memory_bswap(MemOp memop) 1407{ 1408 return false; 1409} 1410 1411static TCGReg ldst_ra_gen(TCGContext *s, const TCGLabelQemuLdst *l, int arg) 1412{ 1413 /* We arrive at the slow path via "BLNE", so R14 contains l->raddr. */ 1414 return TCG_REG_R14; 1415} 1416 1417static const TCGLdstHelperParam ldst_helper_param = { 1418 .ra_gen = ldst_ra_gen, 1419 .ntmp = 1, 1420 .tmp = { TCG_REG_TMP }, 1421}; 1422 1423static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1424{ 1425 MemOp opc = get_memop(lb->oi); 1426 1427 if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1428 return false; 1429 } 1430 1431 tcg_out_ld_helper_args(s, lb, &ldst_helper_param); 1432 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE]); 1433 tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param); 1434 1435 tcg_out_goto(s, COND_AL, lb->raddr); 1436 return true; 1437} 1438 1439static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1440{ 1441 MemOp opc = get_memop(lb->oi); 1442 1443 if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1444 return false; 1445 } 1446 1447 tcg_out_st_helper_args(s, lb, &ldst_helper_param); 1448 1449 /* Tail-call to the helper, which will return to the fast path. */ 1450 tcg_out_goto(s, COND_AL, qemu_st_helpers[opc & MO_SIZE]); 1451 return true; 1452} 1453 1454/* We expect to use an 9-bit sign-magnitude negative offset from ENV. */ 1455#define MIN_TLB_MASK_TABLE_OFS -256 1456 1457static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1458 TCGReg addr, MemOpIdx oi, bool is_ld) 1459{ 1460 TCGLabelQemuLdst *ldst = NULL; 1461 MemOp opc = get_memop(oi); 1462 unsigned a_mask; 1463 1464 if (tcg_use_softmmu) { 1465 *h = (HostAddress){ 1466 .cond = COND_AL, 1467 .base = addr, 1468 .index = TCG_REG_R1, 1469 .index_scratch = true, 1470 }; 1471 } else { 1472 *h = (HostAddress){ 1473 .cond = COND_AL, 1474 .base = addr, 1475 .index = guest_base ? TCG_REG_GUEST_BASE : -1, 1476 .index_scratch = false, 1477 }; 1478 } 1479 1480 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); 1481 a_mask = (1 << h->aa.align) - 1; 1482 1483 if (tcg_use_softmmu) { 1484 int mem_index = get_mmuidx(oi); 1485 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read) 1486 : offsetof(CPUTLBEntry, addr_write); 1487 int fast_off = tlb_mask_table_ofs(s, mem_index); 1488 unsigned s_mask = (1 << (opc & MO_SIZE)) - 1; 1489 TCGReg t_addr; 1490 1491 ldst = new_ldst_label(s); 1492 ldst->is_ld = is_ld; 1493 ldst->oi = oi; 1494 ldst->addr_reg = addr; 1495 1496 /* Load cpu->neg.tlb.f[mmu_idx].{mask,table} into {r0,r1}. */ 1497 QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0); 1498 QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != 4); 1499 tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off); 1500 1501 /* Extract the tlb index from the address into R0. */ 1502 tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, addr, 1503 SHIFT_IMM_LSR(s->page_bits - CPU_TLB_ENTRY_BITS)); 1504 1505 /* 1506 * Add the tlb_table pointer, creating the CPUTLBEntry address in R1. 1507 * Load the tlb comparator into R2 and the fast path addend into R1. 1508 */ 1509 if (cmp_off == 0) { 1510 tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0); 1511 } else { 1512 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, 1513 TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0); 1514 tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); 1515 } 1516 1517 /* Load the tlb addend. */ 1518 tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R1, 1519 offsetof(CPUTLBEntry, addend)); 1520 1521 /* 1522 * Check alignment, check comparators. 1523 * Do this in 2-4 insns. Use MOVW for v7, if possible, 1524 * to reduce the number of sequential conditional instructions. 1525 * Almost all guests have at least 4k pages, which means that we need 1526 * to clear at least 9 bits even for an 8-byte memory, which means it 1527 * isn't worth checking for an immediate operand for BIC. 1528 * 1529 * For unaligned accesses, test the page of the last unit of alignment. 1530 * This leaves the least significant alignment bits unchanged, and of 1531 * course must be zero. 1532 */ 1533 t_addr = addr; 1534 if (a_mask < s_mask) { 1535 t_addr = TCG_REG_R0; 1536 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, t_addr, 1537 addr, s_mask - a_mask); 1538 } 1539 if (use_armv7_instructions && s->page_bits <= 16) { 1540 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, ~(s->page_mask | a_mask)); 1541 tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP, 1542 t_addr, TCG_REG_TMP, 0); 1543 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, 1544 TCG_REG_R2, TCG_REG_TMP, 0); 1545 } else { 1546 if (a_mask) { 1547 tcg_debug_assert(a_mask <= 0xff); 1548 tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addr, a_mask); 1549 } 1550 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, t_addr, 1551 SHIFT_IMM_LSR(s->page_bits)); 1552 tcg_out_dat_reg(s, (a_mask ? COND_EQ : COND_AL), ARITH_CMP, 1553 0, TCG_REG_R2, TCG_REG_TMP, 1554 SHIFT_IMM_LSL(s->page_bits)); 1555 } 1556 } else if (a_mask) { 1557 ldst = new_ldst_label(s); 1558 ldst->is_ld = is_ld; 1559 ldst->oi = oi; 1560 ldst->addr_reg = addr; 1561 1562 /* We are expecting alignment to max out at 7 */ 1563 tcg_debug_assert(a_mask <= 0xff); 1564 /* tst addr, #mask */ 1565 tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addr, a_mask); 1566 } 1567 1568 return ldst; 1569} 1570 1571static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo, 1572 TCGReg datahi, HostAddress h) 1573{ 1574 TCGReg base; 1575 1576 /* Byte swapping is left to middle-end expansion. */ 1577 tcg_debug_assert((opc & MO_BSWAP) == 0); 1578 1579 switch (opc & MO_SSIZE) { 1580 case MO_UB: 1581 if (h.index < 0) { 1582 tcg_out_ld8_12(s, h.cond, datalo, h.base, 0); 1583 } else { 1584 tcg_out_ld8_r(s, h.cond, datalo, h.base, h.index); 1585 } 1586 break; 1587 case MO_SB: 1588 if (h.index < 0) { 1589 tcg_out_ld8s_8(s, h.cond, datalo, h.base, 0); 1590 } else { 1591 tcg_out_ld8s_r(s, h.cond, datalo, h.base, h.index); 1592 } 1593 break; 1594 case MO_UW: 1595 if (h.index < 0) { 1596 tcg_out_ld16u_8(s, h.cond, datalo, h.base, 0); 1597 } else { 1598 tcg_out_ld16u_r(s, h.cond, datalo, h.base, h.index); 1599 } 1600 break; 1601 case MO_SW: 1602 if (h.index < 0) { 1603 tcg_out_ld16s_8(s, h.cond, datalo, h.base, 0); 1604 } else { 1605 tcg_out_ld16s_r(s, h.cond, datalo, h.base, h.index); 1606 } 1607 break; 1608 case MO_UL: 1609 if (h.index < 0) { 1610 tcg_out_ld32_12(s, h.cond, datalo, h.base, 0); 1611 } else { 1612 tcg_out_ld32_r(s, h.cond, datalo, h.base, h.index); 1613 } 1614 break; 1615 case MO_UQ: 1616 /* We used pair allocation for datalo, so already should be aligned. */ 1617 tcg_debug_assert((datalo & 1) == 0); 1618 tcg_debug_assert(datahi == datalo + 1); 1619 /* LDRD requires alignment; double-check that. */ 1620 if (memop_alignment_bits(opc) >= MO_64) { 1621 if (h.index < 0) { 1622 tcg_out_ldrd_8(s, h.cond, datalo, h.base, 0); 1623 break; 1624 } 1625 /* 1626 * Rm (the second address op) must not overlap Rt or Rt + 1. 1627 * Since datalo is aligned, we can simplify the test via alignment. 1628 * Flip the two address arguments if that works. 1629 */ 1630 if ((h.index & ~1) != datalo) { 1631 tcg_out_ldrd_r(s, h.cond, datalo, h.base, h.index); 1632 break; 1633 } 1634 if ((h.base & ~1) != datalo) { 1635 tcg_out_ldrd_r(s, h.cond, datalo, h.index, h.base); 1636 break; 1637 } 1638 } 1639 if (h.index < 0) { 1640 base = h.base; 1641 if (datalo == h.base) { 1642 tcg_out_mov_reg(s, h.cond, TCG_REG_TMP, base); 1643 base = TCG_REG_TMP; 1644 } 1645 } else if (h.index_scratch) { 1646 tcg_out_ld32_rwb(s, h.cond, datalo, h.index, h.base); 1647 tcg_out_ld32_12(s, h.cond, datahi, h.index, 4); 1648 break; 1649 } else { 1650 tcg_out_dat_reg(s, h.cond, ARITH_ADD, TCG_REG_TMP, 1651 h.base, h.index, SHIFT_IMM_LSL(0)); 1652 base = TCG_REG_TMP; 1653 } 1654 tcg_out_ld32_12(s, h.cond, datalo, base, 0); 1655 tcg_out_ld32_12(s, h.cond, datahi, base, 4); 1656 break; 1657 default: 1658 g_assert_not_reached(); 1659 } 1660} 1661 1662static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, 1663 TCGReg addr, MemOpIdx oi, TCGType data_type) 1664{ 1665 MemOp opc = get_memop(oi); 1666 TCGLabelQemuLdst *ldst; 1667 HostAddress h; 1668 1669 ldst = prepare_host_addr(s, &h, addr, oi, true); 1670 if (ldst) { 1671 ldst->type = data_type; 1672 ldst->datalo_reg = datalo; 1673 ldst->datahi_reg = datahi; 1674 1675 /* 1676 * This a conditional BL only to load a pointer within this 1677 * opcode into LR for the slow path. We will not be using 1678 * the value for a tail call. 1679 */ 1680 ldst->label_ptr[0] = s->code_ptr; 1681 tcg_out_bl_imm(s, COND_NE, 0); 1682 1683 tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); 1684 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1685 } else { 1686 tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); 1687 } 1688} 1689 1690static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo, 1691 TCGReg datahi, HostAddress h) 1692{ 1693 /* Byte swapping is left to middle-end expansion. */ 1694 tcg_debug_assert((opc & MO_BSWAP) == 0); 1695 1696 switch (opc & MO_SIZE) { 1697 case MO_8: 1698 if (h.index < 0) { 1699 tcg_out_st8_12(s, h.cond, datalo, h.base, 0); 1700 } else { 1701 tcg_out_st8_r(s, h.cond, datalo, h.base, h.index); 1702 } 1703 break; 1704 case MO_16: 1705 if (h.index < 0) { 1706 tcg_out_st16_8(s, h.cond, datalo, h.base, 0); 1707 } else { 1708 tcg_out_st16_r(s, h.cond, datalo, h.base, h.index); 1709 } 1710 break; 1711 case MO_32: 1712 if (h.index < 0) { 1713 tcg_out_st32_12(s, h.cond, datalo, h.base, 0); 1714 } else { 1715 tcg_out_st32_r(s, h.cond, datalo, h.base, h.index); 1716 } 1717 break; 1718 case MO_64: 1719 /* We used pair allocation for datalo, so already should be aligned. */ 1720 tcg_debug_assert((datalo & 1) == 0); 1721 tcg_debug_assert(datahi == datalo + 1); 1722 /* STRD requires alignment; double-check that. */ 1723 if (memop_alignment_bits(opc) >= MO_64) { 1724 if (h.index < 0) { 1725 tcg_out_strd_8(s, h.cond, datalo, h.base, 0); 1726 } else { 1727 tcg_out_strd_r(s, h.cond, datalo, h.base, h.index); 1728 } 1729 } else if (h.index < 0) { 1730 tcg_out_st32_12(s, h.cond, datalo, h.base, 0); 1731 tcg_out_st32_12(s, h.cond, datahi, h.base, 4); 1732 } else if (h.index_scratch) { 1733 tcg_out_st32_rwb(s, h.cond, datalo, h.index, h.base); 1734 tcg_out_st32_12(s, h.cond, datahi, h.index, 4); 1735 } else { 1736 tcg_out_dat_reg(s, h.cond, ARITH_ADD, TCG_REG_TMP, 1737 h.base, h.index, SHIFT_IMM_LSL(0)); 1738 tcg_out_st32_12(s, h.cond, datalo, TCG_REG_TMP, 0); 1739 tcg_out_st32_12(s, h.cond, datahi, TCG_REG_TMP, 4); 1740 } 1741 break; 1742 default: 1743 g_assert_not_reached(); 1744 } 1745} 1746 1747static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, 1748 TCGReg addr, MemOpIdx oi, TCGType data_type) 1749{ 1750 MemOp opc = get_memop(oi); 1751 TCGLabelQemuLdst *ldst; 1752 HostAddress h; 1753 1754 ldst = prepare_host_addr(s, &h, addr, oi, false); 1755 if (ldst) { 1756 ldst->type = data_type; 1757 ldst->datalo_reg = datalo; 1758 ldst->datahi_reg = datahi; 1759 1760 h.cond = COND_EQ; 1761 tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); 1762 1763 /* The conditional call is last, as we're going to return here. */ 1764 ldst->label_ptr[0] = s->code_ptr; 1765 tcg_out_bl_imm(s, COND_NE, 0); 1766 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1767 } else { 1768 tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); 1769 } 1770} 1771 1772static void tcg_out_epilogue(TCGContext *s); 1773 1774static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg) 1775{ 1776 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, arg); 1777 tcg_out_epilogue(s); 1778} 1779 1780static void tcg_out_goto_tb(TCGContext *s, int which) 1781{ 1782 uintptr_t i_addr; 1783 intptr_t i_disp; 1784 1785 /* Direct branch will be patched by tb_target_set_jmp_target. */ 1786 set_jmp_insn_offset(s, which); 1787 tcg_out32(s, INSN_NOP); 1788 1789 /* When branch is out of range, fall through to indirect. */ 1790 i_addr = get_jmp_target_addr(s, which); 1791 i_disp = tcg_pcrel_diff(s, (void *)i_addr) - 8; 1792 tcg_debug_assert(i_disp < 0); 1793 if (i_disp >= -0xfff) { 1794 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, i_disp); 1795 } else { 1796 /* 1797 * The TB is close, but outside the 12 bits addressable by 1798 * the load. We can extend this to 20 bits with a sub of a 1799 * shifted immediate from pc. 1800 */ 1801 int h = -i_disp; 1802 int l = -(h & 0xfff); 1803 1804 h = encode_imm_nofail(h + l); 1805 tcg_out_dat_imm(s, COND_AL, ARITH_SUB, TCG_REG_R0, TCG_REG_PC, h); 1806 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_R0, l); 1807 } 1808 set_jmp_reset_offset(s, which); 1809} 1810 1811void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1812 uintptr_t jmp_rx, uintptr_t jmp_rw) 1813{ 1814 uintptr_t addr = tb->jmp_target_addr[n]; 1815 ptrdiff_t offset = addr - (jmp_rx + 8); 1816 tcg_insn_unit insn; 1817 1818 /* Either directly branch, or fall through to indirect branch. */ 1819 if (offset == sextract64(offset, 0, 26)) { 1820 /* B <addr> */ 1821 insn = deposit32((COND_AL << 28) | INSN_B, 0, 24, offset >> 2); 1822 } else { 1823 insn = INSN_NOP; 1824 } 1825 1826 qatomic_set((uint32_t *)jmp_rw, insn); 1827 flush_idcache_range(jmp_rx, jmp_rw, 4); 1828} 1829 1830 1831static void tgen_add(TCGContext *s, TCGType type, 1832 TCGReg a0, TCGReg a1, TCGReg a2) 1833{ 1834 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, a0, a1, a2, SHIFT_IMM_LSL(0)); 1835} 1836 1837static void tgen_addi(TCGContext *s, TCGType type, 1838 TCGReg a0, TCGReg a1, tcg_target_long a2) 1839{ 1840 tcg_out_dat_IN(s, COND_AL, ARITH_ADD, ARITH_SUB, a0, a1, a2); 1841} 1842 1843static const TCGOutOpBinary outop_add = { 1844 .base.static_constraint = C_O1_I2(r, r, rIN), 1845 .out_rrr = tgen_add, 1846 .out_rri = tgen_addi, 1847}; 1848 1849 1850static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, 1851 const TCGArg args[TCG_MAX_OP_ARGS], 1852 const int const_args[TCG_MAX_OP_ARGS]) 1853{ 1854 TCGArg a0, a1, a2, a3, a4, a5; 1855 int c; 1856 1857 switch (opc) { 1858 case INDEX_op_goto_ptr: 1859 tcg_out_b_reg(s, COND_AL, args[0]); 1860 break; 1861 case INDEX_op_br: 1862 tcg_out_goto_label(s, COND_AL, arg_label(args[0])); 1863 break; 1864 1865 case INDEX_op_ld8u_i32: 1866 tcg_out_ld8u(s, COND_AL, args[0], args[1], args[2]); 1867 break; 1868 case INDEX_op_ld8s_i32: 1869 tcg_out_ld8s(s, COND_AL, args[0], args[1], args[2]); 1870 break; 1871 case INDEX_op_ld16u_i32: 1872 tcg_out_ld16u(s, COND_AL, args[0], args[1], args[2]); 1873 break; 1874 case INDEX_op_ld16s_i32: 1875 tcg_out_ld16s(s, COND_AL, args[0], args[1], args[2]); 1876 break; 1877 case INDEX_op_ld_i32: 1878 tcg_out_ld32u(s, COND_AL, args[0], args[1], args[2]); 1879 break; 1880 case INDEX_op_st8_i32: 1881 tcg_out_st8(s, COND_AL, args[0], args[1], args[2]); 1882 break; 1883 case INDEX_op_st16_i32: 1884 tcg_out_st16(s, COND_AL, args[0], args[1], args[2]); 1885 break; 1886 case INDEX_op_st_i32: 1887 tcg_out_st32(s, COND_AL, args[0], args[1], args[2]); 1888 break; 1889 1890 case INDEX_op_movcond_i32: 1891 /* Constraints mean that v2 is always in the same register as dest, 1892 * so we only need to do "if condition passed, move v1 to dest". 1893 */ 1894 c = tcg_out_cmp(s, args[5], args[1], args[2], const_args[2]); 1895 tcg_out_dat_rIK(s, tcg_cond_to_arm_cond[c], ARITH_MOV, 1896 ARITH_MVN, args[0], 0, args[3], const_args[3]); 1897 break; 1898 case INDEX_op_sub_i32: 1899 if (const_args[1]) { 1900 if (const_args[2]) { 1901 tcg_out_movi32(s, COND_AL, args[0], args[1] - args[2]); 1902 } else { 1903 tcg_out_dat_rI(s, COND_AL, ARITH_RSB, 1904 args[0], args[2], args[1], 1); 1905 } 1906 } else { 1907 tcg_out_dat_rIN(s, COND_AL, ARITH_SUB, ARITH_ADD, 1908 args[0], args[1], args[2], const_args[2]); 1909 } 1910 break; 1911 case INDEX_op_and_i32: 1912 tcg_out_dat_rIK(s, COND_AL, ARITH_AND, ARITH_BIC, 1913 args[0], args[1], args[2], const_args[2]); 1914 break; 1915 case INDEX_op_andc_i32: 1916 tcg_out_dat_rIK(s, COND_AL, ARITH_BIC, ARITH_AND, 1917 args[0], args[1], args[2], const_args[2]); 1918 break; 1919 case INDEX_op_or_i32: 1920 c = ARITH_ORR; 1921 goto gen_arith; 1922 case INDEX_op_xor_i32: 1923 c = ARITH_EOR; 1924 /* Fall through. */ 1925 gen_arith: 1926 tcg_out_dat_rI(s, COND_AL, c, args[0], args[1], args[2], const_args[2]); 1927 break; 1928 case INDEX_op_add2_i32: 1929 a0 = args[0], a1 = args[1], a2 = args[2]; 1930 a3 = args[3], a4 = args[4], a5 = args[5]; 1931 if (a0 == a3 || (a0 == a5 && !const_args[5])) { 1932 a0 = TCG_REG_TMP; 1933 } 1934 tcg_out_dat_rIN(s, COND_AL, ARITH_ADD | TO_CPSR, ARITH_SUB | TO_CPSR, 1935 a0, a2, a4, const_args[4]); 1936 tcg_out_dat_rIK(s, COND_AL, ARITH_ADC, ARITH_SBC, 1937 a1, a3, a5, const_args[5]); 1938 tcg_out_mov_reg(s, COND_AL, args[0], a0); 1939 break; 1940 case INDEX_op_sub2_i32: 1941 a0 = args[0], a1 = args[1], a2 = args[2]; 1942 a3 = args[3], a4 = args[4], a5 = args[5]; 1943 if ((a0 == a3 && !const_args[3]) || (a0 == a5 && !const_args[5])) { 1944 a0 = TCG_REG_TMP; 1945 } 1946 if (const_args[2]) { 1947 if (const_args[4]) { 1948 tcg_out_movi32(s, COND_AL, a0, a4); 1949 a4 = a0; 1950 } 1951 tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR, a0, a4, a2, 1); 1952 } else { 1953 tcg_out_dat_rIN(s, COND_AL, ARITH_SUB | TO_CPSR, 1954 ARITH_ADD | TO_CPSR, a0, a2, a4, const_args[4]); 1955 } 1956 if (const_args[3]) { 1957 if (const_args[5]) { 1958 tcg_out_movi32(s, COND_AL, a1, a5); 1959 a5 = a1; 1960 } 1961 tcg_out_dat_rI(s, COND_AL, ARITH_RSC, a1, a5, a3, 1); 1962 } else { 1963 tcg_out_dat_rIK(s, COND_AL, ARITH_SBC, ARITH_ADC, 1964 a1, a3, a5, const_args[5]); 1965 } 1966 tcg_out_mov_reg(s, COND_AL, args[0], a0); 1967 break; 1968 case INDEX_op_neg_i32: 1969 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, args[0], args[1], 0); 1970 break; 1971 case INDEX_op_not_i32: 1972 tcg_out_dat_reg(s, COND_AL, 1973 ARITH_MVN, args[0], 0, args[1], SHIFT_IMM_LSL(0)); 1974 break; 1975 case INDEX_op_mul_i32: 1976 tcg_out_mul32(s, COND_AL, args[0], args[1], args[2]); 1977 break; 1978 case INDEX_op_mulu2_i32: 1979 tcg_out_umull32(s, COND_AL, args[0], args[1], args[2], args[3]); 1980 break; 1981 case INDEX_op_muls2_i32: 1982 tcg_out_smull32(s, COND_AL, args[0], args[1], args[2], args[3]); 1983 break; 1984 /* XXX: Perhaps args[2] & 0x1f is wrong */ 1985 case INDEX_op_shl_i32: 1986 c = const_args[2] ? 1987 SHIFT_IMM_LSL(args[2] & 0x1f) : SHIFT_REG_LSL(args[2]); 1988 goto gen_shift32; 1989 case INDEX_op_shr_i32: 1990 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_LSR(args[2] & 0x1f) : 1991 SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args[2]); 1992 goto gen_shift32; 1993 case INDEX_op_sar_i32: 1994 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ASR(args[2] & 0x1f) : 1995 SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args[2]); 1996 goto gen_shift32; 1997 case INDEX_op_rotr_i32: 1998 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ROR(args[2] & 0x1f) : 1999 SHIFT_IMM_LSL(0) : SHIFT_REG_ROR(args[2]); 2000 /* Fall through. */ 2001 gen_shift32: 2002 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], c); 2003 break; 2004 2005 case INDEX_op_rotl_i32: 2006 if (const_args[2]) { 2007 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], 2008 ((0x20 - args[2]) & 0x1f) ? 2009 SHIFT_IMM_ROR((0x20 - args[2]) & 0x1f) : 2010 SHIFT_IMM_LSL(0)); 2011 } else { 2012 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, TCG_REG_TMP, args[2], 0x20); 2013 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], 2014 SHIFT_REG_ROR(TCG_REG_TMP)); 2015 } 2016 break; 2017 2018 case INDEX_op_ctz_i32: 2019 tcg_out_dat_reg(s, COND_AL, INSN_RBIT, TCG_REG_TMP, 0, args[1], 0); 2020 a1 = TCG_REG_TMP; 2021 goto do_clz; 2022 2023 case INDEX_op_clz_i32: 2024 a1 = args[1]; 2025 do_clz: 2026 a0 = args[0]; 2027 a2 = args[2]; 2028 c = const_args[2]; 2029 if (c && a2 == 32) { 2030 tcg_out_dat_reg(s, COND_AL, INSN_CLZ, a0, 0, a1, 0); 2031 break; 2032 } 2033 tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0, a1, 0); 2034 tcg_out_dat_reg(s, COND_NE, INSN_CLZ, a0, 0, a1, 0); 2035 if (c || a0 != a2) { 2036 tcg_out_dat_rIK(s, COND_EQ, ARITH_MOV, ARITH_MVN, a0, 0, a2, c); 2037 } 2038 break; 2039 2040 case INDEX_op_brcond_i32: 2041 c = tcg_out_cmp(s, args[2], args[0], args[1], const_args[1]); 2042 tcg_out_goto_label(s, tcg_cond_to_arm_cond[c], arg_label(args[3])); 2043 break; 2044 case INDEX_op_setcond_i32: 2045 c = tcg_out_cmp(s, args[3], args[1], args[2], const_args[2]); 2046 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[c], 2047 ARITH_MOV, args[0], 0, 1); 2048 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(c)], 2049 ARITH_MOV, args[0], 0, 0); 2050 break; 2051 case INDEX_op_negsetcond_i32: 2052 c = tcg_out_cmp(s, args[3], args[1], args[2], const_args[2]); 2053 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[c], 2054 ARITH_MVN, args[0], 0, 0); 2055 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(c)], 2056 ARITH_MOV, args[0], 0, 0); 2057 break; 2058 2059 case INDEX_op_brcond2_i32: 2060 c = tcg_out_cmp2(s, args, const_args); 2061 tcg_out_goto_label(s, tcg_cond_to_arm_cond[c], arg_label(args[5])); 2062 break; 2063 case INDEX_op_setcond2_i32: 2064 c = tcg_out_cmp2(s, args + 1, const_args + 1); 2065 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[c], ARITH_MOV, args[0], 0, 1); 2066 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(c)], 2067 ARITH_MOV, args[0], 0, 0); 2068 break; 2069 2070 case INDEX_op_qemu_ld_i32: 2071 tcg_out_qemu_ld(s, args[0], -1, args[1], args[2], TCG_TYPE_I32); 2072 break; 2073 case INDEX_op_qemu_ld_i64: 2074 tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3], TCG_TYPE_I64); 2075 break; 2076 2077 case INDEX_op_qemu_st_i32: 2078 tcg_out_qemu_st(s, args[0], -1, args[1], args[2], TCG_TYPE_I32); 2079 break; 2080 case INDEX_op_qemu_st_i64: 2081 tcg_out_qemu_st(s, args[0], args[1], args[2], args[3], TCG_TYPE_I64); 2082 break; 2083 2084 case INDEX_op_bswap16_i32: 2085 tcg_out_bswap16(s, COND_AL, args[0], args[1], args[2]); 2086 break; 2087 case INDEX_op_bswap32_i32: 2088 tcg_out_bswap32(s, COND_AL, args[0], args[1]); 2089 break; 2090 2091 case INDEX_op_deposit_i32: 2092 tcg_out_deposit(s, COND_AL, args[0], args[2], 2093 args[3], args[4], const_args[2]); 2094 break; 2095 case INDEX_op_extract_i32: 2096 tcg_out_extract(s, COND_AL, args[0], args[1], args[2], args[3]); 2097 break; 2098 case INDEX_op_sextract_i32: 2099 tcg_out_sextract(s, COND_AL, args[0], args[1], args[2], args[3]); 2100 break; 2101 case INDEX_op_extract2_i32: 2102 /* ??? These optimization vs zero should be generic. */ 2103 /* ??? But we can't substitute 2 for 1 in the opcode stream yet. */ 2104 if (const_args[1]) { 2105 if (const_args[2]) { 2106 tcg_out_movi(s, TCG_TYPE_REG, args[0], 0); 2107 } else { 2108 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, 2109 args[2], SHIFT_IMM_LSL(32 - args[3])); 2110 } 2111 } else if (const_args[2]) { 2112 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, 2113 args[1], SHIFT_IMM_LSR(args[3])); 2114 } else { 2115 /* We can do extract2 in 2 insns, vs the 3 required otherwise. */ 2116 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, 2117 args[2], SHIFT_IMM_LSL(32 - args[3])); 2118 tcg_out_dat_reg(s, COND_AL, ARITH_ORR, args[0], TCG_REG_TMP, 2119 args[1], SHIFT_IMM_LSR(args[3])); 2120 } 2121 break; 2122 2123 case INDEX_op_div_i32: 2124 tcg_out_sdiv(s, COND_AL, args[0], args[1], args[2]); 2125 break; 2126 case INDEX_op_divu_i32: 2127 tcg_out_udiv(s, COND_AL, args[0], args[1], args[2]); 2128 break; 2129 2130 case INDEX_op_mb: 2131 tcg_out_mb(s, args[0]); 2132 break; 2133 2134 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2135 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2136 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2137 default: 2138 g_assert_not_reached(); 2139 } 2140} 2141 2142static TCGConstraintSetIndex 2143tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) 2144{ 2145 switch (op) { 2146 case INDEX_op_goto_ptr: 2147 return C_O0_I1(r); 2148 2149 case INDEX_op_ld8u_i32: 2150 case INDEX_op_ld8s_i32: 2151 case INDEX_op_ld16u_i32: 2152 case INDEX_op_ld16s_i32: 2153 case INDEX_op_ld_i32: 2154 case INDEX_op_neg_i32: 2155 case INDEX_op_not_i32: 2156 case INDEX_op_bswap16_i32: 2157 case INDEX_op_bswap32_i32: 2158 case INDEX_op_extract_i32: 2159 case INDEX_op_sextract_i32: 2160 return C_O1_I1(r, r); 2161 2162 case INDEX_op_st8_i32: 2163 case INDEX_op_st16_i32: 2164 case INDEX_op_st_i32: 2165 return C_O0_I2(r, r); 2166 2167 case INDEX_op_sub_i32: 2168 case INDEX_op_setcond_i32: 2169 case INDEX_op_negsetcond_i32: 2170 return C_O1_I2(r, r, rIN); 2171 2172 case INDEX_op_and_i32: 2173 case INDEX_op_andc_i32: 2174 case INDEX_op_clz_i32: 2175 case INDEX_op_ctz_i32: 2176 return C_O1_I2(r, r, rIK); 2177 2178 case INDEX_op_mul_i32: 2179 case INDEX_op_div_i32: 2180 case INDEX_op_divu_i32: 2181 return C_O1_I2(r, r, r); 2182 2183 case INDEX_op_mulu2_i32: 2184 case INDEX_op_muls2_i32: 2185 return C_O2_I2(r, r, r, r); 2186 2187 case INDEX_op_or_i32: 2188 case INDEX_op_xor_i32: 2189 return C_O1_I2(r, r, rI); 2190 2191 case INDEX_op_shl_i32: 2192 case INDEX_op_shr_i32: 2193 case INDEX_op_sar_i32: 2194 case INDEX_op_rotl_i32: 2195 case INDEX_op_rotr_i32: 2196 return C_O1_I2(r, r, ri); 2197 2198 case INDEX_op_brcond_i32: 2199 return C_O0_I2(r, rIN); 2200 case INDEX_op_deposit_i32: 2201 return C_O1_I2(r, 0, rZ); 2202 case INDEX_op_extract2_i32: 2203 return C_O1_I2(r, rZ, rZ); 2204 case INDEX_op_movcond_i32: 2205 return C_O1_I4(r, r, rIN, rIK, 0); 2206 case INDEX_op_add2_i32: 2207 return C_O2_I4(r, r, r, r, rIN, rIK); 2208 case INDEX_op_sub2_i32: 2209 return C_O2_I4(r, r, rI, rI, rIN, rIK); 2210 case INDEX_op_brcond2_i32: 2211 return C_O0_I4(r, r, rI, rI); 2212 case INDEX_op_setcond2_i32: 2213 return C_O1_I4(r, r, r, rI, rI); 2214 2215 case INDEX_op_qemu_ld_i32: 2216 return C_O1_I1(r, q); 2217 case INDEX_op_qemu_ld_i64: 2218 return C_O2_I1(e, p, q); 2219 case INDEX_op_qemu_st_i32: 2220 return C_O0_I2(q, q); 2221 case INDEX_op_qemu_st_i64: 2222 return C_O0_I3(Q, p, q); 2223 2224 case INDEX_op_st_vec: 2225 return C_O0_I2(w, r); 2226 case INDEX_op_ld_vec: 2227 case INDEX_op_dupm_vec: 2228 return C_O1_I1(w, r); 2229 case INDEX_op_dup_vec: 2230 return C_O1_I1(w, wr); 2231 case INDEX_op_abs_vec: 2232 case INDEX_op_neg_vec: 2233 case INDEX_op_not_vec: 2234 case INDEX_op_shli_vec: 2235 case INDEX_op_shri_vec: 2236 case INDEX_op_sari_vec: 2237 return C_O1_I1(w, w); 2238 case INDEX_op_dup2_vec: 2239 case INDEX_op_add_vec: 2240 case INDEX_op_mul_vec: 2241 case INDEX_op_smax_vec: 2242 case INDEX_op_smin_vec: 2243 case INDEX_op_ssadd_vec: 2244 case INDEX_op_sssub_vec: 2245 case INDEX_op_sub_vec: 2246 case INDEX_op_umax_vec: 2247 case INDEX_op_umin_vec: 2248 case INDEX_op_usadd_vec: 2249 case INDEX_op_ussub_vec: 2250 case INDEX_op_xor_vec: 2251 case INDEX_op_arm_sshl_vec: 2252 case INDEX_op_arm_ushl_vec: 2253 return C_O1_I2(w, w, w); 2254 case INDEX_op_arm_sli_vec: 2255 return C_O1_I2(w, 0, w); 2256 case INDEX_op_or_vec: 2257 case INDEX_op_andc_vec: 2258 return C_O1_I2(w, w, wO); 2259 case INDEX_op_and_vec: 2260 case INDEX_op_orc_vec: 2261 return C_O1_I2(w, w, wV); 2262 case INDEX_op_cmp_vec: 2263 return C_O1_I2(w, w, wZ); 2264 case INDEX_op_bitsel_vec: 2265 return C_O1_I3(w, w, w, w); 2266 default: 2267 return C_NotImplemented; 2268 } 2269} 2270 2271static void tcg_target_init(TCGContext *s) 2272{ 2273 /* 2274 * Only probe for the platform and capabilities if we haven't already 2275 * determined maximum values at compile time. 2276 */ 2277#if !defined(use_idiv_instructions) || !defined(use_neon_instructions) 2278 { 2279 unsigned long hwcap = qemu_getauxval(AT_HWCAP); 2280#ifndef use_idiv_instructions 2281 use_idiv_instructions = (hwcap & HWCAP_ARM_IDIVA) != 0; 2282#endif 2283#ifndef use_neon_instructions 2284 use_neon_instructions = (hwcap & HWCAP_ARM_NEON) != 0; 2285#endif 2286 } 2287#endif 2288 2289 if (__ARM_ARCH < 7) { 2290 const char *pl = (const char *)qemu_getauxval(AT_PLATFORM); 2291 if (pl != NULL && pl[0] == 'v' && pl[1] >= '4' && pl[1] <= '9') { 2292 arm_arch = pl[1] - '0'; 2293 } 2294 2295 if (arm_arch < 6) { 2296 error_report("TCG: ARMv%d is unsupported; exiting", arm_arch); 2297 exit(EXIT_FAILURE); 2298 } 2299 } 2300 2301 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS; 2302 2303 tcg_target_call_clobber_regs = 0; 2304 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); 2305 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1); 2306 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2); 2307 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3); 2308 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12); 2309 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14); 2310 2311 if (use_neon_instructions) { 2312 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS; 2313 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS; 2314 2315 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q0); 2316 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q1); 2317 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q2); 2318 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q3); 2319 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q8); 2320 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q9); 2321 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q10); 2322 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q11); 2323 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q12); 2324 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q13); 2325 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q14); 2326 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q15); 2327 } 2328 2329 s->reserved_regs = 0; 2330 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); 2331 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP); 2332 tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC); 2333 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP); 2334} 2335 2336static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 2337 TCGReg arg1, intptr_t arg2) 2338{ 2339 switch (type) { 2340 case TCG_TYPE_I32: 2341 tcg_out_ld32u(s, COND_AL, arg, arg1, arg2); 2342 return; 2343 case TCG_TYPE_V64: 2344 /* regs 1; size 8; align 8 */ 2345 tcg_out_vldst(s, INSN_VLD1 | 0x7d0, arg, arg1, arg2); 2346 return; 2347 case TCG_TYPE_V128: 2348 /* 2349 * We have only 8-byte alignment for the stack per the ABI. 2350 * Rather than dynamically re-align the stack, it's easier 2351 * to simply not request alignment beyond that. So: 2352 * regs 2; size 8; align 8 2353 */ 2354 tcg_out_vldst(s, INSN_VLD1 | 0xad0, arg, arg1, arg2); 2355 return; 2356 default: 2357 g_assert_not_reached(); 2358 } 2359} 2360 2361static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 2362 TCGReg arg1, intptr_t arg2) 2363{ 2364 switch (type) { 2365 case TCG_TYPE_I32: 2366 tcg_out_st32(s, COND_AL, arg, arg1, arg2); 2367 return; 2368 case TCG_TYPE_V64: 2369 /* regs 1; size 8; align 8 */ 2370 tcg_out_vldst(s, INSN_VST1 | 0x7d0, arg, arg1, arg2); 2371 return; 2372 case TCG_TYPE_V128: 2373 /* See tcg_out_ld re alignment: regs 2; size 8; align 8 */ 2374 tcg_out_vldst(s, INSN_VST1 | 0xad0, arg, arg1, arg2); 2375 return; 2376 default: 2377 g_assert_not_reached(); 2378 } 2379} 2380 2381static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 2382 TCGReg base, intptr_t ofs) 2383{ 2384 return false; 2385} 2386 2387static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 2388{ 2389 if (ret == arg) { 2390 return true; 2391 } 2392 switch (type) { 2393 case TCG_TYPE_I32: 2394 if (ret < TCG_REG_Q0 && arg < TCG_REG_Q0) { 2395 tcg_out_mov_reg(s, COND_AL, ret, arg); 2396 return true; 2397 } 2398 return false; 2399 2400 case TCG_TYPE_V64: 2401 case TCG_TYPE_V128: 2402 /* "VMOV D,N" is an alias for "VORR D,N,N". */ 2403 tcg_out_vreg3(s, INSN_VORR, type - TCG_TYPE_V64, 0, ret, arg, arg); 2404 return true; 2405 2406 default: 2407 g_assert_not_reached(); 2408 } 2409} 2410 2411static void tcg_out_movi(TCGContext *s, TCGType type, 2412 TCGReg ret, tcg_target_long arg) 2413{ 2414 tcg_debug_assert(type == TCG_TYPE_I32); 2415 tcg_debug_assert(ret < TCG_REG_Q0); 2416 tcg_out_movi32(s, COND_AL, ret, arg); 2417} 2418 2419static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 2420{ 2421 return false; 2422} 2423 2424static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 2425 tcg_target_long imm) 2426{ 2427 int enc, opc = ARITH_ADD; 2428 2429 /* All of the easiest immediates to encode are positive. */ 2430 if (imm < 0) { 2431 imm = -imm; 2432 opc = ARITH_SUB; 2433 } 2434 enc = encode_imm(imm); 2435 if (enc >= 0) { 2436 tcg_out_dat_imm(s, COND_AL, opc, rd, rs, enc); 2437 } else { 2438 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, imm); 2439 tcg_out_dat_reg(s, COND_AL, opc, rd, rs, 2440 TCG_REG_TMP, SHIFT_IMM_LSL(0)); 2441 } 2442} 2443 2444/* Type is always V128, with I64 elements. */ 2445static void tcg_out_dup2_vec(TCGContext *s, TCGReg rd, TCGReg rl, TCGReg rh) 2446{ 2447 /* Move high element into place first. */ 2448 /* VMOV Dd+1, Ds */ 2449 tcg_out_vreg3(s, INSN_VORR | (1 << 12), 0, 0, rd, rh, rh); 2450 /* Move low element into place; tcg_out_mov will check for nop. */ 2451 tcg_out_mov(s, TCG_TYPE_V64, rd, rl); 2452} 2453 2454static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 2455 TCGReg rd, TCGReg rs) 2456{ 2457 int q = type - TCG_TYPE_V64; 2458 2459 if (vece == MO_64) { 2460 if (type == TCG_TYPE_V128) { 2461 tcg_out_dup2_vec(s, rd, rs, rs); 2462 } else { 2463 tcg_out_mov(s, TCG_TYPE_V64, rd, rs); 2464 } 2465 } else if (rs < TCG_REG_Q0) { 2466 int b = (vece == MO_8); 2467 int e = (vece == MO_16); 2468 tcg_out32(s, INSN_VDUP_G | (b << 22) | (q << 21) | (e << 5) | 2469 encode_vn(rd) | (rs << 12)); 2470 } else { 2471 int imm4 = 1 << vece; 2472 tcg_out32(s, INSN_VDUP_S | (imm4 << 16) | (q << 6) | 2473 encode_vd(rd) | encode_vm(rs)); 2474 } 2475 return true; 2476} 2477 2478static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 2479 TCGReg rd, TCGReg base, intptr_t offset) 2480{ 2481 if (vece == MO_64) { 2482 tcg_out_ld(s, TCG_TYPE_V64, rd, base, offset); 2483 if (type == TCG_TYPE_V128) { 2484 tcg_out_dup2_vec(s, rd, rd, rd); 2485 } 2486 } else { 2487 int q = type - TCG_TYPE_V64; 2488 tcg_out_vldst(s, INSN_VLD1R | (vece << 6) | (q << 5), 2489 rd, base, offset); 2490 } 2491 return true; 2492} 2493 2494static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 2495 TCGReg rd, int64_t v64) 2496{ 2497 int q = type - TCG_TYPE_V64; 2498 int cmode, imm8, i; 2499 2500 /* Test all bytes equal first. */ 2501 if (vece == MO_8) { 2502 tcg_out_vmovi(s, rd, q, 0, 0xe, v64); 2503 return; 2504 } 2505 2506 /* 2507 * Test all bytes 0x00 or 0xff second. This can match cases that 2508 * might otherwise take 2 or 3 insns for MO_16 or MO_32 below. 2509 */ 2510 for (i = imm8 = 0; i < 8; i++) { 2511 uint8_t byte = v64 >> (i * 8); 2512 if (byte == 0xff) { 2513 imm8 |= 1 << i; 2514 } else if (byte != 0) { 2515 goto fail_bytes; 2516 } 2517 } 2518 tcg_out_vmovi(s, rd, q, 1, 0xe, imm8); 2519 return; 2520 fail_bytes: 2521 2522 /* 2523 * Tests for various replications. For each element width, if we 2524 * cannot find an expansion there's no point checking a larger 2525 * width because we already know by replication it cannot match. 2526 */ 2527 if (vece == MO_16) { 2528 uint16_t v16 = v64; 2529 2530 if (is_shimm16(v16, &cmode, &imm8)) { 2531 tcg_out_vmovi(s, rd, q, 0, cmode, imm8); 2532 return; 2533 } 2534 if (is_shimm16(~v16, &cmode, &imm8)) { 2535 tcg_out_vmovi(s, rd, q, 1, cmode, imm8); 2536 return; 2537 } 2538 2539 /* 2540 * Otherwise, all remaining constants can be loaded in two insns: 2541 * rd = v16 & 0xff, rd |= v16 & 0xff00. 2542 */ 2543 tcg_out_vmovi(s, rd, q, 0, 0x8, v16 & 0xff); 2544 tcg_out_vmovi(s, rd, q, 0, 0xb, v16 >> 8); /* VORRI */ 2545 return; 2546 } 2547 2548 if (vece == MO_32) { 2549 uint32_t v32 = v64; 2550 2551 if (is_shimm32(v32, &cmode, &imm8) || 2552 is_soimm32(v32, &cmode, &imm8)) { 2553 tcg_out_vmovi(s, rd, q, 0, cmode, imm8); 2554 return; 2555 } 2556 if (is_shimm32(~v32, &cmode, &imm8) || 2557 is_soimm32(~v32, &cmode, &imm8)) { 2558 tcg_out_vmovi(s, rd, q, 1, cmode, imm8); 2559 return; 2560 } 2561 2562 /* 2563 * Restrict the set of constants to those we can load with 2564 * two instructions. Others we load from the pool. 2565 */ 2566 i = is_shimm32_pair(v32, &cmode, &imm8); 2567 if (i) { 2568 tcg_out_vmovi(s, rd, q, 0, cmode, imm8); 2569 tcg_out_vmovi(s, rd, q, 0, i | 1, extract32(v32, i * 4, 8)); 2570 return; 2571 } 2572 i = is_shimm32_pair(~v32, &cmode, &imm8); 2573 if (i) { 2574 tcg_out_vmovi(s, rd, q, 1, cmode, imm8); 2575 tcg_out_vmovi(s, rd, q, 1, i | 1, extract32(~v32, i * 4, 8)); 2576 return; 2577 } 2578 } 2579 2580 /* 2581 * As a last resort, load from the constant pool. 2582 */ 2583 if (!q || vece == MO_64) { 2584 new_pool_l2(s, R_ARM_PC11, s->code_ptr, 0, v64, v64 >> 32); 2585 /* VLDR Dd, [pc + offset] */ 2586 tcg_out32(s, INSN_VLDR_D | encode_vd(rd) | (0xf << 16)); 2587 if (q) { 2588 tcg_out_dup2_vec(s, rd, rd, rd); 2589 } 2590 } else { 2591 new_pool_label(s, (uint32_t)v64, R_ARM_PC8, s->code_ptr, 0); 2592 /* add tmp, pc, offset */ 2593 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_TMP, TCG_REG_PC, 0); 2594 tcg_out_dupm_vec(s, type, MO_32, rd, TCG_REG_TMP, 0); 2595 } 2596} 2597 2598static const ARMInsn vec_cmp_insn[16] = { 2599 [TCG_COND_EQ] = INSN_VCEQ, 2600 [TCG_COND_GT] = INSN_VCGT, 2601 [TCG_COND_GE] = INSN_VCGE, 2602 [TCG_COND_GTU] = INSN_VCGT_U, 2603 [TCG_COND_GEU] = INSN_VCGE_U, 2604}; 2605 2606static const ARMInsn vec_cmp0_insn[16] = { 2607 [TCG_COND_EQ] = INSN_VCEQ0, 2608 [TCG_COND_GT] = INSN_VCGT0, 2609 [TCG_COND_GE] = INSN_VCGE0, 2610 [TCG_COND_LT] = INSN_VCLT0, 2611 [TCG_COND_LE] = INSN_VCLE0, 2612}; 2613 2614static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 2615 unsigned vecl, unsigned vece, 2616 const TCGArg args[TCG_MAX_OP_ARGS], 2617 const int const_args[TCG_MAX_OP_ARGS]) 2618{ 2619 TCGType type = vecl + TCG_TYPE_V64; 2620 unsigned q = vecl; 2621 TCGArg a0, a1, a2, a3; 2622 int cmode, imm8; 2623 2624 a0 = args[0]; 2625 a1 = args[1]; 2626 a2 = args[2]; 2627 2628 switch (opc) { 2629 case INDEX_op_ld_vec: 2630 tcg_out_ld(s, type, a0, a1, a2); 2631 return; 2632 case INDEX_op_st_vec: 2633 tcg_out_st(s, type, a0, a1, a2); 2634 return; 2635 case INDEX_op_dupm_vec: 2636 tcg_out_dupm_vec(s, type, vece, a0, a1, a2); 2637 return; 2638 case INDEX_op_dup2_vec: 2639 tcg_out_dup2_vec(s, a0, a1, a2); 2640 return; 2641 case INDEX_op_abs_vec: 2642 tcg_out_vreg2(s, INSN_VABS, q, vece, a0, a1); 2643 return; 2644 case INDEX_op_neg_vec: 2645 tcg_out_vreg2(s, INSN_VNEG, q, vece, a0, a1); 2646 return; 2647 case INDEX_op_not_vec: 2648 tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a1); 2649 return; 2650 case INDEX_op_add_vec: 2651 tcg_out_vreg3(s, INSN_VADD, q, vece, a0, a1, a2); 2652 return; 2653 case INDEX_op_mul_vec: 2654 tcg_out_vreg3(s, INSN_VMUL, q, vece, a0, a1, a2); 2655 return; 2656 case INDEX_op_smax_vec: 2657 tcg_out_vreg3(s, INSN_VMAX, q, vece, a0, a1, a2); 2658 return; 2659 case INDEX_op_smin_vec: 2660 tcg_out_vreg3(s, INSN_VMIN, q, vece, a0, a1, a2); 2661 return; 2662 case INDEX_op_sub_vec: 2663 tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2); 2664 return; 2665 case INDEX_op_ssadd_vec: 2666 tcg_out_vreg3(s, INSN_VQADD, q, vece, a0, a1, a2); 2667 return; 2668 case INDEX_op_sssub_vec: 2669 tcg_out_vreg3(s, INSN_VQSUB, q, vece, a0, a1, a2); 2670 return; 2671 case INDEX_op_umax_vec: 2672 tcg_out_vreg3(s, INSN_VMAX_U, q, vece, a0, a1, a2); 2673 return; 2674 case INDEX_op_umin_vec: 2675 tcg_out_vreg3(s, INSN_VMIN_U, q, vece, a0, a1, a2); 2676 return; 2677 case INDEX_op_usadd_vec: 2678 tcg_out_vreg3(s, INSN_VQADD_U, q, vece, a0, a1, a2); 2679 return; 2680 case INDEX_op_ussub_vec: 2681 tcg_out_vreg3(s, INSN_VQSUB_U, q, vece, a0, a1, a2); 2682 return; 2683 case INDEX_op_xor_vec: 2684 tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2); 2685 return; 2686 case INDEX_op_arm_sshl_vec: 2687 /* 2688 * Note that Vm is the data and Vn is the shift count, 2689 * therefore the arguments appear reversed. 2690 */ 2691 tcg_out_vreg3(s, INSN_VSHL_S, q, vece, a0, a2, a1); 2692 return; 2693 case INDEX_op_arm_ushl_vec: 2694 /* See above. */ 2695 tcg_out_vreg3(s, INSN_VSHL_U, q, vece, a0, a2, a1); 2696 return; 2697 case INDEX_op_shli_vec: 2698 tcg_out_vshifti(s, INSN_VSHLI, q, a0, a1, a2 + (8 << vece)); 2699 return; 2700 case INDEX_op_shri_vec: 2701 tcg_out_vshifti(s, INSN_VSHRI, q, a0, a1, (16 << vece) - a2); 2702 return; 2703 case INDEX_op_sari_vec: 2704 tcg_out_vshifti(s, INSN_VSARI, q, a0, a1, (16 << vece) - a2); 2705 return; 2706 case INDEX_op_arm_sli_vec: 2707 tcg_out_vshifti(s, INSN_VSLI, q, a0, a2, args[3] + (8 << vece)); 2708 return; 2709 2710 case INDEX_op_andc_vec: 2711 if (!const_args[2]) { 2712 tcg_out_vreg3(s, INSN_VBIC, q, 0, a0, a1, a2); 2713 return; 2714 } 2715 a2 = ~a2; 2716 /* fall through */ 2717 case INDEX_op_and_vec: 2718 if (const_args[2]) { 2719 is_shimm1632(~a2, &cmode, &imm8); 2720 if (a0 == a1) { 2721 tcg_out_vmovi(s, a0, q, 1, cmode | 1, imm8); /* VBICI */ 2722 return; 2723 } 2724 tcg_out_vmovi(s, a0, q, 1, cmode, imm8); /* VMVNI */ 2725 a2 = a0; 2726 } 2727 tcg_out_vreg3(s, INSN_VAND, q, 0, a0, a1, a2); 2728 return; 2729 2730 case INDEX_op_orc_vec: 2731 if (!const_args[2]) { 2732 tcg_out_vreg3(s, INSN_VORN, q, 0, a0, a1, a2); 2733 return; 2734 } 2735 a2 = ~a2; 2736 /* fall through */ 2737 case INDEX_op_or_vec: 2738 if (const_args[2]) { 2739 is_shimm1632(a2, &cmode, &imm8); 2740 if (a0 == a1) { 2741 tcg_out_vmovi(s, a0, q, 0, cmode | 1, imm8); /* VORRI */ 2742 return; 2743 } 2744 tcg_out_vmovi(s, a0, q, 0, cmode, imm8); /* VMOVI */ 2745 a2 = a0; 2746 } 2747 tcg_out_vreg3(s, INSN_VORR, q, 0, a0, a1, a2); 2748 return; 2749 2750 case INDEX_op_cmp_vec: 2751 { 2752 TCGCond cond = args[3]; 2753 ARMInsn insn; 2754 2755 switch (cond) { 2756 case TCG_COND_NE: 2757 if (const_args[2]) { 2758 tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a1); 2759 } else { 2760 tcg_out_vreg3(s, INSN_VCEQ, q, vece, a0, a1, a2); 2761 tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0); 2762 } 2763 break; 2764 2765 case TCG_COND_TSTNE: 2766 case TCG_COND_TSTEQ: 2767 if (const_args[2]) { 2768 /* (x & 0) == 0 */ 2769 tcg_out_dupi_vec(s, type, MO_8, a0, 2770 -(cond == TCG_COND_TSTEQ)); 2771 break; 2772 } 2773 tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a2); 2774 if (cond == TCG_COND_TSTEQ) { 2775 tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0); 2776 } 2777 break; 2778 2779 default: 2780 if (const_args[2]) { 2781 insn = vec_cmp0_insn[cond]; 2782 if (insn) { 2783 tcg_out_vreg2(s, insn, q, vece, a0, a1); 2784 return; 2785 } 2786 tcg_out_dupi_vec(s, type, MO_8, TCG_VEC_TMP, 0); 2787 a2 = TCG_VEC_TMP; 2788 } 2789 insn = vec_cmp_insn[cond]; 2790 if (insn == 0) { 2791 TCGArg t; 2792 t = a1, a1 = a2, a2 = t; 2793 cond = tcg_swap_cond(cond); 2794 insn = vec_cmp_insn[cond]; 2795 tcg_debug_assert(insn != 0); 2796 } 2797 tcg_out_vreg3(s, insn, q, vece, a0, a1, a2); 2798 break; 2799 } 2800 } 2801 return; 2802 2803 case INDEX_op_bitsel_vec: 2804 a3 = args[3]; 2805 if (a0 == a3) { 2806 tcg_out_vreg3(s, INSN_VBIT, q, 0, a0, a2, a1); 2807 } else if (a0 == a2) { 2808 tcg_out_vreg3(s, INSN_VBIF, q, 0, a0, a3, a1); 2809 } else { 2810 tcg_out_mov(s, type, a0, a1); 2811 tcg_out_vreg3(s, INSN_VBSL, q, 0, a0, a2, a3); 2812 } 2813 return; 2814 2815 case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ 2816 case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ 2817 default: 2818 g_assert_not_reached(); 2819 } 2820} 2821 2822int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 2823{ 2824 switch (opc) { 2825 case INDEX_op_add_vec: 2826 case INDEX_op_sub_vec: 2827 case INDEX_op_and_vec: 2828 case INDEX_op_andc_vec: 2829 case INDEX_op_or_vec: 2830 case INDEX_op_orc_vec: 2831 case INDEX_op_xor_vec: 2832 case INDEX_op_not_vec: 2833 case INDEX_op_shli_vec: 2834 case INDEX_op_shri_vec: 2835 case INDEX_op_sari_vec: 2836 case INDEX_op_ssadd_vec: 2837 case INDEX_op_sssub_vec: 2838 case INDEX_op_usadd_vec: 2839 case INDEX_op_ussub_vec: 2840 case INDEX_op_bitsel_vec: 2841 return 1; 2842 case INDEX_op_abs_vec: 2843 case INDEX_op_cmp_vec: 2844 case INDEX_op_mul_vec: 2845 case INDEX_op_neg_vec: 2846 case INDEX_op_smax_vec: 2847 case INDEX_op_smin_vec: 2848 case INDEX_op_umax_vec: 2849 case INDEX_op_umin_vec: 2850 return vece < MO_64; 2851 case INDEX_op_shlv_vec: 2852 case INDEX_op_shrv_vec: 2853 case INDEX_op_sarv_vec: 2854 case INDEX_op_rotli_vec: 2855 case INDEX_op_rotlv_vec: 2856 case INDEX_op_rotrv_vec: 2857 return -1; 2858 default: 2859 return 0; 2860 } 2861} 2862 2863void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 2864 TCGArg a0, ...) 2865{ 2866 va_list va; 2867 TCGv_vec v0, v1, v2, t1, t2, c1; 2868 TCGArg a2; 2869 2870 va_start(va, a0); 2871 v0 = temp_tcgv_vec(arg_temp(a0)); 2872 v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 2873 a2 = va_arg(va, TCGArg); 2874 va_end(va); 2875 2876 switch (opc) { 2877 case INDEX_op_shlv_vec: 2878 /* 2879 * Merely propagate shlv_vec to arm_ushl_vec. 2880 * In this way we don't set TCG_TARGET_HAS_shv_vec 2881 * because everything is done via expansion. 2882 */ 2883 v2 = temp_tcgv_vec(arg_temp(a2)); 2884 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0), 2885 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 2886 break; 2887 2888 case INDEX_op_shrv_vec: 2889 case INDEX_op_sarv_vec: 2890 /* Right shifts are negative left shifts for NEON. */ 2891 v2 = temp_tcgv_vec(arg_temp(a2)); 2892 t1 = tcg_temp_new_vec(type); 2893 tcg_gen_neg_vec(vece, t1, v2); 2894 if (opc == INDEX_op_shrv_vec) { 2895 opc = INDEX_op_arm_ushl_vec; 2896 } else { 2897 opc = INDEX_op_arm_sshl_vec; 2898 } 2899 vec_gen_3(opc, type, vece, tcgv_vec_arg(v0), 2900 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 2901 tcg_temp_free_vec(t1); 2902 break; 2903 2904 case INDEX_op_rotli_vec: 2905 t1 = tcg_temp_new_vec(type); 2906 tcg_gen_shri_vec(vece, t1, v1, -a2 & ((8 << vece) - 1)); 2907 vec_gen_4(INDEX_op_arm_sli_vec, type, vece, 2908 tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(v1), a2); 2909 tcg_temp_free_vec(t1); 2910 break; 2911 2912 case INDEX_op_rotlv_vec: 2913 v2 = temp_tcgv_vec(arg_temp(a2)); 2914 t1 = tcg_temp_new_vec(type); 2915 c1 = tcg_constant_vec(type, vece, 8 << vece); 2916 tcg_gen_sub_vec(vece, t1, v2, c1); 2917 /* Right shifts are negative left shifts for NEON. */ 2918 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1), 2919 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 2920 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0), 2921 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 2922 tcg_gen_or_vec(vece, v0, v0, t1); 2923 tcg_temp_free_vec(t1); 2924 break; 2925 2926 case INDEX_op_rotrv_vec: 2927 v2 = temp_tcgv_vec(arg_temp(a2)); 2928 t1 = tcg_temp_new_vec(type); 2929 t2 = tcg_temp_new_vec(type); 2930 c1 = tcg_constant_vec(type, vece, 8 << vece); 2931 tcg_gen_neg_vec(vece, t1, v2); 2932 tcg_gen_sub_vec(vece, t2, c1, v2); 2933 /* Right shifts are negative left shifts for NEON. */ 2934 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1), 2935 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 2936 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t2), 2937 tcgv_vec_arg(v1), tcgv_vec_arg(t2)); 2938 tcg_gen_or_vec(vece, v0, t1, t2); 2939 tcg_temp_free_vec(t1); 2940 tcg_temp_free_vec(t2); 2941 break; 2942 2943 default: 2944 g_assert_not_reached(); 2945 } 2946} 2947 2948static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 2949{ 2950 int i; 2951 for (i = 0; i < count; ++i) { 2952 p[i] = INSN_NOP; 2953 } 2954} 2955 2956/* Compute frame size via macros, to share between tcg_target_qemu_prologue 2957 and tcg_register_jit. */ 2958 2959#define PUSH_SIZE ((11 - 4 + 1 + 1) * sizeof(tcg_target_long)) 2960 2961#define FRAME_SIZE \ 2962 ((PUSH_SIZE \ 2963 + TCG_STATIC_CALL_ARGS_SIZE \ 2964 + CPU_TEMP_BUF_NLONGS * sizeof(long) \ 2965 + TCG_TARGET_STACK_ALIGN - 1) \ 2966 & -TCG_TARGET_STACK_ALIGN) 2967 2968#define STACK_ADDEND (FRAME_SIZE - PUSH_SIZE) 2969 2970static void tcg_target_qemu_prologue(TCGContext *s) 2971{ 2972 /* Calling convention requires us to save r4-r11 and lr. */ 2973 /* stmdb sp!, { r4 - r11, lr } */ 2974 tcg_out_ldstm(s, COND_AL, INSN_STMDB, TCG_REG_CALL_STACK, 2975 (1 << TCG_REG_R4) | (1 << TCG_REG_R5) | (1 << TCG_REG_R6) | 2976 (1 << TCG_REG_R7) | (1 << TCG_REG_R8) | (1 << TCG_REG_R9) | 2977 (1 << TCG_REG_R10) | (1 << TCG_REG_R11) | (1 << TCG_REG_R14)); 2978 2979 /* Reserve callee argument and tcg temp space. */ 2980 tcg_out_dat_rI(s, COND_AL, ARITH_SUB, TCG_REG_CALL_STACK, 2981 TCG_REG_CALL_STACK, STACK_ADDEND, 1); 2982 tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE, 2983 CPU_TEMP_BUF_NLONGS * sizeof(long)); 2984 2985 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 2986 2987 if (!tcg_use_softmmu && guest_base) { 2988 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_GUEST_BASE, guest_base); 2989 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GUEST_BASE); 2990 } 2991 2992 tcg_out_b_reg(s, COND_AL, tcg_target_call_iarg_regs[1]); 2993 2994 /* 2995 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 2996 * and fall through to the rest of the epilogue. 2997 */ 2998 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 2999 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, 0); 3000 tcg_out_epilogue(s); 3001} 3002 3003static void tcg_out_epilogue(TCGContext *s) 3004{ 3005 /* Release local stack frame. */ 3006 tcg_out_dat_rI(s, COND_AL, ARITH_ADD, TCG_REG_CALL_STACK, 3007 TCG_REG_CALL_STACK, STACK_ADDEND, 1); 3008 3009 /* ldmia sp!, { r4 - r11, pc } */ 3010 tcg_out_ldstm(s, COND_AL, INSN_LDMIA, TCG_REG_CALL_STACK, 3011 (1 << TCG_REG_R4) | (1 << TCG_REG_R5) | (1 << TCG_REG_R6) | 3012 (1 << TCG_REG_R7) | (1 << TCG_REG_R8) | (1 << TCG_REG_R9) | 3013 (1 << TCG_REG_R10) | (1 << TCG_REG_R11) | (1 << TCG_REG_PC)); 3014} 3015 3016static void tcg_out_tb_start(TCGContext *s) 3017{ 3018 /* nothing to do */ 3019} 3020 3021typedef struct { 3022 DebugFrameHeader h; 3023 uint8_t fde_def_cfa[4]; 3024 uint8_t fde_reg_ofs[18]; 3025} DebugFrame; 3026 3027#define ELF_HOST_MACHINE EM_ARM 3028 3029/* We're expecting a 2 byte uleb128 encoded value. */ 3030QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); 3031 3032static const DebugFrame debug_frame = { 3033 .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ 3034 .h.cie.id = -1, 3035 .h.cie.version = 1, 3036 .h.cie.code_align = 1, 3037 .h.cie.data_align = 0x7c, /* sleb128 -4 */ 3038 .h.cie.return_column = 14, 3039 3040 /* Total FDE size does not include the "len" member. */ 3041 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 3042 3043 .fde_def_cfa = { 3044 12, 13, /* DW_CFA_def_cfa sp, ... */ 3045 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 3046 (FRAME_SIZE >> 7) 3047 }, 3048 .fde_reg_ofs = { 3049 /* The following must match the stmdb in the prologue. */ 3050 0x8e, 1, /* DW_CFA_offset, lr, -4 */ 3051 0x8b, 2, /* DW_CFA_offset, r11, -8 */ 3052 0x8a, 3, /* DW_CFA_offset, r10, -12 */ 3053 0x89, 4, /* DW_CFA_offset, r9, -16 */ 3054 0x88, 5, /* DW_CFA_offset, r8, -20 */ 3055 0x87, 6, /* DW_CFA_offset, r7, -24 */ 3056 0x86, 7, /* DW_CFA_offset, r6, -28 */ 3057 0x85, 8, /* DW_CFA_offset, r5, -32 */ 3058 0x84, 9, /* DW_CFA_offset, r4, -36 */ 3059 } 3060}; 3061 3062void tcg_register_jit(const void *buf, size_t buf_size) 3063{ 3064 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 3065} 3066