1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Andrzej Zaborowski 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25#include "elf.h" 26#include "../tcg-ldst.c.inc" 27#include "../tcg-pool.c.inc" 28 29int arm_arch = __ARM_ARCH; 30 31#ifndef use_idiv_instructions 32bool use_idiv_instructions; 33#endif 34#ifndef use_neon_instructions 35bool use_neon_instructions; 36#endif 37 38#ifdef CONFIG_DEBUG_TCG 39static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 40 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", 41 "%r8", "%r9", "%r10", "%r11", "%r12", "%sp", "%r14", "%pc", 42 "%q0", "%q1", "%q2", "%q3", "%q4", "%q5", "%q6", "%q7", 43 "%q8", "%q9", "%q10", "%q11", "%q12", "%q13", "%q14", "%q15", 44}; 45#endif 46 47static const int tcg_target_reg_alloc_order[] = { 48 TCG_REG_R4, 49 TCG_REG_R5, 50 TCG_REG_R6, 51 TCG_REG_R7, 52 TCG_REG_R8, 53 TCG_REG_R9, 54 TCG_REG_R10, 55 TCG_REG_R11, 56 TCG_REG_R13, 57 TCG_REG_R0, 58 TCG_REG_R1, 59 TCG_REG_R2, 60 TCG_REG_R3, 61 TCG_REG_R12, 62 TCG_REG_R14, 63 64 TCG_REG_Q0, 65 TCG_REG_Q1, 66 TCG_REG_Q2, 67 TCG_REG_Q3, 68 /* Q4 - Q7 are call-saved, and skipped. */ 69 TCG_REG_Q8, 70 TCG_REG_Q9, 71 TCG_REG_Q10, 72 TCG_REG_Q11, 73 TCG_REG_Q12, 74 TCG_REG_Q13, 75 TCG_REG_Q14, 76 TCG_REG_Q15, 77}; 78 79static const int tcg_target_call_iarg_regs[4] = { 80 TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3 81}; 82 83static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 84{ 85 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 86 tcg_debug_assert(slot >= 0 && slot <= 3); 87 return TCG_REG_R0 + slot; 88} 89 90#define TCG_REG_TMP TCG_REG_R12 91#define TCG_VEC_TMP TCG_REG_Q15 92#ifndef CONFIG_SOFTMMU 93#define TCG_REG_GUEST_BASE TCG_REG_R11 94#endif 95 96typedef enum { 97 COND_EQ = 0x0, 98 COND_NE = 0x1, 99 COND_CS = 0x2, /* Unsigned greater or equal */ 100 COND_CC = 0x3, /* Unsigned less than */ 101 COND_MI = 0x4, /* Negative */ 102 COND_PL = 0x5, /* Zero or greater */ 103 COND_VS = 0x6, /* Overflow */ 104 COND_VC = 0x7, /* No overflow */ 105 COND_HI = 0x8, /* Unsigned greater than */ 106 COND_LS = 0x9, /* Unsigned less or equal */ 107 COND_GE = 0xa, 108 COND_LT = 0xb, 109 COND_GT = 0xc, 110 COND_LE = 0xd, 111 COND_AL = 0xe, 112} ARMCond; 113 114#define TO_CPSR (1 << 20) 115 116#define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00) 117#define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20) 118#define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40) 119#define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60) 120#define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10) 121#define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30) 122#define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50) 123#define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70) 124 125typedef enum { 126 ARITH_AND = 0x0 << 21, 127 ARITH_EOR = 0x1 << 21, 128 ARITH_SUB = 0x2 << 21, 129 ARITH_RSB = 0x3 << 21, 130 ARITH_ADD = 0x4 << 21, 131 ARITH_ADC = 0x5 << 21, 132 ARITH_SBC = 0x6 << 21, 133 ARITH_RSC = 0x7 << 21, 134 ARITH_TST = 0x8 << 21 | TO_CPSR, 135 ARITH_CMP = 0xa << 21 | TO_CPSR, 136 ARITH_CMN = 0xb << 21 | TO_CPSR, 137 ARITH_ORR = 0xc << 21, 138 ARITH_MOV = 0xd << 21, 139 ARITH_BIC = 0xe << 21, 140 ARITH_MVN = 0xf << 21, 141 142 INSN_B = 0x0a000000, 143 144 INSN_CLZ = 0x016f0f10, 145 INSN_RBIT = 0x06ff0f30, 146 147 INSN_LDMIA = 0x08b00000, 148 INSN_STMDB = 0x09200000, 149 150 INSN_LDR_IMM = 0x04100000, 151 INSN_LDR_REG = 0x06100000, 152 INSN_STR_IMM = 0x04000000, 153 INSN_STR_REG = 0x06000000, 154 155 INSN_LDRH_IMM = 0x005000b0, 156 INSN_LDRH_REG = 0x001000b0, 157 INSN_LDRSH_IMM = 0x005000f0, 158 INSN_LDRSH_REG = 0x001000f0, 159 INSN_STRH_IMM = 0x004000b0, 160 INSN_STRH_REG = 0x000000b0, 161 162 INSN_LDRB_IMM = 0x04500000, 163 INSN_LDRB_REG = 0x06500000, 164 INSN_LDRSB_IMM = 0x005000d0, 165 INSN_LDRSB_REG = 0x001000d0, 166 INSN_STRB_IMM = 0x04400000, 167 INSN_STRB_REG = 0x06400000, 168 169 INSN_LDRD_IMM = 0x004000d0, 170 INSN_LDRD_REG = 0x000000d0, 171 INSN_STRD_IMM = 0x004000f0, 172 INSN_STRD_REG = 0x000000f0, 173 174 INSN_DMB_ISH = 0xf57ff05b, 175 INSN_DMB_MCR = 0xee070fba, 176 177 /* Architected nop introduced in v6k. */ 178 /* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this 179 also Just So Happened to do nothing on pre-v6k so that we 180 don't need to conditionalize it? */ 181 INSN_NOP_v6k = 0xe320f000, 182 /* Otherwise the assembler uses mov r0,r0 */ 183 INSN_NOP_v4 = (COND_AL << 28) | ARITH_MOV, 184 185 INSN_VADD = 0xf2000800, 186 INSN_VAND = 0xf2000110, 187 INSN_VBIC = 0xf2100110, 188 INSN_VEOR = 0xf3000110, 189 INSN_VORN = 0xf2300110, 190 INSN_VORR = 0xf2200110, 191 INSN_VSUB = 0xf3000800, 192 INSN_VMUL = 0xf2000910, 193 INSN_VQADD = 0xf2000010, 194 INSN_VQADD_U = 0xf3000010, 195 INSN_VQSUB = 0xf2000210, 196 INSN_VQSUB_U = 0xf3000210, 197 INSN_VMAX = 0xf2000600, 198 INSN_VMAX_U = 0xf3000600, 199 INSN_VMIN = 0xf2000610, 200 INSN_VMIN_U = 0xf3000610, 201 202 INSN_VABS = 0xf3b10300, 203 INSN_VMVN = 0xf3b00580, 204 INSN_VNEG = 0xf3b10380, 205 206 INSN_VCEQ0 = 0xf3b10100, 207 INSN_VCGT0 = 0xf3b10000, 208 INSN_VCGE0 = 0xf3b10080, 209 INSN_VCLE0 = 0xf3b10180, 210 INSN_VCLT0 = 0xf3b10200, 211 212 INSN_VCEQ = 0xf3000810, 213 INSN_VCGE = 0xf2000310, 214 INSN_VCGT = 0xf2000300, 215 INSN_VCGE_U = 0xf3000310, 216 INSN_VCGT_U = 0xf3000300, 217 218 INSN_VSHLI = 0xf2800510, /* VSHL (immediate) */ 219 INSN_VSARI = 0xf2800010, /* VSHR.S */ 220 INSN_VSHRI = 0xf3800010, /* VSHR.U */ 221 INSN_VSLI = 0xf3800510, 222 INSN_VSHL_S = 0xf2000400, /* VSHL.S (register) */ 223 INSN_VSHL_U = 0xf3000400, /* VSHL.U (register) */ 224 225 INSN_VBSL = 0xf3100110, 226 INSN_VBIT = 0xf3200110, 227 INSN_VBIF = 0xf3300110, 228 229 INSN_VTST = 0xf2000810, 230 231 INSN_VDUP_G = 0xee800b10, /* VDUP (ARM core register) */ 232 INSN_VDUP_S = 0xf3b00c00, /* VDUP (scalar) */ 233 INSN_VLDR_D = 0xed100b00, /* VLDR.64 */ 234 INSN_VLD1 = 0xf4200000, /* VLD1 (multiple single elements) */ 235 INSN_VLD1R = 0xf4a00c00, /* VLD1 (single element to all lanes) */ 236 INSN_VST1 = 0xf4000000, /* VST1 (multiple single elements) */ 237 INSN_VMOVI = 0xf2800010, /* VMOV (immediate) */ 238} ARMInsn; 239 240#define INSN_NOP (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4) 241 242static const uint8_t tcg_cond_to_arm_cond[] = { 243 [TCG_COND_EQ] = COND_EQ, 244 [TCG_COND_NE] = COND_NE, 245 [TCG_COND_LT] = COND_LT, 246 [TCG_COND_GE] = COND_GE, 247 [TCG_COND_LE] = COND_LE, 248 [TCG_COND_GT] = COND_GT, 249 /* unsigned */ 250 [TCG_COND_LTU] = COND_CC, 251 [TCG_COND_GEU] = COND_CS, 252 [TCG_COND_LEU] = COND_LS, 253 [TCG_COND_GTU] = COND_HI, 254}; 255 256static int encode_imm(uint32_t imm); 257 258/* TCG private relocation type: add with pc+imm8 */ 259#define R_ARM_PC8 11 260 261/* TCG private relocation type: vldr with imm8 << 2 */ 262#define R_ARM_PC11 12 263 264static bool reloc_pc24(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 265{ 266 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 267 ptrdiff_t offset = (tcg_ptr_byte_diff(target, src_rx) - 8) >> 2; 268 269 if (offset == sextract32(offset, 0, 24)) { 270 *src_rw = deposit32(*src_rw, 0, 24, offset); 271 return true; 272 } 273 return false; 274} 275 276static bool reloc_pc13(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 277{ 278 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 279 ptrdiff_t offset = tcg_ptr_byte_diff(target, src_rx) - 8; 280 281 if (offset >= -0xfff && offset <= 0xfff) { 282 tcg_insn_unit insn = *src_rw; 283 bool u = (offset >= 0); 284 if (!u) { 285 offset = -offset; 286 } 287 insn = deposit32(insn, 23, 1, u); 288 insn = deposit32(insn, 0, 12, offset); 289 *src_rw = insn; 290 return true; 291 } 292 return false; 293} 294 295static bool reloc_pc11(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 296{ 297 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 298 ptrdiff_t offset = (tcg_ptr_byte_diff(target, src_rx) - 8) / 4; 299 300 if (offset >= -0xff && offset <= 0xff) { 301 tcg_insn_unit insn = *src_rw; 302 bool u = (offset >= 0); 303 if (!u) { 304 offset = -offset; 305 } 306 insn = deposit32(insn, 23, 1, u); 307 insn = deposit32(insn, 0, 8, offset); 308 *src_rw = insn; 309 return true; 310 } 311 return false; 312} 313 314static bool reloc_pc8(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 315{ 316 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 317 ptrdiff_t offset = tcg_ptr_byte_diff(target, src_rx) - 8; 318 int imm12 = encode_imm(offset); 319 320 if (imm12 >= 0) { 321 *src_rw = deposit32(*src_rw, 0, 12, imm12); 322 return true; 323 } 324 return false; 325} 326 327static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 328 intptr_t value, intptr_t addend) 329{ 330 tcg_debug_assert(addend == 0); 331 switch (type) { 332 case R_ARM_PC24: 333 return reloc_pc24(code_ptr, (const tcg_insn_unit *)value); 334 case R_ARM_PC13: 335 return reloc_pc13(code_ptr, (const tcg_insn_unit *)value); 336 case R_ARM_PC11: 337 return reloc_pc11(code_ptr, (const tcg_insn_unit *)value); 338 case R_ARM_PC8: 339 return reloc_pc8(code_ptr, (const tcg_insn_unit *)value); 340 default: 341 g_assert_not_reached(); 342 } 343} 344 345#define TCG_CT_CONST_ARM 0x100 346#define TCG_CT_CONST_INV 0x200 347#define TCG_CT_CONST_NEG 0x400 348#define TCG_CT_CONST_ZERO 0x800 349#define TCG_CT_CONST_ORRI 0x1000 350#define TCG_CT_CONST_ANDI 0x2000 351 352#define ALL_GENERAL_REGS 0xffffu 353#define ALL_VECTOR_REGS 0xffff0000u 354 355/* 356 * r0-r2 will be overwritten when reading the tlb entry (softmmu only) 357 * and r0-r1 doing the byte swapping, so don't use these. 358 * r3 is removed for softmmu to avoid clashes with helper arguments. 359 */ 360#ifdef CONFIG_SOFTMMU 361#define ALL_QLOAD_REGS \ 362 (ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1) | \ 363 (1 << TCG_REG_R2) | (1 << TCG_REG_R3) | \ 364 (1 << TCG_REG_R14))) 365#define ALL_QSTORE_REGS \ 366 (ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1) | \ 367 (1 << TCG_REG_R2) | (1 << TCG_REG_R14) | \ 368 ((TARGET_LONG_BITS == 64) << TCG_REG_R3))) 369#else 370#define ALL_QLOAD_REGS ALL_GENERAL_REGS 371#define ALL_QSTORE_REGS \ 372 (ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1))) 373#endif 374 375/* 376 * ARM immediates for ALU instructions are made of an unsigned 8-bit 377 * right-rotated by an even amount between 0 and 30. 378 * 379 * Return < 0 if @imm cannot be encoded, else the entire imm12 field. 380 */ 381static int encode_imm(uint32_t imm) 382{ 383 uint32_t rot, imm8; 384 385 /* Simple case, no rotation required. */ 386 if ((imm & ~0xff) == 0) { 387 return imm; 388 } 389 390 /* Next, try a simple even shift. */ 391 rot = ctz32(imm) & ~1; 392 imm8 = imm >> rot; 393 rot = 32 - rot; 394 if ((imm8 & ~0xff) == 0) { 395 goto found; 396 } 397 398 /* 399 * Finally, try harder with rotations. 400 * The ctz test above will have taken care of rotates >= 8. 401 */ 402 for (rot = 2; rot < 8; rot += 2) { 403 imm8 = rol32(imm, rot); 404 if ((imm8 & ~0xff) == 0) { 405 goto found; 406 } 407 } 408 /* Fail: imm cannot be encoded. */ 409 return -1; 410 411 found: 412 /* Note that rot is even, and we discard bit 0 by shifting by 7. */ 413 return rot << 7 | imm8; 414} 415 416static int encode_imm_nofail(uint32_t imm) 417{ 418 int ret = encode_imm(imm); 419 tcg_debug_assert(ret >= 0); 420 return ret; 421} 422 423static bool check_fit_imm(uint32_t imm) 424{ 425 return encode_imm(imm) >= 0; 426} 427 428/* Return true if v16 is a valid 16-bit shifted immediate. */ 429static bool is_shimm16(uint16_t v16, int *cmode, int *imm8) 430{ 431 if (v16 == (v16 & 0xff)) { 432 *cmode = 0x8; 433 *imm8 = v16 & 0xff; 434 return true; 435 } else if (v16 == (v16 & 0xff00)) { 436 *cmode = 0xa; 437 *imm8 = v16 >> 8; 438 return true; 439 } 440 return false; 441} 442 443/* Return true if v32 is a valid 32-bit shifted immediate. */ 444static bool is_shimm32(uint32_t v32, int *cmode, int *imm8) 445{ 446 if (v32 == (v32 & 0xff)) { 447 *cmode = 0x0; 448 *imm8 = v32 & 0xff; 449 return true; 450 } else if (v32 == (v32 & 0xff00)) { 451 *cmode = 0x2; 452 *imm8 = (v32 >> 8) & 0xff; 453 return true; 454 } else if (v32 == (v32 & 0xff0000)) { 455 *cmode = 0x4; 456 *imm8 = (v32 >> 16) & 0xff; 457 return true; 458 } else if (v32 == (v32 & 0xff000000)) { 459 *cmode = 0x6; 460 *imm8 = v32 >> 24; 461 return true; 462 } 463 return false; 464} 465 466/* Return true if v32 is a valid 32-bit shifting ones immediate. */ 467static bool is_soimm32(uint32_t v32, int *cmode, int *imm8) 468{ 469 if ((v32 & 0xffff00ff) == 0xff) { 470 *cmode = 0xc; 471 *imm8 = (v32 >> 8) & 0xff; 472 return true; 473 } else if ((v32 & 0xff00ffff) == 0xffff) { 474 *cmode = 0xd; 475 *imm8 = (v32 >> 16) & 0xff; 476 return true; 477 } 478 return false; 479} 480 481/* 482 * Return non-zero if v32 can be formed by MOVI+ORR. 483 * Place the parameters for MOVI in (cmode, imm8). 484 * Return the cmode for ORR; the imm8 can be had via extraction from v32. 485 */ 486static int is_shimm32_pair(uint32_t v32, int *cmode, int *imm8) 487{ 488 int i; 489 490 for (i = 6; i > 0; i -= 2) { 491 /* Mask out one byte we can add with ORR. */ 492 uint32_t tmp = v32 & ~(0xffu << (i * 4)); 493 if (is_shimm32(tmp, cmode, imm8) || 494 is_soimm32(tmp, cmode, imm8)) { 495 break; 496 } 497 } 498 return i; 499} 500 501/* Return true if V is a valid 16-bit or 32-bit shifted immediate. */ 502static bool is_shimm1632(uint32_t v32, int *cmode, int *imm8) 503{ 504 if (v32 == deposit32(v32, 16, 16, v32)) { 505 return is_shimm16(v32, cmode, imm8); 506 } else { 507 return is_shimm32(v32, cmode, imm8); 508 } 509} 510 511/* Test if a constant matches the constraint. 512 * TODO: define constraints for: 513 * 514 * ldr/str offset: between -0xfff and 0xfff 515 * ldrh/strh offset: between -0xff and 0xff 516 * mov operand2: values represented with x << (2 * y), x < 0x100 517 * add, sub, eor...: ditto 518 */ 519static bool tcg_target_const_match(int64_t val, TCGType type, int ct) 520{ 521 if (ct & TCG_CT_CONST) { 522 return 1; 523 } else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val)) { 524 return 1; 525 } else if ((ct & TCG_CT_CONST_INV) && check_fit_imm(~val)) { 526 return 1; 527 } else if ((ct & TCG_CT_CONST_NEG) && check_fit_imm(-val)) { 528 return 1; 529 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 530 return 1; 531 } 532 533 switch (ct & (TCG_CT_CONST_ORRI | TCG_CT_CONST_ANDI)) { 534 case 0: 535 break; 536 case TCG_CT_CONST_ANDI: 537 val = ~val; 538 /* fallthru */ 539 case TCG_CT_CONST_ORRI: 540 if (val == deposit64(val, 32, 32, val)) { 541 int cmode, imm8; 542 return is_shimm1632(val, &cmode, &imm8); 543 } 544 break; 545 default: 546 /* Both bits should not be set for the same insn. */ 547 g_assert_not_reached(); 548 } 549 550 return 0; 551} 552 553static void tcg_out_b_imm(TCGContext *s, ARMCond cond, int32_t offset) 554{ 555 tcg_out32(s, (cond << 28) | INSN_B | 556 (((offset - 8) >> 2) & 0x00ffffff)); 557} 558 559static void tcg_out_bl_imm(TCGContext *s, ARMCond cond, int32_t offset) 560{ 561 tcg_out32(s, (cond << 28) | 0x0b000000 | 562 (((offset - 8) >> 2) & 0x00ffffff)); 563} 564 565static void tcg_out_blx_reg(TCGContext *s, ARMCond cond, TCGReg rn) 566{ 567 tcg_out32(s, (cond << 28) | 0x012fff30 | rn); 568} 569 570static void tcg_out_blx_imm(TCGContext *s, int32_t offset) 571{ 572 tcg_out32(s, 0xfa000000 | ((offset & 2) << 23) | 573 (((offset - 8) >> 2) & 0x00ffffff)); 574} 575 576static void tcg_out_dat_reg(TCGContext *s, ARMCond cond, ARMInsn opc, 577 TCGReg rd, TCGReg rn, TCGReg rm, int shift) 578{ 579 tcg_out32(s, (cond << 28) | (0 << 25) | opc | 580 (rn << 16) | (rd << 12) | shift | rm); 581} 582 583static void tcg_out_mov_reg(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rm) 584{ 585 /* Simple reg-reg move, optimising out the 'do nothing' case */ 586 if (rd != rm) { 587 tcg_out_dat_reg(s, cond, ARITH_MOV, rd, 0, rm, SHIFT_IMM_LSL(0)); 588 } 589} 590 591static void tcg_out_bx_reg(TCGContext *s, ARMCond cond, TCGReg rn) 592{ 593 tcg_out32(s, (cond << 28) | 0x012fff10 | rn); 594} 595 596static void tcg_out_b_reg(TCGContext *s, ARMCond cond, TCGReg rn) 597{ 598 /* 599 * Unless the C portion of QEMU is compiled as thumb, we don't need 600 * true BX semantics; merely a branch to an address held in a register. 601 */ 602 tcg_out_bx_reg(s, cond, rn); 603} 604 605static void tcg_out_dat_imm(TCGContext *s, ARMCond cond, ARMInsn opc, 606 TCGReg rd, TCGReg rn, int im) 607{ 608 tcg_out32(s, (cond << 28) | (1 << 25) | opc | 609 (rn << 16) | (rd << 12) | im); 610} 611 612static void tcg_out_ldstm(TCGContext *s, ARMCond cond, ARMInsn opc, 613 TCGReg rn, uint16_t mask) 614{ 615 tcg_out32(s, (cond << 28) | opc | (rn << 16) | mask); 616} 617 618/* Note that this routine is used for both LDR and LDRH formats, so we do 619 not wish to include an immediate shift at this point. */ 620static void tcg_out_memop_r(TCGContext *s, ARMCond cond, ARMInsn opc, TCGReg rt, 621 TCGReg rn, TCGReg rm, bool u, bool p, bool w) 622{ 623 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) 624 | (w << 21) | (rn << 16) | (rt << 12) | rm); 625} 626 627static void tcg_out_memop_8(TCGContext *s, ARMCond cond, ARMInsn opc, TCGReg rt, 628 TCGReg rn, int imm8, bool p, bool w) 629{ 630 bool u = 1; 631 if (imm8 < 0) { 632 imm8 = -imm8; 633 u = 0; 634 } 635 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | 636 (rn << 16) | (rt << 12) | ((imm8 & 0xf0) << 4) | (imm8 & 0xf)); 637} 638 639static void tcg_out_memop_12(TCGContext *s, ARMCond cond, ARMInsn opc, 640 TCGReg rt, TCGReg rn, int imm12, bool p, bool w) 641{ 642 bool u = 1; 643 if (imm12 < 0) { 644 imm12 = -imm12; 645 u = 0; 646 } 647 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | 648 (rn << 16) | (rt << 12) | imm12); 649} 650 651static void tcg_out_ld32_12(TCGContext *s, ARMCond cond, TCGReg rt, 652 TCGReg rn, int imm12) 653{ 654 tcg_out_memop_12(s, cond, INSN_LDR_IMM, rt, rn, imm12, 1, 0); 655} 656 657static void tcg_out_st32_12(TCGContext *s, ARMCond cond, TCGReg rt, 658 TCGReg rn, int imm12) 659{ 660 tcg_out_memop_12(s, cond, INSN_STR_IMM, rt, rn, imm12, 1, 0); 661} 662 663static void tcg_out_ld32_r(TCGContext *s, ARMCond cond, TCGReg rt, 664 TCGReg rn, TCGReg rm) 665{ 666 tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 0); 667} 668 669static void tcg_out_st32_r(TCGContext *s, ARMCond cond, TCGReg rt, 670 TCGReg rn, TCGReg rm) 671{ 672 tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 0); 673} 674 675static void tcg_out_ldrd_8(TCGContext *s, ARMCond cond, TCGReg rt, 676 TCGReg rn, int imm8) 677{ 678 tcg_out_memop_8(s, cond, INSN_LDRD_IMM, rt, rn, imm8, 1, 0); 679} 680 681static void tcg_out_ldrd_r(TCGContext *s, ARMCond cond, TCGReg rt, 682 TCGReg rn, TCGReg rm) 683{ 684 tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 0); 685} 686 687static void __attribute__((unused)) 688tcg_out_ldrd_rwb(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, TCGReg rm) 689{ 690 tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 1); 691} 692 693static void __attribute__((unused)) 694tcg_out_strd_8(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, int imm8) 695{ 696 tcg_out_memop_8(s, cond, INSN_STRD_IMM, rt, rn, imm8, 1, 0); 697} 698 699static void tcg_out_strd_r(TCGContext *s, ARMCond cond, TCGReg rt, 700 TCGReg rn, TCGReg rm) 701{ 702 tcg_out_memop_r(s, cond, INSN_STRD_REG, rt, rn, rm, 1, 1, 0); 703} 704 705/* Register pre-increment with base writeback. */ 706static void tcg_out_ld32_rwb(TCGContext *s, ARMCond cond, TCGReg rt, 707 TCGReg rn, TCGReg rm) 708{ 709 tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 1); 710} 711 712static void tcg_out_st32_rwb(TCGContext *s, ARMCond cond, TCGReg rt, 713 TCGReg rn, TCGReg rm) 714{ 715 tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 1); 716} 717 718static void tcg_out_ld16u_8(TCGContext *s, ARMCond cond, TCGReg rt, 719 TCGReg rn, int imm8) 720{ 721 tcg_out_memop_8(s, cond, INSN_LDRH_IMM, rt, rn, imm8, 1, 0); 722} 723 724static void tcg_out_st16_8(TCGContext *s, ARMCond cond, TCGReg rt, 725 TCGReg rn, int imm8) 726{ 727 tcg_out_memop_8(s, cond, INSN_STRH_IMM, rt, rn, imm8, 1, 0); 728} 729 730static void tcg_out_ld16u_r(TCGContext *s, ARMCond cond, TCGReg rt, 731 TCGReg rn, TCGReg rm) 732{ 733 tcg_out_memop_r(s, cond, INSN_LDRH_REG, rt, rn, rm, 1, 1, 0); 734} 735 736static void tcg_out_st16_r(TCGContext *s, ARMCond cond, TCGReg rt, 737 TCGReg rn, TCGReg rm) 738{ 739 tcg_out_memop_r(s, cond, INSN_STRH_REG, rt, rn, rm, 1, 1, 0); 740} 741 742static void tcg_out_ld16s_8(TCGContext *s, ARMCond cond, TCGReg rt, 743 TCGReg rn, int imm8) 744{ 745 tcg_out_memop_8(s, cond, INSN_LDRSH_IMM, rt, rn, imm8, 1, 0); 746} 747 748static void tcg_out_ld16s_r(TCGContext *s, ARMCond cond, TCGReg rt, 749 TCGReg rn, TCGReg rm) 750{ 751 tcg_out_memop_r(s, cond, INSN_LDRSH_REG, rt, rn, rm, 1, 1, 0); 752} 753 754static void tcg_out_ld8_12(TCGContext *s, ARMCond cond, TCGReg rt, 755 TCGReg rn, int imm12) 756{ 757 tcg_out_memop_12(s, cond, INSN_LDRB_IMM, rt, rn, imm12, 1, 0); 758} 759 760static void tcg_out_st8_12(TCGContext *s, ARMCond cond, TCGReg rt, 761 TCGReg rn, int imm12) 762{ 763 tcg_out_memop_12(s, cond, INSN_STRB_IMM, rt, rn, imm12, 1, 0); 764} 765 766static void tcg_out_ld8_r(TCGContext *s, ARMCond cond, TCGReg rt, 767 TCGReg rn, TCGReg rm) 768{ 769 tcg_out_memop_r(s, cond, INSN_LDRB_REG, rt, rn, rm, 1, 1, 0); 770} 771 772static void tcg_out_st8_r(TCGContext *s, ARMCond cond, TCGReg rt, 773 TCGReg rn, TCGReg rm) 774{ 775 tcg_out_memop_r(s, cond, INSN_STRB_REG, rt, rn, rm, 1, 1, 0); 776} 777 778static void tcg_out_ld8s_8(TCGContext *s, ARMCond cond, TCGReg rt, 779 TCGReg rn, int imm8) 780{ 781 tcg_out_memop_8(s, cond, INSN_LDRSB_IMM, rt, rn, imm8, 1, 0); 782} 783 784static void tcg_out_ld8s_r(TCGContext *s, ARMCond cond, TCGReg rt, 785 TCGReg rn, TCGReg rm) 786{ 787 tcg_out_memop_r(s, cond, INSN_LDRSB_REG, rt, rn, rm, 1, 1, 0); 788} 789 790static void tcg_out_movi_pool(TCGContext *s, ARMCond cond, 791 TCGReg rd, uint32_t arg) 792{ 793 new_pool_label(s, arg, R_ARM_PC13, s->code_ptr, 0); 794 tcg_out_ld32_12(s, cond, rd, TCG_REG_PC, 0); 795} 796 797static void tcg_out_movi32(TCGContext *s, ARMCond cond, 798 TCGReg rd, uint32_t arg) 799{ 800 int imm12, diff, opc, sh1, sh2; 801 uint32_t tt0, tt1, tt2; 802 803 /* Check a single MOV/MVN before anything else. */ 804 imm12 = encode_imm(arg); 805 if (imm12 >= 0) { 806 tcg_out_dat_imm(s, cond, ARITH_MOV, rd, 0, imm12); 807 return; 808 } 809 imm12 = encode_imm(~arg); 810 if (imm12 >= 0) { 811 tcg_out_dat_imm(s, cond, ARITH_MVN, rd, 0, imm12); 812 return; 813 } 814 815 /* Check for a pc-relative address. This will usually be the TB, 816 or within the TB, which is immediately before the code block. */ 817 diff = tcg_pcrel_diff(s, (void *)arg) - 8; 818 if (diff >= 0) { 819 imm12 = encode_imm(diff); 820 if (imm12 >= 0) { 821 tcg_out_dat_imm(s, cond, ARITH_ADD, rd, TCG_REG_PC, imm12); 822 return; 823 } 824 } else { 825 imm12 = encode_imm(-diff); 826 if (imm12 >= 0) { 827 tcg_out_dat_imm(s, cond, ARITH_SUB, rd, TCG_REG_PC, imm12); 828 return; 829 } 830 } 831 832 /* Use movw + movt. */ 833 if (use_armv7_instructions) { 834 /* movw */ 835 tcg_out32(s, (cond << 28) | 0x03000000 | (rd << 12) 836 | ((arg << 4) & 0x000f0000) | (arg & 0xfff)); 837 if (arg & 0xffff0000) { 838 /* movt */ 839 tcg_out32(s, (cond << 28) | 0x03400000 | (rd << 12) 840 | ((arg >> 12) & 0x000f0000) | ((arg >> 16) & 0xfff)); 841 } 842 return; 843 } 844 845 /* Look for sequences of two insns. If we have lots of 1's, we can 846 shorten the sequence by beginning with mvn and then clearing 847 higher bits with eor. */ 848 tt0 = arg; 849 opc = ARITH_MOV; 850 if (ctpop32(arg) > 16) { 851 tt0 = ~arg; 852 opc = ARITH_MVN; 853 } 854 sh1 = ctz32(tt0) & ~1; 855 tt1 = tt0 & ~(0xff << sh1); 856 sh2 = ctz32(tt1) & ~1; 857 tt2 = tt1 & ~(0xff << sh2); 858 if (tt2 == 0) { 859 int rot; 860 861 rot = ((32 - sh1) << 7) & 0xf00; 862 tcg_out_dat_imm(s, cond, opc, rd, 0, ((tt0 >> sh1) & 0xff) | rot); 863 rot = ((32 - sh2) << 7) & 0xf00; 864 tcg_out_dat_imm(s, cond, ARITH_EOR, rd, rd, 865 ((tt0 >> sh2) & 0xff) | rot); 866 return; 867 } 868 869 /* Otherwise, drop it into the constant pool. */ 870 tcg_out_movi_pool(s, cond, rd, arg); 871} 872 873/* 874 * Emit either the reg,imm or reg,reg form of a data-processing insn. 875 * rhs must satisfy the "rI" constraint. 876 */ 877static void tcg_out_dat_rI(TCGContext *s, ARMCond cond, ARMInsn opc, 878 TCGReg dst, TCGReg lhs, TCGArg rhs, int rhs_is_const) 879{ 880 if (rhs_is_const) { 881 tcg_out_dat_imm(s, cond, opc, dst, lhs, encode_imm_nofail(rhs)); 882 } else { 883 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); 884 } 885} 886 887/* 888 * Emit either the reg,imm or reg,reg form of a data-processing insn. 889 * rhs must satisfy the "rIK" constraint. 890 */ 891static void tcg_out_dat_rIK(TCGContext *s, ARMCond cond, ARMInsn opc, 892 ARMInsn opinv, TCGReg dst, TCGReg lhs, TCGArg rhs, 893 bool rhs_is_const) 894{ 895 if (rhs_is_const) { 896 int imm12 = encode_imm(rhs); 897 if (imm12 < 0) { 898 imm12 = encode_imm_nofail(~rhs); 899 opc = opinv; 900 } 901 tcg_out_dat_imm(s, cond, opc, dst, lhs, imm12); 902 } else { 903 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); 904 } 905} 906 907static void tcg_out_dat_rIN(TCGContext *s, ARMCond cond, ARMInsn opc, 908 ARMInsn opneg, TCGReg dst, TCGReg lhs, TCGArg rhs, 909 bool rhs_is_const) 910{ 911 /* Emit either the reg,imm or reg,reg form of a data-processing insn. 912 * rhs must satisfy the "rIN" constraint. 913 */ 914 if (rhs_is_const) { 915 int imm12 = encode_imm(rhs); 916 if (imm12 < 0) { 917 imm12 = encode_imm_nofail(-rhs); 918 opc = opneg; 919 } 920 tcg_out_dat_imm(s, cond, opc, dst, lhs, imm12); 921 } else { 922 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); 923 } 924} 925 926static void tcg_out_mul32(TCGContext *s, ARMCond cond, TCGReg rd, 927 TCGReg rn, TCGReg rm) 928{ 929 /* mul */ 930 tcg_out32(s, (cond << 28) | 0x90 | (rd << 16) | (rm << 8) | rn); 931} 932 933static void tcg_out_umull32(TCGContext *s, ARMCond cond, TCGReg rd0, 934 TCGReg rd1, TCGReg rn, TCGReg rm) 935{ 936 /* umull */ 937 tcg_out32(s, (cond << 28) | 0x00800090 | 938 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); 939} 940 941static void tcg_out_smull32(TCGContext *s, ARMCond cond, TCGReg rd0, 942 TCGReg rd1, TCGReg rn, TCGReg rm) 943{ 944 /* smull */ 945 tcg_out32(s, (cond << 28) | 0x00c00090 | 946 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); 947} 948 949static void tcg_out_sdiv(TCGContext *s, ARMCond cond, 950 TCGReg rd, TCGReg rn, TCGReg rm) 951{ 952 tcg_out32(s, 0x0710f010 | (cond << 28) | (rd << 16) | rn | (rm << 8)); 953} 954 955static void tcg_out_udiv(TCGContext *s, ARMCond cond, 956 TCGReg rd, TCGReg rn, TCGReg rm) 957{ 958 tcg_out32(s, 0x0730f010 | (cond << 28) | (rd << 16) | rn | (rm << 8)); 959} 960 961static void tcg_out_ext8s(TCGContext *s, TCGType t, TCGReg rd, TCGReg rn) 962{ 963 /* sxtb */ 964 tcg_out32(s, 0x06af0070 | (COND_AL << 28) | (rd << 12) | rn); 965} 966 967static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rn) 968{ 969 tcg_out_dat_imm(s, COND_AL, ARITH_AND, rd, rn, 0xff); 970} 971 972static void tcg_out_ext16s(TCGContext *s, TCGType t, TCGReg rd, TCGReg rn) 973{ 974 /* sxth */ 975 tcg_out32(s, 0x06bf0070 | (COND_AL << 28) | (rd << 12) | rn); 976} 977 978static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rn) 979{ 980 /* uxth */ 981 tcg_out32(s, 0x06ff0070 | (COND_AL << 28) | (rd << 12) | rn); 982} 983 984static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rn) 985{ 986 g_assert_not_reached(); 987} 988 989static void tcg_out_ext32u(TCGContext *s, TCGReg rd, TCGReg rn) 990{ 991 g_assert_not_reached(); 992} 993 994static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rn) 995{ 996 g_assert_not_reached(); 997} 998 999static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rn) 1000{ 1001 g_assert_not_reached(); 1002} 1003 1004static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rn) 1005{ 1006 g_assert_not_reached(); 1007} 1008 1009static void tcg_out_bswap16(TCGContext *s, ARMCond cond, 1010 TCGReg rd, TCGReg rn, int flags) 1011{ 1012 if (flags & TCG_BSWAP_OS) { 1013 /* revsh */ 1014 tcg_out32(s, 0x06ff0fb0 | (cond << 28) | (rd << 12) | rn); 1015 return; 1016 } 1017 1018 /* rev16 */ 1019 tcg_out32(s, 0x06bf0fb0 | (cond << 28) | (rd << 12) | rn); 1020 if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 1021 /* uxth */ 1022 tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | rd); 1023 } 1024} 1025 1026static void tcg_out_bswap32(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rn) 1027{ 1028 /* rev */ 1029 tcg_out32(s, 0x06bf0f30 | (cond << 28) | (rd << 12) | rn); 1030} 1031 1032static void tcg_out_deposit(TCGContext *s, ARMCond cond, TCGReg rd, 1033 TCGArg a1, int ofs, int len, bool const_a1) 1034{ 1035 if (const_a1) { 1036 /* bfi becomes bfc with rn == 15. */ 1037 a1 = 15; 1038 } 1039 /* bfi/bfc */ 1040 tcg_out32(s, 0x07c00010 | (cond << 28) | (rd << 12) | a1 1041 | (ofs << 7) | ((ofs + len - 1) << 16)); 1042} 1043 1044static void tcg_out_extract(TCGContext *s, ARMCond cond, TCGReg rd, 1045 TCGReg rn, int ofs, int len) 1046{ 1047 /* ubfx */ 1048 tcg_out32(s, 0x07e00050 | (cond << 28) | (rd << 12) | rn 1049 | (ofs << 7) | ((len - 1) << 16)); 1050} 1051 1052static void tcg_out_sextract(TCGContext *s, ARMCond cond, TCGReg rd, 1053 TCGReg rn, int ofs, int len) 1054{ 1055 /* sbfx */ 1056 tcg_out32(s, 0x07a00050 | (cond << 28) | (rd << 12) | rn 1057 | (ofs << 7) | ((len - 1) << 16)); 1058} 1059 1060static void tcg_out_ld32u(TCGContext *s, ARMCond cond, 1061 TCGReg rd, TCGReg rn, int32_t offset) 1062{ 1063 if (offset > 0xfff || offset < -0xfff) { 1064 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1065 tcg_out_ld32_r(s, cond, rd, rn, TCG_REG_TMP); 1066 } else 1067 tcg_out_ld32_12(s, cond, rd, rn, offset); 1068} 1069 1070static void tcg_out_st32(TCGContext *s, ARMCond cond, 1071 TCGReg rd, TCGReg rn, int32_t offset) 1072{ 1073 if (offset > 0xfff || offset < -0xfff) { 1074 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1075 tcg_out_st32_r(s, cond, rd, rn, TCG_REG_TMP); 1076 } else 1077 tcg_out_st32_12(s, cond, rd, rn, offset); 1078} 1079 1080static void tcg_out_ld16u(TCGContext *s, ARMCond cond, 1081 TCGReg rd, TCGReg rn, int32_t offset) 1082{ 1083 if (offset > 0xff || offset < -0xff) { 1084 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1085 tcg_out_ld16u_r(s, cond, rd, rn, TCG_REG_TMP); 1086 } else 1087 tcg_out_ld16u_8(s, cond, rd, rn, offset); 1088} 1089 1090static void tcg_out_ld16s(TCGContext *s, ARMCond cond, 1091 TCGReg rd, TCGReg rn, int32_t offset) 1092{ 1093 if (offset > 0xff || offset < -0xff) { 1094 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1095 tcg_out_ld16s_r(s, cond, rd, rn, TCG_REG_TMP); 1096 } else 1097 tcg_out_ld16s_8(s, cond, rd, rn, offset); 1098} 1099 1100static void tcg_out_st16(TCGContext *s, ARMCond cond, 1101 TCGReg rd, TCGReg rn, int32_t offset) 1102{ 1103 if (offset > 0xff || offset < -0xff) { 1104 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1105 tcg_out_st16_r(s, cond, rd, rn, TCG_REG_TMP); 1106 } else 1107 tcg_out_st16_8(s, cond, rd, rn, offset); 1108} 1109 1110static void tcg_out_ld8u(TCGContext *s, ARMCond cond, 1111 TCGReg rd, TCGReg rn, int32_t offset) 1112{ 1113 if (offset > 0xfff || offset < -0xfff) { 1114 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1115 tcg_out_ld8_r(s, cond, rd, rn, TCG_REG_TMP); 1116 } else 1117 tcg_out_ld8_12(s, cond, rd, rn, offset); 1118} 1119 1120static void tcg_out_ld8s(TCGContext *s, ARMCond cond, 1121 TCGReg rd, TCGReg rn, int32_t offset) 1122{ 1123 if (offset > 0xff || offset < -0xff) { 1124 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1125 tcg_out_ld8s_r(s, cond, rd, rn, TCG_REG_TMP); 1126 } else 1127 tcg_out_ld8s_8(s, cond, rd, rn, offset); 1128} 1129 1130static void tcg_out_st8(TCGContext *s, ARMCond cond, 1131 TCGReg rd, TCGReg rn, int32_t offset) 1132{ 1133 if (offset > 0xfff || offset < -0xfff) { 1134 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1135 tcg_out_st8_r(s, cond, rd, rn, TCG_REG_TMP); 1136 } else 1137 tcg_out_st8_12(s, cond, rd, rn, offset); 1138} 1139 1140/* 1141 * The _goto case is normally between TBs within the same code buffer, and 1142 * with the code buffer limited to 16MB we wouldn't need the long case. 1143 * But we also use it for the tail-call to the qemu_ld/st helpers, which does. 1144 */ 1145static void tcg_out_goto(TCGContext *s, ARMCond cond, const tcg_insn_unit *addr) 1146{ 1147 intptr_t addri = (intptr_t)addr; 1148 ptrdiff_t disp = tcg_pcrel_diff(s, addr); 1149 bool arm_mode = !(addri & 1); 1150 1151 if (arm_mode && disp - 8 < 0x01fffffd && disp - 8 > -0x01fffffd) { 1152 tcg_out_b_imm(s, cond, disp); 1153 return; 1154 } 1155 1156 /* LDR is interworking from v5t. */ 1157 tcg_out_movi_pool(s, cond, TCG_REG_PC, addri); 1158} 1159 1160/* 1161 * The call case is mostly used for helpers - so it's not unreasonable 1162 * for them to be beyond branch range. 1163 */ 1164static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *addr) 1165{ 1166 intptr_t addri = (intptr_t)addr; 1167 ptrdiff_t disp = tcg_pcrel_diff(s, addr); 1168 bool arm_mode = !(addri & 1); 1169 1170 if (disp - 8 < 0x02000000 && disp - 8 >= -0x02000000) { 1171 if (arm_mode) { 1172 tcg_out_bl_imm(s, COND_AL, disp); 1173 } else { 1174 tcg_out_blx_imm(s, disp); 1175 } 1176 return; 1177 } 1178 1179 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri); 1180 tcg_out_blx_reg(s, COND_AL, TCG_REG_TMP); 1181} 1182 1183static void tcg_out_call(TCGContext *s, const tcg_insn_unit *addr, 1184 const TCGHelperInfo *info) 1185{ 1186 tcg_out_call_int(s, addr); 1187} 1188 1189static void tcg_out_goto_label(TCGContext *s, ARMCond cond, TCGLabel *l) 1190{ 1191 if (l->has_value) { 1192 tcg_out_goto(s, cond, l->u.value_ptr); 1193 } else { 1194 tcg_out_reloc(s, s->code_ptr, R_ARM_PC24, l, 0); 1195 tcg_out_b_imm(s, cond, 0); 1196 } 1197} 1198 1199static void tcg_out_mb(TCGContext *s, TCGArg a0) 1200{ 1201 if (use_armv7_instructions) { 1202 tcg_out32(s, INSN_DMB_ISH); 1203 } else { 1204 tcg_out32(s, INSN_DMB_MCR); 1205 } 1206} 1207 1208static TCGCond tcg_out_cmp2(TCGContext *s, const TCGArg *args, 1209 const int *const_args) 1210{ 1211 TCGReg al = args[0]; 1212 TCGReg ah = args[1]; 1213 TCGArg bl = args[2]; 1214 TCGArg bh = args[3]; 1215 TCGCond cond = args[4]; 1216 int const_bl = const_args[2]; 1217 int const_bh = const_args[3]; 1218 1219 switch (cond) { 1220 case TCG_COND_EQ: 1221 case TCG_COND_NE: 1222 case TCG_COND_LTU: 1223 case TCG_COND_LEU: 1224 case TCG_COND_GTU: 1225 case TCG_COND_GEU: 1226 /* We perform a conditional comparision. If the high half is 1227 equal, then overwrite the flags with the comparison of the 1228 low half. The resulting flags cover the whole. */ 1229 tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, ah, bh, const_bh); 1230 tcg_out_dat_rI(s, COND_EQ, ARITH_CMP, 0, al, bl, const_bl); 1231 return cond; 1232 1233 case TCG_COND_LT: 1234 case TCG_COND_GE: 1235 /* We perform a double-word subtraction and examine the result. 1236 We do not actually need the result of the subtract, so the 1237 low part "subtract" is a compare. For the high half we have 1238 no choice but to compute into a temporary. */ 1239 tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, al, bl, const_bl); 1240 tcg_out_dat_rI(s, COND_AL, ARITH_SBC | TO_CPSR, 1241 TCG_REG_TMP, ah, bh, const_bh); 1242 return cond; 1243 1244 case TCG_COND_LE: 1245 case TCG_COND_GT: 1246 /* Similar, but with swapped arguments, via reversed subtract. */ 1247 tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR, 1248 TCG_REG_TMP, al, bl, const_bl); 1249 tcg_out_dat_rI(s, COND_AL, ARITH_RSC | TO_CPSR, 1250 TCG_REG_TMP, ah, bh, const_bh); 1251 return tcg_swap_cond(cond); 1252 1253 default: 1254 g_assert_not_reached(); 1255 } 1256} 1257 1258/* 1259 * Note that TCGReg references Q-registers. 1260 * Q-regno = 2 * D-regno, so shift left by 1 whlie inserting. 1261 */ 1262static uint32_t encode_vd(TCGReg rd) 1263{ 1264 tcg_debug_assert(rd >= TCG_REG_Q0); 1265 return (extract32(rd, 3, 1) << 22) | (extract32(rd, 0, 3) << 13); 1266} 1267 1268static uint32_t encode_vn(TCGReg rn) 1269{ 1270 tcg_debug_assert(rn >= TCG_REG_Q0); 1271 return (extract32(rn, 3, 1) << 7) | (extract32(rn, 0, 3) << 17); 1272} 1273 1274static uint32_t encode_vm(TCGReg rm) 1275{ 1276 tcg_debug_assert(rm >= TCG_REG_Q0); 1277 return (extract32(rm, 3, 1) << 5) | (extract32(rm, 0, 3) << 1); 1278} 1279 1280static void tcg_out_vreg2(TCGContext *s, ARMInsn insn, int q, int vece, 1281 TCGReg d, TCGReg m) 1282{ 1283 tcg_out32(s, insn | (vece << 18) | (q << 6) | 1284 encode_vd(d) | encode_vm(m)); 1285} 1286 1287static void tcg_out_vreg3(TCGContext *s, ARMInsn insn, int q, int vece, 1288 TCGReg d, TCGReg n, TCGReg m) 1289{ 1290 tcg_out32(s, insn | (vece << 20) | (q << 6) | 1291 encode_vd(d) | encode_vn(n) | encode_vm(m)); 1292} 1293 1294static void tcg_out_vmovi(TCGContext *s, TCGReg rd, 1295 int q, int op, int cmode, uint8_t imm8) 1296{ 1297 tcg_out32(s, INSN_VMOVI | encode_vd(rd) | (q << 6) | (op << 5) 1298 | (cmode << 8) | extract32(imm8, 0, 4) 1299 | (extract32(imm8, 4, 3) << 16) 1300 | (extract32(imm8, 7, 1) << 24)); 1301} 1302 1303static void tcg_out_vshifti(TCGContext *s, ARMInsn insn, int q, 1304 TCGReg rd, TCGReg rm, int l_imm6) 1305{ 1306 tcg_out32(s, insn | (q << 6) | encode_vd(rd) | encode_vm(rm) | 1307 (extract32(l_imm6, 6, 1) << 7) | 1308 (extract32(l_imm6, 0, 6) << 16)); 1309} 1310 1311static void tcg_out_vldst(TCGContext *s, ARMInsn insn, 1312 TCGReg rd, TCGReg rn, int offset) 1313{ 1314 if (offset != 0) { 1315 if (check_fit_imm(offset) || check_fit_imm(-offset)) { 1316 tcg_out_dat_rIN(s, COND_AL, ARITH_ADD, ARITH_SUB, 1317 TCG_REG_TMP, rn, offset, true); 1318 } else { 1319 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, offset); 1320 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, 1321 TCG_REG_TMP, TCG_REG_TMP, rn, 0); 1322 } 1323 rn = TCG_REG_TMP; 1324 } 1325 tcg_out32(s, insn | (rn << 16) | encode_vd(rd) | 0xf); 1326} 1327 1328typedef struct { 1329 ARMCond cond; 1330 TCGReg base; 1331 int index; 1332 bool index_scratch; 1333} HostAddress; 1334 1335#ifdef CONFIG_SOFTMMU 1336/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, 1337 * int mmu_idx, uintptr_t ra) 1338 */ 1339static void * const qemu_ld_helpers[MO_SSIZE + 1] = { 1340 [MO_UB] = helper_ret_ldub_mmu, 1341 [MO_SB] = helper_ret_ldsb_mmu, 1342#if HOST_BIG_ENDIAN 1343 [MO_UW] = helper_be_lduw_mmu, 1344 [MO_UL] = helper_be_ldul_mmu, 1345 [MO_UQ] = helper_be_ldq_mmu, 1346 [MO_SW] = helper_be_ldsw_mmu, 1347 [MO_SL] = helper_be_ldul_mmu, 1348#else 1349 [MO_UW] = helper_le_lduw_mmu, 1350 [MO_UL] = helper_le_ldul_mmu, 1351 [MO_UQ] = helper_le_ldq_mmu, 1352 [MO_SW] = helper_le_ldsw_mmu, 1353 [MO_SL] = helper_le_ldul_mmu, 1354#endif 1355}; 1356 1357/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr, 1358 * uintxx_t val, int mmu_idx, uintptr_t ra) 1359 */ 1360static void * const qemu_st_helpers[MO_SIZE + 1] = { 1361 [MO_8] = helper_ret_stb_mmu, 1362#if HOST_BIG_ENDIAN 1363 [MO_16] = helper_be_stw_mmu, 1364 [MO_32] = helper_be_stl_mmu, 1365 [MO_64] = helper_be_stq_mmu, 1366#else 1367 [MO_16] = helper_le_stw_mmu, 1368 [MO_32] = helper_le_stl_mmu, 1369 [MO_64] = helper_le_stq_mmu, 1370#endif 1371}; 1372 1373static TCGReg ldst_ra_gen(TCGContext *s, const TCGLabelQemuLdst *l, int arg) 1374{ 1375 /* We arrive at the slow path via "BLNE", so R14 contains l->raddr. */ 1376 return TCG_REG_R14; 1377} 1378 1379static const TCGLdstHelperParam ldst_helper_param = { 1380 .ra_gen = ldst_ra_gen, 1381 .ntmp = 1, 1382 .tmp = { TCG_REG_TMP }, 1383}; 1384 1385static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1386{ 1387 MemOp opc = get_memop(lb->oi); 1388 1389 if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1390 return false; 1391 } 1392 1393 tcg_out_ld_helper_args(s, lb, &ldst_helper_param); 1394 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE]); 1395 tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param); 1396 1397 tcg_out_goto(s, COND_AL, lb->raddr); 1398 return true; 1399} 1400 1401static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1402{ 1403 MemOp opc = get_memop(lb->oi); 1404 1405 if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1406 return false; 1407 } 1408 1409 tcg_out_st_helper_args(s, lb, &ldst_helper_param); 1410 1411 /* Tail-call to the helper, which will return to the fast path. */ 1412 tcg_out_goto(s, COND_AL, qemu_st_helpers[opc & MO_SIZE]); 1413 return true; 1414} 1415#else 1416static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) 1417{ 1418 if (!reloc_pc24(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1419 return false; 1420 } 1421 1422 if (TARGET_LONG_BITS == 64) { 1423 /* 64-bit target address is aligned into R2:R3. */ 1424 TCGMovExtend ext[2] = { 1425 { .dst = TCG_REG_R2, .dst_type = TCG_TYPE_I32, 1426 .src = l->addrlo_reg, 1427 .src_type = TCG_TYPE_I32, .src_ext = MO_UL }, 1428 { .dst = TCG_REG_R3, .dst_type = TCG_TYPE_I32, 1429 .src = l->addrhi_reg, 1430 .src_type = TCG_TYPE_I32, .src_ext = MO_UL }, 1431 }; 1432 tcg_out_movext2(s, &ext[0], &ext[1], TCG_REG_TMP); 1433 } else { 1434 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R1, l->addrlo_reg); 1435 } 1436 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_AREG0); 1437 1438 /* 1439 * Tail call to the helper, with the return address back inline, 1440 * just for the clarity of the debugging traceback -- the helper 1441 * cannot return. We have used BLNE to arrive here, so LR is 1442 * already set. 1443 */ 1444 tcg_out_goto(s, COND_AL, (const void *) 1445 (l->is_ld ? helper_unaligned_ld : helper_unaligned_st)); 1446 return true; 1447} 1448 1449static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1450{ 1451 return tcg_out_fail_alignment(s, l); 1452} 1453 1454static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1455{ 1456 return tcg_out_fail_alignment(s, l); 1457} 1458#endif /* SOFTMMU */ 1459 1460static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1461 TCGReg addrlo, TCGReg addrhi, 1462 MemOpIdx oi, bool is_ld) 1463{ 1464 TCGLabelQemuLdst *ldst = NULL; 1465 MemOp opc = get_memop(oi); 1466 MemOp a_bits = get_alignment_bits(opc); 1467 unsigned a_mask = (1 << a_bits) - 1; 1468 1469#ifdef CONFIG_SOFTMMU 1470 int mem_index = get_mmuidx(oi); 1471 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read) 1472 : offsetof(CPUTLBEntry, addr_write); 1473 int fast_off = TLB_MASK_TABLE_OFS(mem_index); 1474 unsigned s_mask = (1 << (opc & MO_SIZE)) - 1; 1475 TCGReg t_addr; 1476 1477 ldst = new_ldst_label(s); 1478 ldst->is_ld = is_ld; 1479 ldst->oi = oi; 1480 ldst->addrlo_reg = addrlo; 1481 ldst->addrhi_reg = addrhi; 1482 1483 /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {r0,r1}. */ 1484 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); 1485 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -256); 1486 QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0); 1487 QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != 4); 1488 tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off); 1489 1490 /* Extract the tlb index from the address into R0. */ 1491 tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, addrlo, 1492 SHIFT_IMM_LSR(TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS)); 1493 1494 /* 1495 * Add the tlb_table pointer, creating the CPUTLBEntry address in R1. 1496 * Load the tlb comparator into R2/R3 and the fast path addend into R1. 1497 */ 1498 if (cmp_off == 0) { 1499 if (TARGET_LONG_BITS == 64) { 1500 tcg_out_ldrd_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0); 1501 } else { 1502 tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0); 1503 } 1504 } else { 1505 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, 1506 TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0); 1507 if (TARGET_LONG_BITS == 64) { 1508 tcg_out_ldrd_8(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); 1509 } else { 1510 tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); 1511 } 1512 } 1513 1514 /* Load the tlb addend. */ 1515 tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R1, 1516 offsetof(CPUTLBEntry, addend)); 1517 1518 /* 1519 * Check alignment, check comparators. 1520 * Do this in 2-4 insns. Use MOVW for v7, if possible, 1521 * to reduce the number of sequential conditional instructions. 1522 * Almost all guests have at least 4k pages, which means that we need 1523 * to clear at least 9 bits even for an 8-byte memory, which means it 1524 * isn't worth checking for an immediate operand for BIC. 1525 * 1526 * For unaligned accesses, test the page of the last unit of alignment. 1527 * This leaves the least significant alignment bits unchanged, and of 1528 * course must be zero. 1529 */ 1530 t_addr = addrlo; 1531 if (a_mask < s_mask) { 1532 t_addr = TCG_REG_R0; 1533 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, t_addr, 1534 addrlo, s_mask - a_mask); 1535 } 1536 if (use_armv7_instructions && TARGET_PAGE_BITS <= 16) { 1537 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, ~(TARGET_PAGE_MASK | a_mask)); 1538 tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP, 1539 t_addr, TCG_REG_TMP, 0); 1540 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R2, TCG_REG_TMP, 0); 1541 } else { 1542 if (a_mask) { 1543 tcg_debug_assert(a_mask <= 0xff); 1544 tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask); 1545 } 1546 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, t_addr, 1547 SHIFT_IMM_LSR(TARGET_PAGE_BITS)); 1548 tcg_out_dat_reg(s, (a_mask ? COND_EQ : COND_AL), ARITH_CMP, 1549 0, TCG_REG_R2, TCG_REG_TMP, 1550 SHIFT_IMM_LSL(TARGET_PAGE_BITS)); 1551 } 1552 1553 if (TARGET_LONG_BITS == 64) { 1554 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R3, addrhi, 0); 1555 } 1556 1557 *h = (HostAddress){ 1558 .cond = COND_AL, 1559 .base = addrlo, 1560 .index = TCG_REG_R1, 1561 .index_scratch = true, 1562 }; 1563#else 1564 if (a_mask) { 1565 ldst = new_ldst_label(s); 1566 ldst->is_ld = is_ld; 1567 ldst->oi = oi; 1568 ldst->addrlo_reg = addrlo; 1569 ldst->addrhi_reg = addrhi; 1570 1571 /* We are expecting a_bits to max out at 7 */ 1572 tcg_debug_assert(a_mask <= 0xff); 1573 /* tst addr, #mask */ 1574 tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask); 1575 } 1576 1577 *h = (HostAddress){ 1578 .cond = COND_AL, 1579 .base = addrlo, 1580 .index = guest_base ? TCG_REG_GUEST_BASE : -1, 1581 .index_scratch = false, 1582 }; 1583#endif 1584 1585 return ldst; 1586} 1587 1588static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo, 1589 TCGReg datahi, HostAddress h) 1590{ 1591 TCGReg base; 1592 1593 /* Byte swapping is left to middle-end expansion. */ 1594 tcg_debug_assert((opc & MO_BSWAP) == 0); 1595 1596 switch (opc & MO_SSIZE) { 1597 case MO_UB: 1598 if (h.index < 0) { 1599 tcg_out_ld8_12(s, h.cond, datalo, h.base, 0); 1600 } else { 1601 tcg_out_ld8_r(s, h.cond, datalo, h.base, h.index); 1602 } 1603 break; 1604 case MO_SB: 1605 if (h.index < 0) { 1606 tcg_out_ld8s_8(s, h.cond, datalo, h.base, 0); 1607 } else { 1608 tcg_out_ld8s_r(s, h.cond, datalo, h.base, h.index); 1609 } 1610 break; 1611 case MO_UW: 1612 if (h.index < 0) { 1613 tcg_out_ld16u_8(s, h.cond, datalo, h.base, 0); 1614 } else { 1615 tcg_out_ld16u_r(s, h.cond, datalo, h.base, h.index); 1616 } 1617 break; 1618 case MO_SW: 1619 if (h.index < 0) { 1620 tcg_out_ld16s_8(s, h.cond, datalo, h.base, 0); 1621 } else { 1622 tcg_out_ld16s_r(s, h.cond, datalo, h.base, h.index); 1623 } 1624 break; 1625 case MO_UL: 1626 if (h.index < 0) { 1627 tcg_out_ld32_12(s, h.cond, datalo, h.base, 0); 1628 } else { 1629 tcg_out_ld32_r(s, h.cond, datalo, h.base, h.index); 1630 } 1631 break; 1632 case MO_UQ: 1633 /* We used pair allocation for datalo, so already should be aligned. */ 1634 tcg_debug_assert((datalo & 1) == 0); 1635 tcg_debug_assert(datahi == datalo + 1); 1636 /* LDRD requires alignment; double-check that. */ 1637 if (get_alignment_bits(opc) >= MO_64) { 1638 if (h.index < 0) { 1639 tcg_out_ldrd_8(s, h.cond, datalo, h.base, 0); 1640 break; 1641 } 1642 /* 1643 * Rm (the second address op) must not overlap Rt or Rt + 1. 1644 * Since datalo is aligned, we can simplify the test via alignment. 1645 * Flip the two address arguments if that works. 1646 */ 1647 if ((h.index & ~1) != datalo) { 1648 tcg_out_ldrd_r(s, h.cond, datalo, h.base, h.index); 1649 break; 1650 } 1651 if ((h.base & ~1) != datalo) { 1652 tcg_out_ldrd_r(s, h.cond, datalo, h.index, h.base); 1653 break; 1654 } 1655 } 1656 if (h.index < 0) { 1657 base = h.base; 1658 if (datalo == h.base) { 1659 tcg_out_mov_reg(s, h.cond, TCG_REG_TMP, base); 1660 base = TCG_REG_TMP; 1661 } 1662 } else if (h.index_scratch) { 1663 tcg_out_ld32_rwb(s, h.cond, datalo, h.index, h.base); 1664 tcg_out_ld32_12(s, h.cond, datahi, h.index, 4); 1665 break; 1666 } else { 1667 tcg_out_dat_reg(s, h.cond, ARITH_ADD, TCG_REG_TMP, 1668 h.base, h.index, SHIFT_IMM_LSL(0)); 1669 base = TCG_REG_TMP; 1670 } 1671 tcg_out_ld32_12(s, h.cond, datalo, base, 0); 1672 tcg_out_ld32_12(s, h.cond, datahi, base, 4); 1673 break; 1674 default: 1675 g_assert_not_reached(); 1676 } 1677} 1678 1679static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, 1680 TCGReg addrlo, TCGReg addrhi, 1681 MemOpIdx oi, TCGType data_type) 1682{ 1683 MemOp opc = get_memop(oi); 1684 TCGLabelQemuLdst *ldst; 1685 HostAddress h; 1686 1687 ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, true); 1688 if (ldst) { 1689 ldst->type = data_type; 1690 ldst->datalo_reg = datalo; 1691 ldst->datahi_reg = datahi; 1692 1693 /* 1694 * This a conditional BL only to load a pointer within this 1695 * opcode into LR for the slow path. We will not be using 1696 * the value for a tail call. 1697 */ 1698 ldst->label_ptr[0] = s->code_ptr; 1699 tcg_out_bl_imm(s, COND_NE, 0); 1700 1701 tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); 1702 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1703 } else { 1704 tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); 1705 } 1706} 1707 1708static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo, 1709 TCGReg datahi, HostAddress h) 1710{ 1711 /* Byte swapping is left to middle-end expansion. */ 1712 tcg_debug_assert((opc & MO_BSWAP) == 0); 1713 1714 switch (opc & MO_SIZE) { 1715 case MO_8: 1716 if (h.index < 0) { 1717 tcg_out_st8_12(s, h.cond, datalo, h.base, 0); 1718 } else { 1719 tcg_out_st8_r(s, h.cond, datalo, h.base, h.index); 1720 } 1721 break; 1722 case MO_16: 1723 if (h.index < 0) { 1724 tcg_out_st16_8(s, h.cond, datalo, h.base, 0); 1725 } else { 1726 tcg_out_st16_r(s, h.cond, datalo, h.base, h.index); 1727 } 1728 break; 1729 case MO_32: 1730 if (h.index < 0) { 1731 tcg_out_st32_12(s, h.cond, datalo, h.base, 0); 1732 } else { 1733 tcg_out_st32_r(s, h.cond, datalo, h.base, h.index); 1734 } 1735 break; 1736 case MO_64: 1737 /* We used pair allocation for datalo, so already should be aligned. */ 1738 tcg_debug_assert((datalo & 1) == 0); 1739 tcg_debug_assert(datahi == datalo + 1); 1740 /* STRD requires alignment; double-check that. */ 1741 if (get_alignment_bits(opc) >= MO_64) { 1742 if (h.index < 0) { 1743 tcg_out_strd_8(s, h.cond, datalo, h.base, 0); 1744 } else { 1745 tcg_out_strd_r(s, h.cond, datalo, h.base, h.index); 1746 } 1747 } else if (h.index_scratch) { 1748 tcg_out_st32_rwb(s, h.cond, datalo, h.index, h.base); 1749 tcg_out_st32_12(s, h.cond, datahi, h.index, 4); 1750 } else { 1751 tcg_out_dat_reg(s, h.cond, ARITH_ADD, TCG_REG_TMP, 1752 h.base, h.index, SHIFT_IMM_LSL(0)); 1753 tcg_out_st32_12(s, h.cond, datalo, TCG_REG_TMP, 0); 1754 tcg_out_st32_12(s, h.cond, datahi, TCG_REG_TMP, 4); 1755 } 1756 break; 1757 default: 1758 g_assert_not_reached(); 1759 } 1760} 1761 1762static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, 1763 TCGReg addrlo, TCGReg addrhi, 1764 MemOpIdx oi, TCGType data_type) 1765{ 1766 MemOp opc = get_memop(oi); 1767 TCGLabelQemuLdst *ldst; 1768 HostAddress h; 1769 1770 ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, false); 1771 if (ldst) { 1772 ldst->type = data_type; 1773 ldst->datalo_reg = datalo; 1774 ldst->datahi_reg = datahi; 1775 1776 h.cond = COND_EQ; 1777 tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); 1778 1779 /* The conditional call is last, as we're going to return here. */ 1780 ldst->label_ptr[0] = s->code_ptr; 1781 tcg_out_bl_imm(s, COND_NE, 0); 1782 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1783 } else { 1784 tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); 1785 } 1786} 1787 1788static void tcg_out_epilogue(TCGContext *s); 1789 1790static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg) 1791{ 1792 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, arg); 1793 tcg_out_epilogue(s); 1794} 1795 1796static void tcg_out_goto_tb(TCGContext *s, int which) 1797{ 1798 uintptr_t i_addr; 1799 intptr_t i_disp; 1800 1801 /* Direct branch will be patched by tb_target_set_jmp_target. */ 1802 set_jmp_insn_offset(s, which); 1803 tcg_out32(s, INSN_NOP); 1804 1805 /* When branch is out of range, fall through to indirect. */ 1806 i_addr = get_jmp_target_addr(s, which); 1807 i_disp = tcg_pcrel_diff(s, (void *)i_addr) - 8; 1808 tcg_debug_assert(i_disp < 0); 1809 if (i_disp >= -0xfff) { 1810 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, i_disp); 1811 } else { 1812 /* 1813 * The TB is close, but outside the 12 bits addressable by 1814 * the load. We can extend this to 20 bits with a sub of a 1815 * shifted immediate from pc. 1816 */ 1817 int h = -i_disp; 1818 int l = h & 0xfff; 1819 1820 h = encode_imm_nofail(h - l); 1821 tcg_out_dat_imm(s, COND_AL, ARITH_SUB, TCG_REG_R0, TCG_REG_PC, h); 1822 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_R0, l); 1823 } 1824 set_jmp_reset_offset(s, which); 1825} 1826 1827void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1828 uintptr_t jmp_rx, uintptr_t jmp_rw) 1829{ 1830 uintptr_t addr = tb->jmp_target_addr[n]; 1831 ptrdiff_t offset = addr - (jmp_rx + 8); 1832 tcg_insn_unit insn; 1833 1834 /* Either directly branch, or fall through to indirect branch. */ 1835 if (offset == sextract64(offset, 0, 26)) { 1836 /* B <addr> */ 1837 insn = deposit32((COND_AL << 28) | INSN_B, 0, 24, offset >> 2); 1838 } else { 1839 insn = INSN_NOP; 1840 } 1841 1842 qatomic_set((uint32_t *)jmp_rw, insn); 1843 flush_idcache_range(jmp_rx, jmp_rw, 4); 1844} 1845 1846static void tcg_out_op(TCGContext *s, TCGOpcode opc, 1847 const TCGArg args[TCG_MAX_OP_ARGS], 1848 const int const_args[TCG_MAX_OP_ARGS]) 1849{ 1850 TCGArg a0, a1, a2, a3, a4, a5; 1851 int c; 1852 1853 switch (opc) { 1854 case INDEX_op_goto_ptr: 1855 tcg_out_b_reg(s, COND_AL, args[0]); 1856 break; 1857 case INDEX_op_br: 1858 tcg_out_goto_label(s, COND_AL, arg_label(args[0])); 1859 break; 1860 1861 case INDEX_op_ld8u_i32: 1862 tcg_out_ld8u(s, COND_AL, args[0], args[1], args[2]); 1863 break; 1864 case INDEX_op_ld8s_i32: 1865 tcg_out_ld8s(s, COND_AL, args[0], args[1], args[2]); 1866 break; 1867 case INDEX_op_ld16u_i32: 1868 tcg_out_ld16u(s, COND_AL, args[0], args[1], args[2]); 1869 break; 1870 case INDEX_op_ld16s_i32: 1871 tcg_out_ld16s(s, COND_AL, args[0], args[1], args[2]); 1872 break; 1873 case INDEX_op_ld_i32: 1874 tcg_out_ld32u(s, COND_AL, args[0], args[1], args[2]); 1875 break; 1876 case INDEX_op_st8_i32: 1877 tcg_out_st8(s, COND_AL, args[0], args[1], args[2]); 1878 break; 1879 case INDEX_op_st16_i32: 1880 tcg_out_st16(s, COND_AL, args[0], args[1], args[2]); 1881 break; 1882 case INDEX_op_st_i32: 1883 tcg_out_st32(s, COND_AL, args[0], args[1], args[2]); 1884 break; 1885 1886 case INDEX_op_movcond_i32: 1887 /* Constraints mean that v2 is always in the same register as dest, 1888 * so we only need to do "if condition passed, move v1 to dest". 1889 */ 1890 tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, 1891 args[1], args[2], const_args[2]); 1892 tcg_out_dat_rIK(s, tcg_cond_to_arm_cond[args[5]], ARITH_MOV, 1893 ARITH_MVN, args[0], 0, args[3], const_args[3]); 1894 break; 1895 case INDEX_op_add_i32: 1896 tcg_out_dat_rIN(s, COND_AL, ARITH_ADD, ARITH_SUB, 1897 args[0], args[1], args[2], const_args[2]); 1898 break; 1899 case INDEX_op_sub_i32: 1900 if (const_args[1]) { 1901 if (const_args[2]) { 1902 tcg_out_movi32(s, COND_AL, args[0], args[1] - args[2]); 1903 } else { 1904 tcg_out_dat_rI(s, COND_AL, ARITH_RSB, 1905 args[0], args[2], args[1], 1); 1906 } 1907 } else { 1908 tcg_out_dat_rIN(s, COND_AL, ARITH_SUB, ARITH_ADD, 1909 args[0], args[1], args[2], const_args[2]); 1910 } 1911 break; 1912 case INDEX_op_and_i32: 1913 tcg_out_dat_rIK(s, COND_AL, ARITH_AND, ARITH_BIC, 1914 args[0], args[1], args[2], const_args[2]); 1915 break; 1916 case INDEX_op_andc_i32: 1917 tcg_out_dat_rIK(s, COND_AL, ARITH_BIC, ARITH_AND, 1918 args[0], args[1], args[2], const_args[2]); 1919 break; 1920 case INDEX_op_or_i32: 1921 c = ARITH_ORR; 1922 goto gen_arith; 1923 case INDEX_op_xor_i32: 1924 c = ARITH_EOR; 1925 /* Fall through. */ 1926 gen_arith: 1927 tcg_out_dat_rI(s, COND_AL, c, args[0], args[1], args[2], const_args[2]); 1928 break; 1929 case INDEX_op_add2_i32: 1930 a0 = args[0], a1 = args[1], a2 = args[2]; 1931 a3 = args[3], a4 = args[4], a5 = args[5]; 1932 if (a0 == a3 || (a0 == a5 && !const_args[5])) { 1933 a0 = TCG_REG_TMP; 1934 } 1935 tcg_out_dat_rIN(s, COND_AL, ARITH_ADD | TO_CPSR, ARITH_SUB | TO_CPSR, 1936 a0, a2, a4, const_args[4]); 1937 tcg_out_dat_rIK(s, COND_AL, ARITH_ADC, ARITH_SBC, 1938 a1, a3, a5, const_args[5]); 1939 tcg_out_mov_reg(s, COND_AL, args[0], a0); 1940 break; 1941 case INDEX_op_sub2_i32: 1942 a0 = args[0], a1 = args[1], a2 = args[2]; 1943 a3 = args[3], a4 = args[4], a5 = args[5]; 1944 if ((a0 == a3 && !const_args[3]) || (a0 == a5 && !const_args[5])) { 1945 a0 = TCG_REG_TMP; 1946 } 1947 if (const_args[2]) { 1948 if (const_args[4]) { 1949 tcg_out_movi32(s, COND_AL, a0, a4); 1950 a4 = a0; 1951 } 1952 tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR, a0, a4, a2, 1); 1953 } else { 1954 tcg_out_dat_rIN(s, COND_AL, ARITH_SUB | TO_CPSR, 1955 ARITH_ADD | TO_CPSR, a0, a2, a4, const_args[4]); 1956 } 1957 if (const_args[3]) { 1958 if (const_args[5]) { 1959 tcg_out_movi32(s, COND_AL, a1, a5); 1960 a5 = a1; 1961 } 1962 tcg_out_dat_rI(s, COND_AL, ARITH_RSC, a1, a5, a3, 1); 1963 } else { 1964 tcg_out_dat_rIK(s, COND_AL, ARITH_SBC, ARITH_ADC, 1965 a1, a3, a5, const_args[5]); 1966 } 1967 tcg_out_mov_reg(s, COND_AL, args[0], a0); 1968 break; 1969 case INDEX_op_neg_i32: 1970 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, args[0], args[1], 0); 1971 break; 1972 case INDEX_op_not_i32: 1973 tcg_out_dat_reg(s, COND_AL, 1974 ARITH_MVN, args[0], 0, args[1], SHIFT_IMM_LSL(0)); 1975 break; 1976 case INDEX_op_mul_i32: 1977 tcg_out_mul32(s, COND_AL, args[0], args[1], args[2]); 1978 break; 1979 case INDEX_op_mulu2_i32: 1980 tcg_out_umull32(s, COND_AL, args[0], args[1], args[2], args[3]); 1981 break; 1982 case INDEX_op_muls2_i32: 1983 tcg_out_smull32(s, COND_AL, args[0], args[1], args[2], args[3]); 1984 break; 1985 /* XXX: Perhaps args[2] & 0x1f is wrong */ 1986 case INDEX_op_shl_i32: 1987 c = const_args[2] ? 1988 SHIFT_IMM_LSL(args[2] & 0x1f) : SHIFT_REG_LSL(args[2]); 1989 goto gen_shift32; 1990 case INDEX_op_shr_i32: 1991 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_LSR(args[2] & 0x1f) : 1992 SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args[2]); 1993 goto gen_shift32; 1994 case INDEX_op_sar_i32: 1995 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ASR(args[2] & 0x1f) : 1996 SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args[2]); 1997 goto gen_shift32; 1998 case INDEX_op_rotr_i32: 1999 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ROR(args[2] & 0x1f) : 2000 SHIFT_IMM_LSL(0) : SHIFT_REG_ROR(args[2]); 2001 /* Fall through. */ 2002 gen_shift32: 2003 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], c); 2004 break; 2005 2006 case INDEX_op_rotl_i32: 2007 if (const_args[2]) { 2008 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], 2009 ((0x20 - args[2]) & 0x1f) ? 2010 SHIFT_IMM_ROR((0x20 - args[2]) & 0x1f) : 2011 SHIFT_IMM_LSL(0)); 2012 } else { 2013 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, TCG_REG_TMP, args[2], 0x20); 2014 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], 2015 SHIFT_REG_ROR(TCG_REG_TMP)); 2016 } 2017 break; 2018 2019 case INDEX_op_ctz_i32: 2020 tcg_out_dat_reg(s, COND_AL, INSN_RBIT, TCG_REG_TMP, 0, args[1], 0); 2021 a1 = TCG_REG_TMP; 2022 goto do_clz; 2023 2024 case INDEX_op_clz_i32: 2025 a1 = args[1]; 2026 do_clz: 2027 a0 = args[0]; 2028 a2 = args[2]; 2029 c = const_args[2]; 2030 if (c && a2 == 32) { 2031 tcg_out_dat_reg(s, COND_AL, INSN_CLZ, a0, 0, a1, 0); 2032 break; 2033 } 2034 tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0, a1, 0); 2035 tcg_out_dat_reg(s, COND_NE, INSN_CLZ, a0, 0, a1, 0); 2036 if (c || a0 != a2) { 2037 tcg_out_dat_rIK(s, COND_EQ, ARITH_MOV, ARITH_MVN, a0, 0, a2, c); 2038 } 2039 break; 2040 2041 case INDEX_op_brcond_i32: 2042 tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, 2043 args[0], args[1], const_args[1]); 2044 tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[2]], 2045 arg_label(args[3])); 2046 break; 2047 case INDEX_op_setcond_i32: 2048 tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, 2049 args[1], args[2], const_args[2]); 2050 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[3]], 2051 ARITH_MOV, args[0], 0, 1); 2052 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[3])], 2053 ARITH_MOV, args[0], 0, 0); 2054 break; 2055 2056 case INDEX_op_brcond2_i32: 2057 c = tcg_out_cmp2(s, args, const_args); 2058 tcg_out_goto_label(s, tcg_cond_to_arm_cond[c], arg_label(args[5])); 2059 break; 2060 case INDEX_op_setcond2_i32: 2061 c = tcg_out_cmp2(s, args + 1, const_args + 1); 2062 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[c], ARITH_MOV, args[0], 0, 1); 2063 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(c)], 2064 ARITH_MOV, args[0], 0, 0); 2065 break; 2066 2067 case INDEX_op_qemu_ld_i32: 2068 if (TARGET_LONG_BITS == 32) { 2069 tcg_out_qemu_ld(s, args[0], -1, args[1], -1, 2070 args[2], TCG_TYPE_I32); 2071 } else { 2072 tcg_out_qemu_ld(s, args[0], -1, args[1], args[2], 2073 args[3], TCG_TYPE_I32); 2074 } 2075 break; 2076 case INDEX_op_qemu_ld_i64: 2077 if (TARGET_LONG_BITS == 32) { 2078 tcg_out_qemu_ld(s, args[0], args[1], args[2], -1, 2079 args[3], TCG_TYPE_I64); 2080 } else { 2081 tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3], 2082 args[4], TCG_TYPE_I64); 2083 } 2084 break; 2085 case INDEX_op_qemu_st_i32: 2086 if (TARGET_LONG_BITS == 32) { 2087 tcg_out_qemu_st(s, args[0], -1, args[1], -1, 2088 args[2], TCG_TYPE_I32); 2089 } else { 2090 tcg_out_qemu_st(s, args[0], -1, args[1], args[2], 2091 args[3], TCG_TYPE_I32); 2092 } 2093 break; 2094 case INDEX_op_qemu_st_i64: 2095 if (TARGET_LONG_BITS == 32) { 2096 tcg_out_qemu_st(s, args[0], args[1], args[2], -1, 2097 args[3], TCG_TYPE_I64); 2098 } else { 2099 tcg_out_qemu_st(s, args[0], args[1], args[2], args[3], 2100 args[4], TCG_TYPE_I64); 2101 } 2102 break; 2103 2104 case INDEX_op_bswap16_i32: 2105 tcg_out_bswap16(s, COND_AL, args[0], args[1], args[2]); 2106 break; 2107 case INDEX_op_bswap32_i32: 2108 tcg_out_bswap32(s, COND_AL, args[0], args[1]); 2109 break; 2110 2111 case INDEX_op_deposit_i32: 2112 tcg_out_deposit(s, COND_AL, args[0], args[2], 2113 args[3], args[4], const_args[2]); 2114 break; 2115 case INDEX_op_extract_i32: 2116 tcg_out_extract(s, COND_AL, args[0], args[1], args[2], args[3]); 2117 break; 2118 case INDEX_op_sextract_i32: 2119 tcg_out_sextract(s, COND_AL, args[0], args[1], args[2], args[3]); 2120 break; 2121 case INDEX_op_extract2_i32: 2122 /* ??? These optimization vs zero should be generic. */ 2123 /* ??? But we can't substitute 2 for 1 in the opcode stream yet. */ 2124 if (const_args[1]) { 2125 if (const_args[2]) { 2126 tcg_out_movi(s, TCG_TYPE_REG, args[0], 0); 2127 } else { 2128 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, 2129 args[2], SHIFT_IMM_LSL(32 - args[3])); 2130 } 2131 } else if (const_args[2]) { 2132 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, 2133 args[1], SHIFT_IMM_LSR(args[3])); 2134 } else { 2135 /* We can do extract2 in 2 insns, vs the 3 required otherwise. */ 2136 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, 2137 args[2], SHIFT_IMM_LSL(32 - args[3])); 2138 tcg_out_dat_reg(s, COND_AL, ARITH_ORR, args[0], TCG_REG_TMP, 2139 args[1], SHIFT_IMM_LSR(args[3])); 2140 } 2141 break; 2142 2143 case INDEX_op_div_i32: 2144 tcg_out_sdiv(s, COND_AL, args[0], args[1], args[2]); 2145 break; 2146 case INDEX_op_divu_i32: 2147 tcg_out_udiv(s, COND_AL, args[0], args[1], args[2]); 2148 break; 2149 2150 case INDEX_op_mb: 2151 tcg_out_mb(s, args[0]); 2152 break; 2153 2154 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ 2155 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2156 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2157 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2158 case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ 2159 case INDEX_op_ext8u_i32: 2160 case INDEX_op_ext16s_i32: 2161 case INDEX_op_ext16u_i32: 2162 default: 2163 g_assert_not_reached(); 2164 } 2165} 2166 2167static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) 2168{ 2169 switch (op) { 2170 case INDEX_op_goto_ptr: 2171 return C_O0_I1(r); 2172 2173 case INDEX_op_ld8u_i32: 2174 case INDEX_op_ld8s_i32: 2175 case INDEX_op_ld16u_i32: 2176 case INDEX_op_ld16s_i32: 2177 case INDEX_op_ld_i32: 2178 case INDEX_op_neg_i32: 2179 case INDEX_op_not_i32: 2180 case INDEX_op_bswap16_i32: 2181 case INDEX_op_bswap32_i32: 2182 case INDEX_op_ext8s_i32: 2183 case INDEX_op_ext16s_i32: 2184 case INDEX_op_ext16u_i32: 2185 case INDEX_op_extract_i32: 2186 case INDEX_op_sextract_i32: 2187 return C_O1_I1(r, r); 2188 2189 case INDEX_op_st8_i32: 2190 case INDEX_op_st16_i32: 2191 case INDEX_op_st_i32: 2192 return C_O0_I2(r, r); 2193 2194 case INDEX_op_add_i32: 2195 case INDEX_op_sub_i32: 2196 case INDEX_op_setcond_i32: 2197 return C_O1_I2(r, r, rIN); 2198 2199 case INDEX_op_and_i32: 2200 case INDEX_op_andc_i32: 2201 case INDEX_op_clz_i32: 2202 case INDEX_op_ctz_i32: 2203 return C_O1_I2(r, r, rIK); 2204 2205 case INDEX_op_mul_i32: 2206 case INDEX_op_div_i32: 2207 case INDEX_op_divu_i32: 2208 return C_O1_I2(r, r, r); 2209 2210 case INDEX_op_mulu2_i32: 2211 case INDEX_op_muls2_i32: 2212 return C_O2_I2(r, r, r, r); 2213 2214 case INDEX_op_or_i32: 2215 case INDEX_op_xor_i32: 2216 return C_O1_I2(r, r, rI); 2217 2218 case INDEX_op_shl_i32: 2219 case INDEX_op_shr_i32: 2220 case INDEX_op_sar_i32: 2221 case INDEX_op_rotl_i32: 2222 case INDEX_op_rotr_i32: 2223 return C_O1_I2(r, r, ri); 2224 2225 case INDEX_op_brcond_i32: 2226 return C_O0_I2(r, rIN); 2227 case INDEX_op_deposit_i32: 2228 return C_O1_I2(r, 0, rZ); 2229 case INDEX_op_extract2_i32: 2230 return C_O1_I2(r, rZ, rZ); 2231 case INDEX_op_movcond_i32: 2232 return C_O1_I4(r, r, rIN, rIK, 0); 2233 case INDEX_op_add2_i32: 2234 return C_O2_I4(r, r, r, r, rIN, rIK); 2235 case INDEX_op_sub2_i32: 2236 return C_O2_I4(r, r, rI, rI, rIN, rIK); 2237 case INDEX_op_brcond2_i32: 2238 return C_O0_I4(r, r, rI, rI); 2239 case INDEX_op_setcond2_i32: 2240 return C_O1_I4(r, r, r, rI, rI); 2241 2242 case INDEX_op_qemu_ld_i32: 2243 return TARGET_LONG_BITS == 32 ? C_O1_I1(r, l) : C_O1_I2(r, l, l); 2244 case INDEX_op_qemu_ld_i64: 2245 return TARGET_LONG_BITS == 32 ? C_O2_I1(e, p, l) : C_O2_I2(e, p, l, l); 2246 case INDEX_op_qemu_st_i32: 2247 return TARGET_LONG_BITS == 32 ? C_O0_I2(s, s) : C_O0_I3(s, s, s); 2248 case INDEX_op_qemu_st_i64: 2249 return TARGET_LONG_BITS == 32 ? C_O0_I3(S, p, s) : C_O0_I4(S, p, s, s); 2250 2251 case INDEX_op_st_vec: 2252 return C_O0_I2(w, r); 2253 case INDEX_op_ld_vec: 2254 case INDEX_op_dupm_vec: 2255 return C_O1_I1(w, r); 2256 case INDEX_op_dup_vec: 2257 return C_O1_I1(w, wr); 2258 case INDEX_op_abs_vec: 2259 case INDEX_op_neg_vec: 2260 case INDEX_op_not_vec: 2261 case INDEX_op_shli_vec: 2262 case INDEX_op_shri_vec: 2263 case INDEX_op_sari_vec: 2264 return C_O1_I1(w, w); 2265 case INDEX_op_dup2_vec: 2266 case INDEX_op_add_vec: 2267 case INDEX_op_mul_vec: 2268 case INDEX_op_smax_vec: 2269 case INDEX_op_smin_vec: 2270 case INDEX_op_ssadd_vec: 2271 case INDEX_op_sssub_vec: 2272 case INDEX_op_sub_vec: 2273 case INDEX_op_umax_vec: 2274 case INDEX_op_umin_vec: 2275 case INDEX_op_usadd_vec: 2276 case INDEX_op_ussub_vec: 2277 case INDEX_op_xor_vec: 2278 case INDEX_op_arm_sshl_vec: 2279 case INDEX_op_arm_ushl_vec: 2280 return C_O1_I2(w, w, w); 2281 case INDEX_op_arm_sli_vec: 2282 return C_O1_I2(w, 0, w); 2283 case INDEX_op_or_vec: 2284 case INDEX_op_andc_vec: 2285 return C_O1_I2(w, w, wO); 2286 case INDEX_op_and_vec: 2287 case INDEX_op_orc_vec: 2288 return C_O1_I2(w, w, wV); 2289 case INDEX_op_cmp_vec: 2290 return C_O1_I2(w, w, wZ); 2291 case INDEX_op_bitsel_vec: 2292 return C_O1_I3(w, w, w, w); 2293 default: 2294 g_assert_not_reached(); 2295 } 2296} 2297 2298static void tcg_target_init(TCGContext *s) 2299{ 2300 /* 2301 * Only probe for the platform and capabilities if we haven't already 2302 * determined maximum values at compile time. 2303 */ 2304#if !defined(use_idiv_instructions) || !defined(use_neon_instructions) 2305 { 2306 unsigned long hwcap = qemu_getauxval(AT_HWCAP); 2307#ifndef use_idiv_instructions 2308 use_idiv_instructions = (hwcap & HWCAP_ARM_IDIVA) != 0; 2309#endif 2310#ifndef use_neon_instructions 2311 use_neon_instructions = (hwcap & HWCAP_ARM_NEON) != 0; 2312#endif 2313 } 2314#endif 2315 2316 if (__ARM_ARCH < 7) { 2317 const char *pl = (const char *)qemu_getauxval(AT_PLATFORM); 2318 if (pl != NULL && pl[0] == 'v' && pl[1] >= '4' && pl[1] <= '9') { 2319 arm_arch = pl[1] - '0'; 2320 } 2321 2322 if (arm_arch < 6) { 2323 error_report("TCG: ARMv%d is unsupported; exiting", arm_arch); 2324 exit(EXIT_FAILURE); 2325 } 2326 } 2327 2328 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS; 2329 2330 tcg_target_call_clobber_regs = 0; 2331 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); 2332 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1); 2333 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2); 2334 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3); 2335 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12); 2336 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14); 2337 2338 if (use_neon_instructions) { 2339 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS; 2340 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS; 2341 2342 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q0); 2343 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q1); 2344 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q2); 2345 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q3); 2346 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q8); 2347 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q9); 2348 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q10); 2349 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q11); 2350 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q12); 2351 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q13); 2352 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q14); 2353 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q15); 2354 } 2355 2356 s->reserved_regs = 0; 2357 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); 2358 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP); 2359 tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC); 2360 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP); 2361} 2362 2363static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 2364 TCGReg arg1, intptr_t arg2) 2365{ 2366 switch (type) { 2367 case TCG_TYPE_I32: 2368 tcg_out_ld32u(s, COND_AL, arg, arg1, arg2); 2369 return; 2370 case TCG_TYPE_V64: 2371 /* regs 1; size 8; align 8 */ 2372 tcg_out_vldst(s, INSN_VLD1 | 0x7d0, arg, arg1, arg2); 2373 return; 2374 case TCG_TYPE_V128: 2375 /* 2376 * We have only 8-byte alignment for the stack per the ABI. 2377 * Rather than dynamically re-align the stack, it's easier 2378 * to simply not request alignment beyond that. So: 2379 * regs 2; size 8; align 8 2380 */ 2381 tcg_out_vldst(s, INSN_VLD1 | 0xad0, arg, arg1, arg2); 2382 return; 2383 default: 2384 g_assert_not_reached(); 2385 } 2386} 2387 2388static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 2389 TCGReg arg1, intptr_t arg2) 2390{ 2391 switch (type) { 2392 case TCG_TYPE_I32: 2393 tcg_out_st32(s, COND_AL, arg, arg1, arg2); 2394 return; 2395 case TCG_TYPE_V64: 2396 /* regs 1; size 8; align 8 */ 2397 tcg_out_vldst(s, INSN_VST1 | 0x7d0, arg, arg1, arg2); 2398 return; 2399 case TCG_TYPE_V128: 2400 /* See tcg_out_ld re alignment: regs 2; size 8; align 8 */ 2401 tcg_out_vldst(s, INSN_VST1 | 0xad0, arg, arg1, arg2); 2402 return; 2403 default: 2404 g_assert_not_reached(); 2405 } 2406} 2407 2408static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 2409 TCGReg base, intptr_t ofs) 2410{ 2411 return false; 2412} 2413 2414static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 2415{ 2416 if (ret == arg) { 2417 return true; 2418 } 2419 switch (type) { 2420 case TCG_TYPE_I32: 2421 if (ret < TCG_REG_Q0 && arg < TCG_REG_Q0) { 2422 tcg_out_mov_reg(s, COND_AL, ret, arg); 2423 return true; 2424 } 2425 return false; 2426 2427 case TCG_TYPE_V64: 2428 case TCG_TYPE_V128: 2429 /* "VMOV D,N" is an alias for "VORR D,N,N". */ 2430 tcg_out_vreg3(s, INSN_VORR, type - TCG_TYPE_V64, 0, ret, arg, arg); 2431 return true; 2432 2433 default: 2434 g_assert_not_reached(); 2435 } 2436} 2437 2438static void tcg_out_movi(TCGContext *s, TCGType type, 2439 TCGReg ret, tcg_target_long arg) 2440{ 2441 tcg_debug_assert(type == TCG_TYPE_I32); 2442 tcg_debug_assert(ret < TCG_REG_Q0); 2443 tcg_out_movi32(s, COND_AL, ret, arg); 2444} 2445 2446static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 2447{ 2448 return false; 2449} 2450 2451static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 2452 tcg_target_long imm) 2453{ 2454 int enc, opc = ARITH_ADD; 2455 2456 /* All of the easiest immediates to encode are positive. */ 2457 if (imm < 0) { 2458 imm = -imm; 2459 opc = ARITH_SUB; 2460 } 2461 enc = encode_imm(imm); 2462 if (enc >= 0) { 2463 tcg_out_dat_imm(s, COND_AL, opc, rd, rs, enc); 2464 } else { 2465 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, imm); 2466 tcg_out_dat_reg(s, COND_AL, opc, rd, rs, 2467 TCG_REG_TMP, SHIFT_IMM_LSL(0)); 2468 } 2469} 2470 2471/* Type is always V128, with I64 elements. */ 2472static void tcg_out_dup2_vec(TCGContext *s, TCGReg rd, TCGReg rl, TCGReg rh) 2473{ 2474 /* Move high element into place first. */ 2475 /* VMOV Dd+1, Ds */ 2476 tcg_out_vreg3(s, INSN_VORR | (1 << 12), 0, 0, rd, rh, rh); 2477 /* Move low element into place; tcg_out_mov will check for nop. */ 2478 tcg_out_mov(s, TCG_TYPE_V64, rd, rl); 2479} 2480 2481static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 2482 TCGReg rd, TCGReg rs) 2483{ 2484 int q = type - TCG_TYPE_V64; 2485 2486 if (vece == MO_64) { 2487 if (type == TCG_TYPE_V128) { 2488 tcg_out_dup2_vec(s, rd, rs, rs); 2489 } else { 2490 tcg_out_mov(s, TCG_TYPE_V64, rd, rs); 2491 } 2492 } else if (rs < TCG_REG_Q0) { 2493 int b = (vece == MO_8); 2494 int e = (vece == MO_16); 2495 tcg_out32(s, INSN_VDUP_G | (b << 22) | (q << 21) | (e << 5) | 2496 encode_vn(rd) | (rs << 12)); 2497 } else { 2498 int imm4 = 1 << vece; 2499 tcg_out32(s, INSN_VDUP_S | (imm4 << 16) | (q << 6) | 2500 encode_vd(rd) | encode_vm(rs)); 2501 } 2502 return true; 2503} 2504 2505static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 2506 TCGReg rd, TCGReg base, intptr_t offset) 2507{ 2508 if (vece == MO_64) { 2509 tcg_out_ld(s, TCG_TYPE_V64, rd, base, offset); 2510 if (type == TCG_TYPE_V128) { 2511 tcg_out_dup2_vec(s, rd, rd, rd); 2512 } 2513 } else { 2514 int q = type - TCG_TYPE_V64; 2515 tcg_out_vldst(s, INSN_VLD1R | (vece << 6) | (q << 5), 2516 rd, base, offset); 2517 } 2518 return true; 2519} 2520 2521static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 2522 TCGReg rd, int64_t v64) 2523{ 2524 int q = type - TCG_TYPE_V64; 2525 int cmode, imm8, i; 2526 2527 /* Test all bytes equal first. */ 2528 if (vece == MO_8) { 2529 tcg_out_vmovi(s, rd, q, 0, 0xe, v64); 2530 return; 2531 } 2532 2533 /* 2534 * Test all bytes 0x00 or 0xff second. This can match cases that 2535 * might otherwise take 2 or 3 insns for MO_16 or MO_32 below. 2536 */ 2537 for (i = imm8 = 0; i < 8; i++) { 2538 uint8_t byte = v64 >> (i * 8); 2539 if (byte == 0xff) { 2540 imm8 |= 1 << i; 2541 } else if (byte != 0) { 2542 goto fail_bytes; 2543 } 2544 } 2545 tcg_out_vmovi(s, rd, q, 1, 0xe, imm8); 2546 return; 2547 fail_bytes: 2548 2549 /* 2550 * Tests for various replications. For each element width, if we 2551 * cannot find an expansion there's no point checking a larger 2552 * width because we already know by replication it cannot match. 2553 */ 2554 if (vece == MO_16) { 2555 uint16_t v16 = v64; 2556 2557 if (is_shimm16(v16, &cmode, &imm8)) { 2558 tcg_out_vmovi(s, rd, q, 0, cmode, imm8); 2559 return; 2560 } 2561 if (is_shimm16(~v16, &cmode, &imm8)) { 2562 tcg_out_vmovi(s, rd, q, 1, cmode, imm8); 2563 return; 2564 } 2565 2566 /* 2567 * Otherwise, all remaining constants can be loaded in two insns: 2568 * rd = v16 & 0xff, rd |= v16 & 0xff00. 2569 */ 2570 tcg_out_vmovi(s, rd, q, 0, 0x8, v16 & 0xff); 2571 tcg_out_vmovi(s, rd, q, 0, 0xb, v16 >> 8); /* VORRI */ 2572 return; 2573 } 2574 2575 if (vece == MO_32) { 2576 uint32_t v32 = v64; 2577 2578 if (is_shimm32(v32, &cmode, &imm8) || 2579 is_soimm32(v32, &cmode, &imm8)) { 2580 tcg_out_vmovi(s, rd, q, 0, cmode, imm8); 2581 return; 2582 } 2583 if (is_shimm32(~v32, &cmode, &imm8) || 2584 is_soimm32(~v32, &cmode, &imm8)) { 2585 tcg_out_vmovi(s, rd, q, 1, cmode, imm8); 2586 return; 2587 } 2588 2589 /* 2590 * Restrict the set of constants to those we can load with 2591 * two instructions. Others we load from the pool. 2592 */ 2593 i = is_shimm32_pair(v32, &cmode, &imm8); 2594 if (i) { 2595 tcg_out_vmovi(s, rd, q, 0, cmode, imm8); 2596 tcg_out_vmovi(s, rd, q, 0, i | 1, extract32(v32, i * 4, 8)); 2597 return; 2598 } 2599 i = is_shimm32_pair(~v32, &cmode, &imm8); 2600 if (i) { 2601 tcg_out_vmovi(s, rd, q, 1, cmode, imm8); 2602 tcg_out_vmovi(s, rd, q, 1, i | 1, extract32(~v32, i * 4, 8)); 2603 return; 2604 } 2605 } 2606 2607 /* 2608 * As a last resort, load from the constant pool. 2609 */ 2610 if (!q || vece == MO_64) { 2611 new_pool_l2(s, R_ARM_PC11, s->code_ptr, 0, v64, v64 >> 32); 2612 /* VLDR Dd, [pc + offset] */ 2613 tcg_out32(s, INSN_VLDR_D | encode_vd(rd) | (0xf << 16)); 2614 if (q) { 2615 tcg_out_dup2_vec(s, rd, rd, rd); 2616 } 2617 } else { 2618 new_pool_label(s, (uint32_t)v64, R_ARM_PC8, s->code_ptr, 0); 2619 /* add tmp, pc, offset */ 2620 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_TMP, TCG_REG_PC, 0); 2621 tcg_out_dupm_vec(s, type, MO_32, rd, TCG_REG_TMP, 0); 2622 } 2623} 2624 2625static const ARMInsn vec_cmp_insn[16] = { 2626 [TCG_COND_EQ] = INSN_VCEQ, 2627 [TCG_COND_GT] = INSN_VCGT, 2628 [TCG_COND_GE] = INSN_VCGE, 2629 [TCG_COND_GTU] = INSN_VCGT_U, 2630 [TCG_COND_GEU] = INSN_VCGE_U, 2631}; 2632 2633static const ARMInsn vec_cmp0_insn[16] = { 2634 [TCG_COND_EQ] = INSN_VCEQ0, 2635 [TCG_COND_GT] = INSN_VCGT0, 2636 [TCG_COND_GE] = INSN_VCGE0, 2637 [TCG_COND_LT] = INSN_VCLT0, 2638 [TCG_COND_LE] = INSN_VCLE0, 2639}; 2640 2641static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 2642 unsigned vecl, unsigned vece, 2643 const TCGArg args[TCG_MAX_OP_ARGS], 2644 const int const_args[TCG_MAX_OP_ARGS]) 2645{ 2646 TCGType type = vecl + TCG_TYPE_V64; 2647 unsigned q = vecl; 2648 TCGArg a0, a1, a2, a3; 2649 int cmode, imm8; 2650 2651 a0 = args[0]; 2652 a1 = args[1]; 2653 a2 = args[2]; 2654 2655 switch (opc) { 2656 case INDEX_op_ld_vec: 2657 tcg_out_ld(s, type, a0, a1, a2); 2658 return; 2659 case INDEX_op_st_vec: 2660 tcg_out_st(s, type, a0, a1, a2); 2661 return; 2662 case INDEX_op_dupm_vec: 2663 tcg_out_dupm_vec(s, type, vece, a0, a1, a2); 2664 return; 2665 case INDEX_op_dup2_vec: 2666 tcg_out_dup2_vec(s, a0, a1, a2); 2667 return; 2668 case INDEX_op_abs_vec: 2669 tcg_out_vreg2(s, INSN_VABS, q, vece, a0, a1); 2670 return; 2671 case INDEX_op_neg_vec: 2672 tcg_out_vreg2(s, INSN_VNEG, q, vece, a0, a1); 2673 return; 2674 case INDEX_op_not_vec: 2675 tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a1); 2676 return; 2677 case INDEX_op_add_vec: 2678 tcg_out_vreg3(s, INSN_VADD, q, vece, a0, a1, a2); 2679 return; 2680 case INDEX_op_mul_vec: 2681 tcg_out_vreg3(s, INSN_VMUL, q, vece, a0, a1, a2); 2682 return; 2683 case INDEX_op_smax_vec: 2684 tcg_out_vreg3(s, INSN_VMAX, q, vece, a0, a1, a2); 2685 return; 2686 case INDEX_op_smin_vec: 2687 tcg_out_vreg3(s, INSN_VMIN, q, vece, a0, a1, a2); 2688 return; 2689 case INDEX_op_sub_vec: 2690 tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2); 2691 return; 2692 case INDEX_op_ssadd_vec: 2693 tcg_out_vreg3(s, INSN_VQADD, q, vece, a0, a1, a2); 2694 return; 2695 case INDEX_op_sssub_vec: 2696 tcg_out_vreg3(s, INSN_VQSUB, q, vece, a0, a1, a2); 2697 return; 2698 case INDEX_op_umax_vec: 2699 tcg_out_vreg3(s, INSN_VMAX_U, q, vece, a0, a1, a2); 2700 return; 2701 case INDEX_op_umin_vec: 2702 tcg_out_vreg3(s, INSN_VMIN_U, q, vece, a0, a1, a2); 2703 return; 2704 case INDEX_op_usadd_vec: 2705 tcg_out_vreg3(s, INSN_VQADD_U, q, vece, a0, a1, a2); 2706 return; 2707 case INDEX_op_ussub_vec: 2708 tcg_out_vreg3(s, INSN_VQSUB_U, q, vece, a0, a1, a2); 2709 return; 2710 case INDEX_op_xor_vec: 2711 tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2); 2712 return; 2713 case INDEX_op_arm_sshl_vec: 2714 /* 2715 * Note that Vm is the data and Vn is the shift count, 2716 * therefore the arguments appear reversed. 2717 */ 2718 tcg_out_vreg3(s, INSN_VSHL_S, q, vece, a0, a2, a1); 2719 return; 2720 case INDEX_op_arm_ushl_vec: 2721 /* See above. */ 2722 tcg_out_vreg3(s, INSN_VSHL_U, q, vece, a0, a2, a1); 2723 return; 2724 case INDEX_op_shli_vec: 2725 tcg_out_vshifti(s, INSN_VSHLI, q, a0, a1, a2 + (8 << vece)); 2726 return; 2727 case INDEX_op_shri_vec: 2728 tcg_out_vshifti(s, INSN_VSHRI, q, a0, a1, (16 << vece) - a2); 2729 return; 2730 case INDEX_op_sari_vec: 2731 tcg_out_vshifti(s, INSN_VSARI, q, a0, a1, (16 << vece) - a2); 2732 return; 2733 case INDEX_op_arm_sli_vec: 2734 tcg_out_vshifti(s, INSN_VSLI, q, a0, a2, args[3] + (8 << vece)); 2735 return; 2736 2737 case INDEX_op_andc_vec: 2738 if (!const_args[2]) { 2739 tcg_out_vreg3(s, INSN_VBIC, q, 0, a0, a1, a2); 2740 return; 2741 } 2742 a2 = ~a2; 2743 /* fall through */ 2744 case INDEX_op_and_vec: 2745 if (const_args[2]) { 2746 is_shimm1632(~a2, &cmode, &imm8); 2747 if (a0 == a1) { 2748 tcg_out_vmovi(s, a0, q, 1, cmode | 1, imm8); /* VBICI */ 2749 return; 2750 } 2751 tcg_out_vmovi(s, a0, q, 1, cmode, imm8); /* VMVNI */ 2752 a2 = a0; 2753 } 2754 tcg_out_vreg3(s, INSN_VAND, q, 0, a0, a1, a2); 2755 return; 2756 2757 case INDEX_op_orc_vec: 2758 if (!const_args[2]) { 2759 tcg_out_vreg3(s, INSN_VORN, q, 0, a0, a1, a2); 2760 return; 2761 } 2762 a2 = ~a2; 2763 /* fall through */ 2764 case INDEX_op_or_vec: 2765 if (const_args[2]) { 2766 is_shimm1632(a2, &cmode, &imm8); 2767 if (a0 == a1) { 2768 tcg_out_vmovi(s, a0, q, 0, cmode | 1, imm8); /* VORRI */ 2769 return; 2770 } 2771 tcg_out_vmovi(s, a0, q, 0, cmode, imm8); /* VMOVI */ 2772 a2 = a0; 2773 } 2774 tcg_out_vreg3(s, INSN_VORR, q, 0, a0, a1, a2); 2775 return; 2776 2777 case INDEX_op_cmp_vec: 2778 { 2779 TCGCond cond = args[3]; 2780 2781 if (cond == TCG_COND_NE) { 2782 if (const_args[2]) { 2783 tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a1); 2784 } else { 2785 tcg_out_vreg3(s, INSN_VCEQ, q, vece, a0, a1, a2); 2786 tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0); 2787 } 2788 } else { 2789 ARMInsn insn; 2790 2791 if (const_args[2]) { 2792 insn = vec_cmp0_insn[cond]; 2793 if (insn) { 2794 tcg_out_vreg2(s, insn, q, vece, a0, a1); 2795 return; 2796 } 2797 tcg_out_dupi_vec(s, type, MO_8, TCG_VEC_TMP, 0); 2798 a2 = TCG_VEC_TMP; 2799 } 2800 insn = vec_cmp_insn[cond]; 2801 if (insn == 0) { 2802 TCGArg t; 2803 t = a1, a1 = a2, a2 = t; 2804 cond = tcg_swap_cond(cond); 2805 insn = vec_cmp_insn[cond]; 2806 tcg_debug_assert(insn != 0); 2807 } 2808 tcg_out_vreg3(s, insn, q, vece, a0, a1, a2); 2809 } 2810 } 2811 return; 2812 2813 case INDEX_op_bitsel_vec: 2814 a3 = args[3]; 2815 if (a0 == a3) { 2816 tcg_out_vreg3(s, INSN_VBIT, q, 0, a0, a2, a1); 2817 } else if (a0 == a2) { 2818 tcg_out_vreg3(s, INSN_VBIF, q, 0, a0, a3, a1); 2819 } else { 2820 tcg_out_mov(s, type, a0, a1); 2821 tcg_out_vreg3(s, INSN_VBSL, q, 0, a0, a2, a3); 2822 } 2823 return; 2824 2825 case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ 2826 case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ 2827 default: 2828 g_assert_not_reached(); 2829 } 2830} 2831 2832int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 2833{ 2834 switch (opc) { 2835 case INDEX_op_add_vec: 2836 case INDEX_op_sub_vec: 2837 case INDEX_op_and_vec: 2838 case INDEX_op_andc_vec: 2839 case INDEX_op_or_vec: 2840 case INDEX_op_orc_vec: 2841 case INDEX_op_xor_vec: 2842 case INDEX_op_not_vec: 2843 case INDEX_op_shli_vec: 2844 case INDEX_op_shri_vec: 2845 case INDEX_op_sari_vec: 2846 case INDEX_op_ssadd_vec: 2847 case INDEX_op_sssub_vec: 2848 case INDEX_op_usadd_vec: 2849 case INDEX_op_ussub_vec: 2850 case INDEX_op_bitsel_vec: 2851 return 1; 2852 case INDEX_op_abs_vec: 2853 case INDEX_op_cmp_vec: 2854 case INDEX_op_mul_vec: 2855 case INDEX_op_neg_vec: 2856 case INDEX_op_smax_vec: 2857 case INDEX_op_smin_vec: 2858 case INDEX_op_umax_vec: 2859 case INDEX_op_umin_vec: 2860 return vece < MO_64; 2861 case INDEX_op_shlv_vec: 2862 case INDEX_op_shrv_vec: 2863 case INDEX_op_sarv_vec: 2864 case INDEX_op_rotli_vec: 2865 case INDEX_op_rotlv_vec: 2866 case INDEX_op_rotrv_vec: 2867 return -1; 2868 default: 2869 return 0; 2870 } 2871} 2872 2873void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 2874 TCGArg a0, ...) 2875{ 2876 va_list va; 2877 TCGv_vec v0, v1, v2, t1, t2, c1; 2878 TCGArg a2; 2879 2880 va_start(va, a0); 2881 v0 = temp_tcgv_vec(arg_temp(a0)); 2882 v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 2883 a2 = va_arg(va, TCGArg); 2884 va_end(va); 2885 2886 switch (opc) { 2887 case INDEX_op_shlv_vec: 2888 /* 2889 * Merely propagate shlv_vec to arm_ushl_vec. 2890 * In this way we don't set TCG_TARGET_HAS_shv_vec 2891 * because everything is done via expansion. 2892 */ 2893 v2 = temp_tcgv_vec(arg_temp(a2)); 2894 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0), 2895 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 2896 break; 2897 2898 case INDEX_op_shrv_vec: 2899 case INDEX_op_sarv_vec: 2900 /* Right shifts are negative left shifts for NEON. */ 2901 v2 = temp_tcgv_vec(arg_temp(a2)); 2902 t1 = tcg_temp_new_vec(type); 2903 tcg_gen_neg_vec(vece, t1, v2); 2904 if (opc == INDEX_op_shrv_vec) { 2905 opc = INDEX_op_arm_ushl_vec; 2906 } else { 2907 opc = INDEX_op_arm_sshl_vec; 2908 } 2909 vec_gen_3(opc, type, vece, tcgv_vec_arg(v0), 2910 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 2911 tcg_temp_free_vec(t1); 2912 break; 2913 2914 case INDEX_op_rotli_vec: 2915 t1 = tcg_temp_new_vec(type); 2916 tcg_gen_shri_vec(vece, t1, v1, -a2 & ((8 << vece) - 1)); 2917 vec_gen_4(INDEX_op_arm_sli_vec, type, vece, 2918 tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(v1), a2); 2919 tcg_temp_free_vec(t1); 2920 break; 2921 2922 case INDEX_op_rotlv_vec: 2923 v2 = temp_tcgv_vec(arg_temp(a2)); 2924 t1 = tcg_temp_new_vec(type); 2925 c1 = tcg_constant_vec(type, vece, 8 << vece); 2926 tcg_gen_sub_vec(vece, t1, v2, c1); 2927 /* Right shifts are negative left shifts for NEON. */ 2928 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1), 2929 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 2930 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0), 2931 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 2932 tcg_gen_or_vec(vece, v0, v0, t1); 2933 tcg_temp_free_vec(t1); 2934 break; 2935 2936 case INDEX_op_rotrv_vec: 2937 v2 = temp_tcgv_vec(arg_temp(a2)); 2938 t1 = tcg_temp_new_vec(type); 2939 t2 = tcg_temp_new_vec(type); 2940 c1 = tcg_constant_vec(type, vece, 8 << vece); 2941 tcg_gen_neg_vec(vece, t1, v2); 2942 tcg_gen_sub_vec(vece, t2, c1, v2); 2943 /* Right shifts are negative left shifts for NEON. */ 2944 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1), 2945 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 2946 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t2), 2947 tcgv_vec_arg(v1), tcgv_vec_arg(t2)); 2948 tcg_gen_or_vec(vece, v0, t1, t2); 2949 tcg_temp_free_vec(t1); 2950 tcg_temp_free_vec(t2); 2951 break; 2952 2953 default: 2954 g_assert_not_reached(); 2955 } 2956} 2957 2958static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 2959{ 2960 int i; 2961 for (i = 0; i < count; ++i) { 2962 p[i] = INSN_NOP; 2963 } 2964} 2965 2966/* Compute frame size via macros, to share between tcg_target_qemu_prologue 2967 and tcg_register_jit. */ 2968 2969#define PUSH_SIZE ((11 - 4 + 1 + 1) * sizeof(tcg_target_long)) 2970 2971#define FRAME_SIZE \ 2972 ((PUSH_SIZE \ 2973 + TCG_STATIC_CALL_ARGS_SIZE \ 2974 + CPU_TEMP_BUF_NLONGS * sizeof(long) \ 2975 + TCG_TARGET_STACK_ALIGN - 1) \ 2976 & -TCG_TARGET_STACK_ALIGN) 2977 2978#define STACK_ADDEND (FRAME_SIZE - PUSH_SIZE) 2979 2980static void tcg_target_qemu_prologue(TCGContext *s) 2981{ 2982 /* Calling convention requires us to save r4-r11 and lr. */ 2983 /* stmdb sp!, { r4 - r11, lr } */ 2984 tcg_out_ldstm(s, COND_AL, INSN_STMDB, TCG_REG_CALL_STACK, 2985 (1 << TCG_REG_R4) | (1 << TCG_REG_R5) | (1 << TCG_REG_R6) | 2986 (1 << TCG_REG_R7) | (1 << TCG_REG_R8) | (1 << TCG_REG_R9) | 2987 (1 << TCG_REG_R10) | (1 << TCG_REG_R11) | (1 << TCG_REG_R14)); 2988 2989 /* Reserve callee argument and tcg temp space. */ 2990 tcg_out_dat_rI(s, COND_AL, ARITH_SUB, TCG_REG_CALL_STACK, 2991 TCG_REG_CALL_STACK, STACK_ADDEND, 1); 2992 tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE, 2993 CPU_TEMP_BUF_NLONGS * sizeof(long)); 2994 2995 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 2996 2997#ifndef CONFIG_SOFTMMU 2998 if (guest_base) { 2999 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_GUEST_BASE, guest_base); 3000 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GUEST_BASE); 3001 } 3002#endif 3003 3004 tcg_out_b_reg(s, COND_AL, tcg_target_call_iarg_regs[1]); 3005 3006 /* 3007 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 3008 * and fall through to the rest of the epilogue. 3009 */ 3010 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 3011 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, 0); 3012 tcg_out_epilogue(s); 3013} 3014 3015static void tcg_out_epilogue(TCGContext *s) 3016{ 3017 /* Release local stack frame. */ 3018 tcg_out_dat_rI(s, COND_AL, ARITH_ADD, TCG_REG_CALL_STACK, 3019 TCG_REG_CALL_STACK, STACK_ADDEND, 1); 3020 3021 /* ldmia sp!, { r4 - r11, pc } */ 3022 tcg_out_ldstm(s, COND_AL, INSN_LDMIA, TCG_REG_CALL_STACK, 3023 (1 << TCG_REG_R4) | (1 << TCG_REG_R5) | (1 << TCG_REG_R6) | 3024 (1 << TCG_REG_R7) | (1 << TCG_REG_R8) | (1 << TCG_REG_R9) | 3025 (1 << TCG_REG_R10) | (1 << TCG_REG_R11) | (1 << TCG_REG_PC)); 3026} 3027 3028typedef struct { 3029 DebugFrameHeader h; 3030 uint8_t fde_def_cfa[4]; 3031 uint8_t fde_reg_ofs[18]; 3032} DebugFrame; 3033 3034#define ELF_HOST_MACHINE EM_ARM 3035 3036/* We're expecting a 2 byte uleb128 encoded value. */ 3037QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); 3038 3039static const DebugFrame debug_frame = { 3040 .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ 3041 .h.cie.id = -1, 3042 .h.cie.version = 1, 3043 .h.cie.code_align = 1, 3044 .h.cie.data_align = 0x7c, /* sleb128 -4 */ 3045 .h.cie.return_column = 14, 3046 3047 /* Total FDE size does not include the "len" member. */ 3048 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 3049 3050 .fde_def_cfa = { 3051 12, 13, /* DW_CFA_def_cfa sp, ... */ 3052 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 3053 (FRAME_SIZE >> 7) 3054 }, 3055 .fde_reg_ofs = { 3056 /* The following must match the stmdb in the prologue. */ 3057 0x8e, 1, /* DW_CFA_offset, lr, -4 */ 3058 0x8b, 2, /* DW_CFA_offset, r11, -8 */ 3059 0x8a, 3, /* DW_CFA_offset, r10, -12 */ 3060 0x89, 4, /* DW_CFA_offset, r9, -16 */ 3061 0x88, 5, /* DW_CFA_offset, r8, -20 */ 3062 0x87, 6, /* DW_CFA_offset, r7, -24 */ 3063 0x86, 7, /* DW_CFA_offset, r6, -28 */ 3064 0x85, 8, /* DW_CFA_offset, r5, -32 */ 3065 0x84, 9, /* DW_CFA_offset, r4, -36 */ 3066 } 3067}; 3068 3069void tcg_register_jit(const void *buf, size_t buf_size) 3070{ 3071 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 3072} 3073