1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Andrzej Zaborowski 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25#include "elf.h" 26 27int arm_arch = __ARM_ARCH; 28 29#ifndef use_idiv_instructions 30bool use_idiv_instructions; 31#endif 32#ifndef use_neon_instructions 33bool use_neon_instructions; 34#endif 35 36/* Used for function call generation. */ 37#define TCG_TARGET_STACK_ALIGN 8 38#define TCG_TARGET_CALL_STACK_OFFSET 0 39#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL 40#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN 41#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN 42#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF 43 44#ifdef CONFIG_DEBUG_TCG 45static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 46 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", 47 "%r8", "%r9", "%r10", "%r11", "%r12", "%sp", "%r14", "%pc", 48 "%q0", "%q1", "%q2", "%q3", "%q4", "%q5", "%q6", "%q7", 49 "%q8", "%q9", "%q10", "%q11", "%q12", "%q13", "%q14", "%q15", 50}; 51#endif 52 53static const int tcg_target_reg_alloc_order[] = { 54 TCG_REG_R4, 55 TCG_REG_R5, 56 TCG_REG_R6, 57 TCG_REG_R7, 58 TCG_REG_R8, 59 TCG_REG_R9, 60 TCG_REG_R10, 61 TCG_REG_R11, 62 TCG_REG_R13, 63 TCG_REG_R0, 64 TCG_REG_R1, 65 TCG_REG_R2, 66 TCG_REG_R3, 67 TCG_REG_R12, 68 TCG_REG_R14, 69 70 TCG_REG_Q0, 71 TCG_REG_Q1, 72 TCG_REG_Q2, 73 TCG_REG_Q3, 74 /* Q4 - Q7 are call-saved, and skipped. */ 75 TCG_REG_Q8, 76 TCG_REG_Q9, 77 TCG_REG_Q10, 78 TCG_REG_Q11, 79 TCG_REG_Q12, 80 TCG_REG_Q13, 81 TCG_REG_Q14, 82 TCG_REG_Q15, 83}; 84 85static const int tcg_target_call_iarg_regs[4] = { 86 TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3 87}; 88 89static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 90{ 91 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 92 tcg_debug_assert(slot >= 0 && slot <= 3); 93 return TCG_REG_R0 + slot; 94} 95 96#define TCG_REG_TMP TCG_REG_R12 97#define TCG_VEC_TMP TCG_REG_Q15 98#define TCG_REG_GUEST_BASE TCG_REG_R11 99 100typedef enum { 101 COND_EQ = 0x0, 102 COND_NE = 0x1, 103 COND_CS = 0x2, /* Unsigned greater or equal */ 104 COND_CC = 0x3, /* Unsigned less than */ 105 COND_MI = 0x4, /* Negative */ 106 COND_PL = 0x5, /* Zero or greater */ 107 COND_VS = 0x6, /* Overflow */ 108 COND_VC = 0x7, /* No overflow */ 109 COND_HI = 0x8, /* Unsigned greater than */ 110 COND_LS = 0x9, /* Unsigned less or equal */ 111 COND_GE = 0xa, 112 COND_LT = 0xb, 113 COND_GT = 0xc, 114 COND_LE = 0xd, 115 COND_AL = 0xe, 116} ARMCond; 117 118#define TO_CPSR (1 << 20) 119 120#define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00) 121#define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20) 122#define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40) 123#define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60) 124#define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10) 125#define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30) 126#define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50) 127#define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70) 128 129typedef enum { 130 ARITH_AND = 0x0 << 21, 131 ARITH_EOR = 0x1 << 21, 132 ARITH_SUB = 0x2 << 21, 133 ARITH_RSB = 0x3 << 21, 134 ARITH_ADD = 0x4 << 21, 135 ARITH_ADC = 0x5 << 21, 136 ARITH_SBC = 0x6 << 21, 137 ARITH_RSC = 0x7 << 21, 138 ARITH_TST = 0x8 << 21 | TO_CPSR, 139 ARITH_CMP = 0xa << 21 | TO_CPSR, 140 ARITH_CMN = 0xb << 21 | TO_CPSR, 141 ARITH_ORR = 0xc << 21, 142 ARITH_MOV = 0xd << 21, 143 ARITH_BIC = 0xe << 21, 144 ARITH_MVN = 0xf << 21, 145 146 INSN_B = 0x0a000000, 147 148 INSN_CLZ = 0x016f0f10, 149 INSN_RBIT = 0x06ff0f30, 150 151 INSN_LDMIA = 0x08b00000, 152 INSN_STMDB = 0x09200000, 153 154 INSN_LDR_IMM = 0x04100000, 155 INSN_LDR_REG = 0x06100000, 156 INSN_STR_IMM = 0x04000000, 157 INSN_STR_REG = 0x06000000, 158 159 INSN_LDRH_IMM = 0x005000b0, 160 INSN_LDRH_REG = 0x001000b0, 161 INSN_LDRSH_IMM = 0x005000f0, 162 INSN_LDRSH_REG = 0x001000f0, 163 INSN_STRH_IMM = 0x004000b0, 164 INSN_STRH_REG = 0x000000b0, 165 166 INSN_LDRB_IMM = 0x04500000, 167 INSN_LDRB_REG = 0x06500000, 168 INSN_LDRSB_IMM = 0x005000d0, 169 INSN_LDRSB_REG = 0x001000d0, 170 INSN_STRB_IMM = 0x04400000, 171 INSN_STRB_REG = 0x06400000, 172 173 INSN_LDRD_IMM = 0x004000d0, 174 INSN_LDRD_REG = 0x000000d0, 175 INSN_STRD_IMM = 0x004000f0, 176 INSN_STRD_REG = 0x000000f0, 177 178 INSN_DMB_ISH = 0xf57ff05b, 179 INSN_DMB_MCR = 0xee070fba, 180 181 /* Architected nop introduced in v6k. */ 182 /* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this 183 also Just So Happened to do nothing on pre-v6k so that we 184 don't need to conditionalize it? */ 185 INSN_NOP_v6k = 0xe320f000, 186 /* Otherwise the assembler uses mov r0,r0 */ 187 INSN_NOP_v4 = (COND_AL << 28) | ARITH_MOV, 188 189 INSN_VADD = 0xf2000800, 190 INSN_VAND = 0xf2000110, 191 INSN_VBIC = 0xf2100110, 192 INSN_VEOR = 0xf3000110, 193 INSN_VORN = 0xf2300110, 194 INSN_VORR = 0xf2200110, 195 INSN_VSUB = 0xf3000800, 196 INSN_VMUL = 0xf2000910, 197 INSN_VQADD = 0xf2000010, 198 INSN_VQADD_U = 0xf3000010, 199 INSN_VQSUB = 0xf2000210, 200 INSN_VQSUB_U = 0xf3000210, 201 INSN_VMAX = 0xf2000600, 202 INSN_VMAX_U = 0xf3000600, 203 INSN_VMIN = 0xf2000610, 204 INSN_VMIN_U = 0xf3000610, 205 206 INSN_VABS = 0xf3b10300, 207 INSN_VMVN = 0xf3b00580, 208 INSN_VNEG = 0xf3b10380, 209 210 INSN_VCEQ0 = 0xf3b10100, 211 INSN_VCGT0 = 0xf3b10000, 212 INSN_VCGE0 = 0xf3b10080, 213 INSN_VCLE0 = 0xf3b10180, 214 INSN_VCLT0 = 0xf3b10200, 215 216 INSN_VCEQ = 0xf3000810, 217 INSN_VCGE = 0xf2000310, 218 INSN_VCGT = 0xf2000300, 219 INSN_VCGE_U = 0xf3000310, 220 INSN_VCGT_U = 0xf3000300, 221 222 INSN_VSHLI = 0xf2800510, /* VSHL (immediate) */ 223 INSN_VSARI = 0xf2800010, /* VSHR.S */ 224 INSN_VSHRI = 0xf3800010, /* VSHR.U */ 225 INSN_VSLI = 0xf3800510, 226 INSN_VSHL_S = 0xf2000400, /* VSHL.S (register) */ 227 INSN_VSHL_U = 0xf3000400, /* VSHL.U (register) */ 228 229 INSN_VBSL = 0xf3100110, 230 INSN_VBIT = 0xf3200110, 231 INSN_VBIF = 0xf3300110, 232 233 INSN_VTST = 0xf2000810, 234 235 INSN_VDUP_G = 0xee800b10, /* VDUP (ARM core register) */ 236 INSN_VDUP_S = 0xf3b00c00, /* VDUP (scalar) */ 237 INSN_VLDR_D = 0xed100b00, /* VLDR.64 */ 238 INSN_VLD1 = 0xf4200000, /* VLD1 (multiple single elements) */ 239 INSN_VLD1R = 0xf4a00c00, /* VLD1 (single element to all lanes) */ 240 INSN_VST1 = 0xf4000000, /* VST1 (multiple single elements) */ 241 INSN_VMOVI = 0xf2800010, /* VMOV (immediate) */ 242} ARMInsn; 243 244#define INSN_NOP (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4) 245 246static const uint8_t tcg_cond_to_arm_cond[] = { 247 [TCG_COND_EQ] = COND_EQ, 248 [TCG_COND_NE] = COND_NE, 249 [TCG_COND_LT] = COND_LT, 250 [TCG_COND_GE] = COND_GE, 251 [TCG_COND_LE] = COND_LE, 252 [TCG_COND_GT] = COND_GT, 253 /* unsigned */ 254 [TCG_COND_LTU] = COND_CC, 255 [TCG_COND_GEU] = COND_CS, 256 [TCG_COND_LEU] = COND_LS, 257 [TCG_COND_GTU] = COND_HI, 258}; 259 260static int encode_imm(uint32_t imm); 261 262/* TCG private relocation type: add with pc+imm8 */ 263#define R_ARM_PC8 11 264 265/* TCG private relocation type: vldr with imm8 << 2 */ 266#define R_ARM_PC11 12 267 268static bool reloc_pc24(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 269{ 270 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 271 ptrdiff_t offset = (tcg_ptr_byte_diff(target, src_rx) - 8) >> 2; 272 273 if (offset == sextract32(offset, 0, 24)) { 274 *src_rw = deposit32(*src_rw, 0, 24, offset); 275 return true; 276 } 277 return false; 278} 279 280static bool reloc_pc13(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 281{ 282 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 283 ptrdiff_t offset = tcg_ptr_byte_diff(target, src_rx) - 8; 284 285 if (offset >= -0xfff && offset <= 0xfff) { 286 tcg_insn_unit insn = *src_rw; 287 bool u = (offset >= 0); 288 if (!u) { 289 offset = -offset; 290 } 291 insn = deposit32(insn, 23, 1, u); 292 insn = deposit32(insn, 0, 12, offset); 293 *src_rw = insn; 294 return true; 295 } 296 return false; 297} 298 299static bool reloc_pc11(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 300{ 301 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 302 ptrdiff_t offset = (tcg_ptr_byte_diff(target, src_rx) - 8) / 4; 303 304 if (offset >= -0xff && offset <= 0xff) { 305 tcg_insn_unit insn = *src_rw; 306 bool u = (offset >= 0); 307 if (!u) { 308 offset = -offset; 309 } 310 insn = deposit32(insn, 23, 1, u); 311 insn = deposit32(insn, 0, 8, offset); 312 *src_rw = insn; 313 return true; 314 } 315 return false; 316} 317 318static bool reloc_pc8(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 319{ 320 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 321 ptrdiff_t offset = tcg_ptr_byte_diff(target, src_rx) - 8; 322 int imm12 = encode_imm(offset); 323 324 if (imm12 >= 0) { 325 *src_rw = deposit32(*src_rw, 0, 12, imm12); 326 return true; 327 } 328 return false; 329} 330 331static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 332 intptr_t value, intptr_t addend) 333{ 334 tcg_debug_assert(addend == 0); 335 switch (type) { 336 case R_ARM_PC24: 337 return reloc_pc24(code_ptr, (const tcg_insn_unit *)value); 338 case R_ARM_PC13: 339 return reloc_pc13(code_ptr, (const tcg_insn_unit *)value); 340 case R_ARM_PC11: 341 return reloc_pc11(code_ptr, (const tcg_insn_unit *)value); 342 case R_ARM_PC8: 343 return reloc_pc8(code_ptr, (const tcg_insn_unit *)value); 344 default: 345 g_assert_not_reached(); 346 } 347} 348 349#define TCG_CT_CONST_ARM 0x100 350#define TCG_CT_CONST_INV 0x200 351#define TCG_CT_CONST_NEG 0x400 352#define TCG_CT_CONST_ZERO 0x800 353#define TCG_CT_CONST_ORRI 0x1000 354#define TCG_CT_CONST_ANDI 0x2000 355 356#define ALL_GENERAL_REGS 0xffffu 357#define ALL_VECTOR_REGS 0xffff0000u 358 359/* 360 * r0-r3 will be overwritten when reading the tlb entry (system-mode only); 361 * r14 will be overwritten by the BLNE branching to the slow path. 362 */ 363#define ALL_QLDST_REGS \ 364 (ALL_GENERAL_REGS & ~((tcg_use_softmmu ? 0xf : 0) | (1 << TCG_REG_R14))) 365 366/* 367 * ARM immediates for ALU instructions are made of an unsigned 8-bit 368 * right-rotated by an even amount between 0 and 30. 369 * 370 * Return < 0 if @imm cannot be encoded, else the entire imm12 field. 371 */ 372static int encode_imm(uint32_t imm) 373{ 374 uint32_t rot, imm8; 375 376 /* Simple case, no rotation required. */ 377 if ((imm & ~0xff) == 0) { 378 return imm; 379 } 380 381 /* Next, try a simple even shift. */ 382 rot = ctz32(imm) & ~1; 383 imm8 = imm >> rot; 384 rot = 32 - rot; 385 if ((imm8 & ~0xff) == 0) { 386 goto found; 387 } 388 389 /* 390 * Finally, try harder with rotations. 391 * The ctz test above will have taken care of rotates >= 8. 392 */ 393 for (rot = 2; rot < 8; rot += 2) { 394 imm8 = rol32(imm, rot); 395 if ((imm8 & ~0xff) == 0) { 396 goto found; 397 } 398 } 399 /* Fail: imm cannot be encoded. */ 400 return -1; 401 402 found: 403 /* Note that rot is even, and we discard bit 0 by shifting by 7. */ 404 return rot << 7 | imm8; 405} 406 407static int encode_imm_nofail(uint32_t imm) 408{ 409 int ret = encode_imm(imm); 410 tcg_debug_assert(ret >= 0); 411 return ret; 412} 413 414static bool check_fit_imm(uint32_t imm) 415{ 416 return encode_imm(imm) >= 0; 417} 418 419/* Return true if v16 is a valid 16-bit shifted immediate. */ 420static bool is_shimm16(uint16_t v16, int *cmode, int *imm8) 421{ 422 if (v16 == (v16 & 0xff)) { 423 *cmode = 0x8; 424 *imm8 = v16 & 0xff; 425 return true; 426 } else if (v16 == (v16 & 0xff00)) { 427 *cmode = 0xa; 428 *imm8 = v16 >> 8; 429 return true; 430 } 431 return false; 432} 433 434/* Return true if v32 is a valid 32-bit shifted immediate. */ 435static bool is_shimm32(uint32_t v32, int *cmode, int *imm8) 436{ 437 if (v32 == (v32 & 0xff)) { 438 *cmode = 0x0; 439 *imm8 = v32 & 0xff; 440 return true; 441 } else if (v32 == (v32 & 0xff00)) { 442 *cmode = 0x2; 443 *imm8 = (v32 >> 8) & 0xff; 444 return true; 445 } else if (v32 == (v32 & 0xff0000)) { 446 *cmode = 0x4; 447 *imm8 = (v32 >> 16) & 0xff; 448 return true; 449 } else if (v32 == (v32 & 0xff000000)) { 450 *cmode = 0x6; 451 *imm8 = v32 >> 24; 452 return true; 453 } 454 return false; 455} 456 457/* Return true if v32 is a valid 32-bit shifting ones immediate. */ 458static bool is_soimm32(uint32_t v32, int *cmode, int *imm8) 459{ 460 if ((v32 & 0xffff00ff) == 0xff) { 461 *cmode = 0xc; 462 *imm8 = (v32 >> 8) & 0xff; 463 return true; 464 } else if ((v32 & 0xff00ffff) == 0xffff) { 465 *cmode = 0xd; 466 *imm8 = (v32 >> 16) & 0xff; 467 return true; 468 } 469 return false; 470} 471 472/* 473 * Return non-zero if v32 can be formed by MOVI+ORR. 474 * Place the parameters for MOVI in (cmode, imm8). 475 * Return the cmode for ORR; the imm8 can be had via extraction from v32. 476 */ 477static int is_shimm32_pair(uint32_t v32, int *cmode, int *imm8) 478{ 479 int i; 480 481 for (i = 6; i > 0; i -= 2) { 482 /* Mask out one byte we can add with ORR. */ 483 uint32_t tmp = v32 & ~(0xffu << (i * 4)); 484 if (is_shimm32(tmp, cmode, imm8) || 485 is_soimm32(tmp, cmode, imm8)) { 486 break; 487 } 488 } 489 return i; 490} 491 492/* Return true if V is a valid 16-bit or 32-bit shifted immediate. */ 493static bool is_shimm1632(uint32_t v32, int *cmode, int *imm8) 494{ 495 if (v32 == deposit32(v32, 16, 16, v32)) { 496 return is_shimm16(v32, cmode, imm8); 497 } else { 498 return is_shimm32(v32, cmode, imm8); 499 } 500} 501 502/* Test if a constant matches the constraint. 503 * TODO: define constraints for: 504 * 505 * ldr/str offset: between -0xfff and 0xfff 506 * ldrh/strh offset: between -0xff and 0xff 507 * mov operand2: values represented with x << (2 * y), x < 0x100 508 * add, sub, eor...: ditto 509 */ 510static bool tcg_target_const_match(int64_t val, int ct, 511 TCGType type, TCGCond cond, int vece) 512{ 513 if (ct & TCG_CT_CONST) { 514 return 1; 515 } else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val)) { 516 return 1; 517 } else if ((ct & TCG_CT_CONST_INV) && check_fit_imm(~val)) { 518 return 1; 519 } else if ((ct & TCG_CT_CONST_NEG) && check_fit_imm(-val)) { 520 return 1; 521 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 522 return 1; 523 } 524 525 switch (ct & (TCG_CT_CONST_ORRI | TCG_CT_CONST_ANDI)) { 526 case 0: 527 break; 528 case TCG_CT_CONST_ANDI: 529 val = ~val; 530 /* fallthru */ 531 case TCG_CT_CONST_ORRI: 532 if (val == deposit64(val, 32, 32, val)) { 533 int cmode, imm8; 534 return is_shimm1632(val, &cmode, &imm8); 535 } 536 break; 537 default: 538 /* Both bits should not be set for the same insn. */ 539 g_assert_not_reached(); 540 } 541 542 return 0; 543} 544 545static void tcg_out_b_imm(TCGContext *s, ARMCond cond, int32_t offset) 546{ 547 tcg_out32(s, (cond << 28) | INSN_B | 548 (((offset - 8) >> 2) & 0x00ffffff)); 549} 550 551static void tcg_out_bl_imm(TCGContext *s, ARMCond cond, int32_t offset) 552{ 553 tcg_out32(s, (cond << 28) | 0x0b000000 | 554 (((offset - 8) >> 2) & 0x00ffffff)); 555} 556 557static void tcg_out_blx_reg(TCGContext *s, ARMCond cond, TCGReg rn) 558{ 559 tcg_out32(s, (cond << 28) | 0x012fff30 | rn); 560} 561 562static void tcg_out_blx_imm(TCGContext *s, int32_t offset) 563{ 564 tcg_out32(s, 0xfa000000 | ((offset & 2) << 23) | 565 (((offset - 8) >> 2) & 0x00ffffff)); 566} 567 568static void tcg_out_dat_reg(TCGContext *s, ARMCond cond, ARMInsn opc, 569 TCGReg rd, TCGReg rn, TCGReg rm, int shift) 570{ 571 tcg_out32(s, (cond << 28) | (0 << 25) | opc | 572 (rn << 16) | (rd << 12) | shift | rm); 573} 574 575static void tcg_out_mov_reg(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rm) 576{ 577 /* Simple reg-reg move, optimising out the 'do nothing' case */ 578 if (rd != rm) { 579 tcg_out_dat_reg(s, cond, ARITH_MOV, rd, 0, rm, SHIFT_IMM_LSL(0)); 580 } 581} 582 583static void tcg_out_bx_reg(TCGContext *s, ARMCond cond, TCGReg rn) 584{ 585 tcg_out32(s, (cond << 28) | 0x012fff10 | rn); 586} 587 588static void tcg_out_b_reg(TCGContext *s, ARMCond cond, TCGReg rn) 589{ 590 /* 591 * Unless the C portion of QEMU is compiled as thumb, we don't need 592 * true BX semantics; merely a branch to an address held in a register. 593 */ 594 tcg_out_bx_reg(s, cond, rn); 595} 596 597static void tcg_out_dat_imm(TCGContext *s, ARMCond cond, ARMInsn opc, 598 TCGReg rd, TCGReg rn, int im) 599{ 600 tcg_out32(s, (cond << 28) | (1 << 25) | opc | 601 (rn << 16) | (rd << 12) | im); 602} 603 604static void tcg_out_ldstm(TCGContext *s, ARMCond cond, ARMInsn opc, 605 TCGReg rn, uint16_t mask) 606{ 607 tcg_out32(s, (cond << 28) | opc | (rn << 16) | mask); 608} 609 610/* Note that this routine is used for both LDR and LDRH formats, so we do 611 not wish to include an immediate shift at this point. */ 612static void tcg_out_memop_r(TCGContext *s, ARMCond cond, ARMInsn opc, TCGReg rt, 613 TCGReg rn, TCGReg rm, bool u, bool p, bool w) 614{ 615 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) 616 | (w << 21) | (rn << 16) | (rt << 12) | rm); 617} 618 619static void tcg_out_memop_8(TCGContext *s, ARMCond cond, ARMInsn opc, TCGReg rt, 620 TCGReg rn, int imm8, bool p, bool w) 621{ 622 bool u = 1; 623 if (imm8 < 0) { 624 imm8 = -imm8; 625 u = 0; 626 } 627 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | 628 (rn << 16) | (rt << 12) | ((imm8 & 0xf0) << 4) | (imm8 & 0xf)); 629} 630 631static void tcg_out_memop_12(TCGContext *s, ARMCond cond, ARMInsn opc, 632 TCGReg rt, TCGReg rn, int imm12, bool p, bool w) 633{ 634 bool u = 1; 635 if (imm12 < 0) { 636 imm12 = -imm12; 637 u = 0; 638 } 639 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | 640 (rn << 16) | (rt << 12) | imm12); 641} 642 643static void tcg_out_ld32_12(TCGContext *s, ARMCond cond, TCGReg rt, 644 TCGReg rn, int imm12) 645{ 646 tcg_out_memop_12(s, cond, INSN_LDR_IMM, rt, rn, imm12, 1, 0); 647} 648 649static void tcg_out_st32_12(TCGContext *s, ARMCond cond, TCGReg rt, 650 TCGReg rn, int imm12) 651{ 652 tcg_out_memop_12(s, cond, INSN_STR_IMM, rt, rn, imm12, 1, 0); 653} 654 655static void tcg_out_ld32_r(TCGContext *s, ARMCond cond, TCGReg rt, 656 TCGReg rn, TCGReg rm) 657{ 658 tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 0); 659} 660 661static void tcg_out_st32_r(TCGContext *s, ARMCond cond, TCGReg rt, 662 TCGReg rn, TCGReg rm) 663{ 664 tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 0); 665} 666 667static void tcg_out_ldrd_8(TCGContext *s, ARMCond cond, TCGReg rt, 668 TCGReg rn, int imm8) 669{ 670 tcg_out_memop_8(s, cond, INSN_LDRD_IMM, rt, rn, imm8, 1, 0); 671} 672 673static void tcg_out_ldrd_r(TCGContext *s, ARMCond cond, TCGReg rt, 674 TCGReg rn, TCGReg rm) 675{ 676 tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 0); 677} 678 679static void tcg_out_strd_8(TCGContext *s, ARMCond cond, TCGReg rt, 680 TCGReg rn, int imm8) 681{ 682 tcg_out_memop_8(s, cond, INSN_STRD_IMM, rt, rn, imm8, 1, 0); 683} 684 685static void tcg_out_strd_r(TCGContext *s, ARMCond cond, TCGReg rt, 686 TCGReg rn, TCGReg rm) 687{ 688 tcg_out_memop_r(s, cond, INSN_STRD_REG, rt, rn, rm, 1, 1, 0); 689} 690 691/* Register pre-increment with base writeback. */ 692static void tcg_out_ld32_rwb(TCGContext *s, ARMCond cond, TCGReg rt, 693 TCGReg rn, TCGReg rm) 694{ 695 tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 1); 696} 697 698static void tcg_out_st32_rwb(TCGContext *s, ARMCond cond, TCGReg rt, 699 TCGReg rn, TCGReg rm) 700{ 701 tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 1); 702} 703 704static void tcg_out_ld16u_8(TCGContext *s, ARMCond cond, TCGReg rt, 705 TCGReg rn, int imm8) 706{ 707 tcg_out_memop_8(s, cond, INSN_LDRH_IMM, rt, rn, imm8, 1, 0); 708} 709 710static void tcg_out_st16_8(TCGContext *s, ARMCond cond, TCGReg rt, 711 TCGReg rn, int imm8) 712{ 713 tcg_out_memop_8(s, cond, INSN_STRH_IMM, rt, rn, imm8, 1, 0); 714} 715 716static void tcg_out_ld16u_r(TCGContext *s, ARMCond cond, TCGReg rt, 717 TCGReg rn, TCGReg rm) 718{ 719 tcg_out_memop_r(s, cond, INSN_LDRH_REG, rt, rn, rm, 1, 1, 0); 720} 721 722static void tcg_out_st16_r(TCGContext *s, ARMCond cond, TCGReg rt, 723 TCGReg rn, TCGReg rm) 724{ 725 tcg_out_memop_r(s, cond, INSN_STRH_REG, rt, rn, rm, 1, 1, 0); 726} 727 728static void tcg_out_ld16s_8(TCGContext *s, ARMCond cond, TCGReg rt, 729 TCGReg rn, int imm8) 730{ 731 tcg_out_memop_8(s, cond, INSN_LDRSH_IMM, rt, rn, imm8, 1, 0); 732} 733 734static void tcg_out_ld16s_r(TCGContext *s, ARMCond cond, TCGReg rt, 735 TCGReg rn, TCGReg rm) 736{ 737 tcg_out_memop_r(s, cond, INSN_LDRSH_REG, rt, rn, rm, 1, 1, 0); 738} 739 740static void tcg_out_ld8_12(TCGContext *s, ARMCond cond, TCGReg rt, 741 TCGReg rn, int imm12) 742{ 743 tcg_out_memop_12(s, cond, INSN_LDRB_IMM, rt, rn, imm12, 1, 0); 744} 745 746static void tcg_out_st8_12(TCGContext *s, ARMCond cond, TCGReg rt, 747 TCGReg rn, int imm12) 748{ 749 tcg_out_memop_12(s, cond, INSN_STRB_IMM, rt, rn, imm12, 1, 0); 750} 751 752static void tcg_out_ld8_r(TCGContext *s, ARMCond cond, TCGReg rt, 753 TCGReg rn, TCGReg rm) 754{ 755 tcg_out_memop_r(s, cond, INSN_LDRB_REG, rt, rn, rm, 1, 1, 0); 756} 757 758static void tcg_out_st8_r(TCGContext *s, ARMCond cond, TCGReg rt, 759 TCGReg rn, TCGReg rm) 760{ 761 tcg_out_memop_r(s, cond, INSN_STRB_REG, rt, rn, rm, 1, 1, 0); 762} 763 764static void tcg_out_ld8s_8(TCGContext *s, ARMCond cond, TCGReg rt, 765 TCGReg rn, int imm8) 766{ 767 tcg_out_memop_8(s, cond, INSN_LDRSB_IMM, rt, rn, imm8, 1, 0); 768} 769 770static void tcg_out_ld8s_r(TCGContext *s, ARMCond cond, TCGReg rt, 771 TCGReg rn, TCGReg rm) 772{ 773 tcg_out_memop_r(s, cond, INSN_LDRSB_REG, rt, rn, rm, 1, 1, 0); 774} 775 776static void tcg_out_movi_pool(TCGContext *s, ARMCond cond, 777 TCGReg rd, uint32_t arg) 778{ 779 new_pool_label(s, arg, R_ARM_PC13, s->code_ptr, 0); 780 tcg_out_ld32_12(s, cond, rd, TCG_REG_PC, 0); 781} 782 783static void tcg_out_movi32(TCGContext *s, ARMCond cond, 784 TCGReg rd, uint32_t arg) 785{ 786 int imm12, diff, opc, sh1, sh2; 787 uint32_t tt0, tt1, tt2; 788 789 /* Check a single MOV/MVN before anything else. */ 790 imm12 = encode_imm(arg); 791 if (imm12 >= 0) { 792 tcg_out_dat_imm(s, cond, ARITH_MOV, rd, 0, imm12); 793 return; 794 } 795 imm12 = encode_imm(~arg); 796 if (imm12 >= 0) { 797 tcg_out_dat_imm(s, cond, ARITH_MVN, rd, 0, imm12); 798 return; 799 } 800 801 /* Check for a pc-relative address. This will usually be the TB, 802 or within the TB, which is immediately before the code block. */ 803 diff = tcg_pcrel_diff(s, (void *)arg) - 8; 804 if (diff >= 0) { 805 imm12 = encode_imm(diff); 806 if (imm12 >= 0) { 807 tcg_out_dat_imm(s, cond, ARITH_ADD, rd, TCG_REG_PC, imm12); 808 return; 809 } 810 } else { 811 imm12 = encode_imm(-diff); 812 if (imm12 >= 0) { 813 tcg_out_dat_imm(s, cond, ARITH_SUB, rd, TCG_REG_PC, imm12); 814 return; 815 } 816 } 817 818 /* Use movw + movt. */ 819 if (use_armv7_instructions) { 820 /* movw */ 821 tcg_out32(s, (cond << 28) | 0x03000000 | (rd << 12) 822 | ((arg << 4) & 0x000f0000) | (arg & 0xfff)); 823 if (arg & 0xffff0000) { 824 /* movt */ 825 tcg_out32(s, (cond << 28) | 0x03400000 | (rd << 12) 826 | ((arg >> 12) & 0x000f0000) | ((arg >> 16) & 0xfff)); 827 } 828 return; 829 } 830 831 /* Look for sequences of two insns. If we have lots of 1's, we can 832 shorten the sequence by beginning with mvn and then clearing 833 higher bits with eor. */ 834 tt0 = arg; 835 opc = ARITH_MOV; 836 if (ctpop32(arg) > 16) { 837 tt0 = ~arg; 838 opc = ARITH_MVN; 839 } 840 sh1 = ctz32(tt0) & ~1; 841 tt1 = tt0 & ~(0xff << sh1); 842 sh2 = ctz32(tt1) & ~1; 843 tt2 = tt1 & ~(0xff << sh2); 844 if (tt2 == 0) { 845 int rot; 846 847 rot = ((32 - sh1) << 7) & 0xf00; 848 tcg_out_dat_imm(s, cond, opc, rd, 0, ((tt0 >> sh1) & 0xff) | rot); 849 rot = ((32 - sh2) << 7) & 0xf00; 850 tcg_out_dat_imm(s, cond, ARITH_EOR, rd, rd, 851 ((tt0 >> sh2) & 0xff) | rot); 852 return; 853 } 854 855 /* Otherwise, drop it into the constant pool. */ 856 tcg_out_movi_pool(s, cond, rd, arg); 857} 858 859/* 860 * Emit either the reg,imm or reg,reg form of a data-processing insn. 861 * rhs must satisfy the "rI" constraint. 862 */ 863static void tcg_out_dat_rI(TCGContext *s, ARMCond cond, ARMInsn opc, 864 TCGReg dst, TCGReg lhs, TCGArg rhs, int rhs_is_const) 865{ 866 if (rhs_is_const) { 867 tcg_out_dat_imm(s, cond, opc, dst, lhs, encode_imm_nofail(rhs)); 868 } else { 869 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); 870 } 871} 872 873/* 874 * Emit either the reg,imm or reg,reg form of a data-processing insn. 875 * rhs must satisfy the "rIK" constraint. 876 */ 877static void tcg_out_dat_IK(TCGContext *s, ARMCond cond, ARMInsn opc, 878 ARMInsn opinv, TCGReg dst, TCGReg lhs, TCGArg rhs) 879{ 880 int imm12 = encode_imm(rhs); 881 if (imm12 < 0) { 882 imm12 = encode_imm_nofail(~rhs); 883 opc = opinv; 884 } 885 tcg_out_dat_imm(s, cond, opc, dst, lhs, imm12); 886} 887 888static void tcg_out_dat_rIK(TCGContext *s, ARMCond cond, ARMInsn opc, 889 ARMInsn opinv, TCGReg dst, TCGReg lhs, TCGArg rhs, 890 bool rhs_is_const) 891{ 892 if (rhs_is_const) { 893 tcg_out_dat_IK(s, cond, opc, opinv, dst, lhs, rhs); 894 } else { 895 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); 896 } 897} 898 899static void tcg_out_dat_IN(TCGContext *s, ARMCond cond, ARMInsn opc, 900 ARMInsn opneg, TCGReg dst, TCGReg lhs, TCGArg rhs) 901{ 902 int imm12 = encode_imm(rhs); 903 if (imm12 < 0) { 904 imm12 = encode_imm_nofail(-rhs); 905 opc = opneg; 906 } 907 tcg_out_dat_imm(s, cond, opc, dst, lhs, imm12); 908} 909 910static void tcg_out_dat_rIN(TCGContext *s, ARMCond cond, ARMInsn opc, 911 ARMInsn opneg, TCGReg dst, TCGReg lhs, TCGArg rhs, 912 bool rhs_is_const) 913{ 914 /* Emit either the reg,imm or reg,reg form of a data-processing insn. 915 * rhs must satisfy the "rIN" constraint. 916 */ 917 if (rhs_is_const) { 918 tcg_out_dat_IN(s, cond, opc, opneg, dst, lhs, rhs); 919 } else { 920 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); 921 } 922} 923 924static void tcg_out_mul32(TCGContext *s, ARMCond cond, TCGReg rd, 925 TCGReg rn, TCGReg rm) 926{ 927 /* mul */ 928 tcg_out32(s, (cond << 28) | 0x90 | (rd << 16) | (rm << 8) | rn); 929} 930 931static void tcg_out_umull32(TCGContext *s, ARMCond cond, TCGReg rd0, 932 TCGReg rd1, TCGReg rn, TCGReg rm) 933{ 934 /* umull */ 935 tcg_out32(s, (cond << 28) | 0x00800090 | 936 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); 937} 938 939static void tcg_out_smull32(TCGContext *s, ARMCond cond, TCGReg rd0, 940 TCGReg rd1, TCGReg rn, TCGReg rm) 941{ 942 /* smull */ 943 tcg_out32(s, (cond << 28) | 0x00c00090 | 944 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); 945} 946 947static void tcg_out_sdiv(TCGContext *s, ARMCond cond, 948 TCGReg rd, TCGReg rn, TCGReg rm) 949{ 950 tcg_out32(s, 0x0710f010 | (cond << 28) | (rd << 16) | rn | (rm << 8)); 951} 952 953static void tcg_out_udiv(TCGContext *s, ARMCond cond, 954 TCGReg rd, TCGReg rn, TCGReg rm) 955{ 956 tcg_out32(s, 0x0730f010 | (cond << 28) | (rd << 16) | rn | (rm << 8)); 957} 958 959static void tcg_out_ext8s(TCGContext *s, TCGType t, TCGReg rd, TCGReg rn) 960{ 961 /* sxtb */ 962 tcg_out32(s, 0x06af0070 | (COND_AL << 28) | (rd << 12) | rn); 963} 964 965static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rn) 966{ 967 tcg_out_dat_imm(s, COND_AL, ARITH_AND, rd, rn, 0xff); 968} 969 970static void tcg_out_ext16s(TCGContext *s, TCGType t, TCGReg rd, TCGReg rn) 971{ 972 /* sxth */ 973 tcg_out32(s, 0x06bf0070 | (COND_AL << 28) | (rd << 12) | rn); 974} 975 976static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rn) 977{ 978 /* uxth */ 979 tcg_out32(s, 0x06ff0070 | (COND_AL << 28) | (rd << 12) | rn); 980} 981 982static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rn) 983{ 984 g_assert_not_reached(); 985} 986 987static void tcg_out_ext32u(TCGContext *s, TCGReg rd, TCGReg rn) 988{ 989 g_assert_not_reached(); 990} 991 992static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rn) 993{ 994 g_assert_not_reached(); 995} 996 997static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rn) 998{ 999 g_assert_not_reached(); 1000} 1001 1002static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rn) 1003{ 1004 g_assert_not_reached(); 1005} 1006 1007static void tcg_out_bswap16(TCGContext *s, ARMCond cond, 1008 TCGReg rd, TCGReg rn, int flags) 1009{ 1010 if (flags & TCG_BSWAP_OS) { 1011 /* revsh */ 1012 tcg_out32(s, 0x06ff0fb0 | (cond << 28) | (rd << 12) | rn); 1013 return; 1014 } 1015 1016 /* rev16 */ 1017 tcg_out32(s, 0x06bf0fb0 | (cond << 28) | (rd << 12) | rn); 1018 if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 1019 /* uxth */ 1020 tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | rd); 1021 } 1022} 1023 1024static void tcg_out_bswap32(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rn) 1025{ 1026 /* rev */ 1027 tcg_out32(s, 0x06bf0f30 | (cond << 28) | (rd << 12) | rn); 1028} 1029 1030static void tcg_out_deposit(TCGContext *s, ARMCond cond, TCGReg rd, 1031 TCGArg a1, int ofs, int len, bool const_a1) 1032{ 1033 if (const_a1) { 1034 /* bfi becomes bfc with rn == 15. */ 1035 a1 = 15; 1036 } 1037 /* bfi/bfc */ 1038 tcg_out32(s, 0x07c00010 | (cond << 28) | (rd << 12) | a1 1039 | (ofs << 7) | ((ofs + len - 1) << 16)); 1040} 1041 1042static void tcg_out_extract(TCGContext *s, ARMCond cond, TCGReg rd, 1043 TCGReg rn, int ofs, int len) 1044{ 1045 /* According to gcc, AND can be faster. */ 1046 if (ofs == 0 && len <= 8) { 1047 tcg_out_dat_imm(s, cond, ARITH_AND, rd, rn, 1048 encode_imm_nofail((1 << len) - 1)); 1049 return; 1050 } 1051 1052 if (use_armv7_instructions) { 1053 /* ubfx */ 1054 tcg_out32(s, 0x07e00050 | (cond << 28) | (rd << 12) | rn 1055 | (ofs << 7) | ((len - 1) << 16)); 1056 return; 1057 } 1058 1059 assert(ofs % 8 == 0); 1060 switch (len) { 1061 case 8: 1062 /* uxtb */ 1063 tcg_out32(s, 0x06ef0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn); 1064 break; 1065 case 16: 1066 /* uxth */ 1067 tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn); 1068 break; 1069 default: 1070 g_assert_not_reached(); 1071 } 1072} 1073 1074static void tcg_out_sextract(TCGContext *s, ARMCond cond, TCGReg rd, 1075 TCGReg rn, int ofs, int len) 1076{ 1077 if (use_armv7_instructions) { 1078 /* sbfx */ 1079 tcg_out32(s, 0x07a00050 | (cond << 28) | (rd << 12) | rn 1080 | (ofs << 7) | ((len - 1) << 16)); 1081 return; 1082 } 1083 1084 assert(ofs % 8 == 0); 1085 switch (len) { 1086 case 8: 1087 /* sxtb */ 1088 tcg_out32(s, 0x06af0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn); 1089 break; 1090 case 16: 1091 /* sxth */ 1092 tcg_out32(s, 0x06bf0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn); 1093 break; 1094 default: 1095 g_assert_not_reached(); 1096 } 1097} 1098 1099 1100static void tcg_out_ld32u(TCGContext *s, ARMCond cond, 1101 TCGReg rd, TCGReg rn, int32_t offset) 1102{ 1103 if (offset > 0xfff || offset < -0xfff) { 1104 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1105 tcg_out_ld32_r(s, cond, rd, rn, TCG_REG_TMP); 1106 } else 1107 tcg_out_ld32_12(s, cond, rd, rn, offset); 1108} 1109 1110static void tcg_out_st32(TCGContext *s, ARMCond cond, 1111 TCGReg rd, TCGReg rn, int32_t offset) 1112{ 1113 if (offset > 0xfff || offset < -0xfff) { 1114 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1115 tcg_out_st32_r(s, cond, rd, rn, TCG_REG_TMP); 1116 } else 1117 tcg_out_st32_12(s, cond, rd, rn, offset); 1118} 1119 1120static void tcg_out_ld16u(TCGContext *s, ARMCond cond, 1121 TCGReg rd, TCGReg rn, int32_t offset) 1122{ 1123 if (offset > 0xff || offset < -0xff) { 1124 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1125 tcg_out_ld16u_r(s, cond, rd, rn, TCG_REG_TMP); 1126 } else 1127 tcg_out_ld16u_8(s, cond, rd, rn, offset); 1128} 1129 1130static void tcg_out_ld16s(TCGContext *s, ARMCond cond, 1131 TCGReg rd, TCGReg rn, int32_t offset) 1132{ 1133 if (offset > 0xff || offset < -0xff) { 1134 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1135 tcg_out_ld16s_r(s, cond, rd, rn, TCG_REG_TMP); 1136 } else 1137 tcg_out_ld16s_8(s, cond, rd, rn, offset); 1138} 1139 1140static void tcg_out_st16(TCGContext *s, ARMCond cond, 1141 TCGReg rd, TCGReg rn, int32_t offset) 1142{ 1143 if (offset > 0xff || offset < -0xff) { 1144 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1145 tcg_out_st16_r(s, cond, rd, rn, TCG_REG_TMP); 1146 } else 1147 tcg_out_st16_8(s, cond, rd, rn, offset); 1148} 1149 1150static void tcg_out_ld8u(TCGContext *s, ARMCond cond, 1151 TCGReg rd, TCGReg rn, int32_t offset) 1152{ 1153 if (offset > 0xfff || offset < -0xfff) { 1154 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1155 tcg_out_ld8_r(s, cond, rd, rn, TCG_REG_TMP); 1156 } else 1157 tcg_out_ld8_12(s, cond, rd, rn, offset); 1158} 1159 1160static void tcg_out_ld8s(TCGContext *s, ARMCond cond, 1161 TCGReg rd, TCGReg rn, int32_t offset) 1162{ 1163 if (offset > 0xff || offset < -0xff) { 1164 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1165 tcg_out_ld8s_r(s, cond, rd, rn, TCG_REG_TMP); 1166 } else 1167 tcg_out_ld8s_8(s, cond, rd, rn, offset); 1168} 1169 1170static void tcg_out_st8(TCGContext *s, ARMCond cond, 1171 TCGReg rd, TCGReg rn, int32_t offset) 1172{ 1173 if (offset > 0xfff || offset < -0xfff) { 1174 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1175 tcg_out_st8_r(s, cond, rd, rn, TCG_REG_TMP); 1176 } else 1177 tcg_out_st8_12(s, cond, rd, rn, offset); 1178} 1179 1180/* 1181 * The _goto case is normally between TBs within the same code buffer, and 1182 * with the code buffer limited to 16MB we wouldn't need the long case. 1183 * But we also use it for the tail-call to the qemu_ld/st helpers, which does. 1184 */ 1185static void tcg_out_goto(TCGContext *s, ARMCond cond, const tcg_insn_unit *addr) 1186{ 1187 intptr_t addri = (intptr_t)addr; 1188 ptrdiff_t disp = tcg_pcrel_diff(s, addr); 1189 bool arm_mode = !(addri & 1); 1190 1191 if (arm_mode && disp - 8 < 0x01fffffd && disp - 8 > -0x01fffffd) { 1192 tcg_out_b_imm(s, cond, disp); 1193 return; 1194 } 1195 1196 /* LDR is interworking from v5t. */ 1197 tcg_out_movi_pool(s, cond, TCG_REG_PC, addri); 1198} 1199 1200/* 1201 * The call case is mostly used for helpers - so it's not unreasonable 1202 * for them to be beyond branch range. 1203 */ 1204static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *addr) 1205{ 1206 intptr_t addri = (intptr_t)addr; 1207 ptrdiff_t disp = tcg_pcrel_diff(s, addr); 1208 bool arm_mode = !(addri & 1); 1209 1210 if (disp - 8 < 0x02000000 && disp - 8 >= -0x02000000) { 1211 if (arm_mode) { 1212 tcg_out_bl_imm(s, COND_AL, disp); 1213 } else { 1214 tcg_out_blx_imm(s, disp); 1215 } 1216 return; 1217 } 1218 1219 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri); 1220 tcg_out_blx_reg(s, COND_AL, TCG_REG_TMP); 1221} 1222 1223static void tcg_out_call(TCGContext *s, const tcg_insn_unit *addr, 1224 const TCGHelperInfo *info) 1225{ 1226 tcg_out_call_int(s, addr); 1227} 1228 1229static void tcg_out_goto_label(TCGContext *s, ARMCond cond, TCGLabel *l) 1230{ 1231 if (l->has_value) { 1232 tcg_out_goto(s, cond, l->u.value_ptr); 1233 } else { 1234 tcg_out_reloc(s, s->code_ptr, R_ARM_PC24, l, 0); 1235 tcg_out_b_imm(s, cond, 0); 1236 } 1237} 1238 1239static void tcg_out_mb(TCGContext *s, TCGArg a0) 1240{ 1241 if (use_armv7_instructions) { 1242 tcg_out32(s, INSN_DMB_ISH); 1243 } else { 1244 tcg_out32(s, INSN_DMB_MCR); 1245 } 1246} 1247 1248static TCGCond tcg_out_cmp(TCGContext *s, TCGCond cond, TCGReg a, 1249 TCGArg b, int b_const) 1250{ 1251 if (!is_tst_cond(cond)) { 1252 tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, a, b, b_const); 1253 return cond; 1254 } 1255 1256 cond = tcg_tst_eqne_cond(cond); 1257 if (b_const) { 1258 int imm12 = encode_imm(b); 1259 1260 /* 1261 * The compare constraints allow rIN, but TST does not support N. 1262 * Be prepared to load the constant into a scratch register. 1263 */ 1264 if (imm12 >= 0) { 1265 tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, a, imm12); 1266 return cond; 1267 } 1268 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, b); 1269 b = TCG_REG_TMP; 1270 } 1271 tcg_out_dat_reg(s, COND_AL, ARITH_TST, 0, a, b, SHIFT_IMM_LSL(0)); 1272 return cond; 1273} 1274 1275static TCGCond tcg_out_cmp2(TCGContext *s, const TCGArg *args, 1276 const int *const_args) 1277{ 1278 TCGReg al = args[0]; 1279 TCGReg ah = args[1]; 1280 TCGArg bl = args[2]; 1281 TCGArg bh = args[3]; 1282 TCGCond cond = args[4]; 1283 int const_bl = const_args[2]; 1284 int const_bh = const_args[3]; 1285 1286 switch (cond) { 1287 case TCG_COND_EQ: 1288 case TCG_COND_NE: 1289 case TCG_COND_LTU: 1290 case TCG_COND_LEU: 1291 case TCG_COND_GTU: 1292 case TCG_COND_GEU: 1293 /* 1294 * We perform a conditional comparison. If the high half is 1295 * equal, then overwrite the flags with the comparison of the 1296 * low half. The resulting flags cover the whole. 1297 */ 1298 tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, ah, bh, const_bh); 1299 tcg_out_dat_rI(s, COND_EQ, ARITH_CMP, 0, al, bl, const_bl); 1300 return cond; 1301 1302 case TCG_COND_TSTEQ: 1303 case TCG_COND_TSTNE: 1304 /* Similar, but with TST instead of CMP. */ 1305 tcg_out_dat_rI(s, COND_AL, ARITH_TST, 0, ah, bh, const_bh); 1306 tcg_out_dat_rI(s, COND_EQ, ARITH_TST, 0, al, bl, const_bl); 1307 return tcg_tst_eqne_cond(cond); 1308 1309 case TCG_COND_LT: 1310 case TCG_COND_GE: 1311 /* We perform a double-word subtraction and examine the result. 1312 We do not actually need the result of the subtract, so the 1313 low part "subtract" is a compare. For the high half we have 1314 no choice but to compute into a temporary. */ 1315 tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, al, bl, const_bl); 1316 tcg_out_dat_rI(s, COND_AL, ARITH_SBC | TO_CPSR, 1317 TCG_REG_TMP, ah, bh, const_bh); 1318 return cond; 1319 1320 case TCG_COND_LE: 1321 case TCG_COND_GT: 1322 /* Similar, but with swapped arguments, via reversed subtract. */ 1323 tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR, 1324 TCG_REG_TMP, al, bl, const_bl); 1325 tcg_out_dat_rI(s, COND_AL, ARITH_RSC | TO_CPSR, 1326 TCG_REG_TMP, ah, bh, const_bh); 1327 return tcg_swap_cond(cond); 1328 1329 default: 1330 g_assert_not_reached(); 1331 } 1332} 1333 1334/* 1335 * Note that TCGReg references Q-registers. 1336 * Q-regno = 2 * D-regno, so shift left by 1 while inserting. 1337 */ 1338static uint32_t encode_vd(TCGReg rd) 1339{ 1340 tcg_debug_assert(rd >= TCG_REG_Q0); 1341 return (extract32(rd, 3, 1) << 22) | (extract32(rd, 0, 3) << 13); 1342} 1343 1344static uint32_t encode_vn(TCGReg rn) 1345{ 1346 tcg_debug_assert(rn >= TCG_REG_Q0); 1347 return (extract32(rn, 3, 1) << 7) | (extract32(rn, 0, 3) << 17); 1348} 1349 1350static uint32_t encode_vm(TCGReg rm) 1351{ 1352 tcg_debug_assert(rm >= TCG_REG_Q0); 1353 return (extract32(rm, 3, 1) << 5) | (extract32(rm, 0, 3) << 1); 1354} 1355 1356static void tcg_out_vreg2(TCGContext *s, ARMInsn insn, int q, int vece, 1357 TCGReg d, TCGReg m) 1358{ 1359 tcg_out32(s, insn | (vece << 18) | (q << 6) | 1360 encode_vd(d) | encode_vm(m)); 1361} 1362 1363static void tcg_out_vreg3(TCGContext *s, ARMInsn insn, int q, int vece, 1364 TCGReg d, TCGReg n, TCGReg m) 1365{ 1366 tcg_out32(s, insn | (vece << 20) | (q << 6) | 1367 encode_vd(d) | encode_vn(n) | encode_vm(m)); 1368} 1369 1370static void tcg_out_vmovi(TCGContext *s, TCGReg rd, 1371 int q, int op, int cmode, uint8_t imm8) 1372{ 1373 tcg_out32(s, INSN_VMOVI | encode_vd(rd) | (q << 6) | (op << 5) 1374 | (cmode << 8) | extract32(imm8, 0, 4) 1375 | (extract32(imm8, 4, 3) << 16) 1376 | (extract32(imm8, 7, 1) << 24)); 1377} 1378 1379static void tcg_out_vshifti(TCGContext *s, ARMInsn insn, int q, 1380 TCGReg rd, TCGReg rm, int l_imm6) 1381{ 1382 tcg_out32(s, insn | (q << 6) | encode_vd(rd) | encode_vm(rm) | 1383 (extract32(l_imm6, 6, 1) << 7) | 1384 (extract32(l_imm6, 0, 6) << 16)); 1385} 1386 1387static void tcg_out_vldst(TCGContext *s, ARMInsn insn, 1388 TCGReg rd, TCGReg rn, int offset) 1389{ 1390 if (offset != 0) { 1391 if (check_fit_imm(offset) || check_fit_imm(-offset)) { 1392 tcg_out_dat_rIN(s, COND_AL, ARITH_ADD, ARITH_SUB, 1393 TCG_REG_TMP, rn, offset, true); 1394 } else { 1395 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, offset); 1396 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, 1397 TCG_REG_TMP, TCG_REG_TMP, rn, 0); 1398 } 1399 rn = TCG_REG_TMP; 1400 } 1401 tcg_out32(s, insn | (rn << 16) | encode_vd(rd) | 0xf); 1402} 1403 1404typedef struct { 1405 ARMCond cond; 1406 TCGReg base; 1407 int index; 1408 bool index_scratch; 1409 TCGAtomAlign aa; 1410} HostAddress; 1411 1412bool tcg_target_has_memory_bswap(MemOp memop) 1413{ 1414 return false; 1415} 1416 1417static TCGReg ldst_ra_gen(TCGContext *s, const TCGLabelQemuLdst *l, int arg) 1418{ 1419 /* We arrive at the slow path via "BLNE", so R14 contains l->raddr. */ 1420 return TCG_REG_R14; 1421} 1422 1423static const TCGLdstHelperParam ldst_helper_param = { 1424 .ra_gen = ldst_ra_gen, 1425 .ntmp = 1, 1426 .tmp = { TCG_REG_TMP }, 1427}; 1428 1429static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1430{ 1431 MemOp opc = get_memop(lb->oi); 1432 1433 if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1434 return false; 1435 } 1436 1437 tcg_out_ld_helper_args(s, lb, &ldst_helper_param); 1438 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE]); 1439 tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param); 1440 1441 tcg_out_goto(s, COND_AL, lb->raddr); 1442 return true; 1443} 1444 1445static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1446{ 1447 MemOp opc = get_memop(lb->oi); 1448 1449 if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1450 return false; 1451 } 1452 1453 tcg_out_st_helper_args(s, lb, &ldst_helper_param); 1454 1455 /* Tail-call to the helper, which will return to the fast path. */ 1456 tcg_out_goto(s, COND_AL, qemu_st_helpers[opc & MO_SIZE]); 1457 return true; 1458} 1459 1460/* We expect to use an 9-bit sign-magnitude negative offset from ENV. */ 1461#define MIN_TLB_MASK_TABLE_OFS -256 1462 1463static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1464 TCGReg addr, MemOpIdx oi, bool is_ld) 1465{ 1466 TCGLabelQemuLdst *ldst = NULL; 1467 MemOp opc = get_memop(oi); 1468 unsigned a_mask; 1469 1470 if (tcg_use_softmmu) { 1471 *h = (HostAddress){ 1472 .cond = COND_AL, 1473 .base = addr, 1474 .index = TCG_REG_R1, 1475 .index_scratch = true, 1476 }; 1477 } else { 1478 *h = (HostAddress){ 1479 .cond = COND_AL, 1480 .base = addr, 1481 .index = guest_base ? TCG_REG_GUEST_BASE : -1, 1482 .index_scratch = false, 1483 }; 1484 } 1485 1486 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); 1487 a_mask = (1 << h->aa.align) - 1; 1488 1489 if (tcg_use_softmmu) { 1490 int mem_index = get_mmuidx(oi); 1491 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read) 1492 : offsetof(CPUTLBEntry, addr_write); 1493 int fast_off = tlb_mask_table_ofs(s, mem_index); 1494 unsigned s_mask = (1 << (opc & MO_SIZE)) - 1; 1495 TCGReg t_addr; 1496 1497 ldst = new_ldst_label(s); 1498 ldst->is_ld = is_ld; 1499 ldst->oi = oi; 1500 ldst->addr_reg = addr; 1501 1502 /* Load cpu->neg.tlb.f[mmu_idx].{mask,table} into {r0,r1}. */ 1503 QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0); 1504 QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != 4); 1505 tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off); 1506 1507 /* Extract the tlb index from the address into R0. */ 1508 tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, addr, 1509 SHIFT_IMM_LSR(s->page_bits - CPU_TLB_ENTRY_BITS)); 1510 1511 /* 1512 * Add the tlb_table pointer, creating the CPUTLBEntry address in R1. 1513 * Load the tlb comparator into R2 and the fast path addend into R1. 1514 */ 1515 if (cmp_off == 0) { 1516 tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0); 1517 } else { 1518 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, 1519 TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0); 1520 tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); 1521 } 1522 1523 /* Load the tlb addend. */ 1524 tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R1, 1525 offsetof(CPUTLBEntry, addend)); 1526 1527 /* 1528 * Check alignment, check comparators. 1529 * Do this in 2-4 insns. Use MOVW for v7, if possible, 1530 * to reduce the number of sequential conditional instructions. 1531 * Almost all guests have at least 4k pages, which means that we need 1532 * to clear at least 9 bits even for an 8-byte memory, which means it 1533 * isn't worth checking for an immediate operand for BIC. 1534 * 1535 * For unaligned accesses, test the page of the last unit of alignment. 1536 * This leaves the least significant alignment bits unchanged, and of 1537 * course must be zero. 1538 */ 1539 t_addr = addr; 1540 if (a_mask < s_mask) { 1541 t_addr = TCG_REG_R0; 1542 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, t_addr, 1543 addr, s_mask - a_mask); 1544 } 1545 if (use_armv7_instructions && s->page_bits <= 16) { 1546 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, ~(s->page_mask | a_mask)); 1547 tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP, 1548 t_addr, TCG_REG_TMP, 0); 1549 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, 1550 TCG_REG_R2, TCG_REG_TMP, 0); 1551 } else { 1552 if (a_mask) { 1553 tcg_debug_assert(a_mask <= 0xff); 1554 tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addr, a_mask); 1555 } 1556 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, t_addr, 1557 SHIFT_IMM_LSR(s->page_bits)); 1558 tcg_out_dat_reg(s, (a_mask ? COND_EQ : COND_AL), ARITH_CMP, 1559 0, TCG_REG_R2, TCG_REG_TMP, 1560 SHIFT_IMM_LSL(s->page_bits)); 1561 } 1562 } else if (a_mask) { 1563 ldst = new_ldst_label(s); 1564 ldst->is_ld = is_ld; 1565 ldst->oi = oi; 1566 ldst->addr_reg = addr; 1567 1568 /* We are expecting alignment to max out at 7 */ 1569 tcg_debug_assert(a_mask <= 0xff); 1570 /* tst addr, #mask */ 1571 tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addr, a_mask); 1572 } 1573 1574 return ldst; 1575} 1576 1577static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo, 1578 TCGReg datahi, HostAddress h) 1579{ 1580 TCGReg base; 1581 1582 /* Byte swapping is left to middle-end expansion. */ 1583 tcg_debug_assert((opc & MO_BSWAP) == 0); 1584 1585 switch (opc & MO_SSIZE) { 1586 case MO_UB: 1587 if (h.index < 0) { 1588 tcg_out_ld8_12(s, h.cond, datalo, h.base, 0); 1589 } else { 1590 tcg_out_ld8_r(s, h.cond, datalo, h.base, h.index); 1591 } 1592 break; 1593 case MO_SB: 1594 if (h.index < 0) { 1595 tcg_out_ld8s_8(s, h.cond, datalo, h.base, 0); 1596 } else { 1597 tcg_out_ld8s_r(s, h.cond, datalo, h.base, h.index); 1598 } 1599 break; 1600 case MO_UW: 1601 if (h.index < 0) { 1602 tcg_out_ld16u_8(s, h.cond, datalo, h.base, 0); 1603 } else { 1604 tcg_out_ld16u_r(s, h.cond, datalo, h.base, h.index); 1605 } 1606 break; 1607 case MO_SW: 1608 if (h.index < 0) { 1609 tcg_out_ld16s_8(s, h.cond, datalo, h.base, 0); 1610 } else { 1611 tcg_out_ld16s_r(s, h.cond, datalo, h.base, h.index); 1612 } 1613 break; 1614 case MO_UL: 1615 if (h.index < 0) { 1616 tcg_out_ld32_12(s, h.cond, datalo, h.base, 0); 1617 } else { 1618 tcg_out_ld32_r(s, h.cond, datalo, h.base, h.index); 1619 } 1620 break; 1621 case MO_UQ: 1622 /* We used pair allocation for datalo, so already should be aligned. */ 1623 tcg_debug_assert((datalo & 1) == 0); 1624 tcg_debug_assert(datahi == datalo + 1); 1625 /* LDRD requires alignment; double-check that. */ 1626 if (memop_alignment_bits(opc) >= MO_64) { 1627 if (h.index < 0) { 1628 tcg_out_ldrd_8(s, h.cond, datalo, h.base, 0); 1629 break; 1630 } 1631 /* 1632 * Rm (the second address op) must not overlap Rt or Rt + 1. 1633 * Since datalo is aligned, we can simplify the test via alignment. 1634 * Flip the two address arguments if that works. 1635 */ 1636 if ((h.index & ~1) != datalo) { 1637 tcg_out_ldrd_r(s, h.cond, datalo, h.base, h.index); 1638 break; 1639 } 1640 if ((h.base & ~1) != datalo) { 1641 tcg_out_ldrd_r(s, h.cond, datalo, h.index, h.base); 1642 break; 1643 } 1644 } 1645 if (h.index < 0) { 1646 base = h.base; 1647 if (datalo == h.base) { 1648 tcg_out_mov_reg(s, h.cond, TCG_REG_TMP, base); 1649 base = TCG_REG_TMP; 1650 } 1651 } else if (h.index_scratch) { 1652 tcg_out_ld32_rwb(s, h.cond, datalo, h.index, h.base); 1653 tcg_out_ld32_12(s, h.cond, datahi, h.index, 4); 1654 break; 1655 } else { 1656 tcg_out_dat_reg(s, h.cond, ARITH_ADD, TCG_REG_TMP, 1657 h.base, h.index, SHIFT_IMM_LSL(0)); 1658 base = TCG_REG_TMP; 1659 } 1660 tcg_out_ld32_12(s, h.cond, datalo, base, 0); 1661 tcg_out_ld32_12(s, h.cond, datahi, base, 4); 1662 break; 1663 default: 1664 g_assert_not_reached(); 1665 } 1666} 1667 1668static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, 1669 TCGReg addr, MemOpIdx oi, TCGType data_type) 1670{ 1671 MemOp opc = get_memop(oi); 1672 TCGLabelQemuLdst *ldst; 1673 HostAddress h; 1674 1675 ldst = prepare_host_addr(s, &h, addr, oi, true); 1676 if (ldst) { 1677 ldst->type = data_type; 1678 ldst->datalo_reg = datalo; 1679 ldst->datahi_reg = datahi; 1680 1681 /* 1682 * This a conditional BL only to load a pointer within this 1683 * opcode into LR for the slow path. We will not be using 1684 * the value for a tail call. 1685 */ 1686 ldst->label_ptr[0] = s->code_ptr; 1687 tcg_out_bl_imm(s, COND_NE, 0); 1688 1689 tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); 1690 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1691 } else { 1692 tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); 1693 } 1694} 1695 1696static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo, 1697 TCGReg datahi, HostAddress h) 1698{ 1699 /* Byte swapping is left to middle-end expansion. */ 1700 tcg_debug_assert((opc & MO_BSWAP) == 0); 1701 1702 switch (opc & MO_SIZE) { 1703 case MO_8: 1704 if (h.index < 0) { 1705 tcg_out_st8_12(s, h.cond, datalo, h.base, 0); 1706 } else { 1707 tcg_out_st8_r(s, h.cond, datalo, h.base, h.index); 1708 } 1709 break; 1710 case MO_16: 1711 if (h.index < 0) { 1712 tcg_out_st16_8(s, h.cond, datalo, h.base, 0); 1713 } else { 1714 tcg_out_st16_r(s, h.cond, datalo, h.base, h.index); 1715 } 1716 break; 1717 case MO_32: 1718 if (h.index < 0) { 1719 tcg_out_st32_12(s, h.cond, datalo, h.base, 0); 1720 } else { 1721 tcg_out_st32_r(s, h.cond, datalo, h.base, h.index); 1722 } 1723 break; 1724 case MO_64: 1725 /* We used pair allocation for datalo, so already should be aligned. */ 1726 tcg_debug_assert((datalo & 1) == 0); 1727 tcg_debug_assert(datahi == datalo + 1); 1728 /* STRD requires alignment; double-check that. */ 1729 if (memop_alignment_bits(opc) >= MO_64) { 1730 if (h.index < 0) { 1731 tcg_out_strd_8(s, h.cond, datalo, h.base, 0); 1732 } else { 1733 tcg_out_strd_r(s, h.cond, datalo, h.base, h.index); 1734 } 1735 } else if (h.index < 0) { 1736 tcg_out_st32_12(s, h.cond, datalo, h.base, 0); 1737 tcg_out_st32_12(s, h.cond, datahi, h.base, 4); 1738 } else if (h.index_scratch) { 1739 tcg_out_st32_rwb(s, h.cond, datalo, h.index, h.base); 1740 tcg_out_st32_12(s, h.cond, datahi, h.index, 4); 1741 } else { 1742 tcg_out_dat_reg(s, h.cond, ARITH_ADD, TCG_REG_TMP, 1743 h.base, h.index, SHIFT_IMM_LSL(0)); 1744 tcg_out_st32_12(s, h.cond, datalo, TCG_REG_TMP, 0); 1745 tcg_out_st32_12(s, h.cond, datahi, TCG_REG_TMP, 4); 1746 } 1747 break; 1748 default: 1749 g_assert_not_reached(); 1750 } 1751} 1752 1753static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, 1754 TCGReg addr, MemOpIdx oi, TCGType data_type) 1755{ 1756 MemOp opc = get_memop(oi); 1757 TCGLabelQemuLdst *ldst; 1758 HostAddress h; 1759 1760 ldst = prepare_host_addr(s, &h, addr, oi, false); 1761 if (ldst) { 1762 ldst->type = data_type; 1763 ldst->datalo_reg = datalo; 1764 ldst->datahi_reg = datahi; 1765 1766 h.cond = COND_EQ; 1767 tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); 1768 1769 /* The conditional call is last, as we're going to return here. */ 1770 ldst->label_ptr[0] = s->code_ptr; 1771 tcg_out_bl_imm(s, COND_NE, 0); 1772 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1773 } else { 1774 tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); 1775 } 1776} 1777 1778static void tcg_out_epilogue(TCGContext *s); 1779 1780static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg) 1781{ 1782 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, arg); 1783 tcg_out_epilogue(s); 1784} 1785 1786static void tcg_out_goto_tb(TCGContext *s, int which) 1787{ 1788 uintptr_t i_addr; 1789 intptr_t i_disp; 1790 1791 /* Direct branch will be patched by tb_target_set_jmp_target. */ 1792 set_jmp_insn_offset(s, which); 1793 tcg_out32(s, INSN_NOP); 1794 1795 /* When branch is out of range, fall through to indirect. */ 1796 i_addr = get_jmp_target_addr(s, which); 1797 i_disp = tcg_pcrel_diff(s, (void *)i_addr) - 8; 1798 tcg_debug_assert(i_disp < 0); 1799 if (i_disp >= -0xfff) { 1800 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, i_disp); 1801 } else { 1802 /* 1803 * The TB is close, but outside the 12 bits addressable by 1804 * the load. We can extend this to 20 bits with a sub of a 1805 * shifted immediate from pc. 1806 */ 1807 int h = -i_disp; 1808 int l = -(h & 0xfff); 1809 1810 h = encode_imm_nofail(h + l); 1811 tcg_out_dat_imm(s, COND_AL, ARITH_SUB, TCG_REG_R0, TCG_REG_PC, h); 1812 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_R0, l); 1813 } 1814 set_jmp_reset_offset(s, which); 1815} 1816 1817void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1818 uintptr_t jmp_rx, uintptr_t jmp_rw) 1819{ 1820 uintptr_t addr = tb->jmp_target_addr[n]; 1821 ptrdiff_t offset = addr - (jmp_rx + 8); 1822 tcg_insn_unit insn; 1823 1824 /* Either directly branch, or fall through to indirect branch. */ 1825 if (offset == sextract64(offset, 0, 26)) { 1826 /* B <addr> */ 1827 insn = deposit32((COND_AL << 28) | INSN_B, 0, 24, offset >> 2); 1828 } else { 1829 insn = INSN_NOP; 1830 } 1831 1832 qatomic_set((uint32_t *)jmp_rw, insn); 1833 flush_idcache_range(jmp_rx, jmp_rw, 4); 1834} 1835 1836 1837static void tgen_add(TCGContext *s, TCGType type, 1838 TCGReg a0, TCGReg a1, TCGReg a2) 1839{ 1840 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, a0, a1, a2, SHIFT_IMM_LSL(0)); 1841} 1842 1843static void tgen_addi(TCGContext *s, TCGType type, 1844 TCGReg a0, TCGReg a1, tcg_target_long a2) 1845{ 1846 tcg_out_dat_IN(s, COND_AL, ARITH_ADD, ARITH_SUB, a0, a1, a2); 1847} 1848 1849static const TCGOutOpBinary outop_add = { 1850 .base.static_constraint = C_O1_I2(r, r, rIN), 1851 .out_rrr = tgen_add, 1852 .out_rri = tgen_addi, 1853}; 1854 1855static void tgen_and(TCGContext *s, TCGType type, 1856 TCGReg a0, TCGReg a1, TCGReg a2) 1857{ 1858 tcg_out_dat_reg(s, COND_AL, ARITH_AND, a0, a1, a2, SHIFT_IMM_LSL(0)); 1859} 1860 1861static void tgen_andi(TCGContext *s, TCGType type, 1862 TCGReg a0, TCGReg a1, tcg_target_long a2) 1863{ 1864 tcg_out_dat_IK(s, COND_AL, ARITH_AND, ARITH_BIC, a0, a1, a2); 1865} 1866 1867static const TCGOutOpBinary outop_and = { 1868 .base.static_constraint = C_O1_I2(r, r, rIK), 1869 .out_rrr = tgen_and, 1870 .out_rri = tgen_andi, 1871}; 1872 1873static void tgen_andc(TCGContext *s, TCGType type, 1874 TCGReg a0, TCGReg a1, TCGReg a2) 1875{ 1876 tcg_out_dat_reg(s, COND_AL, ARITH_BIC, a0, a1, a2, SHIFT_IMM_LSL(0)); 1877} 1878 1879static const TCGOutOpBinary outop_andc = { 1880 .base.static_constraint = C_O1_I2(r, r, r), 1881 .out_rrr = tgen_andc, 1882}; 1883 1884static void tgen_or(TCGContext *s, TCGType type, 1885 TCGReg a0, TCGReg a1, TCGReg a2) 1886{ 1887 tcg_out_dat_reg(s, COND_AL, ARITH_ORR, a0, a1, a2, SHIFT_IMM_LSL(0)); 1888} 1889 1890static void tgen_ori(TCGContext *s, TCGType type, 1891 TCGReg a0, TCGReg a1, tcg_target_long a2) 1892{ 1893 tcg_out_dat_imm(s, COND_AL, ARITH_ORR, a0, a1, encode_imm_nofail(a2)); 1894} 1895 1896static const TCGOutOpBinary outop_or = { 1897 .base.static_constraint = C_O1_I2(r, r, rI), 1898 .out_rrr = tgen_or, 1899 .out_rri = tgen_ori, 1900}; 1901 1902 1903static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, 1904 const TCGArg args[TCG_MAX_OP_ARGS], 1905 const int const_args[TCG_MAX_OP_ARGS]) 1906{ 1907 TCGArg a0, a1, a2, a3, a4, a5; 1908 int c; 1909 1910 switch (opc) { 1911 case INDEX_op_goto_ptr: 1912 tcg_out_b_reg(s, COND_AL, args[0]); 1913 break; 1914 case INDEX_op_br: 1915 tcg_out_goto_label(s, COND_AL, arg_label(args[0])); 1916 break; 1917 1918 case INDEX_op_ld8u_i32: 1919 tcg_out_ld8u(s, COND_AL, args[0], args[1], args[2]); 1920 break; 1921 case INDEX_op_ld8s_i32: 1922 tcg_out_ld8s(s, COND_AL, args[0], args[1], args[2]); 1923 break; 1924 case INDEX_op_ld16u_i32: 1925 tcg_out_ld16u(s, COND_AL, args[0], args[1], args[2]); 1926 break; 1927 case INDEX_op_ld16s_i32: 1928 tcg_out_ld16s(s, COND_AL, args[0], args[1], args[2]); 1929 break; 1930 case INDEX_op_ld_i32: 1931 tcg_out_ld32u(s, COND_AL, args[0], args[1], args[2]); 1932 break; 1933 case INDEX_op_st8_i32: 1934 tcg_out_st8(s, COND_AL, args[0], args[1], args[2]); 1935 break; 1936 case INDEX_op_st16_i32: 1937 tcg_out_st16(s, COND_AL, args[0], args[1], args[2]); 1938 break; 1939 case INDEX_op_st_i32: 1940 tcg_out_st32(s, COND_AL, args[0], args[1], args[2]); 1941 break; 1942 1943 case INDEX_op_movcond_i32: 1944 /* Constraints mean that v2 is always in the same register as dest, 1945 * so we only need to do "if condition passed, move v1 to dest". 1946 */ 1947 c = tcg_out_cmp(s, args[5], args[1], args[2], const_args[2]); 1948 tcg_out_dat_rIK(s, tcg_cond_to_arm_cond[c], ARITH_MOV, 1949 ARITH_MVN, args[0], 0, args[3], const_args[3]); 1950 break; 1951 case INDEX_op_sub_i32: 1952 if (const_args[1]) { 1953 if (const_args[2]) { 1954 tcg_out_movi32(s, COND_AL, args[0], args[1] - args[2]); 1955 } else { 1956 tcg_out_dat_rI(s, COND_AL, ARITH_RSB, 1957 args[0], args[2], args[1], 1); 1958 } 1959 } else { 1960 tcg_out_dat_rIN(s, COND_AL, ARITH_SUB, ARITH_ADD, 1961 args[0], args[1], args[2], const_args[2]); 1962 } 1963 break; 1964 case INDEX_op_xor_i32: 1965 c = ARITH_EOR; 1966 tcg_out_dat_rI(s, COND_AL, c, args[0], args[1], args[2], const_args[2]); 1967 break; 1968 case INDEX_op_add2_i32: 1969 a0 = args[0], a1 = args[1], a2 = args[2]; 1970 a3 = args[3], a4 = args[4], a5 = args[5]; 1971 if (a0 == a3 || (a0 == a5 && !const_args[5])) { 1972 a0 = TCG_REG_TMP; 1973 } 1974 tcg_out_dat_rIN(s, COND_AL, ARITH_ADD | TO_CPSR, ARITH_SUB | TO_CPSR, 1975 a0, a2, a4, const_args[4]); 1976 tcg_out_dat_rIK(s, COND_AL, ARITH_ADC, ARITH_SBC, 1977 a1, a3, a5, const_args[5]); 1978 tcg_out_mov_reg(s, COND_AL, args[0], a0); 1979 break; 1980 case INDEX_op_sub2_i32: 1981 a0 = args[0], a1 = args[1], a2 = args[2]; 1982 a3 = args[3], a4 = args[4], a5 = args[5]; 1983 if ((a0 == a3 && !const_args[3]) || (a0 == a5 && !const_args[5])) { 1984 a0 = TCG_REG_TMP; 1985 } 1986 if (const_args[2]) { 1987 if (const_args[4]) { 1988 tcg_out_movi32(s, COND_AL, a0, a4); 1989 a4 = a0; 1990 } 1991 tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR, a0, a4, a2, 1); 1992 } else { 1993 tcg_out_dat_rIN(s, COND_AL, ARITH_SUB | TO_CPSR, 1994 ARITH_ADD | TO_CPSR, a0, a2, a4, const_args[4]); 1995 } 1996 if (const_args[3]) { 1997 if (const_args[5]) { 1998 tcg_out_movi32(s, COND_AL, a1, a5); 1999 a5 = a1; 2000 } 2001 tcg_out_dat_rI(s, COND_AL, ARITH_RSC, a1, a5, a3, 1); 2002 } else { 2003 tcg_out_dat_rIK(s, COND_AL, ARITH_SBC, ARITH_ADC, 2004 a1, a3, a5, const_args[5]); 2005 } 2006 tcg_out_mov_reg(s, COND_AL, args[0], a0); 2007 break; 2008 case INDEX_op_neg_i32: 2009 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, args[0], args[1], 0); 2010 break; 2011 case INDEX_op_not_i32: 2012 tcg_out_dat_reg(s, COND_AL, 2013 ARITH_MVN, args[0], 0, args[1], SHIFT_IMM_LSL(0)); 2014 break; 2015 case INDEX_op_mul_i32: 2016 tcg_out_mul32(s, COND_AL, args[0], args[1], args[2]); 2017 break; 2018 case INDEX_op_mulu2_i32: 2019 tcg_out_umull32(s, COND_AL, args[0], args[1], args[2], args[3]); 2020 break; 2021 case INDEX_op_muls2_i32: 2022 tcg_out_smull32(s, COND_AL, args[0], args[1], args[2], args[3]); 2023 break; 2024 /* XXX: Perhaps args[2] & 0x1f is wrong */ 2025 case INDEX_op_shl_i32: 2026 c = const_args[2] ? 2027 SHIFT_IMM_LSL(args[2] & 0x1f) : SHIFT_REG_LSL(args[2]); 2028 goto gen_shift32; 2029 case INDEX_op_shr_i32: 2030 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_LSR(args[2] & 0x1f) : 2031 SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args[2]); 2032 goto gen_shift32; 2033 case INDEX_op_sar_i32: 2034 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ASR(args[2] & 0x1f) : 2035 SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args[2]); 2036 goto gen_shift32; 2037 case INDEX_op_rotr_i32: 2038 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ROR(args[2] & 0x1f) : 2039 SHIFT_IMM_LSL(0) : SHIFT_REG_ROR(args[2]); 2040 /* Fall through. */ 2041 gen_shift32: 2042 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], c); 2043 break; 2044 2045 case INDEX_op_rotl_i32: 2046 if (const_args[2]) { 2047 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], 2048 ((0x20 - args[2]) & 0x1f) ? 2049 SHIFT_IMM_ROR((0x20 - args[2]) & 0x1f) : 2050 SHIFT_IMM_LSL(0)); 2051 } else { 2052 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, TCG_REG_TMP, args[2], 0x20); 2053 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], 2054 SHIFT_REG_ROR(TCG_REG_TMP)); 2055 } 2056 break; 2057 2058 case INDEX_op_ctz_i32: 2059 tcg_out_dat_reg(s, COND_AL, INSN_RBIT, TCG_REG_TMP, 0, args[1], 0); 2060 a1 = TCG_REG_TMP; 2061 goto do_clz; 2062 2063 case INDEX_op_clz_i32: 2064 a1 = args[1]; 2065 do_clz: 2066 a0 = args[0]; 2067 a2 = args[2]; 2068 c = const_args[2]; 2069 if (c && a2 == 32) { 2070 tcg_out_dat_reg(s, COND_AL, INSN_CLZ, a0, 0, a1, 0); 2071 break; 2072 } 2073 tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0, a1, 0); 2074 tcg_out_dat_reg(s, COND_NE, INSN_CLZ, a0, 0, a1, 0); 2075 if (c || a0 != a2) { 2076 tcg_out_dat_rIK(s, COND_EQ, ARITH_MOV, ARITH_MVN, a0, 0, a2, c); 2077 } 2078 break; 2079 2080 case INDEX_op_brcond_i32: 2081 c = tcg_out_cmp(s, args[2], args[0], args[1], const_args[1]); 2082 tcg_out_goto_label(s, tcg_cond_to_arm_cond[c], arg_label(args[3])); 2083 break; 2084 case INDEX_op_setcond_i32: 2085 c = tcg_out_cmp(s, args[3], args[1], args[2], const_args[2]); 2086 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[c], 2087 ARITH_MOV, args[0], 0, 1); 2088 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(c)], 2089 ARITH_MOV, args[0], 0, 0); 2090 break; 2091 case INDEX_op_negsetcond_i32: 2092 c = tcg_out_cmp(s, args[3], args[1], args[2], const_args[2]); 2093 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[c], 2094 ARITH_MVN, args[0], 0, 0); 2095 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(c)], 2096 ARITH_MOV, args[0], 0, 0); 2097 break; 2098 2099 case INDEX_op_brcond2_i32: 2100 c = tcg_out_cmp2(s, args, const_args); 2101 tcg_out_goto_label(s, tcg_cond_to_arm_cond[c], arg_label(args[5])); 2102 break; 2103 case INDEX_op_setcond2_i32: 2104 c = tcg_out_cmp2(s, args + 1, const_args + 1); 2105 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[c], ARITH_MOV, args[0], 0, 1); 2106 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(c)], 2107 ARITH_MOV, args[0], 0, 0); 2108 break; 2109 2110 case INDEX_op_qemu_ld_i32: 2111 tcg_out_qemu_ld(s, args[0], -1, args[1], args[2], TCG_TYPE_I32); 2112 break; 2113 case INDEX_op_qemu_ld_i64: 2114 tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3], TCG_TYPE_I64); 2115 break; 2116 2117 case INDEX_op_qemu_st_i32: 2118 tcg_out_qemu_st(s, args[0], -1, args[1], args[2], TCG_TYPE_I32); 2119 break; 2120 case INDEX_op_qemu_st_i64: 2121 tcg_out_qemu_st(s, args[0], args[1], args[2], args[3], TCG_TYPE_I64); 2122 break; 2123 2124 case INDEX_op_bswap16_i32: 2125 tcg_out_bswap16(s, COND_AL, args[0], args[1], args[2]); 2126 break; 2127 case INDEX_op_bswap32_i32: 2128 tcg_out_bswap32(s, COND_AL, args[0], args[1]); 2129 break; 2130 2131 case INDEX_op_deposit_i32: 2132 tcg_out_deposit(s, COND_AL, args[0], args[2], 2133 args[3], args[4], const_args[2]); 2134 break; 2135 case INDEX_op_extract_i32: 2136 tcg_out_extract(s, COND_AL, args[0], args[1], args[2], args[3]); 2137 break; 2138 case INDEX_op_sextract_i32: 2139 tcg_out_sextract(s, COND_AL, args[0], args[1], args[2], args[3]); 2140 break; 2141 case INDEX_op_extract2_i32: 2142 /* ??? These optimization vs zero should be generic. */ 2143 /* ??? But we can't substitute 2 for 1 in the opcode stream yet. */ 2144 if (const_args[1]) { 2145 if (const_args[2]) { 2146 tcg_out_movi(s, TCG_TYPE_REG, args[0], 0); 2147 } else { 2148 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, 2149 args[2], SHIFT_IMM_LSL(32 - args[3])); 2150 } 2151 } else if (const_args[2]) { 2152 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, 2153 args[1], SHIFT_IMM_LSR(args[3])); 2154 } else { 2155 /* We can do extract2 in 2 insns, vs the 3 required otherwise. */ 2156 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, 2157 args[2], SHIFT_IMM_LSL(32 - args[3])); 2158 tcg_out_dat_reg(s, COND_AL, ARITH_ORR, args[0], TCG_REG_TMP, 2159 args[1], SHIFT_IMM_LSR(args[3])); 2160 } 2161 break; 2162 2163 case INDEX_op_div_i32: 2164 tcg_out_sdiv(s, COND_AL, args[0], args[1], args[2]); 2165 break; 2166 case INDEX_op_divu_i32: 2167 tcg_out_udiv(s, COND_AL, args[0], args[1], args[2]); 2168 break; 2169 2170 case INDEX_op_mb: 2171 tcg_out_mb(s, args[0]); 2172 break; 2173 2174 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2175 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2176 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2177 default: 2178 g_assert_not_reached(); 2179 } 2180} 2181 2182static TCGConstraintSetIndex 2183tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) 2184{ 2185 switch (op) { 2186 case INDEX_op_goto_ptr: 2187 return C_O0_I1(r); 2188 2189 case INDEX_op_ld8u_i32: 2190 case INDEX_op_ld8s_i32: 2191 case INDEX_op_ld16u_i32: 2192 case INDEX_op_ld16s_i32: 2193 case INDEX_op_ld_i32: 2194 case INDEX_op_neg_i32: 2195 case INDEX_op_not_i32: 2196 case INDEX_op_bswap16_i32: 2197 case INDEX_op_bswap32_i32: 2198 case INDEX_op_extract_i32: 2199 case INDEX_op_sextract_i32: 2200 return C_O1_I1(r, r); 2201 2202 case INDEX_op_st8_i32: 2203 case INDEX_op_st16_i32: 2204 case INDEX_op_st_i32: 2205 return C_O0_I2(r, r); 2206 2207 case INDEX_op_sub_i32: 2208 case INDEX_op_setcond_i32: 2209 case INDEX_op_negsetcond_i32: 2210 return C_O1_I2(r, r, rIN); 2211 2212 case INDEX_op_clz_i32: 2213 case INDEX_op_ctz_i32: 2214 return C_O1_I2(r, r, rIK); 2215 2216 case INDEX_op_mul_i32: 2217 case INDEX_op_div_i32: 2218 case INDEX_op_divu_i32: 2219 return C_O1_I2(r, r, r); 2220 2221 case INDEX_op_mulu2_i32: 2222 case INDEX_op_muls2_i32: 2223 return C_O2_I2(r, r, r, r); 2224 2225 case INDEX_op_xor_i32: 2226 return C_O1_I2(r, r, rI); 2227 2228 case INDEX_op_shl_i32: 2229 case INDEX_op_shr_i32: 2230 case INDEX_op_sar_i32: 2231 case INDEX_op_rotl_i32: 2232 case INDEX_op_rotr_i32: 2233 return C_O1_I2(r, r, ri); 2234 2235 case INDEX_op_brcond_i32: 2236 return C_O0_I2(r, rIN); 2237 case INDEX_op_deposit_i32: 2238 return C_O1_I2(r, 0, rZ); 2239 case INDEX_op_extract2_i32: 2240 return C_O1_I2(r, rZ, rZ); 2241 case INDEX_op_movcond_i32: 2242 return C_O1_I4(r, r, rIN, rIK, 0); 2243 case INDEX_op_add2_i32: 2244 return C_O2_I4(r, r, r, r, rIN, rIK); 2245 case INDEX_op_sub2_i32: 2246 return C_O2_I4(r, r, rI, rI, rIN, rIK); 2247 case INDEX_op_brcond2_i32: 2248 return C_O0_I4(r, r, rI, rI); 2249 case INDEX_op_setcond2_i32: 2250 return C_O1_I4(r, r, r, rI, rI); 2251 2252 case INDEX_op_qemu_ld_i32: 2253 return C_O1_I1(r, q); 2254 case INDEX_op_qemu_ld_i64: 2255 return C_O2_I1(e, p, q); 2256 case INDEX_op_qemu_st_i32: 2257 return C_O0_I2(q, q); 2258 case INDEX_op_qemu_st_i64: 2259 return C_O0_I3(Q, p, q); 2260 2261 case INDEX_op_st_vec: 2262 return C_O0_I2(w, r); 2263 case INDEX_op_ld_vec: 2264 case INDEX_op_dupm_vec: 2265 return C_O1_I1(w, r); 2266 case INDEX_op_dup_vec: 2267 return C_O1_I1(w, wr); 2268 case INDEX_op_abs_vec: 2269 case INDEX_op_neg_vec: 2270 case INDEX_op_not_vec: 2271 case INDEX_op_shli_vec: 2272 case INDEX_op_shri_vec: 2273 case INDEX_op_sari_vec: 2274 return C_O1_I1(w, w); 2275 case INDEX_op_dup2_vec: 2276 case INDEX_op_add_vec: 2277 case INDEX_op_mul_vec: 2278 case INDEX_op_smax_vec: 2279 case INDEX_op_smin_vec: 2280 case INDEX_op_ssadd_vec: 2281 case INDEX_op_sssub_vec: 2282 case INDEX_op_sub_vec: 2283 case INDEX_op_umax_vec: 2284 case INDEX_op_umin_vec: 2285 case INDEX_op_usadd_vec: 2286 case INDEX_op_ussub_vec: 2287 case INDEX_op_xor_vec: 2288 case INDEX_op_arm_sshl_vec: 2289 case INDEX_op_arm_ushl_vec: 2290 return C_O1_I2(w, w, w); 2291 case INDEX_op_arm_sli_vec: 2292 return C_O1_I2(w, 0, w); 2293 case INDEX_op_or_vec: 2294 case INDEX_op_andc_vec: 2295 return C_O1_I2(w, w, wO); 2296 case INDEX_op_and_vec: 2297 case INDEX_op_orc_vec: 2298 return C_O1_I2(w, w, wV); 2299 case INDEX_op_cmp_vec: 2300 return C_O1_I2(w, w, wZ); 2301 case INDEX_op_bitsel_vec: 2302 return C_O1_I3(w, w, w, w); 2303 default: 2304 return C_NotImplemented; 2305 } 2306} 2307 2308static void tcg_target_init(TCGContext *s) 2309{ 2310 /* 2311 * Only probe for the platform and capabilities if we haven't already 2312 * determined maximum values at compile time. 2313 */ 2314#if !defined(use_idiv_instructions) || !defined(use_neon_instructions) 2315 { 2316 unsigned long hwcap = qemu_getauxval(AT_HWCAP); 2317#ifndef use_idiv_instructions 2318 use_idiv_instructions = (hwcap & HWCAP_ARM_IDIVA) != 0; 2319#endif 2320#ifndef use_neon_instructions 2321 use_neon_instructions = (hwcap & HWCAP_ARM_NEON) != 0; 2322#endif 2323 } 2324#endif 2325 2326 if (__ARM_ARCH < 7) { 2327 const char *pl = (const char *)qemu_getauxval(AT_PLATFORM); 2328 if (pl != NULL && pl[0] == 'v' && pl[1] >= '4' && pl[1] <= '9') { 2329 arm_arch = pl[1] - '0'; 2330 } 2331 2332 if (arm_arch < 6) { 2333 error_report("TCG: ARMv%d is unsupported; exiting", arm_arch); 2334 exit(EXIT_FAILURE); 2335 } 2336 } 2337 2338 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS; 2339 2340 tcg_target_call_clobber_regs = 0; 2341 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); 2342 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1); 2343 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2); 2344 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3); 2345 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12); 2346 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14); 2347 2348 if (use_neon_instructions) { 2349 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS; 2350 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS; 2351 2352 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q0); 2353 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q1); 2354 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q2); 2355 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q3); 2356 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q8); 2357 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q9); 2358 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q10); 2359 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q11); 2360 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q12); 2361 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q13); 2362 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q14); 2363 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q15); 2364 } 2365 2366 s->reserved_regs = 0; 2367 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); 2368 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP); 2369 tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC); 2370 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP); 2371} 2372 2373static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 2374 TCGReg arg1, intptr_t arg2) 2375{ 2376 switch (type) { 2377 case TCG_TYPE_I32: 2378 tcg_out_ld32u(s, COND_AL, arg, arg1, arg2); 2379 return; 2380 case TCG_TYPE_V64: 2381 /* regs 1; size 8; align 8 */ 2382 tcg_out_vldst(s, INSN_VLD1 | 0x7d0, arg, arg1, arg2); 2383 return; 2384 case TCG_TYPE_V128: 2385 /* 2386 * We have only 8-byte alignment for the stack per the ABI. 2387 * Rather than dynamically re-align the stack, it's easier 2388 * to simply not request alignment beyond that. So: 2389 * regs 2; size 8; align 8 2390 */ 2391 tcg_out_vldst(s, INSN_VLD1 | 0xad0, arg, arg1, arg2); 2392 return; 2393 default: 2394 g_assert_not_reached(); 2395 } 2396} 2397 2398static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 2399 TCGReg arg1, intptr_t arg2) 2400{ 2401 switch (type) { 2402 case TCG_TYPE_I32: 2403 tcg_out_st32(s, COND_AL, arg, arg1, arg2); 2404 return; 2405 case TCG_TYPE_V64: 2406 /* regs 1; size 8; align 8 */ 2407 tcg_out_vldst(s, INSN_VST1 | 0x7d0, arg, arg1, arg2); 2408 return; 2409 case TCG_TYPE_V128: 2410 /* See tcg_out_ld re alignment: regs 2; size 8; align 8 */ 2411 tcg_out_vldst(s, INSN_VST1 | 0xad0, arg, arg1, arg2); 2412 return; 2413 default: 2414 g_assert_not_reached(); 2415 } 2416} 2417 2418static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 2419 TCGReg base, intptr_t ofs) 2420{ 2421 return false; 2422} 2423 2424static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 2425{ 2426 if (ret == arg) { 2427 return true; 2428 } 2429 switch (type) { 2430 case TCG_TYPE_I32: 2431 if (ret < TCG_REG_Q0 && arg < TCG_REG_Q0) { 2432 tcg_out_mov_reg(s, COND_AL, ret, arg); 2433 return true; 2434 } 2435 return false; 2436 2437 case TCG_TYPE_V64: 2438 case TCG_TYPE_V128: 2439 /* "VMOV D,N" is an alias for "VORR D,N,N". */ 2440 tcg_out_vreg3(s, INSN_VORR, type - TCG_TYPE_V64, 0, ret, arg, arg); 2441 return true; 2442 2443 default: 2444 g_assert_not_reached(); 2445 } 2446} 2447 2448static void tcg_out_movi(TCGContext *s, TCGType type, 2449 TCGReg ret, tcg_target_long arg) 2450{ 2451 tcg_debug_assert(type == TCG_TYPE_I32); 2452 tcg_debug_assert(ret < TCG_REG_Q0); 2453 tcg_out_movi32(s, COND_AL, ret, arg); 2454} 2455 2456static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 2457{ 2458 return false; 2459} 2460 2461static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 2462 tcg_target_long imm) 2463{ 2464 int enc, opc = ARITH_ADD; 2465 2466 /* All of the easiest immediates to encode are positive. */ 2467 if (imm < 0) { 2468 imm = -imm; 2469 opc = ARITH_SUB; 2470 } 2471 enc = encode_imm(imm); 2472 if (enc >= 0) { 2473 tcg_out_dat_imm(s, COND_AL, opc, rd, rs, enc); 2474 } else { 2475 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, imm); 2476 tcg_out_dat_reg(s, COND_AL, opc, rd, rs, 2477 TCG_REG_TMP, SHIFT_IMM_LSL(0)); 2478 } 2479} 2480 2481/* Type is always V128, with I64 elements. */ 2482static void tcg_out_dup2_vec(TCGContext *s, TCGReg rd, TCGReg rl, TCGReg rh) 2483{ 2484 /* Move high element into place first. */ 2485 /* VMOV Dd+1, Ds */ 2486 tcg_out_vreg3(s, INSN_VORR | (1 << 12), 0, 0, rd, rh, rh); 2487 /* Move low element into place; tcg_out_mov will check for nop. */ 2488 tcg_out_mov(s, TCG_TYPE_V64, rd, rl); 2489} 2490 2491static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 2492 TCGReg rd, TCGReg rs) 2493{ 2494 int q = type - TCG_TYPE_V64; 2495 2496 if (vece == MO_64) { 2497 if (type == TCG_TYPE_V128) { 2498 tcg_out_dup2_vec(s, rd, rs, rs); 2499 } else { 2500 tcg_out_mov(s, TCG_TYPE_V64, rd, rs); 2501 } 2502 } else if (rs < TCG_REG_Q0) { 2503 int b = (vece == MO_8); 2504 int e = (vece == MO_16); 2505 tcg_out32(s, INSN_VDUP_G | (b << 22) | (q << 21) | (e << 5) | 2506 encode_vn(rd) | (rs << 12)); 2507 } else { 2508 int imm4 = 1 << vece; 2509 tcg_out32(s, INSN_VDUP_S | (imm4 << 16) | (q << 6) | 2510 encode_vd(rd) | encode_vm(rs)); 2511 } 2512 return true; 2513} 2514 2515static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 2516 TCGReg rd, TCGReg base, intptr_t offset) 2517{ 2518 if (vece == MO_64) { 2519 tcg_out_ld(s, TCG_TYPE_V64, rd, base, offset); 2520 if (type == TCG_TYPE_V128) { 2521 tcg_out_dup2_vec(s, rd, rd, rd); 2522 } 2523 } else { 2524 int q = type - TCG_TYPE_V64; 2525 tcg_out_vldst(s, INSN_VLD1R | (vece << 6) | (q << 5), 2526 rd, base, offset); 2527 } 2528 return true; 2529} 2530 2531static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 2532 TCGReg rd, int64_t v64) 2533{ 2534 int q = type - TCG_TYPE_V64; 2535 int cmode, imm8, i; 2536 2537 /* Test all bytes equal first. */ 2538 if (vece == MO_8) { 2539 tcg_out_vmovi(s, rd, q, 0, 0xe, v64); 2540 return; 2541 } 2542 2543 /* 2544 * Test all bytes 0x00 or 0xff second. This can match cases that 2545 * might otherwise take 2 or 3 insns for MO_16 or MO_32 below. 2546 */ 2547 for (i = imm8 = 0; i < 8; i++) { 2548 uint8_t byte = v64 >> (i * 8); 2549 if (byte == 0xff) { 2550 imm8 |= 1 << i; 2551 } else if (byte != 0) { 2552 goto fail_bytes; 2553 } 2554 } 2555 tcg_out_vmovi(s, rd, q, 1, 0xe, imm8); 2556 return; 2557 fail_bytes: 2558 2559 /* 2560 * Tests for various replications. For each element width, if we 2561 * cannot find an expansion there's no point checking a larger 2562 * width because we already know by replication it cannot match. 2563 */ 2564 if (vece == MO_16) { 2565 uint16_t v16 = v64; 2566 2567 if (is_shimm16(v16, &cmode, &imm8)) { 2568 tcg_out_vmovi(s, rd, q, 0, cmode, imm8); 2569 return; 2570 } 2571 if (is_shimm16(~v16, &cmode, &imm8)) { 2572 tcg_out_vmovi(s, rd, q, 1, cmode, imm8); 2573 return; 2574 } 2575 2576 /* 2577 * Otherwise, all remaining constants can be loaded in two insns: 2578 * rd = v16 & 0xff, rd |= v16 & 0xff00. 2579 */ 2580 tcg_out_vmovi(s, rd, q, 0, 0x8, v16 & 0xff); 2581 tcg_out_vmovi(s, rd, q, 0, 0xb, v16 >> 8); /* VORRI */ 2582 return; 2583 } 2584 2585 if (vece == MO_32) { 2586 uint32_t v32 = v64; 2587 2588 if (is_shimm32(v32, &cmode, &imm8) || 2589 is_soimm32(v32, &cmode, &imm8)) { 2590 tcg_out_vmovi(s, rd, q, 0, cmode, imm8); 2591 return; 2592 } 2593 if (is_shimm32(~v32, &cmode, &imm8) || 2594 is_soimm32(~v32, &cmode, &imm8)) { 2595 tcg_out_vmovi(s, rd, q, 1, cmode, imm8); 2596 return; 2597 } 2598 2599 /* 2600 * Restrict the set of constants to those we can load with 2601 * two instructions. Others we load from the pool. 2602 */ 2603 i = is_shimm32_pair(v32, &cmode, &imm8); 2604 if (i) { 2605 tcg_out_vmovi(s, rd, q, 0, cmode, imm8); 2606 tcg_out_vmovi(s, rd, q, 0, i | 1, extract32(v32, i * 4, 8)); 2607 return; 2608 } 2609 i = is_shimm32_pair(~v32, &cmode, &imm8); 2610 if (i) { 2611 tcg_out_vmovi(s, rd, q, 1, cmode, imm8); 2612 tcg_out_vmovi(s, rd, q, 1, i | 1, extract32(~v32, i * 4, 8)); 2613 return; 2614 } 2615 } 2616 2617 /* 2618 * As a last resort, load from the constant pool. 2619 */ 2620 if (!q || vece == MO_64) { 2621 new_pool_l2(s, R_ARM_PC11, s->code_ptr, 0, v64, v64 >> 32); 2622 /* VLDR Dd, [pc + offset] */ 2623 tcg_out32(s, INSN_VLDR_D | encode_vd(rd) | (0xf << 16)); 2624 if (q) { 2625 tcg_out_dup2_vec(s, rd, rd, rd); 2626 } 2627 } else { 2628 new_pool_label(s, (uint32_t)v64, R_ARM_PC8, s->code_ptr, 0); 2629 /* add tmp, pc, offset */ 2630 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_TMP, TCG_REG_PC, 0); 2631 tcg_out_dupm_vec(s, type, MO_32, rd, TCG_REG_TMP, 0); 2632 } 2633} 2634 2635static const ARMInsn vec_cmp_insn[16] = { 2636 [TCG_COND_EQ] = INSN_VCEQ, 2637 [TCG_COND_GT] = INSN_VCGT, 2638 [TCG_COND_GE] = INSN_VCGE, 2639 [TCG_COND_GTU] = INSN_VCGT_U, 2640 [TCG_COND_GEU] = INSN_VCGE_U, 2641}; 2642 2643static const ARMInsn vec_cmp0_insn[16] = { 2644 [TCG_COND_EQ] = INSN_VCEQ0, 2645 [TCG_COND_GT] = INSN_VCGT0, 2646 [TCG_COND_GE] = INSN_VCGE0, 2647 [TCG_COND_LT] = INSN_VCLT0, 2648 [TCG_COND_LE] = INSN_VCLE0, 2649}; 2650 2651static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 2652 unsigned vecl, unsigned vece, 2653 const TCGArg args[TCG_MAX_OP_ARGS], 2654 const int const_args[TCG_MAX_OP_ARGS]) 2655{ 2656 TCGType type = vecl + TCG_TYPE_V64; 2657 unsigned q = vecl; 2658 TCGArg a0, a1, a2, a3; 2659 int cmode, imm8; 2660 2661 a0 = args[0]; 2662 a1 = args[1]; 2663 a2 = args[2]; 2664 2665 switch (opc) { 2666 case INDEX_op_ld_vec: 2667 tcg_out_ld(s, type, a0, a1, a2); 2668 return; 2669 case INDEX_op_st_vec: 2670 tcg_out_st(s, type, a0, a1, a2); 2671 return; 2672 case INDEX_op_dupm_vec: 2673 tcg_out_dupm_vec(s, type, vece, a0, a1, a2); 2674 return; 2675 case INDEX_op_dup2_vec: 2676 tcg_out_dup2_vec(s, a0, a1, a2); 2677 return; 2678 case INDEX_op_abs_vec: 2679 tcg_out_vreg2(s, INSN_VABS, q, vece, a0, a1); 2680 return; 2681 case INDEX_op_neg_vec: 2682 tcg_out_vreg2(s, INSN_VNEG, q, vece, a0, a1); 2683 return; 2684 case INDEX_op_not_vec: 2685 tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a1); 2686 return; 2687 case INDEX_op_add_vec: 2688 tcg_out_vreg3(s, INSN_VADD, q, vece, a0, a1, a2); 2689 return; 2690 case INDEX_op_mul_vec: 2691 tcg_out_vreg3(s, INSN_VMUL, q, vece, a0, a1, a2); 2692 return; 2693 case INDEX_op_smax_vec: 2694 tcg_out_vreg3(s, INSN_VMAX, q, vece, a0, a1, a2); 2695 return; 2696 case INDEX_op_smin_vec: 2697 tcg_out_vreg3(s, INSN_VMIN, q, vece, a0, a1, a2); 2698 return; 2699 case INDEX_op_sub_vec: 2700 tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2); 2701 return; 2702 case INDEX_op_ssadd_vec: 2703 tcg_out_vreg3(s, INSN_VQADD, q, vece, a0, a1, a2); 2704 return; 2705 case INDEX_op_sssub_vec: 2706 tcg_out_vreg3(s, INSN_VQSUB, q, vece, a0, a1, a2); 2707 return; 2708 case INDEX_op_umax_vec: 2709 tcg_out_vreg3(s, INSN_VMAX_U, q, vece, a0, a1, a2); 2710 return; 2711 case INDEX_op_umin_vec: 2712 tcg_out_vreg3(s, INSN_VMIN_U, q, vece, a0, a1, a2); 2713 return; 2714 case INDEX_op_usadd_vec: 2715 tcg_out_vreg3(s, INSN_VQADD_U, q, vece, a0, a1, a2); 2716 return; 2717 case INDEX_op_ussub_vec: 2718 tcg_out_vreg3(s, INSN_VQSUB_U, q, vece, a0, a1, a2); 2719 return; 2720 case INDEX_op_xor_vec: 2721 tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2); 2722 return; 2723 case INDEX_op_arm_sshl_vec: 2724 /* 2725 * Note that Vm is the data and Vn is the shift count, 2726 * therefore the arguments appear reversed. 2727 */ 2728 tcg_out_vreg3(s, INSN_VSHL_S, q, vece, a0, a2, a1); 2729 return; 2730 case INDEX_op_arm_ushl_vec: 2731 /* See above. */ 2732 tcg_out_vreg3(s, INSN_VSHL_U, q, vece, a0, a2, a1); 2733 return; 2734 case INDEX_op_shli_vec: 2735 tcg_out_vshifti(s, INSN_VSHLI, q, a0, a1, a2 + (8 << vece)); 2736 return; 2737 case INDEX_op_shri_vec: 2738 tcg_out_vshifti(s, INSN_VSHRI, q, a0, a1, (16 << vece) - a2); 2739 return; 2740 case INDEX_op_sari_vec: 2741 tcg_out_vshifti(s, INSN_VSARI, q, a0, a1, (16 << vece) - a2); 2742 return; 2743 case INDEX_op_arm_sli_vec: 2744 tcg_out_vshifti(s, INSN_VSLI, q, a0, a2, args[3] + (8 << vece)); 2745 return; 2746 2747 case INDEX_op_andc_vec: 2748 if (!const_args[2]) { 2749 tcg_out_vreg3(s, INSN_VBIC, q, 0, a0, a1, a2); 2750 return; 2751 } 2752 a2 = ~a2; 2753 /* fall through */ 2754 case INDEX_op_and_vec: 2755 if (const_args[2]) { 2756 is_shimm1632(~a2, &cmode, &imm8); 2757 if (a0 == a1) { 2758 tcg_out_vmovi(s, a0, q, 1, cmode | 1, imm8); /* VBICI */ 2759 return; 2760 } 2761 tcg_out_vmovi(s, a0, q, 1, cmode, imm8); /* VMVNI */ 2762 a2 = a0; 2763 } 2764 tcg_out_vreg3(s, INSN_VAND, q, 0, a0, a1, a2); 2765 return; 2766 2767 case INDEX_op_orc_vec: 2768 if (!const_args[2]) { 2769 tcg_out_vreg3(s, INSN_VORN, q, 0, a0, a1, a2); 2770 return; 2771 } 2772 a2 = ~a2; 2773 /* fall through */ 2774 case INDEX_op_or_vec: 2775 if (const_args[2]) { 2776 is_shimm1632(a2, &cmode, &imm8); 2777 if (a0 == a1) { 2778 tcg_out_vmovi(s, a0, q, 0, cmode | 1, imm8); /* VORRI */ 2779 return; 2780 } 2781 tcg_out_vmovi(s, a0, q, 0, cmode, imm8); /* VMOVI */ 2782 a2 = a0; 2783 } 2784 tcg_out_vreg3(s, INSN_VORR, q, 0, a0, a1, a2); 2785 return; 2786 2787 case INDEX_op_cmp_vec: 2788 { 2789 TCGCond cond = args[3]; 2790 ARMInsn insn; 2791 2792 switch (cond) { 2793 case TCG_COND_NE: 2794 if (const_args[2]) { 2795 tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a1); 2796 } else { 2797 tcg_out_vreg3(s, INSN_VCEQ, q, vece, a0, a1, a2); 2798 tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0); 2799 } 2800 break; 2801 2802 case TCG_COND_TSTNE: 2803 case TCG_COND_TSTEQ: 2804 if (const_args[2]) { 2805 /* (x & 0) == 0 */ 2806 tcg_out_dupi_vec(s, type, MO_8, a0, 2807 -(cond == TCG_COND_TSTEQ)); 2808 break; 2809 } 2810 tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a2); 2811 if (cond == TCG_COND_TSTEQ) { 2812 tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0); 2813 } 2814 break; 2815 2816 default: 2817 if (const_args[2]) { 2818 insn = vec_cmp0_insn[cond]; 2819 if (insn) { 2820 tcg_out_vreg2(s, insn, q, vece, a0, a1); 2821 return; 2822 } 2823 tcg_out_dupi_vec(s, type, MO_8, TCG_VEC_TMP, 0); 2824 a2 = TCG_VEC_TMP; 2825 } 2826 insn = vec_cmp_insn[cond]; 2827 if (insn == 0) { 2828 TCGArg t; 2829 t = a1, a1 = a2, a2 = t; 2830 cond = tcg_swap_cond(cond); 2831 insn = vec_cmp_insn[cond]; 2832 tcg_debug_assert(insn != 0); 2833 } 2834 tcg_out_vreg3(s, insn, q, vece, a0, a1, a2); 2835 break; 2836 } 2837 } 2838 return; 2839 2840 case INDEX_op_bitsel_vec: 2841 a3 = args[3]; 2842 if (a0 == a3) { 2843 tcg_out_vreg3(s, INSN_VBIT, q, 0, a0, a2, a1); 2844 } else if (a0 == a2) { 2845 tcg_out_vreg3(s, INSN_VBIF, q, 0, a0, a3, a1); 2846 } else { 2847 tcg_out_mov(s, type, a0, a1); 2848 tcg_out_vreg3(s, INSN_VBSL, q, 0, a0, a2, a3); 2849 } 2850 return; 2851 2852 case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ 2853 case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ 2854 default: 2855 g_assert_not_reached(); 2856 } 2857} 2858 2859int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 2860{ 2861 switch (opc) { 2862 case INDEX_op_add_vec: 2863 case INDEX_op_sub_vec: 2864 case INDEX_op_and_vec: 2865 case INDEX_op_andc_vec: 2866 case INDEX_op_or_vec: 2867 case INDEX_op_orc_vec: 2868 case INDEX_op_xor_vec: 2869 case INDEX_op_not_vec: 2870 case INDEX_op_shli_vec: 2871 case INDEX_op_shri_vec: 2872 case INDEX_op_sari_vec: 2873 case INDEX_op_ssadd_vec: 2874 case INDEX_op_sssub_vec: 2875 case INDEX_op_usadd_vec: 2876 case INDEX_op_ussub_vec: 2877 case INDEX_op_bitsel_vec: 2878 return 1; 2879 case INDEX_op_abs_vec: 2880 case INDEX_op_cmp_vec: 2881 case INDEX_op_mul_vec: 2882 case INDEX_op_neg_vec: 2883 case INDEX_op_smax_vec: 2884 case INDEX_op_smin_vec: 2885 case INDEX_op_umax_vec: 2886 case INDEX_op_umin_vec: 2887 return vece < MO_64; 2888 case INDEX_op_shlv_vec: 2889 case INDEX_op_shrv_vec: 2890 case INDEX_op_sarv_vec: 2891 case INDEX_op_rotli_vec: 2892 case INDEX_op_rotlv_vec: 2893 case INDEX_op_rotrv_vec: 2894 return -1; 2895 default: 2896 return 0; 2897 } 2898} 2899 2900void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 2901 TCGArg a0, ...) 2902{ 2903 va_list va; 2904 TCGv_vec v0, v1, v2, t1, t2, c1; 2905 TCGArg a2; 2906 2907 va_start(va, a0); 2908 v0 = temp_tcgv_vec(arg_temp(a0)); 2909 v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 2910 a2 = va_arg(va, TCGArg); 2911 va_end(va); 2912 2913 switch (opc) { 2914 case INDEX_op_shlv_vec: 2915 /* 2916 * Merely propagate shlv_vec to arm_ushl_vec. 2917 * In this way we don't set TCG_TARGET_HAS_shv_vec 2918 * because everything is done via expansion. 2919 */ 2920 v2 = temp_tcgv_vec(arg_temp(a2)); 2921 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0), 2922 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 2923 break; 2924 2925 case INDEX_op_shrv_vec: 2926 case INDEX_op_sarv_vec: 2927 /* Right shifts are negative left shifts for NEON. */ 2928 v2 = temp_tcgv_vec(arg_temp(a2)); 2929 t1 = tcg_temp_new_vec(type); 2930 tcg_gen_neg_vec(vece, t1, v2); 2931 if (opc == INDEX_op_shrv_vec) { 2932 opc = INDEX_op_arm_ushl_vec; 2933 } else { 2934 opc = INDEX_op_arm_sshl_vec; 2935 } 2936 vec_gen_3(opc, type, vece, tcgv_vec_arg(v0), 2937 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 2938 tcg_temp_free_vec(t1); 2939 break; 2940 2941 case INDEX_op_rotli_vec: 2942 t1 = tcg_temp_new_vec(type); 2943 tcg_gen_shri_vec(vece, t1, v1, -a2 & ((8 << vece) - 1)); 2944 vec_gen_4(INDEX_op_arm_sli_vec, type, vece, 2945 tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(v1), a2); 2946 tcg_temp_free_vec(t1); 2947 break; 2948 2949 case INDEX_op_rotlv_vec: 2950 v2 = temp_tcgv_vec(arg_temp(a2)); 2951 t1 = tcg_temp_new_vec(type); 2952 c1 = tcg_constant_vec(type, vece, 8 << vece); 2953 tcg_gen_sub_vec(vece, t1, v2, c1); 2954 /* Right shifts are negative left shifts for NEON. */ 2955 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1), 2956 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 2957 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0), 2958 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 2959 tcg_gen_or_vec(vece, v0, v0, t1); 2960 tcg_temp_free_vec(t1); 2961 break; 2962 2963 case INDEX_op_rotrv_vec: 2964 v2 = temp_tcgv_vec(arg_temp(a2)); 2965 t1 = tcg_temp_new_vec(type); 2966 t2 = tcg_temp_new_vec(type); 2967 c1 = tcg_constant_vec(type, vece, 8 << vece); 2968 tcg_gen_neg_vec(vece, t1, v2); 2969 tcg_gen_sub_vec(vece, t2, c1, v2); 2970 /* Right shifts are negative left shifts for NEON. */ 2971 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1), 2972 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 2973 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t2), 2974 tcgv_vec_arg(v1), tcgv_vec_arg(t2)); 2975 tcg_gen_or_vec(vece, v0, t1, t2); 2976 tcg_temp_free_vec(t1); 2977 tcg_temp_free_vec(t2); 2978 break; 2979 2980 default: 2981 g_assert_not_reached(); 2982 } 2983} 2984 2985static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 2986{ 2987 int i; 2988 for (i = 0; i < count; ++i) { 2989 p[i] = INSN_NOP; 2990 } 2991} 2992 2993/* Compute frame size via macros, to share between tcg_target_qemu_prologue 2994 and tcg_register_jit. */ 2995 2996#define PUSH_SIZE ((11 - 4 + 1 + 1) * sizeof(tcg_target_long)) 2997 2998#define FRAME_SIZE \ 2999 ((PUSH_SIZE \ 3000 + TCG_STATIC_CALL_ARGS_SIZE \ 3001 + CPU_TEMP_BUF_NLONGS * sizeof(long) \ 3002 + TCG_TARGET_STACK_ALIGN - 1) \ 3003 & -TCG_TARGET_STACK_ALIGN) 3004 3005#define STACK_ADDEND (FRAME_SIZE - PUSH_SIZE) 3006 3007static void tcg_target_qemu_prologue(TCGContext *s) 3008{ 3009 /* Calling convention requires us to save r4-r11 and lr. */ 3010 /* stmdb sp!, { r4 - r11, lr } */ 3011 tcg_out_ldstm(s, COND_AL, INSN_STMDB, TCG_REG_CALL_STACK, 3012 (1 << TCG_REG_R4) | (1 << TCG_REG_R5) | (1 << TCG_REG_R6) | 3013 (1 << TCG_REG_R7) | (1 << TCG_REG_R8) | (1 << TCG_REG_R9) | 3014 (1 << TCG_REG_R10) | (1 << TCG_REG_R11) | (1 << TCG_REG_R14)); 3015 3016 /* Reserve callee argument and tcg temp space. */ 3017 tcg_out_dat_rI(s, COND_AL, ARITH_SUB, TCG_REG_CALL_STACK, 3018 TCG_REG_CALL_STACK, STACK_ADDEND, 1); 3019 tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE, 3020 CPU_TEMP_BUF_NLONGS * sizeof(long)); 3021 3022 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 3023 3024 if (!tcg_use_softmmu && guest_base) { 3025 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_GUEST_BASE, guest_base); 3026 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GUEST_BASE); 3027 } 3028 3029 tcg_out_b_reg(s, COND_AL, tcg_target_call_iarg_regs[1]); 3030 3031 /* 3032 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 3033 * and fall through to the rest of the epilogue. 3034 */ 3035 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 3036 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, 0); 3037 tcg_out_epilogue(s); 3038} 3039 3040static void tcg_out_epilogue(TCGContext *s) 3041{ 3042 /* Release local stack frame. */ 3043 tcg_out_dat_rI(s, COND_AL, ARITH_ADD, TCG_REG_CALL_STACK, 3044 TCG_REG_CALL_STACK, STACK_ADDEND, 1); 3045 3046 /* ldmia sp!, { r4 - r11, pc } */ 3047 tcg_out_ldstm(s, COND_AL, INSN_LDMIA, TCG_REG_CALL_STACK, 3048 (1 << TCG_REG_R4) | (1 << TCG_REG_R5) | (1 << TCG_REG_R6) | 3049 (1 << TCG_REG_R7) | (1 << TCG_REG_R8) | (1 << TCG_REG_R9) | 3050 (1 << TCG_REG_R10) | (1 << TCG_REG_R11) | (1 << TCG_REG_PC)); 3051} 3052 3053static void tcg_out_tb_start(TCGContext *s) 3054{ 3055 /* nothing to do */ 3056} 3057 3058typedef struct { 3059 DebugFrameHeader h; 3060 uint8_t fde_def_cfa[4]; 3061 uint8_t fde_reg_ofs[18]; 3062} DebugFrame; 3063 3064#define ELF_HOST_MACHINE EM_ARM 3065 3066/* We're expecting a 2 byte uleb128 encoded value. */ 3067QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); 3068 3069static const DebugFrame debug_frame = { 3070 .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ 3071 .h.cie.id = -1, 3072 .h.cie.version = 1, 3073 .h.cie.code_align = 1, 3074 .h.cie.data_align = 0x7c, /* sleb128 -4 */ 3075 .h.cie.return_column = 14, 3076 3077 /* Total FDE size does not include the "len" member. */ 3078 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 3079 3080 .fde_def_cfa = { 3081 12, 13, /* DW_CFA_def_cfa sp, ... */ 3082 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 3083 (FRAME_SIZE >> 7) 3084 }, 3085 .fde_reg_ofs = { 3086 /* The following must match the stmdb in the prologue. */ 3087 0x8e, 1, /* DW_CFA_offset, lr, -4 */ 3088 0x8b, 2, /* DW_CFA_offset, r11, -8 */ 3089 0x8a, 3, /* DW_CFA_offset, r10, -12 */ 3090 0x89, 4, /* DW_CFA_offset, r9, -16 */ 3091 0x88, 5, /* DW_CFA_offset, r8, -20 */ 3092 0x87, 6, /* DW_CFA_offset, r7, -24 */ 3093 0x86, 7, /* DW_CFA_offset, r6, -28 */ 3094 0x85, 8, /* DW_CFA_offset, r5, -32 */ 3095 0x84, 9, /* DW_CFA_offset, r4, -36 */ 3096 } 3097}; 3098 3099void tcg_register_jit(const void *buf, size_t buf_size) 3100{ 3101 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 3102} 3103