1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Andrzej Zaborowski 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25#include "elf.h" 26 27int arm_arch = __ARM_ARCH; 28 29#ifndef use_idiv_instructions 30bool use_idiv_instructions; 31#endif 32#ifndef use_neon_instructions 33bool use_neon_instructions; 34#endif 35 36/* Used for function call generation. */ 37#define TCG_TARGET_STACK_ALIGN 8 38#define TCG_TARGET_CALL_STACK_OFFSET 0 39#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL 40#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN 41#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN 42#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF 43 44#ifdef CONFIG_DEBUG_TCG 45static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 46 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", 47 "%r8", "%r9", "%r10", "%r11", "%r12", "%sp", "%r14", "%pc", 48 "%q0", "%q1", "%q2", "%q3", "%q4", "%q5", "%q6", "%q7", 49 "%q8", "%q9", "%q10", "%q11", "%q12", "%q13", "%q14", "%q15", 50}; 51#endif 52 53static const int tcg_target_reg_alloc_order[] = { 54 TCG_REG_R4, 55 TCG_REG_R5, 56 TCG_REG_R6, 57 TCG_REG_R7, 58 TCG_REG_R8, 59 TCG_REG_R9, 60 TCG_REG_R10, 61 TCG_REG_R11, 62 TCG_REG_R13, 63 TCG_REG_R0, 64 TCG_REG_R1, 65 TCG_REG_R2, 66 TCG_REG_R3, 67 TCG_REG_R12, 68 TCG_REG_R14, 69 70 TCG_REG_Q0, 71 TCG_REG_Q1, 72 TCG_REG_Q2, 73 TCG_REG_Q3, 74 /* Q4 - Q7 are call-saved, and skipped. */ 75 TCG_REG_Q8, 76 TCG_REG_Q9, 77 TCG_REG_Q10, 78 TCG_REG_Q11, 79 TCG_REG_Q12, 80 TCG_REG_Q13, 81 TCG_REG_Q14, 82 TCG_REG_Q15, 83}; 84 85static const int tcg_target_call_iarg_regs[4] = { 86 TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3 87}; 88 89static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 90{ 91 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 92 tcg_debug_assert(slot >= 0 && slot <= 3); 93 return TCG_REG_R0 + slot; 94} 95 96#define TCG_REG_TMP TCG_REG_R12 97#define TCG_VEC_TMP TCG_REG_Q15 98#define TCG_REG_GUEST_BASE TCG_REG_R11 99 100typedef enum { 101 COND_EQ = 0x0, 102 COND_NE = 0x1, 103 COND_CS = 0x2, /* Unsigned greater or equal */ 104 COND_CC = 0x3, /* Unsigned less than */ 105 COND_MI = 0x4, /* Negative */ 106 COND_PL = 0x5, /* Zero or greater */ 107 COND_VS = 0x6, /* Overflow */ 108 COND_VC = 0x7, /* No overflow */ 109 COND_HI = 0x8, /* Unsigned greater than */ 110 COND_LS = 0x9, /* Unsigned less or equal */ 111 COND_GE = 0xa, 112 COND_LT = 0xb, 113 COND_GT = 0xc, 114 COND_LE = 0xd, 115 COND_AL = 0xe, 116} ARMCond; 117 118#define TO_CPSR (1 << 20) 119 120#define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00) 121#define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20) 122#define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40) 123#define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60) 124#define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10) 125#define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30) 126#define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50) 127#define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70) 128 129typedef enum { 130 ARITH_AND = 0x0 << 21, 131 ARITH_EOR = 0x1 << 21, 132 ARITH_SUB = 0x2 << 21, 133 ARITH_RSB = 0x3 << 21, 134 ARITH_ADD = 0x4 << 21, 135 ARITH_ADC = 0x5 << 21, 136 ARITH_SBC = 0x6 << 21, 137 ARITH_RSC = 0x7 << 21, 138 ARITH_TST = 0x8 << 21 | TO_CPSR, 139 ARITH_CMP = 0xa << 21 | TO_CPSR, 140 ARITH_CMN = 0xb << 21 | TO_CPSR, 141 ARITH_ORR = 0xc << 21, 142 ARITH_MOV = 0xd << 21, 143 ARITH_BIC = 0xe << 21, 144 ARITH_MVN = 0xf << 21, 145 146 INSN_B = 0x0a000000, 147 148 INSN_CLZ = 0x016f0f10, 149 INSN_RBIT = 0x06ff0f30, 150 151 INSN_LDMIA = 0x08b00000, 152 INSN_STMDB = 0x09200000, 153 154 INSN_LDR_IMM = 0x04100000, 155 INSN_LDR_REG = 0x06100000, 156 INSN_STR_IMM = 0x04000000, 157 INSN_STR_REG = 0x06000000, 158 159 INSN_LDRH_IMM = 0x005000b0, 160 INSN_LDRH_REG = 0x001000b0, 161 INSN_LDRSH_IMM = 0x005000f0, 162 INSN_LDRSH_REG = 0x001000f0, 163 INSN_STRH_IMM = 0x004000b0, 164 INSN_STRH_REG = 0x000000b0, 165 166 INSN_LDRB_IMM = 0x04500000, 167 INSN_LDRB_REG = 0x06500000, 168 INSN_LDRSB_IMM = 0x005000d0, 169 INSN_LDRSB_REG = 0x001000d0, 170 INSN_STRB_IMM = 0x04400000, 171 INSN_STRB_REG = 0x06400000, 172 173 INSN_LDRD_IMM = 0x004000d0, 174 INSN_LDRD_REG = 0x000000d0, 175 INSN_STRD_IMM = 0x004000f0, 176 INSN_STRD_REG = 0x000000f0, 177 178 INSN_DMB_ISH = 0xf57ff05b, 179 INSN_DMB_MCR = 0xee070fba, 180 181 /* Architected nop introduced in v6k. */ 182 /* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this 183 also Just So Happened to do nothing on pre-v6k so that we 184 don't need to conditionalize it? */ 185 INSN_NOP_v6k = 0xe320f000, 186 /* Otherwise the assembler uses mov r0,r0 */ 187 INSN_NOP_v4 = (COND_AL << 28) | ARITH_MOV, 188 189 INSN_VADD = 0xf2000800, 190 INSN_VAND = 0xf2000110, 191 INSN_VBIC = 0xf2100110, 192 INSN_VEOR = 0xf3000110, 193 INSN_VORN = 0xf2300110, 194 INSN_VORR = 0xf2200110, 195 INSN_VSUB = 0xf3000800, 196 INSN_VMUL = 0xf2000910, 197 INSN_VQADD = 0xf2000010, 198 INSN_VQADD_U = 0xf3000010, 199 INSN_VQSUB = 0xf2000210, 200 INSN_VQSUB_U = 0xf3000210, 201 INSN_VMAX = 0xf2000600, 202 INSN_VMAX_U = 0xf3000600, 203 INSN_VMIN = 0xf2000610, 204 INSN_VMIN_U = 0xf3000610, 205 206 INSN_VABS = 0xf3b10300, 207 INSN_VMVN = 0xf3b00580, 208 INSN_VNEG = 0xf3b10380, 209 210 INSN_VCEQ0 = 0xf3b10100, 211 INSN_VCGT0 = 0xf3b10000, 212 INSN_VCGE0 = 0xf3b10080, 213 INSN_VCLE0 = 0xf3b10180, 214 INSN_VCLT0 = 0xf3b10200, 215 216 INSN_VCEQ = 0xf3000810, 217 INSN_VCGE = 0xf2000310, 218 INSN_VCGT = 0xf2000300, 219 INSN_VCGE_U = 0xf3000310, 220 INSN_VCGT_U = 0xf3000300, 221 222 INSN_VSHLI = 0xf2800510, /* VSHL (immediate) */ 223 INSN_VSARI = 0xf2800010, /* VSHR.S */ 224 INSN_VSHRI = 0xf3800010, /* VSHR.U */ 225 INSN_VSLI = 0xf3800510, 226 INSN_VSHL_S = 0xf2000400, /* VSHL.S (register) */ 227 INSN_VSHL_U = 0xf3000400, /* VSHL.U (register) */ 228 229 INSN_VBSL = 0xf3100110, 230 INSN_VBIT = 0xf3200110, 231 INSN_VBIF = 0xf3300110, 232 233 INSN_VTST = 0xf2000810, 234 235 INSN_VDUP_G = 0xee800b10, /* VDUP (ARM core register) */ 236 INSN_VDUP_S = 0xf3b00c00, /* VDUP (scalar) */ 237 INSN_VLDR_D = 0xed100b00, /* VLDR.64 */ 238 INSN_VLD1 = 0xf4200000, /* VLD1 (multiple single elements) */ 239 INSN_VLD1R = 0xf4a00c00, /* VLD1 (single element to all lanes) */ 240 INSN_VST1 = 0xf4000000, /* VST1 (multiple single elements) */ 241 INSN_VMOVI = 0xf2800010, /* VMOV (immediate) */ 242} ARMInsn; 243 244#define INSN_NOP (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4) 245 246static const uint8_t tcg_cond_to_arm_cond[] = { 247 [TCG_COND_EQ] = COND_EQ, 248 [TCG_COND_NE] = COND_NE, 249 [TCG_COND_LT] = COND_LT, 250 [TCG_COND_GE] = COND_GE, 251 [TCG_COND_LE] = COND_LE, 252 [TCG_COND_GT] = COND_GT, 253 /* unsigned */ 254 [TCG_COND_LTU] = COND_CC, 255 [TCG_COND_GEU] = COND_CS, 256 [TCG_COND_LEU] = COND_LS, 257 [TCG_COND_GTU] = COND_HI, 258}; 259 260static int encode_imm(uint32_t imm); 261 262/* TCG private relocation type: add with pc+imm8 */ 263#define R_ARM_PC8 11 264 265/* TCG private relocation type: vldr with imm8 << 2 */ 266#define R_ARM_PC11 12 267 268static bool reloc_pc24(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 269{ 270 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 271 ptrdiff_t offset = (tcg_ptr_byte_diff(target, src_rx) - 8) >> 2; 272 273 if (offset == sextract32(offset, 0, 24)) { 274 *src_rw = deposit32(*src_rw, 0, 24, offset); 275 return true; 276 } 277 return false; 278} 279 280static bool reloc_pc13(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 281{ 282 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 283 ptrdiff_t offset = tcg_ptr_byte_diff(target, src_rx) - 8; 284 285 if (offset >= -0xfff && offset <= 0xfff) { 286 tcg_insn_unit insn = *src_rw; 287 bool u = (offset >= 0); 288 if (!u) { 289 offset = -offset; 290 } 291 insn = deposit32(insn, 23, 1, u); 292 insn = deposit32(insn, 0, 12, offset); 293 *src_rw = insn; 294 return true; 295 } 296 return false; 297} 298 299static bool reloc_pc11(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 300{ 301 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 302 ptrdiff_t offset = (tcg_ptr_byte_diff(target, src_rx) - 8) / 4; 303 304 if (offset >= -0xff && offset <= 0xff) { 305 tcg_insn_unit insn = *src_rw; 306 bool u = (offset >= 0); 307 if (!u) { 308 offset = -offset; 309 } 310 insn = deposit32(insn, 23, 1, u); 311 insn = deposit32(insn, 0, 8, offset); 312 *src_rw = insn; 313 return true; 314 } 315 return false; 316} 317 318static bool reloc_pc8(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 319{ 320 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 321 ptrdiff_t offset = tcg_ptr_byte_diff(target, src_rx) - 8; 322 int imm12 = encode_imm(offset); 323 324 if (imm12 >= 0) { 325 *src_rw = deposit32(*src_rw, 0, 12, imm12); 326 return true; 327 } 328 return false; 329} 330 331static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 332 intptr_t value, intptr_t addend) 333{ 334 tcg_debug_assert(addend == 0); 335 switch (type) { 336 case R_ARM_PC24: 337 return reloc_pc24(code_ptr, (const tcg_insn_unit *)value); 338 case R_ARM_PC13: 339 return reloc_pc13(code_ptr, (const tcg_insn_unit *)value); 340 case R_ARM_PC11: 341 return reloc_pc11(code_ptr, (const tcg_insn_unit *)value); 342 case R_ARM_PC8: 343 return reloc_pc8(code_ptr, (const tcg_insn_unit *)value); 344 default: 345 g_assert_not_reached(); 346 } 347} 348 349#define TCG_CT_CONST_ARM 0x100 350#define TCG_CT_CONST_INV 0x200 351#define TCG_CT_CONST_NEG 0x400 352#define TCG_CT_CONST_ZERO 0x800 353#define TCG_CT_CONST_ORRI 0x1000 354#define TCG_CT_CONST_ANDI 0x2000 355 356#define ALL_GENERAL_REGS 0xffffu 357#define ALL_VECTOR_REGS 0xffff0000u 358 359/* 360 * r0-r3 will be overwritten when reading the tlb entry (system-mode only); 361 * r14 will be overwritten by the BLNE branching to the slow path. 362 */ 363#define ALL_QLDST_REGS \ 364 (ALL_GENERAL_REGS & ~((tcg_use_softmmu ? 0xf : 0) | (1 << TCG_REG_R14))) 365 366/* 367 * ARM immediates for ALU instructions are made of an unsigned 8-bit 368 * right-rotated by an even amount between 0 and 30. 369 * 370 * Return < 0 if @imm cannot be encoded, else the entire imm12 field. 371 */ 372static int encode_imm(uint32_t imm) 373{ 374 uint32_t rot, imm8; 375 376 /* Simple case, no rotation required. */ 377 if ((imm & ~0xff) == 0) { 378 return imm; 379 } 380 381 /* Next, try a simple even shift. */ 382 rot = ctz32(imm) & ~1; 383 imm8 = imm >> rot; 384 rot = 32 - rot; 385 if ((imm8 & ~0xff) == 0) { 386 goto found; 387 } 388 389 /* 390 * Finally, try harder with rotations. 391 * The ctz test above will have taken care of rotates >= 8. 392 */ 393 for (rot = 2; rot < 8; rot += 2) { 394 imm8 = rol32(imm, rot); 395 if ((imm8 & ~0xff) == 0) { 396 goto found; 397 } 398 } 399 /* Fail: imm cannot be encoded. */ 400 return -1; 401 402 found: 403 /* Note that rot is even, and we discard bit 0 by shifting by 7. */ 404 return rot << 7 | imm8; 405} 406 407static int encode_imm_nofail(uint32_t imm) 408{ 409 int ret = encode_imm(imm); 410 tcg_debug_assert(ret >= 0); 411 return ret; 412} 413 414static bool check_fit_imm(uint32_t imm) 415{ 416 return encode_imm(imm) >= 0; 417} 418 419/* Return true if v16 is a valid 16-bit shifted immediate. */ 420static bool is_shimm16(uint16_t v16, int *cmode, int *imm8) 421{ 422 if (v16 == (v16 & 0xff)) { 423 *cmode = 0x8; 424 *imm8 = v16 & 0xff; 425 return true; 426 } else if (v16 == (v16 & 0xff00)) { 427 *cmode = 0xa; 428 *imm8 = v16 >> 8; 429 return true; 430 } 431 return false; 432} 433 434/* Return true if v32 is a valid 32-bit shifted immediate. */ 435static bool is_shimm32(uint32_t v32, int *cmode, int *imm8) 436{ 437 if (v32 == (v32 & 0xff)) { 438 *cmode = 0x0; 439 *imm8 = v32 & 0xff; 440 return true; 441 } else if (v32 == (v32 & 0xff00)) { 442 *cmode = 0x2; 443 *imm8 = (v32 >> 8) & 0xff; 444 return true; 445 } else if (v32 == (v32 & 0xff0000)) { 446 *cmode = 0x4; 447 *imm8 = (v32 >> 16) & 0xff; 448 return true; 449 } else if (v32 == (v32 & 0xff000000)) { 450 *cmode = 0x6; 451 *imm8 = v32 >> 24; 452 return true; 453 } 454 return false; 455} 456 457/* Return true if v32 is a valid 32-bit shifting ones immediate. */ 458static bool is_soimm32(uint32_t v32, int *cmode, int *imm8) 459{ 460 if ((v32 & 0xffff00ff) == 0xff) { 461 *cmode = 0xc; 462 *imm8 = (v32 >> 8) & 0xff; 463 return true; 464 } else if ((v32 & 0xff00ffff) == 0xffff) { 465 *cmode = 0xd; 466 *imm8 = (v32 >> 16) & 0xff; 467 return true; 468 } 469 return false; 470} 471 472/* 473 * Return non-zero if v32 can be formed by MOVI+ORR. 474 * Place the parameters for MOVI in (cmode, imm8). 475 * Return the cmode for ORR; the imm8 can be had via extraction from v32. 476 */ 477static int is_shimm32_pair(uint32_t v32, int *cmode, int *imm8) 478{ 479 int i; 480 481 for (i = 6; i > 0; i -= 2) { 482 /* Mask out one byte we can add with ORR. */ 483 uint32_t tmp = v32 & ~(0xffu << (i * 4)); 484 if (is_shimm32(tmp, cmode, imm8) || 485 is_soimm32(tmp, cmode, imm8)) { 486 break; 487 } 488 } 489 return i; 490} 491 492/* Return true if V is a valid 16-bit or 32-bit shifted immediate. */ 493static bool is_shimm1632(uint32_t v32, int *cmode, int *imm8) 494{ 495 if (v32 == deposit32(v32, 16, 16, v32)) { 496 return is_shimm16(v32, cmode, imm8); 497 } else { 498 return is_shimm32(v32, cmode, imm8); 499 } 500} 501 502/* Test if a constant matches the constraint. 503 * TODO: define constraints for: 504 * 505 * ldr/str offset: between -0xfff and 0xfff 506 * ldrh/strh offset: between -0xff and 0xff 507 * mov operand2: values represented with x << (2 * y), x < 0x100 508 * add, sub, eor...: ditto 509 */ 510static bool tcg_target_const_match(int64_t val, int ct, 511 TCGType type, TCGCond cond, int vece) 512{ 513 if (ct & TCG_CT_CONST) { 514 return 1; 515 } else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val)) { 516 return 1; 517 } else if ((ct & TCG_CT_CONST_INV) && check_fit_imm(~val)) { 518 return 1; 519 } else if ((ct & TCG_CT_CONST_NEG) && check_fit_imm(-val)) { 520 return 1; 521 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 522 return 1; 523 } 524 525 switch (ct & (TCG_CT_CONST_ORRI | TCG_CT_CONST_ANDI)) { 526 case 0: 527 break; 528 case TCG_CT_CONST_ANDI: 529 val = ~val; 530 /* fallthru */ 531 case TCG_CT_CONST_ORRI: 532 if (val == deposit64(val, 32, 32, val)) { 533 int cmode, imm8; 534 return is_shimm1632(val, &cmode, &imm8); 535 } 536 break; 537 default: 538 /* Both bits should not be set for the same insn. */ 539 g_assert_not_reached(); 540 } 541 542 return 0; 543} 544 545static void tcg_out_b_imm(TCGContext *s, ARMCond cond, int32_t offset) 546{ 547 tcg_out32(s, (cond << 28) | INSN_B | 548 (((offset - 8) >> 2) & 0x00ffffff)); 549} 550 551static void tcg_out_bl_imm(TCGContext *s, ARMCond cond, int32_t offset) 552{ 553 tcg_out32(s, (cond << 28) | 0x0b000000 | 554 (((offset - 8) >> 2) & 0x00ffffff)); 555} 556 557static void tcg_out_blx_reg(TCGContext *s, ARMCond cond, TCGReg rn) 558{ 559 tcg_out32(s, (cond << 28) | 0x012fff30 | rn); 560} 561 562static void tcg_out_blx_imm(TCGContext *s, int32_t offset) 563{ 564 tcg_out32(s, 0xfa000000 | ((offset & 2) << 23) | 565 (((offset - 8) >> 2) & 0x00ffffff)); 566} 567 568static void tcg_out_dat_reg(TCGContext *s, ARMCond cond, ARMInsn opc, 569 TCGReg rd, TCGReg rn, TCGReg rm, int shift) 570{ 571 tcg_out32(s, (cond << 28) | (0 << 25) | opc | 572 (rn << 16) | (rd << 12) | shift | rm); 573} 574 575static void tcg_out_mov_reg(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rm) 576{ 577 /* Simple reg-reg move, optimising out the 'do nothing' case */ 578 if (rd != rm) { 579 tcg_out_dat_reg(s, cond, ARITH_MOV, rd, 0, rm, SHIFT_IMM_LSL(0)); 580 } 581} 582 583static void tcg_out_bx_reg(TCGContext *s, ARMCond cond, TCGReg rn) 584{ 585 tcg_out32(s, (cond << 28) | 0x012fff10 | rn); 586} 587 588static void tcg_out_b_reg(TCGContext *s, ARMCond cond, TCGReg rn) 589{ 590 /* 591 * Unless the C portion of QEMU is compiled as thumb, we don't need 592 * true BX semantics; merely a branch to an address held in a register. 593 */ 594 tcg_out_bx_reg(s, cond, rn); 595} 596 597static void tcg_out_dat_imm(TCGContext *s, ARMCond cond, ARMInsn opc, 598 TCGReg rd, TCGReg rn, int im) 599{ 600 tcg_out32(s, (cond << 28) | (1 << 25) | opc | 601 (rn << 16) | (rd << 12) | im); 602} 603 604static void tcg_out_ldstm(TCGContext *s, ARMCond cond, ARMInsn opc, 605 TCGReg rn, uint16_t mask) 606{ 607 tcg_out32(s, (cond << 28) | opc | (rn << 16) | mask); 608} 609 610/* Note that this routine is used for both LDR and LDRH formats, so we do 611 not wish to include an immediate shift at this point. */ 612static void tcg_out_memop_r(TCGContext *s, ARMCond cond, ARMInsn opc, TCGReg rt, 613 TCGReg rn, TCGReg rm, bool u, bool p, bool w) 614{ 615 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) 616 | (w << 21) | (rn << 16) | (rt << 12) | rm); 617} 618 619static void tcg_out_memop_8(TCGContext *s, ARMCond cond, ARMInsn opc, TCGReg rt, 620 TCGReg rn, int imm8, bool p, bool w) 621{ 622 bool u = 1; 623 if (imm8 < 0) { 624 imm8 = -imm8; 625 u = 0; 626 } 627 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | 628 (rn << 16) | (rt << 12) | ((imm8 & 0xf0) << 4) | (imm8 & 0xf)); 629} 630 631static void tcg_out_memop_12(TCGContext *s, ARMCond cond, ARMInsn opc, 632 TCGReg rt, TCGReg rn, int imm12, bool p, bool w) 633{ 634 bool u = 1; 635 if (imm12 < 0) { 636 imm12 = -imm12; 637 u = 0; 638 } 639 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | 640 (rn << 16) | (rt << 12) | imm12); 641} 642 643static void tcg_out_ld32_12(TCGContext *s, ARMCond cond, TCGReg rt, 644 TCGReg rn, int imm12) 645{ 646 tcg_out_memop_12(s, cond, INSN_LDR_IMM, rt, rn, imm12, 1, 0); 647} 648 649static void tcg_out_st32_12(TCGContext *s, ARMCond cond, TCGReg rt, 650 TCGReg rn, int imm12) 651{ 652 tcg_out_memop_12(s, cond, INSN_STR_IMM, rt, rn, imm12, 1, 0); 653} 654 655static void tcg_out_ld32_r(TCGContext *s, ARMCond cond, TCGReg rt, 656 TCGReg rn, TCGReg rm) 657{ 658 tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 0); 659} 660 661static void tcg_out_st32_r(TCGContext *s, ARMCond cond, TCGReg rt, 662 TCGReg rn, TCGReg rm) 663{ 664 tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 0); 665} 666 667static void tcg_out_ldrd_8(TCGContext *s, ARMCond cond, TCGReg rt, 668 TCGReg rn, int imm8) 669{ 670 tcg_out_memop_8(s, cond, INSN_LDRD_IMM, rt, rn, imm8, 1, 0); 671} 672 673static void tcg_out_ldrd_r(TCGContext *s, ARMCond cond, TCGReg rt, 674 TCGReg rn, TCGReg rm) 675{ 676 tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 0); 677} 678 679static void tcg_out_strd_8(TCGContext *s, ARMCond cond, TCGReg rt, 680 TCGReg rn, int imm8) 681{ 682 tcg_out_memop_8(s, cond, INSN_STRD_IMM, rt, rn, imm8, 1, 0); 683} 684 685static void tcg_out_strd_r(TCGContext *s, ARMCond cond, TCGReg rt, 686 TCGReg rn, TCGReg rm) 687{ 688 tcg_out_memop_r(s, cond, INSN_STRD_REG, rt, rn, rm, 1, 1, 0); 689} 690 691/* Register pre-increment with base writeback. */ 692static void tcg_out_ld32_rwb(TCGContext *s, ARMCond cond, TCGReg rt, 693 TCGReg rn, TCGReg rm) 694{ 695 tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 1); 696} 697 698static void tcg_out_st32_rwb(TCGContext *s, ARMCond cond, TCGReg rt, 699 TCGReg rn, TCGReg rm) 700{ 701 tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 1); 702} 703 704static void tcg_out_ld16u_8(TCGContext *s, ARMCond cond, TCGReg rt, 705 TCGReg rn, int imm8) 706{ 707 tcg_out_memop_8(s, cond, INSN_LDRH_IMM, rt, rn, imm8, 1, 0); 708} 709 710static void tcg_out_st16_8(TCGContext *s, ARMCond cond, TCGReg rt, 711 TCGReg rn, int imm8) 712{ 713 tcg_out_memop_8(s, cond, INSN_STRH_IMM, rt, rn, imm8, 1, 0); 714} 715 716static void tcg_out_ld16u_r(TCGContext *s, ARMCond cond, TCGReg rt, 717 TCGReg rn, TCGReg rm) 718{ 719 tcg_out_memop_r(s, cond, INSN_LDRH_REG, rt, rn, rm, 1, 1, 0); 720} 721 722static void tcg_out_st16_r(TCGContext *s, ARMCond cond, TCGReg rt, 723 TCGReg rn, TCGReg rm) 724{ 725 tcg_out_memop_r(s, cond, INSN_STRH_REG, rt, rn, rm, 1, 1, 0); 726} 727 728static void tcg_out_ld16s_8(TCGContext *s, ARMCond cond, TCGReg rt, 729 TCGReg rn, int imm8) 730{ 731 tcg_out_memop_8(s, cond, INSN_LDRSH_IMM, rt, rn, imm8, 1, 0); 732} 733 734static void tcg_out_ld16s_r(TCGContext *s, ARMCond cond, TCGReg rt, 735 TCGReg rn, TCGReg rm) 736{ 737 tcg_out_memop_r(s, cond, INSN_LDRSH_REG, rt, rn, rm, 1, 1, 0); 738} 739 740static void tcg_out_ld8_12(TCGContext *s, ARMCond cond, TCGReg rt, 741 TCGReg rn, int imm12) 742{ 743 tcg_out_memop_12(s, cond, INSN_LDRB_IMM, rt, rn, imm12, 1, 0); 744} 745 746static void tcg_out_st8_12(TCGContext *s, ARMCond cond, TCGReg rt, 747 TCGReg rn, int imm12) 748{ 749 tcg_out_memop_12(s, cond, INSN_STRB_IMM, rt, rn, imm12, 1, 0); 750} 751 752static void tcg_out_ld8_r(TCGContext *s, ARMCond cond, TCGReg rt, 753 TCGReg rn, TCGReg rm) 754{ 755 tcg_out_memop_r(s, cond, INSN_LDRB_REG, rt, rn, rm, 1, 1, 0); 756} 757 758static void tcg_out_st8_r(TCGContext *s, ARMCond cond, TCGReg rt, 759 TCGReg rn, TCGReg rm) 760{ 761 tcg_out_memop_r(s, cond, INSN_STRB_REG, rt, rn, rm, 1, 1, 0); 762} 763 764static void tcg_out_ld8s_8(TCGContext *s, ARMCond cond, TCGReg rt, 765 TCGReg rn, int imm8) 766{ 767 tcg_out_memop_8(s, cond, INSN_LDRSB_IMM, rt, rn, imm8, 1, 0); 768} 769 770static void tcg_out_ld8s_r(TCGContext *s, ARMCond cond, TCGReg rt, 771 TCGReg rn, TCGReg rm) 772{ 773 tcg_out_memop_r(s, cond, INSN_LDRSB_REG, rt, rn, rm, 1, 1, 0); 774} 775 776static void tcg_out_movi_pool(TCGContext *s, ARMCond cond, 777 TCGReg rd, uint32_t arg) 778{ 779 new_pool_label(s, arg, R_ARM_PC13, s->code_ptr, 0); 780 tcg_out_ld32_12(s, cond, rd, TCG_REG_PC, 0); 781} 782 783static void tcg_out_movi32(TCGContext *s, ARMCond cond, 784 TCGReg rd, uint32_t arg) 785{ 786 int imm12, diff, opc, sh1, sh2; 787 uint32_t tt0, tt1, tt2; 788 789 /* Check a single MOV/MVN before anything else. */ 790 imm12 = encode_imm(arg); 791 if (imm12 >= 0) { 792 tcg_out_dat_imm(s, cond, ARITH_MOV, rd, 0, imm12); 793 return; 794 } 795 imm12 = encode_imm(~arg); 796 if (imm12 >= 0) { 797 tcg_out_dat_imm(s, cond, ARITH_MVN, rd, 0, imm12); 798 return; 799 } 800 801 /* Check for a pc-relative address. This will usually be the TB, 802 or within the TB, which is immediately before the code block. */ 803 diff = tcg_pcrel_diff(s, (void *)arg) - 8; 804 if (diff >= 0) { 805 imm12 = encode_imm(diff); 806 if (imm12 >= 0) { 807 tcg_out_dat_imm(s, cond, ARITH_ADD, rd, TCG_REG_PC, imm12); 808 return; 809 } 810 } else { 811 imm12 = encode_imm(-diff); 812 if (imm12 >= 0) { 813 tcg_out_dat_imm(s, cond, ARITH_SUB, rd, TCG_REG_PC, imm12); 814 return; 815 } 816 } 817 818 /* Use movw + movt. */ 819 if (use_armv7_instructions) { 820 /* movw */ 821 tcg_out32(s, (cond << 28) | 0x03000000 | (rd << 12) 822 | ((arg << 4) & 0x000f0000) | (arg & 0xfff)); 823 if (arg & 0xffff0000) { 824 /* movt */ 825 tcg_out32(s, (cond << 28) | 0x03400000 | (rd << 12) 826 | ((arg >> 12) & 0x000f0000) | ((arg >> 16) & 0xfff)); 827 } 828 return; 829 } 830 831 /* Look for sequences of two insns. If we have lots of 1's, we can 832 shorten the sequence by beginning with mvn and then clearing 833 higher bits with eor. */ 834 tt0 = arg; 835 opc = ARITH_MOV; 836 if (ctpop32(arg) > 16) { 837 tt0 = ~arg; 838 opc = ARITH_MVN; 839 } 840 sh1 = ctz32(tt0) & ~1; 841 tt1 = tt0 & ~(0xff << sh1); 842 sh2 = ctz32(tt1) & ~1; 843 tt2 = tt1 & ~(0xff << sh2); 844 if (tt2 == 0) { 845 int rot; 846 847 rot = ((32 - sh1) << 7) & 0xf00; 848 tcg_out_dat_imm(s, cond, opc, rd, 0, ((tt0 >> sh1) & 0xff) | rot); 849 rot = ((32 - sh2) << 7) & 0xf00; 850 tcg_out_dat_imm(s, cond, ARITH_EOR, rd, rd, 851 ((tt0 >> sh2) & 0xff) | rot); 852 return; 853 } 854 855 /* Otherwise, drop it into the constant pool. */ 856 tcg_out_movi_pool(s, cond, rd, arg); 857} 858 859/* 860 * Emit either the reg,imm or reg,reg form of a data-processing insn. 861 * rhs must satisfy the "rI" constraint. 862 */ 863static void tcg_out_dat_rI(TCGContext *s, ARMCond cond, ARMInsn opc, 864 TCGReg dst, TCGReg lhs, TCGArg rhs, int rhs_is_const) 865{ 866 if (rhs_is_const) { 867 tcg_out_dat_imm(s, cond, opc, dst, lhs, encode_imm_nofail(rhs)); 868 } else { 869 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); 870 } 871} 872 873/* 874 * Emit either the reg,imm or reg,reg form of a data-processing insn. 875 * rhs must satisfy the "rIK" constraint. 876 */ 877static void tcg_out_dat_IK(TCGContext *s, ARMCond cond, ARMInsn opc, 878 ARMInsn opinv, TCGReg dst, TCGReg lhs, TCGArg rhs) 879{ 880 int imm12 = encode_imm(rhs); 881 if (imm12 < 0) { 882 imm12 = encode_imm_nofail(~rhs); 883 opc = opinv; 884 } 885 tcg_out_dat_imm(s, cond, opc, dst, lhs, imm12); 886} 887 888static void tcg_out_dat_rIK(TCGContext *s, ARMCond cond, ARMInsn opc, 889 ARMInsn opinv, TCGReg dst, TCGReg lhs, TCGArg rhs, 890 bool rhs_is_const) 891{ 892 if (rhs_is_const) { 893 tcg_out_dat_IK(s, cond, opc, opinv, dst, lhs, rhs); 894 } else { 895 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); 896 } 897} 898 899static void tcg_out_dat_IN(TCGContext *s, ARMCond cond, ARMInsn opc, 900 ARMInsn opneg, TCGReg dst, TCGReg lhs, TCGArg rhs) 901{ 902 int imm12 = encode_imm(rhs); 903 if (imm12 < 0) { 904 imm12 = encode_imm_nofail(-rhs); 905 opc = opneg; 906 } 907 tcg_out_dat_imm(s, cond, opc, dst, lhs, imm12); 908} 909 910static void tcg_out_dat_rIN(TCGContext *s, ARMCond cond, ARMInsn opc, 911 ARMInsn opneg, TCGReg dst, TCGReg lhs, TCGArg rhs, 912 bool rhs_is_const) 913{ 914 /* Emit either the reg,imm or reg,reg form of a data-processing insn. 915 * rhs must satisfy the "rIN" constraint. 916 */ 917 if (rhs_is_const) { 918 tcg_out_dat_IN(s, cond, opc, opneg, dst, lhs, rhs); 919 } else { 920 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); 921 } 922} 923 924static void tcg_out_ext8s(TCGContext *s, TCGType t, TCGReg rd, TCGReg rn) 925{ 926 /* sxtb */ 927 tcg_out32(s, 0x06af0070 | (COND_AL << 28) | (rd << 12) | rn); 928} 929 930static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rn) 931{ 932 tcg_out_dat_imm(s, COND_AL, ARITH_AND, rd, rn, 0xff); 933} 934 935static void tcg_out_ext16s(TCGContext *s, TCGType t, TCGReg rd, TCGReg rn) 936{ 937 /* sxth */ 938 tcg_out32(s, 0x06bf0070 | (COND_AL << 28) | (rd << 12) | rn); 939} 940 941static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rn) 942{ 943 /* uxth */ 944 tcg_out32(s, 0x06ff0070 | (COND_AL << 28) | (rd << 12) | rn); 945} 946 947static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rn) 948{ 949 g_assert_not_reached(); 950} 951 952static void tcg_out_ext32u(TCGContext *s, TCGReg rd, TCGReg rn) 953{ 954 g_assert_not_reached(); 955} 956 957static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rn) 958{ 959 g_assert_not_reached(); 960} 961 962static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rn) 963{ 964 g_assert_not_reached(); 965} 966 967static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rn) 968{ 969 g_assert_not_reached(); 970} 971 972static void tcg_out_deposit(TCGContext *s, ARMCond cond, TCGReg rd, 973 TCGArg a1, int ofs, int len, bool const_a1) 974{ 975 if (const_a1) { 976 /* bfi becomes bfc with rn == 15. */ 977 a1 = 15; 978 } 979 /* bfi/bfc */ 980 tcg_out32(s, 0x07c00010 | (cond << 28) | (rd << 12) | a1 981 | (ofs << 7) | ((ofs + len - 1) << 16)); 982} 983 984static void tcg_out_extract(TCGContext *s, ARMCond cond, TCGReg rd, 985 TCGReg rn, int ofs, int len) 986{ 987 /* According to gcc, AND can be faster. */ 988 if (ofs == 0 && len <= 8) { 989 tcg_out_dat_imm(s, cond, ARITH_AND, rd, rn, 990 encode_imm_nofail((1 << len) - 1)); 991 return; 992 } 993 994 if (use_armv7_instructions) { 995 /* ubfx */ 996 tcg_out32(s, 0x07e00050 | (cond << 28) | (rd << 12) | rn 997 | (ofs << 7) | ((len - 1) << 16)); 998 return; 999 } 1000 1001 assert(ofs % 8 == 0); 1002 switch (len) { 1003 case 8: 1004 /* uxtb */ 1005 tcg_out32(s, 0x06ef0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn); 1006 break; 1007 case 16: 1008 /* uxth */ 1009 tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn); 1010 break; 1011 default: 1012 g_assert_not_reached(); 1013 } 1014} 1015 1016static void tcg_out_sextract(TCGContext *s, ARMCond cond, TCGReg rd, 1017 TCGReg rn, int ofs, int len) 1018{ 1019 if (use_armv7_instructions) { 1020 /* sbfx */ 1021 tcg_out32(s, 0x07a00050 | (cond << 28) | (rd << 12) | rn 1022 | (ofs << 7) | ((len - 1) << 16)); 1023 return; 1024 } 1025 1026 assert(ofs % 8 == 0); 1027 switch (len) { 1028 case 8: 1029 /* sxtb */ 1030 tcg_out32(s, 0x06af0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn); 1031 break; 1032 case 16: 1033 /* sxth */ 1034 tcg_out32(s, 0x06bf0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn); 1035 break; 1036 default: 1037 g_assert_not_reached(); 1038 } 1039} 1040 1041 1042static void tcg_out_ld32u(TCGContext *s, ARMCond cond, 1043 TCGReg rd, TCGReg rn, int32_t offset) 1044{ 1045 if (offset > 0xfff || offset < -0xfff) { 1046 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1047 tcg_out_ld32_r(s, cond, rd, rn, TCG_REG_TMP); 1048 } else 1049 tcg_out_ld32_12(s, cond, rd, rn, offset); 1050} 1051 1052static void tcg_out_st32(TCGContext *s, ARMCond cond, 1053 TCGReg rd, TCGReg rn, int32_t offset) 1054{ 1055 if (offset > 0xfff || offset < -0xfff) { 1056 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1057 tcg_out_st32_r(s, cond, rd, rn, TCG_REG_TMP); 1058 } else 1059 tcg_out_st32_12(s, cond, rd, rn, offset); 1060} 1061 1062static void tcg_out_ld16u(TCGContext *s, ARMCond cond, 1063 TCGReg rd, TCGReg rn, int32_t offset) 1064{ 1065 if (offset > 0xff || offset < -0xff) { 1066 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1067 tcg_out_ld16u_r(s, cond, rd, rn, TCG_REG_TMP); 1068 } else 1069 tcg_out_ld16u_8(s, cond, rd, rn, offset); 1070} 1071 1072static void tcg_out_ld16s(TCGContext *s, ARMCond cond, 1073 TCGReg rd, TCGReg rn, int32_t offset) 1074{ 1075 if (offset > 0xff || offset < -0xff) { 1076 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1077 tcg_out_ld16s_r(s, cond, rd, rn, TCG_REG_TMP); 1078 } else 1079 tcg_out_ld16s_8(s, cond, rd, rn, offset); 1080} 1081 1082static void tcg_out_st16(TCGContext *s, ARMCond cond, 1083 TCGReg rd, TCGReg rn, int32_t offset) 1084{ 1085 if (offset > 0xff || offset < -0xff) { 1086 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1087 tcg_out_st16_r(s, cond, rd, rn, TCG_REG_TMP); 1088 } else 1089 tcg_out_st16_8(s, cond, rd, rn, offset); 1090} 1091 1092static void tcg_out_ld8u(TCGContext *s, ARMCond cond, 1093 TCGReg rd, TCGReg rn, int32_t offset) 1094{ 1095 if (offset > 0xfff || offset < -0xfff) { 1096 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1097 tcg_out_ld8_r(s, cond, rd, rn, TCG_REG_TMP); 1098 } else 1099 tcg_out_ld8_12(s, cond, rd, rn, offset); 1100} 1101 1102static void tcg_out_ld8s(TCGContext *s, ARMCond cond, 1103 TCGReg rd, TCGReg rn, int32_t offset) 1104{ 1105 if (offset > 0xff || offset < -0xff) { 1106 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1107 tcg_out_ld8s_r(s, cond, rd, rn, TCG_REG_TMP); 1108 } else 1109 tcg_out_ld8s_8(s, cond, rd, rn, offset); 1110} 1111 1112static void tcg_out_st8(TCGContext *s, ARMCond cond, 1113 TCGReg rd, TCGReg rn, int32_t offset) 1114{ 1115 if (offset > 0xfff || offset < -0xfff) { 1116 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1117 tcg_out_st8_r(s, cond, rd, rn, TCG_REG_TMP); 1118 } else 1119 tcg_out_st8_12(s, cond, rd, rn, offset); 1120} 1121 1122/* 1123 * The _goto case is normally between TBs within the same code buffer, and 1124 * with the code buffer limited to 16MB we wouldn't need the long case. 1125 * But we also use it for the tail-call to the qemu_ld/st helpers, which does. 1126 */ 1127static void tcg_out_goto(TCGContext *s, ARMCond cond, const tcg_insn_unit *addr) 1128{ 1129 intptr_t addri = (intptr_t)addr; 1130 ptrdiff_t disp = tcg_pcrel_diff(s, addr); 1131 bool arm_mode = !(addri & 1); 1132 1133 if (arm_mode && disp - 8 < 0x01fffffd && disp - 8 > -0x01fffffd) { 1134 tcg_out_b_imm(s, cond, disp); 1135 return; 1136 } 1137 1138 /* LDR is interworking from v5t. */ 1139 tcg_out_movi_pool(s, cond, TCG_REG_PC, addri); 1140} 1141 1142/* 1143 * The call case is mostly used for helpers - so it's not unreasonable 1144 * for them to be beyond branch range. 1145 */ 1146static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *addr) 1147{ 1148 intptr_t addri = (intptr_t)addr; 1149 ptrdiff_t disp = tcg_pcrel_diff(s, addr); 1150 bool arm_mode = !(addri & 1); 1151 1152 if (disp - 8 < 0x02000000 && disp - 8 >= -0x02000000) { 1153 if (arm_mode) { 1154 tcg_out_bl_imm(s, COND_AL, disp); 1155 } else { 1156 tcg_out_blx_imm(s, disp); 1157 } 1158 return; 1159 } 1160 1161 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri); 1162 tcg_out_blx_reg(s, COND_AL, TCG_REG_TMP); 1163} 1164 1165static void tcg_out_call(TCGContext *s, const tcg_insn_unit *addr, 1166 const TCGHelperInfo *info) 1167{ 1168 tcg_out_call_int(s, addr); 1169} 1170 1171static void tcg_out_goto_label(TCGContext *s, ARMCond cond, TCGLabel *l) 1172{ 1173 if (l->has_value) { 1174 tcg_out_goto(s, cond, l->u.value_ptr); 1175 } else { 1176 tcg_out_reloc(s, s->code_ptr, R_ARM_PC24, l, 0); 1177 tcg_out_b_imm(s, cond, 0); 1178 } 1179} 1180 1181static void tcg_out_mb(TCGContext *s, TCGArg a0) 1182{ 1183 if (use_armv7_instructions) { 1184 tcg_out32(s, INSN_DMB_ISH); 1185 } else { 1186 tcg_out32(s, INSN_DMB_MCR); 1187 } 1188} 1189 1190static TCGCond tgen_cmp(TCGContext *s, TCGCond cond, TCGReg a, TCGReg b) 1191{ 1192 if (is_tst_cond(cond)) { 1193 tcg_out_dat_reg(s, COND_AL, ARITH_TST, 0, a, b, SHIFT_IMM_LSL(0)); 1194 return tcg_tst_eqne_cond(cond); 1195 } 1196 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, a, b, SHIFT_IMM_LSL(0)); 1197 return cond; 1198} 1199 1200static TCGCond tgen_cmpi(TCGContext *s, TCGCond cond, TCGReg a, TCGArg b) 1201{ 1202 int imm12; 1203 1204 if (!is_tst_cond(cond)) { 1205 tcg_out_dat_IN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, a, b); 1206 return cond; 1207 } 1208 1209 /* 1210 * The compare constraints allow rIN, but TST does not support N. 1211 * Be prepared to load the constant into a scratch register. 1212 */ 1213 imm12 = encode_imm(b); 1214 if (imm12 >= 0) { 1215 tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, a, imm12); 1216 } else { 1217 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, b); 1218 tcg_out_dat_reg(s, COND_AL, ARITH_TST, 0, 1219 a, TCG_REG_TMP, SHIFT_IMM_LSL(0)); 1220 } 1221 return tcg_tst_eqne_cond(cond); 1222} 1223 1224static TCGCond tcg_out_cmp(TCGContext *s, TCGCond cond, TCGReg a, 1225 TCGArg b, int b_const) 1226{ 1227 if (b_const) { 1228 return tgen_cmpi(s, cond, a, b); 1229 } else { 1230 return tgen_cmp(s, cond, a, b); 1231 } 1232} 1233 1234static TCGCond tcg_out_cmp2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, 1235 TCGArg bl, bool const_bl, TCGArg bh, bool const_bh) 1236{ 1237 switch (cond) { 1238 case TCG_COND_EQ: 1239 case TCG_COND_NE: 1240 case TCG_COND_LTU: 1241 case TCG_COND_LEU: 1242 case TCG_COND_GTU: 1243 case TCG_COND_GEU: 1244 /* 1245 * We perform a conditional comparison. If the high half is 1246 * equal, then overwrite the flags with the comparison of the 1247 * low half. The resulting flags cover the whole. 1248 */ 1249 tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, ah, bh, const_bh); 1250 tcg_out_dat_rI(s, COND_EQ, ARITH_CMP, 0, al, bl, const_bl); 1251 return cond; 1252 1253 case TCG_COND_TSTEQ: 1254 case TCG_COND_TSTNE: 1255 /* Similar, but with TST instead of CMP. */ 1256 tcg_out_dat_rI(s, COND_AL, ARITH_TST, 0, ah, bh, const_bh); 1257 tcg_out_dat_rI(s, COND_EQ, ARITH_TST, 0, al, bl, const_bl); 1258 return tcg_tst_eqne_cond(cond); 1259 1260 case TCG_COND_LT: 1261 case TCG_COND_GE: 1262 /* We perform a double-word subtraction and examine the result. 1263 We do not actually need the result of the subtract, so the 1264 low part "subtract" is a compare. For the high half we have 1265 no choice but to compute into a temporary. */ 1266 tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, al, bl, const_bl); 1267 tcg_out_dat_rI(s, COND_AL, ARITH_SBC | TO_CPSR, 1268 TCG_REG_TMP, ah, bh, const_bh); 1269 return cond; 1270 1271 case TCG_COND_LE: 1272 case TCG_COND_GT: 1273 /* Similar, but with swapped arguments, via reversed subtract. */ 1274 tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR, 1275 TCG_REG_TMP, al, bl, const_bl); 1276 tcg_out_dat_rI(s, COND_AL, ARITH_RSC | TO_CPSR, 1277 TCG_REG_TMP, ah, bh, const_bh); 1278 return tcg_swap_cond(cond); 1279 1280 default: 1281 g_assert_not_reached(); 1282 } 1283} 1284 1285/* 1286 * Note that TCGReg references Q-registers. 1287 * Q-regno = 2 * D-regno, so shift left by 1 while inserting. 1288 */ 1289static uint32_t encode_vd(TCGReg rd) 1290{ 1291 tcg_debug_assert(rd >= TCG_REG_Q0); 1292 return (extract32(rd, 3, 1) << 22) | (extract32(rd, 0, 3) << 13); 1293} 1294 1295static uint32_t encode_vn(TCGReg rn) 1296{ 1297 tcg_debug_assert(rn >= TCG_REG_Q0); 1298 return (extract32(rn, 3, 1) << 7) | (extract32(rn, 0, 3) << 17); 1299} 1300 1301static uint32_t encode_vm(TCGReg rm) 1302{ 1303 tcg_debug_assert(rm >= TCG_REG_Q0); 1304 return (extract32(rm, 3, 1) << 5) | (extract32(rm, 0, 3) << 1); 1305} 1306 1307static void tcg_out_vreg2(TCGContext *s, ARMInsn insn, int q, int vece, 1308 TCGReg d, TCGReg m) 1309{ 1310 tcg_out32(s, insn | (vece << 18) | (q << 6) | 1311 encode_vd(d) | encode_vm(m)); 1312} 1313 1314static void tcg_out_vreg3(TCGContext *s, ARMInsn insn, int q, int vece, 1315 TCGReg d, TCGReg n, TCGReg m) 1316{ 1317 tcg_out32(s, insn | (vece << 20) | (q << 6) | 1318 encode_vd(d) | encode_vn(n) | encode_vm(m)); 1319} 1320 1321static void tcg_out_vmovi(TCGContext *s, TCGReg rd, 1322 int q, int op, int cmode, uint8_t imm8) 1323{ 1324 tcg_out32(s, INSN_VMOVI | encode_vd(rd) | (q << 6) | (op << 5) 1325 | (cmode << 8) | extract32(imm8, 0, 4) 1326 | (extract32(imm8, 4, 3) << 16) 1327 | (extract32(imm8, 7, 1) << 24)); 1328} 1329 1330static void tcg_out_vshifti(TCGContext *s, ARMInsn insn, int q, 1331 TCGReg rd, TCGReg rm, int l_imm6) 1332{ 1333 tcg_out32(s, insn | (q << 6) | encode_vd(rd) | encode_vm(rm) | 1334 (extract32(l_imm6, 6, 1) << 7) | 1335 (extract32(l_imm6, 0, 6) << 16)); 1336} 1337 1338static void tcg_out_vldst(TCGContext *s, ARMInsn insn, 1339 TCGReg rd, TCGReg rn, int offset) 1340{ 1341 if (offset != 0) { 1342 if (check_fit_imm(offset) || check_fit_imm(-offset)) { 1343 tcg_out_dat_rIN(s, COND_AL, ARITH_ADD, ARITH_SUB, 1344 TCG_REG_TMP, rn, offset, true); 1345 } else { 1346 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, offset); 1347 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, 1348 TCG_REG_TMP, TCG_REG_TMP, rn, 0); 1349 } 1350 rn = TCG_REG_TMP; 1351 } 1352 tcg_out32(s, insn | (rn << 16) | encode_vd(rd) | 0xf); 1353} 1354 1355typedef struct { 1356 ARMCond cond; 1357 TCGReg base; 1358 int index; 1359 bool index_scratch; 1360 TCGAtomAlign aa; 1361} HostAddress; 1362 1363bool tcg_target_has_memory_bswap(MemOp memop) 1364{ 1365 return false; 1366} 1367 1368static TCGReg ldst_ra_gen(TCGContext *s, const TCGLabelQemuLdst *l, int arg) 1369{ 1370 /* We arrive at the slow path via "BLNE", so R14 contains l->raddr. */ 1371 return TCG_REG_R14; 1372} 1373 1374static const TCGLdstHelperParam ldst_helper_param = { 1375 .ra_gen = ldst_ra_gen, 1376 .ntmp = 1, 1377 .tmp = { TCG_REG_TMP }, 1378}; 1379 1380static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1381{ 1382 MemOp opc = get_memop(lb->oi); 1383 1384 if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1385 return false; 1386 } 1387 1388 tcg_out_ld_helper_args(s, lb, &ldst_helper_param); 1389 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE]); 1390 tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param); 1391 1392 tcg_out_goto(s, COND_AL, lb->raddr); 1393 return true; 1394} 1395 1396static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1397{ 1398 MemOp opc = get_memop(lb->oi); 1399 1400 if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1401 return false; 1402 } 1403 1404 tcg_out_st_helper_args(s, lb, &ldst_helper_param); 1405 1406 /* Tail-call to the helper, which will return to the fast path. */ 1407 tcg_out_goto(s, COND_AL, qemu_st_helpers[opc & MO_SIZE]); 1408 return true; 1409} 1410 1411/* We expect to use an 9-bit sign-magnitude negative offset from ENV. */ 1412#define MIN_TLB_MASK_TABLE_OFS -256 1413 1414static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1415 TCGReg addr, MemOpIdx oi, bool is_ld) 1416{ 1417 TCGLabelQemuLdst *ldst = NULL; 1418 MemOp opc = get_memop(oi); 1419 unsigned a_mask; 1420 1421 if (tcg_use_softmmu) { 1422 *h = (HostAddress){ 1423 .cond = COND_AL, 1424 .base = addr, 1425 .index = TCG_REG_R1, 1426 .index_scratch = true, 1427 }; 1428 } else { 1429 *h = (HostAddress){ 1430 .cond = COND_AL, 1431 .base = addr, 1432 .index = guest_base ? TCG_REG_GUEST_BASE : -1, 1433 .index_scratch = false, 1434 }; 1435 } 1436 1437 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); 1438 a_mask = (1 << h->aa.align) - 1; 1439 1440 if (tcg_use_softmmu) { 1441 int mem_index = get_mmuidx(oi); 1442 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read) 1443 : offsetof(CPUTLBEntry, addr_write); 1444 int fast_off = tlb_mask_table_ofs(s, mem_index); 1445 unsigned s_mask = (1 << (opc & MO_SIZE)) - 1; 1446 TCGReg t_addr; 1447 1448 ldst = new_ldst_label(s); 1449 ldst->is_ld = is_ld; 1450 ldst->oi = oi; 1451 ldst->addr_reg = addr; 1452 1453 /* Load cpu->neg.tlb.f[mmu_idx].{mask,table} into {r0,r1}. */ 1454 QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0); 1455 QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != 4); 1456 tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off); 1457 1458 /* Extract the tlb index from the address into R0. */ 1459 tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, addr, 1460 SHIFT_IMM_LSR(s->page_bits - CPU_TLB_ENTRY_BITS)); 1461 1462 /* 1463 * Add the tlb_table pointer, creating the CPUTLBEntry address in R1. 1464 * Load the tlb comparator into R2 and the fast path addend into R1. 1465 */ 1466 if (cmp_off == 0) { 1467 tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0); 1468 } else { 1469 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, 1470 TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0); 1471 tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); 1472 } 1473 1474 /* Load the tlb addend. */ 1475 tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R1, 1476 offsetof(CPUTLBEntry, addend)); 1477 1478 /* 1479 * Check alignment, check comparators. 1480 * Do this in 2-4 insns. Use MOVW for v7, if possible, 1481 * to reduce the number of sequential conditional instructions. 1482 * Almost all guests have at least 4k pages, which means that we need 1483 * to clear at least 9 bits even for an 8-byte memory, which means it 1484 * isn't worth checking for an immediate operand for BIC. 1485 * 1486 * For unaligned accesses, test the page of the last unit of alignment. 1487 * This leaves the least significant alignment bits unchanged, and of 1488 * course must be zero. 1489 */ 1490 t_addr = addr; 1491 if (a_mask < s_mask) { 1492 t_addr = TCG_REG_R0; 1493 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, t_addr, 1494 addr, s_mask - a_mask); 1495 } 1496 if (use_armv7_instructions && s->page_bits <= 16) { 1497 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, ~(s->page_mask | a_mask)); 1498 tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP, 1499 t_addr, TCG_REG_TMP, 0); 1500 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, 1501 TCG_REG_R2, TCG_REG_TMP, 0); 1502 } else { 1503 if (a_mask) { 1504 tcg_debug_assert(a_mask <= 0xff); 1505 tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addr, a_mask); 1506 } 1507 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, t_addr, 1508 SHIFT_IMM_LSR(s->page_bits)); 1509 tcg_out_dat_reg(s, (a_mask ? COND_EQ : COND_AL), ARITH_CMP, 1510 0, TCG_REG_R2, TCG_REG_TMP, 1511 SHIFT_IMM_LSL(s->page_bits)); 1512 } 1513 } else if (a_mask) { 1514 ldst = new_ldst_label(s); 1515 ldst->is_ld = is_ld; 1516 ldst->oi = oi; 1517 ldst->addr_reg = addr; 1518 1519 /* We are expecting alignment to max out at 7 */ 1520 tcg_debug_assert(a_mask <= 0xff); 1521 /* tst addr, #mask */ 1522 tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addr, a_mask); 1523 } 1524 1525 return ldst; 1526} 1527 1528static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo, 1529 TCGReg datahi, HostAddress h) 1530{ 1531 TCGReg base; 1532 1533 /* Byte swapping is left to middle-end expansion. */ 1534 tcg_debug_assert((opc & MO_BSWAP) == 0); 1535 1536 switch (opc & MO_SSIZE) { 1537 case MO_UB: 1538 if (h.index < 0) { 1539 tcg_out_ld8_12(s, h.cond, datalo, h.base, 0); 1540 } else { 1541 tcg_out_ld8_r(s, h.cond, datalo, h.base, h.index); 1542 } 1543 break; 1544 case MO_SB: 1545 if (h.index < 0) { 1546 tcg_out_ld8s_8(s, h.cond, datalo, h.base, 0); 1547 } else { 1548 tcg_out_ld8s_r(s, h.cond, datalo, h.base, h.index); 1549 } 1550 break; 1551 case MO_UW: 1552 if (h.index < 0) { 1553 tcg_out_ld16u_8(s, h.cond, datalo, h.base, 0); 1554 } else { 1555 tcg_out_ld16u_r(s, h.cond, datalo, h.base, h.index); 1556 } 1557 break; 1558 case MO_SW: 1559 if (h.index < 0) { 1560 tcg_out_ld16s_8(s, h.cond, datalo, h.base, 0); 1561 } else { 1562 tcg_out_ld16s_r(s, h.cond, datalo, h.base, h.index); 1563 } 1564 break; 1565 case MO_UL: 1566 if (h.index < 0) { 1567 tcg_out_ld32_12(s, h.cond, datalo, h.base, 0); 1568 } else { 1569 tcg_out_ld32_r(s, h.cond, datalo, h.base, h.index); 1570 } 1571 break; 1572 case MO_UQ: 1573 /* We used pair allocation for datalo, so already should be aligned. */ 1574 tcg_debug_assert((datalo & 1) == 0); 1575 tcg_debug_assert(datahi == datalo + 1); 1576 /* LDRD requires alignment; double-check that. */ 1577 if (memop_alignment_bits(opc) >= MO_64) { 1578 if (h.index < 0) { 1579 tcg_out_ldrd_8(s, h.cond, datalo, h.base, 0); 1580 break; 1581 } 1582 /* 1583 * Rm (the second address op) must not overlap Rt or Rt + 1. 1584 * Since datalo is aligned, we can simplify the test via alignment. 1585 * Flip the two address arguments if that works. 1586 */ 1587 if ((h.index & ~1) != datalo) { 1588 tcg_out_ldrd_r(s, h.cond, datalo, h.base, h.index); 1589 break; 1590 } 1591 if ((h.base & ~1) != datalo) { 1592 tcg_out_ldrd_r(s, h.cond, datalo, h.index, h.base); 1593 break; 1594 } 1595 } 1596 if (h.index < 0) { 1597 base = h.base; 1598 if (datalo == h.base) { 1599 tcg_out_mov_reg(s, h.cond, TCG_REG_TMP, base); 1600 base = TCG_REG_TMP; 1601 } 1602 } else if (h.index_scratch) { 1603 tcg_out_ld32_rwb(s, h.cond, datalo, h.index, h.base); 1604 tcg_out_ld32_12(s, h.cond, datahi, h.index, 4); 1605 break; 1606 } else { 1607 tcg_out_dat_reg(s, h.cond, ARITH_ADD, TCG_REG_TMP, 1608 h.base, h.index, SHIFT_IMM_LSL(0)); 1609 base = TCG_REG_TMP; 1610 } 1611 tcg_out_ld32_12(s, h.cond, datalo, base, 0); 1612 tcg_out_ld32_12(s, h.cond, datahi, base, 4); 1613 break; 1614 default: 1615 g_assert_not_reached(); 1616 } 1617} 1618 1619static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, 1620 TCGReg addr, MemOpIdx oi, TCGType data_type) 1621{ 1622 MemOp opc = get_memop(oi); 1623 TCGLabelQemuLdst *ldst; 1624 HostAddress h; 1625 1626 ldst = prepare_host_addr(s, &h, addr, oi, true); 1627 if (ldst) { 1628 ldst->type = data_type; 1629 ldst->datalo_reg = datalo; 1630 ldst->datahi_reg = datahi; 1631 1632 /* 1633 * This a conditional BL only to load a pointer within this 1634 * opcode into LR for the slow path. We will not be using 1635 * the value for a tail call. 1636 */ 1637 ldst->label_ptr[0] = s->code_ptr; 1638 tcg_out_bl_imm(s, COND_NE, 0); 1639 1640 tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); 1641 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1642 } else { 1643 tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); 1644 } 1645} 1646 1647static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo, 1648 TCGReg datahi, HostAddress h) 1649{ 1650 /* Byte swapping is left to middle-end expansion. */ 1651 tcg_debug_assert((opc & MO_BSWAP) == 0); 1652 1653 switch (opc & MO_SIZE) { 1654 case MO_8: 1655 if (h.index < 0) { 1656 tcg_out_st8_12(s, h.cond, datalo, h.base, 0); 1657 } else { 1658 tcg_out_st8_r(s, h.cond, datalo, h.base, h.index); 1659 } 1660 break; 1661 case MO_16: 1662 if (h.index < 0) { 1663 tcg_out_st16_8(s, h.cond, datalo, h.base, 0); 1664 } else { 1665 tcg_out_st16_r(s, h.cond, datalo, h.base, h.index); 1666 } 1667 break; 1668 case MO_32: 1669 if (h.index < 0) { 1670 tcg_out_st32_12(s, h.cond, datalo, h.base, 0); 1671 } else { 1672 tcg_out_st32_r(s, h.cond, datalo, h.base, h.index); 1673 } 1674 break; 1675 case MO_64: 1676 /* We used pair allocation for datalo, so already should be aligned. */ 1677 tcg_debug_assert((datalo & 1) == 0); 1678 tcg_debug_assert(datahi == datalo + 1); 1679 /* STRD requires alignment; double-check that. */ 1680 if (memop_alignment_bits(opc) >= MO_64) { 1681 if (h.index < 0) { 1682 tcg_out_strd_8(s, h.cond, datalo, h.base, 0); 1683 } else { 1684 tcg_out_strd_r(s, h.cond, datalo, h.base, h.index); 1685 } 1686 } else if (h.index < 0) { 1687 tcg_out_st32_12(s, h.cond, datalo, h.base, 0); 1688 tcg_out_st32_12(s, h.cond, datahi, h.base, 4); 1689 } else if (h.index_scratch) { 1690 tcg_out_st32_rwb(s, h.cond, datalo, h.index, h.base); 1691 tcg_out_st32_12(s, h.cond, datahi, h.index, 4); 1692 } else { 1693 tcg_out_dat_reg(s, h.cond, ARITH_ADD, TCG_REG_TMP, 1694 h.base, h.index, SHIFT_IMM_LSL(0)); 1695 tcg_out_st32_12(s, h.cond, datalo, TCG_REG_TMP, 0); 1696 tcg_out_st32_12(s, h.cond, datahi, TCG_REG_TMP, 4); 1697 } 1698 break; 1699 default: 1700 g_assert_not_reached(); 1701 } 1702} 1703 1704static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, 1705 TCGReg addr, MemOpIdx oi, TCGType data_type) 1706{ 1707 MemOp opc = get_memop(oi); 1708 TCGLabelQemuLdst *ldst; 1709 HostAddress h; 1710 1711 ldst = prepare_host_addr(s, &h, addr, oi, false); 1712 if (ldst) { 1713 ldst->type = data_type; 1714 ldst->datalo_reg = datalo; 1715 ldst->datahi_reg = datahi; 1716 1717 h.cond = COND_EQ; 1718 tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); 1719 1720 /* The conditional call is last, as we're going to return here. */ 1721 ldst->label_ptr[0] = s->code_ptr; 1722 tcg_out_bl_imm(s, COND_NE, 0); 1723 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1724 } else { 1725 tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); 1726 } 1727} 1728 1729static void tcg_out_epilogue(TCGContext *s); 1730 1731static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg) 1732{ 1733 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, arg); 1734 tcg_out_epilogue(s); 1735} 1736 1737static void tcg_out_goto_tb(TCGContext *s, int which) 1738{ 1739 uintptr_t i_addr; 1740 intptr_t i_disp; 1741 1742 /* Direct branch will be patched by tb_target_set_jmp_target. */ 1743 set_jmp_insn_offset(s, which); 1744 tcg_out32(s, INSN_NOP); 1745 1746 /* When branch is out of range, fall through to indirect. */ 1747 i_addr = get_jmp_target_addr(s, which); 1748 i_disp = tcg_pcrel_diff(s, (void *)i_addr) - 8; 1749 tcg_debug_assert(i_disp < 0); 1750 if (i_disp >= -0xfff) { 1751 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, i_disp); 1752 } else { 1753 /* 1754 * The TB is close, but outside the 12 bits addressable by 1755 * the load. We can extend this to 20 bits with a sub of a 1756 * shifted immediate from pc. 1757 */ 1758 int h = -i_disp; 1759 int l = -(h & 0xfff); 1760 1761 h = encode_imm_nofail(h + l); 1762 tcg_out_dat_imm(s, COND_AL, ARITH_SUB, TCG_REG_R0, TCG_REG_PC, h); 1763 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_R0, l); 1764 } 1765 set_jmp_reset_offset(s, which); 1766} 1767 1768void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1769 uintptr_t jmp_rx, uintptr_t jmp_rw) 1770{ 1771 uintptr_t addr = tb->jmp_target_addr[n]; 1772 ptrdiff_t offset = addr - (jmp_rx + 8); 1773 tcg_insn_unit insn; 1774 1775 /* Either directly branch, or fall through to indirect branch. */ 1776 if (offset == sextract64(offset, 0, 26)) { 1777 /* B <addr> */ 1778 insn = deposit32((COND_AL << 28) | INSN_B, 0, 24, offset >> 2); 1779 } else { 1780 insn = INSN_NOP; 1781 } 1782 1783 qatomic_set((uint32_t *)jmp_rw, insn); 1784 flush_idcache_range(jmp_rx, jmp_rw, 4); 1785} 1786 1787 1788static void tgen_add(TCGContext *s, TCGType type, 1789 TCGReg a0, TCGReg a1, TCGReg a2) 1790{ 1791 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, a0, a1, a2, SHIFT_IMM_LSL(0)); 1792} 1793 1794static void tgen_addi(TCGContext *s, TCGType type, 1795 TCGReg a0, TCGReg a1, tcg_target_long a2) 1796{ 1797 tcg_out_dat_IN(s, COND_AL, ARITH_ADD, ARITH_SUB, a0, a1, a2); 1798} 1799 1800static const TCGOutOpBinary outop_add = { 1801 .base.static_constraint = C_O1_I2(r, r, rIN), 1802 .out_rrr = tgen_add, 1803 .out_rri = tgen_addi, 1804}; 1805 1806static void tgen_and(TCGContext *s, TCGType type, 1807 TCGReg a0, TCGReg a1, TCGReg a2) 1808{ 1809 tcg_out_dat_reg(s, COND_AL, ARITH_AND, a0, a1, a2, SHIFT_IMM_LSL(0)); 1810} 1811 1812static void tgen_andi(TCGContext *s, TCGType type, 1813 TCGReg a0, TCGReg a1, tcg_target_long a2) 1814{ 1815 tcg_out_dat_IK(s, COND_AL, ARITH_AND, ARITH_BIC, a0, a1, a2); 1816} 1817 1818static const TCGOutOpBinary outop_and = { 1819 .base.static_constraint = C_O1_I2(r, r, rIK), 1820 .out_rrr = tgen_and, 1821 .out_rri = tgen_andi, 1822}; 1823 1824static void tgen_andc(TCGContext *s, TCGType type, 1825 TCGReg a0, TCGReg a1, TCGReg a2) 1826{ 1827 tcg_out_dat_reg(s, COND_AL, ARITH_BIC, a0, a1, a2, SHIFT_IMM_LSL(0)); 1828} 1829 1830static const TCGOutOpBinary outop_andc = { 1831 .base.static_constraint = C_O1_I2(r, r, r), 1832 .out_rrr = tgen_andc, 1833}; 1834 1835static void tgen_clz(TCGContext *s, TCGType type, 1836 TCGReg a0, TCGReg a1, TCGReg a2) 1837{ 1838 tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0, a1, 0); 1839 tcg_out_dat_reg(s, COND_NE, INSN_CLZ, a0, 0, a1, 0); 1840 tcg_out_mov_reg(s, COND_EQ, a0, a2); 1841} 1842 1843static void tgen_clzi(TCGContext *s, TCGType type, 1844 TCGReg a0, TCGReg a1, tcg_target_long a2) 1845{ 1846 if (a2 == 32) { 1847 tcg_out_dat_reg(s, COND_AL, INSN_CLZ, a0, 0, a1, 0); 1848 } else { 1849 tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0, a1, 0); 1850 tcg_out_dat_reg(s, COND_NE, INSN_CLZ, a0, 0, a1, 0); 1851 tcg_out_movi32(s, COND_EQ, a0, a2); 1852 } 1853} 1854 1855static const TCGOutOpBinary outop_clz = { 1856 .base.static_constraint = C_O1_I2(r, r, rIK), 1857 .out_rrr = tgen_clz, 1858 .out_rri = tgen_clzi, 1859}; 1860 1861static const TCGOutOpUnary outop_ctpop = { 1862 .base.static_constraint = C_NotImplemented, 1863}; 1864 1865static void tgen_ctz(TCGContext *s, TCGType type, 1866 TCGReg a0, TCGReg a1, TCGReg a2) 1867{ 1868 tcg_out_dat_reg(s, COND_AL, INSN_RBIT, TCG_REG_TMP, 0, a1, 0); 1869 tgen_clz(s, TCG_TYPE_I32, a0, TCG_REG_TMP, a2); 1870} 1871 1872static void tgen_ctzi(TCGContext *s, TCGType type, 1873 TCGReg a0, TCGReg a1, tcg_target_long a2) 1874{ 1875 tcg_out_dat_reg(s, COND_AL, INSN_RBIT, TCG_REG_TMP, 0, a1, 0); 1876 tgen_clzi(s, TCG_TYPE_I32, a0, TCG_REG_TMP, a2); 1877} 1878 1879static TCGConstraintSetIndex cset_ctz(TCGType type, unsigned flags) 1880{ 1881 return use_armv7_instructions ? C_O1_I2(r, r, rIK) : C_NotImplemented; 1882} 1883 1884static const TCGOutOpBinary outop_ctz = { 1885 .base.static_constraint = C_Dynamic, 1886 .base.dynamic_constraint = cset_ctz, 1887 .out_rrr = tgen_ctz, 1888 .out_rri = tgen_ctzi, 1889}; 1890 1891static TCGConstraintSetIndex cset_idiv(TCGType type, unsigned flags) 1892{ 1893 return use_idiv_instructions ? C_O1_I2(r, r, r) : C_NotImplemented; 1894} 1895 1896static void tgen_divs(TCGContext *s, TCGType type, 1897 TCGReg a0, TCGReg a1, TCGReg a2) 1898{ 1899 /* sdiv */ 1900 tcg_out32(s, 0x0710f010 | (COND_AL << 28) | (a0 << 16) | a1 | (a2 << 8)); 1901} 1902 1903static const TCGOutOpBinary outop_divs = { 1904 .base.static_constraint = C_Dynamic, 1905 .base.dynamic_constraint = cset_idiv, 1906 .out_rrr = tgen_divs, 1907}; 1908 1909static const TCGOutOpDivRem outop_divs2 = { 1910 .base.static_constraint = C_NotImplemented, 1911}; 1912 1913static void tgen_divu(TCGContext *s, TCGType type, 1914 TCGReg a0, TCGReg a1, TCGReg a2) 1915{ 1916 /* udiv */ 1917 tcg_out32(s, 0x0730f010 | (COND_AL << 28) | (a0 << 16) | a1 | (a2 << 8)); 1918} 1919 1920static const TCGOutOpBinary outop_divu = { 1921 .base.static_constraint = C_Dynamic, 1922 .base.dynamic_constraint = cset_idiv, 1923 .out_rrr = tgen_divu, 1924}; 1925 1926static const TCGOutOpDivRem outop_divu2 = { 1927 .base.static_constraint = C_NotImplemented, 1928}; 1929 1930static const TCGOutOpBinary outop_eqv = { 1931 .base.static_constraint = C_NotImplemented, 1932}; 1933 1934static void tgen_mul(TCGContext *s, TCGType type, 1935 TCGReg a0, TCGReg a1, TCGReg a2) 1936{ 1937 /* mul */ 1938 tcg_out32(s, (COND_AL << 28) | 0x90 | (a0 << 16) | (a1 << 8) | a2); 1939} 1940 1941static const TCGOutOpBinary outop_mul = { 1942 .base.static_constraint = C_O1_I2(r, r, r), 1943 .out_rrr = tgen_mul, 1944}; 1945 1946static void tgen_muls2(TCGContext *s, TCGType type, 1947 TCGReg rd0, TCGReg rd1, TCGReg rn, TCGReg rm) 1948{ 1949 /* smull */ 1950 tcg_out32(s, (COND_AL << 28) | 0x00c00090 | 1951 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); 1952} 1953 1954static const TCGOutOpMul2 outop_muls2 = { 1955 .base.static_constraint = C_O2_I2(r, r, r, r), 1956 .out_rrrr = tgen_muls2, 1957}; 1958 1959static const TCGOutOpBinary outop_mulsh = { 1960 .base.static_constraint = C_NotImplemented, 1961}; 1962 1963static void tgen_mulu2(TCGContext *s, TCGType type, 1964 TCGReg rd0, TCGReg rd1, TCGReg rn, TCGReg rm) 1965{ 1966 /* umull */ 1967 tcg_out32(s, (COND_AL << 28) | 0x00800090 | 1968 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); 1969} 1970 1971static const TCGOutOpMul2 outop_mulu2 = { 1972 .base.static_constraint = C_O2_I2(r, r, r, r), 1973 .out_rrrr = tgen_mulu2, 1974}; 1975 1976static const TCGOutOpBinary outop_muluh = { 1977 .base.static_constraint = C_NotImplemented, 1978}; 1979 1980static const TCGOutOpBinary outop_nand = { 1981 .base.static_constraint = C_NotImplemented, 1982}; 1983 1984static const TCGOutOpBinary outop_nor = { 1985 .base.static_constraint = C_NotImplemented, 1986}; 1987 1988static void tgen_or(TCGContext *s, TCGType type, 1989 TCGReg a0, TCGReg a1, TCGReg a2) 1990{ 1991 tcg_out_dat_reg(s, COND_AL, ARITH_ORR, a0, a1, a2, SHIFT_IMM_LSL(0)); 1992} 1993 1994static void tgen_ori(TCGContext *s, TCGType type, 1995 TCGReg a0, TCGReg a1, tcg_target_long a2) 1996{ 1997 tcg_out_dat_imm(s, COND_AL, ARITH_ORR, a0, a1, encode_imm_nofail(a2)); 1998} 1999 2000static const TCGOutOpBinary outop_or = { 2001 .base.static_constraint = C_O1_I2(r, r, rI), 2002 .out_rrr = tgen_or, 2003 .out_rri = tgen_ori, 2004}; 2005 2006static const TCGOutOpBinary outop_orc = { 2007 .base.static_constraint = C_NotImplemented, 2008}; 2009 2010static const TCGOutOpBinary outop_rems = { 2011 .base.static_constraint = C_NotImplemented, 2012}; 2013 2014static const TCGOutOpBinary outop_remu = { 2015 .base.static_constraint = C_NotImplemented, 2016}; 2017 2018static const TCGOutOpBinary outop_rotl = { 2019 .base.static_constraint = C_NotImplemented, 2020}; 2021 2022static void tgen_rotr(TCGContext *s, TCGType type, 2023 TCGReg a0, TCGReg a1, TCGReg a2) 2024{ 2025 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, SHIFT_REG_ROR(a2)); 2026} 2027 2028static void tgen_rotri(TCGContext *s, TCGType type, 2029 TCGReg a0, TCGReg a1, tcg_target_long a2) 2030{ 2031 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, SHIFT_IMM_ROR(a2 & 0x1f)); 2032} 2033 2034static const TCGOutOpBinary outop_rotr = { 2035 .base.static_constraint = C_O1_I2(r, r, ri), 2036 .out_rrr = tgen_rotr, 2037 .out_rri = tgen_rotri, 2038}; 2039 2040static void tgen_sar(TCGContext *s, TCGType type, 2041 TCGReg a0, TCGReg a1, TCGReg a2) 2042{ 2043 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, SHIFT_REG_ASR(a2)); 2044} 2045 2046static void tgen_sari(TCGContext *s, TCGType type, 2047 TCGReg a0, TCGReg a1, tcg_target_long a2) 2048{ 2049 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, 2050 SHIFT_IMM_ASR(a2 & 0x1f)); 2051} 2052 2053static const TCGOutOpBinary outop_sar = { 2054 .base.static_constraint = C_O1_I2(r, r, ri), 2055 .out_rrr = tgen_sar, 2056 .out_rri = tgen_sari, 2057}; 2058 2059static void tgen_shl(TCGContext *s, TCGType type, 2060 TCGReg a0, TCGReg a1, TCGReg a2) 2061{ 2062 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, SHIFT_REG_LSL(a2)); 2063} 2064 2065static void tgen_shli(TCGContext *s, TCGType type, 2066 TCGReg a0, TCGReg a1, tcg_target_long a2) 2067{ 2068 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, 2069 SHIFT_IMM_LSL(a2 & 0x1f)); 2070} 2071 2072static const TCGOutOpBinary outop_shl = { 2073 .base.static_constraint = C_O1_I2(r, r, ri), 2074 .out_rrr = tgen_shl, 2075 .out_rri = tgen_shli, 2076}; 2077 2078static void tgen_shr(TCGContext *s, TCGType type, 2079 TCGReg a0, TCGReg a1, TCGReg a2) 2080{ 2081 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, SHIFT_REG_LSR(a2)); 2082} 2083 2084static void tgen_shri(TCGContext *s, TCGType type, 2085 TCGReg a0, TCGReg a1, tcg_target_long a2) 2086{ 2087 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, 2088 SHIFT_IMM_LSR(a2 & 0x1f)); 2089} 2090 2091static const TCGOutOpBinary outop_shr = { 2092 .base.static_constraint = C_O1_I2(r, r, ri), 2093 .out_rrr = tgen_shr, 2094 .out_rri = tgen_shri, 2095}; 2096 2097static void tgen_sub(TCGContext *s, TCGType type, 2098 TCGReg a0, TCGReg a1, TCGReg a2) 2099{ 2100 tcg_out_dat_reg(s, COND_AL, ARITH_SUB, a0, a1, a2, SHIFT_IMM_LSL(0)); 2101} 2102 2103static void tgen_subfi(TCGContext *s, TCGType type, 2104 TCGReg a0, tcg_target_long a1, TCGReg a2) 2105{ 2106 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, a0, a2, encode_imm_nofail(a1)); 2107} 2108 2109static const TCGOutOpSubtract outop_sub = { 2110 .base.static_constraint = C_O1_I2(r, rI, r), 2111 .out_rrr = tgen_sub, 2112 .out_rir = tgen_subfi, 2113}; 2114 2115static void tgen_xor(TCGContext *s, TCGType type, 2116 TCGReg a0, TCGReg a1, TCGReg a2) 2117{ 2118 tcg_out_dat_reg(s, COND_AL, ARITH_EOR, a0, a1, a2, SHIFT_IMM_LSL(0)); 2119} 2120 2121static void tgen_xori(TCGContext *s, TCGType type, 2122 TCGReg a0, TCGReg a1, tcg_target_long a2) 2123{ 2124 tcg_out_dat_imm(s, COND_AL, ARITH_EOR, a0, a1, encode_imm_nofail(a2)); 2125} 2126 2127static const TCGOutOpBinary outop_xor = { 2128 .base.static_constraint = C_O1_I2(r, r, rI), 2129 .out_rrr = tgen_xor, 2130 .out_rri = tgen_xori, 2131}; 2132 2133static void tgen_bswap16(TCGContext *s, TCGType type, 2134 TCGReg rd, TCGReg rn, unsigned flags) 2135{ 2136 if (flags & TCG_BSWAP_OS) { 2137 /* revsh */ 2138 tcg_out32(s, 0x06ff0fb0 | (COND_AL << 28) | (rd << 12) | rn); 2139 return; 2140 } 2141 2142 /* rev16 */ 2143 tcg_out32(s, 0x06bf0fb0 | (COND_AL << 28) | (rd << 12) | rn); 2144 if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 2145 tcg_out_ext16u(s, rd, rd); 2146 } 2147} 2148 2149static const TCGOutOpBswap outop_bswap16 = { 2150 .base.static_constraint = C_O1_I1(r, r), 2151 .out_rr = tgen_bswap16, 2152}; 2153 2154static void tgen_bswap32(TCGContext *s, TCGType type, 2155 TCGReg rd, TCGReg rn, unsigned flags) 2156{ 2157 /* rev */ 2158 tcg_out32(s, 0x06bf0f30 | (COND_AL << 28) | (rd << 12) | rn); 2159} 2160 2161static const TCGOutOpBswap outop_bswap32 = { 2162 .base.static_constraint = C_O1_I1(r, r), 2163 .out_rr = tgen_bswap32, 2164}; 2165 2166static const TCGOutOpUnary outop_bswap64 = { 2167 .base.static_constraint = C_NotImplemented, 2168}; 2169 2170static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2171{ 2172 tgen_subfi(s, type, a0, 0, a1); 2173} 2174 2175static const TCGOutOpUnary outop_neg = { 2176 .base.static_constraint = C_O1_I1(r, r), 2177 .out_rr = tgen_neg, 2178}; 2179 2180static void tgen_not(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2181{ 2182 tcg_out_dat_reg(s, COND_AL, ARITH_MVN, a0, 0, a1, SHIFT_IMM_LSL(0)); 2183} 2184 2185static const TCGOutOpUnary outop_not = { 2186 .base.static_constraint = C_O1_I1(r, r), 2187 .out_rr = tgen_not, 2188}; 2189 2190static void tgen_brcond(TCGContext *s, TCGType type, TCGCond cond, 2191 TCGReg a0, TCGReg a1, TCGLabel *l) 2192{ 2193 cond = tgen_cmp(s, cond, a0, a1); 2194 tcg_out_goto_label(s, tcg_cond_to_arm_cond[cond], l); 2195} 2196 2197static void tgen_brcondi(TCGContext *s, TCGType type, TCGCond cond, 2198 TCGReg a0, tcg_target_long a1, TCGLabel *l) 2199{ 2200 cond = tgen_cmpi(s, cond, a0, a1); 2201 tcg_out_goto_label(s, tcg_cond_to_arm_cond[cond], l); 2202} 2203 2204static const TCGOutOpBrcond outop_brcond = { 2205 .base.static_constraint = C_O0_I2(r, rIN), 2206 .out_rr = tgen_brcond, 2207 .out_ri = tgen_brcondi, 2208}; 2209 2210static void finish_setcond(TCGContext *s, TCGCond cond, TCGReg ret, bool neg) 2211{ 2212 tcg_out_movi32(s, tcg_cond_to_arm_cond[tcg_invert_cond(cond)], ret, 0); 2213 tcg_out_movi32(s, tcg_cond_to_arm_cond[cond], ret, neg ? -1 : 1); 2214} 2215 2216static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, 2217 TCGReg a0, TCGReg a1, TCGReg a2) 2218{ 2219 cond = tgen_cmp(s, cond, a1, a2); 2220 finish_setcond(s, cond, a0, false); 2221} 2222 2223static void tgen_setcondi(TCGContext *s, TCGType type, TCGCond cond, 2224 TCGReg a0, TCGReg a1, tcg_target_long a2) 2225{ 2226 cond = tgen_cmpi(s, cond, a1, a2); 2227 finish_setcond(s, cond, a0, false); 2228} 2229 2230static const TCGOutOpSetcond outop_setcond = { 2231 .base.static_constraint = C_O1_I2(r, r, rIN), 2232 .out_rrr = tgen_setcond, 2233 .out_rri = tgen_setcondi, 2234}; 2235 2236static void tgen_negsetcond(TCGContext *s, TCGType type, TCGCond cond, 2237 TCGReg a0, TCGReg a1, TCGReg a2) 2238{ 2239 cond = tgen_cmp(s, cond, a1, a2); 2240 finish_setcond(s, cond, a0, true); 2241} 2242 2243static void tgen_negsetcondi(TCGContext *s, TCGType type, TCGCond cond, 2244 TCGReg a0, TCGReg a1, tcg_target_long a2) 2245{ 2246 cond = tgen_cmpi(s, cond, a1, a2); 2247 finish_setcond(s, cond, a0, true); 2248} 2249 2250static const TCGOutOpSetcond outop_negsetcond = { 2251 .base.static_constraint = C_O1_I2(r, r, rIN), 2252 .out_rrr = tgen_negsetcond, 2253 .out_rri = tgen_negsetcondi, 2254}; 2255 2256static void tgen_movcond(TCGContext *s, TCGType type, TCGCond cond, 2257 TCGReg ret, TCGReg c1, TCGArg c2, bool const_c2, 2258 TCGArg vt, bool const_vt, TCGArg vf, bool consf_vf) 2259{ 2260 cond = tcg_out_cmp(s, cond, c1, c2, const_c2); 2261 tcg_out_dat_rIK(s, tcg_cond_to_arm_cond[cond], ARITH_MOV, ARITH_MVN, 2262 ret, 0, vt, const_vt); 2263} 2264 2265static const TCGOutOpMovcond outop_movcond = { 2266 .base.static_constraint = C_O1_I4(r, r, rIN, rIK, 0), 2267 .out = tgen_movcond, 2268}; 2269 2270static void tgen_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, 2271 TCGArg bl, bool const_bl, TCGArg bh, bool const_bh, 2272 TCGLabel *l) 2273{ 2274 cond = tcg_out_cmp2(s, cond, al, ah, bl, const_bl, bh, const_bh); 2275 tcg_out_goto_label(s, tcg_cond_to_arm_cond[cond], l); 2276} 2277 2278static const TCGOutOpBrcond2 outop_brcond2 = { 2279 .base.static_constraint = C_O0_I4(r, r, rI, rI), 2280 .out = tgen_brcond2, 2281}; 2282 2283static void tgen_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, 2284 TCGReg al, TCGReg ah, 2285 TCGArg bl, bool const_bl, 2286 TCGArg bh, bool const_bh) 2287{ 2288 cond = tcg_out_cmp2(s, cond, al, ah, bl, const_bl, bh, const_bh); 2289 finish_setcond(s, cond, ret, false); 2290} 2291 2292static const TCGOutOpSetcond2 outop_setcond2 = { 2293 .base.static_constraint = C_O1_I4(r, r, r, rI, rI), 2294 .out = tgen_setcond2, 2295}; 2296 2297static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, 2298 const TCGArg args[TCG_MAX_OP_ARGS], 2299 const int const_args[TCG_MAX_OP_ARGS]) 2300{ 2301 TCGArg a0, a1, a2, a3, a4, a5; 2302 2303 switch (opc) { 2304 case INDEX_op_goto_ptr: 2305 tcg_out_b_reg(s, COND_AL, args[0]); 2306 break; 2307 case INDEX_op_br: 2308 tcg_out_goto_label(s, COND_AL, arg_label(args[0])); 2309 break; 2310 2311 case INDEX_op_ld8u_i32: 2312 tcg_out_ld8u(s, COND_AL, args[0], args[1], args[2]); 2313 break; 2314 case INDEX_op_ld8s_i32: 2315 tcg_out_ld8s(s, COND_AL, args[0], args[1], args[2]); 2316 break; 2317 case INDEX_op_ld16u_i32: 2318 tcg_out_ld16u(s, COND_AL, args[0], args[1], args[2]); 2319 break; 2320 case INDEX_op_ld16s_i32: 2321 tcg_out_ld16s(s, COND_AL, args[0], args[1], args[2]); 2322 break; 2323 case INDEX_op_ld_i32: 2324 tcg_out_ld32u(s, COND_AL, args[0], args[1], args[2]); 2325 break; 2326 case INDEX_op_st8_i32: 2327 tcg_out_st8(s, COND_AL, args[0], args[1], args[2]); 2328 break; 2329 case INDEX_op_st16_i32: 2330 tcg_out_st16(s, COND_AL, args[0], args[1], args[2]); 2331 break; 2332 case INDEX_op_st_i32: 2333 tcg_out_st32(s, COND_AL, args[0], args[1], args[2]); 2334 break; 2335 2336 case INDEX_op_add2_i32: 2337 a0 = args[0], a1 = args[1], a2 = args[2]; 2338 a3 = args[3], a4 = args[4], a5 = args[5]; 2339 if (a0 == a3 || (a0 == a5 && !const_args[5])) { 2340 a0 = TCG_REG_TMP; 2341 } 2342 tcg_out_dat_rIN(s, COND_AL, ARITH_ADD | TO_CPSR, ARITH_SUB | TO_CPSR, 2343 a0, a2, a4, const_args[4]); 2344 tcg_out_dat_rIK(s, COND_AL, ARITH_ADC, ARITH_SBC, 2345 a1, a3, a5, const_args[5]); 2346 tcg_out_mov_reg(s, COND_AL, args[0], a0); 2347 break; 2348 case INDEX_op_sub2_i32: 2349 a0 = args[0], a1 = args[1], a2 = args[2]; 2350 a3 = args[3], a4 = args[4], a5 = args[5]; 2351 if ((a0 == a3 && !const_args[3]) || (a0 == a5 && !const_args[5])) { 2352 a0 = TCG_REG_TMP; 2353 } 2354 if (const_args[2]) { 2355 if (const_args[4]) { 2356 tcg_out_movi32(s, COND_AL, a0, a4); 2357 a4 = a0; 2358 } 2359 tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR, a0, a4, a2, 1); 2360 } else { 2361 tcg_out_dat_rIN(s, COND_AL, ARITH_SUB | TO_CPSR, 2362 ARITH_ADD | TO_CPSR, a0, a2, a4, const_args[4]); 2363 } 2364 if (const_args[3]) { 2365 if (const_args[5]) { 2366 tcg_out_movi32(s, COND_AL, a1, a5); 2367 a5 = a1; 2368 } 2369 tcg_out_dat_rI(s, COND_AL, ARITH_RSC, a1, a5, a3, 1); 2370 } else { 2371 tcg_out_dat_rIK(s, COND_AL, ARITH_SBC, ARITH_ADC, 2372 a1, a3, a5, const_args[5]); 2373 } 2374 tcg_out_mov_reg(s, COND_AL, args[0], a0); 2375 break; 2376 2377 case INDEX_op_qemu_ld_i32: 2378 tcg_out_qemu_ld(s, args[0], -1, args[1], args[2], TCG_TYPE_I32); 2379 break; 2380 case INDEX_op_qemu_ld_i64: 2381 tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3], TCG_TYPE_I64); 2382 break; 2383 2384 case INDEX_op_qemu_st_i32: 2385 tcg_out_qemu_st(s, args[0], -1, args[1], args[2], TCG_TYPE_I32); 2386 break; 2387 case INDEX_op_qemu_st_i64: 2388 tcg_out_qemu_st(s, args[0], args[1], args[2], args[3], TCG_TYPE_I64); 2389 break; 2390 2391 case INDEX_op_deposit_i32: 2392 tcg_out_deposit(s, COND_AL, args[0], args[2], 2393 args[3], args[4], const_args[2]); 2394 break; 2395 case INDEX_op_extract_i32: 2396 tcg_out_extract(s, COND_AL, args[0], args[1], args[2], args[3]); 2397 break; 2398 case INDEX_op_sextract_i32: 2399 tcg_out_sextract(s, COND_AL, args[0], args[1], args[2], args[3]); 2400 break; 2401 case INDEX_op_extract2_i32: 2402 /* ??? These optimization vs zero should be generic. */ 2403 /* ??? But we can't substitute 2 for 1 in the opcode stream yet. */ 2404 if (const_args[1]) { 2405 if (const_args[2]) { 2406 tcg_out_movi(s, TCG_TYPE_REG, args[0], 0); 2407 } else { 2408 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, 2409 args[2], SHIFT_IMM_LSL(32 - args[3])); 2410 } 2411 } else if (const_args[2]) { 2412 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, 2413 args[1], SHIFT_IMM_LSR(args[3])); 2414 } else { 2415 /* We can do extract2 in 2 insns, vs the 3 required otherwise. */ 2416 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, 2417 args[2], SHIFT_IMM_LSL(32 - args[3])); 2418 tcg_out_dat_reg(s, COND_AL, ARITH_ORR, args[0], TCG_REG_TMP, 2419 args[1], SHIFT_IMM_LSR(args[3])); 2420 } 2421 break; 2422 2423 case INDEX_op_mb: 2424 tcg_out_mb(s, args[0]); 2425 break; 2426 2427 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2428 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2429 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2430 default: 2431 g_assert_not_reached(); 2432 } 2433} 2434 2435static TCGConstraintSetIndex 2436tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) 2437{ 2438 switch (op) { 2439 case INDEX_op_goto_ptr: 2440 return C_O0_I1(r); 2441 2442 case INDEX_op_ld8u_i32: 2443 case INDEX_op_ld8s_i32: 2444 case INDEX_op_ld16u_i32: 2445 case INDEX_op_ld16s_i32: 2446 case INDEX_op_ld_i32: 2447 case INDEX_op_extract_i32: 2448 case INDEX_op_sextract_i32: 2449 return C_O1_I1(r, r); 2450 2451 case INDEX_op_st8_i32: 2452 case INDEX_op_st16_i32: 2453 case INDEX_op_st_i32: 2454 return C_O0_I2(r, r); 2455 2456 case INDEX_op_deposit_i32: 2457 return C_O1_I2(r, 0, rZ); 2458 case INDEX_op_extract2_i32: 2459 return C_O1_I2(r, rZ, rZ); 2460 case INDEX_op_add2_i32: 2461 return C_O2_I4(r, r, r, r, rIN, rIK); 2462 case INDEX_op_sub2_i32: 2463 return C_O2_I4(r, r, rI, rI, rIN, rIK); 2464 case INDEX_op_qemu_ld_i32: 2465 return C_O1_I1(r, q); 2466 case INDEX_op_qemu_ld_i64: 2467 return C_O2_I1(e, p, q); 2468 case INDEX_op_qemu_st_i32: 2469 return C_O0_I2(q, q); 2470 case INDEX_op_qemu_st_i64: 2471 return C_O0_I3(Q, p, q); 2472 2473 case INDEX_op_st_vec: 2474 return C_O0_I2(w, r); 2475 case INDEX_op_ld_vec: 2476 case INDEX_op_dupm_vec: 2477 return C_O1_I1(w, r); 2478 case INDEX_op_dup_vec: 2479 return C_O1_I1(w, wr); 2480 case INDEX_op_abs_vec: 2481 case INDEX_op_neg_vec: 2482 case INDEX_op_not_vec: 2483 case INDEX_op_shli_vec: 2484 case INDEX_op_shri_vec: 2485 case INDEX_op_sari_vec: 2486 return C_O1_I1(w, w); 2487 case INDEX_op_dup2_vec: 2488 case INDEX_op_add_vec: 2489 case INDEX_op_mul_vec: 2490 case INDEX_op_smax_vec: 2491 case INDEX_op_smin_vec: 2492 case INDEX_op_ssadd_vec: 2493 case INDEX_op_sssub_vec: 2494 case INDEX_op_sub_vec: 2495 case INDEX_op_umax_vec: 2496 case INDEX_op_umin_vec: 2497 case INDEX_op_usadd_vec: 2498 case INDEX_op_ussub_vec: 2499 case INDEX_op_xor_vec: 2500 case INDEX_op_arm_sshl_vec: 2501 case INDEX_op_arm_ushl_vec: 2502 return C_O1_I2(w, w, w); 2503 case INDEX_op_arm_sli_vec: 2504 return C_O1_I2(w, 0, w); 2505 case INDEX_op_or_vec: 2506 case INDEX_op_andc_vec: 2507 return C_O1_I2(w, w, wO); 2508 case INDEX_op_and_vec: 2509 case INDEX_op_orc_vec: 2510 return C_O1_I2(w, w, wV); 2511 case INDEX_op_cmp_vec: 2512 return C_O1_I2(w, w, wZ); 2513 case INDEX_op_bitsel_vec: 2514 return C_O1_I3(w, w, w, w); 2515 default: 2516 return C_NotImplemented; 2517 } 2518} 2519 2520static void tcg_target_init(TCGContext *s) 2521{ 2522 /* 2523 * Only probe for the platform and capabilities if we haven't already 2524 * determined maximum values at compile time. 2525 */ 2526#if !defined(use_idiv_instructions) || !defined(use_neon_instructions) 2527 { 2528 unsigned long hwcap = qemu_getauxval(AT_HWCAP); 2529#ifndef use_idiv_instructions 2530 use_idiv_instructions = (hwcap & HWCAP_ARM_IDIVA) != 0; 2531#endif 2532#ifndef use_neon_instructions 2533 use_neon_instructions = (hwcap & HWCAP_ARM_NEON) != 0; 2534#endif 2535 } 2536#endif 2537 2538 if (__ARM_ARCH < 7) { 2539 const char *pl = (const char *)qemu_getauxval(AT_PLATFORM); 2540 if (pl != NULL && pl[0] == 'v' && pl[1] >= '4' && pl[1] <= '9') { 2541 arm_arch = pl[1] - '0'; 2542 } 2543 2544 if (arm_arch < 6) { 2545 error_report("TCG: ARMv%d is unsupported; exiting", arm_arch); 2546 exit(EXIT_FAILURE); 2547 } 2548 } 2549 2550 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS; 2551 2552 tcg_target_call_clobber_regs = 0; 2553 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); 2554 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1); 2555 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2); 2556 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3); 2557 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12); 2558 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14); 2559 2560 if (use_neon_instructions) { 2561 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS; 2562 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS; 2563 2564 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q0); 2565 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q1); 2566 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q2); 2567 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q3); 2568 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q8); 2569 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q9); 2570 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q10); 2571 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q11); 2572 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q12); 2573 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q13); 2574 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q14); 2575 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q15); 2576 } 2577 2578 s->reserved_regs = 0; 2579 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); 2580 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP); 2581 tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC); 2582 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP); 2583} 2584 2585static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 2586 TCGReg arg1, intptr_t arg2) 2587{ 2588 switch (type) { 2589 case TCG_TYPE_I32: 2590 tcg_out_ld32u(s, COND_AL, arg, arg1, arg2); 2591 return; 2592 case TCG_TYPE_V64: 2593 /* regs 1; size 8; align 8 */ 2594 tcg_out_vldst(s, INSN_VLD1 | 0x7d0, arg, arg1, arg2); 2595 return; 2596 case TCG_TYPE_V128: 2597 /* 2598 * We have only 8-byte alignment for the stack per the ABI. 2599 * Rather than dynamically re-align the stack, it's easier 2600 * to simply not request alignment beyond that. So: 2601 * regs 2; size 8; align 8 2602 */ 2603 tcg_out_vldst(s, INSN_VLD1 | 0xad0, arg, arg1, arg2); 2604 return; 2605 default: 2606 g_assert_not_reached(); 2607 } 2608} 2609 2610static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 2611 TCGReg arg1, intptr_t arg2) 2612{ 2613 switch (type) { 2614 case TCG_TYPE_I32: 2615 tcg_out_st32(s, COND_AL, arg, arg1, arg2); 2616 return; 2617 case TCG_TYPE_V64: 2618 /* regs 1; size 8; align 8 */ 2619 tcg_out_vldst(s, INSN_VST1 | 0x7d0, arg, arg1, arg2); 2620 return; 2621 case TCG_TYPE_V128: 2622 /* See tcg_out_ld re alignment: regs 2; size 8; align 8 */ 2623 tcg_out_vldst(s, INSN_VST1 | 0xad0, arg, arg1, arg2); 2624 return; 2625 default: 2626 g_assert_not_reached(); 2627 } 2628} 2629 2630static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 2631 TCGReg base, intptr_t ofs) 2632{ 2633 return false; 2634} 2635 2636static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 2637{ 2638 if (ret == arg) { 2639 return true; 2640 } 2641 switch (type) { 2642 case TCG_TYPE_I32: 2643 if (ret < TCG_REG_Q0 && arg < TCG_REG_Q0) { 2644 tcg_out_mov_reg(s, COND_AL, ret, arg); 2645 return true; 2646 } 2647 return false; 2648 2649 case TCG_TYPE_V64: 2650 case TCG_TYPE_V128: 2651 /* "VMOV D,N" is an alias for "VORR D,N,N". */ 2652 tcg_out_vreg3(s, INSN_VORR, type - TCG_TYPE_V64, 0, ret, arg, arg); 2653 return true; 2654 2655 default: 2656 g_assert_not_reached(); 2657 } 2658} 2659 2660static void tcg_out_movi(TCGContext *s, TCGType type, 2661 TCGReg ret, tcg_target_long arg) 2662{ 2663 tcg_debug_assert(type == TCG_TYPE_I32); 2664 tcg_debug_assert(ret < TCG_REG_Q0); 2665 tcg_out_movi32(s, COND_AL, ret, arg); 2666} 2667 2668static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 2669{ 2670 return false; 2671} 2672 2673static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 2674 tcg_target_long imm) 2675{ 2676 int enc, opc = ARITH_ADD; 2677 2678 /* All of the easiest immediates to encode are positive. */ 2679 if (imm < 0) { 2680 imm = -imm; 2681 opc = ARITH_SUB; 2682 } 2683 enc = encode_imm(imm); 2684 if (enc >= 0) { 2685 tcg_out_dat_imm(s, COND_AL, opc, rd, rs, enc); 2686 } else { 2687 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, imm); 2688 tcg_out_dat_reg(s, COND_AL, opc, rd, rs, 2689 TCG_REG_TMP, SHIFT_IMM_LSL(0)); 2690 } 2691} 2692 2693/* Type is always V128, with I64 elements. */ 2694static void tcg_out_dup2_vec(TCGContext *s, TCGReg rd, TCGReg rl, TCGReg rh) 2695{ 2696 /* Move high element into place first. */ 2697 /* VMOV Dd+1, Ds */ 2698 tcg_out_vreg3(s, INSN_VORR | (1 << 12), 0, 0, rd, rh, rh); 2699 /* Move low element into place; tcg_out_mov will check for nop. */ 2700 tcg_out_mov(s, TCG_TYPE_V64, rd, rl); 2701} 2702 2703static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 2704 TCGReg rd, TCGReg rs) 2705{ 2706 int q = type - TCG_TYPE_V64; 2707 2708 if (vece == MO_64) { 2709 if (type == TCG_TYPE_V128) { 2710 tcg_out_dup2_vec(s, rd, rs, rs); 2711 } else { 2712 tcg_out_mov(s, TCG_TYPE_V64, rd, rs); 2713 } 2714 } else if (rs < TCG_REG_Q0) { 2715 int b = (vece == MO_8); 2716 int e = (vece == MO_16); 2717 tcg_out32(s, INSN_VDUP_G | (b << 22) | (q << 21) | (e << 5) | 2718 encode_vn(rd) | (rs << 12)); 2719 } else { 2720 int imm4 = 1 << vece; 2721 tcg_out32(s, INSN_VDUP_S | (imm4 << 16) | (q << 6) | 2722 encode_vd(rd) | encode_vm(rs)); 2723 } 2724 return true; 2725} 2726 2727static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 2728 TCGReg rd, TCGReg base, intptr_t offset) 2729{ 2730 if (vece == MO_64) { 2731 tcg_out_ld(s, TCG_TYPE_V64, rd, base, offset); 2732 if (type == TCG_TYPE_V128) { 2733 tcg_out_dup2_vec(s, rd, rd, rd); 2734 } 2735 } else { 2736 int q = type - TCG_TYPE_V64; 2737 tcg_out_vldst(s, INSN_VLD1R | (vece << 6) | (q << 5), 2738 rd, base, offset); 2739 } 2740 return true; 2741} 2742 2743static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 2744 TCGReg rd, int64_t v64) 2745{ 2746 int q = type - TCG_TYPE_V64; 2747 int cmode, imm8, i; 2748 2749 /* Test all bytes equal first. */ 2750 if (vece == MO_8) { 2751 tcg_out_vmovi(s, rd, q, 0, 0xe, v64); 2752 return; 2753 } 2754 2755 /* 2756 * Test all bytes 0x00 or 0xff second. This can match cases that 2757 * might otherwise take 2 or 3 insns for MO_16 or MO_32 below. 2758 */ 2759 for (i = imm8 = 0; i < 8; i++) { 2760 uint8_t byte = v64 >> (i * 8); 2761 if (byte == 0xff) { 2762 imm8 |= 1 << i; 2763 } else if (byte != 0) { 2764 goto fail_bytes; 2765 } 2766 } 2767 tcg_out_vmovi(s, rd, q, 1, 0xe, imm8); 2768 return; 2769 fail_bytes: 2770 2771 /* 2772 * Tests for various replications. For each element width, if we 2773 * cannot find an expansion there's no point checking a larger 2774 * width because we already know by replication it cannot match. 2775 */ 2776 if (vece == MO_16) { 2777 uint16_t v16 = v64; 2778 2779 if (is_shimm16(v16, &cmode, &imm8)) { 2780 tcg_out_vmovi(s, rd, q, 0, cmode, imm8); 2781 return; 2782 } 2783 if (is_shimm16(~v16, &cmode, &imm8)) { 2784 tcg_out_vmovi(s, rd, q, 1, cmode, imm8); 2785 return; 2786 } 2787 2788 /* 2789 * Otherwise, all remaining constants can be loaded in two insns: 2790 * rd = v16 & 0xff, rd |= v16 & 0xff00. 2791 */ 2792 tcg_out_vmovi(s, rd, q, 0, 0x8, v16 & 0xff); 2793 tcg_out_vmovi(s, rd, q, 0, 0xb, v16 >> 8); /* VORRI */ 2794 return; 2795 } 2796 2797 if (vece == MO_32) { 2798 uint32_t v32 = v64; 2799 2800 if (is_shimm32(v32, &cmode, &imm8) || 2801 is_soimm32(v32, &cmode, &imm8)) { 2802 tcg_out_vmovi(s, rd, q, 0, cmode, imm8); 2803 return; 2804 } 2805 if (is_shimm32(~v32, &cmode, &imm8) || 2806 is_soimm32(~v32, &cmode, &imm8)) { 2807 tcg_out_vmovi(s, rd, q, 1, cmode, imm8); 2808 return; 2809 } 2810 2811 /* 2812 * Restrict the set of constants to those we can load with 2813 * two instructions. Others we load from the pool. 2814 */ 2815 i = is_shimm32_pair(v32, &cmode, &imm8); 2816 if (i) { 2817 tcg_out_vmovi(s, rd, q, 0, cmode, imm8); 2818 tcg_out_vmovi(s, rd, q, 0, i | 1, extract32(v32, i * 4, 8)); 2819 return; 2820 } 2821 i = is_shimm32_pair(~v32, &cmode, &imm8); 2822 if (i) { 2823 tcg_out_vmovi(s, rd, q, 1, cmode, imm8); 2824 tcg_out_vmovi(s, rd, q, 1, i | 1, extract32(~v32, i * 4, 8)); 2825 return; 2826 } 2827 } 2828 2829 /* 2830 * As a last resort, load from the constant pool. 2831 */ 2832 if (!q || vece == MO_64) { 2833 new_pool_l2(s, R_ARM_PC11, s->code_ptr, 0, v64, v64 >> 32); 2834 /* VLDR Dd, [pc + offset] */ 2835 tcg_out32(s, INSN_VLDR_D | encode_vd(rd) | (0xf << 16)); 2836 if (q) { 2837 tcg_out_dup2_vec(s, rd, rd, rd); 2838 } 2839 } else { 2840 new_pool_label(s, (uint32_t)v64, R_ARM_PC8, s->code_ptr, 0); 2841 /* add tmp, pc, offset */ 2842 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_TMP, TCG_REG_PC, 0); 2843 tcg_out_dupm_vec(s, type, MO_32, rd, TCG_REG_TMP, 0); 2844 } 2845} 2846 2847static const ARMInsn vec_cmp_insn[16] = { 2848 [TCG_COND_EQ] = INSN_VCEQ, 2849 [TCG_COND_GT] = INSN_VCGT, 2850 [TCG_COND_GE] = INSN_VCGE, 2851 [TCG_COND_GTU] = INSN_VCGT_U, 2852 [TCG_COND_GEU] = INSN_VCGE_U, 2853}; 2854 2855static const ARMInsn vec_cmp0_insn[16] = { 2856 [TCG_COND_EQ] = INSN_VCEQ0, 2857 [TCG_COND_GT] = INSN_VCGT0, 2858 [TCG_COND_GE] = INSN_VCGE0, 2859 [TCG_COND_LT] = INSN_VCLT0, 2860 [TCG_COND_LE] = INSN_VCLE0, 2861}; 2862 2863static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 2864 unsigned vecl, unsigned vece, 2865 const TCGArg args[TCG_MAX_OP_ARGS], 2866 const int const_args[TCG_MAX_OP_ARGS]) 2867{ 2868 TCGType type = vecl + TCG_TYPE_V64; 2869 unsigned q = vecl; 2870 TCGArg a0, a1, a2, a3; 2871 int cmode, imm8; 2872 2873 a0 = args[0]; 2874 a1 = args[1]; 2875 a2 = args[2]; 2876 2877 switch (opc) { 2878 case INDEX_op_ld_vec: 2879 tcg_out_ld(s, type, a0, a1, a2); 2880 return; 2881 case INDEX_op_st_vec: 2882 tcg_out_st(s, type, a0, a1, a2); 2883 return; 2884 case INDEX_op_dupm_vec: 2885 tcg_out_dupm_vec(s, type, vece, a0, a1, a2); 2886 return; 2887 case INDEX_op_dup2_vec: 2888 tcg_out_dup2_vec(s, a0, a1, a2); 2889 return; 2890 case INDEX_op_abs_vec: 2891 tcg_out_vreg2(s, INSN_VABS, q, vece, a0, a1); 2892 return; 2893 case INDEX_op_neg_vec: 2894 tcg_out_vreg2(s, INSN_VNEG, q, vece, a0, a1); 2895 return; 2896 case INDEX_op_not_vec: 2897 tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a1); 2898 return; 2899 case INDEX_op_add_vec: 2900 tcg_out_vreg3(s, INSN_VADD, q, vece, a0, a1, a2); 2901 return; 2902 case INDEX_op_mul_vec: 2903 tcg_out_vreg3(s, INSN_VMUL, q, vece, a0, a1, a2); 2904 return; 2905 case INDEX_op_smax_vec: 2906 tcg_out_vreg3(s, INSN_VMAX, q, vece, a0, a1, a2); 2907 return; 2908 case INDEX_op_smin_vec: 2909 tcg_out_vreg3(s, INSN_VMIN, q, vece, a0, a1, a2); 2910 return; 2911 case INDEX_op_sub_vec: 2912 tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2); 2913 return; 2914 case INDEX_op_ssadd_vec: 2915 tcg_out_vreg3(s, INSN_VQADD, q, vece, a0, a1, a2); 2916 return; 2917 case INDEX_op_sssub_vec: 2918 tcg_out_vreg3(s, INSN_VQSUB, q, vece, a0, a1, a2); 2919 return; 2920 case INDEX_op_umax_vec: 2921 tcg_out_vreg3(s, INSN_VMAX_U, q, vece, a0, a1, a2); 2922 return; 2923 case INDEX_op_umin_vec: 2924 tcg_out_vreg3(s, INSN_VMIN_U, q, vece, a0, a1, a2); 2925 return; 2926 case INDEX_op_usadd_vec: 2927 tcg_out_vreg3(s, INSN_VQADD_U, q, vece, a0, a1, a2); 2928 return; 2929 case INDEX_op_ussub_vec: 2930 tcg_out_vreg3(s, INSN_VQSUB_U, q, vece, a0, a1, a2); 2931 return; 2932 case INDEX_op_xor_vec: 2933 tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2); 2934 return; 2935 case INDEX_op_arm_sshl_vec: 2936 /* 2937 * Note that Vm is the data and Vn is the shift count, 2938 * therefore the arguments appear reversed. 2939 */ 2940 tcg_out_vreg3(s, INSN_VSHL_S, q, vece, a0, a2, a1); 2941 return; 2942 case INDEX_op_arm_ushl_vec: 2943 /* See above. */ 2944 tcg_out_vreg3(s, INSN_VSHL_U, q, vece, a0, a2, a1); 2945 return; 2946 case INDEX_op_shli_vec: 2947 tcg_out_vshifti(s, INSN_VSHLI, q, a0, a1, a2 + (8 << vece)); 2948 return; 2949 case INDEX_op_shri_vec: 2950 tcg_out_vshifti(s, INSN_VSHRI, q, a0, a1, (16 << vece) - a2); 2951 return; 2952 case INDEX_op_sari_vec: 2953 tcg_out_vshifti(s, INSN_VSARI, q, a0, a1, (16 << vece) - a2); 2954 return; 2955 case INDEX_op_arm_sli_vec: 2956 tcg_out_vshifti(s, INSN_VSLI, q, a0, a2, args[3] + (8 << vece)); 2957 return; 2958 2959 case INDEX_op_andc_vec: 2960 if (!const_args[2]) { 2961 tcg_out_vreg3(s, INSN_VBIC, q, 0, a0, a1, a2); 2962 return; 2963 } 2964 a2 = ~a2; 2965 /* fall through */ 2966 case INDEX_op_and_vec: 2967 if (const_args[2]) { 2968 is_shimm1632(~a2, &cmode, &imm8); 2969 if (a0 == a1) { 2970 tcg_out_vmovi(s, a0, q, 1, cmode | 1, imm8); /* VBICI */ 2971 return; 2972 } 2973 tcg_out_vmovi(s, a0, q, 1, cmode, imm8); /* VMVNI */ 2974 a2 = a0; 2975 } 2976 tcg_out_vreg3(s, INSN_VAND, q, 0, a0, a1, a2); 2977 return; 2978 2979 case INDEX_op_orc_vec: 2980 if (!const_args[2]) { 2981 tcg_out_vreg3(s, INSN_VORN, q, 0, a0, a1, a2); 2982 return; 2983 } 2984 a2 = ~a2; 2985 /* fall through */ 2986 case INDEX_op_or_vec: 2987 if (const_args[2]) { 2988 is_shimm1632(a2, &cmode, &imm8); 2989 if (a0 == a1) { 2990 tcg_out_vmovi(s, a0, q, 0, cmode | 1, imm8); /* VORRI */ 2991 return; 2992 } 2993 tcg_out_vmovi(s, a0, q, 0, cmode, imm8); /* VMOVI */ 2994 a2 = a0; 2995 } 2996 tcg_out_vreg3(s, INSN_VORR, q, 0, a0, a1, a2); 2997 return; 2998 2999 case INDEX_op_cmp_vec: 3000 { 3001 TCGCond cond = args[3]; 3002 ARMInsn insn; 3003 3004 switch (cond) { 3005 case TCG_COND_NE: 3006 if (const_args[2]) { 3007 tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a1); 3008 } else { 3009 tcg_out_vreg3(s, INSN_VCEQ, q, vece, a0, a1, a2); 3010 tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0); 3011 } 3012 break; 3013 3014 case TCG_COND_TSTNE: 3015 case TCG_COND_TSTEQ: 3016 if (const_args[2]) { 3017 /* (x & 0) == 0 */ 3018 tcg_out_dupi_vec(s, type, MO_8, a0, 3019 -(cond == TCG_COND_TSTEQ)); 3020 break; 3021 } 3022 tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a2); 3023 if (cond == TCG_COND_TSTEQ) { 3024 tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0); 3025 } 3026 break; 3027 3028 default: 3029 if (const_args[2]) { 3030 insn = vec_cmp0_insn[cond]; 3031 if (insn) { 3032 tcg_out_vreg2(s, insn, q, vece, a0, a1); 3033 return; 3034 } 3035 tcg_out_dupi_vec(s, type, MO_8, TCG_VEC_TMP, 0); 3036 a2 = TCG_VEC_TMP; 3037 } 3038 insn = vec_cmp_insn[cond]; 3039 if (insn == 0) { 3040 TCGArg t; 3041 t = a1, a1 = a2, a2 = t; 3042 cond = tcg_swap_cond(cond); 3043 insn = vec_cmp_insn[cond]; 3044 tcg_debug_assert(insn != 0); 3045 } 3046 tcg_out_vreg3(s, insn, q, vece, a0, a1, a2); 3047 break; 3048 } 3049 } 3050 return; 3051 3052 case INDEX_op_bitsel_vec: 3053 a3 = args[3]; 3054 if (a0 == a3) { 3055 tcg_out_vreg3(s, INSN_VBIT, q, 0, a0, a2, a1); 3056 } else if (a0 == a2) { 3057 tcg_out_vreg3(s, INSN_VBIF, q, 0, a0, a3, a1); 3058 } else { 3059 tcg_out_mov(s, type, a0, a1); 3060 tcg_out_vreg3(s, INSN_VBSL, q, 0, a0, a2, a3); 3061 } 3062 return; 3063 3064 case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ 3065 case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ 3066 default: 3067 g_assert_not_reached(); 3068 } 3069} 3070 3071int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 3072{ 3073 switch (opc) { 3074 case INDEX_op_add_vec: 3075 case INDEX_op_sub_vec: 3076 case INDEX_op_and_vec: 3077 case INDEX_op_andc_vec: 3078 case INDEX_op_or_vec: 3079 case INDEX_op_orc_vec: 3080 case INDEX_op_xor_vec: 3081 case INDEX_op_not_vec: 3082 case INDEX_op_shli_vec: 3083 case INDEX_op_shri_vec: 3084 case INDEX_op_sari_vec: 3085 case INDEX_op_ssadd_vec: 3086 case INDEX_op_sssub_vec: 3087 case INDEX_op_usadd_vec: 3088 case INDEX_op_ussub_vec: 3089 case INDEX_op_bitsel_vec: 3090 return 1; 3091 case INDEX_op_abs_vec: 3092 case INDEX_op_cmp_vec: 3093 case INDEX_op_mul_vec: 3094 case INDEX_op_neg_vec: 3095 case INDEX_op_smax_vec: 3096 case INDEX_op_smin_vec: 3097 case INDEX_op_umax_vec: 3098 case INDEX_op_umin_vec: 3099 return vece < MO_64; 3100 case INDEX_op_shlv_vec: 3101 case INDEX_op_shrv_vec: 3102 case INDEX_op_sarv_vec: 3103 case INDEX_op_rotli_vec: 3104 case INDEX_op_rotlv_vec: 3105 case INDEX_op_rotrv_vec: 3106 return -1; 3107 default: 3108 return 0; 3109 } 3110} 3111 3112void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 3113 TCGArg a0, ...) 3114{ 3115 va_list va; 3116 TCGv_vec v0, v1, v2, t1, t2, c1; 3117 TCGArg a2; 3118 3119 va_start(va, a0); 3120 v0 = temp_tcgv_vec(arg_temp(a0)); 3121 v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 3122 a2 = va_arg(va, TCGArg); 3123 va_end(va); 3124 3125 switch (opc) { 3126 case INDEX_op_shlv_vec: 3127 /* 3128 * Merely propagate shlv_vec to arm_ushl_vec. 3129 * In this way we don't set TCG_TARGET_HAS_shv_vec 3130 * because everything is done via expansion. 3131 */ 3132 v2 = temp_tcgv_vec(arg_temp(a2)); 3133 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0), 3134 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 3135 break; 3136 3137 case INDEX_op_shrv_vec: 3138 case INDEX_op_sarv_vec: 3139 /* Right shifts are negative left shifts for NEON. */ 3140 v2 = temp_tcgv_vec(arg_temp(a2)); 3141 t1 = tcg_temp_new_vec(type); 3142 tcg_gen_neg_vec(vece, t1, v2); 3143 if (opc == INDEX_op_shrv_vec) { 3144 opc = INDEX_op_arm_ushl_vec; 3145 } else { 3146 opc = INDEX_op_arm_sshl_vec; 3147 } 3148 vec_gen_3(opc, type, vece, tcgv_vec_arg(v0), 3149 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 3150 tcg_temp_free_vec(t1); 3151 break; 3152 3153 case INDEX_op_rotli_vec: 3154 t1 = tcg_temp_new_vec(type); 3155 tcg_gen_shri_vec(vece, t1, v1, -a2 & ((8 << vece) - 1)); 3156 vec_gen_4(INDEX_op_arm_sli_vec, type, vece, 3157 tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(v1), a2); 3158 tcg_temp_free_vec(t1); 3159 break; 3160 3161 case INDEX_op_rotlv_vec: 3162 v2 = temp_tcgv_vec(arg_temp(a2)); 3163 t1 = tcg_temp_new_vec(type); 3164 c1 = tcg_constant_vec(type, vece, 8 << vece); 3165 tcg_gen_sub_vec(vece, t1, v2, c1); 3166 /* Right shifts are negative left shifts for NEON. */ 3167 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1), 3168 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 3169 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0), 3170 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 3171 tcg_gen_or_vec(vece, v0, v0, t1); 3172 tcg_temp_free_vec(t1); 3173 break; 3174 3175 case INDEX_op_rotrv_vec: 3176 v2 = temp_tcgv_vec(arg_temp(a2)); 3177 t1 = tcg_temp_new_vec(type); 3178 t2 = tcg_temp_new_vec(type); 3179 c1 = tcg_constant_vec(type, vece, 8 << vece); 3180 tcg_gen_neg_vec(vece, t1, v2); 3181 tcg_gen_sub_vec(vece, t2, c1, v2); 3182 /* Right shifts are negative left shifts for NEON. */ 3183 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1), 3184 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 3185 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t2), 3186 tcgv_vec_arg(v1), tcgv_vec_arg(t2)); 3187 tcg_gen_or_vec(vece, v0, t1, t2); 3188 tcg_temp_free_vec(t1); 3189 tcg_temp_free_vec(t2); 3190 break; 3191 3192 default: 3193 g_assert_not_reached(); 3194 } 3195} 3196 3197static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 3198{ 3199 int i; 3200 for (i = 0; i < count; ++i) { 3201 p[i] = INSN_NOP; 3202 } 3203} 3204 3205/* Compute frame size via macros, to share between tcg_target_qemu_prologue 3206 and tcg_register_jit. */ 3207 3208#define PUSH_SIZE ((11 - 4 + 1 + 1) * sizeof(tcg_target_long)) 3209 3210#define FRAME_SIZE \ 3211 ((PUSH_SIZE \ 3212 + TCG_STATIC_CALL_ARGS_SIZE \ 3213 + CPU_TEMP_BUF_NLONGS * sizeof(long) \ 3214 + TCG_TARGET_STACK_ALIGN - 1) \ 3215 & -TCG_TARGET_STACK_ALIGN) 3216 3217#define STACK_ADDEND (FRAME_SIZE - PUSH_SIZE) 3218 3219static void tcg_target_qemu_prologue(TCGContext *s) 3220{ 3221 /* Calling convention requires us to save r4-r11 and lr. */ 3222 /* stmdb sp!, { r4 - r11, lr } */ 3223 tcg_out_ldstm(s, COND_AL, INSN_STMDB, TCG_REG_CALL_STACK, 3224 (1 << TCG_REG_R4) | (1 << TCG_REG_R5) | (1 << TCG_REG_R6) | 3225 (1 << TCG_REG_R7) | (1 << TCG_REG_R8) | (1 << TCG_REG_R9) | 3226 (1 << TCG_REG_R10) | (1 << TCG_REG_R11) | (1 << TCG_REG_R14)); 3227 3228 /* Reserve callee argument and tcg temp space. */ 3229 tcg_out_dat_rI(s, COND_AL, ARITH_SUB, TCG_REG_CALL_STACK, 3230 TCG_REG_CALL_STACK, STACK_ADDEND, 1); 3231 tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE, 3232 CPU_TEMP_BUF_NLONGS * sizeof(long)); 3233 3234 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 3235 3236 if (!tcg_use_softmmu && guest_base) { 3237 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_GUEST_BASE, guest_base); 3238 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GUEST_BASE); 3239 } 3240 3241 tcg_out_b_reg(s, COND_AL, tcg_target_call_iarg_regs[1]); 3242 3243 /* 3244 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 3245 * and fall through to the rest of the epilogue. 3246 */ 3247 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 3248 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, 0); 3249 tcg_out_epilogue(s); 3250} 3251 3252static void tcg_out_epilogue(TCGContext *s) 3253{ 3254 /* Release local stack frame. */ 3255 tcg_out_dat_rI(s, COND_AL, ARITH_ADD, TCG_REG_CALL_STACK, 3256 TCG_REG_CALL_STACK, STACK_ADDEND, 1); 3257 3258 /* ldmia sp!, { r4 - r11, pc } */ 3259 tcg_out_ldstm(s, COND_AL, INSN_LDMIA, TCG_REG_CALL_STACK, 3260 (1 << TCG_REG_R4) | (1 << TCG_REG_R5) | (1 << TCG_REG_R6) | 3261 (1 << TCG_REG_R7) | (1 << TCG_REG_R8) | (1 << TCG_REG_R9) | 3262 (1 << TCG_REG_R10) | (1 << TCG_REG_R11) | (1 << TCG_REG_PC)); 3263} 3264 3265static void tcg_out_tb_start(TCGContext *s) 3266{ 3267 /* nothing to do */ 3268} 3269 3270typedef struct { 3271 DebugFrameHeader h; 3272 uint8_t fde_def_cfa[4]; 3273 uint8_t fde_reg_ofs[18]; 3274} DebugFrame; 3275 3276#define ELF_HOST_MACHINE EM_ARM 3277 3278/* We're expecting a 2 byte uleb128 encoded value. */ 3279QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); 3280 3281static const DebugFrame debug_frame = { 3282 .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ 3283 .h.cie.id = -1, 3284 .h.cie.version = 1, 3285 .h.cie.code_align = 1, 3286 .h.cie.data_align = 0x7c, /* sleb128 -4 */ 3287 .h.cie.return_column = 14, 3288 3289 /* Total FDE size does not include the "len" member. */ 3290 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 3291 3292 .fde_def_cfa = { 3293 12, 13, /* DW_CFA_def_cfa sp, ... */ 3294 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 3295 (FRAME_SIZE >> 7) 3296 }, 3297 .fde_reg_ofs = { 3298 /* The following must match the stmdb in the prologue. */ 3299 0x8e, 1, /* DW_CFA_offset, lr, -4 */ 3300 0x8b, 2, /* DW_CFA_offset, r11, -8 */ 3301 0x8a, 3, /* DW_CFA_offset, r10, -12 */ 3302 0x89, 4, /* DW_CFA_offset, r9, -16 */ 3303 0x88, 5, /* DW_CFA_offset, r8, -20 */ 3304 0x87, 6, /* DW_CFA_offset, r7, -24 */ 3305 0x86, 7, /* DW_CFA_offset, r6, -28 */ 3306 0x85, 8, /* DW_CFA_offset, r5, -32 */ 3307 0x84, 9, /* DW_CFA_offset, r4, -36 */ 3308 } 3309}; 3310 3311void tcg_register_jit(const void *buf, size_t buf_size) 3312{ 3313 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 3314} 3315