1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Andrzej Zaborowski 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25#include "elf.h" 26 27int arm_arch = __ARM_ARCH; 28 29#ifndef use_idiv_instructions 30bool use_idiv_instructions; 31#endif 32#ifndef use_neon_instructions 33bool use_neon_instructions; 34#endif 35 36/* Used for function call generation. */ 37#define TCG_TARGET_STACK_ALIGN 8 38#define TCG_TARGET_CALL_STACK_OFFSET 0 39#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL 40#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN 41#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN 42#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF 43 44#ifdef CONFIG_DEBUG_TCG 45static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 46 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", 47 "%r8", "%r9", "%r10", "%r11", "%r12", "%sp", "%r14", "%pc", 48 "%q0", "%q1", "%q2", "%q3", "%q4", "%q5", "%q6", "%q7", 49 "%q8", "%q9", "%q10", "%q11", "%q12", "%q13", "%q14", "%q15", 50}; 51#endif 52 53static const int tcg_target_reg_alloc_order[] = { 54 TCG_REG_R4, 55 TCG_REG_R5, 56 TCG_REG_R6, 57 TCG_REG_R7, 58 TCG_REG_R8, 59 TCG_REG_R9, 60 TCG_REG_R10, 61 TCG_REG_R11, 62 TCG_REG_R13, 63 TCG_REG_R0, 64 TCG_REG_R1, 65 TCG_REG_R2, 66 TCG_REG_R3, 67 TCG_REG_R12, 68 TCG_REG_R14, 69 70 TCG_REG_Q0, 71 TCG_REG_Q1, 72 TCG_REG_Q2, 73 TCG_REG_Q3, 74 /* Q4 - Q7 are call-saved, and skipped. */ 75 TCG_REG_Q8, 76 TCG_REG_Q9, 77 TCG_REG_Q10, 78 TCG_REG_Q11, 79 TCG_REG_Q12, 80 TCG_REG_Q13, 81 TCG_REG_Q14, 82 TCG_REG_Q15, 83}; 84 85static const int tcg_target_call_iarg_regs[4] = { 86 TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3 87}; 88 89static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 90{ 91 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 92 tcg_debug_assert(slot >= 0 && slot <= 3); 93 return TCG_REG_R0 + slot; 94} 95 96#define TCG_REG_TMP TCG_REG_R12 97#define TCG_VEC_TMP TCG_REG_Q15 98#define TCG_REG_GUEST_BASE TCG_REG_R11 99 100typedef enum { 101 COND_EQ = 0x0, 102 COND_NE = 0x1, 103 COND_CS = 0x2, /* Unsigned greater or equal */ 104 COND_CC = 0x3, /* Unsigned less than */ 105 COND_MI = 0x4, /* Negative */ 106 COND_PL = 0x5, /* Zero or greater */ 107 COND_VS = 0x6, /* Overflow */ 108 COND_VC = 0x7, /* No overflow */ 109 COND_HI = 0x8, /* Unsigned greater than */ 110 COND_LS = 0x9, /* Unsigned less or equal */ 111 COND_GE = 0xa, 112 COND_LT = 0xb, 113 COND_GT = 0xc, 114 COND_LE = 0xd, 115 COND_AL = 0xe, 116} ARMCond; 117 118#define TO_CPSR (1 << 20) 119 120#define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00) 121#define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20) 122#define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40) 123#define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60) 124#define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10) 125#define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30) 126#define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50) 127#define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70) 128 129typedef enum { 130 ARITH_AND = 0x0 << 21, 131 ARITH_EOR = 0x1 << 21, 132 ARITH_SUB = 0x2 << 21, 133 ARITH_RSB = 0x3 << 21, 134 ARITH_ADD = 0x4 << 21, 135 ARITH_ADC = 0x5 << 21, 136 ARITH_SBC = 0x6 << 21, 137 ARITH_RSC = 0x7 << 21, 138 ARITH_TST = 0x8 << 21 | TO_CPSR, 139 ARITH_CMP = 0xa << 21 | TO_CPSR, 140 ARITH_CMN = 0xb << 21 | TO_CPSR, 141 ARITH_ORR = 0xc << 21, 142 ARITH_MOV = 0xd << 21, 143 ARITH_BIC = 0xe << 21, 144 ARITH_MVN = 0xf << 21, 145 146 INSN_B = 0x0a000000, 147 148 INSN_CLZ = 0x016f0f10, 149 INSN_RBIT = 0x06ff0f30, 150 151 INSN_LDMIA = 0x08b00000, 152 INSN_STMDB = 0x09200000, 153 154 INSN_LDR_IMM = 0x04100000, 155 INSN_LDR_REG = 0x06100000, 156 INSN_STR_IMM = 0x04000000, 157 INSN_STR_REG = 0x06000000, 158 159 INSN_LDRH_IMM = 0x005000b0, 160 INSN_LDRH_REG = 0x001000b0, 161 INSN_LDRSH_IMM = 0x005000f0, 162 INSN_LDRSH_REG = 0x001000f0, 163 INSN_STRH_IMM = 0x004000b0, 164 INSN_STRH_REG = 0x000000b0, 165 166 INSN_LDRB_IMM = 0x04500000, 167 INSN_LDRB_REG = 0x06500000, 168 INSN_LDRSB_IMM = 0x005000d0, 169 INSN_LDRSB_REG = 0x001000d0, 170 INSN_STRB_IMM = 0x04400000, 171 INSN_STRB_REG = 0x06400000, 172 173 INSN_LDRD_IMM = 0x004000d0, 174 INSN_LDRD_REG = 0x000000d0, 175 INSN_STRD_IMM = 0x004000f0, 176 INSN_STRD_REG = 0x000000f0, 177 178 INSN_DMB_ISH = 0xf57ff05b, 179 INSN_DMB_MCR = 0xee070fba, 180 181 /* Architected nop introduced in v6k. */ 182 /* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this 183 also Just So Happened to do nothing on pre-v6k so that we 184 don't need to conditionalize it? */ 185 INSN_NOP_v6k = 0xe320f000, 186 /* Otherwise the assembler uses mov r0,r0 */ 187 INSN_NOP_v4 = (COND_AL << 28) | ARITH_MOV, 188 189 INSN_VADD = 0xf2000800, 190 INSN_VAND = 0xf2000110, 191 INSN_VBIC = 0xf2100110, 192 INSN_VEOR = 0xf3000110, 193 INSN_VORN = 0xf2300110, 194 INSN_VORR = 0xf2200110, 195 INSN_VSUB = 0xf3000800, 196 INSN_VMUL = 0xf2000910, 197 INSN_VQADD = 0xf2000010, 198 INSN_VQADD_U = 0xf3000010, 199 INSN_VQSUB = 0xf2000210, 200 INSN_VQSUB_U = 0xf3000210, 201 INSN_VMAX = 0xf2000600, 202 INSN_VMAX_U = 0xf3000600, 203 INSN_VMIN = 0xf2000610, 204 INSN_VMIN_U = 0xf3000610, 205 206 INSN_VABS = 0xf3b10300, 207 INSN_VMVN = 0xf3b00580, 208 INSN_VNEG = 0xf3b10380, 209 210 INSN_VCEQ0 = 0xf3b10100, 211 INSN_VCGT0 = 0xf3b10000, 212 INSN_VCGE0 = 0xf3b10080, 213 INSN_VCLE0 = 0xf3b10180, 214 INSN_VCLT0 = 0xf3b10200, 215 216 INSN_VCEQ = 0xf3000810, 217 INSN_VCGE = 0xf2000310, 218 INSN_VCGT = 0xf2000300, 219 INSN_VCGE_U = 0xf3000310, 220 INSN_VCGT_U = 0xf3000300, 221 222 INSN_VSHLI = 0xf2800510, /* VSHL (immediate) */ 223 INSN_VSARI = 0xf2800010, /* VSHR.S */ 224 INSN_VSHRI = 0xf3800010, /* VSHR.U */ 225 INSN_VSLI = 0xf3800510, 226 INSN_VSHL_S = 0xf2000400, /* VSHL.S (register) */ 227 INSN_VSHL_U = 0xf3000400, /* VSHL.U (register) */ 228 229 INSN_VBSL = 0xf3100110, 230 INSN_VBIT = 0xf3200110, 231 INSN_VBIF = 0xf3300110, 232 233 INSN_VTST = 0xf2000810, 234 235 INSN_VDUP_G = 0xee800b10, /* VDUP (ARM core register) */ 236 INSN_VDUP_S = 0xf3b00c00, /* VDUP (scalar) */ 237 INSN_VLDR_D = 0xed100b00, /* VLDR.64 */ 238 INSN_VLD1 = 0xf4200000, /* VLD1 (multiple single elements) */ 239 INSN_VLD1R = 0xf4a00c00, /* VLD1 (single element to all lanes) */ 240 INSN_VST1 = 0xf4000000, /* VST1 (multiple single elements) */ 241 INSN_VMOVI = 0xf2800010, /* VMOV (immediate) */ 242} ARMInsn; 243 244#define INSN_NOP (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4) 245 246static const uint8_t tcg_cond_to_arm_cond[] = { 247 [TCG_COND_EQ] = COND_EQ, 248 [TCG_COND_NE] = COND_NE, 249 [TCG_COND_LT] = COND_LT, 250 [TCG_COND_GE] = COND_GE, 251 [TCG_COND_LE] = COND_LE, 252 [TCG_COND_GT] = COND_GT, 253 /* unsigned */ 254 [TCG_COND_LTU] = COND_CC, 255 [TCG_COND_GEU] = COND_CS, 256 [TCG_COND_LEU] = COND_LS, 257 [TCG_COND_GTU] = COND_HI, 258}; 259 260static int encode_imm(uint32_t imm); 261 262/* TCG private relocation type: add with pc+imm8 */ 263#define R_ARM_PC8 11 264 265/* TCG private relocation type: vldr with imm8 << 2 */ 266#define R_ARM_PC11 12 267 268static bool reloc_pc24(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 269{ 270 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 271 ptrdiff_t offset = (tcg_ptr_byte_diff(target, src_rx) - 8) >> 2; 272 273 if (offset == sextract32(offset, 0, 24)) { 274 *src_rw = deposit32(*src_rw, 0, 24, offset); 275 return true; 276 } 277 return false; 278} 279 280static bool reloc_pc13(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 281{ 282 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 283 ptrdiff_t offset = tcg_ptr_byte_diff(target, src_rx) - 8; 284 285 if (offset >= -0xfff && offset <= 0xfff) { 286 tcg_insn_unit insn = *src_rw; 287 bool u = (offset >= 0); 288 if (!u) { 289 offset = -offset; 290 } 291 insn = deposit32(insn, 23, 1, u); 292 insn = deposit32(insn, 0, 12, offset); 293 *src_rw = insn; 294 return true; 295 } 296 return false; 297} 298 299static bool reloc_pc11(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 300{ 301 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 302 ptrdiff_t offset = (tcg_ptr_byte_diff(target, src_rx) - 8) / 4; 303 304 if (offset >= -0xff && offset <= 0xff) { 305 tcg_insn_unit insn = *src_rw; 306 bool u = (offset >= 0); 307 if (!u) { 308 offset = -offset; 309 } 310 insn = deposit32(insn, 23, 1, u); 311 insn = deposit32(insn, 0, 8, offset); 312 *src_rw = insn; 313 return true; 314 } 315 return false; 316} 317 318static bool reloc_pc8(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 319{ 320 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 321 ptrdiff_t offset = tcg_ptr_byte_diff(target, src_rx) - 8; 322 int imm12 = encode_imm(offset); 323 324 if (imm12 >= 0) { 325 *src_rw = deposit32(*src_rw, 0, 12, imm12); 326 return true; 327 } 328 return false; 329} 330 331static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 332 intptr_t value, intptr_t addend) 333{ 334 tcg_debug_assert(addend == 0); 335 switch (type) { 336 case R_ARM_PC24: 337 return reloc_pc24(code_ptr, (const tcg_insn_unit *)value); 338 case R_ARM_PC13: 339 return reloc_pc13(code_ptr, (const tcg_insn_unit *)value); 340 case R_ARM_PC11: 341 return reloc_pc11(code_ptr, (const tcg_insn_unit *)value); 342 case R_ARM_PC8: 343 return reloc_pc8(code_ptr, (const tcg_insn_unit *)value); 344 default: 345 g_assert_not_reached(); 346 } 347} 348 349#define TCG_CT_CONST_ARM 0x100 350#define TCG_CT_CONST_INV 0x200 351#define TCG_CT_CONST_NEG 0x400 352#define TCG_CT_CONST_ZERO 0x800 353#define TCG_CT_CONST_ORRI 0x1000 354#define TCG_CT_CONST_ANDI 0x2000 355 356#define ALL_GENERAL_REGS 0xffffu 357#define ALL_VECTOR_REGS 0xffff0000u 358 359/* 360 * r0-r3 will be overwritten when reading the tlb entry (system-mode only); 361 * r14 will be overwritten by the BLNE branching to the slow path. 362 */ 363#define ALL_QLDST_REGS \ 364 (ALL_GENERAL_REGS & ~((tcg_use_softmmu ? 0xf : 0) | (1 << TCG_REG_R14))) 365 366/* 367 * ARM immediates for ALU instructions are made of an unsigned 8-bit 368 * right-rotated by an even amount between 0 and 30. 369 * 370 * Return < 0 if @imm cannot be encoded, else the entire imm12 field. 371 */ 372static int encode_imm(uint32_t imm) 373{ 374 uint32_t rot, imm8; 375 376 /* Simple case, no rotation required. */ 377 if ((imm & ~0xff) == 0) { 378 return imm; 379 } 380 381 /* Next, try a simple even shift. */ 382 rot = ctz32(imm) & ~1; 383 imm8 = imm >> rot; 384 rot = 32 - rot; 385 if ((imm8 & ~0xff) == 0) { 386 goto found; 387 } 388 389 /* 390 * Finally, try harder with rotations. 391 * The ctz test above will have taken care of rotates >= 8. 392 */ 393 for (rot = 2; rot < 8; rot += 2) { 394 imm8 = rol32(imm, rot); 395 if ((imm8 & ~0xff) == 0) { 396 goto found; 397 } 398 } 399 /* Fail: imm cannot be encoded. */ 400 return -1; 401 402 found: 403 /* Note that rot is even, and we discard bit 0 by shifting by 7. */ 404 return rot << 7 | imm8; 405} 406 407static int encode_imm_nofail(uint32_t imm) 408{ 409 int ret = encode_imm(imm); 410 tcg_debug_assert(ret >= 0); 411 return ret; 412} 413 414static bool check_fit_imm(uint32_t imm) 415{ 416 return encode_imm(imm) >= 0; 417} 418 419/* Return true if v16 is a valid 16-bit shifted immediate. */ 420static bool is_shimm16(uint16_t v16, int *cmode, int *imm8) 421{ 422 if (v16 == (v16 & 0xff)) { 423 *cmode = 0x8; 424 *imm8 = v16 & 0xff; 425 return true; 426 } else if (v16 == (v16 & 0xff00)) { 427 *cmode = 0xa; 428 *imm8 = v16 >> 8; 429 return true; 430 } 431 return false; 432} 433 434/* Return true if v32 is a valid 32-bit shifted immediate. */ 435static bool is_shimm32(uint32_t v32, int *cmode, int *imm8) 436{ 437 if (v32 == (v32 & 0xff)) { 438 *cmode = 0x0; 439 *imm8 = v32 & 0xff; 440 return true; 441 } else if (v32 == (v32 & 0xff00)) { 442 *cmode = 0x2; 443 *imm8 = (v32 >> 8) & 0xff; 444 return true; 445 } else if (v32 == (v32 & 0xff0000)) { 446 *cmode = 0x4; 447 *imm8 = (v32 >> 16) & 0xff; 448 return true; 449 } else if (v32 == (v32 & 0xff000000)) { 450 *cmode = 0x6; 451 *imm8 = v32 >> 24; 452 return true; 453 } 454 return false; 455} 456 457/* Return true if v32 is a valid 32-bit shifting ones immediate. */ 458static bool is_soimm32(uint32_t v32, int *cmode, int *imm8) 459{ 460 if ((v32 & 0xffff00ff) == 0xff) { 461 *cmode = 0xc; 462 *imm8 = (v32 >> 8) & 0xff; 463 return true; 464 } else if ((v32 & 0xff00ffff) == 0xffff) { 465 *cmode = 0xd; 466 *imm8 = (v32 >> 16) & 0xff; 467 return true; 468 } 469 return false; 470} 471 472/* 473 * Return non-zero if v32 can be formed by MOVI+ORR. 474 * Place the parameters for MOVI in (cmode, imm8). 475 * Return the cmode for ORR; the imm8 can be had via extraction from v32. 476 */ 477static int is_shimm32_pair(uint32_t v32, int *cmode, int *imm8) 478{ 479 int i; 480 481 for (i = 6; i > 0; i -= 2) { 482 /* Mask out one byte we can add with ORR. */ 483 uint32_t tmp = v32 & ~(0xffu << (i * 4)); 484 if (is_shimm32(tmp, cmode, imm8) || 485 is_soimm32(tmp, cmode, imm8)) { 486 break; 487 } 488 } 489 return i; 490} 491 492/* Return true if V is a valid 16-bit or 32-bit shifted immediate. */ 493static bool is_shimm1632(uint32_t v32, int *cmode, int *imm8) 494{ 495 if (v32 == deposit32(v32, 16, 16, v32)) { 496 return is_shimm16(v32, cmode, imm8); 497 } else { 498 return is_shimm32(v32, cmode, imm8); 499 } 500} 501 502/* Test if a constant matches the constraint. 503 * TODO: define constraints for: 504 * 505 * ldr/str offset: between -0xfff and 0xfff 506 * ldrh/strh offset: between -0xff and 0xff 507 * mov operand2: values represented with x << (2 * y), x < 0x100 508 * add, sub, eor...: ditto 509 */ 510static bool tcg_target_const_match(int64_t val, int ct, 511 TCGType type, TCGCond cond, int vece) 512{ 513 if (ct & TCG_CT_CONST) { 514 return 1; 515 } else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val)) { 516 return 1; 517 } else if ((ct & TCG_CT_CONST_INV) && check_fit_imm(~val)) { 518 return 1; 519 } else if ((ct & TCG_CT_CONST_NEG) && check_fit_imm(-val)) { 520 return 1; 521 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 522 return 1; 523 } 524 525 switch (ct & (TCG_CT_CONST_ORRI | TCG_CT_CONST_ANDI)) { 526 case 0: 527 break; 528 case TCG_CT_CONST_ANDI: 529 val = ~val; 530 /* fallthru */ 531 case TCG_CT_CONST_ORRI: 532 if (val == deposit64(val, 32, 32, val)) { 533 int cmode, imm8; 534 return is_shimm1632(val, &cmode, &imm8); 535 } 536 break; 537 default: 538 /* Both bits should not be set for the same insn. */ 539 g_assert_not_reached(); 540 } 541 542 return 0; 543} 544 545static void tcg_out_b_imm(TCGContext *s, ARMCond cond, int32_t offset) 546{ 547 tcg_out32(s, (cond << 28) | INSN_B | 548 (((offset - 8) >> 2) & 0x00ffffff)); 549} 550 551static void tcg_out_bl_imm(TCGContext *s, ARMCond cond, int32_t offset) 552{ 553 tcg_out32(s, (cond << 28) | 0x0b000000 | 554 (((offset - 8) >> 2) & 0x00ffffff)); 555} 556 557static void tcg_out_blx_reg(TCGContext *s, ARMCond cond, TCGReg rn) 558{ 559 tcg_out32(s, (cond << 28) | 0x012fff30 | rn); 560} 561 562static void tcg_out_blx_imm(TCGContext *s, int32_t offset) 563{ 564 tcg_out32(s, 0xfa000000 | ((offset & 2) << 23) | 565 (((offset - 8) >> 2) & 0x00ffffff)); 566} 567 568static void tcg_out_dat_reg(TCGContext *s, ARMCond cond, ARMInsn opc, 569 TCGReg rd, TCGReg rn, TCGReg rm, int shift) 570{ 571 tcg_out32(s, (cond << 28) | (0 << 25) | opc | 572 (rn << 16) | (rd << 12) | shift | rm); 573} 574 575static void tcg_out_mov_reg(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rm) 576{ 577 /* Simple reg-reg move, optimising out the 'do nothing' case */ 578 if (rd != rm) { 579 tcg_out_dat_reg(s, cond, ARITH_MOV, rd, 0, rm, SHIFT_IMM_LSL(0)); 580 } 581} 582 583static void tcg_out_bx_reg(TCGContext *s, ARMCond cond, TCGReg rn) 584{ 585 tcg_out32(s, (cond << 28) | 0x012fff10 | rn); 586} 587 588static void tcg_out_b_reg(TCGContext *s, ARMCond cond, TCGReg rn) 589{ 590 /* 591 * Unless the C portion of QEMU is compiled as thumb, we don't need 592 * true BX semantics; merely a branch to an address held in a register. 593 */ 594 tcg_out_bx_reg(s, cond, rn); 595} 596 597static void tcg_out_dat_imm(TCGContext *s, ARMCond cond, ARMInsn opc, 598 TCGReg rd, TCGReg rn, int im) 599{ 600 tcg_out32(s, (cond << 28) | (1 << 25) | opc | 601 (rn << 16) | (rd << 12) | im); 602} 603 604static void tcg_out_ldstm(TCGContext *s, ARMCond cond, ARMInsn opc, 605 TCGReg rn, uint16_t mask) 606{ 607 tcg_out32(s, (cond << 28) | opc | (rn << 16) | mask); 608} 609 610/* Note that this routine is used for both LDR and LDRH formats, so we do 611 not wish to include an immediate shift at this point. */ 612static void tcg_out_memop_r(TCGContext *s, ARMCond cond, ARMInsn opc, TCGReg rt, 613 TCGReg rn, TCGReg rm, bool u, bool p, bool w) 614{ 615 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) 616 | (w << 21) | (rn << 16) | (rt << 12) | rm); 617} 618 619static void tcg_out_memop_8(TCGContext *s, ARMCond cond, ARMInsn opc, TCGReg rt, 620 TCGReg rn, int imm8, bool p, bool w) 621{ 622 bool u = 1; 623 if (imm8 < 0) { 624 imm8 = -imm8; 625 u = 0; 626 } 627 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | 628 (rn << 16) | (rt << 12) | ((imm8 & 0xf0) << 4) | (imm8 & 0xf)); 629} 630 631static void tcg_out_memop_12(TCGContext *s, ARMCond cond, ARMInsn opc, 632 TCGReg rt, TCGReg rn, int imm12, bool p, bool w) 633{ 634 bool u = 1; 635 if (imm12 < 0) { 636 imm12 = -imm12; 637 u = 0; 638 } 639 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | 640 (rn << 16) | (rt << 12) | imm12); 641} 642 643static void tcg_out_ld32_12(TCGContext *s, ARMCond cond, TCGReg rt, 644 TCGReg rn, int imm12) 645{ 646 tcg_out_memop_12(s, cond, INSN_LDR_IMM, rt, rn, imm12, 1, 0); 647} 648 649static void tcg_out_st32_12(TCGContext *s, ARMCond cond, TCGReg rt, 650 TCGReg rn, int imm12) 651{ 652 tcg_out_memop_12(s, cond, INSN_STR_IMM, rt, rn, imm12, 1, 0); 653} 654 655static void tcg_out_ld32_r(TCGContext *s, ARMCond cond, TCGReg rt, 656 TCGReg rn, TCGReg rm) 657{ 658 tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 0); 659} 660 661static void tcg_out_st32_r(TCGContext *s, ARMCond cond, TCGReg rt, 662 TCGReg rn, TCGReg rm) 663{ 664 tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 0); 665} 666 667static void tcg_out_ldrd_8(TCGContext *s, ARMCond cond, TCGReg rt, 668 TCGReg rn, int imm8) 669{ 670 tcg_out_memop_8(s, cond, INSN_LDRD_IMM, rt, rn, imm8, 1, 0); 671} 672 673static void tcg_out_ldrd_r(TCGContext *s, ARMCond cond, TCGReg rt, 674 TCGReg rn, TCGReg rm) 675{ 676 tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 0); 677} 678 679static void tcg_out_strd_8(TCGContext *s, ARMCond cond, TCGReg rt, 680 TCGReg rn, int imm8) 681{ 682 tcg_out_memop_8(s, cond, INSN_STRD_IMM, rt, rn, imm8, 1, 0); 683} 684 685static void tcg_out_strd_r(TCGContext *s, ARMCond cond, TCGReg rt, 686 TCGReg rn, TCGReg rm) 687{ 688 tcg_out_memop_r(s, cond, INSN_STRD_REG, rt, rn, rm, 1, 1, 0); 689} 690 691/* Register pre-increment with base writeback. */ 692static void tcg_out_ld32_rwb(TCGContext *s, ARMCond cond, TCGReg rt, 693 TCGReg rn, TCGReg rm) 694{ 695 tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 1); 696} 697 698static void tcg_out_st32_rwb(TCGContext *s, ARMCond cond, TCGReg rt, 699 TCGReg rn, TCGReg rm) 700{ 701 tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 1); 702} 703 704static void tcg_out_ld16u_8(TCGContext *s, ARMCond cond, TCGReg rt, 705 TCGReg rn, int imm8) 706{ 707 tcg_out_memop_8(s, cond, INSN_LDRH_IMM, rt, rn, imm8, 1, 0); 708} 709 710static void tcg_out_st16_8(TCGContext *s, ARMCond cond, TCGReg rt, 711 TCGReg rn, int imm8) 712{ 713 tcg_out_memop_8(s, cond, INSN_STRH_IMM, rt, rn, imm8, 1, 0); 714} 715 716static void tcg_out_ld16u_r(TCGContext *s, ARMCond cond, TCGReg rt, 717 TCGReg rn, TCGReg rm) 718{ 719 tcg_out_memop_r(s, cond, INSN_LDRH_REG, rt, rn, rm, 1, 1, 0); 720} 721 722static void tcg_out_st16_r(TCGContext *s, ARMCond cond, TCGReg rt, 723 TCGReg rn, TCGReg rm) 724{ 725 tcg_out_memop_r(s, cond, INSN_STRH_REG, rt, rn, rm, 1, 1, 0); 726} 727 728static void tcg_out_ld16s_8(TCGContext *s, ARMCond cond, TCGReg rt, 729 TCGReg rn, int imm8) 730{ 731 tcg_out_memop_8(s, cond, INSN_LDRSH_IMM, rt, rn, imm8, 1, 0); 732} 733 734static void tcg_out_ld16s_r(TCGContext *s, ARMCond cond, TCGReg rt, 735 TCGReg rn, TCGReg rm) 736{ 737 tcg_out_memop_r(s, cond, INSN_LDRSH_REG, rt, rn, rm, 1, 1, 0); 738} 739 740static void tcg_out_ld8_12(TCGContext *s, ARMCond cond, TCGReg rt, 741 TCGReg rn, int imm12) 742{ 743 tcg_out_memop_12(s, cond, INSN_LDRB_IMM, rt, rn, imm12, 1, 0); 744} 745 746static void tcg_out_st8_12(TCGContext *s, ARMCond cond, TCGReg rt, 747 TCGReg rn, int imm12) 748{ 749 tcg_out_memop_12(s, cond, INSN_STRB_IMM, rt, rn, imm12, 1, 0); 750} 751 752static void tcg_out_ld8_r(TCGContext *s, ARMCond cond, TCGReg rt, 753 TCGReg rn, TCGReg rm) 754{ 755 tcg_out_memop_r(s, cond, INSN_LDRB_REG, rt, rn, rm, 1, 1, 0); 756} 757 758static void tcg_out_st8_r(TCGContext *s, ARMCond cond, TCGReg rt, 759 TCGReg rn, TCGReg rm) 760{ 761 tcg_out_memop_r(s, cond, INSN_STRB_REG, rt, rn, rm, 1, 1, 0); 762} 763 764static void tcg_out_ld8s_8(TCGContext *s, ARMCond cond, TCGReg rt, 765 TCGReg rn, int imm8) 766{ 767 tcg_out_memop_8(s, cond, INSN_LDRSB_IMM, rt, rn, imm8, 1, 0); 768} 769 770static void tcg_out_ld8s_r(TCGContext *s, ARMCond cond, TCGReg rt, 771 TCGReg rn, TCGReg rm) 772{ 773 tcg_out_memop_r(s, cond, INSN_LDRSB_REG, rt, rn, rm, 1, 1, 0); 774} 775 776static void tcg_out_movi_pool(TCGContext *s, ARMCond cond, 777 TCGReg rd, uint32_t arg) 778{ 779 new_pool_label(s, arg, R_ARM_PC13, s->code_ptr, 0); 780 tcg_out_ld32_12(s, cond, rd, TCG_REG_PC, 0); 781} 782 783static void tcg_out_movi32(TCGContext *s, ARMCond cond, 784 TCGReg rd, uint32_t arg) 785{ 786 int imm12, diff, opc, sh1, sh2; 787 uint32_t tt0, tt1, tt2; 788 789 /* Check a single MOV/MVN before anything else. */ 790 imm12 = encode_imm(arg); 791 if (imm12 >= 0) { 792 tcg_out_dat_imm(s, cond, ARITH_MOV, rd, 0, imm12); 793 return; 794 } 795 imm12 = encode_imm(~arg); 796 if (imm12 >= 0) { 797 tcg_out_dat_imm(s, cond, ARITH_MVN, rd, 0, imm12); 798 return; 799 } 800 801 /* Check for a pc-relative address. This will usually be the TB, 802 or within the TB, which is immediately before the code block. */ 803 diff = tcg_pcrel_diff(s, (void *)arg) - 8; 804 if (diff >= 0) { 805 imm12 = encode_imm(diff); 806 if (imm12 >= 0) { 807 tcg_out_dat_imm(s, cond, ARITH_ADD, rd, TCG_REG_PC, imm12); 808 return; 809 } 810 } else { 811 imm12 = encode_imm(-diff); 812 if (imm12 >= 0) { 813 tcg_out_dat_imm(s, cond, ARITH_SUB, rd, TCG_REG_PC, imm12); 814 return; 815 } 816 } 817 818 /* Use movw + movt. */ 819 if (use_armv7_instructions) { 820 /* movw */ 821 tcg_out32(s, (cond << 28) | 0x03000000 | (rd << 12) 822 | ((arg << 4) & 0x000f0000) | (arg & 0xfff)); 823 if (arg & 0xffff0000) { 824 /* movt */ 825 tcg_out32(s, (cond << 28) | 0x03400000 | (rd << 12) 826 | ((arg >> 12) & 0x000f0000) | ((arg >> 16) & 0xfff)); 827 } 828 return; 829 } 830 831 /* Look for sequences of two insns. If we have lots of 1's, we can 832 shorten the sequence by beginning with mvn and then clearing 833 higher bits with eor. */ 834 tt0 = arg; 835 opc = ARITH_MOV; 836 if (ctpop32(arg) > 16) { 837 tt0 = ~arg; 838 opc = ARITH_MVN; 839 } 840 sh1 = ctz32(tt0) & ~1; 841 tt1 = tt0 & ~(0xff << sh1); 842 sh2 = ctz32(tt1) & ~1; 843 tt2 = tt1 & ~(0xff << sh2); 844 if (tt2 == 0) { 845 int rot; 846 847 rot = ((32 - sh1) << 7) & 0xf00; 848 tcg_out_dat_imm(s, cond, opc, rd, 0, ((tt0 >> sh1) & 0xff) | rot); 849 rot = ((32 - sh2) << 7) & 0xf00; 850 tcg_out_dat_imm(s, cond, ARITH_EOR, rd, rd, 851 ((tt0 >> sh2) & 0xff) | rot); 852 return; 853 } 854 855 /* Otherwise, drop it into the constant pool. */ 856 tcg_out_movi_pool(s, cond, rd, arg); 857} 858 859/* 860 * Emit either the reg,imm or reg,reg form of a data-processing insn. 861 * rhs must satisfy the "rI" constraint. 862 */ 863static void tcg_out_dat_rI(TCGContext *s, ARMCond cond, ARMInsn opc, 864 TCGReg dst, TCGReg lhs, TCGArg rhs, int rhs_is_const) 865{ 866 if (rhs_is_const) { 867 tcg_out_dat_imm(s, cond, opc, dst, lhs, encode_imm_nofail(rhs)); 868 } else { 869 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); 870 } 871} 872 873/* 874 * Emit either the reg,imm or reg,reg form of a data-processing insn. 875 * rhs must satisfy the "rIK" constraint. 876 */ 877static void tcg_out_dat_rIK(TCGContext *s, ARMCond cond, ARMInsn opc, 878 ARMInsn opinv, TCGReg dst, TCGReg lhs, TCGArg rhs, 879 bool rhs_is_const) 880{ 881 if (rhs_is_const) { 882 int imm12 = encode_imm(rhs); 883 if (imm12 < 0) { 884 imm12 = encode_imm_nofail(~rhs); 885 opc = opinv; 886 } 887 tcg_out_dat_imm(s, cond, opc, dst, lhs, imm12); 888 } else { 889 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); 890 } 891} 892 893static void tcg_out_dat_rIN(TCGContext *s, ARMCond cond, ARMInsn opc, 894 ARMInsn opneg, TCGReg dst, TCGReg lhs, TCGArg rhs, 895 bool rhs_is_const) 896{ 897 /* Emit either the reg,imm or reg,reg form of a data-processing insn. 898 * rhs must satisfy the "rIN" constraint. 899 */ 900 if (rhs_is_const) { 901 int imm12 = encode_imm(rhs); 902 if (imm12 < 0) { 903 imm12 = encode_imm_nofail(-rhs); 904 opc = opneg; 905 } 906 tcg_out_dat_imm(s, cond, opc, dst, lhs, imm12); 907 } else { 908 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); 909 } 910} 911 912static void tcg_out_mul32(TCGContext *s, ARMCond cond, TCGReg rd, 913 TCGReg rn, TCGReg rm) 914{ 915 /* mul */ 916 tcg_out32(s, (cond << 28) | 0x90 | (rd << 16) | (rm << 8) | rn); 917} 918 919static void tcg_out_umull32(TCGContext *s, ARMCond cond, TCGReg rd0, 920 TCGReg rd1, TCGReg rn, TCGReg rm) 921{ 922 /* umull */ 923 tcg_out32(s, (cond << 28) | 0x00800090 | 924 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); 925} 926 927static void tcg_out_smull32(TCGContext *s, ARMCond cond, TCGReg rd0, 928 TCGReg rd1, TCGReg rn, TCGReg rm) 929{ 930 /* smull */ 931 tcg_out32(s, (cond << 28) | 0x00c00090 | 932 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); 933} 934 935static void tcg_out_sdiv(TCGContext *s, ARMCond cond, 936 TCGReg rd, TCGReg rn, TCGReg rm) 937{ 938 tcg_out32(s, 0x0710f010 | (cond << 28) | (rd << 16) | rn | (rm << 8)); 939} 940 941static void tcg_out_udiv(TCGContext *s, ARMCond cond, 942 TCGReg rd, TCGReg rn, TCGReg rm) 943{ 944 tcg_out32(s, 0x0730f010 | (cond << 28) | (rd << 16) | rn | (rm << 8)); 945} 946 947static void tcg_out_ext8s(TCGContext *s, TCGType t, TCGReg rd, TCGReg rn) 948{ 949 /* sxtb */ 950 tcg_out32(s, 0x06af0070 | (COND_AL << 28) | (rd << 12) | rn); 951} 952 953static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rn) 954{ 955 tcg_out_dat_imm(s, COND_AL, ARITH_AND, rd, rn, 0xff); 956} 957 958static void tcg_out_ext16s(TCGContext *s, TCGType t, TCGReg rd, TCGReg rn) 959{ 960 /* sxth */ 961 tcg_out32(s, 0x06bf0070 | (COND_AL << 28) | (rd << 12) | rn); 962} 963 964static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rn) 965{ 966 /* uxth */ 967 tcg_out32(s, 0x06ff0070 | (COND_AL << 28) | (rd << 12) | rn); 968} 969 970static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rn) 971{ 972 g_assert_not_reached(); 973} 974 975static void tcg_out_ext32u(TCGContext *s, TCGReg rd, TCGReg rn) 976{ 977 g_assert_not_reached(); 978} 979 980static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rn) 981{ 982 g_assert_not_reached(); 983} 984 985static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rn) 986{ 987 g_assert_not_reached(); 988} 989 990static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rn) 991{ 992 g_assert_not_reached(); 993} 994 995static void tcg_out_bswap16(TCGContext *s, ARMCond cond, 996 TCGReg rd, TCGReg rn, int flags) 997{ 998 if (flags & TCG_BSWAP_OS) { 999 /* revsh */ 1000 tcg_out32(s, 0x06ff0fb0 | (cond << 28) | (rd << 12) | rn); 1001 return; 1002 } 1003 1004 /* rev16 */ 1005 tcg_out32(s, 0x06bf0fb0 | (cond << 28) | (rd << 12) | rn); 1006 if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 1007 /* uxth */ 1008 tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | rd); 1009 } 1010} 1011 1012static void tcg_out_bswap32(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rn) 1013{ 1014 /* rev */ 1015 tcg_out32(s, 0x06bf0f30 | (cond << 28) | (rd << 12) | rn); 1016} 1017 1018static void tcg_out_deposit(TCGContext *s, ARMCond cond, TCGReg rd, 1019 TCGArg a1, int ofs, int len, bool const_a1) 1020{ 1021 if (const_a1) { 1022 /* bfi becomes bfc with rn == 15. */ 1023 a1 = 15; 1024 } 1025 /* bfi/bfc */ 1026 tcg_out32(s, 0x07c00010 | (cond << 28) | (rd << 12) | a1 1027 | (ofs << 7) | ((ofs + len - 1) << 16)); 1028} 1029 1030static void tcg_out_extract(TCGContext *s, ARMCond cond, TCGReg rd, 1031 TCGReg rn, int ofs, int len) 1032{ 1033 /* According to gcc, AND can be faster. */ 1034 if (ofs == 0 && len <= 8) { 1035 tcg_out_dat_imm(s, cond, ARITH_AND, rd, rn, 1036 encode_imm_nofail((1 << len) - 1)); 1037 return; 1038 } 1039 1040 if (use_armv7_instructions) { 1041 /* ubfx */ 1042 tcg_out32(s, 0x07e00050 | (cond << 28) | (rd << 12) | rn 1043 | (ofs << 7) | ((len - 1) << 16)); 1044 return; 1045 } 1046 1047 assert(ofs % 8 == 0); 1048 switch (len) { 1049 case 8: 1050 /* uxtb */ 1051 tcg_out32(s, 0x06ef0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn); 1052 break; 1053 case 16: 1054 /* uxth */ 1055 tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn); 1056 break; 1057 default: 1058 g_assert_not_reached(); 1059 } 1060} 1061 1062static void tcg_out_sextract(TCGContext *s, ARMCond cond, TCGReg rd, 1063 TCGReg rn, int ofs, int len) 1064{ 1065 if (use_armv7_instructions) { 1066 /* sbfx */ 1067 tcg_out32(s, 0x07a00050 | (cond << 28) | (rd << 12) | rn 1068 | (ofs << 7) | ((len - 1) << 16)); 1069 return; 1070 } 1071 1072 assert(ofs % 8 == 0); 1073 switch (len) { 1074 case 8: 1075 /* sxtb */ 1076 tcg_out32(s, 0x06af0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn); 1077 break; 1078 case 16: 1079 /* sxth */ 1080 tcg_out32(s, 0x06bf0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn); 1081 break; 1082 default: 1083 g_assert_not_reached(); 1084 } 1085} 1086 1087 1088static void tcg_out_ld32u(TCGContext *s, ARMCond cond, 1089 TCGReg rd, TCGReg rn, int32_t offset) 1090{ 1091 if (offset > 0xfff || offset < -0xfff) { 1092 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1093 tcg_out_ld32_r(s, cond, rd, rn, TCG_REG_TMP); 1094 } else 1095 tcg_out_ld32_12(s, cond, rd, rn, offset); 1096} 1097 1098static void tcg_out_st32(TCGContext *s, ARMCond cond, 1099 TCGReg rd, TCGReg rn, int32_t offset) 1100{ 1101 if (offset > 0xfff || offset < -0xfff) { 1102 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1103 tcg_out_st32_r(s, cond, rd, rn, TCG_REG_TMP); 1104 } else 1105 tcg_out_st32_12(s, cond, rd, rn, offset); 1106} 1107 1108static void tcg_out_ld16u(TCGContext *s, ARMCond cond, 1109 TCGReg rd, TCGReg rn, int32_t offset) 1110{ 1111 if (offset > 0xff || offset < -0xff) { 1112 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1113 tcg_out_ld16u_r(s, cond, rd, rn, TCG_REG_TMP); 1114 } else 1115 tcg_out_ld16u_8(s, cond, rd, rn, offset); 1116} 1117 1118static void tcg_out_ld16s(TCGContext *s, ARMCond cond, 1119 TCGReg rd, TCGReg rn, int32_t offset) 1120{ 1121 if (offset > 0xff || offset < -0xff) { 1122 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1123 tcg_out_ld16s_r(s, cond, rd, rn, TCG_REG_TMP); 1124 } else 1125 tcg_out_ld16s_8(s, cond, rd, rn, offset); 1126} 1127 1128static void tcg_out_st16(TCGContext *s, ARMCond cond, 1129 TCGReg rd, TCGReg rn, int32_t offset) 1130{ 1131 if (offset > 0xff || offset < -0xff) { 1132 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1133 tcg_out_st16_r(s, cond, rd, rn, TCG_REG_TMP); 1134 } else 1135 tcg_out_st16_8(s, cond, rd, rn, offset); 1136} 1137 1138static void tcg_out_ld8u(TCGContext *s, ARMCond cond, 1139 TCGReg rd, TCGReg rn, int32_t offset) 1140{ 1141 if (offset > 0xfff || offset < -0xfff) { 1142 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1143 tcg_out_ld8_r(s, cond, rd, rn, TCG_REG_TMP); 1144 } else 1145 tcg_out_ld8_12(s, cond, rd, rn, offset); 1146} 1147 1148static void tcg_out_ld8s(TCGContext *s, ARMCond cond, 1149 TCGReg rd, TCGReg rn, int32_t offset) 1150{ 1151 if (offset > 0xff || offset < -0xff) { 1152 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1153 tcg_out_ld8s_r(s, cond, rd, rn, TCG_REG_TMP); 1154 } else 1155 tcg_out_ld8s_8(s, cond, rd, rn, offset); 1156} 1157 1158static void tcg_out_st8(TCGContext *s, ARMCond cond, 1159 TCGReg rd, TCGReg rn, int32_t offset) 1160{ 1161 if (offset > 0xfff || offset < -0xfff) { 1162 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1163 tcg_out_st8_r(s, cond, rd, rn, TCG_REG_TMP); 1164 } else 1165 tcg_out_st8_12(s, cond, rd, rn, offset); 1166} 1167 1168/* 1169 * The _goto case is normally between TBs within the same code buffer, and 1170 * with the code buffer limited to 16MB we wouldn't need the long case. 1171 * But we also use it for the tail-call to the qemu_ld/st helpers, which does. 1172 */ 1173static void tcg_out_goto(TCGContext *s, ARMCond cond, const tcg_insn_unit *addr) 1174{ 1175 intptr_t addri = (intptr_t)addr; 1176 ptrdiff_t disp = tcg_pcrel_diff(s, addr); 1177 bool arm_mode = !(addri & 1); 1178 1179 if (arm_mode && disp - 8 < 0x01fffffd && disp - 8 > -0x01fffffd) { 1180 tcg_out_b_imm(s, cond, disp); 1181 return; 1182 } 1183 1184 /* LDR is interworking from v5t. */ 1185 tcg_out_movi_pool(s, cond, TCG_REG_PC, addri); 1186} 1187 1188/* 1189 * The call case is mostly used for helpers - so it's not unreasonable 1190 * for them to be beyond branch range. 1191 */ 1192static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *addr) 1193{ 1194 intptr_t addri = (intptr_t)addr; 1195 ptrdiff_t disp = tcg_pcrel_diff(s, addr); 1196 bool arm_mode = !(addri & 1); 1197 1198 if (disp - 8 < 0x02000000 && disp - 8 >= -0x02000000) { 1199 if (arm_mode) { 1200 tcg_out_bl_imm(s, COND_AL, disp); 1201 } else { 1202 tcg_out_blx_imm(s, disp); 1203 } 1204 return; 1205 } 1206 1207 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri); 1208 tcg_out_blx_reg(s, COND_AL, TCG_REG_TMP); 1209} 1210 1211static void tcg_out_call(TCGContext *s, const tcg_insn_unit *addr, 1212 const TCGHelperInfo *info) 1213{ 1214 tcg_out_call_int(s, addr); 1215} 1216 1217static void tcg_out_goto_label(TCGContext *s, ARMCond cond, TCGLabel *l) 1218{ 1219 if (l->has_value) { 1220 tcg_out_goto(s, cond, l->u.value_ptr); 1221 } else { 1222 tcg_out_reloc(s, s->code_ptr, R_ARM_PC24, l, 0); 1223 tcg_out_b_imm(s, cond, 0); 1224 } 1225} 1226 1227static void tcg_out_mb(TCGContext *s, TCGArg a0) 1228{ 1229 if (use_armv7_instructions) { 1230 tcg_out32(s, INSN_DMB_ISH); 1231 } else { 1232 tcg_out32(s, INSN_DMB_MCR); 1233 } 1234} 1235 1236static TCGCond tcg_out_cmp(TCGContext *s, TCGCond cond, TCGReg a, 1237 TCGArg b, int b_const) 1238{ 1239 if (!is_tst_cond(cond)) { 1240 tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, a, b, b_const); 1241 return cond; 1242 } 1243 1244 cond = tcg_tst_eqne_cond(cond); 1245 if (b_const) { 1246 int imm12 = encode_imm(b); 1247 1248 /* 1249 * The compare constraints allow rIN, but TST does not support N. 1250 * Be prepared to load the constant into a scratch register. 1251 */ 1252 if (imm12 >= 0) { 1253 tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, a, imm12); 1254 return cond; 1255 } 1256 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, b); 1257 b = TCG_REG_TMP; 1258 } 1259 tcg_out_dat_reg(s, COND_AL, ARITH_TST, 0, a, b, SHIFT_IMM_LSL(0)); 1260 return cond; 1261} 1262 1263static TCGCond tcg_out_cmp2(TCGContext *s, const TCGArg *args, 1264 const int *const_args) 1265{ 1266 TCGReg al = args[0]; 1267 TCGReg ah = args[1]; 1268 TCGArg bl = args[2]; 1269 TCGArg bh = args[3]; 1270 TCGCond cond = args[4]; 1271 int const_bl = const_args[2]; 1272 int const_bh = const_args[3]; 1273 1274 switch (cond) { 1275 case TCG_COND_EQ: 1276 case TCG_COND_NE: 1277 case TCG_COND_LTU: 1278 case TCG_COND_LEU: 1279 case TCG_COND_GTU: 1280 case TCG_COND_GEU: 1281 /* 1282 * We perform a conditional comparison. If the high half is 1283 * equal, then overwrite the flags with the comparison of the 1284 * low half. The resulting flags cover the whole. 1285 */ 1286 tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, ah, bh, const_bh); 1287 tcg_out_dat_rI(s, COND_EQ, ARITH_CMP, 0, al, bl, const_bl); 1288 return cond; 1289 1290 case TCG_COND_TSTEQ: 1291 case TCG_COND_TSTNE: 1292 /* Similar, but with TST instead of CMP. */ 1293 tcg_out_dat_rI(s, COND_AL, ARITH_TST, 0, ah, bh, const_bh); 1294 tcg_out_dat_rI(s, COND_EQ, ARITH_TST, 0, al, bl, const_bl); 1295 return tcg_tst_eqne_cond(cond); 1296 1297 case TCG_COND_LT: 1298 case TCG_COND_GE: 1299 /* We perform a double-word subtraction and examine the result. 1300 We do not actually need the result of the subtract, so the 1301 low part "subtract" is a compare. For the high half we have 1302 no choice but to compute into a temporary. */ 1303 tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, al, bl, const_bl); 1304 tcg_out_dat_rI(s, COND_AL, ARITH_SBC | TO_CPSR, 1305 TCG_REG_TMP, ah, bh, const_bh); 1306 return cond; 1307 1308 case TCG_COND_LE: 1309 case TCG_COND_GT: 1310 /* Similar, but with swapped arguments, via reversed subtract. */ 1311 tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR, 1312 TCG_REG_TMP, al, bl, const_bl); 1313 tcg_out_dat_rI(s, COND_AL, ARITH_RSC | TO_CPSR, 1314 TCG_REG_TMP, ah, bh, const_bh); 1315 return tcg_swap_cond(cond); 1316 1317 default: 1318 g_assert_not_reached(); 1319 } 1320} 1321 1322/* 1323 * Note that TCGReg references Q-registers. 1324 * Q-regno = 2 * D-regno, so shift left by 1 while inserting. 1325 */ 1326static uint32_t encode_vd(TCGReg rd) 1327{ 1328 tcg_debug_assert(rd >= TCG_REG_Q0); 1329 return (extract32(rd, 3, 1) << 22) | (extract32(rd, 0, 3) << 13); 1330} 1331 1332static uint32_t encode_vn(TCGReg rn) 1333{ 1334 tcg_debug_assert(rn >= TCG_REG_Q0); 1335 return (extract32(rn, 3, 1) << 7) | (extract32(rn, 0, 3) << 17); 1336} 1337 1338static uint32_t encode_vm(TCGReg rm) 1339{ 1340 tcg_debug_assert(rm >= TCG_REG_Q0); 1341 return (extract32(rm, 3, 1) << 5) | (extract32(rm, 0, 3) << 1); 1342} 1343 1344static void tcg_out_vreg2(TCGContext *s, ARMInsn insn, int q, int vece, 1345 TCGReg d, TCGReg m) 1346{ 1347 tcg_out32(s, insn | (vece << 18) | (q << 6) | 1348 encode_vd(d) | encode_vm(m)); 1349} 1350 1351static void tcg_out_vreg3(TCGContext *s, ARMInsn insn, int q, int vece, 1352 TCGReg d, TCGReg n, TCGReg m) 1353{ 1354 tcg_out32(s, insn | (vece << 20) | (q << 6) | 1355 encode_vd(d) | encode_vn(n) | encode_vm(m)); 1356} 1357 1358static void tcg_out_vmovi(TCGContext *s, TCGReg rd, 1359 int q, int op, int cmode, uint8_t imm8) 1360{ 1361 tcg_out32(s, INSN_VMOVI | encode_vd(rd) | (q << 6) | (op << 5) 1362 | (cmode << 8) | extract32(imm8, 0, 4) 1363 | (extract32(imm8, 4, 3) << 16) 1364 | (extract32(imm8, 7, 1) << 24)); 1365} 1366 1367static void tcg_out_vshifti(TCGContext *s, ARMInsn insn, int q, 1368 TCGReg rd, TCGReg rm, int l_imm6) 1369{ 1370 tcg_out32(s, insn | (q << 6) | encode_vd(rd) | encode_vm(rm) | 1371 (extract32(l_imm6, 6, 1) << 7) | 1372 (extract32(l_imm6, 0, 6) << 16)); 1373} 1374 1375static void tcg_out_vldst(TCGContext *s, ARMInsn insn, 1376 TCGReg rd, TCGReg rn, int offset) 1377{ 1378 if (offset != 0) { 1379 if (check_fit_imm(offset) || check_fit_imm(-offset)) { 1380 tcg_out_dat_rIN(s, COND_AL, ARITH_ADD, ARITH_SUB, 1381 TCG_REG_TMP, rn, offset, true); 1382 } else { 1383 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, offset); 1384 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, 1385 TCG_REG_TMP, TCG_REG_TMP, rn, 0); 1386 } 1387 rn = TCG_REG_TMP; 1388 } 1389 tcg_out32(s, insn | (rn << 16) | encode_vd(rd) | 0xf); 1390} 1391 1392typedef struct { 1393 ARMCond cond; 1394 TCGReg base; 1395 int index; 1396 bool index_scratch; 1397 TCGAtomAlign aa; 1398} HostAddress; 1399 1400bool tcg_target_has_memory_bswap(MemOp memop) 1401{ 1402 return false; 1403} 1404 1405static TCGReg ldst_ra_gen(TCGContext *s, const TCGLabelQemuLdst *l, int arg) 1406{ 1407 /* We arrive at the slow path via "BLNE", so R14 contains l->raddr. */ 1408 return TCG_REG_R14; 1409} 1410 1411static const TCGLdstHelperParam ldst_helper_param = { 1412 .ra_gen = ldst_ra_gen, 1413 .ntmp = 1, 1414 .tmp = { TCG_REG_TMP }, 1415}; 1416 1417static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1418{ 1419 MemOp opc = get_memop(lb->oi); 1420 1421 if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1422 return false; 1423 } 1424 1425 tcg_out_ld_helper_args(s, lb, &ldst_helper_param); 1426 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE]); 1427 tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param); 1428 1429 tcg_out_goto(s, COND_AL, lb->raddr); 1430 return true; 1431} 1432 1433static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1434{ 1435 MemOp opc = get_memop(lb->oi); 1436 1437 if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1438 return false; 1439 } 1440 1441 tcg_out_st_helper_args(s, lb, &ldst_helper_param); 1442 1443 /* Tail-call to the helper, which will return to the fast path. */ 1444 tcg_out_goto(s, COND_AL, qemu_st_helpers[opc & MO_SIZE]); 1445 return true; 1446} 1447 1448/* We expect to use an 9-bit sign-magnitude negative offset from ENV. */ 1449#define MIN_TLB_MASK_TABLE_OFS -256 1450 1451static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1452 TCGReg addr, MemOpIdx oi, bool is_ld) 1453{ 1454 TCGLabelQemuLdst *ldst = NULL; 1455 MemOp opc = get_memop(oi); 1456 unsigned a_mask; 1457 1458 if (tcg_use_softmmu) { 1459 *h = (HostAddress){ 1460 .cond = COND_AL, 1461 .base = addr, 1462 .index = TCG_REG_R1, 1463 .index_scratch = true, 1464 }; 1465 } else { 1466 *h = (HostAddress){ 1467 .cond = COND_AL, 1468 .base = addr, 1469 .index = guest_base ? TCG_REG_GUEST_BASE : -1, 1470 .index_scratch = false, 1471 }; 1472 } 1473 1474 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); 1475 a_mask = (1 << h->aa.align) - 1; 1476 1477 if (tcg_use_softmmu) { 1478 int mem_index = get_mmuidx(oi); 1479 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read) 1480 : offsetof(CPUTLBEntry, addr_write); 1481 int fast_off = tlb_mask_table_ofs(s, mem_index); 1482 unsigned s_mask = (1 << (opc & MO_SIZE)) - 1; 1483 TCGReg t_addr; 1484 1485 ldst = new_ldst_label(s); 1486 ldst->is_ld = is_ld; 1487 ldst->oi = oi; 1488 ldst->addr_reg = addr; 1489 1490 /* Load cpu->neg.tlb.f[mmu_idx].{mask,table} into {r0,r1}. */ 1491 QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0); 1492 QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != 4); 1493 tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off); 1494 1495 /* Extract the tlb index from the address into R0. */ 1496 tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, addr, 1497 SHIFT_IMM_LSR(s->page_bits - CPU_TLB_ENTRY_BITS)); 1498 1499 /* 1500 * Add the tlb_table pointer, creating the CPUTLBEntry address in R1. 1501 * Load the tlb comparator into R2 and the fast path addend into R1. 1502 */ 1503 if (cmp_off == 0) { 1504 tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0); 1505 } else { 1506 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, 1507 TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0); 1508 tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); 1509 } 1510 1511 /* Load the tlb addend. */ 1512 tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R1, 1513 offsetof(CPUTLBEntry, addend)); 1514 1515 /* 1516 * Check alignment, check comparators. 1517 * Do this in 2-4 insns. Use MOVW for v7, if possible, 1518 * to reduce the number of sequential conditional instructions. 1519 * Almost all guests have at least 4k pages, which means that we need 1520 * to clear at least 9 bits even for an 8-byte memory, which means it 1521 * isn't worth checking for an immediate operand for BIC. 1522 * 1523 * For unaligned accesses, test the page of the last unit of alignment. 1524 * This leaves the least significant alignment bits unchanged, and of 1525 * course must be zero. 1526 */ 1527 t_addr = addr; 1528 if (a_mask < s_mask) { 1529 t_addr = TCG_REG_R0; 1530 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, t_addr, 1531 addr, s_mask - a_mask); 1532 } 1533 if (use_armv7_instructions && s->page_bits <= 16) { 1534 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, ~(s->page_mask | a_mask)); 1535 tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP, 1536 t_addr, TCG_REG_TMP, 0); 1537 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, 1538 TCG_REG_R2, TCG_REG_TMP, 0); 1539 } else { 1540 if (a_mask) { 1541 tcg_debug_assert(a_mask <= 0xff); 1542 tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addr, a_mask); 1543 } 1544 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, t_addr, 1545 SHIFT_IMM_LSR(s->page_bits)); 1546 tcg_out_dat_reg(s, (a_mask ? COND_EQ : COND_AL), ARITH_CMP, 1547 0, TCG_REG_R2, TCG_REG_TMP, 1548 SHIFT_IMM_LSL(s->page_bits)); 1549 } 1550 } else if (a_mask) { 1551 ldst = new_ldst_label(s); 1552 ldst->is_ld = is_ld; 1553 ldst->oi = oi; 1554 ldst->addr_reg = addr; 1555 1556 /* We are expecting alignment to max out at 7 */ 1557 tcg_debug_assert(a_mask <= 0xff); 1558 /* tst addr, #mask */ 1559 tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addr, a_mask); 1560 } 1561 1562 return ldst; 1563} 1564 1565static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo, 1566 TCGReg datahi, HostAddress h) 1567{ 1568 TCGReg base; 1569 1570 /* Byte swapping is left to middle-end expansion. */ 1571 tcg_debug_assert((opc & MO_BSWAP) == 0); 1572 1573 switch (opc & MO_SSIZE) { 1574 case MO_UB: 1575 if (h.index < 0) { 1576 tcg_out_ld8_12(s, h.cond, datalo, h.base, 0); 1577 } else { 1578 tcg_out_ld8_r(s, h.cond, datalo, h.base, h.index); 1579 } 1580 break; 1581 case MO_SB: 1582 if (h.index < 0) { 1583 tcg_out_ld8s_8(s, h.cond, datalo, h.base, 0); 1584 } else { 1585 tcg_out_ld8s_r(s, h.cond, datalo, h.base, h.index); 1586 } 1587 break; 1588 case MO_UW: 1589 if (h.index < 0) { 1590 tcg_out_ld16u_8(s, h.cond, datalo, h.base, 0); 1591 } else { 1592 tcg_out_ld16u_r(s, h.cond, datalo, h.base, h.index); 1593 } 1594 break; 1595 case MO_SW: 1596 if (h.index < 0) { 1597 tcg_out_ld16s_8(s, h.cond, datalo, h.base, 0); 1598 } else { 1599 tcg_out_ld16s_r(s, h.cond, datalo, h.base, h.index); 1600 } 1601 break; 1602 case MO_UL: 1603 if (h.index < 0) { 1604 tcg_out_ld32_12(s, h.cond, datalo, h.base, 0); 1605 } else { 1606 tcg_out_ld32_r(s, h.cond, datalo, h.base, h.index); 1607 } 1608 break; 1609 case MO_UQ: 1610 /* We used pair allocation for datalo, so already should be aligned. */ 1611 tcg_debug_assert((datalo & 1) == 0); 1612 tcg_debug_assert(datahi == datalo + 1); 1613 /* LDRD requires alignment; double-check that. */ 1614 if (memop_alignment_bits(opc) >= MO_64) { 1615 if (h.index < 0) { 1616 tcg_out_ldrd_8(s, h.cond, datalo, h.base, 0); 1617 break; 1618 } 1619 /* 1620 * Rm (the second address op) must not overlap Rt or Rt + 1. 1621 * Since datalo is aligned, we can simplify the test via alignment. 1622 * Flip the two address arguments if that works. 1623 */ 1624 if ((h.index & ~1) != datalo) { 1625 tcg_out_ldrd_r(s, h.cond, datalo, h.base, h.index); 1626 break; 1627 } 1628 if ((h.base & ~1) != datalo) { 1629 tcg_out_ldrd_r(s, h.cond, datalo, h.index, h.base); 1630 break; 1631 } 1632 } 1633 if (h.index < 0) { 1634 base = h.base; 1635 if (datalo == h.base) { 1636 tcg_out_mov_reg(s, h.cond, TCG_REG_TMP, base); 1637 base = TCG_REG_TMP; 1638 } 1639 } else if (h.index_scratch) { 1640 tcg_out_ld32_rwb(s, h.cond, datalo, h.index, h.base); 1641 tcg_out_ld32_12(s, h.cond, datahi, h.index, 4); 1642 break; 1643 } else { 1644 tcg_out_dat_reg(s, h.cond, ARITH_ADD, TCG_REG_TMP, 1645 h.base, h.index, SHIFT_IMM_LSL(0)); 1646 base = TCG_REG_TMP; 1647 } 1648 tcg_out_ld32_12(s, h.cond, datalo, base, 0); 1649 tcg_out_ld32_12(s, h.cond, datahi, base, 4); 1650 break; 1651 default: 1652 g_assert_not_reached(); 1653 } 1654} 1655 1656static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, 1657 TCGReg addr, MemOpIdx oi, TCGType data_type) 1658{ 1659 MemOp opc = get_memop(oi); 1660 TCGLabelQemuLdst *ldst; 1661 HostAddress h; 1662 1663 ldst = prepare_host_addr(s, &h, addr, oi, true); 1664 if (ldst) { 1665 ldst->type = data_type; 1666 ldst->datalo_reg = datalo; 1667 ldst->datahi_reg = datahi; 1668 1669 /* 1670 * This a conditional BL only to load a pointer within this 1671 * opcode into LR for the slow path. We will not be using 1672 * the value for a tail call. 1673 */ 1674 ldst->label_ptr[0] = s->code_ptr; 1675 tcg_out_bl_imm(s, COND_NE, 0); 1676 1677 tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); 1678 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1679 } else { 1680 tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); 1681 } 1682} 1683 1684static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo, 1685 TCGReg datahi, HostAddress h) 1686{ 1687 /* Byte swapping is left to middle-end expansion. */ 1688 tcg_debug_assert((opc & MO_BSWAP) == 0); 1689 1690 switch (opc & MO_SIZE) { 1691 case MO_8: 1692 if (h.index < 0) { 1693 tcg_out_st8_12(s, h.cond, datalo, h.base, 0); 1694 } else { 1695 tcg_out_st8_r(s, h.cond, datalo, h.base, h.index); 1696 } 1697 break; 1698 case MO_16: 1699 if (h.index < 0) { 1700 tcg_out_st16_8(s, h.cond, datalo, h.base, 0); 1701 } else { 1702 tcg_out_st16_r(s, h.cond, datalo, h.base, h.index); 1703 } 1704 break; 1705 case MO_32: 1706 if (h.index < 0) { 1707 tcg_out_st32_12(s, h.cond, datalo, h.base, 0); 1708 } else { 1709 tcg_out_st32_r(s, h.cond, datalo, h.base, h.index); 1710 } 1711 break; 1712 case MO_64: 1713 /* We used pair allocation for datalo, so already should be aligned. */ 1714 tcg_debug_assert((datalo & 1) == 0); 1715 tcg_debug_assert(datahi == datalo + 1); 1716 /* STRD requires alignment; double-check that. */ 1717 if (memop_alignment_bits(opc) >= MO_64) { 1718 if (h.index < 0) { 1719 tcg_out_strd_8(s, h.cond, datalo, h.base, 0); 1720 } else { 1721 tcg_out_strd_r(s, h.cond, datalo, h.base, h.index); 1722 } 1723 } else if (h.index < 0) { 1724 tcg_out_st32_12(s, h.cond, datalo, h.base, 0); 1725 tcg_out_st32_12(s, h.cond, datahi, h.base, 4); 1726 } else if (h.index_scratch) { 1727 tcg_out_st32_rwb(s, h.cond, datalo, h.index, h.base); 1728 tcg_out_st32_12(s, h.cond, datahi, h.index, 4); 1729 } else { 1730 tcg_out_dat_reg(s, h.cond, ARITH_ADD, TCG_REG_TMP, 1731 h.base, h.index, SHIFT_IMM_LSL(0)); 1732 tcg_out_st32_12(s, h.cond, datalo, TCG_REG_TMP, 0); 1733 tcg_out_st32_12(s, h.cond, datahi, TCG_REG_TMP, 4); 1734 } 1735 break; 1736 default: 1737 g_assert_not_reached(); 1738 } 1739} 1740 1741static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, 1742 TCGReg addr, MemOpIdx oi, TCGType data_type) 1743{ 1744 MemOp opc = get_memop(oi); 1745 TCGLabelQemuLdst *ldst; 1746 HostAddress h; 1747 1748 ldst = prepare_host_addr(s, &h, addr, oi, false); 1749 if (ldst) { 1750 ldst->type = data_type; 1751 ldst->datalo_reg = datalo; 1752 ldst->datahi_reg = datahi; 1753 1754 h.cond = COND_EQ; 1755 tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); 1756 1757 /* The conditional call is last, as we're going to return here. */ 1758 ldst->label_ptr[0] = s->code_ptr; 1759 tcg_out_bl_imm(s, COND_NE, 0); 1760 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1761 } else { 1762 tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); 1763 } 1764} 1765 1766static void tcg_out_epilogue(TCGContext *s); 1767 1768static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg) 1769{ 1770 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, arg); 1771 tcg_out_epilogue(s); 1772} 1773 1774static void tcg_out_goto_tb(TCGContext *s, int which) 1775{ 1776 uintptr_t i_addr; 1777 intptr_t i_disp; 1778 1779 /* Direct branch will be patched by tb_target_set_jmp_target. */ 1780 set_jmp_insn_offset(s, which); 1781 tcg_out32(s, INSN_NOP); 1782 1783 /* When branch is out of range, fall through to indirect. */ 1784 i_addr = get_jmp_target_addr(s, which); 1785 i_disp = tcg_pcrel_diff(s, (void *)i_addr) - 8; 1786 tcg_debug_assert(i_disp < 0); 1787 if (i_disp >= -0xfff) { 1788 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, i_disp); 1789 } else { 1790 /* 1791 * The TB is close, but outside the 12 bits addressable by 1792 * the load. We can extend this to 20 bits with a sub of a 1793 * shifted immediate from pc. 1794 */ 1795 int h = -i_disp; 1796 int l = -(h & 0xfff); 1797 1798 h = encode_imm_nofail(h + l); 1799 tcg_out_dat_imm(s, COND_AL, ARITH_SUB, TCG_REG_R0, TCG_REG_PC, h); 1800 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_R0, l); 1801 } 1802 set_jmp_reset_offset(s, which); 1803} 1804 1805void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1806 uintptr_t jmp_rx, uintptr_t jmp_rw) 1807{ 1808 uintptr_t addr = tb->jmp_target_addr[n]; 1809 ptrdiff_t offset = addr - (jmp_rx + 8); 1810 tcg_insn_unit insn; 1811 1812 /* Either directly branch, or fall through to indirect branch. */ 1813 if (offset == sextract64(offset, 0, 26)) { 1814 /* B <addr> */ 1815 insn = deposit32((COND_AL << 28) | INSN_B, 0, 24, offset >> 2); 1816 } else { 1817 insn = INSN_NOP; 1818 } 1819 1820 qatomic_set((uint32_t *)jmp_rw, insn); 1821 flush_idcache_range(jmp_rx, jmp_rw, 4); 1822} 1823 1824static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, 1825 const TCGArg args[TCG_MAX_OP_ARGS], 1826 const int const_args[TCG_MAX_OP_ARGS]) 1827{ 1828 TCGArg a0, a1, a2, a3, a4, a5; 1829 int c; 1830 1831 switch (opc) { 1832 case INDEX_op_goto_ptr: 1833 tcg_out_b_reg(s, COND_AL, args[0]); 1834 break; 1835 case INDEX_op_br: 1836 tcg_out_goto_label(s, COND_AL, arg_label(args[0])); 1837 break; 1838 1839 case INDEX_op_ld8u_i32: 1840 tcg_out_ld8u(s, COND_AL, args[0], args[1], args[2]); 1841 break; 1842 case INDEX_op_ld8s_i32: 1843 tcg_out_ld8s(s, COND_AL, args[0], args[1], args[2]); 1844 break; 1845 case INDEX_op_ld16u_i32: 1846 tcg_out_ld16u(s, COND_AL, args[0], args[1], args[2]); 1847 break; 1848 case INDEX_op_ld16s_i32: 1849 tcg_out_ld16s(s, COND_AL, args[0], args[1], args[2]); 1850 break; 1851 case INDEX_op_ld_i32: 1852 tcg_out_ld32u(s, COND_AL, args[0], args[1], args[2]); 1853 break; 1854 case INDEX_op_st8_i32: 1855 tcg_out_st8(s, COND_AL, args[0], args[1], args[2]); 1856 break; 1857 case INDEX_op_st16_i32: 1858 tcg_out_st16(s, COND_AL, args[0], args[1], args[2]); 1859 break; 1860 case INDEX_op_st_i32: 1861 tcg_out_st32(s, COND_AL, args[0], args[1], args[2]); 1862 break; 1863 1864 case INDEX_op_movcond_i32: 1865 /* Constraints mean that v2 is always in the same register as dest, 1866 * so we only need to do "if condition passed, move v1 to dest". 1867 */ 1868 c = tcg_out_cmp(s, args[5], args[1], args[2], const_args[2]); 1869 tcg_out_dat_rIK(s, tcg_cond_to_arm_cond[c], ARITH_MOV, 1870 ARITH_MVN, args[0], 0, args[3], const_args[3]); 1871 break; 1872 case INDEX_op_add_i32: 1873 tcg_out_dat_rIN(s, COND_AL, ARITH_ADD, ARITH_SUB, 1874 args[0], args[1], args[2], const_args[2]); 1875 break; 1876 case INDEX_op_sub_i32: 1877 if (const_args[1]) { 1878 if (const_args[2]) { 1879 tcg_out_movi32(s, COND_AL, args[0], args[1] - args[2]); 1880 } else { 1881 tcg_out_dat_rI(s, COND_AL, ARITH_RSB, 1882 args[0], args[2], args[1], 1); 1883 } 1884 } else { 1885 tcg_out_dat_rIN(s, COND_AL, ARITH_SUB, ARITH_ADD, 1886 args[0], args[1], args[2], const_args[2]); 1887 } 1888 break; 1889 case INDEX_op_and_i32: 1890 tcg_out_dat_rIK(s, COND_AL, ARITH_AND, ARITH_BIC, 1891 args[0], args[1], args[2], const_args[2]); 1892 break; 1893 case INDEX_op_andc_i32: 1894 tcg_out_dat_rIK(s, COND_AL, ARITH_BIC, ARITH_AND, 1895 args[0], args[1], args[2], const_args[2]); 1896 break; 1897 case INDEX_op_or_i32: 1898 c = ARITH_ORR; 1899 goto gen_arith; 1900 case INDEX_op_xor_i32: 1901 c = ARITH_EOR; 1902 /* Fall through. */ 1903 gen_arith: 1904 tcg_out_dat_rI(s, COND_AL, c, args[0], args[1], args[2], const_args[2]); 1905 break; 1906 case INDEX_op_add2_i32: 1907 a0 = args[0], a1 = args[1], a2 = args[2]; 1908 a3 = args[3], a4 = args[4], a5 = args[5]; 1909 if (a0 == a3 || (a0 == a5 && !const_args[5])) { 1910 a0 = TCG_REG_TMP; 1911 } 1912 tcg_out_dat_rIN(s, COND_AL, ARITH_ADD | TO_CPSR, ARITH_SUB | TO_CPSR, 1913 a0, a2, a4, const_args[4]); 1914 tcg_out_dat_rIK(s, COND_AL, ARITH_ADC, ARITH_SBC, 1915 a1, a3, a5, const_args[5]); 1916 tcg_out_mov_reg(s, COND_AL, args[0], a0); 1917 break; 1918 case INDEX_op_sub2_i32: 1919 a0 = args[0], a1 = args[1], a2 = args[2]; 1920 a3 = args[3], a4 = args[4], a5 = args[5]; 1921 if ((a0 == a3 && !const_args[3]) || (a0 == a5 && !const_args[5])) { 1922 a0 = TCG_REG_TMP; 1923 } 1924 if (const_args[2]) { 1925 if (const_args[4]) { 1926 tcg_out_movi32(s, COND_AL, a0, a4); 1927 a4 = a0; 1928 } 1929 tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR, a0, a4, a2, 1); 1930 } else { 1931 tcg_out_dat_rIN(s, COND_AL, ARITH_SUB | TO_CPSR, 1932 ARITH_ADD | TO_CPSR, a0, a2, a4, const_args[4]); 1933 } 1934 if (const_args[3]) { 1935 if (const_args[5]) { 1936 tcg_out_movi32(s, COND_AL, a1, a5); 1937 a5 = a1; 1938 } 1939 tcg_out_dat_rI(s, COND_AL, ARITH_RSC, a1, a5, a3, 1); 1940 } else { 1941 tcg_out_dat_rIK(s, COND_AL, ARITH_SBC, ARITH_ADC, 1942 a1, a3, a5, const_args[5]); 1943 } 1944 tcg_out_mov_reg(s, COND_AL, args[0], a0); 1945 break; 1946 case INDEX_op_neg_i32: 1947 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, args[0], args[1], 0); 1948 break; 1949 case INDEX_op_not_i32: 1950 tcg_out_dat_reg(s, COND_AL, 1951 ARITH_MVN, args[0], 0, args[1], SHIFT_IMM_LSL(0)); 1952 break; 1953 case INDEX_op_mul_i32: 1954 tcg_out_mul32(s, COND_AL, args[0], args[1], args[2]); 1955 break; 1956 case INDEX_op_mulu2_i32: 1957 tcg_out_umull32(s, COND_AL, args[0], args[1], args[2], args[3]); 1958 break; 1959 case INDEX_op_muls2_i32: 1960 tcg_out_smull32(s, COND_AL, args[0], args[1], args[2], args[3]); 1961 break; 1962 /* XXX: Perhaps args[2] & 0x1f is wrong */ 1963 case INDEX_op_shl_i32: 1964 c = const_args[2] ? 1965 SHIFT_IMM_LSL(args[2] & 0x1f) : SHIFT_REG_LSL(args[2]); 1966 goto gen_shift32; 1967 case INDEX_op_shr_i32: 1968 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_LSR(args[2] & 0x1f) : 1969 SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args[2]); 1970 goto gen_shift32; 1971 case INDEX_op_sar_i32: 1972 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ASR(args[2] & 0x1f) : 1973 SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args[2]); 1974 goto gen_shift32; 1975 case INDEX_op_rotr_i32: 1976 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ROR(args[2] & 0x1f) : 1977 SHIFT_IMM_LSL(0) : SHIFT_REG_ROR(args[2]); 1978 /* Fall through. */ 1979 gen_shift32: 1980 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], c); 1981 break; 1982 1983 case INDEX_op_rotl_i32: 1984 if (const_args[2]) { 1985 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], 1986 ((0x20 - args[2]) & 0x1f) ? 1987 SHIFT_IMM_ROR((0x20 - args[2]) & 0x1f) : 1988 SHIFT_IMM_LSL(0)); 1989 } else { 1990 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, TCG_REG_TMP, args[2], 0x20); 1991 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], 1992 SHIFT_REG_ROR(TCG_REG_TMP)); 1993 } 1994 break; 1995 1996 case INDEX_op_ctz_i32: 1997 tcg_out_dat_reg(s, COND_AL, INSN_RBIT, TCG_REG_TMP, 0, args[1], 0); 1998 a1 = TCG_REG_TMP; 1999 goto do_clz; 2000 2001 case INDEX_op_clz_i32: 2002 a1 = args[1]; 2003 do_clz: 2004 a0 = args[0]; 2005 a2 = args[2]; 2006 c = const_args[2]; 2007 if (c && a2 == 32) { 2008 tcg_out_dat_reg(s, COND_AL, INSN_CLZ, a0, 0, a1, 0); 2009 break; 2010 } 2011 tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0, a1, 0); 2012 tcg_out_dat_reg(s, COND_NE, INSN_CLZ, a0, 0, a1, 0); 2013 if (c || a0 != a2) { 2014 tcg_out_dat_rIK(s, COND_EQ, ARITH_MOV, ARITH_MVN, a0, 0, a2, c); 2015 } 2016 break; 2017 2018 case INDEX_op_brcond_i32: 2019 c = tcg_out_cmp(s, args[2], args[0], args[1], const_args[1]); 2020 tcg_out_goto_label(s, tcg_cond_to_arm_cond[c], arg_label(args[3])); 2021 break; 2022 case INDEX_op_setcond_i32: 2023 c = tcg_out_cmp(s, args[3], args[1], args[2], const_args[2]); 2024 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[c], 2025 ARITH_MOV, args[0], 0, 1); 2026 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(c)], 2027 ARITH_MOV, args[0], 0, 0); 2028 break; 2029 case INDEX_op_negsetcond_i32: 2030 c = tcg_out_cmp(s, args[3], args[1], args[2], const_args[2]); 2031 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[c], 2032 ARITH_MVN, args[0], 0, 0); 2033 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(c)], 2034 ARITH_MOV, args[0], 0, 0); 2035 break; 2036 2037 case INDEX_op_brcond2_i32: 2038 c = tcg_out_cmp2(s, args, const_args); 2039 tcg_out_goto_label(s, tcg_cond_to_arm_cond[c], arg_label(args[5])); 2040 break; 2041 case INDEX_op_setcond2_i32: 2042 c = tcg_out_cmp2(s, args + 1, const_args + 1); 2043 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[c], ARITH_MOV, args[0], 0, 1); 2044 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(c)], 2045 ARITH_MOV, args[0], 0, 0); 2046 break; 2047 2048 case INDEX_op_qemu_ld_i32: 2049 tcg_out_qemu_ld(s, args[0], -1, args[1], args[2], TCG_TYPE_I32); 2050 break; 2051 case INDEX_op_qemu_ld_i64: 2052 tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3], TCG_TYPE_I64); 2053 break; 2054 2055 case INDEX_op_qemu_st_i32: 2056 tcg_out_qemu_st(s, args[0], -1, args[1], args[2], TCG_TYPE_I32); 2057 break; 2058 case INDEX_op_qemu_st_i64: 2059 tcg_out_qemu_st(s, args[0], args[1], args[2], args[3], TCG_TYPE_I64); 2060 break; 2061 2062 case INDEX_op_bswap16_i32: 2063 tcg_out_bswap16(s, COND_AL, args[0], args[1], args[2]); 2064 break; 2065 case INDEX_op_bswap32_i32: 2066 tcg_out_bswap32(s, COND_AL, args[0], args[1]); 2067 break; 2068 2069 case INDEX_op_deposit_i32: 2070 tcg_out_deposit(s, COND_AL, args[0], args[2], 2071 args[3], args[4], const_args[2]); 2072 break; 2073 case INDEX_op_extract_i32: 2074 tcg_out_extract(s, COND_AL, args[0], args[1], args[2], args[3]); 2075 break; 2076 case INDEX_op_sextract_i32: 2077 tcg_out_sextract(s, COND_AL, args[0], args[1], args[2], args[3]); 2078 break; 2079 case INDEX_op_extract2_i32: 2080 /* ??? These optimization vs zero should be generic. */ 2081 /* ??? But we can't substitute 2 for 1 in the opcode stream yet. */ 2082 if (const_args[1]) { 2083 if (const_args[2]) { 2084 tcg_out_movi(s, TCG_TYPE_REG, args[0], 0); 2085 } else { 2086 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, 2087 args[2], SHIFT_IMM_LSL(32 - args[3])); 2088 } 2089 } else if (const_args[2]) { 2090 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, 2091 args[1], SHIFT_IMM_LSR(args[3])); 2092 } else { 2093 /* We can do extract2 in 2 insns, vs the 3 required otherwise. */ 2094 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, 2095 args[2], SHIFT_IMM_LSL(32 - args[3])); 2096 tcg_out_dat_reg(s, COND_AL, ARITH_ORR, args[0], TCG_REG_TMP, 2097 args[1], SHIFT_IMM_LSR(args[3])); 2098 } 2099 break; 2100 2101 case INDEX_op_div_i32: 2102 tcg_out_sdiv(s, COND_AL, args[0], args[1], args[2]); 2103 break; 2104 case INDEX_op_divu_i32: 2105 tcg_out_udiv(s, COND_AL, args[0], args[1], args[2]); 2106 break; 2107 2108 case INDEX_op_mb: 2109 tcg_out_mb(s, args[0]); 2110 break; 2111 2112 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ 2113 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2114 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2115 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2116 case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ 2117 case INDEX_op_ext8u_i32: 2118 case INDEX_op_ext16s_i32: 2119 case INDEX_op_ext16u_i32: 2120 default: 2121 g_assert_not_reached(); 2122 } 2123} 2124 2125static TCGConstraintSetIndex 2126tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) 2127{ 2128 switch (op) { 2129 case INDEX_op_goto_ptr: 2130 return C_O0_I1(r); 2131 2132 case INDEX_op_ld8u_i32: 2133 case INDEX_op_ld8s_i32: 2134 case INDEX_op_ld16u_i32: 2135 case INDEX_op_ld16s_i32: 2136 case INDEX_op_ld_i32: 2137 case INDEX_op_neg_i32: 2138 case INDEX_op_not_i32: 2139 case INDEX_op_bswap16_i32: 2140 case INDEX_op_bswap32_i32: 2141 case INDEX_op_ext8s_i32: 2142 case INDEX_op_ext16s_i32: 2143 case INDEX_op_ext16u_i32: 2144 case INDEX_op_extract_i32: 2145 case INDEX_op_sextract_i32: 2146 return C_O1_I1(r, r); 2147 2148 case INDEX_op_st8_i32: 2149 case INDEX_op_st16_i32: 2150 case INDEX_op_st_i32: 2151 return C_O0_I2(r, r); 2152 2153 case INDEX_op_add_i32: 2154 case INDEX_op_sub_i32: 2155 case INDEX_op_setcond_i32: 2156 case INDEX_op_negsetcond_i32: 2157 return C_O1_I2(r, r, rIN); 2158 2159 case INDEX_op_and_i32: 2160 case INDEX_op_andc_i32: 2161 case INDEX_op_clz_i32: 2162 case INDEX_op_ctz_i32: 2163 return C_O1_I2(r, r, rIK); 2164 2165 case INDEX_op_mul_i32: 2166 case INDEX_op_div_i32: 2167 case INDEX_op_divu_i32: 2168 return C_O1_I2(r, r, r); 2169 2170 case INDEX_op_mulu2_i32: 2171 case INDEX_op_muls2_i32: 2172 return C_O2_I2(r, r, r, r); 2173 2174 case INDEX_op_or_i32: 2175 case INDEX_op_xor_i32: 2176 return C_O1_I2(r, r, rI); 2177 2178 case INDEX_op_shl_i32: 2179 case INDEX_op_shr_i32: 2180 case INDEX_op_sar_i32: 2181 case INDEX_op_rotl_i32: 2182 case INDEX_op_rotr_i32: 2183 return C_O1_I2(r, r, ri); 2184 2185 case INDEX_op_brcond_i32: 2186 return C_O0_I2(r, rIN); 2187 case INDEX_op_deposit_i32: 2188 return C_O1_I2(r, 0, rZ); 2189 case INDEX_op_extract2_i32: 2190 return C_O1_I2(r, rZ, rZ); 2191 case INDEX_op_movcond_i32: 2192 return C_O1_I4(r, r, rIN, rIK, 0); 2193 case INDEX_op_add2_i32: 2194 return C_O2_I4(r, r, r, r, rIN, rIK); 2195 case INDEX_op_sub2_i32: 2196 return C_O2_I4(r, r, rI, rI, rIN, rIK); 2197 case INDEX_op_brcond2_i32: 2198 return C_O0_I4(r, r, rI, rI); 2199 case INDEX_op_setcond2_i32: 2200 return C_O1_I4(r, r, r, rI, rI); 2201 2202 case INDEX_op_qemu_ld_i32: 2203 return C_O1_I1(r, q); 2204 case INDEX_op_qemu_ld_i64: 2205 return C_O2_I1(e, p, q); 2206 case INDEX_op_qemu_st_i32: 2207 return C_O0_I2(q, q); 2208 case INDEX_op_qemu_st_i64: 2209 return C_O0_I3(Q, p, q); 2210 2211 case INDEX_op_st_vec: 2212 return C_O0_I2(w, r); 2213 case INDEX_op_ld_vec: 2214 case INDEX_op_dupm_vec: 2215 return C_O1_I1(w, r); 2216 case INDEX_op_dup_vec: 2217 return C_O1_I1(w, wr); 2218 case INDEX_op_abs_vec: 2219 case INDEX_op_neg_vec: 2220 case INDEX_op_not_vec: 2221 case INDEX_op_shli_vec: 2222 case INDEX_op_shri_vec: 2223 case INDEX_op_sari_vec: 2224 return C_O1_I1(w, w); 2225 case INDEX_op_dup2_vec: 2226 case INDEX_op_add_vec: 2227 case INDEX_op_mul_vec: 2228 case INDEX_op_smax_vec: 2229 case INDEX_op_smin_vec: 2230 case INDEX_op_ssadd_vec: 2231 case INDEX_op_sssub_vec: 2232 case INDEX_op_sub_vec: 2233 case INDEX_op_umax_vec: 2234 case INDEX_op_umin_vec: 2235 case INDEX_op_usadd_vec: 2236 case INDEX_op_ussub_vec: 2237 case INDEX_op_xor_vec: 2238 case INDEX_op_arm_sshl_vec: 2239 case INDEX_op_arm_ushl_vec: 2240 return C_O1_I2(w, w, w); 2241 case INDEX_op_arm_sli_vec: 2242 return C_O1_I2(w, 0, w); 2243 case INDEX_op_or_vec: 2244 case INDEX_op_andc_vec: 2245 return C_O1_I2(w, w, wO); 2246 case INDEX_op_and_vec: 2247 case INDEX_op_orc_vec: 2248 return C_O1_I2(w, w, wV); 2249 case INDEX_op_cmp_vec: 2250 return C_O1_I2(w, w, wZ); 2251 case INDEX_op_bitsel_vec: 2252 return C_O1_I3(w, w, w, w); 2253 default: 2254 return C_NotImplemented; 2255 } 2256} 2257 2258static void tcg_target_init(TCGContext *s) 2259{ 2260 /* 2261 * Only probe for the platform and capabilities if we haven't already 2262 * determined maximum values at compile time. 2263 */ 2264#if !defined(use_idiv_instructions) || !defined(use_neon_instructions) 2265 { 2266 unsigned long hwcap = qemu_getauxval(AT_HWCAP); 2267#ifndef use_idiv_instructions 2268 use_idiv_instructions = (hwcap & HWCAP_ARM_IDIVA) != 0; 2269#endif 2270#ifndef use_neon_instructions 2271 use_neon_instructions = (hwcap & HWCAP_ARM_NEON) != 0; 2272#endif 2273 } 2274#endif 2275 2276 if (__ARM_ARCH < 7) { 2277 const char *pl = (const char *)qemu_getauxval(AT_PLATFORM); 2278 if (pl != NULL && pl[0] == 'v' && pl[1] >= '4' && pl[1] <= '9') { 2279 arm_arch = pl[1] - '0'; 2280 } 2281 2282 if (arm_arch < 6) { 2283 error_report("TCG: ARMv%d is unsupported; exiting", arm_arch); 2284 exit(EXIT_FAILURE); 2285 } 2286 } 2287 2288 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS; 2289 2290 tcg_target_call_clobber_regs = 0; 2291 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); 2292 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1); 2293 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2); 2294 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3); 2295 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12); 2296 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14); 2297 2298 if (use_neon_instructions) { 2299 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS; 2300 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS; 2301 2302 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q0); 2303 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q1); 2304 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q2); 2305 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q3); 2306 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q8); 2307 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q9); 2308 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q10); 2309 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q11); 2310 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q12); 2311 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q13); 2312 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q14); 2313 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q15); 2314 } 2315 2316 s->reserved_regs = 0; 2317 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); 2318 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP); 2319 tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC); 2320 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP); 2321} 2322 2323static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 2324 TCGReg arg1, intptr_t arg2) 2325{ 2326 switch (type) { 2327 case TCG_TYPE_I32: 2328 tcg_out_ld32u(s, COND_AL, arg, arg1, arg2); 2329 return; 2330 case TCG_TYPE_V64: 2331 /* regs 1; size 8; align 8 */ 2332 tcg_out_vldst(s, INSN_VLD1 | 0x7d0, arg, arg1, arg2); 2333 return; 2334 case TCG_TYPE_V128: 2335 /* 2336 * We have only 8-byte alignment for the stack per the ABI. 2337 * Rather than dynamically re-align the stack, it's easier 2338 * to simply not request alignment beyond that. So: 2339 * regs 2; size 8; align 8 2340 */ 2341 tcg_out_vldst(s, INSN_VLD1 | 0xad0, arg, arg1, arg2); 2342 return; 2343 default: 2344 g_assert_not_reached(); 2345 } 2346} 2347 2348static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 2349 TCGReg arg1, intptr_t arg2) 2350{ 2351 switch (type) { 2352 case TCG_TYPE_I32: 2353 tcg_out_st32(s, COND_AL, arg, arg1, arg2); 2354 return; 2355 case TCG_TYPE_V64: 2356 /* regs 1; size 8; align 8 */ 2357 tcg_out_vldst(s, INSN_VST1 | 0x7d0, arg, arg1, arg2); 2358 return; 2359 case TCG_TYPE_V128: 2360 /* See tcg_out_ld re alignment: regs 2; size 8; align 8 */ 2361 tcg_out_vldst(s, INSN_VST1 | 0xad0, arg, arg1, arg2); 2362 return; 2363 default: 2364 g_assert_not_reached(); 2365 } 2366} 2367 2368static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 2369 TCGReg base, intptr_t ofs) 2370{ 2371 return false; 2372} 2373 2374static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 2375{ 2376 if (ret == arg) { 2377 return true; 2378 } 2379 switch (type) { 2380 case TCG_TYPE_I32: 2381 if (ret < TCG_REG_Q0 && arg < TCG_REG_Q0) { 2382 tcg_out_mov_reg(s, COND_AL, ret, arg); 2383 return true; 2384 } 2385 return false; 2386 2387 case TCG_TYPE_V64: 2388 case TCG_TYPE_V128: 2389 /* "VMOV D,N" is an alias for "VORR D,N,N". */ 2390 tcg_out_vreg3(s, INSN_VORR, type - TCG_TYPE_V64, 0, ret, arg, arg); 2391 return true; 2392 2393 default: 2394 g_assert_not_reached(); 2395 } 2396} 2397 2398static void tcg_out_movi(TCGContext *s, TCGType type, 2399 TCGReg ret, tcg_target_long arg) 2400{ 2401 tcg_debug_assert(type == TCG_TYPE_I32); 2402 tcg_debug_assert(ret < TCG_REG_Q0); 2403 tcg_out_movi32(s, COND_AL, ret, arg); 2404} 2405 2406static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 2407{ 2408 return false; 2409} 2410 2411static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 2412 tcg_target_long imm) 2413{ 2414 int enc, opc = ARITH_ADD; 2415 2416 /* All of the easiest immediates to encode are positive. */ 2417 if (imm < 0) { 2418 imm = -imm; 2419 opc = ARITH_SUB; 2420 } 2421 enc = encode_imm(imm); 2422 if (enc >= 0) { 2423 tcg_out_dat_imm(s, COND_AL, opc, rd, rs, enc); 2424 } else { 2425 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, imm); 2426 tcg_out_dat_reg(s, COND_AL, opc, rd, rs, 2427 TCG_REG_TMP, SHIFT_IMM_LSL(0)); 2428 } 2429} 2430 2431/* Type is always V128, with I64 elements. */ 2432static void tcg_out_dup2_vec(TCGContext *s, TCGReg rd, TCGReg rl, TCGReg rh) 2433{ 2434 /* Move high element into place first. */ 2435 /* VMOV Dd+1, Ds */ 2436 tcg_out_vreg3(s, INSN_VORR | (1 << 12), 0, 0, rd, rh, rh); 2437 /* Move low element into place; tcg_out_mov will check for nop. */ 2438 tcg_out_mov(s, TCG_TYPE_V64, rd, rl); 2439} 2440 2441static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 2442 TCGReg rd, TCGReg rs) 2443{ 2444 int q = type - TCG_TYPE_V64; 2445 2446 if (vece == MO_64) { 2447 if (type == TCG_TYPE_V128) { 2448 tcg_out_dup2_vec(s, rd, rs, rs); 2449 } else { 2450 tcg_out_mov(s, TCG_TYPE_V64, rd, rs); 2451 } 2452 } else if (rs < TCG_REG_Q0) { 2453 int b = (vece == MO_8); 2454 int e = (vece == MO_16); 2455 tcg_out32(s, INSN_VDUP_G | (b << 22) | (q << 21) | (e << 5) | 2456 encode_vn(rd) | (rs << 12)); 2457 } else { 2458 int imm4 = 1 << vece; 2459 tcg_out32(s, INSN_VDUP_S | (imm4 << 16) | (q << 6) | 2460 encode_vd(rd) | encode_vm(rs)); 2461 } 2462 return true; 2463} 2464 2465static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 2466 TCGReg rd, TCGReg base, intptr_t offset) 2467{ 2468 if (vece == MO_64) { 2469 tcg_out_ld(s, TCG_TYPE_V64, rd, base, offset); 2470 if (type == TCG_TYPE_V128) { 2471 tcg_out_dup2_vec(s, rd, rd, rd); 2472 } 2473 } else { 2474 int q = type - TCG_TYPE_V64; 2475 tcg_out_vldst(s, INSN_VLD1R | (vece << 6) | (q << 5), 2476 rd, base, offset); 2477 } 2478 return true; 2479} 2480 2481static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 2482 TCGReg rd, int64_t v64) 2483{ 2484 int q = type - TCG_TYPE_V64; 2485 int cmode, imm8, i; 2486 2487 /* Test all bytes equal first. */ 2488 if (vece == MO_8) { 2489 tcg_out_vmovi(s, rd, q, 0, 0xe, v64); 2490 return; 2491 } 2492 2493 /* 2494 * Test all bytes 0x00 or 0xff second. This can match cases that 2495 * might otherwise take 2 or 3 insns for MO_16 or MO_32 below. 2496 */ 2497 for (i = imm8 = 0; i < 8; i++) { 2498 uint8_t byte = v64 >> (i * 8); 2499 if (byte == 0xff) { 2500 imm8 |= 1 << i; 2501 } else if (byte != 0) { 2502 goto fail_bytes; 2503 } 2504 } 2505 tcg_out_vmovi(s, rd, q, 1, 0xe, imm8); 2506 return; 2507 fail_bytes: 2508 2509 /* 2510 * Tests for various replications. For each element width, if we 2511 * cannot find an expansion there's no point checking a larger 2512 * width because we already know by replication it cannot match. 2513 */ 2514 if (vece == MO_16) { 2515 uint16_t v16 = v64; 2516 2517 if (is_shimm16(v16, &cmode, &imm8)) { 2518 tcg_out_vmovi(s, rd, q, 0, cmode, imm8); 2519 return; 2520 } 2521 if (is_shimm16(~v16, &cmode, &imm8)) { 2522 tcg_out_vmovi(s, rd, q, 1, cmode, imm8); 2523 return; 2524 } 2525 2526 /* 2527 * Otherwise, all remaining constants can be loaded in two insns: 2528 * rd = v16 & 0xff, rd |= v16 & 0xff00. 2529 */ 2530 tcg_out_vmovi(s, rd, q, 0, 0x8, v16 & 0xff); 2531 tcg_out_vmovi(s, rd, q, 0, 0xb, v16 >> 8); /* VORRI */ 2532 return; 2533 } 2534 2535 if (vece == MO_32) { 2536 uint32_t v32 = v64; 2537 2538 if (is_shimm32(v32, &cmode, &imm8) || 2539 is_soimm32(v32, &cmode, &imm8)) { 2540 tcg_out_vmovi(s, rd, q, 0, cmode, imm8); 2541 return; 2542 } 2543 if (is_shimm32(~v32, &cmode, &imm8) || 2544 is_soimm32(~v32, &cmode, &imm8)) { 2545 tcg_out_vmovi(s, rd, q, 1, cmode, imm8); 2546 return; 2547 } 2548 2549 /* 2550 * Restrict the set of constants to those we can load with 2551 * two instructions. Others we load from the pool. 2552 */ 2553 i = is_shimm32_pair(v32, &cmode, &imm8); 2554 if (i) { 2555 tcg_out_vmovi(s, rd, q, 0, cmode, imm8); 2556 tcg_out_vmovi(s, rd, q, 0, i | 1, extract32(v32, i * 4, 8)); 2557 return; 2558 } 2559 i = is_shimm32_pair(~v32, &cmode, &imm8); 2560 if (i) { 2561 tcg_out_vmovi(s, rd, q, 1, cmode, imm8); 2562 tcg_out_vmovi(s, rd, q, 1, i | 1, extract32(~v32, i * 4, 8)); 2563 return; 2564 } 2565 } 2566 2567 /* 2568 * As a last resort, load from the constant pool. 2569 */ 2570 if (!q || vece == MO_64) { 2571 new_pool_l2(s, R_ARM_PC11, s->code_ptr, 0, v64, v64 >> 32); 2572 /* VLDR Dd, [pc + offset] */ 2573 tcg_out32(s, INSN_VLDR_D | encode_vd(rd) | (0xf << 16)); 2574 if (q) { 2575 tcg_out_dup2_vec(s, rd, rd, rd); 2576 } 2577 } else { 2578 new_pool_label(s, (uint32_t)v64, R_ARM_PC8, s->code_ptr, 0); 2579 /* add tmp, pc, offset */ 2580 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_TMP, TCG_REG_PC, 0); 2581 tcg_out_dupm_vec(s, type, MO_32, rd, TCG_REG_TMP, 0); 2582 } 2583} 2584 2585static const ARMInsn vec_cmp_insn[16] = { 2586 [TCG_COND_EQ] = INSN_VCEQ, 2587 [TCG_COND_GT] = INSN_VCGT, 2588 [TCG_COND_GE] = INSN_VCGE, 2589 [TCG_COND_GTU] = INSN_VCGT_U, 2590 [TCG_COND_GEU] = INSN_VCGE_U, 2591}; 2592 2593static const ARMInsn vec_cmp0_insn[16] = { 2594 [TCG_COND_EQ] = INSN_VCEQ0, 2595 [TCG_COND_GT] = INSN_VCGT0, 2596 [TCG_COND_GE] = INSN_VCGE0, 2597 [TCG_COND_LT] = INSN_VCLT0, 2598 [TCG_COND_LE] = INSN_VCLE0, 2599}; 2600 2601static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 2602 unsigned vecl, unsigned vece, 2603 const TCGArg args[TCG_MAX_OP_ARGS], 2604 const int const_args[TCG_MAX_OP_ARGS]) 2605{ 2606 TCGType type = vecl + TCG_TYPE_V64; 2607 unsigned q = vecl; 2608 TCGArg a0, a1, a2, a3; 2609 int cmode, imm8; 2610 2611 a0 = args[0]; 2612 a1 = args[1]; 2613 a2 = args[2]; 2614 2615 switch (opc) { 2616 case INDEX_op_ld_vec: 2617 tcg_out_ld(s, type, a0, a1, a2); 2618 return; 2619 case INDEX_op_st_vec: 2620 tcg_out_st(s, type, a0, a1, a2); 2621 return; 2622 case INDEX_op_dupm_vec: 2623 tcg_out_dupm_vec(s, type, vece, a0, a1, a2); 2624 return; 2625 case INDEX_op_dup2_vec: 2626 tcg_out_dup2_vec(s, a0, a1, a2); 2627 return; 2628 case INDEX_op_abs_vec: 2629 tcg_out_vreg2(s, INSN_VABS, q, vece, a0, a1); 2630 return; 2631 case INDEX_op_neg_vec: 2632 tcg_out_vreg2(s, INSN_VNEG, q, vece, a0, a1); 2633 return; 2634 case INDEX_op_not_vec: 2635 tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a1); 2636 return; 2637 case INDEX_op_add_vec: 2638 tcg_out_vreg3(s, INSN_VADD, q, vece, a0, a1, a2); 2639 return; 2640 case INDEX_op_mul_vec: 2641 tcg_out_vreg3(s, INSN_VMUL, q, vece, a0, a1, a2); 2642 return; 2643 case INDEX_op_smax_vec: 2644 tcg_out_vreg3(s, INSN_VMAX, q, vece, a0, a1, a2); 2645 return; 2646 case INDEX_op_smin_vec: 2647 tcg_out_vreg3(s, INSN_VMIN, q, vece, a0, a1, a2); 2648 return; 2649 case INDEX_op_sub_vec: 2650 tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2); 2651 return; 2652 case INDEX_op_ssadd_vec: 2653 tcg_out_vreg3(s, INSN_VQADD, q, vece, a0, a1, a2); 2654 return; 2655 case INDEX_op_sssub_vec: 2656 tcg_out_vreg3(s, INSN_VQSUB, q, vece, a0, a1, a2); 2657 return; 2658 case INDEX_op_umax_vec: 2659 tcg_out_vreg3(s, INSN_VMAX_U, q, vece, a0, a1, a2); 2660 return; 2661 case INDEX_op_umin_vec: 2662 tcg_out_vreg3(s, INSN_VMIN_U, q, vece, a0, a1, a2); 2663 return; 2664 case INDEX_op_usadd_vec: 2665 tcg_out_vreg3(s, INSN_VQADD_U, q, vece, a0, a1, a2); 2666 return; 2667 case INDEX_op_ussub_vec: 2668 tcg_out_vreg3(s, INSN_VQSUB_U, q, vece, a0, a1, a2); 2669 return; 2670 case INDEX_op_xor_vec: 2671 tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2); 2672 return; 2673 case INDEX_op_arm_sshl_vec: 2674 /* 2675 * Note that Vm is the data and Vn is the shift count, 2676 * therefore the arguments appear reversed. 2677 */ 2678 tcg_out_vreg3(s, INSN_VSHL_S, q, vece, a0, a2, a1); 2679 return; 2680 case INDEX_op_arm_ushl_vec: 2681 /* See above. */ 2682 tcg_out_vreg3(s, INSN_VSHL_U, q, vece, a0, a2, a1); 2683 return; 2684 case INDEX_op_shli_vec: 2685 tcg_out_vshifti(s, INSN_VSHLI, q, a0, a1, a2 + (8 << vece)); 2686 return; 2687 case INDEX_op_shri_vec: 2688 tcg_out_vshifti(s, INSN_VSHRI, q, a0, a1, (16 << vece) - a2); 2689 return; 2690 case INDEX_op_sari_vec: 2691 tcg_out_vshifti(s, INSN_VSARI, q, a0, a1, (16 << vece) - a2); 2692 return; 2693 case INDEX_op_arm_sli_vec: 2694 tcg_out_vshifti(s, INSN_VSLI, q, a0, a2, args[3] + (8 << vece)); 2695 return; 2696 2697 case INDEX_op_andc_vec: 2698 if (!const_args[2]) { 2699 tcg_out_vreg3(s, INSN_VBIC, q, 0, a0, a1, a2); 2700 return; 2701 } 2702 a2 = ~a2; 2703 /* fall through */ 2704 case INDEX_op_and_vec: 2705 if (const_args[2]) { 2706 is_shimm1632(~a2, &cmode, &imm8); 2707 if (a0 == a1) { 2708 tcg_out_vmovi(s, a0, q, 1, cmode | 1, imm8); /* VBICI */ 2709 return; 2710 } 2711 tcg_out_vmovi(s, a0, q, 1, cmode, imm8); /* VMVNI */ 2712 a2 = a0; 2713 } 2714 tcg_out_vreg3(s, INSN_VAND, q, 0, a0, a1, a2); 2715 return; 2716 2717 case INDEX_op_orc_vec: 2718 if (!const_args[2]) { 2719 tcg_out_vreg3(s, INSN_VORN, q, 0, a0, a1, a2); 2720 return; 2721 } 2722 a2 = ~a2; 2723 /* fall through */ 2724 case INDEX_op_or_vec: 2725 if (const_args[2]) { 2726 is_shimm1632(a2, &cmode, &imm8); 2727 if (a0 == a1) { 2728 tcg_out_vmovi(s, a0, q, 0, cmode | 1, imm8); /* VORRI */ 2729 return; 2730 } 2731 tcg_out_vmovi(s, a0, q, 0, cmode, imm8); /* VMOVI */ 2732 a2 = a0; 2733 } 2734 tcg_out_vreg3(s, INSN_VORR, q, 0, a0, a1, a2); 2735 return; 2736 2737 case INDEX_op_cmp_vec: 2738 { 2739 TCGCond cond = args[3]; 2740 ARMInsn insn; 2741 2742 switch (cond) { 2743 case TCG_COND_NE: 2744 if (const_args[2]) { 2745 tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a1); 2746 } else { 2747 tcg_out_vreg3(s, INSN_VCEQ, q, vece, a0, a1, a2); 2748 tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0); 2749 } 2750 break; 2751 2752 case TCG_COND_TSTNE: 2753 case TCG_COND_TSTEQ: 2754 if (const_args[2]) { 2755 /* (x & 0) == 0 */ 2756 tcg_out_dupi_vec(s, type, MO_8, a0, 2757 -(cond == TCG_COND_TSTEQ)); 2758 break; 2759 } 2760 tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a2); 2761 if (cond == TCG_COND_TSTEQ) { 2762 tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0); 2763 } 2764 break; 2765 2766 default: 2767 if (const_args[2]) { 2768 insn = vec_cmp0_insn[cond]; 2769 if (insn) { 2770 tcg_out_vreg2(s, insn, q, vece, a0, a1); 2771 return; 2772 } 2773 tcg_out_dupi_vec(s, type, MO_8, TCG_VEC_TMP, 0); 2774 a2 = TCG_VEC_TMP; 2775 } 2776 insn = vec_cmp_insn[cond]; 2777 if (insn == 0) { 2778 TCGArg t; 2779 t = a1, a1 = a2, a2 = t; 2780 cond = tcg_swap_cond(cond); 2781 insn = vec_cmp_insn[cond]; 2782 tcg_debug_assert(insn != 0); 2783 } 2784 tcg_out_vreg3(s, insn, q, vece, a0, a1, a2); 2785 break; 2786 } 2787 } 2788 return; 2789 2790 case INDEX_op_bitsel_vec: 2791 a3 = args[3]; 2792 if (a0 == a3) { 2793 tcg_out_vreg3(s, INSN_VBIT, q, 0, a0, a2, a1); 2794 } else if (a0 == a2) { 2795 tcg_out_vreg3(s, INSN_VBIF, q, 0, a0, a3, a1); 2796 } else { 2797 tcg_out_mov(s, type, a0, a1); 2798 tcg_out_vreg3(s, INSN_VBSL, q, 0, a0, a2, a3); 2799 } 2800 return; 2801 2802 case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ 2803 case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ 2804 default: 2805 g_assert_not_reached(); 2806 } 2807} 2808 2809int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 2810{ 2811 switch (opc) { 2812 case INDEX_op_add_vec: 2813 case INDEX_op_sub_vec: 2814 case INDEX_op_and_vec: 2815 case INDEX_op_andc_vec: 2816 case INDEX_op_or_vec: 2817 case INDEX_op_orc_vec: 2818 case INDEX_op_xor_vec: 2819 case INDEX_op_not_vec: 2820 case INDEX_op_shli_vec: 2821 case INDEX_op_shri_vec: 2822 case INDEX_op_sari_vec: 2823 case INDEX_op_ssadd_vec: 2824 case INDEX_op_sssub_vec: 2825 case INDEX_op_usadd_vec: 2826 case INDEX_op_ussub_vec: 2827 case INDEX_op_bitsel_vec: 2828 return 1; 2829 case INDEX_op_abs_vec: 2830 case INDEX_op_cmp_vec: 2831 case INDEX_op_mul_vec: 2832 case INDEX_op_neg_vec: 2833 case INDEX_op_smax_vec: 2834 case INDEX_op_smin_vec: 2835 case INDEX_op_umax_vec: 2836 case INDEX_op_umin_vec: 2837 return vece < MO_64; 2838 case INDEX_op_shlv_vec: 2839 case INDEX_op_shrv_vec: 2840 case INDEX_op_sarv_vec: 2841 case INDEX_op_rotli_vec: 2842 case INDEX_op_rotlv_vec: 2843 case INDEX_op_rotrv_vec: 2844 return -1; 2845 default: 2846 return 0; 2847 } 2848} 2849 2850void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 2851 TCGArg a0, ...) 2852{ 2853 va_list va; 2854 TCGv_vec v0, v1, v2, t1, t2, c1; 2855 TCGArg a2; 2856 2857 va_start(va, a0); 2858 v0 = temp_tcgv_vec(arg_temp(a0)); 2859 v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 2860 a2 = va_arg(va, TCGArg); 2861 va_end(va); 2862 2863 switch (opc) { 2864 case INDEX_op_shlv_vec: 2865 /* 2866 * Merely propagate shlv_vec to arm_ushl_vec. 2867 * In this way we don't set TCG_TARGET_HAS_shv_vec 2868 * because everything is done via expansion. 2869 */ 2870 v2 = temp_tcgv_vec(arg_temp(a2)); 2871 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0), 2872 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 2873 break; 2874 2875 case INDEX_op_shrv_vec: 2876 case INDEX_op_sarv_vec: 2877 /* Right shifts are negative left shifts for NEON. */ 2878 v2 = temp_tcgv_vec(arg_temp(a2)); 2879 t1 = tcg_temp_new_vec(type); 2880 tcg_gen_neg_vec(vece, t1, v2); 2881 if (opc == INDEX_op_shrv_vec) { 2882 opc = INDEX_op_arm_ushl_vec; 2883 } else { 2884 opc = INDEX_op_arm_sshl_vec; 2885 } 2886 vec_gen_3(opc, type, vece, tcgv_vec_arg(v0), 2887 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 2888 tcg_temp_free_vec(t1); 2889 break; 2890 2891 case INDEX_op_rotli_vec: 2892 t1 = tcg_temp_new_vec(type); 2893 tcg_gen_shri_vec(vece, t1, v1, -a2 & ((8 << vece) - 1)); 2894 vec_gen_4(INDEX_op_arm_sli_vec, type, vece, 2895 tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(v1), a2); 2896 tcg_temp_free_vec(t1); 2897 break; 2898 2899 case INDEX_op_rotlv_vec: 2900 v2 = temp_tcgv_vec(arg_temp(a2)); 2901 t1 = tcg_temp_new_vec(type); 2902 c1 = tcg_constant_vec(type, vece, 8 << vece); 2903 tcg_gen_sub_vec(vece, t1, v2, c1); 2904 /* Right shifts are negative left shifts for NEON. */ 2905 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1), 2906 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 2907 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0), 2908 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 2909 tcg_gen_or_vec(vece, v0, v0, t1); 2910 tcg_temp_free_vec(t1); 2911 break; 2912 2913 case INDEX_op_rotrv_vec: 2914 v2 = temp_tcgv_vec(arg_temp(a2)); 2915 t1 = tcg_temp_new_vec(type); 2916 t2 = tcg_temp_new_vec(type); 2917 c1 = tcg_constant_vec(type, vece, 8 << vece); 2918 tcg_gen_neg_vec(vece, t1, v2); 2919 tcg_gen_sub_vec(vece, t2, c1, v2); 2920 /* Right shifts are negative left shifts for NEON. */ 2921 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1), 2922 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 2923 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t2), 2924 tcgv_vec_arg(v1), tcgv_vec_arg(t2)); 2925 tcg_gen_or_vec(vece, v0, t1, t2); 2926 tcg_temp_free_vec(t1); 2927 tcg_temp_free_vec(t2); 2928 break; 2929 2930 default: 2931 g_assert_not_reached(); 2932 } 2933} 2934 2935static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 2936{ 2937 int i; 2938 for (i = 0; i < count; ++i) { 2939 p[i] = INSN_NOP; 2940 } 2941} 2942 2943/* Compute frame size via macros, to share between tcg_target_qemu_prologue 2944 and tcg_register_jit. */ 2945 2946#define PUSH_SIZE ((11 - 4 + 1 + 1) * sizeof(tcg_target_long)) 2947 2948#define FRAME_SIZE \ 2949 ((PUSH_SIZE \ 2950 + TCG_STATIC_CALL_ARGS_SIZE \ 2951 + CPU_TEMP_BUF_NLONGS * sizeof(long) \ 2952 + TCG_TARGET_STACK_ALIGN - 1) \ 2953 & -TCG_TARGET_STACK_ALIGN) 2954 2955#define STACK_ADDEND (FRAME_SIZE - PUSH_SIZE) 2956 2957static void tcg_target_qemu_prologue(TCGContext *s) 2958{ 2959 /* Calling convention requires us to save r4-r11 and lr. */ 2960 /* stmdb sp!, { r4 - r11, lr } */ 2961 tcg_out_ldstm(s, COND_AL, INSN_STMDB, TCG_REG_CALL_STACK, 2962 (1 << TCG_REG_R4) | (1 << TCG_REG_R5) | (1 << TCG_REG_R6) | 2963 (1 << TCG_REG_R7) | (1 << TCG_REG_R8) | (1 << TCG_REG_R9) | 2964 (1 << TCG_REG_R10) | (1 << TCG_REG_R11) | (1 << TCG_REG_R14)); 2965 2966 /* Reserve callee argument and tcg temp space. */ 2967 tcg_out_dat_rI(s, COND_AL, ARITH_SUB, TCG_REG_CALL_STACK, 2968 TCG_REG_CALL_STACK, STACK_ADDEND, 1); 2969 tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE, 2970 CPU_TEMP_BUF_NLONGS * sizeof(long)); 2971 2972 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 2973 2974 if (!tcg_use_softmmu && guest_base) { 2975 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_GUEST_BASE, guest_base); 2976 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GUEST_BASE); 2977 } 2978 2979 tcg_out_b_reg(s, COND_AL, tcg_target_call_iarg_regs[1]); 2980 2981 /* 2982 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 2983 * and fall through to the rest of the epilogue. 2984 */ 2985 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 2986 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, 0); 2987 tcg_out_epilogue(s); 2988} 2989 2990static void tcg_out_epilogue(TCGContext *s) 2991{ 2992 /* Release local stack frame. */ 2993 tcg_out_dat_rI(s, COND_AL, ARITH_ADD, TCG_REG_CALL_STACK, 2994 TCG_REG_CALL_STACK, STACK_ADDEND, 1); 2995 2996 /* ldmia sp!, { r4 - r11, pc } */ 2997 tcg_out_ldstm(s, COND_AL, INSN_LDMIA, TCG_REG_CALL_STACK, 2998 (1 << TCG_REG_R4) | (1 << TCG_REG_R5) | (1 << TCG_REG_R6) | 2999 (1 << TCG_REG_R7) | (1 << TCG_REG_R8) | (1 << TCG_REG_R9) | 3000 (1 << TCG_REG_R10) | (1 << TCG_REG_R11) | (1 << TCG_REG_PC)); 3001} 3002 3003static void tcg_out_tb_start(TCGContext *s) 3004{ 3005 /* nothing to do */ 3006} 3007 3008typedef struct { 3009 DebugFrameHeader h; 3010 uint8_t fde_def_cfa[4]; 3011 uint8_t fde_reg_ofs[18]; 3012} DebugFrame; 3013 3014#define ELF_HOST_MACHINE EM_ARM 3015 3016/* We're expecting a 2 byte uleb128 encoded value. */ 3017QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); 3018 3019static const DebugFrame debug_frame = { 3020 .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ 3021 .h.cie.id = -1, 3022 .h.cie.version = 1, 3023 .h.cie.code_align = 1, 3024 .h.cie.data_align = 0x7c, /* sleb128 -4 */ 3025 .h.cie.return_column = 14, 3026 3027 /* Total FDE size does not include the "len" member. */ 3028 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 3029 3030 .fde_def_cfa = { 3031 12, 13, /* DW_CFA_def_cfa sp, ... */ 3032 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 3033 (FRAME_SIZE >> 7) 3034 }, 3035 .fde_reg_ofs = { 3036 /* The following must match the stmdb in the prologue. */ 3037 0x8e, 1, /* DW_CFA_offset, lr, -4 */ 3038 0x8b, 2, /* DW_CFA_offset, r11, -8 */ 3039 0x8a, 3, /* DW_CFA_offset, r10, -12 */ 3040 0x89, 4, /* DW_CFA_offset, r9, -16 */ 3041 0x88, 5, /* DW_CFA_offset, r8, -20 */ 3042 0x87, 6, /* DW_CFA_offset, r7, -24 */ 3043 0x86, 7, /* DW_CFA_offset, r6, -28 */ 3044 0x85, 8, /* DW_CFA_offset, r5, -32 */ 3045 0x84, 9, /* DW_CFA_offset, r4, -36 */ 3046 } 3047}; 3048 3049void tcg_register_jit(const void *buf, size_t buf_size) 3050{ 3051 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 3052} 3053