1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Andrzej Zaborowski 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25#include "elf.h" 26#include "../tcg-ldst.c.inc" 27#include "../tcg-pool.c.inc" 28 29int arm_arch = __ARM_ARCH; 30 31#ifndef use_idiv_instructions 32bool use_idiv_instructions; 33#endif 34#ifndef use_neon_instructions 35bool use_neon_instructions; 36#endif 37 38#ifdef CONFIG_DEBUG_TCG 39static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 40 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", 41 "%r8", "%r9", "%r10", "%r11", "%r12", "%sp", "%r14", "%pc", 42 "%q0", "%q1", "%q2", "%q3", "%q4", "%q5", "%q6", "%q7", 43 "%q8", "%q9", "%q10", "%q11", "%q12", "%q13", "%q14", "%q15", 44}; 45#endif 46 47static const int tcg_target_reg_alloc_order[] = { 48 TCG_REG_R4, 49 TCG_REG_R5, 50 TCG_REG_R6, 51 TCG_REG_R7, 52 TCG_REG_R8, 53 TCG_REG_R9, 54 TCG_REG_R10, 55 TCG_REG_R11, 56 TCG_REG_R13, 57 TCG_REG_R0, 58 TCG_REG_R1, 59 TCG_REG_R2, 60 TCG_REG_R3, 61 TCG_REG_R12, 62 TCG_REG_R14, 63 64 TCG_REG_Q0, 65 TCG_REG_Q1, 66 TCG_REG_Q2, 67 TCG_REG_Q3, 68 /* Q4 - Q7 are call-saved, and skipped. */ 69 TCG_REG_Q8, 70 TCG_REG_Q9, 71 TCG_REG_Q10, 72 TCG_REG_Q11, 73 TCG_REG_Q12, 74 TCG_REG_Q13, 75 TCG_REG_Q14, 76 TCG_REG_Q15, 77}; 78 79static const int tcg_target_call_iarg_regs[4] = { 80 TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3 81}; 82 83static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 84{ 85 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 86 tcg_debug_assert(slot >= 0 && slot <= 3); 87 return TCG_REG_R0 + slot; 88} 89 90#define TCG_REG_TMP TCG_REG_R12 91#define TCG_VEC_TMP TCG_REG_Q15 92#ifndef CONFIG_SOFTMMU 93#define TCG_REG_GUEST_BASE TCG_REG_R11 94#endif 95 96typedef enum { 97 COND_EQ = 0x0, 98 COND_NE = 0x1, 99 COND_CS = 0x2, /* Unsigned greater or equal */ 100 COND_CC = 0x3, /* Unsigned less than */ 101 COND_MI = 0x4, /* Negative */ 102 COND_PL = 0x5, /* Zero or greater */ 103 COND_VS = 0x6, /* Overflow */ 104 COND_VC = 0x7, /* No overflow */ 105 COND_HI = 0x8, /* Unsigned greater than */ 106 COND_LS = 0x9, /* Unsigned less or equal */ 107 COND_GE = 0xa, 108 COND_LT = 0xb, 109 COND_GT = 0xc, 110 COND_LE = 0xd, 111 COND_AL = 0xe, 112} ARMCond; 113 114#define TO_CPSR (1 << 20) 115 116#define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00) 117#define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20) 118#define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40) 119#define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60) 120#define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10) 121#define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30) 122#define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50) 123#define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70) 124 125typedef enum { 126 ARITH_AND = 0x0 << 21, 127 ARITH_EOR = 0x1 << 21, 128 ARITH_SUB = 0x2 << 21, 129 ARITH_RSB = 0x3 << 21, 130 ARITH_ADD = 0x4 << 21, 131 ARITH_ADC = 0x5 << 21, 132 ARITH_SBC = 0x6 << 21, 133 ARITH_RSC = 0x7 << 21, 134 ARITH_TST = 0x8 << 21 | TO_CPSR, 135 ARITH_CMP = 0xa << 21 | TO_CPSR, 136 ARITH_CMN = 0xb << 21 | TO_CPSR, 137 ARITH_ORR = 0xc << 21, 138 ARITH_MOV = 0xd << 21, 139 ARITH_BIC = 0xe << 21, 140 ARITH_MVN = 0xf << 21, 141 142 INSN_B = 0x0a000000, 143 144 INSN_CLZ = 0x016f0f10, 145 INSN_RBIT = 0x06ff0f30, 146 147 INSN_LDMIA = 0x08b00000, 148 INSN_STMDB = 0x09200000, 149 150 INSN_LDR_IMM = 0x04100000, 151 INSN_LDR_REG = 0x06100000, 152 INSN_STR_IMM = 0x04000000, 153 INSN_STR_REG = 0x06000000, 154 155 INSN_LDRH_IMM = 0x005000b0, 156 INSN_LDRH_REG = 0x001000b0, 157 INSN_LDRSH_IMM = 0x005000f0, 158 INSN_LDRSH_REG = 0x001000f0, 159 INSN_STRH_IMM = 0x004000b0, 160 INSN_STRH_REG = 0x000000b0, 161 162 INSN_LDRB_IMM = 0x04500000, 163 INSN_LDRB_REG = 0x06500000, 164 INSN_LDRSB_IMM = 0x005000d0, 165 INSN_LDRSB_REG = 0x001000d0, 166 INSN_STRB_IMM = 0x04400000, 167 INSN_STRB_REG = 0x06400000, 168 169 INSN_LDRD_IMM = 0x004000d0, 170 INSN_LDRD_REG = 0x000000d0, 171 INSN_STRD_IMM = 0x004000f0, 172 INSN_STRD_REG = 0x000000f0, 173 174 INSN_DMB_ISH = 0xf57ff05b, 175 INSN_DMB_MCR = 0xee070fba, 176 177 /* Architected nop introduced in v6k. */ 178 /* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this 179 also Just So Happened to do nothing on pre-v6k so that we 180 don't need to conditionalize it? */ 181 INSN_NOP_v6k = 0xe320f000, 182 /* Otherwise the assembler uses mov r0,r0 */ 183 INSN_NOP_v4 = (COND_AL << 28) | ARITH_MOV, 184 185 INSN_VADD = 0xf2000800, 186 INSN_VAND = 0xf2000110, 187 INSN_VBIC = 0xf2100110, 188 INSN_VEOR = 0xf3000110, 189 INSN_VORN = 0xf2300110, 190 INSN_VORR = 0xf2200110, 191 INSN_VSUB = 0xf3000800, 192 INSN_VMUL = 0xf2000910, 193 INSN_VQADD = 0xf2000010, 194 INSN_VQADD_U = 0xf3000010, 195 INSN_VQSUB = 0xf2000210, 196 INSN_VQSUB_U = 0xf3000210, 197 INSN_VMAX = 0xf2000600, 198 INSN_VMAX_U = 0xf3000600, 199 INSN_VMIN = 0xf2000610, 200 INSN_VMIN_U = 0xf3000610, 201 202 INSN_VABS = 0xf3b10300, 203 INSN_VMVN = 0xf3b00580, 204 INSN_VNEG = 0xf3b10380, 205 206 INSN_VCEQ0 = 0xf3b10100, 207 INSN_VCGT0 = 0xf3b10000, 208 INSN_VCGE0 = 0xf3b10080, 209 INSN_VCLE0 = 0xf3b10180, 210 INSN_VCLT0 = 0xf3b10200, 211 212 INSN_VCEQ = 0xf3000810, 213 INSN_VCGE = 0xf2000310, 214 INSN_VCGT = 0xf2000300, 215 INSN_VCGE_U = 0xf3000310, 216 INSN_VCGT_U = 0xf3000300, 217 218 INSN_VSHLI = 0xf2800510, /* VSHL (immediate) */ 219 INSN_VSARI = 0xf2800010, /* VSHR.S */ 220 INSN_VSHRI = 0xf3800010, /* VSHR.U */ 221 INSN_VSLI = 0xf3800510, 222 INSN_VSHL_S = 0xf2000400, /* VSHL.S (register) */ 223 INSN_VSHL_U = 0xf3000400, /* VSHL.U (register) */ 224 225 INSN_VBSL = 0xf3100110, 226 INSN_VBIT = 0xf3200110, 227 INSN_VBIF = 0xf3300110, 228 229 INSN_VTST = 0xf2000810, 230 231 INSN_VDUP_G = 0xee800b10, /* VDUP (ARM core register) */ 232 INSN_VDUP_S = 0xf3b00c00, /* VDUP (scalar) */ 233 INSN_VLDR_D = 0xed100b00, /* VLDR.64 */ 234 INSN_VLD1 = 0xf4200000, /* VLD1 (multiple single elements) */ 235 INSN_VLD1R = 0xf4a00c00, /* VLD1 (single element to all lanes) */ 236 INSN_VST1 = 0xf4000000, /* VST1 (multiple single elements) */ 237 INSN_VMOVI = 0xf2800010, /* VMOV (immediate) */ 238} ARMInsn; 239 240#define INSN_NOP (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4) 241 242static const uint8_t tcg_cond_to_arm_cond[] = { 243 [TCG_COND_EQ] = COND_EQ, 244 [TCG_COND_NE] = COND_NE, 245 [TCG_COND_LT] = COND_LT, 246 [TCG_COND_GE] = COND_GE, 247 [TCG_COND_LE] = COND_LE, 248 [TCG_COND_GT] = COND_GT, 249 /* unsigned */ 250 [TCG_COND_LTU] = COND_CC, 251 [TCG_COND_GEU] = COND_CS, 252 [TCG_COND_LEU] = COND_LS, 253 [TCG_COND_GTU] = COND_HI, 254}; 255 256static int encode_imm(uint32_t imm); 257 258/* TCG private relocation type: add with pc+imm8 */ 259#define R_ARM_PC8 11 260 261/* TCG private relocation type: vldr with imm8 << 2 */ 262#define R_ARM_PC11 12 263 264static bool reloc_pc24(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 265{ 266 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 267 ptrdiff_t offset = (tcg_ptr_byte_diff(target, src_rx) - 8) >> 2; 268 269 if (offset == sextract32(offset, 0, 24)) { 270 *src_rw = deposit32(*src_rw, 0, 24, offset); 271 return true; 272 } 273 return false; 274} 275 276static bool reloc_pc13(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 277{ 278 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 279 ptrdiff_t offset = tcg_ptr_byte_diff(target, src_rx) - 8; 280 281 if (offset >= -0xfff && offset <= 0xfff) { 282 tcg_insn_unit insn = *src_rw; 283 bool u = (offset >= 0); 284 if (!u) { 285 offset = -offset; 286 } 287 insn = deposit32(insn, 23, 1, u); 288 insn = deposit32(insn, 0, 12, offset); 289 *src_rw = insn; 290 return true; 291 } 292 return false; 293} 294 295static bool reloc_pc11(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 296{ 297 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 298 ptrdiff_t offset = (tcg_ptr_byte_diff(target, src_rx) - 8) / 4; 299 300 if (offset >= -0xff && offset <= 0xff) { 301 tcg_insn_unit insn = *src_rw; 302 bool u = (offset >= 0); 303 if (!u) { 304 offset = -offset; 305 } 306 insn = deposit32(insn, 23, 1, u); 307 insn = deposit32(insn, 0, 8, offset); 308 *src_rw = insn; 309 return true; 310 } 311 return false; 312} 313 314static bool reloc_pc8(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 315{ 316 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 317 ptrdiff_t offset = tcg_ptr_byte_diff(target, src_rx) - 8; 318 int imm12 = encode_imm(offset); 319 320 if (imm12 >= 0) { 321 *src_rw = deposit32(*src_rw, 0, 12, imm12); 322 return true; 323 } 324 return false; 325} 326 327static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 328 intptr_t value, intptr_t addend) 329{ 330 tcg_debug_assert(addend == 0); 331 switch (type) { 332 case R_ARM_PC24: 333 return reloc_pc24(code_ptr, (const tcg_insn_unit *)value); 334 case R_ARM_PC13: 335 return reloc_pc13(code_ptr, (const tcg_insn_unit *)value); 336 case R_ARM_PC11: 337 return reloc_pc11(code_ptr, (const tcg_insn_unit *)value); 338 case R_ARM_PC8: 339 return reloc_pc8(code_ptr, (const tcg_insn_unit *)value); 340 default: 341 g_assert_not_reached(); 342 } 343} 344 345#define TCG_CT_CONST_ARM 0x100 346#define TCG_CT_CONST_INV 0x200 347#define TCG_CT_CONST_NEG 0x400 348#define TCG_CT_CONST_ZERO 0x800 349#define TCG_CT_CONST_ORRI 0x1000 350#define TCG_CT_CONST_ANDI 0x2000 351 352#define ALL_GENERAL_REGS 0xffffu 353#define ALL_VECTOR_REGS 0xffff0000u 354 355/* 356 * r0-r2 will be overwritten when reading the tlb entry (softmmu only) 357 * and r0-r1 doing the byte swapping, so don't use these. 358 * r3 is removed for softmmu to avoid clashes with helper arguments. 359 */ 360#ifdef CONFIG_SOFTMMU 361#define ALL_QLOAD_REGS \ 362 (ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1) | \ 363 (1 << TCG_REG_R2) | (1 << TCG_REG_R3) | \ 364 (1 << TCG_REG_R14))) 365#define ALL_QSTORE_REGS \ 366 (ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1) | \ 367 (1 << TCG_REG_R2) | (1 << TCG_REG_R14) | \ 368 ((TARGET_LONG_BITS == 64) << TCG_REG_R3))) 369#else 370#define ALL_QLOAD_REGS ALL_GENERAL_REGS 371#define ALL_QSTORE_REGS \ 372 (ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1))) 373#endif 374 375/* 376 * ARM immediates for ALU instructions are made of an unsigned 8-bit 377 * right-rotated by an even amount between 0 and 30. 378 * 379 * Return < 0 if @imm cannot be encoded, else the entire imm12 field. 380 */ 381static int encode_imm(uint32_t imm) 382{ 383 uint32_t rot, imm8; 384 385 /* Simple case, no rotation required. */ 386 if ((imm & ~0xff) == 0) { 387 return imm; 388 } 389 390 /* Next, try a simple even shift. */ 391 rot = ctz32(imm) & ~1; 392 imm8 = imm >> rot; 393 rot = 32 - rot; 394 if ((imm8 & ~0xff) == 0) { 395 goto found; 396 } 397 398 /* 399 * Finally, try harder with rotations. 400 * The ctz test above will have taken care of rotates >= 8. 401 */ 402 for (rot = 2; rot < 8; rot += 2) { 403 imm8 = rol32(imm, rot); 404 if ((imm8 & ~0xff) == 0) { 405 goto found; 406 } 407 } 408 /* Fail: imm cannot be encoded. */ 409 return -1; 410 411 found: 412 /* Note that rot is even, and we discard bit 0 by shifting by 7. */ 413 return rot << 7 | imm8; 414} 415 416static int encode_imm_nofail(uint32_t imm) 417{ 418 int ret = encode_imm(imm); 419 tcg_debug_assert(ret >= 0); 420 return ret; 421} 422 423static bool check_fit_imm(uint32_t imm) 424{ 425 return encode_imm(imm) >= 0; 426} 427 428/* Return true if v16 is a valid 16-bit shifted immediate. */ 429static bool is_shimm16(uint16_t v16, int *cmode, int *imm8) 430{ 431 if (v16 == (v16 & 0xff)) { 432 *cmode = 0x8; 433 *imm8 = v16 & 0xff; 434 return true; 435 } else if (v16 == (v16 & 0xff00)) { 436 *cmode = 0xa; 437 *imm8 = v16 >> 8; 438 return true; 439 } 440 return false; 441} 442 443/* Return true if v32 is a valid 32-bit shifted immediate. */ 444static bool is_shimm32(uint32_t v32, int *cmode, int *imm8) 445{ 446 if (v32 == (v32 & 0xff)) { 447 *cmode = 0x0; 448 *imm8 = v32 & 0xff; 449 return true; 450 } else if (v32 == (v32 & 0xff00)) { 451 *cmode = 0x2; 452 *imm8 = (v32 >> 8) & 0xff; 453 return true; 454 } else if (v32 == (v32 & 0xff0000)) { 455 *cmode = 0x4; 456 *imm8 = (v32 >> 16) & 0xff; 457 return true; 458 } else if (v32 == (v32 & 0xff000000)) { 459 *cmode = 0x6; 460 *imm8 = v32 >> 24; 461 return true; 462 } 463 return false; 464} 465 466/* Return true if v32 is a valid 32-bit shifting ones immediate. */ 467static bool is_soimm32(uint32_t v32, int *cmode, int *imm8) 468{ 469 if ((v32 & 0xffff00ff) == 0xff) { 470 *cmode = 0xc; 471 *imm8 = (v32 >> 8) & 0xff; 472 return true; 473 } else if ((v32 & 0xff00ffff) == 0xffff) { 474 *cmode = 0xd; 475 *imm8 = (v32 >> 16) & 0xff; 476 return true; 477 } 478 return false; 479} 480 481/* 482 * Return non-zero if v32 can be formed by MOVI+ORR. 483 * Place the parameters for MOVI in (cmode, imm8). 484 * Return the cmode for ORR; the imm8 can be had via extraction from v32. 485 */ 486static int is_shimm32_pair(uint32_t v32, int *cmode, int *imm8) 487{ 488 int i; 489 490 for (i = 6; i > 0; i -= 2) { 491 /* Mask out one byte we can add with ORR. */ 492 uint32_t tmp = v32 & ~(0xffu << (i * 4)); 493 if (is_shimm32(tmp, cmode, imm8) || 494 is_soimm32(tmp, cmode, imm8)) { 495 break; 496 } 497 } 498 return i; 499} 500 501/* Return true if V is a valid 16-bit or 32-bit shifted immediate. */ 502static bool is_shimm1632(uint32_t v32, int *cmode, int *imm8) 503{ 504 if (v32 == deposit32(v32, 16, 16, v32)) { 505 return is_shimm16(v32, cmode, imm8); 506 } else { 507 return is_shimm32(v32, cmode, imm8); 508 } 509} 510 511/* Test if a constant matches the constraint. 512 * TODO: define constraints for: 513 * 514 * ldr/str offset: between -0xfff and 0xfff 515 * ldrh/strh offset: between -0xff and 0xff 516 * mov operand2: values represented with x << (2 * y), x < 0x100 517 * add, sub, eor...: ditto 518 */ 519static bool tcg_target_const_match(int64_t val, TCGType type, int ct) 520{ 521 if (ct & TCG_CT_CONST) { 522 return 1; 523 } else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val)) { 524 return 1; 525 } else if ((ct & TCG_CT_CONST_INV) && check_fit_imm(~val)) { 526 return 1; 527 } else if ((ct & TCG_CT_CONST_NEG) && check_fit_imm(-val)) { 528 return 1; 529 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 530 return 1; 531 } 532 533 switch (ct & (TCG_CT_CONST_ORRI | TCG_CT_CONST_ANDI)) { 534 case 0: 535 break; 536 case TCG_CT_CONST_ANDI: 537 val = ~val; 538 /* fallthru */ 539 case TCG_CT_CONST_ORRI: 540 if (val == deposit64(val, 32, 32, val)) { 541 int cmode, imm8; 542 return is_shimm1632(val, &cmode, &imm8); 543 } 544 break; 545 default: 546 /* Both bits should not be set for the same insn. */ 547 g_assert_not_reached(); 548 } 549 550 return 0; 551} 552 553static void tcg_out_b_imm(TCGContext *s, ARMCond cond, int32_t offset) 554{ 555 tcg_out32(s, (cond << 28) | INSN_B | 556 (((offset - 8) >> 2) & 0x00ffffff)); 557} 558 559static void tcg_out_bl_imm(TCGContext *s, ARMCond cond, int32_t offset) 560{ 561 tcg_out32(s, (cond << 28) | 0x0b000000 | 562 (((offset - 8) >> 2) & 0x00ffffff)); 563} 564 565static void tcg_out_blx_reg(TCGContext *s, ARMCond cond, TCGReg rn) 566{ 567 tcg_out32(s, (cond << 28) | 0x012fff30 | rn); 568} 569 570static void tcg_out_blx_imm(TCGContext *s, int32_t offset) 571{ 572 tcg_out32(s, 0xfa000000 | ((offset & 2) << 23) | 573 (((offset - 8) >> 2) & 0x00ffffff)); 574} 575 576static void tcg_out_dat_reg(TCGContext *s, ARMCond cond, ARMInsn opc, 577 TCGReg rd, TCGReg rn, TCGReg rm, int shift) 578{ 579 tcg_out32(s, (cond << 28) | (0 << 25) | opc | 580 (rn << 16) | (rd << 12) | shift | rm); 581} 582 583static void tcg_out_mov_reg(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rm) 584{ 585 /* Simple reg-reg move, optimising out the 'do nothing' case */ 586 if (rd != rm) { 587 tcg_out_dat_reg(s, cond, ARITH_MOV, rd, 0, rm, SHIFT_IMM_LSL(0)); 588 } 589} 590 591static void tcg_out_bx_reg(TCGContext *s, ARMCond cond, TCGReg rn) 592{ 593 tcg_out32(s, (cond << 28) | 0x012fff10 | rn); 594} 595 596static void tcg_out_b_reg(TCGContext *s, ARMCond cond, TCGReg rn) 597{ 598 /* 599 * Unless the C portion of QEMU is compiled as thumb, we don't need 600 * true BX semantics; merely a branch to an address held in a register. 601 */ 602 tcg_out_bx_reg(s, cond, rn); 603} 604 605static void tcg_out_dat_imm(TCGContext *s, ARMCond cond, ARMInsn opc, 606 TCGReg rd, TCGReg rn, int im) 607{ 608 tcg_out32(s, (cond << 28) | (1 << 25) | opc | 609 (rn << 16) | (rd << 12) | im); 610} 611 612static void tcg_out_ldstm(TCGContext *s, ARMCond cond, ARMInsn opc, 613 TCGReg rn, uint16_t mask) 614{ 615 tcg_out32(s, (cond << 28) | opc | (rn << 16) | mask); 616} 617 618/* Note that this routine is used for both LDR and LDRH formats, so we do 619 not wish to include an immediate shift at this point. */ 620static void tcg_out_memop_r(TCGContext *s, ARMCond cond, ARMInsn opc, TCGReg rt, 621 TCGReg rn, TCGReg rm, bool u, bool p, bool w) 622{ 623 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) 624 | (w << 21) | (rn << 16) | (rt << 12) | rm); 625} 626 627static void tcg_out_memop_8(TCGContext *s, ARMCond cond, ARMInsn opc, TCGReg rt, 628 TCGReg rn, int imm8, bool p, bool w) 629{ 630 bool u = 1; 631 if (imm8 < 0) { 632 imm8 = -imm8; 633 u = 0; 634 } 635 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | 636 (rn << 16) | (rt << 12) | ((imm8 & 0xf0) << 4) | (imm8 & 0xf)); 637} 638 639static void tcg_out_memop_12(TCGContext *s, ARMCond cond, ARMInsn opc, 640 TCGReg rt, TCGReg rn, int imm12, bool p, bool w) 641{ 642 bool u = 1; 643 if (imm12 < 0) { 644 imm12 = -imm12; 645 u = 0; 646 } 647 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | 648 (rn << 16) | (rt << 12) | imm12); 649} 650 651static void tcg_out_ld32_12(TCGContext *s, ARMCond cond, TCGReg rt, 652 TCGReg rn, int imm12) 653{ 654 tcg_out_memop_12(s, cond, INSN_LDR_IMM, rt, rn, imm12, 1, 0); 655} 656 657static void tcg_out_st32_12(TCGContext *s, ARMCond cond, TCGReg rt, 658 TCGReg rn, int imm12) 659{ 660 tcg_out_memop_12(s, cond, INSN_STR_IMM, rt, rn, imm12, 1, 0); 661} 662 663static void tcg_out_ld32_r(TCGContext *s, ARMCond cond, TCGReg rt, 664 TCGReg rn, TCGReg rm) 665{ 666 tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 0); 667} 668 669static void tcg_out_st32_r(TCGContext *s, ARMCond cond, TCGReg rt, 670 TCGReg rn, TCGReg rm) 671{ 672 tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 0); 673} 674 675static void tcg_out_ldrd_8(TCGContext *s, ARMCond cond, TCGReg rt, 676 TCGReg rn, int imm8) 677{ 678 tcg_out_memop_8(s, cond, INSN_LDRD_IMM, rt, rn, imm8, 1, 0); 679} 680 681static void tcg_out_ldrd_r(TCGContext *s, ARMCond cond, TCGReg rt, 682 TCGReg rn, TCGReg rm) 683{ 684 tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 0); 685} 686 687static void __attribute__((unused)) 688tcg_out_ldrd_rwb(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, TCGReg rm) 689{ 690 tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 1); 691} 692 693static void tcg_out_strd_8(TCGContext *s, ARMCond cond, TCGReg rt, 694 TCGReg rn, int imm8) 695{ 696 tcg_out_memop_8(s, cond, INSN_STRD_IMM, rt, rn, imm8, 1, 0); 697} 698 699static void tcg_out_strd_r(TCGContext *s, ARMCond cond, TCGReg rt, 700 TCGReg rn, TCGReg rm) 701{ 702 tcg_out_memop_r(s, cond, INSN_STRD_REG, rt, rn, rm, 1, 1, 0); 703} 704 705/* Register pre-increment with base writeback. */ 706static void tcg_out_ld32_rwb(TCGContext *s, ARMCond cond, TCGReg rt, 707 TCGReg rn, TCGReg rm) 708{ 709 tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 1); 710} 711 712static void tcg_out_st32_rwb(TCGContext *s, ARMCond cond, TCGReg rt, 713 TCGReg rn, TCGReg rm) 714{ 715 tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 1); 716} 717 718static void tcg_out_ld16u_8(TCGContext *s, ARMCond cond, TCGReg rt, 719 TCGReg rn, int imm8) 720{ 721 tcg_out_memop_8(s, cond, INSN_LDRH_IMM, rt, rn, imm8, 1, 0); 722} 723 724static void tcg_out_st16_8(TCGContext *s, ARMCond cond, TCGReg rt, 725 TCGReg rn, int imm8) 726{ 727 tcg_out_memop_8(s, cond, INSN_STRH_IMM, rt, rn, imm8, 1, 0); 728} 729 730static void tcg_out_ld16u_r(TCGContext *s, ARMCond cond, TCGReg rt, 731 TCGReg rn, TCGReg rm) 732{ 733 tcg_out_memop_r(s, cond, INSN_LDRH_REG, rt, rn, rm, 1, 1, 0); 734} 735 736static void tcg_out_st16_r(TCGContext *s, ARMCond cond, TCGReg rt, 737 TCGReg rn, TCGReg rm) 738{ 739 tcg_out_memop_r(s, cond, INSN_STRH_REG, rt, rn, rm, 1, 1, 0); 740} 741 742static void tcg_out_ld16s_8(TCGContext *s, ARMCond cond, TCGReg rt, 743 TCGReg rn, int imm8) 744{ 745 tcg_out_memop_8(s, cond, INSN_LDRSH_IMM, rt, rn, imm8, 1, 0); 746} 747 748static void tcg_out_ld16s_r(TCGContext *s, ARMCond cond, TCGReg rt, 749 TCGReg rn, TCGReg rm) 750{ 751 tcg_out_memop_r(s, cond, INSN_LDRSH_REG, rt, rn, rm, 1, 1, 0); 752} 753 754static void tcg_out_ld8_12(TCGContext *s, ARMCond cond, TCGReg rt, 755 TCGReg rn, int imm12) 756{ 757 tcg_out_memop_12(s, cond, INSN_LDRB_IMM, rt, rn, imm12, 1, 0); 758} 759 760static void tcg_out_st8_12(TCGContext *s, ARMCond cond, TCGReg rt, 761 TCGReg rn, int imm12) 762{ 763 tcg_out_memop_12(s, cond, INSN_STRB_IMM, rt, rn, imm12, 1, 0); 764} 765 766static void tcg_out_ld8_r(TCGContext *s, ARMCond cond, TCGReg rt, 767 TCGReg rn, TCGReg rm) 768{ 769 tcg_out_memop_r(s, cond, INSN_LDRB_REG, rt, rn, rm, 1, 1, 0); 770} 771 772static void tcg_out_st8_r(TCGContext *s, ARMCond cond, TCGReg rt, 773 TCGReg rn, TCGReg rm) 774{ 775 tcg_out_memop_r(s, cond, INSN_STRB_REG, rt, rn, rm, 1, 1, 0); 776} 777 778static void tcg_out_ld8s_8(TCGContext *s, ARMCond cond, TCGReg rt, 779 TCGReg rn, int imm8) 780{ 781 tcg_out_memop_8(s, cond, INSN_LDRSB_IMM, rt, rn, imm8, 1, 0); 782} 783 784static void tcg_out_ld8s_r(TCGContext *s, ARMCond cond, TCGReg rt, 785 TCGReg rn, TCGReg rm) 786{ 787 tcg_out_memop_r(s, cond, INSN_LDRSB_REG, rt, rn, rm, 1, 1, 0); 788} 789 790static void tcg_out_movi_pool(TCGContext *s, ARMCond cond, 791 TCGReg rd, uint32_t arg) 792{ 793 new_pool_label(s, arg, R_ARM_PC13, s->code_ptr, 0); 794 tcg_out_ld32_12(s, cond, rd, TCG_REG_PC, 0); 795} 796 797static void tcg_out_movi32(TCGContext *s, ARMCond cond, 798 TCGReg rd, uint32_t arg) 799{ 800 int imm12, diff, opc, sh1, sh2; 801 uint32_t tt0, tt1, tt2; 802 803 /* Check a single MOV/MVN before anything else. */ 804 imm12 = encode_imm(arg); 805 if (imm12 >= 0) { 806 tcg_out_dat_imm(s, cond, ARITH_MOV, rd, 0, imm12); 807 return; 808 } 809 imm12 = encode_imm(~arg); 810 if (imm12 >= 0) { 811 tcg_out_dat_imm(s, cond, ARITH_MVN, rd, 0, imm12); 812 return; 813 } 814 815 /* Check for a pc-relative address. This will usually be the TB, 816 or within the TB, which is immediately before the code block. */ 817 diff = tcg_pcrel_diff(s, (void *)arg) - 8; 818 if (diff >= 0) { 819 imm12 = encode_imm(diff); 820 if (imm12 >= 0) { 821 tcg_out_dat_imm(s, cond, ARITH_ADD, rd, TCG_REG_PC, imm12); 822 return; 823 } 824 } else { 825 imm12 = encode_imm(-diff); 826 if (imm12 >= 0) { 827 tcg_out_dat_imm(s, cond, ARITH_SUB, rd, TCG_REG_PC, imm12); 828 return; 829 } 830 } 831 832 /* Use movw + movt. */ 833 if (use_armv7_instructions) { 834 /* movw */ 835 tcg_out32(s, (cond << 28) | 0x03000000 | (rd << 12) 836 | ((arg << 4) & 0x000f0000) | (arg & 0xfff)); 837 if (arg & 0xffff0000) { 838 /* movt */ 839 tcg_out32(s, (cond << 28) | 0x03400000 | (rd << 12) 840 | ((arg >> 12) & 0x000f0000) | ((arg >> 16) & 0xfff)); 841 } 842 return; 843 } 844 845 /* Look for sequences of two insns. If we have lots of 1's, we can 846 shorten the sequence by beginning with mvn and then clearing 847 higher bits with eor. */ 848 tt0 = arg; 849 opc = ARITH_MOV; 850 if (ctpop32(arg) > 16) { 851 tt0 = ~arg; 852 opc = ARITH_MVN; 853 } 854 sh1 = ctz32(tt0) & ~1; 855 tt1 = tt0 & ~(0xff << sh1); 856 sh2 = ctz32(tt1) & ~1; 857 tt2 = tt1 & ~(0xff << sh2); 858 if (tt2 == 0) { 859 int rot; 860 861 rot = ((32 - sh1) << 7) & 0xf00; 862 tcg_out_dat_imm(s, cond, opc, rd, 0, ((tt0 >> sh1) & 0xff) | rot); 863 rot = ((32 - sh2) << 7) & 0xf00; 864 tcg_out_dat_imm(s, cond, ARITH_EOR, rd, rd, 865 ((tt0 >> sh2) & 0xff) | rot); 866 return; 867 } 868 869 /* Otherwise, drop it into the constant pool. */ 870 tcg_out_movi_pool(s, cond, rd, arg); 871} 872 873/* 874 * Emit either the reg,imm or reg,reg form of a data-processing insn. 875 * rhs must satisfy the "rI" constraint. 876 */ 877static void tcg_out_dat_rI(TCGContext *s, ARMCond cond, ARMInsn opc, 878 TCGReg dst, TCGReg lhs, TCGArg rhs, int rhs_is_const) 879{ 880 if (rhs_is_const) { 881 tcg_out_dat_imm(s, cond, opc, dst, lhs, encode_imm_nofail(rhs)); 882 } else { 883 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); 884 } 885} 886 887/* 888 * Emit either the reg,imm or reg,reg form of a data-processing insn. 889 * rhs must satisfy the "rIK" constraint. 890 */ 891static void tcg_out_dat_rIK(TCGContext *s, ARMCond cond, ARMInsn opc, 892 ARMInsn opinv, TCGReg dst, TCGReg lhs, TCGArg rhs, 893 bool rhs_is_const) 894{ 895 if (rhs_is_const) { 896 int imm12 = encode_imm(rhs); 897 if (imm12 < 0) { 898 imm12 = encode_imm_nofail(~rhs); 899 opc = opinv; 900 } 901 tcg_out_dat_imm(s, cond, opc, dst, lhs, imm12); 902 } else { 903 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); 904 } 905} 906 907static void tcg_out_dat_rIN(TCGContext *s, ARMCond cond, ARMInsn opc, 908 ARMInsn opneg, TCGReg dst, TCGReg lhs, TCGArg rhs, 909 bool rhs_is_const) 910{ 911 /* Emit either the reg,imm or reg,reg form of a data-processing insn. 912 * rhs must satisfy the "rIN" constraint. 913 */ 914 if (rhs_is_const) { 915 int imm12 = encode_imm(rhs); 916 if (imm12 < 0) { 917 imm12 = encode_imm_nofail(-rhs); 918 opc = opneg; 919 } 920 tcg_out_dat_imm(s, cond, opc, dst, lhs, imm12); 921 } else { 922 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); 923 } 924} 925 926static void tcg_out_mul32(TCGContext *s, ARMCond cond, TCGReg rd, 927 TCGReg rn, TCGReg rm) 928{ 929 /* mul */ 930 tcg_out32(s, (cond << 28) | 0x90 | (rd << 16) | (rm << 8) | rn); 931} 932 933static void tcg_out_umull32(TCGContext *s, ARMCond cond, TCGReg rd0, 934 TCGReg rd1, TCGReg rn, TCGReg rm) 935{ 936 /* umull */ 937 tcg_out32(s, (cond << 28) | 0x00800090 | 938 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); 939} 940 941static void tcg_out_smull32(TCGContext *s, ARMCond cond, TCGReg rd0, 942 TCGReg rd1, TCGReg rn, TCGReg rm) 943{ 944 /* smull */ 945 tcg_out32(s, (cond << 28) | 0x00c00090 | 946 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); 947} 948 949static void tcg_out_sdiv(TCGContext *s, ARMCond cond, 950 TCGReg rd, TCGReg rn, TCGReg rm) 951{ 952 tcg_out32(s, 0x0710f010 | (cond << 28) | (rd << 16) | rn | (rm << 8)); 953} 954 955static void tcg_out_udiv(TCGContext *s, ARMCond cond, 956 TCGReg rd, TCGReg rn, TCGReg rm) 957{ 958 tcg_out32(s, 0x0730f010 | (cond << 28) | (rd << 16) | rn | (rm << 8)); 959} 960 961static void tcg_out_ext8s(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rn) 962{ 963 /* sxtb */ 964 tcg_out32(s, 0x06af0070 | (cond << 28) | (rd << 12) | rn); 965} 966 967static void __attribute__((unused)) 968tcg_out_ext8u(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rn) 969{ 970 tcg_out_dat_imm(s, cond, ARITH_AND, rd, rn, 0xff); 971} 972 973static void tcg_out_ext16s(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rn) 974{ 975 /* sxth */ 976 tcg_out32(s, 0x06bf0070 | (cond << 28) | (rd << 12) | rn); 977} 978 979static void tcg_out_ext16u(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rn) 980{ 981 /* uxth */ 982 tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | rn); 983} 984 985static void tcg_out_bswap16(TCGContext *s, ARMCond cond, 986 TCGReg rd, TCGReg rn, int flags) 987{ 988 if (flags & TCG_BSWAP_OS) { 989 /* revsh */ 990 tcg_out32(s, 0x06ff0fb0 | (cond << 28) | (rd << 12) | rn); 991 return; 992 } 993 994 /* rev16 */ 995 tcg_out32(s, 0x06bf0fb0 | (cond << 28) | (rd << 12) | rn); 996 if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 997 /* uxth */ 998 tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | rd); 999 } 1000} 1001 1002static void tcg_out_bswap32(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rn) 1003{ 1004 /* rev */ 1005 tcg_out32(s, 0x06bf0f30 | (cond << 28) | (rd << 12) | rn); 1006} 1007 1008static void tcg_out_deposit(TCGContext *s, ARMCond cond, TCGReg rd, 1009 TCGArg a1, int ofs, int len, bool const_a1) 1010{ 1011 if (const_a1) { 1012 /* bfi becomes bfc with rn == 15. */ 1013 a1 = 15; 1014 } 1015 /* bfi/bfc */ 1016 tcg_out32(s, 0x07c00010 | (cond << 28) | (rd << 12) | a1 1017 | (ofs << 7) | ((ofs + len - 1) << 16)); 1018} 1019 1020static void tcg_out_extract(TCGContext *s, ARMCond cond, TCGReg rd, 1021 TCGReg rn, int ofs, int len) 1022{ 1023 /* ubfx */ 1024 tcg_out32(s, 0x07e00050 | (cond << 28) | (rd << 12) | rn 1025 | (ofs << 7) | ((len - 1) << 16)); 1026} 1027 1028static void tcg_out_sextract(TCGContext *s, ARMCond cond, TCGReg rd, 1029 TCGReg rn, int ofs, int len) 1030{ 1031 /* sbfx */ 1032 tcg_out32(s, 0x07a00050 | (cond << 28) | (rd << 12) | rn 1033 | (ofs << 7) | ((len - 1) << 16)); 1034} 1035 1036static void tcg_out_ld32u(TCGContext *s, ARMCond cond, 1037 TCGReg rd, TCGReg rn, int32_t offset) 1038{ 1039 if (offset > 0xfff || offset < -0xfff) { 1040 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1041 tcg_out_ld32_r(s, cond, rd, rn, TCG_REG_TMP); 1042 } else 1043 tcg_out_ld32_12(s, cond, rd, rn, offset); 1044} 1045 1046static void tcg_out_st32(TCGContext *s, ARMCond cond, 1047 TCGReg rd, TCGReg rn, int32_t offset) 1048{ 1049 if (offset > 0xfff || offset < -0xfff) { 1050 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1051 tcg_out_st32_r(s, cond, rd, rn, TCG_REG_TMP); 1052 } else 1053 tcg_out_st32_12(s, cond, rd, rn, offset); 1054} 1055 1056static void tcg_out_ld16u(TCGContext *s, ARMCond cond, 1057 TCGReg rd, TCGReg rn, int32_t offset) 1058{ 1059 if (offset > 0xff || offset < -0xff) { 1060 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1061 tcg_out_ld16u_r(s, cond, rd, rn, TCG_REG_TMP); 1062 } else 1063 tcg_out_ld16u_8(s, cond, rd, rn, offset); 1064} 1065 1066static void tcg_out_ld16s(TCGContext *s, ARMCond cond, 1067 TCGReg rd, TCGReg rn, int32_t offset) 1068{ 1069 if (offset > 0xff || offset < -0xff) { 1070 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1071 tcg_out_ld16s_r(s, cond, rd, rn, TCG_REG_TMP); 1072 } else 1073 tcg_out_ld16s_8(s, cond, rd, rn, offset); 1074} 1075 1076static void tcg_out_st16(TCGContext *s, ARMCond cond, 1077 TCGReg rd, TCGReg rn, int32_t offset) 1078{ 1079 if (offset > 0xff || offset < -0xff) { 1080 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1081 tcg_out_st16_r(s, cond, rd, rn, TCG_REG_TMP); 1082 } else 1083 tcg_out_st16_8(s, cond, rd, rn, offset); 1084} 1085 1086static void tcg_out_ld8u(TCGContext *s, ARMCond cond, 1087 TCGReg rd, TCGReg rn, int32_t offset) 1088{ 1089 if (offset > 0xfff || offset < -0xfff) { 1090 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1091 tcg_out_ld8_r(s, cond, rd, rn, TCG_REG_TMP); 1092 } else 1093 tcg_out_ld8_12(s, cond, rd, rn, offset); 1094} 1095 1096static void tcg_out_ld8s(TCGContext *s, ARMCond cond, 1097 TCGReg rd, TCGReg rn, int32_t offset) 1098{ 1099 if (offset > 0xff || offset < -0xff) { 1100 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1101 tcg_out_ld8s_r(s, cond, rd, rn, TCG_REG_TMP); 1102 } else 1103 tcg_out_ld8s_8(s, cond, rd, rn, offset); 1104} 1105 1106static void tcg_out_st8(TCGContext *s, ARMCond cond, 1107 TCGReg rd, TCGReg rn, int32_t offset) 1108{ 1109 if (offset > 0xfff || offset < -0xfff) { 1110 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1111 tcg_out_st8_r(s, cond, rd, rn, TCG_REG_TMP); 1112 } else 1113 tcg_out_st8_12(s, cond, rd, rn, offset); 1114} 1115 1116/* 1117 * The _goto case is normally between TBs within the same code buffer, and 1118 * with the code buffer limited to 16MB we wouldn't need the long case. 1119 * But we also use it for the tail-call to the qemu_ld/st helpers, which does. 1120 */ 1121static void tcg_out_goto(TCGContext *s, ARMCond cond, const tcg_insn_unit *addr) 1122{ 1123 intptr_t addri = (intptr_t)addr; 1124 ptrdiff_t disp = tcg_pcrel_diff(s, addr); 1125 bool arm_mode = !(addri & 1); 1126 1127 if (arm_mode && disp - 8 < 0x01fffffd && disp - 8 > -0x01fffffd) { 1128 tcg_out_b_imm(s, cond, disp); 1129 return; 1130 } 1131 1132 /* LDR is interworking from v5t. */ 1133 tcg_out_movi_pool(s, cond, TCG_REG_PC, addri); 1134} 1135 1136/* 1137 * The call case is mostly used for helpers - so it's not unreasonable 1138 * for them to be beyond branch range. 1139 */ 1140static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *addr) 1141{ 1142 intptr_t addri = (intptr_t)addr; 1143 ptrdiff_t disp = tcg_pcrel_diff(s, addr); 1144 bool arm_mode = !(addri & 1); 1145 1146 if (disp - 8 < 0x02000000 && disp - 8 >= -0x02000000) { 1147 if (arm_mode) { 1148 tcg_out_bl_imm(s, COND_AL, disp); 1149 } else { 1150 tcg_out_blx_imm(s, disp); 1151 } 1152 return; 1153 } 1154 1155 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri); 1156 tcg_out_blx_reg(s, COND_AL, TCG_REG_TMP); 1157} 1158 1159static void tcg_out_call(TCGContext *s, const tcg_insn_unit *addr, 1160 const TCGHelperInfo *info) 1161{ 1162 tcg_out_call_int(s, addr); 1163} 1164 1165static void tcg_out_goto_label(TCGContext *s, ARMCond cond, TCGLabel *l) 1166{ 1167 if (l->has_value) { 1168 tcg_out_goto(s, cond, l->u.value_ptr); 1169 } else { 1170 tcg_out_reloc(s, s->code_ptr, R_ARM_PC24, l, 0); 1171 tcg_out_b_imm(s, cond, 0); 1172 } 1173} 1174 1175static void tcg_out_mb(TCGContext *s, TCGArg a0) 1176{ 1177 if (use_armv7_instructions) { 1178 tcg_out32(s, INSN_DMB_ISH); 1179 } else { 1180 tcg_out32(s, INSN_DMB_MCR); 1181 } 1182} 1183 1184static TCGCond tcg_out_cmp2(TCGContext *s, const TCGArg *args, 1185 const int *const_args) 1186{ 1187 TCGReg al = args[0]; 1188 TCGReg ah = args[1]; 1189 TCGArg bl = args[2]; 1190 TCGArg bh = args[3]; 1191 TCGCond cond = args[4]; 1192 int const_bl = const_args[2]; 1193 int const_bh = const_args[3]; 1194 1195 switch (cond) { 1196 case TCG_COND_EQ: 1197 case TCG_COND_NE: 1198 case TCG_COND_LTU: 1199 case TCG_COND_LEU: 1200 case TCG_COND_GTU: 1201 case TCG_COND_GEU: 1202 /* We perform a conditional comparision. If the high half is 1203 equal, then overwrite the flags with the comparison of the 1204 low half. The resulting flags cover the whole. */ 1205 tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, ah, bh, const_bh); 1206 tcg_out_dat_rI(s, COND_EQ, ARITH_CMP, 0, al, bl, const_bl); 1207 return cond; 1208 1209 case TCG_COND_LT: 1210 case TCG_COND_GE: 1211 /* We perform a double-word subtraction and examine the result. 1212 We do not actually need the result of the subtract, so the 1213 low part "subtract" is a compare. For the high half we have 1214 no choice but to compute into a temporary. */ 1215 tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, al, bl, const_bl); 1216 tcg_out_dat_rI(s, COND_AL, ARITH_SBC | TO_CPSR, 1217 TCG_REG_TMP, ah, bh, const_bh); 1218 return cond; 1219 1220 case TCG_COND_LE: 1221 case TCG_COND_GT: 1222 /* Similar, but with swapped arguments, via reversed subtract. */ 1223 tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR, 1224 TCG_REG_TMP, al, bl, const_bl); 1225 tcg_out_dat_rI(s, COND_AL, ARITH_RSC | TO_CPSR, 1226 TCG_REG_TMP, ah, bh, const_bh); 1227 return tcg_swap_cond(cond); 1228 1229 default: 1230 g_assert_not_reached(); 1231 } 1232} 1233 1234/* 1235 * Note that TCGReg references Q-registers. 1236 * Q-regno = 2 * D-regno, so shift left by 1 whlie inserting. 1237 */ 1238static uint32_t encode_vd(TCGReg rd) 1239{ 1240 tcg_debug_assert(rd >= TCG_REG_Q0); 1241 return (extract32(rd, 3, 1) << 22) | (extract32(rd, 0, 3) << 13); 1242} 1243 1244static uint32_t encode_vn(TCGReg rn) 1245{ 1246 tcg_debug_assert(rn >= TCG_REG_Q0); 1247 return (extract32(rn, 3, 1) << 7) | (extract32(rn, 0, 3) << 17); 1248} 1249 1250static uint32_t encode_vm(TCGReg rm) 1251{ 1252 tcg_debug_assert(rm >= TCG_REG_Q0); 1253 return (extract32(rm, 3, 1) << 5) | (extract32(rm, 0, 3) << 1); 1254} 1255 1256static void tcg_out_vreg2(TCGContext *s, ARMInsn insn, int q, int vece, 1257 TCGReg d, TCGReg m) 1258{ 1259 tcg_out32(s, insn | (vece << 18) | (q << 6) | 1260 encode_vd(d) | encode_vm(m)); 1261} 1262 1263static void tcg_out_vreg3(TCGContext *s, ARMInsn insn, int q, int vece, 1264 TCGReg d, TCGReg n, TCGReg m) 1265{ 1266 tcg_out32(s, insn | (vece << 20) | (q << 6) | 1267 encode_vd(d) | encode_vn(n) | encode_vm(m)); 1268} 1269 1270static void tcg_out_vmovi(TCGContext *s, TCGReg rd, 1271 int q, int op, int cmode, uint8_t imm8) 1272{ 1273 tcg_out32(s, INSN_VMOVI | encode_vd(rd) | (q << 6) | (op << 5) 1274 | (cmode << 8) | extract32(imm8, 0, 4) 1275 | (extract32(imm8, 4, 3) << 16) 1276 | (extract32(imm8, 7, 1) << 24)); 1277} 1278 1279static void tcg_out_vshifti(TCGContext *s, ARMInsn insn, int q, 1280 TCGReg rd, TCGReg rm, int l_imm6) 1281{ 1282 tcg_out32(s, insn | (q << 6) | encode_vd(rd) | encode_vm(rm) | 1283 (extract32(l_imm6, 6, 1) << 7) | 1284 (extract32(l_imm6, 0, 6) << 16)); 1285} 1286 1287static void tcg_out_vldst(TCGContext *s, ARMInsn insn, 1288 TCGReg rd, TCGReg rn, int offset) 1289{ 1290 if (offset != 0) { 1291 if (check_fit_imm(offset) || check_fit_imm(-offset)) { 1292 tcg_out_dat_rIN(s, COND_AL, ARITH_ADD, ARITH_SUB, 1293 TCG_REG_TMP, rn, offset, true); 1294 } else { 1295 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, offset); 1296 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, 1297 TCG_REG_TMP, TCG_REG_TMP, rn, 0); 1298 } 1299 rn = TCG_REG_TMP; 1300 } 1301 tcg_out32(s, insn | (rn << 16) | encode_vd(rd) | 0xf); 1302} 1303 1304#ifdef CONFIG_SOFTMMU 1305/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, 1306 * int mmu_idx, uintptr_t ra) 1307 */ 1308static void * const qemu_ld_helpers[MO_SSIZE + 1] = { 1309 [MO_UB] = helper_ret_ldub_mmu, 1310 [MO_SB] = helper_ret_ldsb_mmu, 1311#if HOST_BIG_ENDIAN 1312 [MO_UW] = helper_be_lduw_mmu, 1313 [MO_UL] = helper_be_ldul_mmu, 1314 [MO_UQ] = helper_be_ldq_mmu, 1315 [MO_SW] = helper_be_ldsw_mmu, 1316 [MO_SL] = helper_be_ldul_mmu, 1317#else 1318 [MO_UW] = helper_le_lduw_mmu, 1319 [MO_UL] = helper_le_ldul_mmu, 1320 [MO_UQ] = helper_le_ldq_mmu, 1321 [MO_SW] = helper_le_ldsw_mmu, 1322 [MO_SL] = helper_le_ldul_mmu, 1323#endif 1324}; 1325 1326/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr, 1327 * uintxx_t val, int mmu_idx, uintptr_t ra) 1328 */ 1329static void * const qemu_st_helpers[MO_SIZE + 1] = { 1330 [MO_8] = helper_ret_stb_mmu, 1331#if HOST_BIG_ENDIAN 1332 [MO_16] = helper_be_stw_mmu, 1333 [MO_32] = helper_be_stl_mmu, 1334 [MO_64] = helper_be_stq_mmu, 1335#else 1336 [MO_16] = helper_le_stw_mmu, 1337 [MO_32] = helper_le_stl_mmu, 1338 [MO_64] = helper_le_stq_mmu, 1339#endif 1340}; 1341 1342/* Helper routines for marshalling helper function arguments into 1343 * the correct registers and stack. 1344 * argreg is where we want to put this argument, arg is the argument itself. 1345 * Return value is the updated argreg ready for the next call. 1346 * Note that argreg 0..3 is real registers, 4+ on stack. 1347 * 1348 * We provide routines for arguments which are: immediate, 32 bit 1349 * value in register, 16 and 8 bit values in register (which must be zero 1350 * extended before use) and 64 bit value in a lo:hi register pair. 1351 */ 1352#define DEFINE_TCG_OUT_ARG(NAME, ARGTYPE, MOV_ARG, EXT_ARG) \ 1353static TCGReg NAME(TCGContext *s, TCGReg argreg, ARGTYPE arg) \ 1354{ \ 1355 if (argreg < 4) { \ 1356 MOV_ARG(s, COND_AL, argreg, arg); \ 1357 } else { \ 1358 int ofs = (argreg - 4) * 4; \ 1359 EXT_ARG; \ 1360 tcg_debug_assert(ofs + 4 <= TCG_STATIC_CALL_ARGS_SIZE); \ 1361 tcg_out_st32_12(s, COND_AL, arg, TCG_REG_CALL_STACK, ofs); \ 1362 } \ 1363 return argreg + 1; \ 1364} 1365 1366DEFINE_TCG_OUT_ARG(tcg_out_arg_imm32, uint32_t, tcg_out_movi32, 1367 (tcg_out_movi32(s, COND_AL, TCG_REG_TMP, arg), arg = TCG_REG_TMP)) 1368DEFINE_TCG_OUT_ARG(tcg_out_arg_reg8, TCGReg, tcg_out_ext8u, 1369 (tcg_out_ext8u(s, COND_AL, TCG_REG_TMP, arg), arg = TCG_REG_TMP)) 1370DEFINE_TCG_OUT_ARG(tcg_out_arg_reg16, TCGReg, tcg_out_ext16u, 1371 (tcg_out_ext16u(s, COND_AL, TCG_REG_TMP, arg), arg = TCG_REG_TMP)) 1372DEFINE_TCG_OUT_ARG(tcg_out_arg_reg32, TCGReg, tcg_out_mov_reg, ) 1373 1374static TCGReg tcg_out_arg_reg64(TCGContext *s, TCGReg argreg, 1375 TCGReg arglo, TCGReg arghi) 1376{ 1377 /* 64 bit arguments must go in even/odd register pairs 1378 * and in 8-aligned stack slots. 1379 */ 1380 if (argreg & 1) { 1381 argreg++; 1382 } 1383 if (argreg >= 4 && (arglo & 1) == 0 && arghi == arglo + 1) { 1384 tcg_out_strd_8(s, COND_AL, arglo, 1385 TCG_REG_CALL_STACK, (argreg - 4) * 4); 1386 return argreg + 2; 1387 } else { 1388 argreg = tcg_out_arg_reg32(s, argreg, arglo); 1389 argreg = tcg_out_arg_reg32(s, argreg, arghi); 1390 return argreg; 1391 } 1392} 1393 1394#define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS) 1395 1396/* We expect to use an 9-bit sign-magnitude negative offset from ENV. */ 1397QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); 1398QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -256); 1399 1400/* These offsets are built into the LDRD below. */ 1401QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0); 1402QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != 4); 1403 1404/* Load and compare a TLB entry, leaving the flags set. Returns the register 1405 containing the addend of the tlb entry. Clobbers R0, R1, R2, TMP. */ 1406 1407static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi, 1408 MemOp opc, int mem_index, bool is_load) 1409{ 1410 int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read) 1411 : offsetof(CPUTLBEntry, addr_write)); 1412 int fast_off = TLB_MASK_TABLE_OFS(mem_index); 1413 unsigned s_mask = (1 << (opc & MO_SIZE)) - 1; 1414 unsigned a_mask = (1 << get_alignment_bits(opc)) - 1; 1415 TCGReg t_addr; 1416 1417 /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {r0,r1}. */ 1418 tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off); 1419 1420 /* Extract the tlb index from the address into R0. */ 1421 tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, addrlo, 1422 SHIFT_IMM_LSR(TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS)); 1423 1424 /* 1425 * Add the tlb_table pointer, creating the CPUTLBEntry address in R1. 1426 * Load the tlb comparator into R2/R3 and the fast path addend into R1. 1427 */ 1428 if (cmp_off == 0) { 1429 if (TARGET_LONG_BITS == 64) { 1430 tcg_out_ldrd_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0); 1431 } else { 1432 tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0); 1433 } 1434 } else { 1435 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, 1436 TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0); 1437 if (TARGET_LONG_BITS == 64) { 1438 tcg_out_ldrd_8(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); 1439 } else { 1440 tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); 1441 } 1442 } 1443 1444 /* Load the tlb addend. */ 1445 tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R1, 1446 offsetof(CPUTLBEntry, addend)); 1447 1448 /* 1449 * Check alignment, check comparators. 1450 * Do this in 2-4 insns. Use MOVW for v7, if possible, 1451 * to reduce the number of sequential conditional instructions. 1452 * Almost all guests have at least 4k pages, which means that we need 1453 * to clear at least 9 bits even for an 8-byte memory, which means it 1454 * isn't worth checking for an immediate operand for BIC. 1455 * 1456 * For unaligned accesses, test the page of the last unit of alignment. 1457 * This leaves the least significant alignment bits unchanged, and of 1458 * course must be zero. 1459 */ 1460 t_addr = addrlo; 1461 if (a_mask < s_mask) { 1462 t_addr = TCG_REG_R0; 1463 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, t_addr, 1464 addrlo, s_mask - a_mask); 1465 } 1466 if (use_armv7_instructions && TARGET_PAGE_BITS <= 16) { 1467 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, ~(TARGET_PAGE_MASK | a_mask)); 1468 tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP, 1469 t_addr, TCG_REG_TMP, 0); 1470 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R2, TCG_REG_TMP, 0); 1471 } else { 1472 if (a_mask) { 1473 tcg_debug_assert(a_mask <= 0xff); 1474 tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask); 1475 } 1476 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, t_addr, 1477 SHIFT_IMM_LSR(TARGET_PAGE_BITS)); 1478 tcg_out_dat_reg(s, (a_mask ? COND_EQ : COND_AL), ARITH_CMP, 1479 0, TCG_REG_R2, TCG_REG_TMP, 1480 SHIFT_IMM_LSL(TARGET_PAGE_BITS)); 1481 } 1482 1483 if (TARGET_LONG_BITS == 64) { 1484 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R3, addrhi, 0); 1485 } 1486 1487 return TCG_REG_R1; 1488} 1489 1490/* Record the context of a call to the out of line helper code for the slow 1491 path for a load or store, so that we can later generate the correct 1492 helper code. */ 1493static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi, 1494 TCGReg datalo, TCGReg datahi, TCGReg addrlo, 1495 TCGReg addrhi, tcg_insn_unit *raddr, 1496 tcg_insn_unit *label_ptr) 1497{ 1498 TCGLabelQemuLdst *label = new_ldst_label(s); 1499 1500 label->is_ld = is_ld; 1501 label->oi = oi; 1502 label->datalo_reg = datalo; 1503 label->datahi_reg = datahi; 1504 label->addrlo_reg = addrlo; 1505 label->addrhi_reg = addrhi; 1506 label->raddr = tcg_splitwx_to_rx(raddr); 1507 label->label_ptr[0] = label_ptr; 1508} 1509 1510static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1511{ 1512 TCGReg argreg, datalo, datahi; 1513 MemOpIdx oi = lb->oi; 1514 MemOp opc = get_memop(oi); 1515 1516 if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1517 return false; 1518 } 1519 1520 argreg = tcg_out_arg_reg32(s, TCG_REG_R0, TCG_AREG0); 1521 if (TARGET_LONG_BITS == 64) { 1522 argreg = tcg_out_arg_reg64(s, argreg, lb->addrlo_reg, lb->addrhi_reg); 1523 } else { 1524 argreg = tcg_out_arg_reg32(s, argreg, lb->addrlo_reg); 1525 } 1526 argreg = tcg_out_arg_imm32(s, argreg, oi); 1527 argreg = tcg_out_arg_reg32(s, argreg, TCG_REG_R14); 1528 1529 /* Use the canonical unsigned helpers and minimize icache usage. */ 1530 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE]); 1531 1532 datalo = lb->datalo_reg; 1533 datahi = lb->datahi_reg; 1534 switch (opc & MO_SSIZE) { 1535 case MO_SB: 1536 tcg_out_ext8s(s, COND_AL, datalo, TCG_REG_R0); 1537 break; 1538 case MO_SW: 1539 tcg_out_ext16s(s, COND_AL, datalo, TCG_REG_R0); 1540 break; 1541 default: 1542 tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_R0); 1543 break; 1544 case MO_UQ: 1545 if (datalo != TCG_REG_R1) { 1546 tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_R0); 1547 tcg_out_mov_reg(s, COND_AL, datahi, TCG_REG_R1); 1548 } else if (datahi != TCG_REG_R0) { 1549 tcg_out_mov_reg(s, COND_AL, datahi, TCG_REG_R1); 1550 tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_R0); 1551 } else { 1552 tcg_out_mov_reg(s, COND_AL, TCG_REG_TMP, TCG_REG_R0); 1553 tcg_out_mov_reg(s, COND_AL, datahi, TCG_REG_R1); 1554 tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_TMP); 1555 } 1556 break; 1557 } 1558 1559 tcg_out_goto(s, COND_AL, lb->raddr); 1560 return true; 1561} 1562 1563static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1564{ 1565 TCGReg argreg, datalo, datahi; 1566 MemOpIdx oi = lb->oi; 1567 MemOp opc = get_memop(oi); 1568 1569 if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1570 return false; 1571 } 1572 1573 argreg = TCG_REG_R0; 1574 argreg = tcg_out_arg_reg32(s, argreg, TCG_AREG0); 1575 if (TARGET_LONG_BITS == 64) { 1576 argreg = tcg_out_arg_reg64(s, argreg, lb->addrlo_reg, lb->addrhi_reg); 1577 } else { 1578 argreg = tcg_out_arg_reg32(s, argreg, lb->addrlo_reg); 1579 } 1580 1581 datalo = lb->datalo_reg; 1582 datahi = lb->datahi_reg; 1583 switch (opc & MO_SIZE) { 1584 case MO_8: 1585 argreg = tcg_out_arg_reg8(s, argreg, datalo); 1586 break; 1587 case MO_16: 1588 argreg = tcg_out_arg_reg16(s, argreg, datalo); 1589 break; 1590 case MO_32: 1591 default: 1592 argreg = tcg_out_arg_reg32(s, argreg, datalo); 1593 break; 1594 case MO_64: 1595 argreg = tcg_out_arg_reg64(s, argreg, datalo, datahi); 1596 break; 1597 } 1598 1599 argreg = tcg_out_arg_imm32(s, argreg, oi); 1600 argreg = tcg_out_arg_reg32(s, argreg, TCG_REG_R14); 1601 1602 /* Tail-call to the helper, which will return to the fast path. */ 1603 tcg_out_goto(s, COND_AL, qemu_st_helpers[opc & MO_SIZE]); 1604 return true; 1605} 1606#else 1607 1608static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addrlo, 1609 TCGReg addrhi, unsigned a_bits) 1610{ 1611 unsigned a_mask = (1 << a_bits) - 1; 1612 TCGLabelQemuLdst *label = new_ldst_label(s); 1613 1614 label->is_ld = is_ld; 1615 label->addrlo_reg = addrlo; 1616 label->addrhi_reg = addrhi; 1617 1618 /* We are expecting a_bits to max out at 7, and can easily support 8. */ 1619 tcg_debug_assert(a_mask <= 0xff); 1620 /* tst addr, #mask */ 1621 tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask); 1622 1623 /* blne slow_path */ 1624 label->label_ptr[0] = s->code_ptr; 1625 tcg_out_bl_imm(s, COND_NE, 0); 1626 1627 label->raddr = tcg_splitwx_to_rx(s->code_ptr); 1628} 1629 1630static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) 1631{ 1632 if (!reloc_pc24(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1633 return false; 1634 } 1635 1636 if (TARGET_LONG_BITS == 64) { 1637 /* 64-bit target address is aligned into R2:R3. */ 1638 if (l->addrhi_reg != TCG_REG_R2) { 1639 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R2, l->addrlo_reg); 1640 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R3, l->addrhi_reg); 1641 } else if (l->addrlo_reg != TCG_REG_R3) { 1642 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R3, l->addrhi_reg); 1643 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R2, l->addrlo_reg); 1644 } else { 1645 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R1, TCG_REG_R2); 1646 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R2, TCG_REG_R3); 1647 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R3, TCG_REG_R1); 1648 } 1649 } else { 1650 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R1, l->addrlo_reg); 1651 } 1652 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_AREG0); 1653 1654 /* 1655 * Tail call to the helper, with the return address back inline, 1656 * just for the clarity of the debugging traceback -- the helper 1657 * cannot return. We have used BLNE to arrive here, so LR is 1658 * already set. 1659 */ 1660 tcg_out_goto(s, COND_AL, (const void *) 1661 (l->is_ld ? helper_unaligned_ld : helper_unaligned_st)); 1662 return true; 1663} 1664 1665static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1666{ 1667 return tcg_out_fail_alignment(s, l); 1668} 1669 1670static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1671{ 1672 return tcg_out_fail_alignment(s, l); 1673} 1674#endif /* SOFTMMU */ 1675 1676static void tcg_out_qemu_ld_index(TCGContext *s, MemOp opc, 1677 TCGReg datalo, TCGReg datahi, 1678 TCGReg addrlo, TCGReg addend, 1679 bool scratch_addend) 1680{ 1681 /* Byte swapping is left to middle-end expansion. */ 1682 tcg_debug_assert((opc & MO_BSWAP) == 0); 1683 1684 switch (opc & MO_SSIZE) { 1685 case MO_UB: 1686 tcg_out_ld8_r(s, COND_AL, datalo, addrlo, addend); 1687 break; 1688 case MO_SB: 1689 tcg_out_ld8s_r(s, COND_AL, datalo, addrlo, addend); 1690 break; 1691 case MO_UW: 1692 tcg_out_ld16u_r(s, COND_AL, datalo, addrlo, addend); 1693 break; 1694 case MO_SW: 1695 tcg_out_ld16s_r(s, COND_AL, datalo, addrlo, addend); 1696 break; 1697 case MO_UL: 1698 tcg_out_ld32_r(s, COND_AL, datalo, addrlo, addend); 1699 break; 1700 case MO_UQ: 1701 /* We used pair allocation for datalo, so already should be aligned. */ 1702 tcg_debug_assert((datalo & 1) == 0); 1703 tcg_debug_assert(datahi == datalo + 1); 1704 /* LDRD requires alignment; double-check that. */ 1705 if (get_alignment_bits(opc) >= MO_64) { 1706 /* 1707 * Rm (the second address op) must not overlap Rt or Rt + 1. 1708 * Since datalo is aligned, we can simplify the test via alignment. 1709 * Flip the two address arguments if that works. 1710 */ 1711 if ((addend & ~1) != datalo) { 1712 tcg_out_ldrd_r(s, COND_AL, datalo, addrlo, addend); 1713 break; 1714 } 1715 if ((addrlo & ~1) != datalo) { 1716 tcg_out_ldrd_r(s, COND_AL, datalo, addend, addrlo); 1717 break; 1718 } 1719 } 1720 if (scratch_addend) { 1721 tcg_out_ld32_rwb(s, COND_AL, datalo, addend, addrlo); 1722 tcg_out_ld32_12(s, COND_AL, datahi, addend, 4); 1723 } else { 1724 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_TMP, 1725 addend, addrlo, SHIFT_IMM_LSL(0)); 1726 tcg_out_ld32_12(s, COND_AL, datalo, TCG_REG_TMP, 0); 1727 tcg_out_ld32_12(s, COND_AL, datahi, TCG_REG_TMP, 4); 1728 } 1729 break; 1730 default: 1731 g_assert_not_reached(); 1732 } 1733} 1734 1735#ifndef CONFIG_SOFTMMU 1736static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo, 1737 TCGReg datahi, TCGReg addrlo) 1738{ 1739 /* Byte swapping is left to middle-end expansion. */ 1740 tcg_debug_assert((opc & MO_BSWAP) == 0); 1741 1742 switch (opc & MO_SSIZE) { 1743 case MO_UB: 1744 tcg_out_ld8_12(s, COND_AL, datalo, addrlo, 0); 1745 break; 1746 case MO_SB: 1747 tcg_out_ld8s_8(s, COND_AL, datalo, addrlo, 0); 1748 break; 1749 case MO_UW: 1750 tcg_out_ld16u_8(s, COND_AL, datalo, addrlo, 0); 1751 break; 1752 case MO_SW: 1753 tcg_out_ld16s_8(s, COND_AL, datalo, addrlo, 0); 1754 break; 1755 case MO_UL: 1756 tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0); 1757 break; 1758 case MO_UQ: 1759 /* We used pair allocation for datalo, so already should be aligned. */ 1760 tcg_debug_assert((datalo & 1) == 0); 1761 tcg_debug_assert(datahi == datalo + 1); 1762 /* LDRD requires alignment; double-check that. */ 1763 if (get_alignment_bits(opc) >= MO_64) { 1764 tcg_out_ldrd_8(s, COND_AL, datalo, addrlo, 0); 1765 } else if (datalo == addrlo) { 1766 tcg_out_ld32_12(s, COND_AL, datahi, addrlo, 4); 1767 tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0); 1768 } else { 1769 tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0); 1770 tcg_out_ld32_12(s, COND_AL, datahi, addrlo, 4); 1771 } 1772 break; 1773 default: 1774 g_assert_not_reached(); 1775 } 1776} 1777#endif 1778 1779static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) 1780{ 1781 TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused)); 1782 MemOpIdx oi; 1783 MemOp opc; 1784#ifdef CONFIG_SOFTMMU 1785 int mem_index; 1786 TCGReg addend; 1787 tcg_insn_unit *label_ptr; 1788#else 1789 unsigned a_bits; 1790#endif 1791 1792 datalo = *args++; 1793 datahi = (is64 ? *args++ : 0); 1794 addrlo = *args++; 1795 addrhi = (TARGET_LONG_BITS == 64 ? *args++ : 0); 1796 oi = *args++; 1797 opc = get_memop(oi); 1798 1799#ifdef CONFIG_SOFTMMU 1800 mem_index = get_mmuidx(oi); 1801 addend = tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 1); 1802 1803 /* This a conditional BL only to load a pointer within this opcode into LR 1804 for the slow path. We will not be using the value for a tail call. */ 1805 label_ptr = s->code_ptr; 1806 tcg_out_bl_imm(s, COND_NE, 0); 1807 1808 tcg_out_qemu_ld_index(s, opc, datalo, datahi, addrlo, addend, true); 1809 1810 add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi, 1811 s->code_ptr, label_ptr); 1812#else /* !CONFIG_SOFTMMU */ 1813 a_bits = get_alignment_bits(opc); 1814 if (a_bits) { 1815 tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); 1816 } 1817 if (guest_base) { 1818 tcg_out_qemu_ld_index(s, opc, datalo, datahi, 1819 addrlo, TCG_REG_GUEST_BASE, false); 1820 } else { 1821 tcg_out_qemu_ld_direct(s, opc, datalo, datahi, addrlo); 1822 } 1823#endif 1824} 1825 1826static void tcg_out_qemu_st_index(TCGContext *s, ARMCond cond, MemOp opc, 1827 TCGReg datalo, TCGReg datahi, 1828 TCGReg addrlo, TCGReg addend, 1829 bool scratch_addend) 1830{ 1831 /* Byte swapping is left to middle-end expansion. */ 1832 tcg_debug_assert((opc & MO_BSWAP) == 0); 1833 1834 switch (opc & MO_SIZE) { 1835 case MO_8: 1836 tcg_out_st8_r(s, cond, datalo, addrlo, addend); 1837 break; 1838 case MO_16: 1839 tcg_out_st16_r(s, cond, datalo, addrlo, addend); 1840 break; 1841 case MO_32: 1842 tcg_out_st32_r(s, cond, datalo, addrlo, addend); 1843 break; 1844 case MO_64: 1845 /* We used pair allocation for datalo, so already should be aligned. */ 1846 tcg_debug_assert((datalo & 1) == 0); 1847 tcg_debug_assert(datahi == datalo + 1); 1848 /* STRD requires alignment; double-check that. */ 1849 if (get_alignment_bits(opc) >= MO_64) { 1850 tcg_out_strd_r(s, cond, datalo, addrlo, addend); 1851 } else if (scratch_addend) { 1852 tcg_out_st32_rwb(s, cond, datalo, addend, addrlo); 1853 tcg_out_st32_12(s, cond, datahi, addend, 4); 1854 } else { 1855 tcg_out_dat_reg(s, cond, ARITH_ADD, TCG_REG_TMP, 1856 addend, addrlo, SHIFT_IMM_LSL(0)); 1857 tcg_out_st32_12(s, cond, datalo, TCG_REG_TMP, 0); 1858 tcg_out_st32_12(s, cond, datahi, TCG_REG_TMP, 4); 1859 } 1860 break; 1861 default: 1862 g_assert_not_reached(); 1863 } 1864} 1865 1866#ifndef CONFIG_SOFTMMU 1867static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo, 1868 TCGReg datahi, TCGReg addrlo) 1869{ 1870 /* Byte swapping is left to middle-end expansion. */ 1871 tcg_debug_assert((opc & MO_BSWAP) == 0); 1872 1873 switch (opc & MO_SIZE) { 1874 case MO_8: 1875 tcg_out_st8_12(s, COND_AL, datalo, addrlo, 0); 1876 break; 1877 case MO_16: 1878 tcg_out_st16_8(s, COND_AL, datalo, addrlo, 0); 1879 break; 1880 case MO_32: 1881 tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0); 1882 break; 1883 case MO_64: 1884 /* We used pair allocation for datalo, so already should be aligned. */ 1885 tcg_debug_assert((datalo & 1) == 0); 1886 tcg_debug_assert(datahi == datalo + 1); 1887 /* STRD requires alignment; double-check that. */ 1888 if (get_alignment_bits(opc) >= MO_64) { 1889 tcg_out_strd_8(s, COND_AL, datalo, addrlo, 0); 1890 } else { 1891 tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0); 1892 tcg_out_st32_12(s, COND_AL, datahi, addrlo, 4); 1893 } 1894 break; 1895 default: 1896 g_assert_not_reached(); 1897 } 1898} 1899#endif 1900 1901static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) 1902{ 1903 TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused)); 1904 MemOpIdx oi; 1905 MemOp opc; 1906#ifdef CONFIG_SOFTMMU 1907 int mem_index; 1908 TCGReg addend; 1909 tcg_insn_unit *label_ptr; 1910#else 1911 unsigned a_bits; 1912#endif 1913 1914 datalo = *args++; 1915 datahi = (is64 ? *args++ : 0); 1916 addrlo = *args++; 1917 addrhi = (TARGET_LONG_BITS == 64 ? *args++ : 0); 1918 oi = *args++; 1919 opc = get_memop(oi); 1920 1921#ifdef CONFIG_SOFTMMU 1922 mem_index = get_mmuidx(oi); 1923 addend = tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 0); 1924 1925 tcg_out_qemu_st_index(s, COND_EQ, opc, datalo, datahi, 1926 addrlo, addend, true); 1927 1928 /* The conditional call must come last, as we're going to return here. */ 1929 label_ptr = s->code_ptr; 1930 tcg_out_bl_imm(s, COND_NE, 0); 1931 1932 add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi, 1933 s->code_ptr, label_ptr); 1934#else /* !CONFIG_SOFTMMU */ 1935 a_bits = get_alignment_bits(opc); 1936 if (a_bits) { 1937 tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits); 1938 } 1939 if (guest_base) { 1940 tcg_out_qemu_st_index(s, COND_AL, opc, datalo, datahi, 1941 addrlo, TCG_REG_GUEST_BASE, false); 1942 } else { 1943 tcg_out_qemu_st_direct(s, opc, datalo, datahi, addrlo); 1944 } 1945#endif 1946} 1947 1948static void tcg_out_epilogue(TCGContext *s); 1949 1950static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg) 1951{ 1952 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, arg); 1953 tcg_out_epilogue(s); 1954} 1955 1956static void tcg_out_goto_tb(TCGContext *s, int which) 1957{ 1958 uintptr_t i_addr; 1959 intptr_t i_disp; 1960 1961 /* Direct branch will be patched by tb_target_set_jmp_target. */ 1962 set_jmp_insn_offset(s, which); 1963 tcg_out32(s, INSN_NOP); 1964 1965 /* When branch is out of range, fall through to indirect. */ 1966 i_addr = get_jmp_target_addr(s, which); 1967 i_disp = tcg_pcrel_diff(s, (void *)i_addr) - 8; 1968 tcg_debug_assert(i_disp < 0); 1969 if (i_disp >= -0xfff) { 1970 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, i_disp); 1971 } else { 1972 /* 1973 * The TB is close, but outside the 12 bits addressable by 1974 * the load. We can extend this to 20 bits with a sub of a 1975 * shifted immediate from pc. 1976 */ 1977 int h = -i_disp; 1978 int l = h & 0xfff; 1979 1980 h = encode_imm_nofail(h - l); 1981 tcg_out_dat_imm(s, COND_AL, ARITH_SUB, TCG_REG_R0, TCG_REG_PC, h); 1982 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_R0, l); 1983 } 1984 set_jmp_reset_offset(s, which); 1985} 1986 1987void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1988 uintptr_t jmp_rx, uintptr_t jmp_rw) 1989{ 1990 uintptr_t addr = tb->jmp_target_addr[n]; 1991 ptrdiff_t offset = addr - (jmp_rx + 8); 1992 tcg_insn_unit insn; 1993 1994 /* Either directly branch, or fall through to indirect branch. */ 1995 if (offset == sextract64(offset, 0, 26)) { 1996 /* B <addr> */ 1997 insn = deposit32((COND_AL << 28) | INSN_B, 0, 24, offset >> 2); 1998 } else { 1999 insn = INSN_NOP; 2000 } 2001 2002 qatomic_set((uint32_t *)jmp_rw, insn); 2003 flush_idcache_range(jmp_rx, jmp_rw, 4); 2004} 2005 2006static void tcg_out_op(TCGContext *s, TCGOpcode opc, 2007 const TCGArg args[TCG_MAX_OP_ARGS], 2008 const int const_args[TCG_MAX_OP_ARGS]) 2009{ 2010 TCGArg a0, a1, a2, a3, a4, a5; 2011 int c; 2012 2013 switch (opc) { 2014 case INDEX_op_goto_ptr: 2015 tcg_out_b_reg(s, COND_AL, args[0]); 2016 break; 2017 case INDEX_op_br: 2018 tcg_out_goto_label(s, COND_AL, arg_label(args[0])); 2019 break; 2020 2021 case INDEX_op_ld8u_i32: 2022 tcg_out_ld8u(s, COND_AL, args[0], args[1], args[2]); 2023 break; 2024 case INDEX_op_ld8s_i32: 2025 tcg_out_ld8s(s, COND_AL, args[0], args[1], args[2]); 2026 break; 2027 case INDEX_op_ld16u_i32: 2028 tcg_out_ld16u(s, COND_AL, args[0], args[1], args[2]); 2029 break; 2030 case INDEX_op_ld16s_i32: 2031 tcg_out_ld16s(s, COND_AL, args[0], args[1], args[2]); 2032 break; 2033 case INDEX_op_ld_i32: 2034 tcg_out_ld32u(s, COND_AL, args[0], args[1], args[2]); 2035 break; 2036 case INDEX_op_st8_i32: 2037 tcg_out_st8(s, COND_AL, args[0], args[1], args[2]); 2038 break; 2039 case INDEX_op_st16_i32: 2040 tcg_out_st16(s, COND_AL, args[0], args[1], args[2]); 2041 break; 2042 case INDEX_op_st_i32: 2043 tcg_out_st32(s, COND_AL, args[0], args[1], args[2]); 2044 break; 2045 2046 case INDEX_op_movcond_i32: 2047 /* Constraints mean that v2 is always in the same register as dest, 2048 * so we only need to do "if condition passed, move v1 to dest". 2049 */ 2050 tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, 2051 args[1], args[2], const_args[2]); 2052 tcg_out_dat_rIK(s, tcg_cond_to_arm_cond[args[5]], ARITH_MOV, 2053 ARITH_MVN, args[0], 0, args[3], const_args[3]); 2054 break; 2055 case INDEX_op_add_i32: 2056 tcg_out_dat_rIN(s, COND_AL, ARITH_ADD, ARITH_SUB, 2057 args[0], args[1], args[2], const_args[2]); 2058 break; 2059 case INDEX_op_sub_i32: 2060 if (const_args[1]) { 2061 if (const_args[2]) { 2062 tcg_out_movi32(s, COND_AL, args[0], args[1] - args[2]); 2063 } else { 2064 tcg_out_dat_rI(s, COND_AL, ARITH_RSB, 2065 args[0], args[2], args[1], 1); 2066 } 2067 } else { 2068 tcg_out_dat_rIN(s, COND_AL, ARITH_SUB, ARITH_ADD, 2069 args[0], args[1], args[2], const_args[2]); 2070 } 2071 break; 2072 case INDEX_op_and_i32: 2073 tcg_out_dat_rIK(s, COND_AL, ARITH_AND, ARITH_BIC, 2074 args[0], args[1], args[2], const_args[2]); 2075 break; 2076 case INDEX_op_andc_i32: 2077 tcg_out_dat_rIK(s, COND_AL, ARITH_BIC, ARITH_AND, 2078 args[0], args[1], args[2], const_args[2]); 2079 break; 2080 case INDEX_op_or_i32: 2081 c = ARITH_ORR; 2082 goto gen_arith; 2083 case INDEX_op_xor_i32: 2084 c = ARITH_EOR; 2085 /* Fall through. */ 2086 gen_arith: 2087 tcg_out_dat_rI(s, COND_AL, c, args[0], args[1], args[2], const_args[2]); 2088 break; 2089 case INDEX_op_add2_i32: 2090 a0 = args[0], a1 = args[1], a2 = args[2]; 2091 a3 = args[3], a4 = args[4], a5 = args[5]; 2092 if (a0 == a3 || (a0 == a5 && !const_args[5])) { 2093 a0 = TCG_REG_TMP; 2094 } 2095 tcg_out_dat_rIN(s, COND_AL, ARITH_ADD | TO_CPSR, ARITH_SUB | TO_CPSR, 2096 a0, a2, a4, const_args[4]); 2097 tcg_out_dat_rIK(s, COND_AL, ARITH_ADC, ARITH_SBC, 2098 a1, a3, a5, const_args[5]); 2099 tcg_out_mov_reg(s, COND_AL, args[0], a0); 2100 break; 2101 case INDEX_op_sub2_i32: 2102 a0 = args[0], a1 = args[1], a2 = args[2]; 2103 a3 = args[3], a4 = args[4], a5 = args[5]; 2104 if ((a0 == a3 && !const_args[3]) || (a0 == a5 && !const_args[5])) { 2105 a0 = TCG_REG_TMP; 2106 } 2107 if (const_args[2]) { 2108 if (const_args[4]) { 2109 tcg_out_movi32(s, COND_AL, a0, a4); 2110 a4 = a0; 2111 } 2112 tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR, a0, a4, a2, 1); 2113 } else { 2114 tcg_out_dat_rIN(s, COND_AL, ARITH_SUB | TO_CPSR, 2115 ARITH_ADD | TO_CPSR, a0, a2, a4, const_args[4]); 2116 } 2117 if (const_args[3]) { 2118 if (const_args[5]) { 2119 tcg_out_movi32(s, COND_AL, a1, a5); 2120 a5 = a1; 2121 } 2122 tcg_out_dat_rI(s, COND_AL, ARITH_RSC, a1, a5, a3, 1); 2123 } else { 2124 tcg_out_dat_rIK(s, COND_AL, ARITH_SBC, ARITH_ADC, 2125 a1, a3, a5, const_args[5]); 2126 } 2127 tcg_out_mov_reg(s, COND_AL, args[0], a0); 2128 break; 2129 case INDEX_op_neg_i32: 2130 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, args[0], args[1], 0); 2131 break; 2132 case INDEX_op_not_i32: 2133 tcg_out_dat_reg(s, COND_AL, 2134 ARITH_MVN, args[0], 0, args[1], SHIFT_IMM_LSL(0)); 2135 break; 2136 case INDEX_op_mul_i32: 2137 tcg_out_mul32(s, COND_AL, args[0], args[1], args[2]); 2138 break; 2139 case INDEX_op_mulu2_i32: 2140 tcg_out_umull32(s, COND_AL, args[0], args[1], args[2], args[3]); 2141 break; 2142 case INDEX_op_muls2_i32: 2143 tcg_out_smull32(s, COND_AL, args[0], args[1], args[2], args[3]); 2144 break; 2145 /* XXX: Perhaps args[2] & 0x1f is wrong */ 2146 case INDEX_op_shl_i32: 2147 c = const_args[2] ? 2148 SHIFT_IMM_LSL(args[2] & 0x1f) : SHIFT_REG_LSL(args[2]); 2149 goto gen_shift32; 2150 case INDEX_op_shr_i32: 2151 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_LSR(args[2] & 0x1f) : 2152 SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args[2]); 2153 goto gen_shift32; 2154 case INDEX_op_sar_i32: 2155 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ASR(args[2] & 0x1f) : 2156 SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args[2]); 2157 goto gen_shift32; 2158 case INDEX_op_rotr_i32: 2159 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ROR(args[2] & 0x1f) : 2160 SHIFT_IMM_LSL(0) : SHIFT_REG_ROR(args[2]); 2161 /* Fall through. */ 2162 gen_shift32: 2163 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], c); 2164 break; 2165 2166 case INDEX_op_rotl_i32: 2167 if (const_args[2]) { 2168 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], 2169 ((0x20 - args[2]) & 0x1f) ? 2170 SHIFT_IMM_ROR((0x20 - args[2]) & 0x1f) : 2171 SHIFT_IMM_LSL(0)); 2172 } else { 2173 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, TCG_REG_TMP, args[2], 0x20); 2174 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], 2175 SHIFT_REG_ROR(TCG_REG_TMP)); 2176 } 2177 break; 2178 2179 case INDEX_op_ctz_i32: 2180 tcg_out_dat_reg(s, COND_AL, INSN_RBIT, TCG_REG_TMP, 0, args[1], 0); 2181 a1 = TCG_REG_TMP; 2182 goto do_clz; 2183 2184 case INDEX_op_clz_i32: 2185 a1 = args[1]; 2186 do_clz: 2187 a0 = args[0]; 2188 a2 = args[2]; 2189 c = const_args[2]; 2190 if (c && a2 == 32) { 2191 tcg_out_dat_reg(s, COND_AL, INSN_CLZ, a0, 0, a1, 0); 2192 break; 2193 } 2194 tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0, a1, 0); 2195 tcg_out_dat_reg(s, COND_NE, INSN_CLZ, a0, 0, a1, 0); 2196 if (c || a0 != a2) { 2197 tcg_out_dat_rIK(s, COND_EQ, ARITH_MOV, ARITH_MVN, a0, 0, a2, c); 2198 } 2199 break; 2200 2201 case INDEX_op_brcond_i32: 2202 tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, 2203 args[0], args[1], const_args[1]); 2204 tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[2]], 2205 arg_label(args[3])); 2206 break; 2207 case INDEX_op_setcond_i32: 2208 tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, 2209 args[1], args[2], const_args[2]); 2210 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[3]], 2211 ARITH_MOV, args[0], 0, 1); 2212 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[3])], 2213 ARITH_MOV, args[0], 0, 0); 2214 break; 2215 2216 case INDEX_op_brcond2_i32: 2217 c = tcg_out_cmp2(s, args, const_args); 2218 tcg_out_goto_label(s, tcg_cond_to_arm_cond[c], arg_label(args[5])); 2219 break; 2220 case INDEX_op_setcond2_i32: 2221 c = tcg_out_cmp2(s, args + 1, const_args + 1); 2222 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[c], ARITH_MOV, args[0], 0, 1); 2223 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(c)], 2224 ARITH_MOV, args[0], 0, 0); 2225 break; 2226 2227 case INDEX_op_qemu_ld_i32: 2228 tcg_out_qemu_ld(s, args, 0); 2229 break; 2230 case INDEX_op_qemu_ld_i64: 2231 tcg_out_qemu_ld(s, args, 1); 2232 break; 2233 case INDEX_op_qemu_st_i32: 2234 tcg_out_qemu_st(s, args, 0); 2235 break; 2236 case INDEX_op_qemu_st_i64: 2237 tcg_out_qemu_st(s, args, 1); 2238 break; 2239 2240 case INDEX_op_bswap16_i32: 2241 tcg_out_bswap16(s, COND_AL, args[0], args[1], args[2]); 2242 break; 2243 case INDEX_op_bswap32_i32: 2244 tcg_out_bswap32(s, COND_AL, args[0], args[1]); 2245 break; 2246 2247 case INDEX_op_ext8s_i32: 2248 tcg_out_ext8s(s, COND_AL, args[0], args[1]); 2249 break; 2250 case INDEX_op_ext16s_i32: 2251 tcg_out_ext16s(s, COND_AL, args[0], args[1]); 2252 break; 2253 case INDEX_op_ext16u_i32: 2254 tcg_out_ext16u(s, COND_AL, args[0], args[1]); 2255 break; 2256 2257 case INDEX_op_deposit_i32: 2258 tcg_out_deposit(s, COND_AL, args[0], args[2], 2259 args[3], args[4], const_args[2]); 2260 break; 2261 case INDEX_op_extract_i32: 2262 tcg_out_extract(s, COND_AL, args[0], args[1], args[2], args[3]); 2263 break; 2264 case INDEX_op_sextract_i32: 2265 tcg_out_sextract(s, COND_AL, args[0], args[1], args[2], args[3]); 2266 break; 2267 case INDEX_op_extract2_i32: 2268 /* ??? These optimization vs zero should be generic. */ 2269 /* ??? But we can't substitute 2 for 1 in the opcode stream yet. */ 2270 if (const_args[1]) { 2271 if (const_args[2]) { 2272 tcg_out_movi(s, TCG_TYPE_REG, args[0], 0); 2273 } else { 2274 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, 2275 args[2], SHIFT_IMM_LSL(32 - args[3])); 2276 } 2277 } else if (const_args[2]) { 2278 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, 2279 args[1], SHIFT_IMM_LSR(args[3])); 2280 } else { 2281 /* We can do extract2 in 2 insns, vs the 3 required otherwise. */ 2282 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, 2283 args[2], SHIFT_IMM_LSL(32 - args[3])); 2284 tcg_out_dat_reg(s, COND_AL, ARITH_ORR, args[0], TCG_REG_TMP, 2285 args[1], SHIFT_IMM_LSR(args[3])); 2286 } 2287 break; 2288 2289 case INDEX_op_div_i32: 2290 tcg_out_sdiv(s, COND_AL, args[0], args[1], args[2]); 2291 break; 2292 case INDEX_op_divu_i32: 2293 tcg_out_udiv(s, COND_AL, args[0], args[1], args[2]); 2294 break; 2295 2296 case INDEX_op_mb: 2297 tcg_out_mb(s, args[0]); 2298 break; 2299 2300 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ 2301 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2302 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2303 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2304 default: 2305 tcg_abort(); 2306 } 2307} 2308 2309static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) 2310{ 2311 switch (op) { 2312 case INDEX_op_goto_ptr: 2313 return C_O0_I1(r); 2314 2315 case INDEX_op_ld8u_i32: 2316 case INDEX_op_ld8s_i32: 2317 case INDEX_op_ld16u_i32: 2318 case INDEX_op_ld16s_i32: 2319 case INDEX_op_ld_i32: 2320 case INDEX_op_neg_i32: 2321 case INDEX_op_not_i32: 2322 case INDEX_op_bswap16_i32: 2323 case INDEX_op_bswap32_i32: 2324 case INDEX_op_ext8s_i32: 2325 case INDEX_op_ext16s_i32: 2326 case INDEX_op_ext16u_i32: 2327 case INDEX_op_extract_i32: 2328 case INDEX_op_sextract_i32: 2329 return C_O1_I1(r, r); 2330 2331 case INDEX_op_st8_i32: 2332 case INDEX_op_st16_i32: 2333 case INDEX_op_st_i32: 2334 return C_O0_I2(r, r); 2335 2336 case INDEX_op_add_i32: 2337 case INDEX_op_sub_i32: 2338 case INDEX_op_setcond_i32: 2339 return C_O1_I2(r, r, rIN); 2340 2341 case INDEX_op_and_i32: 2342 case INDEX_op_andc_i32: 2343 case INDEX_op_clz_i32: 2344 case INDEX_op_ctz_i32: 2345 return C_O1_I2(r, r, rIK); 2346 2347 case INDEX_op_mul_i32: 2348 case INDEX_op_div_i32: 2349 case INDEX_op_divu_i32: 2350 return C_O1_I2(r, r, r); 2351 2352 case INDEX_op_mulu2_i32: 2353 case INDEX_op_muls2_i32: 2354 return C_O2_I2(r, r, r, r); 2355 2356 case INDEX_op_or_i32: 2357 case INDEX_op_xor_i32: 2358 return C_O1_I2(r, r, rI); 2359 2360 case INDEX_op_shl_i32: 2361 case INDEX_op_shr_i32: 2362 case INDEX_op_sar_i32: 2363 case INDEX_op_rotl_i32: 2364 case INDEX_op_rotr_i32: 2365 return C_O1_I2(r, r, ri); 2366 2367 case INDEX_op_brcond_i32: 2368 return C_O0_I2(r, rIN); 2369 case INDEX_op_deposit_i32: 2370 return C_O1_I2(r, 0, rZ); 2371 case INDEX_op_extract2_i32: 2372 return C_O1_I2(r, rZ, rZ); 2373 case INDEX_op_movcond_i32: 2374 return C_O1_I4(r, r, rIN, rIK, 0); 2375 case INDEX_op_add2_i32: 2376 return C_O2_I4(r, r, r, r, rIN, rIK); 2377 case INDEX_op_sub2_i32: 2378 return C_O2_I4(r, r, rI, rI, rIN, rIK); 2379 case INDEX_op_brcond2_i32: 2380 return C_O0_I4(r, r, rI, rI); 2381 case INDEX_op_setcond2_i32: 2382 return C_O1_I4(r, r, r, rI, rI); 2383 2384 case INDEX_op_qemu_ld_i32: 2385 return TARGET_LONG_BITS == 32 ? C_O1_I1(r, l) : C_O1_I2(r, l, l); 2386 case INDEX_op_qemu_ld_i64: 2387 return TARGET_LONG_BITS == 32 ? C_O2_I1(e, p, l) : C_O2_I2(e, p, l, l); 2388 case INDEX_op_qemu_st_i32: 2389 return TARGET_LONG_BITS == 32 ? C_O0_I2(s, s) : C_O0_I3(s, s, s); 2390 case INDEX_op_qemu_st_i64: 2391 return TARGET_LONG_BITS == 32 ? C_O0_I3(S, p, s) : C_O0_I4(S, p, s, s); 2392 2393 case INDEX_op_st_vec: 2394 return C_O0_I2(w, r); 2395 case INDEX_op_ld_vec: 2396 case INDEX_op_dupm_vec: 2397 return C_O1_I1(w, r); 2398 case INDEX_op_dup_vec: 2399 return C_O1_I1(w, wr); 2400 case INDEX_op_abs_vec: 2401 case INDEX_op_neg_vec: 2402 case INDEX_op_not_vec: 2403 case INDEX_op_shli_vec: 2404 case INDEX_op_shri_vec: 2405 case INDEX_op_sari_vec: 2406 return C_O1_I1(w, w); 2407 case INDEX_op_dup2_vec: 2408 case INDEX_op_add_vec: 2409 case INDEX_op_mul_vec: 2410 case INDEX_op_smax_vec: 2411 case INDEX_op_smin_vec: 2412 case INDEX_op_ssadd_vec: 2413 case INDEX_op_sssub_vec: 2414 case INDEX_op_sub_vec: 2415 case INDEX_op_umax_vec: 2416 case INDEX_op_umin_vec: 2417 case INDEX_op_usadd_vec: 2418 case INDEX_op_ussub_vec: 2419 case INDEX_op_xor_vec: 2420 case INDEX_op_arm_sshl_vec: 2421 case INDEX_op_arm_ushl_vec: 2422 return C_O1_I2(w, w, w); 2423 case INDEX_op_arm_sli_vec: 2424 return C_O1_I2(w, 0, w); 2425 case INDEX_op_or_vec: 2426 case INDEX_op_andc_vec: 2427 return C_O1_I2(w, w, wO); 2428 case INDEX_op_and_vec: 2429 case INDEX_op_orc_vec: 2430 return C_O1_I2(w, w, wV); 2431 case INDEX_op_cmp_vec: 2432 return C_O1_I2(w, w, wZ); 2433 case INDEX_op_bitsel_vec: 2434 return C_O1_I3(w, w, w, w); 2435 default: 2436 g_assert_not_reached(); 2437 } 2438} 2439 2440static void tcg_target_init(TCGContext *s) 2441{ 2442 /* 2443 * Only probe for the platform and capabilities if we haven't already 2444 * determined maximum values at compile time. 2445 */ 2446#if !defined(use_idiv_instructions) || !defined(use_neon_instructions) 2447 { 2448 unsigned long hwcap = qemu_getauxval(AT_HWCAP); 2449#ifndef use_idiv_instructions 2450 use_idiv_instructions = (hwcap & HWCAP_ARM_IDIVA) != 0; 2451#endif 2452#ifndef use_neon_instructions 2453 use_neon_instructions = (hwcap & HWCAP_ARM_NEON) != 0; 2454#endif 2455 } 2456#endif 2457 2458 if (__ARM_ARCH < 7) { 2459 const char *pl = (const char *)qemu_getauxval(AT_PLATFORM); 2460 if (pl != NULL && pl[0] == 'v' && pl[1] >= '4' && pl[1] <= '9') { 2461 arm_arch = pl[1] - '0'; 2462 } 2463 2464 if (arm_arch < 6) { 2465 error_report("TCG: ARMv%d is unsupported; exiting", arm_arch); 2466 exit(EXIT_FAILURE); 2467 } 2468 } 2469 2470 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS; 2471 2472 tcg_target_call_clobber_regs = 0; 2473 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); 2474 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1); 2475 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2); 2476 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3); 2477 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12); 2478 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14); 2479 2480 if (use_neon_instructions) { 2481 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS; 2482 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS; 2483 2484 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q0); 2485 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q1); 2486 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q2); 2487 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q3); 2488 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q8); 2489 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q9); 2490 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q10); 2491 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q11); 2492 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q12); 2493 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q13); 2494 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q14); 2495 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q15); 2496 } 2497 2498 s->reserved_regs = 0; 2499 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); 2500 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP); 2501 tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC); 2502 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP); 2503} 2504 2505static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 2506 TCGReg arg1, intptr_t arg2) 2507{ 2508 switch (type) { 2509 case TCG_TYPE_I32: 2510 tcg_out_ld32u(s, COND_AL, arg, arg1, arg2); 2511 return; 2512 case TCG_TYPE_V64: 2513 /* regs 1; size 8; align 8 */ 2514 tcg_out_vldst(s, INSN_VLD1 | 0x7d0, arg, arg1, arg2); 2515 return; 2516 case TCG_TYPE_V128: 2517 /* 2518 * We have only 8-byte alignment for the stack per the ABI. 2519 * Rather than dynamically re-align the stack, it's easier 2520 * to simply not request alignment beyond that. So: 2521 * regs 2; size 8; align 8 2522 */ 2523 tcg_out_vldst(s, INSN_VLD1 | 0xad0, arg, arg1, arg2); 2524 return; 2525 default: 2526 g_assert_not_reached(); 2527 } 2528} 2529 2530static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 2531 TCGReg arg1, intptr_t arg2) 2532{ 2533 switch (type) { 2534 case TCG_TYPE_I32: 2535 tcg_out_st32(s, COND_AL, arg, arg1, arg2); 2536 return; 2537 case TCG_TYPE_V64: 2538 /* regs 1; size 8; align 8 */ 2539 tcg_out_vldst(s, INSN_VST1 | 0x7d0, arg, arg1, arg2); 2540 return; 2541 case TCG_TYPE_V128: 2542 /* See tcg_out_ld re alignment: regs 2; size 8; align 8 */ 2543 tcg_out_vldst(s, INSN_VST1 | 0xad0, arg, arg1, arg2); 2544 return; 2545 default: 2546 g_assert_not_reached(); 2547 } 2548} 2549 2550static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 2551 TCGReg base, intptr_t ofs) 2552{ 2553 return false; 2554} 2555 2556static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 2557{ 2558 if (ret == arg) { 2559 return true; 2560 } 2561 switch (type) { 2562 case TCG_TYPE_I32: 2563 if (ret < TCG_REG_Q0 && arg < TCG_REG_Q0) { 2564 tcg_out_mov_reg(s, COND_AL, ret, arg); 2565 return true; 2566 } 2567 return false; 2568 2569 case TCG_TYPE_V64: 2570 case TCG_TYPE_V128: 2571 /* "VMOV D,N" is an alias for "VORR D,N,N". */ 2572 tcg_out_vreg3(s, INSN_VORR, type - TCG_TYPE_V64, 0, ret, arg, arg); 2573 return true; 2574 2575 default: 2576 g_assert_not_reached(); 2577 } 2578} 2579 2580static void tcg_out_movi(TCGContext *s, TCGType type, 2581 TCGReg ret, tcg_target_long arg) 2582{ 2583 tcg_debug_assert(type == TCG_TYPE_I32); 2584 tcg_debug_assert(ret < TCG_REG_Q0); 2585 tcg_out_movi32(s, COND_AL, ret, arg); 2586} 2587 2588static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 2589 tcg_target_long imm) 2590{ 2591 int enc, opc = ARITH_ADD; 2592 2593 /* All of the easiest immediates to encode are positive. */ 2594 if (imm < 0) { 2595 imm = -imm; 2596 opc = ARITH_SUB; 2597 } 2598 enc = encode_imm(imm); 2599 if (enc >= 0) { 2600 tcg_out_dat_imm(s, COND_AL, opc, rd, rs, enc); 2601 } else { 2602 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, imm); 2603 tcg_out_dat_reg(s, COND_AL, opc, rd, rs, 2604 TCG_REG_TMP, SHIFT_IMM_LSL(0)); 2605 } 2606} 2607 2608/* Type is always V128, with I64 elements. */ 2609static void tcg_out_dup2_vec(TCGContext *s, TCGReg rd, TCGReg rl, TCGReg rh) 2610{ 2611 /* Move high element into place first. */ 2612 /* VMOV Dd+1, Ds */ 2613 tcg_out_vreg3(s, INSN_VORR | (1 << 12), 0, 0, rd, rh, rh); 2614 /* Move low element into place; tcg_out_mov will check for nop. */ 2615 tcg_out_mov(s, TCG_TYPE_V64, rd, rl); 2616} 2617 2618static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 2619 TCGReg rd, TCGReg rs) 2620{ 2621 int q = type - TCG_TYPE_V64; 2622 2623 if (vece == MO_64) { 2624 if (type == TCG_TYPE_V128) { 2625 tcg_out_dup2_vec(s, rd, rs, rs); 2626 } else { 2627 tcg_out_mov(s, TCG_TYPE_V64, rd, rs); 2628 } 2629 } else if (rs < TCG_REG_Q0) { 2630 int b = (vece == MO_8); 2631 int e = (vece == MO_16); 2632 tcg_out32(s, INSN_VDUP_G | (b << 22) | (q << 21) | (e << 5) | 2633 encode_vn(rd) | (rs << 12)); 2634 } else { 2635 int imm4 = 1 << vece; 2636 tcg_out32(s, INSN_VDUP_S | (imm4 << 16) | (q << 6) | 2637 encode_vd(rd) | encode_vm(rs)); 2638 } 2639 return true; 2640} 2641 2642static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 2643 TCGReg rd, TCGReg base, intptr_t offset) 2644{ 2645 if (vece == MO_64) { 2646 tcg_out_ld(s, TCG_TYPE_V64, rd, base, offset); 2647 if (type == TCG_TYPE_V128) { 2648 tcg_out_dup2_vec(s, rd, rd, rd); 2649 } 2650 } else { 2651 int q = type - TCG_TYPE_V64; 2652 tcg_out_vldst(s, INSN_VLD1R | (vece << 6) | (q << 5), 2653 rd, base, offset); 2654 } 2655 return true; 2656} 2657 2658static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 2659 TCGReg rd, int64_t v64) 2660{ 2661 int q = type - TCG_TYPE_V64; 2662 int cmode, imm8, i; 2663 2664 /* Test all bytes equal first. */ 2665 if (vece == MO_8) { 2666 tcg_out_vmovi(s, rd, q, 0, 0xe, v64); 2667 return; 2668 } 2669 2670 /* 2671 * Test all bytes 0x00 or 0xff second. This can match cases that 2672 * might otherwise take 2 or 3 insns for MO_16 or MO_32 below. 2673 */ 2674 for (i = imm8 = 0; i < 8; i++) { 2675 uint8_t byte = v64 >> (i * 8); 2676 if (byte == 0xff) { 2677 imm8 |= 1 << i; 2678 } else if (byte != 0) { 2679 goto fail_bytes; 2680 } 2681 } 2682 tcg_out_vmovi(s, rd, q, 1, 0xe, imm8); 2683 return; 2684 fail_bytes: 2685 2686 /* 2687 * Tests for various replications. For each element width, if we 2688 * cannot find an expansion there's no point checking a larger 2689 * width because we already know by replication it cannot match. 2690 */ 2691 if (vece == MO_16) { 2692 uint16_t v16 = v64; 2693 2694 if (is_shimm16(v16, &cmode, &imm8)) { 2695 tcg_out_vmovi(s, rd, q, 0, cmode, imm8); 2696 return; 2697 } 2698 if (is_shimm16(~v16, &cmode, &imm8)) { 2699 tcg_out_vmovi(s, rd, q, 1, cmode, imm8); 2700 return; 2701 } 2702 2703 /* 2704 * Otherwise, all remaining constants can be loaded in two insns: 2705 * rd = v16 & 0xff, rd |= v16 & 0xff00. 2706 */ 2707 tcg_out_vmovi(s, rd, q, 0, 0x8, v16 & 0xff); 2708 tcg_out_vmovi(s, rd, q, 0, 0xb, v16 >> 8); /* VORRI */ 2709 return; 2710 } 2711 2712 if (vece == MO_32) { 2713 uint32_t v32 = v64; 2714 2715 if (is_shimm32(v32, &cmode, &imm8) || 2716 is_soimm32(v32, &cmode, &imm8)) { 2717 tcg_out_vmovi(s, rd, q, 0, cmode, imm8); 2718 return; 2719 } 2720 if (is_shimm32(~v32, &cmode, &imm8) || 2721 is_soimm32(~v32, &cmode, &imm8)) { 2722 tcg_out_vmovi(s, rd, q, 1, cmode, imm8); 2723 return; 2724 } 2725 2726 /* 2727 * Restrict the set of constants to those we can load with 2728 * two instructions. Others we load from the pool. 2729 */ 2730 i = is_shimm32_pair(v32, &cmode, &imm8); 2731 if (i) { 2732 tcg_out_vmovi(s, rd, q, 0, cmode, imm8); 2733 tcg_out_vmovi(s, rd, q, 0, i | 1, extract32(v32, i * 4, 8)); 2734 return; 2735 } 2736 i = is_shimm32_pair(~v32, &cmode, &imm8); 2737 if (i) { 2738 tcg_out_vmovi(s, rd, q, 1, cmode, imm8); 2739 tcg_out_vmovi(s, rd, q, 1, i | 1, extract32(~v32, i * 4, 8)); 2740 return; 2741 } 2742 } 2743 2744 /* 2745 * As a last resort, load from the constant pool. 2746 */ 2747 if (!q || vece == MO_64) { 2748 new_pool_l2(s, R_ARM_PC11, s->code_ptr, 0, v64, v64 >> 32); 2749 /* VLDR Dd, [pc + offset] */ 2750 tcg_out32(s, INSN_VLDR_D | encode_vd(rd) | (0xf << 16)); 2751 if (q) { 2752 tcg_out_dup2_vec(s, rd, rd, rd); 2753 } 2754 } else { 2755 new_pool_label(s, (uint32_t)v64, R_ARM_PC8, s->code_ptr, 0); 2756 /* add tmp, pc, offset */ 2757 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_TMP, TCG_REG_PC, 0); 2758 tcg_out_dupm_vec(s, type, MO_32, rd, TCG_REG_TMP, 0); 2759 } 2760} 2761 2762static const ARMInsn vec_cmp_insn[16] = { 2763 [TCG_COND_EQ] = INSN_VCEQ, 2764 [TCG_COND_GT] = INSN_VCGT, 2765 [TCG_COND_GE] = INSN_VCGE, 2766 [TCG_COND_GTU] = INSN_VCGT_U, 2767 [TCG_COND_GEU] = INSN_VCGE_U, 2768}; 2769 2770static const ARMInsn vec_cmp0_insn[16] = { 2771 [TCG_COND_EQ] = INSN_VCEQ0, 2772 [TCG_COND_GT] = INSN_VCGT0, 2773 [TCG_COND_GE] = INSN_VCGE0, 2774 [TCG_COND_LT] = INSN_VCLT0, 2775 [TCG_COND_LE] = INSN_VCLE0, 2776}; 2777 2778static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 2779 unsigned vecl, unsigned vece, 2780 const TCGArg args[TCG_MAX_OP_ARGS], 2781 const int const_args[TCG_MAX_OP_ARGS]) 2782{ 2783 TCGType type = vecl + TCG_TYPE_V64; 2784 unsigned q = vecl; 2785 TCGArg a0, a1, a2, a3; 2786 int cmode, imm8; 2787 2788 a0 = args[0]; 2789 a1 = args[1]; 2790 a2 = args[2]; 2791 2792 switch (opc) { 2793 case INDEX_op_ld_vec: 2794 tcg_out_ld(s, type, a0, a1, a2); 2795 return; 2796 case INDEX_op_st_vec: 2797 tcg_out_st(s, type, a0, a1, a2); 2798 return; 2799 case INDEX_op_dupm_vec: 2800 tcg_out_dupm_vec(s, type, vece, a0, a1, a2); 2801 return; 2802 case INDEX_op_dup2_vec: 2803 tcg_out_dup2_vec(s, a0, a1, a2); 2804 return; 2805 case INDEX_op_abs_vec: 2806 tcg_out_vreg2(s, INSN_VABS, q, vece, a0, a1); 2807 return; 2808 case INDEX_op_neg_vec: 2809 tcg_out_vreg2(s, INSN_VNEG, q, vece, a0, a1); 2810 return; 2811 case INDEX_op_not_vec: 2812 tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a1); 2813 return; 2814 case INDEX_op_add_vec: 2815 tcg_out_vreg3(s, INSN_VADD, q, vece, a0, a1, a2); 2816 return; 2817 case INDEX_op_mul_vec: 2818 tcg_out_vreg3(s, INSN_VMUL, q, vece, a0, a1, a2); 2819 return; 2820 case INDEX_op_smax_vec: 2821 tcg_out_vreg3(s, INSN_VMAX, q, vece, a0, a1, a2); 2822 return; 2823 case INDEX_op_smin_vec: 2824 tcg_out_vreg3(s, INSN_VMIN, q, vece, a0, a1, a2); 2825 return; 2826 case INDEX_op_sub_vec: 2827 tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2); 2828 return; 2829 case INDEX_op_ssadd_vec: 2830 tcg_out_vreg3(s, INSN_VQADD, q, vece, a0, a1, a2); 2831 return; 2832 case INDEX_op_sssub_vec: 2833 tcg_out_vreg3(s, INSN_VQSUB, q, vece, a0, a1, a2); 2834 return; 2835 case INDEX_op_umax_vec: 2836 tcg_out_vreg3(s, INSN_VMAX_U, q, vece, a0, a1, a2); 2837 return; 2838 case INDEX_op_umin_vec: 2839 tcg_out_vreg3(s, INSN_VMIN_U, q, vece, a0, a1, a2); 2840 return; 2841 case INDEX_op_usadd_vec: 2842 tcg_out_vreg3(s, INSN_VQADD_U, q, vece, a0, a1, a2); 2843 return; 2844 case INDEX_op_ussub_vec: 2845 tcg_out_vreg3(s, INSN_VQSUB_U, q, vece, a0, a1, a2); 2846 return; 2847 case INDEX_op_xor_vec: 2848 tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2); 2849 return; 2850 case INDEX_op_arm_sshl_vec: 2851 /* 2852 * Note that Vm is the data and Vn is the shift count, 2853 * therefore the arguments appear reversed. 2854 */ 2855 tcg_out_vreg3(s, INSN_VSHL_S, q, vece, a0, a2, a1); 2856 return; 2857 case INDEX_op_arm_ushl_vec: 2858 /* See above. */ 2859 tcg_out_vreg3(s, INSN_VSHL_U, q, vece, a0, a2, a1); 2860 return; 2861 case INDEX_op_shli_vec: 2862 tcg_out_vshifti(s, INSN_VSHLI, q, a0, a1, a2 + (8 << vece)); 2863 return; 2864 case INDEX_op_shri_vec: 2865 tcg_out_vshifti(s, INSN_VSHRI, q, a0, a1, (16 << vece) - a2); 2866 return; 2867 case INDEX_op_sari_vec: 2868 tcg_out_vshifti(s, INSN_VSARI, q, a0, a1, (16 << vece) - a2); 2869 return; 2870 case INDEX_op_arm_sli_vec: 2871 tcg_out_vshifti(s, INSN_VSLI, q, a0, a2, args[3] + (8 << vece)); 2872 return; 2873 2874 case INDEX_op_andc_vec: 2875 if (!const_args[2]) { 2876 tcg_out_vreg3(s, INSN_VBIC, q, 0, a0, a1, a2); 2877 return; 2878 } 2879 a2 = ~a2; 2880 /* fall through */ 2881 case INDEX_op_and_vec: 2882 if (const_args[2]) { 2883 is_shimm1632(~a2, &cmode, &imm8); 2884 if (a0 == a1) { 2885 tcg_out_vmovi(s, a0, q, 1, cmode | 1, imm8); /* VBICI */ 2886 return; 2887 } 2888 tcg_out_vmovi(s, a0, q, 1, cmode, imm8); /* VMVNI */ 2889 a2 = a0; 2890 } 2891 tcg_out_vreg3(s, INSN_VAND, q, 0, a0, a1, a2); 2892 return; 2893 2894 case INDEX_op_orc_vec: 2895 if (!const_args[2]) { 2896 tcg_out_vreg3(s, INSN_VORN, q, 0, a0, a1, a2); 2897 return; 2898 } 2899 a2 = ~a2; 2900 /* fall through */ 2901 case INDEX_op_or_vec: 2902 if (const_args[2]) { 2903 is_shimm1632(a2, &cmode, &imm8); 2904 if (a0 == a1) { 2905 tcg_out_vmovi(s, a0, q, 0, cmode | 1, imm8); /* VORRI */ 2906 return; 2907 } 2908 tcg_out_vmovi(s, a0, q, 0, cmode, imm8); /* VMOVI */ 2909 a2 = a0; 2910 } 2911 tcg_out_vreg3(s, INSN_VORR, q, 0, a0, a1, a2); 2912 return; 2913 2914 case INDEX_op_cmp_vec: 2915 { 2916 TCGCond cond = args[3]; 2917 2918 if (cond == TCG_COND_NE) { 2919 if (const_args[2]) { 2920 tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a1); 2921 } else { 2922 tcg_out_vreg3(s, INSN_VCEQ, q, vece, a0, a1, a2); 2923 tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0); 2924 } 2925 } else { 2926 ARMInsn insn; 2927 2928 if (const_args[2]) { 2929 insn = vec_cmp0_insn[cond]; 2930 if (insn) { 2931 tcg_out_vreg2(s, insn, q, vece, a0, a1); 2932 return; 2933 } 2934 tcg_out_dupi_vec(s, type, MO_8, TCG_VEC_TMP, 0); 2935 a2 = TCG_VEC_TMP; 2936 } 2937 insn = vec_cmp_insn[cond]; 2938 if (insn == 0) { 2939 TCGArg t; 2940 t = a1, a1 = a2, a2 = t; 2941 cond = tcg_swap_cond(cond); 2942 insn = vec_cmp_insn[cond]; 2943 tcg_debug_assert(insn != 0); 2944 } 2945 tcg_out_vreg3(s, insn, q, vece, a0, a1, a2); 2946 } 2947 } 2948 return; 2949 2950 case INDEX_op_bitsel_vec: 2951 a3 = args[3]; 2952 if (a0 == a3) { 2953 tcg_out_vreg3(s, INSN_VBIT, q, 0, a0, a2, a1); 2954 } else if (a0 == a2) { 2955 tcg_out_vreg3(s, INSN_VBIF, q, 0, a0, a3, a1); 2956 } else { 2957 tcg_out_mov(s, type, a0, a1); 2958 tcg_out_vreg3(s, INSN_VBSL, q, 0, a0, a2, a3); 2959 } 2960 return; 2961 2962 case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ 2963 case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ 2964 default: 2965 g_assert_not_reached(); 2966 } 2967} 2968 2969int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 2970{ 2971 switch (opc) { 2972 case INDEX_op_add_vec: 2973 case INDEX_op_sub_vec: 2974 case INDEX_op_and_vec: 2975 case INDEX_op_andc_vec: 2976 case INDEX_op_or_vec: 2977 case INDEX_op_orc_vec: 2978 case INDEX_op_xor_vec: 2979 case INDEX_op_not_vec: 2980 case INDEX_op_shli_vec: 2981 case INDEX_op_shri_vec: 2982 case INDEX_op_sari_vec: 2983 case INDEX_op_ssadd_vec: 2984 case INDEX_op_sssub_vec: 2985 case INDEX_op_usadd_vec: 2986 case INDEX_op_ussub_vec: 2987 case INDEX_op_bitsel_vec: 2988 return 1; 2989 case INDEX_op_abs_vec: 2990 case INDEX_op_cmp_vec: 2991 case INDEX_op_mul_vec: 2992 case INDEX_op_neg_vec: 2993 case INDEX_op_smax_vec: 2994 case INDEX_op_smin_vec: 2995 case INDEX_op_umax_vec: 2996 case INDEX_op_umin_vec: 2997 return vece < MO_64; 2998 case INDEX_op_shlv_vec: 2999 case INDEX_op_shrv_vec: 3000 case INDEX_op_sarv_vec: 3001 case INDEX_op_rotli_vec: 3002 case INDEX_op_rotlv_vec: 3003 case INDEX_op_rotrv_vec: 3004 return -1; 3005 default: 3006 return 0; 3007 } 3008} 3009 3010void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 3011 TCGArg a0, ...) 3012{ 3013 va_list va; 3014 TCGv_vec v0, v1, v2, t1, t2, c1; 3015 TCGArg a2; 3016 3017 va_start(va, a0); 3018 v0 = temp_tcgv_vec(arg_temp(a0)); 3019 v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 3020 a2 = va_arg(va, TCGArg); 3021 va_end(va); 3022 3023 switch (opc) { 3024 case INDEX_op_shlv_vec: 3025 /* 3026 * Merely propagate shlv_vec to arm_ushl_vec. 3027 * In this way we don't set TCG_TARGET_HAS_shv_vec 3028 * because everything is done via expansion. 3029 */ 3030 v2 = temp_tcgv_vec(arg_temp(a2)); 3031 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0), 3032 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 3033 break; 3034 3035 case INDEX_op_shrv_vec: 3036 case INDEX_op_sarv_vec: 3037 /* Right shifts are negative left shifts for NEON. */ 3038 v2 = temp_tcgv_vec(arg_temp(a2)); 3039 t1 = tcg_temp_new_vec(type); 3040 tcg_gen_neg_vec(vece, t1, v2); 3041 if (opc == INDEX_op_shrv_vec) { 3042 opc = INDEX_op_arm_ushl_vec; 3043 } else { 3044 opc = INDEX_op_arm_sshl_vec; 3045 } 3046 vec_gen_3(opc, type, vece, tcgv_vec_arg(v0), 3047 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 3048 tcg_temp_free_vec(t1); 3049 break; 3050 3051 case INDEX_op_rotli_vec: 3052 t1 = tcg_temp_new_vec(type); 3053 tcg_gen_shri_vec(vece, t1, v1, -a2 & ((8 << vece) - 1)); 3054 vec_gen_4(INDEX_op_arm_sli_vec, type, vece, 3055 tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(v1), a2); 3056 tcg_temp_free_vec(t1); 3057 break; 3058 3059 case INDEX_op_rotlv_vec: 3060 v2 = temp_tcgv_vec(arg_temp(a2)); 3061 t1 = tcg_temp_new_vec(type); 3062 c1 = tcg_constant_vec(type, vece, 8 << vece); 3063 tcg_gen_sub_vec(vece, t1, v2, c1); 3064 /* Right shifts are negative left shifts for NEON. */ 3065 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1), 3066 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 3067 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0), 3068 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 3069 tcg_gen_or_vec(vece, v0, v0, t1); 3070 tcg_temp_free_vec(t1); 3071 break; 3072 3073 case INDEX_op_rotrv_vec: 3074 v2 = temp_tcgv_vec(arg_temp(a2)); 3075 t1 = tcg_temp_new_vec(type); 3076 t2 = tcg_temp_new_vec(type); 3077 c1 = tcg_constant_vec(type, vece, 8 << vece); 3078 tcg_gen_neg_vec(vece, t1, v2); 3079 tcg_gen_sub_vec(vece, t2, c1, v2); 3080 /* Right shifts are negative left shifts for NEON. */ 3081 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1), 3082 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 3083 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t2), 3084 tcgv_vec_arg(v1), tcgv_vec_arg(t2)); 3085 tcg_gen_or_vec(vece, v0, t1, t2); 3086 tcg_temp_free_vec(t1); 3087 tcg_temp_free_vec(t2); 3088 break; 3089 3090 default: 3091 g_assert_not_reached(); 3092 } 3093} 3094 3095static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 3096{ 3097 int i; 3098 for (i = 0; i < count; ++i) { 3099 p[i] = INSN_NOP; 3100 } 3101} 3102 3103/* Compute frame size via macros, to share between tcg_target_qemu_prologue 3104 and tcg_register_jit. */ 3105 3106#define PUSH_SIZE ((11 - 4 + 1 + 1) * sizeof(tcg_target_long)) 3107 3108#define FRAME_SIZE \ 3109 ((PUSH_SIZE \ 3110 + TCG_STATIC_CALL_ARGS_SIZE \ 3111 + CPU_TEMP_BUF_NLONGS * sizeof(long) \ 3112 + TCG_TARGET_STACK_ALIGN - 1) \ 3113 & -TCG_TARGET_STACK_ALIGN) 3114 3115#define STACK_ADDEND (FRAME_SIZE - PUSH_SIZE) 3116 3117static void tcg_target_qemu_prologue(TCGContext *s) 3118{ 3119 /* Calling convention requires us to save r4-r11 and lr. */ 3120 /* stmdb sp!, { r4 - r11, lr } */ 3121 tcg_out_ldstm(s, COND_AL, INSN_STMDB, TCG_REG_CALL_STACK, 3122 (1 << TCG_REG_R4) | (1 << TCG_REG_R5) | (1 << TCG_REG_R6) | 3123 (1 << TCG_REG_R7) | (1 << TCG_REG_R8) | (1 << TCG_REG_R9) | 3124 (1 << TCG_REG_R10) | (1 << TCG_REG_R11) | (1 << TCG_REG_R14)); 3125 3126 /* Reserve callee argument and tcg temp space. */ 3127 tcg_out_dat_rI(s, COND_AL, ARITH_SUB, TCG_REG_CALL_STACK, 3128 TCG_REG_CALL_STACK, STACK_ADDEND, 1); 3129 tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE, 3130 CPU_TEMP_BUF_NLONGS * sizeof(long)); 3131 3132 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 3133 3134#ifndef CONFIG_SOFTMMU 3135 if (guest_base) { 3136 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_GUEST_BASE, guest_base); 3137 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GUEST_BASE); 3138 } 3139#endif 3140 3141 tcg_out_b_reg(s, COND_AL, tcg_target_call_iarg_regs[1]); 3142 3143 /* 3144 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 3145 * and fall through to the rest of the epilogue. 3146 */ 3147 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 3148 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, 0); 3149 tcg_out_epilogue(s); 3150} 3151 3152static void tcg_out_epilogue(TCGContext *s) 3153{ 3154 /* Release local stack frame. */ 3155 tcg_out_dat_rI(s, COND_AL, ARITH_ADD, TCG_REG_CALL_STACK, 3156 TCG_REG_CALL_STACK, STACK_ADDEND, 1); 3157 3158 /* ldmia sp!, { r4 - r11, pc } */ 3159 tcg_out_ldstm(s, COND_AL, INSN_LDMIA, TCG_REG_CALL_STACK, 3160 (1 << TCG_REG_R4) | (1 << TCG_REG_R5) | (1 << TCG_REG_R6) | 3161 (1 << TCG_REG_R7) | (1 << TCG_REG_R8) | (1 << TCG_REG_R9) | 3162 (1 << TCG_REG_R10) | (1 << TCG_REG_R11) | (1 << TCG_REG_PC)); 3163} 3164 3165typedef struct { 3166 DebugFrameHeader h; 3167 uint8_t fde_def_cfa[4]; 3168 uint8_t fde_reg_ofs[18]; 3169} DebugFrame; 3170 3171#define ELF_HOST_MACHINE EM_ARM 3172 3173/* We're expecting a 2 byte uleb128 encoded value. */ 3174QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); 3175 3176static const DebugFrame debug_frame = { 3177 .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ 3178 .h.cie.id = -1, 3179 .h.cie.version = 1, 3180 .h.cie.code_align = 1, 3181 .h.cie.data_align = 0x7c, /* sleb128 -4 */ 3182 .h.cie.return_column = 14, 3183 3184 /* Total FDE size does not include the "len" member. */ 3185 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 3186 3187 .fde_def_cfa = { 3188 12, 13, /* DW_CFA_def_cfa sp, ... */ 3189 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 3190 (FRAME_SIZE >> 7) 3191 }, 3192 .fde_reg_ofs = { 3193 /* The following must match the stmdb in the prologue. */ 3194 0x8e, 1, /* DW_CFA_offset, lr, -4 */ 3195 0x8b, 2, /* DW_CFA_offset, r11, -8 */ 3196 0x8a, 3, /* DW_CFA_offset, r10, -12 */ 3197 0x89, 4, /* DW_CFA_offset, r9, -16 */ 3198 0x88, 5, /* DW_CFA_offset, r8, -20 */ 3199 0x87, 6, /* DW_CFA_offset, r7, -24 */ 3200 0x86, 7, /* DW_CFA_offset, r6, -28 */ 3201 0x85, 8, /* DW_CFA_offset, r5, -32 */ 3202 0x84, 9, /* DW_CFA_offset, r4, -36 */ 3203 } 3204}; 3205 3206void tcg_register_jit(const void *buf, size_t buf_size) 3207{ 3208 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 3209} 3210