1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Andrzej Zaborowski 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25#include "elf.h" 26 27int arm_arch = __ARM_ARCH; 28 29#ifndef use_idiv_instructions 30bool use_idiv_instructions; 31#endif 32#ifndef use_neon_instructions 33bool use_neon_instructions; 34#endif 35 36/* Used for function call generation. */ 37#define TCG_TARGET_STACK_ALIGN 8 38#define TCG_TARGET_CALL_STACK_OFFSET 0 39#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL 40#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN 41#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN 42#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF 43 44#ifdef CONFIG_DEBUG_TCG 45static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 46 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", 47 "%r8", "%r9", "%r10", "%r11", "%r12", "%sp", "%r14", "%pc", 48 "%q0", "%q1", "%q2", "%q3", "%q4", "%q5", "%q6", "%q7", 49 "%q8", "%q9", "%q10", "%q11", "%q12", "%q13", "%q14", "%q15", 50}; 51#endif 52 53static const int tcg_target_reg_alloc_order[] = { 54 TCG_REG_R4, 55 TCG_REG_R5, 56 TCG_REG_R6, 57 TCG_REG_R7, 58 TCG_REG_R8, 59 TCG_REG_R9, 60 TCG_REG_R10, 61 TCG_REG_R11, 62 TCG_REG_R13, 63 TCG_REG_R0, 64 TCG_REG_R1, 65 TCG_REG_R2, 66 TCG_REG_R3, 67 TCG_REG_R12, 68 TCG_REG_R14, 69 70 TCG_REG_Q0, 71 TCG_REG_Q1, 72 TCG_REG_Q2, 73 TCG_REG_Q3, 74 /* Q4 - Q7 are call-saved, and skipped. */ 75 TCG_REG_Q8, 76 TCG_REG_Q9, 77 TCG_REG_Q10, 78 TCG_REG_Q11, 79 TCG_REG_Q12, 80 TCG_REG_Q13, 81 TCG_REG_Q14, 82 TCG_REG_Q15, 83}; 84 85static const int tcg_target_call_iarg_regs[4] = { 86 TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3 87}; 88 89static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 90{ 91 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 92 tcg_debug_assert(slot >= 0 && slot <= 3); 93 return TCG_REG_R0 + slot; 94} 95 96#define TCG_REG_TMP TCG_REG_R12 97#define TCG_VEC_TMP TCG_REG_Q15 98#define TCG_REG_GUEST_BASE TCG_REG_R11 99 100typedef enum { 101 COND_EQ = 0x0, 102 COND_NE = 0x1, 103 COND_CS = 0x2, /* Unsigned greater or equal */ 104 COND_CC = 0x3, /* Unsigned less than */ 105 COND_MI = 0x4, /* Negative */ 106 COND_PL = 0x5, /* Zero or greater */ 107 COND_VS = 0x6, /* Overflow */ 108 COND_VC = 0x7, /* No overflow */ 109 COND_HI = 0x8, /* Unsigned greater than */ 110 COND_LS = 0x9, /* Unsigned less or equal */ 111 COND_GE = 0xa, 112 COND_LT = 0xb, 113 COND_GT = 0xc, 114 COND_LE = 0xd, 115 COND_AL = 0xe, 116} ARMCond; 117 118#define TO_CPSR (1 << 20) 119 120#define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00) 121#define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20) 122#define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40) 123#define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60) 124#define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10) 125#define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30) 126#define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50) 127#define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70) 128 129typedef enum { 130 ARITH_AND = 0x0 << 21, 131 ARITH_EOR = 0x1 << 21, 132 ARITH_SUB = 0x2 << 21, 133 ARITH_RSB = 0x3 << 21, 134 ARITH_ADD = 0x4 << 21, 135 ARITH_ADC = 0x5 << 21, 136 ARITH_SBC = 0x6 << 21, 137 ARITH_RSC = 0x7 << 21, 138 ARITH_TST = 0x8 << 21 | TO_CPSR, 139 ARITH_CMP = 0xa << 21 | TO_CPSR, 140 ARITH_CMN = 0xb << 21 | TO_CPSR, 141 ARITH_ORR = 0xc << 21, 142 ARITH_MOV = 0xd << 21, 143 ARITH_BIC = 0xe << 21, 144 ARITH_MVN = 0xf << 21, 145 146 INSN_B = 0x0a000000, 147 148 INSN_CLZ = 0x016f0f10, 149 INSN_RBIT = 0x06ff0f30, 150 151 INSN_LDMIA = 0x08b00000, 152 INSN_STMDB = 0x09200000, 153 154 INSN_LDR_IMM = 0x04100000, 155 INSN_LDR_REG = 0x06100000, 156 INSN_STR_IMM = 0x04000000, 157 INSN_STR_REG = 0x06000000, 158 159 INSN_LDRH_IMM = 0x005000b0, 160 INSN_LDRH_REG = 0x001000b0, 161 INSN_LDRSH_IMM = 0x005000f0, 162 INSN_LDRSH_REG = 0x001000f0, 163 INSN_STRH_IMM = 0x004000b0, 164 INSN_STRH_REG = 0x000000b0, 165 166 INSN_LDRB_IMM = 0x04500000, 167 INSN_LDRB_REG = 0x06500000, 168 INSN_LDRSB_IMM = 0x005000d0, 169 INSN_LDRSB_REG = 0x001000d0, 170 INSN_STRB_IMM = 0x04400000, 171 INSN_STRB_REG = 0x06400000, 172 173 INSN_LDRD_IMM = 0x004000d0, 174 INSN_LDRD_REG = 0x000000d0, 175 INSN_STRD_IMM = 0x004000f0, 176 INSN_STRD_REG = 0x000000f0, 177 178 INSN_DMB_ISH = 0xf57ff05b, 179 INSN_DMB_MCR = 0xee070fba, 180 181 /* Architected nop introduced in v6k. */ 182 /* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this 183 also Just So Happened to do nothing on pre-v6k so that we 184 don't need to conditionalize it? */ 185 INSN_NOP_v6k = 0xe320f000, 186 /* Otherwise the assembler uses mov r0,r0 */ 187 INSN_NOP_v4 = (COND_AL << 28) | ARITH_MOV, 188 189 INSN_VADD = 0xf2000800, 190 INSN_VAND = 0xf2000110, 191 INSN_VBIC = 0xf2100110, 192 INSN_VEOR = 0xf3000110, 193 INSN_VORN = 0xf2300110, 194 INSN_VORR = 0xf2200110, 195 INSN_VSUB = 0xf3000800, 196 INSN_VMUL = 0xf2000910, 197 INSN_VQADD = 0xf2000010, 198 INSN_VQADD_U = 0xf3000010, 199 INSN_VQSUB = 0xf2000210, 200 INSN_VQSUB_U = 0xf3000210, 201 INSN_VMAX = 0xf2000600, 202 INSN_VMAX_U = 0xf3000600, 203 INSN_VMIN = 0xf2000610, 204 INSN_VMIN_U = 0xf3000610, 205 206 INSN_VABS = 0xf3b10300, 207 INSN_VMVN = 0xf3b00580, 208 INSN_VNEG = 0xf3b10380, 209 210 INSN_VCEQ0 = 0xf3b10100, 211 INSN_VCGT0 = 0xf3b10000, 212 INSN_VCGE0 = 0xf3b10080, 213 INSN_VCLE0 = 0xf3b10180, 214 INSN_VCLT0 = 0xf3b10200, 215 216 INSN_VCEQ = 0xf3000810, 217 INSN_VCGE = 0xf2000310, 218 INSN_VCGT = 0xf2000300, 219 INSN_VCGE_U = 0xf3000310, 220 INSN_VCGT_U = 0xf3000300, 221 222 INSN_VSHLI = 0xf2800510, /* VSHL (immediate) */ 223 INSN_VSARI = 0xf2800010, /* VSHR.S */ 224 INSN_VSHRI = 0xf3800010, /* VSHR.U */ 225 INSN_VSLI = 0xf3800510, 226 INSN_VSHL_S = 0xf2000400, /* VSHL.S (register) */ 227 INSN_VSHL_U = 0xf3000400, /* VSHL.U (register) */ 228 229 INSN_VBSL = 0xf3100110, 230 INSN_VBIT = 0xf3200110, 231 INSN_VBIF = 0xf3300110, 232 233 INSN_VTST = 0xf2000810, 234 235 INSN_VDUP_G = 0xee800b10, /* VDUP (ARM core register) */ 236 INSN_VDUP_S = 0xf3b00c00, /* VDUP (scalar) */ 237 INSN_VLDR_D = 0xed100b00, /* VLDR.64 */ 238 INSN_VLD1 = 0xf4200000, /* VLD1 (multiple single elements) */ 239 INSN_VLD1R = 0xf4a00c00, /* VLD1 (single element to all lanes) */ 240 INSN_VST1 = 0xf4000000, /* VST1 (multiple single elements) */ 241 INSN_VMOVI = 0xf2800010, /* VMOV (immediate) */ 242} ARMInsn; 243 244#define INSN_NOP (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4) 245 246static const uint8_t tcg_cond_to_arm_cond[] = { 247 [TCG_COND_EQ] = COND_EQ, 248 [TCG_COND_NE] = COND_NE, 249 [TCG_COND_LT] = COND_LT, 250 [TCG_COND_GE] = COND_GE, 251 [TCG_COND_LE] = COND_LE, 252 [TCG_COND_GT] = COND_GT, 253 /* unsigned */ 254 [TCG_COND_LTU] = COND_CC, 255 [TCG_COND_GEU] = COND_CS, 256 [TCG_COND_LEU] = COND_LS, 257 [TCG_COND_GTU] = COND_HI, 258}; 259 260static int encode_imm(uint32_t imm); 261 262/* TCG private relocation type: add with pc+imm8 */ 263#define R_ARM_PC8 11 264 265/* TCG private relocation type: vldr with imm8 << 2 */ 266#define R_ARM_PC11 12 267 268static bool reloc_pc24(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 269{ 270 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 271 ptrdiff_t offset = (tcg_ptr_byte_diff(target, src_rx) - 8) >> 2; 272 273 if (offset == sextract32(offset, 0, 24)) { 274 *src_rw = deposit32(*src_rw, 0, 24, offset); 275 return true; 276 } 277 return false; 278} 279 280static bool reloc_pc13(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 281{ 282 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 283 ptrdiff_t offset = tcg_ptr_byte_diff(target, src_rx) - 8; 284 285 if (offset >= -0xfff && offset <= 0xfff) { 286 tcg_insn_unit insn = *src_rw; 287 bool u = (offset >= 0); 288 if (!u) { 289 offset = -offset; 290 } 291 insn = deposit32(insn, 23, 1, u); 292 insn = deposit32(insn, 0, 12, offset); 293 *src_rw = insn; 294 return true; 295 } 296 return false; 297} 298 299static bool reloc_pc11(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 300{ 301 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 302 ptrdiff_t offset = (tcg_ptr_byte_diff(target, src_rx) - 8) / 4; 303 304 if (offset >= -0xff && offset <= 0xff) { 305 tcg_insn_unit insn = *src_rw; 306 bool u = (offset >= 0); 307 if (!u) { 308 offset = -offset; 309 } 310 insn = deposit32(insn, 23, 1, u); 311 insn = deposit32(insn, 0, 8, offset); 312 *src_rw = insn; 313 return true; 314 } 315 return false; 316} 317 318static bool reloc_pc8(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 319{ 320 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 321 ptrdiff_t offset = tcg_ptr_byte_diff(target, src_rx) - 8; 322 int imm12 = encode_imm(offset); 323 324 if (imm12 >= 0) { 325 *src_rw = deposit32(*src_rw, 0, 12, imm12); 326 return true; 327 } 328 return false; 329} 330 331static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 332 intptr_t value, intptr_t addend) 333{ 334 tcg_debug_assert(addend == 0); 335 switch (type) { 336 case R_ARM_PC24: 337 return reloc_pc24(code_ptr, (const tcg_insn_unit *)value); 338 case R_ARM_PC13: 339 return reloc_pc13(code_ptr, (const tcg_insn_unit *)value); 340 case R_ARM_PC11: 341 return reloc_pc11(code_ptr, (const tcg_insn_unit *)value); 342 case R_ARM_PC8: 343 return reloc_pc8(code_ptr, (const tcg_insn_unit *)value); 344 default: 345 g_assert_not_reached(); 346 } 347} 348 349#define TCG_CT_CONST_ARM 0x100 350#define TCG_CT_CONST_INV 0x200 351#define TCG_CT_CONST_NEG 0x400 352#define TCG_CT_CONST_ZERO 0x800 353#define TCG_CT_CONST_ORRI 0x1000 354#define TCG_CT_CONST_ANDI 0x2000 355 356#define ALL_GENERAL_REGS 0xffffu 357#define ALL_VECTOR_REGS 0xffff0000u 358 359/* 360 * r0-r3 will be overwritten when reading the tlb entry (system-mode only); 361 * r14 will be overwritten by the BLNE branching to the slow path. 362 */ 363#define ALL_QLDST_REGS \ 364 (ALL_GENERAL_REGS & ~((tcg_use_softmmu ? 0xf : 0) | (1 << TCG_REG_R14))) 365 366/* 367 * ARM immediates for ALU instructions are made of an unsigned 8-bit 368 * right-rotated by an even amount between 0 and 30. 369 * 370 * Return < 0 if @imm cannot be encoded, else the entire imm12 field. 371 */ 372static int encode_imm(uint32_t imm) 373{ 374 uint32_t rot, imm8; 375 376 /* Simple case, no rotation required. */ 377 if ((imm & ~0xff) == 0) { 378 return imm; 379 } 380 381 /* Next, try a simple even shift. */ 382 rot = ctz32(imm) & ~1; 383 imm8 = imm >> rot; 384 rot = 32 - rot; 385 if ((imm8 & ~0xff) == 0) { 386 goto found; 387 } 388 389 /* 390 * Finally, try harder with rotations. 391 * The ctz test above will have taken care of rotates >= 8. 392 */ 393 for (rot = 2; rot < 8; rot += 2) { 394 imm8 = rol32(imm, rot); 395 if ((imm8 & ~0xff) == 0) { 396 goto found; 397 } 398 } 399 /* Fail: imm cannot be encoded. */ 400 return -1; 401 402 found: 403 /* Note that rot is even, and we discard bit 0 by shifting by 7. */ 404 return rot << 7 | imm8; 405} 406 407static int encode_imm_nofail(uint32_t imm) 408{ 409 int ret = encode_imm(imm); 410 tcg_debug_assert(ret >= 0); 411 return ret; 412} 413 414static bool check_fit_imm(uint32_t imm) 415{ 416 return encode_imm(imm) >= 0; 417} 418 419/* Return true if v16 is a valid 16-bit shifted immediate. */ 420static bool is_shimm16(uint16_t v16, int *cmode, int *imm8) 421{ 422 if (v16 == (v16 & 0xff)) { 423 *cmode = 0x8; 424 *imm8 = v16 & 0xff; 425 return true; 426 } else if (v16 == (v16 & 0xff00)) { 427 *cmode = 0xa; 428 *imm8 = v16 >> 8; 429 return true; 430 } 431 return false; 432} 433 434/* Return true if v32 is a valid 32-bit shifted immediate. */ 435static bool is_shimm32(uint32_t v32, int *cmode, int *imm8) 436{ 437 if (v32 == (v32 & 0xff)) { 438 *cmode = 0x0; 439 *imm8 = v32 & 0xff; 440 return true; 441 } else if (v32 == (v32 & 0xff00)) { 442 *cmode = 0x2; 443 *imm8 = (v32 >> 8) & 0xff; 444 return true; 445 } else if (v32 == (v32 & 0xff0000)) { 446 *cmode = 0x4; 447 *imm8 = (v32 >> 16) & 0xff; 448 return true; 449 } else if (v32 == (v32 & 0xff000000)) { 450 *cmode = 0x6; 451 *imm8 = v32 >> 24; 452 return true; 453 } 454 return false; 455} 456 457/* Return true if v32 is a valid 32-bit shifting ones immediate. */ 458static bool is_soimm32(uint32_t v32, int *cmode, int *imm8) 459{ 460 if ((v32 & 0xffff00ff) == 0xff) { 461 *cmode = 0xc; 462 *imm8 = (v32 >> 8) & 0xff; 463 return true; 464 } else if ((v32 & 0xff00ffff) == 0xffff) { 465 *cmode = 0xd; 466 *imm8 = (v32 >> 16) & 0xff; 467 return true; 468 } 469 return false; 470} 471 472/* 473 * Return non-zero if v32 can be formed by MOVI+ORR. 474 * Place the parameters for MOVI in (cmode, imm8). 475 * Return the cmode for ORR; the imm8 can be had via extraction from v32. 476 */ 477static int is_shimm32_pair(uint32_t v32, int *cmode, int *imm8) 478{ 479 int i; 480 481 for (i = 6; i > 0; i -= 2) { 482 /* Mask out one byte we can add with ORR. */ 483 uint32_t tmp = v32 & ~(0xffu << (i * 4)); 484 if (is_shimm32(tmp, cmode, imm8) || 485 is_soimm32(tmp, cmode, imm8)) { 486 break; 487 } 488 } 489 return i; 490} 491 492/* Return true if V is a valid 16-bit or 32-bit shifted immediate. */ 493static bool is_shimm1632(uint32_t v32, int *cmode, int *imm8) 494{ 495 if (v32 == deposit32(v32, 16, 16, v32)) { 496 return is_shimm16(v32, cmode, imm8); 497 } else { 498 return is_shimm32(v32, cmode, imm8); 499 } 500} 501 502/* Test if a constant matches the constraint. 503 * TODO: define constraints for: 504 * 505 * ldr/str offset: between -0xfff and 0xfff 506 * ldrh/strh offset: between -0xff and 0xff 507 * mov operand2: values represented with x << (2 * y), x < 0x100 508 * add, sub, eor...: ditto 509 */ 510static bool tcg_target_const_match(int64_t val, int ct, 511 TCGType type, TCGCond cond, int vece) 512{ 513 if (ct & TCG_CT_CONST) { 514 return 1; 515 } else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val)) { 516 return 1; 517 } else if ((ct & TCG_CT_CONST_INV) && check_fit_imm(~val)) { 518 return 1; 519 } else if ((ct & TCG_CT_CONST_NEG) && check_fit_imm(-val)) { 520 return 1; 521 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 522 return 1; 523 } 524 525 switch (ct & (TCG_CT_CONST_ORRI | TCG_CT_CONST_ANDI)) { 526 case 0: 527 break; 528 case TCG_CT_CONST_ANDI: 529 val = ~val; 530 /* fallthru */ 531 case TCG_CT_CONST_ORRI: 532 if (val == deposit64(val, 32, 32, val)) { 533 int cmode, imm8; 534 return is_shimm1632(val, &cmode, &imm8); 535 } 536 break; 537 default: 538 /* Both bits should not be set for the same insn. */ 539 g_assert_not_reached(); 540 } 541 542 return 0; 543} 544 545static void tcg_out_b_imm(TCGContext *s, ARMCond cond, int32_t offset) 546{ 547 tcg_out32(s, (cond << 28) | INSN_B | 548 (((offset - 8) >> 2) & 0x00ffffff)); 549} 550 551static void tcg_out_bl_imm(TCGContext *s, ARMCond cond, int32_t offset) 552{ 553 tcg_out32(s, (cond << 28) | 0x0b000000 | 554 (((offset - 8) >> 2) & 0x00ffffff)); 555} 556 557static void tcg_out_blx_reg(TCGContext *s, ARMCond cond, TCGReg rn) 558{ 559 tcg_out32(s, (cond << 28) | 0x012fff30 | rn); 560} 561 562static void tcg_out_blx_imm(TCGContext *s, int32_t offset) 563{ 564 tcg_out32(s, 0xfa000000 | ((offset & 2) << 23) | 565 (((offset - 8) >> 2) & 0x00ffffff)); 566} 567 568static void tcg_out_dat_reg(TCGContext *s, ARMCond cond, ARMInsn opc, 569 TCGReg rd, TCGReg rn, TCGReg rm, int shift) 570{ 571 tcg_out32(s, (cond << 28) | (0 << 25) | opc | 572 (rn << 16) | (rd << 12) | shift | rm); 573} 574 575static void tcg_out_mov_reg(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rm) 576{ 577 /* Simple reg-reg move, optimising out the 'do nothing' case */ 578 if (rd != rm) { 579 tcg_out_dat_reg(s, cond, ARITH_MOV, rd, 0, rm, SHIFT_IMM_LSL(0)); 580 } 581} 582 583static void tcg_out_bx_reg(TCGContext *s, ARMCond cond, TCGReg rn) 584{ 585 tcg_out32(s, (cond << 28) | 0x012fff10 | rn); 586} 587 588static void tcg_out_b_reg(TCGContext *s, ARMCond cond, TCGReg rn) 589{ 590 /* 591 * Unless the C portion of QEMU is compiled as thumb, we don't need 592 * true BX semantics; merely a branch to an address held in a register. 593 */ 594 tcg_out_bx_reg(s, cond, rn); 595} 596 597static void tcg_out_dat_imm(TCGContext *s, ARMCond cond, ARMInsn opc, 598 TCGReg rd, TCGReg rn, int im) 599{ 600 tcg_out32(s, (cond << 28) | (1 << 25) | opc | 601 (rn << 16) | (rd << 12) | im); 602} 603 604static void tcg_out_ldstm(TCGContext *s, ARMCond cond, ARMInsn opc, 605 TCGReg rn, uint16_t mask) 606{ 607 tcg_out32(s, (cond << 28) | opc | (rn << 16) | mask); 608} 609 610/* Note that this routine is used for both LDR and LDRH formats, so we do 611 not wish to include an immediate shift at this point. */ 612static void tcg_out_memop_r(TCGContext *s, ARMCond cond, ARMInsn opc, TCGReg rt, 613 TCGReg rn, TCGReg rm, bool u, bool p, bool w) 614{ 615 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) 616 | (w << 21) | (rn << 16) | (rt << 12) | rm); 617} 618 619static void tcg_out_memop_8(TCGContext *s, ARMCond cond, ARMInsn opc, TCGReg rt, 620 TCGReg rn, int imm8, bool p, bool w) 621{ 622 bool u = 1; 623 if (imm8 < 0) { 624 imm8 = -imm8; 625 u = 0; 626 } 627 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | 628 (rn << 16) | (rt << 12) | ((imm8 & 0xf0) << 4) | (imm8 & 0xf)); 629} 630 631static void tcg_out_memop_12(TCGContext *s, ARMCond cond, ARMInsn opc, 632 TCGReg rt, TCGReg rn, int imm12, bool p, bool w) 633{ 634 bool u = 1; 635 if (imm12 < 0) { 636 imm12 = -imm12; 637 u = 0; 638 } 639 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | 640 (rn << 16) | (rt << 12) | imm12); 641} 642 643static void tcg_out_ld32_12(TCGContext *s, ARMCond cond, TCGReg rt, 644 TCGReg rn, int imm12) 645{ 646 tcg_out_memop_12(s, cond, INSN_LDR_IMM, rt, rn, imm12, 1, 0); 647} 648 649static void tcg_out_st32_12(TCGContext *s, ARMCond cond, TCGReg rt, 650 TCGReg rn, int imm12) 651{ 652 tcg_out_memop_12(s, cond, INSN_STR_IMM, rt, rn, imm12, 1, 0); 653} 654 655static void tcg_out_ld32_r(TCGContext *s, ARMCond cond, TCGReg rt, 656 TCGReg rn, TCGReg rm) 657{ 658 tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 0); 659} 660 661static void tcg_out_st32_r(TCGContext *s, ARMCond cond, TCGReg rt, 662 TCGReg rn, TCGReg rm) 663{ 664 tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 0); 665} 666 667static void tcg_out_ldrd_8(TCGContext *s, ARMCond cond, TCGReg rt, 668 TCGReg rn, int imm8) 669{ 670 tcg_out_memop_8(s, cond, INSN_LDRD_IMM, rt, rn, imm8, 1, 0); 671} 672 673static void tcg_out_ldrd_r(TCGContext *s, ARMCond cond, TCGReg rt, 674 TCGReg rn, TCGReg rm) 675{ 676 tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 0); 677} 678 679static void tcg_out_strd_8(TCGContext *s, ARMCond cond, TCGReg rt, 680 TCGReg rn, int imm8) 681{ 682 tcg_out_memop_8(s, cond, INSN_STRD_IMM, rt, rn, imm8, 1, 0); 683} 684 685static void tcg_out_strd_r(TCGContext *s, ARMCond cond, TCGReg rt, 686 TCGReg rn, TCGReg rm) 687{ 688 tcg_out_memop_r(s, cond, INSN_STRD_REG, rt, rn, rm, 1, 1, 0); 689} 690 691/* Register pre-increment with base writeback. */ 692static void tcg_out_ld32_rwb(TCGContext *s, ARMCond cond, TCGReg rt, 693 TCGReg rn, TCGReg rm) 694{ 695 tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 1); 696} 697 698static void tcg_out_st32_rwb(TCGContext *s, ARMCond cond, TCGReg rt, 699 TCGReg rn, TCGReg rm) 700{ 701 tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 1); 702} 703 704static void tcg_out_ld16u_8(TCGContext *s, ARMCond cond, TCGReg rt, 705 TCGReg rn, int imm8) 706{ 707 tcg_out_memop_8(s, cond, INSN_LDRH_IMM, rt, rn, imm8, 1, 0); 708} 709 710static void tcg_out_st16_8(TCGContext *s, ARMCond cond, TCGReg rt, 711 TCGReg rn, int imm8) 712{ 713 tcg_out_memop_8(s, cond, INSN_STRH_IMM, rt, rn, imm8, 1, 0); 714} 715 716static void tcg_out_ld16u_r(TCGContext *s, ARMCond cond, TCGReg rt, 717 TCGReg rn, TCGReg rm) 718{ 719 tcg_out_memop_r(s, cond, INSN_LDRH_REG, rt, rn, rm, 1, 1, 0); 720} 721 722static void tcg_out_st16_r(TCGContext *s, ARMCond cond, TCGReg rt, 723 TCGReg rn, TCGReg rm) 724{ 725 tcg_out_memop_r(s, cond, INSN_STRH_REG, rt, rn, rm, 1, 1, 0); 726} 727 728static void tcg_out_ld16s_8(TCGContext *s, ARMCond cond, TCGReg rt, 729 TCGReg rn, int imm8) 730{ 731 tcg_out_memop_8(s, cond, INSN_LDRSH_IMM, rt, rn, imm8, 1, 0); 732} 733 734static void tcg_out_ld16s_r(TCGContext *s, ARMCond cond, TCGReg rt, 735 TCGReg rn, TCGReg rm) 736{ 737 tcg_out_memop_r(s, cond, INSN_LDRSH_REG, rt, rn, rm, 1, 1, 0); 738} 739 740static void tcg_out_ld8_12(TCGContext *s, ARMCond cond, TCGReg rt, 741 TCGReg rn, int imm12) 742{ 743 tcg_out_memop_12(s, cond, INSN_LDRB_IMM, rt, rn, imm12, 1, 0); 744} 745 746static void tcg_out_st8_12(TCGContext *s, ARMCond cond, TCGReg rt, 747 TCGReg rn, int imm12) 748{ 749 tcg_out_memop_12(s, cond, INSN_STRB_IMM, rt, rn, imm12, 1, 0); 750} 751 752static void tcg_out_ld8_r(TCGContext *s, ARMCond cond, TCGReg rt, 753 TCGReg rn, TCGReg rm) 754{ 755 tcg_out_memop_r(s, cond, INSN_LDRB_REG, rt, rn, rm, 1, 1, 0); 756} 757 758static void tcg_out_st8_r(TCGContext *s, ARMCond cond, TCGReg rt, 759 TCGReg rn, TCGReg rm) 760{ 761 tcg_out_memop_r(s, cond, INSN_STRB_REG, rt, rn, rm, 1, 1, 0); 762} 763 764static void tcg_out_ld8s_8(TCGContext *s, ARMCond cond, TCGReg rt, 765 TCGReg rn, int imm8) 766{ 767 tcg_out_memop_8(s, cond, INSN_LDRSB_IMM, rt, rn, imm8, 1, 0); 768} 769 770static void tcg_out_ld8s_r(TCGContext *s, ARMCond cond, TCGReg rt, 771 TCGReg rn, TCGReg rm) 772{ 773 tcg_out_memop_r(s, cond, INSN_LDRSB_REG, rt, rn, rm, 1, 1, 0); 774} 775 776static void tcg_out_movi_pool(TCGContext *s, ARMCond cond, 777 TCGReg rd, uint32_t arg) 778{ 779 new_pool_label(s, arg, R_ARM_PC13, s->code_ptr, 0); 780 tcg_out_ld32_12(s, cond, rd, TCG_REG_PC, 0); 781} 782 783static void tcg_out_movi32(TCGContext *s, ARMCond cond, 784 TCGReg rd, uint32_t arg) 785{ 786 int imm12, diff, opc, sh1, sh2; 787 uint32_t tt0, tt1, tt2; 788 789 /* Check a single MOV/MVN before anything else. */ 790 imm12 = encode_imm(arg); 791 if (imm12 >= 0) { 792 tcg_out_dat_imm(s, cond, ARITH_MOV, rd, 0, imm12); 793 return; 794 } 795 imm12 = encode_imm(~arg); 796 if (imm12 >= 0) { 797 tcg_out_dat_imm(s, cond, ARITH_MVN, rd, 0, imm12); 798 return; 799 } 800 801 /* Check for a pc-relative address. This will usually be the TB, 802 or within the TB, which is immediately before the code block. */ 803 diff = tcg_pcrel_diff(s, (void *)arg) - 8; 804 if (diff >= 0) { 805 imm12 = encode_imm(diff); 806 if (imm12 >= 0) { 807 tcg_out_dat_imm(s, cond, ARITH_ADD, rd, TCG_REG_PC, imm12); 808 return; 809 } 810 } else { 811 imm12 = encode_imm(-diff); 812 if (imm12 >= 0) { 813 tcg_out_dat_imm(s, cond, ARITH_SUB, rd, TCG_REG_PC, imm12); 814 return; 815 } 816 } 817 818 /* Use movw + movt. */ 819 if (use_armv7_instructions) { 820 /* movw */ 821 tcg_out32(s, (cond << 28) | 0x03000000 | (rd << 12) 822 | ((arg << 4) & 0x000f0000) | (arg & 0xfff)); 823 if (arg & 0xffff0000) { 824 /* movt */ 825 tcg_out32(s, (cond << 28) | 0x03400000 | (rd << 12) 826 | ((arg >> 12) & 0x000f0000) | ((arg >> 16) & 0xfff)); 827 } 828 return; 829 } 830 831 /* Look for sequences of two insns. If we have lots of 1's, we can 832 shorten the sequence by beginning with mvn and then clearing 833 higher bits with eor. */ 834 tt0 = arg; 835 opc = ARITH_MOV; 836 if (ctpop32(arg) > 16) { 837 tt0 = ~arg; 838 opc = ARITH_MVN; 839 } 840 sh1 = ctz32(tt0) & ~1; 841 tt1 = tt0 & ~(0xff << sh1); 842 sh2 = ctz32(tt1) & ~1; 843 tt2 = tt1 & ~(0xff << sh2); 844 if (tt2 == 0) { 845 int rot; 846 847 rot = ((32 - sh1) << 7) & 0xf00; 848 tcg_out_dat_imm(s, cond, opc, rd, 0, ((tt0 >> sh1) & 0xff) | rot); 849 rot = ((32 - sh2) << 7) & 0xf00; 850 tcg_out_dat_imm(s, cond, ARITH_EOR, rd, rd, 851 ((tt0 >> sh2) & 0xff) | rot); 852 return; 853 } 854 855 /* Otherwise, drop it into the constant pool. */ 856 tcg_out_movi_pool(s, cond, rd, arg); 857} 858 859/* 860 * Emit either the reg,imm or reg,reg form of a data-processing insn. 861 * rhs must satisfy the "rI" constraint. 862 */ 863static void tcg_out_dat_rI(TCGContext *s, ARMCond cond, ARMInsn opc, 864 TCGReg dst, TCGReg lhs, TCGArg rhs, int rhs_is_const) 865{ 866 if (rhs_is_const) { 867 tcg_out_dat_imm(s, cond, opc, dst, lhs, encode_imm_nofail(rhs)); 868 } else { 869 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); 870 } 871} 872 873/* 874 * Emit either the reg,imm or reg,reg form of a data-processing insn. 875 * rhs must satisfy the "rIK" constraint. 876 */ 877static void tcg_out_dat_IK(TCGContext *s, ARMCond cond, ARMInsn opc, 878 ARMInsn opinv, TCGReg dst, TCGReg lhs, TCGArg rhs) 879{ 880 int imm12 = encode_imm(rhs); 881 if (imm12 < 0) { 882 imm12 = encode_imm_nofail(~rhs); 883 opc = opinv; 884 } 885 tcg_out_dat_imm(s, cond, opc, dst, lhs, imm12); 886} 887 888static void tcg_out_dat_rIK(TCGContext *s, ARMCond cond, ARMInsn opc, 889 ARMInsn opinv, TCGReg dst, TCGReg lhs, TCGArg rhs, 890 bool rhs_is_const) 891{ 892 if (rhs_is_const) { 893 tcg_out_dat_IK(s, cond, opc, opinv, dst, lhs, rhs); 894 } else { 895 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); 896 } 897} 898 899static void tcg_out_dat_IN(TCGContext *s, ARMCond cond, ARMInsn opc, 900 ARMInsn opneg, TCGReg dst, TCGReg lhs, TCGArg rhs) 901{ 902 int imm12 = encode_imm(rhs); 903 if (imm12 < 0) { 904 imm12 = encode_imm_nofail(-rhs); 905 opc = opneg; 906 } 907 tcg_out_dat_imm(s, cond, opc, dst, lhs, imm12); 908} 909 910static void tcg_out_dat_rIN(TCGContext *s, ARMCond cond, ARMInsn opc, 911 ARMInsn opneg, TCGReg dst, TCGReg lhs, TCGArg rhs, 912 bool rhs_is_const) 913{ 914 /* Emit either the reg,imm or reg,reg form of a data-processing insn. 915 * rhs must satisfy the "rIN" constraint. 916 */ 917 if (rhs_is_const) { 918 tcg_out_dat_IN(s, cond, opc, opneg, dst, lhs, rhs); 919 } else { 920 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); 921 } 922} 923 924static void tcg_out_ext8s(TCGContext *s, TCGType t, TCGReg rd, TCGReg rn) 925{ 926 /* sxtb */ 927 tcg_out32(s, 0x06af0070 | (COND_AL << 28) | (rd << 12) | rn); 928} 929 930static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rn) 931{ 932 tcg_out_dat_imm(s, COND_AL, ARITH_AND, rd, rn, 0xff); 933} 934 935static void tcg_out_ext16s(TCGContext *s, TCGType t, TCGReg rd, TCGReg rn) 936{ 937 /* sxth */ 938 tcg_out32(s, 0x06bf0070 | (COND_AL << 28) | (rd << 12) | rn); 939} 940 941static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rn) 942{ 943 /* uxth */ 944 tcg_out32(s, 0x06ff0070 | (COND_AL << 28) | (rd << 12) | rn); 945} 946 947static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rn) 948{ 949 g_assert_not_reached(); 950} 951 952static void tcg_out_ext32u(TCGContext *s, TCGReg rd, TCGReg rn) 953{ 954 g_assert_not_reached(); 955} 956 957static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rn) 958{ 959 g_assert_not_reached(); 960} 961 962static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rn) 963{ 964 g_assert_not_reached(); 965} 966 967static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rn) 968{ 969 g_assert_not_reached(); 970} 971 972static void tcg_out_bswap32(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rn) 973{ 974 /* rev */ 975 tcg_out32(s, 0x06bf0f30 | (cond << 28) | (rd << 12) | rn); 976} 977 978static void tcg_out_deposit(TCGContext *s, ARMCond cond, TCGReg rd, 979 TCGArg a1, int ofs, int len, bool const_a1) 980{ 981 if (const_a1) { 982 /* bfi becomes bfc with rn == 15. */ 983 a1 = 15; 984 } 985 /* bfi/bfc */ 986 tcg_out32(s, 0x07c00010 | (cond << 28) | (rd << 12) | a1 987 | (ofs << 7) | ((ofs + len - 1) << 16)); 988} 989 990static void tcg_out_extract(TCGContext *s, ARMCond cond, TCGReg rd, 991 TCGReg rn, int ofs, int len) 992{ 993 /* According to gcc, AND can be faster. */ 994 if (ofs == 0 && len <= 8) { 995 tcg_out_dat_imm(s, cond, ARITH_AND, rd, rn, 996 encode_imm_nofail((1 << len) - 1)); 997 return; 998 } 999 1000 if (use_armv7_instructions) { 1001 /* ubfx */ 1002 tcg_out32(s, 0x07e00050 | (cond << 28) | (rd << 12) | rn 1003 | (ofs << 7) | ((len - 1) << 16)); 1004 return; 1005 } 1006 1007 assert(ofs % 8 == 0); 1008 switch (len) { 1009 case 8: 1010 /* uxtb */ 1011 tcg_out32(s, 0x06ef0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn); 1012 break; 1013 case 16: 1014 /* uxth */ 1015 tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn); 1016 break; 1017 default: 1018 g_assert_not_reached(); 1019 } 1020} 1021 1022static void tcg_out_sextract(TCGContext *s, ARMCond cond, TCGReg rd, 1023 TCGReg rn, int ofs, int len) 1024{ 1025 if (use_armv7_instructions) { 1026 /* sbfx */ 1027 tcg_out32(s, 0x07a00050 | (cond << 28) | (rd << 12) | rn 1028 | (ofs << 7) | ((len - 1) << 16)); 1029 return; 1030 } 1031 1032 assert(ofs % 8 == 0); 1033 switch (len) { 1034 case 8: 1035 /* sxtb */ 1036 tcg_out32(s, 0x06af0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn); 1037 break; 1038 case 16: 1039 /* sxth */ 1040 tcg_out32(s, 0x06bf0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn); 1041 break; 1042 default: 1043 g_assert_not_reached(); 1044 } 1045} 1046 1047 1048static void tcg_out_ld32u(TCGContext *s, ARMCond cond, 1049 TCGReg rd, TCGReg rn, int32_t offset) 1050{ 1051 if (offset > 0xfff || offset < -0xfff) { 1052 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1053 tcg_out_ld32_r(s, cond, rd, rn, TCG_REG_TMP); 1054 } else 1055 tcg_out_ld32_12(s, cond, rd, rn, offset); 1056} 1057 1058static void tcg_out_st32(TCGContext *s, ARMCond cond, 1059 TCGReg rd, TCGReg rn, int32_t offset) 1060{ 1061 if (offset > 0xfff || offset < -0xfff) { 1062 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1063 tcg_out_st32_r(s, cond, rd, rn, TCG_REG_TMP); 1064 } else 1065 tcg_out_st32_12(s, cond, rd, rn, offset); 1066} 1067 1068static void tcg_out_ld16u(TCGContext *s, ARMCond cond, 1069 TCGReg rd, TCGReg rn, int32_t offset) 1070{ 1071 if (offset > 0xff || offset < -0xff) { 1072 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1073 tcg_out_ld16u_r(s, cond, rd, rn, TCG_REG_TMP); 1074 } else 1075 tcg_out_ld16u_8(s, cond, rd, rn, offset); 1076} 1077 1078static void tcg_out_ld16s(TCGContext *s, ARMCond cond, 1079 TCGReg rd, TCGReg rn, int32_t offset) 1080{ 1081 if (offset > 0xff || offset < -0xff) { 1082 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1083 tcg_out_ld16s_r(s, cond, rd, rn, TCG_REG_TMP); 1084 } else 1085 tcg_out_ld16s_8(s, cond, rd, rn, offset); 1086} 1087 1088static void tcg_out_st16(TCGContext *s, ARMCond cond, 1089 TCGReg rd, TCGReg rn, int32_t offset) 1090{ 1091 if (offset > 0xff || offset < -0xff) { 1092 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1093 tcg_out_st16_r(s, cond, rd, rn, TCG_REG_TMP); 1094 } else 1095 tcg_out_st16_8(s, cond, rd, rn, offset); 1096} 1097 1098static void tcg_out_ld8u(TCGContext *s, ARMCond cond, 1099 TCGReg rd, TCGReg rn, int32_t offset) 1100{ 1101 if (offset > 0xfff || offset < -0xfff) { 1102 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1103 tcg_out_ld8_r(s, cond, rd, rn, TCG_REG_TMP); 1104 } else 1105 tcg_out_ld8_12(s, cond, rd, rn, offset); 1106} 1107 1108static void tcg_out_ld8s(TCGContext *s, ARMCond cond, 1109 TCGReg rd, TCGReg rn, int32_t offset) 1110{ 1111 if (offset > 0xff || offset < -0xff) { 1112 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1113 tcg_out_ld8s_r(s, cond, rd, rn, TCG_REG_TMP); 1114 } else 1115 tcg_out_ld8s_8(s, cond, rd, rn, offset); 1116} 1117 1118static void tcg_out_st8(TCGContext *s, ARMCond cond, 1119 TCGReg rd, TCGReg rn, int32_t offset) 1120{ 1121 if (offset > 0xfff || offset < -0xfff) { 1122 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1123 tcg_out_st8_r(s, cond, rd, rn, TCG_REG_TMP); 1124 } else 1125 tcg_out_st8_12(s, cond, rd, rn, offset); 1126} 1127 1128/* 1129 * The _goto case is normally between TBs within the same code buffer, and 1130 * with the code buffer limited to 16MB we wouldn't need the long case. 1131 * But we also use it for the tail-call to the qemu_ld/st helpers, which does. 1132 */ 1133static void tcg_out_goto(TCGContext *s, ARMCond cond, const tcg_insn_unit *addr) 1134{ 1135 intptr_t addri = (intptr_t)addr; 1136 ptrdiff_t disp = tcg_pcrel_diff(s, addr); 1137 bool arm_mode = !(addri & 1); 1138 1139 if (arm_mode && disp - 8 < 0x01fffffd && disp - 8 > -0x01fffffd) { 1140 tcg_out_b_imm(s, cond, disp); 1141 return; 1142 } 1143 1144 /* LDR is interworking from v5t. */ 1145 tcg_out_movi_pool(s, cond, TCG_REG_PC, addri); 1146} 1147 1148/* 1149 * The call case is mostly used for helpers - so it's not unreasonable 1150 * for them to be beyond branch range. 1151 */ 1152static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *addr) 1153{ 1154 intptr_t addri = (intptr_t)addr; 1155 ptrdiff_t disp = tcg_pcrel_diff(s, addr); 1156 bool arm_mode = !(addri & 1); 1157 1158 if (disp - 8 < 0x02000000 && disp - 8 >= -0x02000000) { 1159 if (arm_mode) { 1160 tcg_out_bl_imm(s, COND_AL, disp); 1161 } else { 1162 tcg_out_blx_imm(s, disp); 1163 } 1164 return; 1165 } 1166 1167 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri); 1168 tcg_out_blx_reg(s, COND_AL, TCG_REG_TMP); 1169} 1170 1171static void tcg_out_call(TCGContext *s, const tcg_insn_unit *addr, 1172 const TCGHelperInfo *info) 1173{ 1174 tcg_out_call_int(s, addr); 1175} 1176 1177static void tcg_out_goto_label(TCGContext *s, ARMCond cond, TCGLabel *l) 1178{ 1179 if (l->has_value) { 1180 tcg_out_goto(s, cond, l->u.value_ptr); 1181 } else { 1182 tcg_out_reloc(s, s->code_ptr, R_ARM_PC24, l, 0); 1183 tcg_out_b_imm(s, cond, 0); 1184 } 1185} 1186 1187static void tcg_out_mb(TCGContext *s, TCGArg a0) 1188{ 1189 if (use_armv7_instructions) { 1190 tcg_out32(s, INSN_DMB_ISH); 1191 } else { 1192 tcg_out32(s, INSN_DMB_MCR); 1193 } 1194} 1195 1196static TCGCond tgen_cmp(TCGContext *s, TCGCond cond, TCGReg a, TCGReg b) 1197{ 1198 if (is_tst_cond(cond)) { 1199 tcg_out_dat_reg(s, COND_AL, ARITH_TST, 0, a, b, SHIFT_IMM_LSL(0)); 1200 return tcg_tst_eqne_cond(cond); 1201 } 1202 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, a, b, SHIFT_IMM_LSL(0)); 1203 return cond; 1204} 1205 1206static TCGCond tgen_cmpi(TCGContext *s, TCGCond cond, TCGReg a, TCGArg b) 1207{ 1208 int imm12; 1209 1210 if (!is_tst_cond(cond)) { 1211 tcg_out_dat_IN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, a, b); 1212 return cond; 1213 } 1214 1215 /* 1216 * The compare constraints allow rIN, but TST does not support N. 1217 * Be prepared to load the constant into a scratch register. 1218 */ 1219 imm12 = encode_imm(b); 1220 if (imm12 >= 0) { 1221 tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, a, imm12); 1222 } else { 1223 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, b); 1224 tcg_out_dat_reg(s, COND_AL, ARITH_TST, 0, 1225 a, TCG_REG_TMP, SHIFT_IMM_LSL(0)); 1226 } 1227 return tcg_tst_eqne_cond(cond); 1228} 1229 1230static TCGCond tcg_out_cmp(TCGContext *s, TCGCond cond, TCGReg a, 1231 TCGArg b, int b_const) 1232{ 1233 if (b_const) { 1234 return tgen_cmpi(s, cond, a, b); 1235 } else { 1236 return tgen_cmp(s, cond, a, b); 1237 } 1238} 1239 1240static TCGCond tcg_out_cmp2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, 1241 TCGArg bl, bool const_bl, TCGArg bh, bool const_bh) 1242{ 1243 switch (cond) { 1244 case TCG_COND_EQ: 1245 case TCG_COND_NE: 1246 case TCG_COND_LTU: 1247 case TCG_COND_LEU: 1248 case TCG_COND_GTU: 1249 case TCG_COND_GEU: 1250 /* 1251 * We perform a conditional comparison. If the high half is 1252 * equal, then overwrite the flags with the comparison of the 1253 * low half. The resulting flags cover the whole. 1254 */ 1255 tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, ah, bh, const_bh); 1256 tcg_out_dat_rI(s, COND_EQ, ARITH_CMP, 0, al, bl, const_bl); 1257 return cond; 1258 1259 case TCG_COND_TSTEQ: 1260 case TCG_COND_TSTNE: 1261 /* Similar, but with TST instead of CMP. */ 1262 tcg_out_dat_rI(s, COND_AL, ARITH_TST, 0, ah, bh, const_bh); 1263 tcg_out_dat_rI(s, COND_EQ, ARITH_TST, 0, al, bl, const_bl); 1264 return tcg_tst_eqne_cond(cond); 1265 1266 case TCG_COND_LT: 1267 case TCG_COND_GE: 1268 /* We perform a double-word subtraction and examine the result. 1269 We do not actually need the result of the subtract, so the 1270 low part "subtract" is a compare. For the high half we have 1271 no choice but to compute into a temporary. */ 1272 tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, al, bl, const_bl); 1273 tcg_out_dat_rI(s, COND_AL, ARITH_SBC | TO_CPSR, 1274 TCG_REG_TMP, ah, bh, const_bh); 1275 return cond; 1276 1277 case TCG_COND_LE: 1278 case TCG_COND_GT: 1279 /* Similar, but with swapped arguments, via reversed subtract. */ 1280 tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR, 1281 TCG_REG_TMP, al, bl, const_bl); 1282 tcg_out_dat_rI(s, COND_AL, ARITH_RSC | TO_CPSR, 1283 TCG_REG_TMP, ah, bh, const_bh); 1284 return tcg_swap_cond(cond); 1285 1286 default: 1287 g_assert_not_reached(); 1288 } 1289} 1290 1291/* 1292 * Note that TCGReg references Q-registers. 1293 * Q-regno = 2 * D-regno, so shift left by 1 while inserting. 1294 */ 1295static uint32_t encode_vd(TCGReg rd) 1296{ 1297 tcg_debug_assert(rd >= TCG_REG_Q0); 1298 return (extract32(rd, 3, 1) << 22) | (extract32(rd, 0, 3) << 13); 1299} 1300 1301static uint32_t encode_vn(TCGReg rn) 1302{ 1303 tcg_debug_assert(rn >= TCG_REG_Q0); 1304 return (extract32(rn, 3, 1) << 7) | (extract32(rn, 0, 3) << 17); 1305} 1306 1307static uint32_t encode_vm(TCGReg rm) 1308{ 1309 tcg_debug_assert(rm >= TCG_REG_Q0); 1310 return (extract32(rm, 3, 1) << 5) | (extract32(rm, 0, 3) << 1); 1311} 1312 1313static void tcg_out_vreg2(TCGContext *s, ARMInsn insn, int q, int vece, 1314 TCGReg d, TCGReg m) 1315{ 1316 tcg_out32(s, insn | (vece << 18) | (q << 6) | 1317 encode_vd(d) | encode_vm(m)); 1318} 1319 1320static void tcg_out_vreg3(TCGContext *s, ARMInsn insn, int q, int vece, 1321 TCGReg d, TCGReg n, TCGReg m) 1322{ 1323 tcg_out32(s, insn | (vece << 20) | (q << 6) | 1324 encode_vd(d) | encode_vn(n) | encode_vm(m)); 1325} 1326 1327static void tcg_out_vmovi(TCGContext *s, TCGReg rd, 1328 int q, int op, int cmode, uint8_t imm8) 1329{ 1330 tcg_out32(s, INSN_VMOVI | encode_vd(rd) | (q << 6) | (op << 5) 1331 | (cmode << 8) | extract32(imm8, 0, 4) 1332 | (extract32(imm8, 4, 3) << 16) 1333 | (extract32(imm8, 7, 1) << 24)); 1334} 1335 1336static void tcg_out_vshifti(TCGContext *s, ARMInsn insn, int q, 1337 TCGReg rd, TCGReg rm, int l_imm6) 1338{ 1339 tcg_out32(s, insn | (q << 6) | encode_vd(rd) | encode_vm(rm) | 1340 (extract32(l_imm6, 6, 1) << 7) | 1341 (extract32(l_imm6, 0, 6) << 16)); 1342} 1343 1344static void tcg_out_vldst(TCGContext *s, ARMInsn insn, 1345 TCGReg rd, TCGReg rn, int offset) 1346{ 1347 if (offset != 0) { 1348 if (check_fit_imm(offset) || check_fit_imm(-offset)) { 1349 tcg_out_dat_rIN(s, COND_AL, ARITH_ADD, ARITH_SUB, 1350 TCG_REG_TMP, rn, offset, true); 1351 } else { 1352 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, offset); 1353 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, 1354 TCG_REG_TMP, TCG_REG_TMP, rn, 0); 1355 } 1356 rn = TCG_REG_TMP; 1357 } 1358 tcg_out32(s, insn | (rn << 16) | encode_vd(rd) | 0xf); 1359} 1360 1361typedef struct { 1362 ARMCond cond; 1363 TCGReg base; 1364 int index; 1365 bool index_scratch; 1366 TCGAtomAlign aa; 1367} HostAddress; 1368 1369bool tcg_target_has_memory_bswap(MemOp memop) 1370{ 1371 return false; 1372} 1373 1374static TCGReg ldst_ra_gen(TCGContext *s, const TCGLabelQemuLdst *l, int arg) 1375{ 1376 /* We arrive at the slow path via "BLNE", so R14 contains l->raddr. */ 1377 return TCG_REG_R14; 1378} 1379 1380static const TCGLdstHelperParam ldst_helper_param = { 1381 .ra_gen = ldst_ra_gen, 1382 .ntmp = 1, 1383 .tmp = { TCG_REG_TMP }, 1384}; 1385 1386static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1387{ 1388 MemOp opc = get_memop(lb->oi); 1389 1390 if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1391 return false; 1392 } 1393 1394 tcg_out_ld_helper_args(s, lb, &ldst_helper_param); 1395 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE]); 1396 tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param); 1397 1398 tcg_out_goto(s, COND_AL, lb->raddr); 1399 return true; 1400} 1401 1402static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1403{ 1404 MemOp opc = get_memop(lb->oi); 1405 1406 if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1407 return false; 1408 } 1409 1410 tcg_out_st_helper_args(s, lb, &ldst_helper_param); 1411 1412 /* Tail-call to the helper, which will return to the fast path. */ 1413 tcg_out_goto(s, COND_AL, qemu_st_helpers[opc & MO_SIZE]); 1414 return true; 1415} 1416 1417/* We expect to use an 9-bit sign-magnitude negative offset from ENV. */ 1418#define MIN_TLB_MASK_TABLE_OFS -256 1419 1420static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1421 TCGReg addr, MemOpIdx oi, bool is_ld) 1422{ 1423 TCGLabelQemuLdst *ldst = NULL; 1424 MemOp opc = get_memop(oi); 1425 unsigned a_mask; 1426 1427 if (tcg_use_softmmu) { 1428 *h = (HostAddress){ 1429 .cond = COND_AL, 1430 .base = addr, 1431 .index = TCG_REG_R1, 1432 .index_scratch = true, 1433 }; 1434 } else { 1435 *h = (HostAddress){ 1436 .cond = COND_AL, 1437 .base = addr, 1438 .index = guest_base ? TCG_REG_GUEST_BASE : -1, 1439 .index_scratch = false, 1440 }; 1441 } 1442 1443 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); 1444 a_mask = (1 << h->aa.align) - 1; 1445 1446 if (tcg_use_softmmu) { 1447 int mem_index = get_mmuidx(oi); 1448 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read) 1449 : offsetof(CPUTLBEntry, addr_write); 1450 int fast_off = tlb_mask_table_ofs(s, mem_index); 1451 unsigned s_mask = (1 << (opc & MO_SIZE)) - 1; 1452 TCGReg t_addr; 1453 1454 ldst = new_ldst_label(s); 1455 ldst->is_ld = is_ld; 1456 ldst->oi = oi; 1457 ldst->addr_reg = addr; 1458 1459 /* Load cpu->neg.tlb.f[mmu_idx].{mask,table} into {r0,r1}. */ 1460 QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0); 1461 QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != 4); 1462 tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off); 1463 1464 /* Extract the tlb index from the address into R0. */ 1465 tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, addr, 1466 SHIFT_IMM_LSR(s->page_bits - CPU_TLB_ENTRY_BITS)); 1467 1468 /* 1469 * Add the tlb_table pointer, creating the CPUTLBEntry address in R1. 1470 * Load the tlb comparator into R2 and the fast path addend into R1. 1471 */ 1472 if (cmp_off == 0) { 1473 tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0); 1474 } else { 1475 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, 1476 TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0); 1477 tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); 1478 } 1479 1480 /* Load the tlb addend. */ 1481 tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R1, 1482 offsetof(CPUTLBEntry, addend)); 1483 1484 /* 1485 * Check alignment, check comparators. 1486 * Do this in 2-4 insns. Use MOVW for v7, if possible, 1487 * to reduce the number of sequential conditional instructions. 1488 * Almost all guests have at least 4k pages, which means that we need 1489 * to clear at least 9 bits even for an 8-byte memory, which means it 1490 * isn't worth checking for an immediate operand for BIC. 1491 * 1492 * For unaligned accesses, test the page of the last unit of alignment. 1493 * This leaves the least significant alignment bits unchanged, and of 1494 * course must be zero. 1495 */ 1496 t_addr = addr; 1497 if (a_mask < s_mask) { 1498 t_addr = TCG_REG_R0; 1499 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, t_addr, 1500 addr, s_mask - a_mask); 1501 } 1502 if (use_armv7_instructions && s->page_bits <= 16) { 1503 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, ~(s->page_mask | a_mask)); 1504 tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP, 1505 t_addr, TCG_REG_TMP, 0); 1506 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, 1507 TCG_REG_R2, TCG_REG_TMP, 0); 1508 } else { 1509 if (a_mask) { 1510 tcg_debug_assert(a_mask <= 0xff); 1511 tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addr, a_mask); 1512 } 1513 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, t_addr, 1514 SHIFT_IMM_LSR(s->page_bits)); 1515 tcg_out_dat_reg(s, (a_mask ? COND_EQ : COND_AL), ARITH_CMP, 1516 0, TCG_REG_R2, TCG_REG_TMP, 1517 SHIFT_IMM_LSL(s->page_bits)); 1518 } 1519 } else if (a_mask) { 1520 ldst = new_ldst_label(s); 1521 ldst->is_ld = is_ld; 1522 ldst->oi = oi; 1523 ldst->addr_reg = addr; 1524 1525 /* We are expecting alignment to max out at 7 */ 1526 tcg_debug_assert(a_mask <= 0xff); 1527 /* tst addr, #mask */ 1528 tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addr, a_mask); 1529 } 1530 1531 return ldst; 1532} 1533 1534static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo, 1535 TCGReg datahi, HostAddress h) 1536{ 1537 TCGReg base; 1538 1539 /* Byte swapping is left to middle-end expansion. */ 1540 tcg_debug_assert((opc & MO_BSWAP) == 0); 1541 1542 switch (opc & MO_SSIZE) { 1543 case MO_UB: 1544 if (h.index < 0) { 1545 tcg_out_ld8_12(s, h.cond, datalo, h.base, 0); 1546 } else { 1547 tcg_out_ld8_r(s, h.cond, datalo, h.base, h.index); 1548 } 1549 break; 1550 case MO_SB: 1551 if (h.index < 0) { 1552 tcg_out_ld8s_8(s, h.cond, datalo, h.base, 0); 1553 } else { 1554 tcg_out_ld8s_r(s, h.cond, datalo, h.base, h.index); 1555 } 1556 break; 1557 case MO_UW: 1558 if (h.index < 0) { 1559 tcg_out_ld16u_8(s, h.cond, datalo, h.base, 0); 1560 } else { 1561 tcg_out_ld16u_r(s, h.cond, datalo, h.base, h.index); 1562 } 1563 break; 1564 case MO_SW: 1565 if (h.index < 0) { 1566 tcg_out_ld16s_8(s, h.cond, datalo, h.base, 0); 1567 } else { 1568 tcg_out_ld16s_r(s, h.cond, datalo, h.base, h.index); 1569 } 1570 break; 1571 case MO_UL: 1572 if (h.index < 0) { 1573 tcg_out_ld32_12(s, h.cond, datalo, h.base, 0); 1574 } else { 1575 tcg_out_ld32_r(s, h.cond, datalo, h.base, h.index); 1576 } 1577 break; 1578 case MO_UQ: 1579 /* We used pair allocation for datalo, so already should be aligned. */ 1580 tcg_debug_assert((datalo & 1) == 0); 1581 tcg_debug_assert(datahi == datalo + 1); 1582 /* LDRD requires alignment; double-check that. */ 1583 if (memop_alignment_bits(opc) >= MO_64) { 1584 if (h.index < 0) { 1585 tcg_out_ldrd_8(s, h.cond, datalo, h.base, 0); 1586 break; 1587 } 1588 /* 1589 * Rm (the second address op) must not overlap Rt or Rt + 1. 1590 * Since datalo is aligned, we can simplify the test via alignment. 1591 * Flip the two address arguments if that works. 1592 */ 1593 if ((h.index & ~1) != datalo) { 1594 tcg_out_ldrd_r(s, h.cond, datalo, h.base, h.index); 1595 break; 1596 } 1597 if ((h.base & ~1) != datalo) { 1598 tcg_out_ldrd_r(s, h.cond, datalo, h.index, h.base); 1599 break; 1600 } 1601 } 1602 if (h.index < 0) { 1603 base = h.base; 1604 if (datalo == h.base) { 1605 tcg_out_mov_reg(s, h.cond, TCG_REG_TMP, base); 1606 base = TCG_REG_TMP; 1607 } 1608 } else if (h.index_scratch) { 1609 tcg_out_ld32_rwb(s, h.cond, datalo, h.index, h.base); 1610 tcg_out_ld32_12(s, h.cond, datahi, h.index, 4); 1611 break; 1612 } else { 1613 tcg_out_dat_reg(s, h.cond, ARITH_ADD, TCG_REG_TMP, 1614 h.base, h.index, SHIFT_IMM_LSL(0)); 1615 base = TCG_REG_TMP; 1616 } 1617 tcg_out_ld32_12(s, h.cond, datalo, base, 0); 1618 tcg_out_ld32_12(s, h.cond, datahi, base, 4); 1619 break; 1620 default: 1621 g_assert_not_reached(); 1622 } 1623} 1624 1625static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, 1626 TCGReg addr, MemOpIdx oi, TCGType data_type) 1627{ 1628 MemOp opc = get_memop(oi); 1629 TCGLabelQemuLdst *ldst; 1630 HostAddress h; 1631 1632 ldst = prepare_host_addr(s, &h, addr, oi, true); 1633 if (ldst) { 1634 ldst->type = data_type; 1635 ldst->datalo_reg = datalo; 1636 ldst->datahi_reg = datahi; 1637 1638 /* 1639 * This a conditional BL only to load a pointer within this 1640 * opcode into LR for the slow path. We will not be using 1641 * the value for a tail call. 1642 */ 1643 ldst->label_ptr[0] = s->code_ptr; 1644 tcg_out_bl_imm(s, COND_NE, 0); 1645 1646 tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); 1647 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1648 } else { 1649 tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); 1650 } 1651} 1652 1653static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo, 1654 TCGReg datahi, HostAddress h) 1655{ 1656 /* Byte swapping is left to middle-end expansion. */ 1657 tcg_debug_assert((opc & MO_BSWAP) == 0); 1658 1659 switch (opc & MO_SIZE) { 1660 case MO_8: 1661 if (h.index < 0) { 1662 tcg_out_st8_12(s, h.cond, datalo, h.base, 0); 1663 } else { 1664 tcg_out_st8_r(s, h.cond, datalo, h.base, h.index); 1665 } 1666 break; 1667 case MO_16: 1668 if (h.index < 0) { 1669 tcg_out_st16_8(s, h.cond, datalo, h.base, 0); 1670 } else { 1671 tcg_out_st16_r(s, h.cond, datalo, h.base, h.index); 1672 } 1673 break; 1674 case MO_32: 1675 if (h.index < 0) { 1676 tcg_out_st32_12(s, h.cond, datalo, h.base, 0); 1677 } else { 1678 tcg_out_st32_r(s, h.cond, datalo, h.base, h.index); 1679 } 1680 break; 1681 case MO_64: 1682 /* We used pair allocation for datalo, so already should be aligned. */ 1683 tcg_debug_assert((datalo & 1) == 0); 1684 tcg_debug_assert(datahi == datalo + 1); 1685 /* STRD requires alignment; double-check that. */ 1686 if (memop_alignment_bits(opc) >= MO_64) { 1687 if (h.index < 0) { 1688 tcg_out_strd_8(s, h.cond, datalo, h.base, 0); 1689 } else { 1690 tcg_out_strd_r(s, h.cond, datalo, h.base, h.index); 1691 } 1692 } else if (h.index < 0) { 1693 tcg_out_st32_12(s, h.cond, datalo, h.base, 0); 1694 tcg_out_st32_12(s, h.cond, datahi, h.base, 4); 1695 } else if (h.index_scratch) { 1696 tcg_out_st32_rwb(s, h.cond, datalo, h.index, h.base); 1697 tcg_out_st32_12(s, h.cond, datahi, h.index, 4); 1698 } else { 1699 tcg_out_dat_reg(s, h.cond, ARITH_ADD, TCG_REG_TMP, 1700 h.base, h.index, SHIFT_IMM_LSL(0)); 1701 tcg_out_st32_12(s, h.cond, datalo, TCG_REG_TMP, 0); 1702 tcg_out_st32_12(s, h.cond, datahi, TCG_REG_TMP, 4); 1703 } 1704 break; 1705 default: 1706 g_assert_not_reached(); 1707 } 1708} 1709 1710static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, 1711 TCGReg addr, MemOpIdx oi, TCGType data_type) 1712{ 1713 MemOp opc = get_memop(oi); 1714 TCGLabelQemuLdst *ldst; 1715 HostAddress h; 1716 1717 ldst = prepare_host_addr(s, &h, addr, oi, false); 1718 if (ldst) { 1719 ldst->type = data_type; 1720 ldst->datalo_reg = datalo; 1721 ldst->datahi_reg = datahi; 1722 1723 h.cond = COND_EQ; 1724 tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); 1725 1726 /* The conditional call is last, as we're going to return here. */ 1727 ldst->label_ptr[0] = s->code_ptr; 1728 tcg_out_bl_imm(s, COND_NE, 0); 1729 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1730 } else { 1731 tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); 1732 } 1733} 1734 1735static void tcg_out_epilogue(TCGContext *s); 1736 1737static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg) 1738{ 1739 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, arg); 1740 tcg_out_epilogue(s); 1741} 1742 1743static void tcg_out_goto_tb(TCGContext *s, int which) 1744{ 1745 uintptr_t i_addr; 1746 intptr_t i_disp; 1747 1748 /* Direct branch will be patched by tb_target_set_jmp_target. */ 1749 set_jmp_insn_offset(s, which); 1750 tcg_out32(s, INSN_NOP); 1751 1752 /* When branch is out of range, fall through to indirect. */ 1753 i_addr = get_jmp_target_addr(s, which); 1754 i_disp = tcg_pcrel_diff(s, (void *)i_addr) - 8; 1755 tcg_debug_assert(i_disp < 0); 1756 if (i_disp >= -0xfff) { 1757 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, i_disp); 1758 } else { 1759 /* 1760 * The TB is close, but outside the 12 bits addressable by 1761 * the load. We can extend this to 20 bits with a sub of a 1762 * shifted immediate from pc. 1763 */ 1764 int h = -i_disp; 1765 int l = -(h & 0xfff); 1766 1767 h = encode_imm_nofail(h + l); 1768 tcg_out_dat_imm(s, COND_AL, ARITH_SUB, TCG_REG_R0, TCG_REG_PC, h); 1769 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_R0, l); 1770 } 1771 set_jmp_reset_offset(s, which); 1772} 1773 1774void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1775 uintptr_t jmp_rx, uintptr_t jmp_rw) 1776{ 1777 uintptr_t addr = tb->jmp_target_addr[n]; 1778 ptrdiff_t offset = addr - (jmp_rx + 8); 1779 tcg_insn_unit insn; 1780 1781 /* Either directly branch, or fall through to indirect branch. */ 1782 if (offset == sextract64(offset, 0, 26)) { 1783 /* B <addr> */ 1784 insn = deposit32((COND_AL << 28) | INSN_B, 0, 24, offset >> 2); 1785 } else { 1786 insn = INSN_NOP; 1787 } 1788 1789 qatomic_set((uint32_t *)jmp_rw, insn); 1790 flush_idcache_range(jmp_rx, jmp_rw, 4); 1791} 1792 1793 1794static void tgen_add(TCGContext *s, TCGType type, 1795 TCGReg a0, TCGReg a1, TCGReg a2) 1796{ 1797 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, a0, a1, a2, SHIFT_IMM_LSL(0)); 1798} 1799 1800static void tgen_addi(TCGContext *s, TCGType type, 1801 TCGReg a0, TCGReg a1, tcg_target_long a2) 1802{ 1803 tcg_out_dat_IN(s, COND_AL, ARITH_ADD, ARITH_SUB, a0, a1, a2); 1804} 1805 1806static const TCGOutOpBinary outop_add = { 1807 .base.static_constraint = C_O1_I2(r, r, rIN), 1808 .out_rrr = tgen_add, 1809 .out_rri = tgen_addi, 1810}; 1811 1812static void tgen_and(TCGContext *s, TCGType type, 1813 TCGReg a0, TCGReg a1, TCGReg a2) 1814{ 1815 tcg_out_dat_reg(s, COND_AL, ARITH_AND, a0, a1, a2, SHIFT_IMM_LSL(0)); 1816} 1817 1818static void tgen_andi(TCGContext *s, TCGType type, 1819 TCGReg a0, TCGReg a1, tcg_target_long a2) 1820{ 1821 tcg_out_dat_IK(s, COND_AL, ARITH_AND, ARITH_BIC, a0, a1, a2); 1822} 1823 1824static const TCGOutOpBinary outop_and = { 1825 .base.static_constraint = C_O1_I2(r, r, rIK), 1826 .out_rrr = tgen_and, 1827 .out_rri = tgen_andi, 1828}; 1829 1830static void tgen_andc(TCGContext *s, TCGType type, 1831 TCGReg a0, TCGReg a1, TCGReg a2) 1832{ 1833 tcg_out_dat_reg(s, COND_AL, ARITH_BIC, a0, a1, a2, SHIFT_IMM_LSL(0)); 1834} 1835 1836static const TCGOutOpBinary outop_andc = { 1837 .base.static_constraint = C_O1_I2(r, r, r), 1838 .out_rrr = tgen_andc, 1839}; 1840 1841static void tgen_clz(TCGContext *s, TCGType type, 1842 TCGReg a0, TCGReg a1, TCGReg a2) 1843{ 1844 tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0, a1, 0); 1845 tcg_out_dat_reg(s, COND_NE, INSN_CLZ, a0, 0, a1, 0); 1846 tcg_out_mov_reg(s, COND_EQ, a0, a2); 1847} 1848 1849static void tgen_clzi(TCGContext *s, TCGType type, 1850 TCGReg a0, TCGReg a1, tcg_target_long a2) 1851{ 1852 if (a2 == 32) { 1853 tcg_out_dat_reg(s, COND_AL, INSN_CLZ, a0, 0, a1, 0); 1854 } else { 1855 tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0, a1, 0); 1856 tcg_out_dat_reg(s, COND_NE, INSN_CLZ, a0, 0, a1, 0); 1857 tcg_out_movi32(s, COND_EQ, a0, a2); 1858 } 1859} 1860 1861static const TCGOutOpBinary outop_clz = { 1862 .base.static_constraint = C_O1_I2(r, r, rIK), 1863 .out_rrr = tgen_clz, 1864 .out_rri = tgen_clzi, 1865}; 1866 1867static const TCGOutOpUnary outop_ctpop = { 1868 .base.static_constraint = C_NotImplemented, 1869}; 1870 1871static void tgen_ctz(TCGContext *s, TCGType type, 1872 TCGReg a0, TCGReg a1, TCGReg a2) 1873{ 1874 tcg_out_dat_reg(s, COND_AL, INSN_RBIT, TCG_REG_TMP, 0, a1, 0); 1875 tgen_clz(s, TCG_TYPE_I32, a0, TCG_REG_TMP, a2); 1876} 1877 1878static void tgen_ctzi(TCGContext *s, TCGType type, 1879 TCGReg a0, TCGReg a1, tcg_target_long a2) 1880{ 1881 tcg_out_dat_reg(s, COND_AL, INSN_RBIT, TCG_REG_TMP, 0, a1, 0); 1882 tgen_clzi(s, TCG_TYPE_I32, a0, TCG_REG_TMP, a2); 1883} 1884 1885static TCGConstraintSetIndex cset_ctz(TCGType type, unsigned flags) 1886{ 1887 return use_armv7_instructions ? C_O1_I2(r, r, rIK) : C_NotImplemented; 1888} 1889 1890static const TCGOutOpBinary outop_ctz = { 1891 .base.static_constraint = C_Dynamic, 1892 .base.dynamic_constraint = cset_ctz, 1893 .out_rrr = tgen_ctz, 1894 .out_rri = tgen_ctzi, 1895}; 1896 1897static TCGConstraintSetIndex cset_idiv(TCGType type, unsigned flags) 1898{ 1899 return use_idiv_instructions ? C_O1_I2(r, r, r) : C_NotImplemented; 1900} 1901 1902static void tgen_divs(TCGContext *s, TCGType type, 1903 TCGReg a0, TCGReg a1, TCGReg a2) 1904{ 1905 /* sdiv */ 1906 tcg_out32(s, 0x0710f010 | (COND_AL << 28) | (a0 << 16) | a1 | (a2 << 8)); 1907} 1908 1909static const TCGOutOpBinary outop_divs = { 1910 .base.static_constraint = C_Dynamic, 1911 .base.dynamic_constraint = cset_idiv, 1912 .out_rrr = tgen_divs, 1913}; 1914 1915static const TCGOutOpDivRem outop_divs2 = { 1916 .base.static_constraint = C_NotImplemented, 1917}; 1918 1919static void tgen_divu(TCGContext *s, TCGType type, 1920 TCGReg a0, TCGReg a1, TCGReg a2) 1921{ 1922 /* udiv */ 1923 tcg_out32(s, 0x0730f010 | (COND_AL << 28) | (a0 << 16) | a1 | (a2 << 8)); 1924} 1925 1926static const TCGOutOpBinary outop_divu = { 1927 .base.static_constraint = C_Dynamic, 1928 .base.dynamic_constraint = cset_idiv, 1929 .out_rrr = tgen_divu, 1930}; 1931 1932static const TCGOutOpDivRem outop_divu2 = { 1933 .base.static_constraint = C_NotImplemented, 1934}; 1935 1936static const TCGOutOpBinary outop_eqv = { 1937 .base.static_constraint = C_NotImplemented, 1938}; 1939 1940static void tgen_mul(TCGContext *s, TCGType type, 1941 TCGReg a0, TCGReg a1, TCGReg a2) 1942{ 1943 /* mul */ 1944 tcg_out32(s, (COND_AL << 28) | 0x90 | (a0 << 16) | (a1 << 8) | a2); 1945} 1946 1947static const TCGOutOpBinary outop_mul = { 1948 .base.static_constraint = C_O1_I2(r, r, r), 1949 .out_rrr = tgen_mul, 1950}; 1951 1952static void tgen_muls2(TCGContext *s, TCGType type, 1953 TCGReg rd0, TCGReg rd1, TCGReg rn, TCGReg rm) 1954{ 1955 /* smull */ 1956 tcg_out32(s, (COND_AL << 28) | 0x00c00090 | 1957 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); 1958} 1959 1960static const TCGOutOpMul2 outop_muls2 = { 1961 .base.static_constraint = C_O2_I2(r, r, r, r), 1962 .out_rrrr = tgen_muls2, 1963}; 1964 1965static const TCGOutOpBinary outop_mulsh = { 1966 .base.static_constraint = C_NotImplemented, 1967}; 1968 1969static void tgen_mulu2(TCGContext *s, TCGType type, 1970 TCGReg rd0, TCGReg rd1, TCGReg rn, TCGReg rm) 1971{ 1972 /* umull */ 1973 tcg_out32(s, (COND_AL << 28) | 0x00800090 | 1974 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); 1975} 1976 1977static const TCGOutOpMul2 outop_mulu2 = { 1978 .base.static_constraint = C_O2_I2(r, r, r, r), 1979 .out_rrrr = tgen_mulu2, 1980}; 1981 1982static const TCGOutOpBinary outop_muluh = { 1983 .base.static_constraint = C_NotImplemented, 1984}; 1985 1986static const TCGOutOpBinary outop_nand = { 1987 .base.static_constraint = C_NotImplemented, 1988}; 1989 1990static const TCGOutOpBinary outop_nor = { 1991 .base.static_constraint = C_NotImplemented, 1992}; 1993 1994static void tgen_or(TCGContext *s, TCGType type, 1995 TCGReg a0, TCGReg a1, TCGReg a2) 1996{ 1997 tcg_out_dat_reg(s, COND_AL, ARITH_ORR, a0, a1, a2, SHIFT_IMM_LSL(0)); 1998} 1999 2000static void tgen_ori(TCGContext *s, TCGType type, 2001 TCGReg a0, TCGReg a1, tcg_target_long a2) 2002{ 2003 tcg_out_dat_imm(s, COND_AL, ARITH_ORR, a0, a1, encode_imm_nofail(a2)); 2004} 2005 2006static const TCGOutOpBinary outop_or = { 2007 .base.static_constraint = C_O1_I2(r, r, rI), 2008 .out_rrr = tgen_or, 2009 .out_rri = tgen_ori, 2010}; 2011 2012static const TCGOutOpBinary outop_orc = { 2013 .base.static_constraint = C_NotImplemented, 2014}; 2015 2016static const TCGOutOpBinary outop_rems = { 2017 .base.static_constraint = C_NotImplemented, 2018}; 2019 2020static const TCGOutOpBinary outop_remu = { 2021 .base.static_constraint = C_NotImplemented, 2022}; 2023 2024static const TCGOutOpBinary outop_rotl = { 2025 .base.static_constraint = C_NotImplemented, 2026}; 2027 2028static void tgen_rotr(TCGContext *s, TCGType type, 2029 TCGReg a0, TCGReg a1, TCGReg a2) 2030{ 2031 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, SHIFT_REG_ROR(a2)); 2032} 2033 2034static void tgen_rotri(TCGContext *s, TCGType type, 2035 TCGReg a0, TCGReg a1, tcg_target_long a2) 2036{ 2037 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, SHIFT_IMM_ROR(a2 & 0x1f)); 2038} 2039 2040static const TCGOutOpBinary outop_rotr = { 2041 .base.static_constraint = C_O1_I2(r, r, ri), 2042 .out_rrr = tgen_rotr, 2043 .out_rri = tgen_rotri, 2044}; 2045 2046static void tgen_sar(TCGContext *s, TCGType type, 2047 TCGReg a0, TCGReg a1, TCGReg a2) 2048{ 2049 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, SHIFT_REG_ASR(a2)); 2050} 2051 2052static void tgen_sari(TCGContext *s, TCGType type, 2053 TCGReg a0, TCGReg a1, tcg_target_long a2) 2054{ 2055 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, 2056 SHIFT_IMM_ASR(a2 & 0x1f)); 2057} 2058 2059static const TCGOutOpBinary outop_sar = { 2060 .base.static_constraint = C_O1_I2(r, r, ri), 2061 .out_rrr = tgen_sar, 2062 .out_rri = tgen_sari, 2063}; 2064 2065static void tgen_shl(TCGContext *s, TCGType type, 2066 TCGReg a0, TCGReg a1, TCGReg a2) 2067{ 2068 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, SHIFT_REG_LSL(a2)); 2069} 2070 2071static void tgen_shli(TCGContext *s, TCGType type, 2072 TCGReg a0, TCGReg a1, tcg_target_long a2) 2073{ 2074 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, 2075 SHIFT_IMM_LSL(a2 & 0x1f)); 2076} 2077 2078static const TCGOutOpBinary outop_shl = { 2079 .base.static_constraint = C_O1_I2(r, r, ri), 2080 .out_rrr = tgen_shl, 2081 .out_rri = tgen_shli, 2082}; 2083 2084static void tgen_shr(TCGContext *s, TCGType type, 2085 TCGReg a0, TCGReg a1, TCGReg a2) 2086{ 2087 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, SHIFT_REG_LSR(a2)); 2088} 2089 2090static void tgen_shri(TCGContext *s, TCGType type, 2091 TCGReg a0, TCGReg a1, tcg_target_long a2) 2092{ 2093 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, 2094 SHIFT_IMM_LSR(a2 & 0x1f)); 2095} 2096 2097static const TCGOutOpBinary outop_shr = { 2098 .base.static_constraint = C_O1_I2(r, r, ri), 2099 .out_rrr = tgen_shr, 2100 .out_rri = tgen_shri, 2101}; 2102 2103static void tgen_sub(TCGContext *s, TCGType type, 2104 TCGReg a0, TCGReg a1, TCGReg a2) 2105{ 2106 tcg_out_dat_reg(s, COND_AL, ARITH_SUB, a0, a1, a2, SHIFT_IMM_LSL(0)); 2107} 2108 2109static void tgen_subfi(TCGContext *s, TCGType type, 2110 TCGReg a0, tcg_target_long a1, TCGReg a2) 2111{ 2112 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, a0, a2, encode_imm_nofail(a1)); 2113} 2114 2115static const TCGOutOpSubtract outop_sub = { 2116 .base.static_constraint = C_O1_I2(r, rI, r), 2117 .out_rrr = tgen_sub, 2118 .out_rir = tgen_subfi, 2119}; 2120 2121static void tgen_xor(TCGContext *s, TCGType type, 2122 TCGReg a0, TCGReg a1, TCGReg a2) 2123{ 2124 tcg_out_dat_reg(s, COND_AL, ARITH_EOR, a0, a1, a2, SHIFT_IMM_LSL(0)); 2125} 2126 2127static void tgen_xori(TCGContext *s, TCGType type, 2128 TCGReg a0, TCGReg a1, tcg_target_long a2) 2129{ 2130 tcg_out_dat_imm(s, COND_AL, ARITH_EOR, a0, a1, encode_imm_nofail(a2)); 2131} 2132 2133static const TCGOutOpBinary outop_xor = { 2134 .base.static_constraint = C_O1_I2(r, r, rI), 2135 .out_rrr = tgen_xor, 2136 .out_rri = tgen_xori, 2137}; 2138 2139static void tgen_bswap16(TCGContext *s, TCGType type, 2140 TCGReg rd, TCGReg rn, unsigned flags) 2141{ 2142 if (flags & TCG_BSWAP_OS) { 2143 /* revsh */ 2144 tcg_out32(s, 0x06ff0fb0 | (COND_AL << 28) | (rd << 12) | rn); 2145 return; 2146 } 2147 2148 /* rev16 */ 2149 tcg_out32(s, 0x06bf0fb0 | (COND_AL << 28) | (rd << 12) | rn); 2150 if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 2151 tcg_out_ext16u(s, rd, rd); 2152 } 2153} 2154 2155static const TCGOutOpBswap outop_bswap16 = { 2156 .base.static_constraint = C_O1_I1(r, r), 2157 .out_rr = tgen_bswap16, 2158}; 2159 2160static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2161{ 2162 tgen_subfi(s, type, a0, 0, a1); 2163} 2164 2165static const TCGOutOpUnary outop_neg = { 2166 .base.static_constraint = C_O1_I1(r, r), 2167 .out_rr = tgen_neg, 2168}; 2169 2170static void tgen_not(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2171{ 2172 tcg_out_dat_reg(s, COND_AL, ARITH_MVN, a0, 0, a1, SHIFT_IMM_LSL(0)); 2173} 2174 2175static const TCGOutOpUnary outop_not = { 2176 .base.static_constraint = C_O1_I1(r, r), 2177 .out_rr = tgen_not, 2178}; 2179 2180static void tgen_brcond(TCGContext *s, TCGType type, TCGCond cond, 2181 TCGReg a0, TCGReg a1, TCGLabel *l) 2182{ 2183 cond = tgen_cmp(s, cond, a0, a1); 2184 tcg_out_goto_label(s, tcg_cond_to_arm_cond[cond], l); 2185} 2186 2187static void tgen_brcondi(TCGContext *s, TCGType type, TCGCond cond, 2188 TCGReg a0, tcg_target_long a1, TCGLabel *l) 2189{ 2190 cond = tgen_cmpi(s, cond, a0, a1); 2191 tcg_out_goto_label(s, tcg_cond_to_arm_cond[cond], l); 2192} 2193 2194static const TCGOutOpBrcond outop_brcond = { 2195 .base.static_constraint = C_O0_I2(r, rIN), 2196 .out_rr = tgen_brcond, 2197 .out_ri = tgen_brcondi, 2198}; 2199 2200static void finish_setcond(TCGContext *s, TCGCond cond, TCGReg ret, bool neg) 2201{ 2202 tcg_out_movi32(s, tcg_cond_to_arm_cond[tcg_invert_cond(cond)], ret, 0); 2203 tcg_out_movi32(s, tcg_cond_to_arm_cond[cond], ret, neg ? -1 : 1); 2204} 2205 2206static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, 2207 TCGReg a0, TCGReg a1, TCGReg a2) 2208{ 2209 cond = tgen_cmp(s, cond, a1, a2); 2210 finish_setcond(s, cond, a0, false); 2211} 2212 2213static void tgen_setcondi(TCGContext *s, TCGType type, TCGCond cond, 2214 TCGReg a0, TCGReg a1, tcg_target_long a2) 2215{ 2216 cond = tgen_cmpi(s, cond, a1, a2); 2217 finish_setcond(s, cond, a0, false); 2218} 2219 2220static const TCGOutOpSetcond outop_setcond = { 2221 .base.static_constraint = C_O1_I2(r, r, rIN), 2222 .out_rrr = tgen_setcond, 2223 .out_rri = tgen_setcondi, 2224}; 2225 2226static void tgen_negsetcond(TCGContext *s, TCGType type, TCGCond cond, 2227 TCGReg a0, TCGReg a1, TCGReg a2) 2228{ 2229 cond = tgen_cmp(s, cond, a1, a2); 2230 finish_setcond(s, cond, a0, true); 2231} 2232 2233static void tgen_negsetcondi(TCGContext *s, TCGType type, TCGCond cond, 2234 TCGReg a0, TCGReg a1, tcg_target_long a2) 2235{ 2236 cond = tgen_cmpi(s, cond, a1, a2); 2237 finish_setcond(s, cond, a0, true); 2238} 2239 2240static const TCGOutOpSetcond outop_negsetcond = { 2241 .base.static_constraint = C_O1_I2(r, r, rIN), 2242 .out_rrr = tgen_negsetcond, 2243 .out_rri = tgen_negsetcondi, 2244}; 2245 2246static void tgen_movcond(TCGContext *s, TCGType type, TCGCond cond, 2247 TCGReg ret, TCGReg c1, TCGArg c2, bool const_c2, 2248 TCGArg vt, bool const_vt, TCGArg vf, bool consf_vf) 2249{ 2250 cond = tcg_out_cmp(s, cond, c1, c2, const_c2); 2251 tcg_out_dat_rIK(s, tcg_cond_to_arm_cond[cond], ARITH_MOV, ARITH_MVN, 2252 ret, 0, vt, const_vt); 2253} 2254 2255static const TCGOutOpMovcond outop_movcond = { 2256 .base.static_constraint = C_O1_I4(r, r, rIN, rIK, 0), 2257 .out = tgen_movcond, 2258}; 2259 2260static void tgen_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, 2261 TCGArg bl, bool const_bl, TCGArg bh, bool const_bh, 2262 TCGLabel *l) 2263{ 2264 cond = tcg_out_cmp2(s, cond, al, ah, bl, const_bl, bh, const_bh); 2265 tcg_out_goto_label(s, tcg_cond_to_arm_cond[cond], l); 2266} 2267 2268static const TCGOutOpBrcond2 outop_brcond2 = { 2269 .base.static_constraint = C_O0_I4(r, r, rI, rI), 2270 .out = tgen_brcond2, 2271}; 2272 2273static void tgen_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, 2274 TCGReg al, TCGReg ah, 2275 TCGArg bl, bool const_bl, 2276 TCGArg bh, bool const_bh) 2277{ 2278 cond = tcg_out_cmp2(s, cond, al, ah, bl, const_bl, bh, const_bh); 2279 finish_setcond(s, cond, ret, false); 2280} 2281 2282static const TCGOutOpSetcond2 outop_setcond2 = { 2283 .base.static_constraint = C_O1_I4(r, r, r, rI, rI), 2284 .out = tgen_setcond2, 2285}; 2286 2287static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, 2288 const TCGArg args[TCG_MAX_OP_ARGS], 2289 const int const_args[TCG_MAX_OP_ARGS]) 2290{ 2291 TCGArg a0, a1, a2, a3, a4, a5; 2292 2293 switch (opc) { 2294 case INDEX_op_goto_ptr: 2295 tcg_out_b_reg(s, COND_AL, args[0]); 2296 break; 2297 case INDEX_op_br: 2298 tcg_out_goto_label(s, COND_AL, arg_label(args[0])); 2299 break; 2300 2301 case INDEX_op_ld8u_i32: 2302 tcg_out_ld8u(s, COND_AL, args[0], args[1], args[2]); 2303 break; 2304 case INDEX_op_ld8s_i32: 2305 tcg_out_ld8s(s, COND_AL, args[0], args[1], args[2]); 2306 break; 2307 case INDEX_op_ld16u_i32: 2308 tcg_out_ld16u(s, COND_AL, args[0], args[1], args[2]); 2309 break; 2310 case INDEX_op_ld16s_i32: 2311 tcg_out_ld16s(s, COND_AL, args[0], args[1], args[2]); 2312 break; 2313 case INDEX_op_ld_i32: 2314 tcg_out_ld32u(s, COND_AL, args[0], args[1], args[2]); 2315 break; 2316 case INDEX_op_st8_i32: 2317 tcg_out_st8(s, COND_AL, args[0], args[1], args[2]); 2318 break; 2319 case INDEX_op_st16_i32: 2320 tcg_out_st16(s, COND_AL, args[0], args[1], args[2]); 2321 break; 2322 case INDEX_op_st_i32: 2323 tcg_out_st32(s, COND_AL, args[0], args[1], args[2]); 2324 break; 2325 2326 case INDEX_op_add2_i32: 2327 a0 = args[0], a1 = args[1], a2 = args[2]; 2328 a3 = args[3], a4 = args[4], a5 = args[5]; 2329 if (a0 == a3 || (a0 == a5 && !const_args[5])) { 2330 a0 = TCG_REG_TMP; 2331 } 2332 tcg_out_dat_rIN(s, COND_AL, ARITH_ADD | TO_CPSR, ARITH_SUB | TO_CPSR, 2333 a0, a2, a4, const_args[4]); 2334 tcg_out_dat_rIK(s, COND_AL, ARITH_ADC, ARITH_SBC, 2335 a1, a3, a5, const_args[5]); 2336 tcg_out_mov_reg(s, COND_AL, args[0], a0); 2337 break; 2338 case INDEX_op_sub2_i32: 2339 a0 = args[0], a1 = args[1], a2 = args[2]; 2340 a3 = args[3], a4 = args[4], a5 = args[5]; 2341 if ((a0 == a3 && !const_args[3]) || (a0 == a5 && !const_args[5])) { 2342 a0 = TCG_REG_TMP; 2343 } 2344 if (const_args[2]) { 2345 if (const_args[4]) { 2346 tcg_out_movi32(s, COND_AL, a0, a4); 2347 a4 = a0; 2348 } 2349 tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR, a0, a4, a2, 1); 2350 } else { 2351 tcg_out_dat_rIN(s, COND_AL, ARITH_SUB | TO_CPSR, 2352 ARITH_ADD | TO_CPSR, a0, a2, a4, const_args[4]); 2353 } 2354 if (const_args[3]) { 2355 if (const_args[5]) { 2356 tcg_out_movi32(s, COND_AL, a1, a5); 2357 a5 = a1; 2358 } 2359 tcg_out_dat_rI(s, COND_AL, ARITH_RSC, a1, a5, a3, 1); 2360 } else { 2361 tcg_out_dat_rIK(s, COND_AL, ARITH_SBC, ARITH_ADC, 2362 a1, a3, a5, const_args[5]); 2363 } 2364 tcg_out_mov_reg(s, COND_AL, args[0], a0); 2365 break; 2366 2367 case INDEX_op_qemu_ld_i32: 2368 tcg_out_qemu_ld(s, args[0], -1, args[1], args[2], TCG_TYPE_I32); 2369 break; 2370 case INDEX_op_qemu_ld_i64: 2371 tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3], TCG_TYPE_I64); 2372 break; 2373 2374 case INDEX_op_qemu_st_i32: 2375 tcg_out_qemu_st(s, args[0], -1, args[1], args[2], TCG_TYPE_I32); 2376 break; 2377 case INDEX_op_qemu_st_i64: 2378 tcg_out_qemu_st(s, args[0], args[1], args[2], args[3], TCG_TYPE_I64); 2379 break; 2380 2381 case INDEX_op_bswap32_i32: 2382 tcg_out_bswap32(s, COND_AL, args[0], args[1]); 2383 break; 2384 2385 case INDEX_op_deposit_i32: 2386 tcg_out_deposit(s, COND_AL, args[0], args[2], 2387 args[3], args[4], const_args[2]); 2388 break; 2389 case INDEX_op_extract_i32: 2390 tcg_out_extract(s, COND_AL, args[0], args[1], args[2], args[3]); 2391 break; 2392 case INDEX_op_sextract_i32: 2393 tcg_out_sextract(s, COND_AL, args[0], args[1], args[2], args[3]); 2394 break; 2395 case INDEX_op_extract2_i32: 2396 /* ??? These optimization vs zero should be generic. */ 2397 /* ??? But we can't substitute 2 for 1 in the opcode stream yet. */ 2398 if (const_args[1]) { 2399 if (const_args[2]) { 2400 tcg_out_movi(s, TCG_TYPE_REG, args[0], 0); 2401 } else { 2402 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, 2403 args[2], SHIFT_IMM_LSL(32 - args[3])); 2404 } 2405 } else if (const_args[2]) { 2406 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, 2407 args[1], SHIFT_IMM_LSR(args[3])); 2408 } else { 2409 /* We can do extract2 in 2 insns, vs the 3 required otherwise. */ 2410 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, 2411 args[2], SHIFT_IMM_LSL(32 - args[3])); 2412 tcg_out_dat_reg(s, COND_AL, ARITH_ORR, args[0], TCG_REG_TMP, 2413 args[1], SHIFT_IMM_LSR(args[3])); 2414 } 2415 break; 2416 2417 case INDEX_op_mb: 2418 tcg_out_mb(s, args[0]); 2419 break; 2420 2421 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2422 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2423 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2424 default: 2425 g_assert_not_reached(); 2426 } 2427} 2428 2429static TCGConstraintSetIndex 2430tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) 2431{ 2432 switch (op) { 2433 case INDEX_op_goto_ptr: 2434 return C_O0_I1(r); 2435 2436 case INDEX_op_ld8u_i32: 2437 case INDEX_op_ld8s_i32: 2438 case INDEX_op_ld16u_i32: 2439 case INDEX_op_ld16s_i32: 2440 case INDEX_op_ld_i32: 2441 case INDEX_op_bswap32_i32: 2442 case INDEX_op_extract_i32: 2443 case INDEX_op_sextract_i32: 2444 return C_O1_I1(r, r); 2445 2446 case INDEX_op_st8_i32: 2447 case INDEX_op_st16_i32: 2448 case INDEX_op_st_i32: 2449 return C_O0_I2(r, r); 2450 2451 case INDEX_op_deposit_i32: 2452 return C_O1_I2(r, 0, rZ); 2453 case INDEX_op_extract2_i32: 2454 return C_O1_I2(r, rZ, rZ); 2455 case INDEX_op_add2_i32: 2456 return C_O2_I4(r, r, r, r, rIN, rIK); 2457 case INDEX_op_sub2_i32: 2458 return C_O2_I4(r, r, rI, rI, rIN, rIK); 2459 case INDEX_op_qemu_ld_i32: 2460 return C_O1_I1(r, q); 2461 case INDEX_op_qemu_ld_i64: 2462 return C_O2_I1(e, p, q); 2463 case INDEX_op_qemu_st_i32: 2464 return C_O0_I2(q, q); 2465 case INDEX_op_qemu_st_i64: 2466 return C_O0_I3(Q, p, q); 2467 2468 case INDEX_op_st_vec: 2469 return C_O0_I2(w, r); 2470 case INDEX_op_ld_vec: 2471 case INDEX_op_dupm_vec: 2472 return C_O1_I1(w, r); 2473 case INDEX_op_dup_vec: 2474 return C_O1_I1(w, wr); 2475 case INDEX_op_abs_vec: 2476 case INDEX_op_neg_vec: 2477 case INDEX_op_not_vec: 2478 case INDEX_op_shli_vec: 2479 case INDEX_op_shri_vec: 2480 case INDEX_op_sari_vec: 2481 return C_O1_I1(w, w); 2482 case INDEX_op_dup2_vec: 2483 case INDEX_op_add_vec: 2484 case INDEX_op_mul_vec: 2485 case INDEX_op_smax_vec: 2486 case INDEX_op_smin_vec: 2487 case INDEX_op_ssadd_vec: 2488 case INDEX_op_sssub_vec: 2489 case INDEX_op_sub_vec: 2490 case INDEX_op_umax_vec: 2491 case INDEX_op_umin_vec: 2492 case INDEX_op_usadd_vec: 2493 case INDEX_op_ussub_vec: 2494 case INDEX_op_xor_vec: 2495 case INDEX_op_arm_sshl_vec: 2496 case INDEX_op_arm_ushl_vec: 2497 return C_O1_I2(w, w, w); 2498 case INDEX_op_arm_sli_vec: 2499 return C_O1_I2(w, 0, w); 2500 case INDEX_op_or_vec: 2501 case INDEX_op_andc_vec: 2502 return C_O1_I2(w, w, wO); 2503 case INDEX_op_and_vec: 2504 case INDEX_op_orc_vec: 2505 return C_O1_I2(w, w, wV); 2506 case INDEX_op_cmp_vec: 2507 return C_O1_I2(w, w, wZ); 2508 case INDEX_op_bitsel_vec: 2509 return C_O1_I3(w, w, w, w); 2510 default: 2511 return C_NotImplemented; 2512 } 2513} 2514 2515static void tcg_target_init(TCGContext *s) 2516{ 2517 /* 2518 * Only probe for the platform and capabilities if we haven't already 2519 * determined maximum values at compile time. 2520 */ 2521#if !defined(use_idiv_instructions) || !defined(use_neon_instructions) 2522 { 2523 unsigned long hwcap = qemu_getauxval(AT_HWCAP); 2524#ifndef use_idiv_instructions 2525 use_idiv_instructions = (hwcap & HWCAP_ARM_IDIVA) != 0; 2526#endif 2527#ifndef use_neon_instructions 2528 use_neon_instructions = (hwcap & HWCAP_ARM_NEON) != 0; 2529#endif 2530 } 2531#endif 2532 2533 if (__ARM_ARCH < 7) { 2534 const char *pl = (const char *)qemu_getauxval(AT_PLATFORM); 2535 if (pl != NULL && pl[0] == 'v' && pl[1] >= '4' && pl[1] <= '9') { 2536 arm_arch = pl[1] - '0'; 2537 } 2538 2539 if (arm_arch < 6) { 2540 error_report("TCG: ARMv%d is unsupported; exiting", arm_arch); 2541 exit(EXIT_FAILURE); 2542 } 2543 } 2544 2545 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS; 2546 2547 tcg_target_call_clobber_regs = 0; 2548 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); 2549 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1); 2550 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2); 2551 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3); 2552 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12); 2553 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14); 2554 2555 if (use_neon_instructions) { 2556 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS; 2557 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS; 2558 2559 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q0); 2560 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q1); 2561 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q2); 2562 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q3); 2563 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q8); 2564 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q9); 2565 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q10); 2566 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q11); 2567 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q12); 2568 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q13); 2569 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q14); 2570 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q15); 2571 } 2572 2573 s->reserved_regs = 0; 2574 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); 2575 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP); 2576 tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC); 2577 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP); 2578} 2579 2580static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 2581 TCGReg arg1, intptr_t arg2) 2582{ 2583 switch (type) { 2584 case TCG_TYPE_I32: 2585 tcg_out_ld32u(s, COND_AL, arg, arg1, arg2); 2586 return; 2587 case TCG_TYPE_V64: 2588 /* regs 1; size 8; align 8 */ 2589 tcg_out_vldst(s, INSN_VLD1 | 0x7d0, arg, arg1, arg2); 2590 return; 2591 case TCG_TYPE_V128: 2592 /* 2593 * We have only 8-byte alignment for the stack per the ABI. 2594 * Rather than dynamically re-align the stack, it's easier 2595 * to simply not request alignment beyond that. So: 2596 * regs 2; size 8; align 8 2597 */ 2598 tcg_out_vldst(s, INSN_VLD1 | 0xad0, arg, arg1, arg2); 2599 return; 2600 default: 2601 g_assert_not_reached(); 2602 } 2603} 2604 2605static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 2606 TCGReg arg1, intptr_t arg2) 2607{ 2608 switch (type) { 2609 case TCG_TYPE_I32: 2610 tcg_out_st32(s, COND_AL, arg, arg1, arg2); 2611 return; 2612 case TCG_TYPE_V64: 2613 /* regs 1; size 8; align 8 */ 2614 tcg_out_vldst(s, INSN_VST1 | 0x7d0, arg, arg1, arg2); 2615 return; 2616 case TCG_TYPE_V128: 2617 /* See tcg_out_ld re alignment: regs 2; size 8; align 8 */ 2618 tcg_out_vldst(s, INSN_VST1 | 0xad0, arg, arg1, arg2); 2619 return; 2620 default: 2621 g_assert_not_reached(); 2622 } 2623} 2624 2625static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 2626 TCGReg base, intptr_t ofs) 2627{ 2628 return false; 2629} 2630 2631static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 2632{ 2633 if (ret == arg) { 2634 return true; 2635 } 2636 switch (type) { 2637 case TCG_TYPE_I32: 2638 if (ret < TCG_REG_Q0 && arg < TCG_REG_Q0) { 2639 tcg_out_mov_reg(s, COND_AL, ret, arg); 2640 return true; 2641 } 2642 return false; 2643 2644 case TCG_TYPE_V64: 2645 case TCG_TYPE_V128: 2646 /* "VMOV D,N" is an alias for "VORR D,N,N". */ 2647 tcg_out_vreg3(s, INSN_VORR, type - TCG_TYPE_V64, 0, ret, arg, arg); 2648 return true; 2649 2650 default: 2651 g_assert_not_reached(); 2652 } 2653} 2654 2655static void tcg_out_movi(TCGContext *s, TCGType type, 2656 TCGReg ret, tcg_target_long arg) 2657{ 2658 tcg_debug_assert(type == TCG_TYPE_I32); 2659 tcg_debug_assert(ret < TCG_REG_Q0); 2660 tcg_out_movi32(s, COND_AL, ret, arg); 2661} 2662 2663static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 2664{ 2665 return false; 2666} 2667 2668static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 2669 tcg_target_long imm) 2670{ 2671 int enc, opc = ARITH_ADD; 2672 2673 /* All of the easiest immediates to encode are positive. */ 2674 if (imm < 0) { 2675 imm = -imm; 2676 opc = ARITH_SUB; 2677 } 2678 enc = encode_imm(imm); 2679 if (enc >= 0) { 2680 tcg_out_dat_imm(s, COND_AL, opc, rd, rs, enc); 2681 } else { 2682 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, imm); 2683 tcg_out_dat_reg(s, COND_AL, opc, rd, rs, 2684 TCG_REG_TMP, SHIFT_IMM_LSL(0)); 2685 } 2686} 2687 2688/* Type is always V128, with I64 elements. */ 2689static void tcg_out_dup2_vec(TCGContext *s, TCGReg rd, TCGReg rl, TCGReg rh) 2690{ 2691 /* Move high element into place first. */ 2692 /* VMOV Dd+1, Ds */ 2693 tcg_out_vreg3(s, INSN_VORR | (1 << 12), 0, 0, rd, rh, rh); 2694 /* Move low element into place; tcg_out_mov will check for nop. */ 2695 tcg_out_mov(s, TCG_TYPE_V64, rd, rl); 2696} 2697 2698static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 2699 TCGReg rd, TCGReg rs) 2700{ 2701 int q = type - TCG_TYPE_V64; 2702 2703 if (vece == MO_64) { 2704 if (type == TCG_TYPE_V128) { 2705 tcg_out_dup2_vec(s, rd, rs, rs); 2706 } else { 2707 tcg_out_mov(s, TCG_TYPE_V64, rd, rs); 2708 } 2709 } else if (rs < TCG_REG_Q0) { 2710 int b = (vece == MO_8); 2711 int e = (vece == MO_16); 2712 tcg_out32(s, INSN_VDUP_G | (b << 22) | (q << 21) | (e << 5) | 2713 encode_vn(rd) | (rs << 12)); 2714 } else { 2715 int imm4 = 1 << vece; 2716 tcg_out32(s, INSN_VDUP_S | (imm4 << 16) | (q << 6) | 2717 encode_vd(rd) | encode_vm(rs)); 2718 } 2719 return true; 2720} 2721 2722static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 2723 TCGReg rd, TCGReg base, intptr_t offset) 2724{ 2725 if (vece == MO_64) { 2726 tcg_out_ld(s, TCG_TYPE_V64, rd, base, offset); 2727 if (type == TCG_TYPE_V128) { 2728 tcg_out_dup2_vec(s, rd, rd, rd); 2729 } 2730 } else { 2731 int q = type - TCG_TYPE_V64; 2732 tcg_out_vldst(s, INSN_VLD1R | (vece << 6) | (q << 5), 2733 rd, base, offset); 2734 } 2735 return true; 2736} 2737 2738static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 2739 TCGReg rd, int64_t v64) 2740{ 2741 int q = type - TCG_TYPE_V64; 2742 int cmode, imm8, i; 2743 2744 /* Test all bytes equal first. */ 2745 if (vece == MO_8) { 2746 tcg_out_vmovi(s, rd, q, 0, 0xe, v64); 2747 return; 2748 } 2749 2750 /* 2751 * Test all bytes 0x00 or 0xff second. This can match cases that 2752 * might otherwise take 2 or 3 insns for MO_16 or MO_32 below. 2753 */ 2754 for (i = imm8 = 0; i < 8; i++) { 2755 uint8_t byte = v64 >> (i * 8); 2756 if (byte == 0xff) { 2757 imm8 |= 1 << i; 2758 } else if (byte != 0) { 2759 goto fail_bytes; 2760 } 2761 } 2762 tcg_out_vmovi(s, rd, q, 1, 0xe, imm8); 2763 return; 2764 fail_bytes: 2765 2766 /* 2767 * Tests for various replications. For each element width, if we 2768 * cannot find an expansion there's no point checking a larger 2769 * width because we already know by replication it cannot match. 2770 */ 2771 if (vece == MO_16) { 2772 uint16_t v16 = v64; 2773 2774 if (is_shimm16(v16, &cmode, &imm8)) { 2775 tcg_out_vmovi(s, rd, q, 0, cmode, imm8); 2776 return; 2777 } 2778 if (is_shimm16(~v16, &cmode, &imm8)) { 2779 tcg_out_vmovi(s, rd, q, 1, cmode, imm8); 2780 return; 2781 } 2782 2783 /* 2784 * Otherwise, all remaining constants can be loaded in two insns: 2785 * rd = v16 & 0xff, rd |= v16 & 0xff00. 2786 */ 2787 tcg_out_vmovi(s, rd, q, 0, 0x8, v16 & 0xff); 2788 tcg_out_vmovi(s, rd, q, 0, 0xb, v16 >> 8); /* VORRI */ 2789 return; 2790 } 2791 2792 if (vece == MO_32) { 2793 uint32_t v32 = v64; 2794 2795 if (is_shimm32(v32, &cmode, &imm8) || 2796 is_soimm32(v32, &cmode, &imm8)) { 2797 tcg_out_vmovi(s, rd, q, 0, cmode, imm8); 2798 return; 2799 } 2800 if (is_shimm32(~v32, &cmode, &imm8) || 2801 is_soimm32(~v32, &cmode, &imm8)) { 2802 tcg_out_vmovi(s, rd, q, 1, cmode, imm8); 2803 return; 2804 } 2805 2806 /* 2807 * Restrict the set of constants to those we can load with 2808 * two instructions. Others we load from the pool. 2809 */ 2810 i = is_shimm32_pair(v32, &cmode, &imm8); 2811 if (i) { 2812 tcg_out_vmovi(s, rd, q, 0, cmode, imm8); 2813 tcg_out_vmovi(s, rd, q, 0, i | 1, extract32(v32, i * 4, 8)); 2814 return; 2815 } 2816 i = is_shimm32_pair(~v32, &cmode, &imm8); 2817 if (i) { 2818 tcg_out_vmovi(s, rd, q, 1, cmode, imm8); 2819 tcg_out_vmovi(s, rd, q, 1, i | 1, extract32(~v32, i * 4, 8)); 2820 return; 2821 } 2822 } 2823 2824 /* 2825 * As a last resort, load from the constant pool. 2826 */ 2827 if (!q || vece == MO_64) { 2828 new_pool_l2(s, R_ARM_PC11, s->code_ptr, 0, v64, v64 >> 32); 2829 /* VLDR Dd, [pc + offset] */ 2830 tcg_out32(s, INSN_VLDR_D | encode_vd(rd) | (0xf << 16)); 2831 if (q) { 2832 tcg_out_dup2_vec(s, rd, rd, rd); 2833 } 2834 } else { 2835 new_pool_label(s, (uint32_t)v64, R_ARM_PC8, s->code_ptr, 0); 2836 /* add tmp, pc, offset */ 2837 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_TMP, TCG_REG_PC, 0); 2838 tcg_out_dupm_vec(s, type, MO_32, rd, TCG_REG_TMP, 0); 2839 } 2840} 2841 2842static const ARMInsn vec_cmp_insn[16] = { 2843 [TCG_COND_EQ] = INSN_VCEQ, 2844 [TCG_COND_GT] = INSN_VCGT, 2845 [TCG_COND_GE] = INSN_VCGE, 2846 [TCG_COND_GTU] = INSN_VCGT_U, 2847 [TCG_COND_GEU] = INSN_VCGE_U, 2848}; 2849 2850static const ARMInsn vec_cmp0_insn[16] = { 2851 [TCG_COND_EQ] = INSN_VCEQ0, 2852 [TCG_COND_GT] = INSN_VCGT0, 2853 [TCG_COND_GE] = INSN_VCGE0, 2854 [TCG_COND_LT] = INSN_VCLT0, 2855 [TCG_COND_LE] = INSN_VCLE0, 2856}; 2857 2858static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 2859 unsigned vecl, unsigned vece, 2860 const TCGArg args[TCG_MAX_OP_ARGS], 2861 const int const_args[TCG_MAX_OP_ARGS]) 2862{ 2863 TCGType type = vecl + TCG_TYPE_V64; 2864 unsigned q = vecl; 2865 TCGArg a0, a1, a2, a3; 2866 int cmode, imm8; 2867 2868 a0 = args[0]; 2869 a1 = args[1]; 2870 a2 = args[2]; 2871 2872 switch (opc) { 2873 case INDEX_op_ld_vec: 2874 tcg_out_ld(s, type, a0, a1, a2); 2875 return; 2876 case INDEX_op_st_vec: 2877 tcg_out_st(s, type, a0, a1, a2); 2878 return; 2879 case INDEX_op_dupm_vec: 2880 tcg_out_dupm_vec(s, type, vece, a0, a1, a2); 2881 return; 2882 case INDEX_op_dup2_vec: 2883 tcg_out_dup2_vec(s, a0, a1, a2); 2884 return; 2885 case INDEX_op_abs_vec: 2886 tcg_out_vreg2(s, INSN_VABS, q, vece, a0, a1); 2887 return; 2888 case INDEX_op_neg_vec: 2889 tcg_out_vreg2(s, INSN_VNEG, q, vece, a0, a1); 2890 return; 2891 case INDEX_op_not_vec: 2892 tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a1); 2893 return; 2894 case INDEX_op_add_vec: 2895 tcg_out_vreg3(s, INSN_VADD, q, vece, a0, a1, a2); 2896 return; 2897 case INDEX_op_mul_vec: 2898 tcg_out_vreg3(s, INSN_VMUL, q, vece, a0, a1, a2); 2899 return; 2900 case INDEX_op_smax_vec: 2901 tcg_out_vreg3(s, INSN_VMAX, q, vece, a0, a1, a2); 2902 return; 2903 case INDEX_op_smin_vec: 2904 tcg_out_vreg3(s, INSN_VMIN, q, vece, a0, a1, a2); 2905 return; 2906 case INDEX_op_sub_vec: 2907 tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2); 2908 return; 2909 case INDEX_op_ssadd_vec: 2910 tcg_out_vreg3(s, INSN_VQADD, q, vece, a0, a1, a2); 2911 return; 2912 case INDEX_op_sssub_vec: 2913 tcg_out_vreg3(s, INSN_VQSUB, q, vece, a0, a1, a2); 2914 return; 2915 case INDEX_op_umax_vec: 2916 tcg_out_vreg3(s, INSN_VMAX_U, q, vece, a0, a1, a2); 2917 return; 2918 case INDEX_op_umin_vec: 2919 tcg_out_vreg3(s, INSN_VMIN_U, q, vece, a0, a1, a2); 2920 return; 2921 case INDEX_op_usadd_vec: 2922 tcg_out_vreg3(s, INSN_VQADD_U, q, vece, a0, a1, a2); 2923 return; 2924 case INDEX_op_ussub_vec: 2925 tcg_out_vreg3(s, INSN_VQSUB_U, q, vece, a0, a1, a2); 2926 return; 2927 case INDEX_op_xor_vec: 2928 tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2); 2929 return; 2930 case INDEX_op_arm_sshl_vec: 2931 /* 2932 * Note that Vm is the data and Vn is the shift count, 2933 * therefore the arguments appear reversed. 2934 */ 2935 tcg_out_vreg3(s, INSN_VSHL_S, q, vece, a0, a2, a1); 2936 return; 2937 case INDEX_op_arm_ushl_vec: 2938 /* See above. */ 2939 tcg_out_vreg3(s, INSN_VSHL_U, q, vece, a0, a2, a1); 2940 return; 2941 case INDEX_op_shli_vec: 2942 tcg_out_vshifti(s, INSN_VSHLI, q, a0, a1, a2 + (8 << vece)); 2943 return; 2944 case INDEX_op_shri_vec: 2945 tcg_out_vshifti(s, INSN_VSHRI, q, a0, a1, (16 << vece) - a2); 2946 return; 2947 case INDEX_op_sari_vec: 2948 tcg_out_vshifti(s, INSN_VSARI, q, a0, a1, (16 << vece) - a2); 2949 return; 2950 case INDEX_op_arm_sli_vec: 2951 tcg_out_vshifti(s, INSN_VSLI, q, a0, a2, args[3] + (8 << vece)); 2952 return; 2953 2954 case INDEX_op_andc_vec: 2955 if (!const_args[2]) { 2956 tcg_out_vreg3(s, INSN_VBIC, q, 0, a0, a1, a2); 2957 return; 2958 } 2959 a2 = ~a2; 2960 /* fall through */ 2961 case INDEX_op_and_vec: 2962 if (const_args[2]) { 2963 is_shimm1632(~a2, &cmode, &imm8); 2964 if (a0 == a1) { 2965 tcg_out_vmovi(s, a0, q, 1, cmode | 1, imm8); /* VBICI */ 2966 return; 2967 } 2968 tcg_out_vmovi(s, a0, q, 1, cmode, imm8); /* VMVNI */ 2969 a2 = a0; 2970 } 2971 tcg_out_vreg3(s, INSN_VAND, q, 0, a0, a1, a2); 2972 return; 2973 2974 case INDEX_op_orc_vec: 2975 if (!const_args[2]) { 2976 tcg_out_vreg3(s, INSN_VORN, q, 0, a0, a1, a2); 2977 return; 2978 } 2979 a2 = ~a2; 2980 /* fall through */ 2981 case INDEX_op_or_vec: 2982 if (const_args[2]) { 2983 is_shimm1632(a2, &cmode, &imm8); 2984 if (a0 == a1) { 2985 tcg_out_vmovi(s, a0, q, 0, cmode | 1, imm8); /* VORRI */ 2986 return; 2987 } 2988 tcg_out_vmovi(s, a0, q, 0, cmode, imm8); /* VMOVI */ 2989 a2 = a0; 2990 } 2991 tcg_out_vreg3(s, INSN_VORR, q, 0, a0, a1, a2); 2992 return; 2993 2994 case INDEX_op_cmp_vec: 2995 { 2996 TCGCond cond = args[3]; 2997 ARMInsn insn; 2998 2999 switch (cond) { 3000 case TCG_COND_NE: 3001 if (const_args[2]) { 3002 tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a1); 3003 } else { 3004 tcg_out_vreg3(s, INSN_VCEQ, q, vece, a0, a1, a2); 3005 tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0); 3006 } 3007 break; 3008 3009 case TCG_COND_TSTNE: 3010 case TCG_COND_TSTEQ: 3011 if (const_args[2]) { 3012 /* (x & 0) == 0 */ 3013 tcg_out_dupi_vec(s, type, MO_8, a0, 3014 -(cond == TCG_COND_TSTEQ)); 3015 break; 3016 } 3017 tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a2); 3018 if (cond == TCG_COND_TSTEQ) { 3019 tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0); 3020 } 3021 break; 3022 3023 default: 3024 if (const_args[2]) { 3025 insn = vec_cmp0_insn[cond]; 3026 if (insn) { 3027 tcg_out_vreg2(s, insn, q, vece, a0, a1); 3028 return; 3029 } 3030 tcg_out_dupi_vec(s, type, MO_8, TCG_VEC_TMP, 0); 3031 a2 = TCG_VEC_TMP; 3032 } 3033 insn = vec_cmp_insn[cond]; 3034 if (insn == 0) { 3035 TCGArg t; 3036 t = a1, a1 = a2, a2 = t; 3037 cond = tcg_swap_cond(cond); 3038 insn = vec_cmp_insn[cond]; 3039 tcg_debug_assert(insn != 0); 3040 } 3041 tcg_out_vreg3(s, insn, q, vece, a0, a1, a2); 3042 break; 3043 } 3044 } 3045 return; 3046 3047 case INDEX_op_bitsel_vec: 3048 a3 = args[3]; 3049 if (a0 == a3) { 3050 tcg_out_vreg3(s, INSN_VBIT, q, 0, a0, a2, a1); 3051 } else if (a0 == a2) { 3052 tcg_out_vreg3(s, INSN_VBIF, q, 0, a0, a3, a1); 3053 } else { 3054 tcg_out_mov(s, type, a0, a1); 3055 tcg_out_vreg3(s, INSN_VBSL, q, 0, a0, a2, a3); 3056 } 3057 return; 3058 3059 case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ 3060 case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ 3061 default: 3062 g_assert_not_reached(); 3063 } 3064} 3065 3066int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 3067{ 3068 switch (opc) { 3069 case INDEX_op_add_vec: 3070 case INDEX_op_sub_vec: 3071 case INDEX_op_and_vec: 3072 case INDEX_op_andc_vec: 3073 case INDEX_op_or_vec: 3074 case INDEX_op_orc_vec: 3075 case INDEX_op_xor_vec: 3076 case INDEX_op_not_vec: 3077 case INDEX_op_shli_vec: 3078 case INDEX_op_shri_vec: 3079 case INDEX_op_sari_vec: 3080 case INDEX_op_ssadd_vec: 3081 case INDEX_op_sssub_vec: 3082 case INDEX_op_usadd_vec: 3083 case INDEX_op_ussub_vec: 3084 case INDEX_op_bitsel_vec: 3085 return 1; 3086 case INDEX_op_abs_vec: 3087 case INDEX_op_cmp_vec: 3088 case INDEX_op_mul_vec: 3089 case INDEX_op_neg_vec: 3090 case INDEX_op_smax_vec: 3091 case INDEX_op_smin_vec: 3092 case INDEX_op_umax_vec: 3093 case INDEX_op_umin_vec: 3094 return vece < MO_64; 3095 case INDEX_op_shlv_vec: 3096 case INDEX_op_shrv_vec: 3097 case INDEX_op_sarv_vec: 3098 case INDEX_op_rotli_vec: 3099 case INDEX_op_rotlv_vec: 3100 case INDEX_op_rotrv_vec: 3101 return -1; 3102 default: 3103 return 0; 3104 } 3105} 3106 3107void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 3108 TCGArg a0, ...) 3109{ 3110 va_list va; 3111 TCGv_vec v0, v1, v2, t1, t2, c1; 3112 TCGArg a2; 3113 3114 va_start(va, a0); 3115 v0 = temp_tcgv_vec(arg_temp(a0)); 3116 v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 3117 a2 = va_arg(va, TCGArg); 3118 va_end(va); 3119 3120 switch (opc) { 3121 case INDEX_op_shlv_vec: 3122 /* 3123 * Merely propagate shlv_vec to arm_ushl_vec. 3124 * In this way we don't set TCG_TARGET_HAS_shv_vec 3125 * because everything is done via expansion. 3126 */ 3127 v2 = temp_tcgv_vec(arg_temp(a2)); 3128 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0), 3129 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 3130 break; 3131 3132 case INDEX_op_shrv_vec: 3133 case INDEX_op_sarv_vec: 3134 /* Right shifts are negative left shifts for NEON. */ 3135 v2 = temp_tcgv_vec(arg_temp(a2)); 3136 t1 = tcg_temp_new_vec(type); 3137 tcg_gen_neg_vec(vece, t1, v2); 3138 if (opc == INDEX_op_shrv_vec) { 3139 opc = INDEX_op_arm_ushl_vec; 3140 } else { 3141 opc = INDEX_op_arm_sshl_vec; 3142 } 3143 vec_gen_3(opc, type, vece, tcgv_vec_arg(v0), 3144 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 3145 tcg_temp_free_vec(t1); 3146 break; 3147 3148 case INDEX_op_rotli_vec: 3149 t1 = tcg_temp_new_vec(type); 3150 tcg_gen_shri_vec(vece, t1, v1, -a2 & ((8 << vece) - 1)); 3151 vec_gen_4(INDEX_op_arm_sli_vec, type, vece, 3152 tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(v1), a2); 3153 tcg_temp_free_vec(t1); 3154 break; 3155 3156 case INDEX_op_rotlv_vec: 3157 v2 = temp_tcgv_vec(arg_temp(a2)); 3158 t1 = tcg_temp_new_vec(type); 3159 c1 = tcg_constant_vec(type, vece, 8 << vece); 3160 tcg_gen_sub_vec(vece, t1, v2, c1); 3161 /* Right shifts are negative left shifts for NEON. */ 3162 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1), 3163 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 3164 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0), 3165 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 3166 tcg_gen_or_vec(vece, v0, v0, t1); 3167 tcg_temp_free_vec(t1); 3168 break; 3169 3170 case INDEX_op_rotrv_vec: 3171 v2 = temp_tcgv_vec(arg_temp(a2)); 3172 t1 = tcg_temp_new_vec(type); 3173 t2 = tcg_temp_new_vec(type); 3174 c1 = tcg_constant_vec(type, vece, 8 << vece); 3175 tcg_gen_neg_vec(vece, t1, v2); 3176 tcg_gen_sub_vec(vece, t2, c1, v2); 3177 /* Right shifts are negative left shifts for NEON. */ 3178 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1), 3179 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 3180 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t2), 3181 tcgv_vec_arg(v1), tcgv_vec_arg(t2)); 3182 tcg_gen_or_vec(vece, v0, t1, t2); 3183 tcg_temp_free_vec(t1); 3184 tcg_temp_free_vec(t2); 3185 break; 3186 3187 default: 3188 g_assert_not_reached(); 3189 } 3190} 3191 3192static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 3193{ 3194 int i; 3195 for (i = 0; i < count; ++i) { 3196 p[i] = INSN_NOP; 3197 } 3198} 3199 3200/* Compute frame size via macros, to share between tcg_target_qemu_prologue 3201 and tcg_register_jit. */ 3202 3203#define PUSH_SIZE ((11 - 4 + 1 + 1) * sizeof(tcg_target_long)) 3204 3205#define FRAME_SIZE \ 3206 ((PUSH_SIZE \ 3207 + TCG_STATIC_CALL_ARGS_SIZE \ 3208 + CPU_TEMP_BUF_NLONGS * sizeof(long) \ 3209 + TCG_TARGET_STACK_ALIGN - 1) \ 3210 & -TCG_TARGET_STACK_ALIGN) 3211 3212#define STACK_ADDEND (FRAME_SIZE - PUSH_SIZE) 3213 3214static void tcg_target_qemu_prologue(TCGContext *s) 3215{ 3216 /* Calling convention requires us to save r4-r11 and lr. */ 3217 /* stmdb sp!, { r4 - r11, lr } */ 3218 tcg_out_ldstm(s, COND_AL, INSN_STMDB, TCG_REG_CALL_STACK, 3219 (1 << TCG_REG_R4) | (1 << TCG_REG_R5) | (1 << TCG_REG_R6) | 3220 (1 << TCG_REG_R7) | (1 << TCG_REG_R8) | (1 << TCG_REG_R9) | 3221 (1 << TCG_REG_R10) | (1 << TCG_REG_R11) | (1 << TCG_REG_R14)); 3222 3223 /* Reserve callee argument and tcg temp space. */ 3224 tcg_out_dat_rI(s, COND_AL, ARITH_SUB, TCG_REG_CALL_STACK, 3225 TCG_REG_CALL_STACK, STACK_ADDEND, 1); 3226 tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE, 3227 CPU_TEMP_BUF_NLONGS * sizeof(long)); 3228 3229 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 3230 3231 if (!tcg_use_softmmu && guest_base) { 3232 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_GUEST_BASE, guest_base); 3233 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GUEST_BASE); 3234 } 3235 3236 tcg_out_b_reg(s, COND_AL, tcg_target_call_iarg_regs[1]); 3237 3238 /* 3239 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 3240 * and fall through to the rest of the epilogue. 3241 */ 3242 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 3243 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, 0); 3244 tcg_out_epilogue(s); 3245} 3246 3247static void tcg_out_epilogue(TCGContext *s) 3248{ 3249 /* Release local stack frame. */ 3250 tcg_out_dat_rI(s, COND_AL, ARITH_ADD, TCG_REG_CALL_STACK, 3251 TCG_REG_CALL_STACK, STACK_ADDEND, 1); 3252 3253 /* ldmia sp!, { r4 - r11, pc } */ 3254 tcg_out_ldstm(s, COND_AL, INSN_LDMIA, TCG_REG_CALL_STACK, 3255 (1 << TCG_REG_R4) | (1 << TCG_REG_R5) | (1 << TCG_REG_R6) | 3256 (1 << TCG_REG_R7) | (1 << TCG_REG_R8) | (1 << TCG_REG_R9) | 3257 (1 << TCG_REG_R10) | (1 << TCG_REG_R11) | (1 << TCG_REG_PC)); 3258} 3259 3260static void tcg_out_tb_start(TCGContext *s) 3261{ 3262 /* nothing to do */ 3263} 3264 3265typedef struct { 3266 DebugFrameHeader h; 3267 uint8_t fde_def_cfa[4]; 3268 uint8_t fde_reg_ofs[18]; 3269} DebugFrame; 3270 3271#define ELF_HOST_MACHINE EM_ARM 3272 3273/* We're expecting a 2 byte uleb128 encoded value. */ 3274QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); 3275 3276static const DebugFrame debug_frame = { 3277 .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ 3278 .h.cie.id = -1, 3279 .h.cie.version = 1, 3280 .h.cie.code_align = 1, 3281 .h.cie.data_align = 0x7c, /* sleb128 -4 */ 3282 .h.cie.return_column = 14, 3283 3284 /* Total FDE size does not include the "len" member. */ 3285 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 3286 3287 .fde_def_cfa = { 3288 12, 13, /* DW_CFA_def_cfa sp, ... */ 3289 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 3290 (FRAME_SIZE >> 7) 3291 }, 3292 .fde_reg_ofs = { 3293 /* The following must match the stmdb in the prologue. */ 3294 0x8e, 1, /* DW_CFA_offset, lr, -4 */ 3295 0x8b, 2, /* DW_CFA_offset, r11, -8 */ 3296 0x8a, 3, /* DW_CFA_offset, r10, -12 */ 3297 0x89, 4, /* DW_CFA_offset, r9, -16 */ 3298 0x88, 5, /* DW_CFA_offset, r8, -20 */ 3299 0x87, 6, /* DW_CFA_offset, r7, -24 */ 3300 0x86, 7, /* DW_CFA_offset, r6, -28 */ 3301 0x85, 8, /* DW_CFA_offset, r5, -32 */ 3302 0x84, 9, /* DW_CFA_offset, r4, -36 */ 3303 } 3304}; 3305 3306void tcg_register_jit(const void *buf, size_t buf_size) 3307{ 3308 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 3309} 3310