1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Andrzej Zaborowski 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25#include "elf.h" 26#include "../tcg-ldst.c.inc" 27#include "../tcg-pool.c.inc" 28 29int arm_arch = __ARM_ARCH; 30 31#ifndef use_idiv_instructions 32bool use_idiv_instructions; 33#endif 34#ifndef use_neon_instructions 35bool use_neon_instructions; 36#endif 37 38#ifdef CONFIG_DEBUG_TCG 39static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 40 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", 41 "%r8", "%r9", "%r10", "%r11", "%r12", "%sp", "%r14", "%pc", 42 "%q0", "%q1", "%q2", "%q3", "%q4", "%q5", "%q6", "%q7", 43 "%q8", "%q9", "%q10", "%q11", "%q12", "%q13", "%q14", "%q15", 44}; 45#endif 46 47static const int tcg_target_reg_alloc_order[] = { 48 TCG_REG_R4, 49 TCG_REG_R5, 50 TCG_REG_R6, 51 TCG_REG_R7, 52 TCG_REG_R8, 53 TCG_REG_R9, 54 TCG_REG_R10, 55 TCG_REG_R11, 56 TCG_REG_R13, 57 TCG_REG_R0, 58 TCG_REG_R1, 59 TCG_REG_R2, 60 TCG_REG_R3, 61 TCG_REG_R12, 62 TCG_REG_R14, 63 64 TCG_REG_Q0, 65 TCG_REG_Q1, 66 TCG_REG_Q2, 67 TCG_REG_Q3, 68 /* Q4 - Q7 are call-saved, and skipped. */ 69 TCG_REG_Q8, 70 TCG_REG_Q9, 71 TCG_REG_Q10, 72 TCG_REG_Q11, 73 TCG_REG_Q12, 74 TCG_REG_Q13, 75 TCG_REG_Q14, 76 TCG_REG_Q15, 77}; 78 79static const int tcg_target_call_iarg_regs[4] = { 80 TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3 81}; 82 83static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 84{ 85 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 86 tcg_debug_assert(slot >= 0 && slot <= 3); 87 return TCG_REG_R0 + slot; 88} 89 90#define TCG_REG_TMP TCG_REG_R12 91#define TCG_VEC_TMP TCG_REG_Q15 92#ifndef CONFIG_SOFTMMU 93#define TCG_REG_GUEST_BASE TCG_REG_R11 94#endif 95 96typedef enum { 97 COND_EQ = 0x0, 98 COND_NE = 0x1, 99 COND_CS = 0x2, /* Unsigned greater or equal */ 100 COND_CC = 0x3, /* Unsigned less than */ 101 COND_MI = 0x4, /* Negative */ 102 COND_PL = 0x5, /* Zero or greater */ 103 COND_VS = 0x6, /* Overflow */ 104 COND_VC = 0x7, /* No overflow */ 105 COND_HI = 0x8, /* Unsigned greater than */ 106 COND_LS = 0x9, /* Unsigned less or equal */ 107 COND_GE = 0xa, 108 COND_LT = 0xb, 109 COND_GT = 0xc, 110 COND_LE = 0xd, 111 COND_AL = 0xe, 112} ARMCond; 113 114#define TO_CPSR (1 << 20) 115 116#define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00) 117#define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20) 118#define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40) 119#define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60) 120#define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10) 121#define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30) 122#define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50) 123#define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70) 124 125typedef enum { 126 ARITH_AND = 0x0 << 21, 127 ARITH_EOR = 0x1 << 21, 128 ARITH_SUB = 0x2 << 21, 129 ARITH_RSB = 0x3 << 21, 130 ARITH_ADD = 0x4 << 21, 131 ARITH_ADC = 0x5 << 21, 132 ARITH_SBC = 0x6 << 21, 133 ARITH_RSC = 0x7 << 21, 134 ARITH_TST = 0x8 << 21 | TO_CPSR, 135 ARITH_CMP = 0xa << 21 | TO_CPSR, 136 ARITH_CMN = 0xb << 21 | TO_CPSR, 137 ARITH_ORR = 0xc << 21, 138 ARITH_MOV = 0xd << 21, 139 ARITH_BIC = 0xe << 21, 140 ARITH_MVN = 0xf << 21, 141 142 INSN_B = 0x0a000000, 143 144 INSN_CLZ = 0x016f0f10, 145 INSN_RBIT = 0x06ff0f30, 146 147 INSN_LDMIA = 0x08b00000, 148 INSN_STMDB = 0x09200000, 149 150 INSN_LDR_IMM = 0x04100000, 151 INSN_LDR_REG = 0x06100000, 152 INSN_STR_IMM = 0x04000000, 153 INSN_STR_REG = 0x06000000, 154 155 INSN_LDRH_IMM = 0x005000b0, 156 INSN_LDRH_REG = 0x001000b0, 157 INSN_LDRSH_IMM = 0x005000f0, 158 INSN_LDRSH_REG = 0x001000f0, 159 INSN_STRH_IMM = 0x004000b0, 160 INSN_STRH_REG = 0x000000b0, 161 162 INSN_LDRB_IMM = 0x04500000, 163 INSN_LDRB_REG = 0x06500000, 164 INSN_LDRSB_IMM = 0x005000d0, 165 INSN_LDRSB_REG = 0x001000d0, 166 INSN_STRB_IMM = 0x04400000, 167 INSN_STRB_REG = 0x06400000, 168 169 INSN_LDRD_IMM = 0x004000d0, 170 INSN_LDRD_REG = 0x000000d0, 171 INSN_STRD_IMM = 0x004000f0, 172 INSN_STRD_REG = 0x000000f0, 173 174 INSN_DMB_ISH = 0xf57ff05b, 175 INSN_DMB_MCR = 0xee070fba, 176 177 /* Architected nop introduced in v6k. */ 178 /* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this 179 also Just So Happened to do nothing on pre-v6k so that we 180 don't need to conditionalize it? */ 181 INSN_NOP_v6k = 0xe320f000, 182 /* Otherwise the assembler uses mov r0,r0 */ 183 INSN_NOP_v4 = (COND_AL << 28) | ARITH_MOV, 184 185 INSN_VADD = 0xf2000800, 186 INSN_VAND = 0xf2000110, 187 INSN_VBIC = 0xf2100110, 188 INSN_VEOR = 0xf3000110, 189 INSN_VORN = 0xf2300110, 190 INSN_VORR = 0xf2200110, 191 INSN_VSUB = 0xf3000800, 192 INSN_VMUL = 0xf2000910, 193 INSN_VQADD = 0xf2000010, 194 INSN_VQADD_U = 0xf3000010, 195 INSN_VQSUB = 0xf2000210, 196 INSN_VQSUB_U = 0xf3000210, 197 INSN_VMAX = 0xf2000600, 198 INSN_VMAX_U = 0xf3000600, 199 INSN_VMIN = 0xf2000610, 200 INSN_VMIN_U = 0xf3000610, 201 202 INSN_VABS = 0xf3b10300, 203 INSN_VMVN = 0xf3b00580, 204 INSN_VNEG = 0xf3b10380, 205 206 INSN_VCEQ0 = 0xf3b10100, 207 INSN_VCGT0 = 0xf3b10000, 208 INSN_VCGE0 = 0xf3b10080, 209 INSN_VCLE0 = 0xf3b10180, 210 INSN_VCLT0 = 0xf3b10200, 211 212 INSN_VCEQ = 0xf3000810, 213 INSN_VCGE = 0xf2000310, 214 INSN_VCGT = 0xf2000300, 215 INSN_VCGE_U = 0xf3000310, 216 INSN_VCGT_U = 0xf3000300, 217 218 INSN_VSHLI = 0xf2800510, /* VSHL (immediate) */ 219 INSN_VSARI = 0xf2800010, /* VSHR.S */ 220 INSN_VSHRI = 0xf3800010, /* VSHR.U */ 221 INSN_VSLI = 0xf3800510, 222 INSN_VSHL_S = 0xf2000400, /* VSHL.S (register) */ 223 INSN_VSHL_U = 0xf3000400, /* VSHL.U (register) */ 224 225 INSN_VBSL = 0xf3100110, 226 INSN_VBIT = 0xf3200110, 227 INSN_VBIF = 0xf3300110, 228 229 INSN_VTST = 0xf2000810, 230 231 INSN_VDUP_G = 0xee800b10, /* VDUP (ARM core register) */ 232 INSN_VDUP_S = 0xf3b00c00, /* VDUP (scalar) */ 233 INSN_VLDR_D = 0xed100b00, /* VLDR.64 */ 234 INSN_VLD1 = 0xf4200000, /* VLD1 (multiple single elements) */ 235 INSN_VLD1R = 0xf4a00c00, /* VLD1 (single element to all lanes) */ 236 INSN_VST1 = 0xf4000000, /* VST1 (multiple single elements) */ 237 INSN_VMOVI = 0xf2800010, /* VMOV (immediate) */ 238} ARMInsn; 239 240#define INSN_NOP (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4) 241 242static const uint8_t tcg_cond_to_arm_cond[] = { 243 [TCG_COND_EQ] = COND_EQ, 244 [TCG_COND_NE] = COND_NE, 245 [TCG_COND_LT] = COND_LT, 246 [TCG_COND_GE] = COND_GE, 247 [TCG_COND_LE] = COND_LE, 248 [TCG_COND_GT] = COND_GT, 249 /* unsigned */ 250 [TCG_COND_LTU] = COND_CC, 251 [TCG_COND_GEU] = COND_CS, 252 [TCG_COND_LEU] = COND_LS, 253 [TCG_COND_GTU] = COND_HI, 254}; 255 256static int encode_imm(uint32_t imm); 257 258/* TCG private relocation type: add with pc+imm8 */ 259#define R_ARM_PC8 11 260 261/* TCG private relocation type: vldr with imm8 << 2 */ 262#define R_ARM_PC11 12 263 264static bool reloc_pc24(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 265{ 266 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 267 ptrdiff_t offset = (tcg_ptr_byte_diff(target, src_rx) - 8) >> 2; 268 269 if (offset == sextract32(offset, 0, 24)) { 270 *src_rw = deposit32(*src_rw, 0, 24, offset); 271 return true; 272 } 273 return false; 274} 275 276static bool reloc_pc13(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 277{ 278 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 279 ptrdiff_t offset = tcg_ptr_byte_diff(target, src_rx) - 8; 280 281 if (offset >= -0xfff && offset <= 0xfff) { 282 tcg_insn_unit insn = *src_rw; 283 bool u = (offset >= 0); 284 if (!u) { 285 offset = -offset; 286 } 287 insn = deposit32(insn, 23, 1, u); 288 insn = deposit32(insn, 0, 12, offset); 289 *src_rw = insn; 290 return true; 291 } 292 return false; 293} 294 295static bool reloc_pc11(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 296{ 297 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 298 ptrdiff_t offset = (tcg_ptr_byte_diff(target, src_rx) - 8) / 4; 299 300 if (offset >= -0xff && offset <= 0xff) { 301 tcg_insn_unit insn = *src_rw; 302 bool u = (offset >= 0); 303 if (!u) { 304 offset = -offset; 305 } 306 insn = deposit32(insn, 23, 1, u); 307 insn = deposit32(insn, 0, 8, offset); 308 *src_rw = insn; 309 return true; 310 } 311 return false; 312} 313 314static bool reloc_pc8(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 315{ 316 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 317 ptrdiff_t offset = tcg_ptr_byte_diff(target, src_rx) - 8; 318 int imm12 = encode_imm(offset); 319 320 if (imm12 >= 0) { 321 *src_rw = deposit32(*src_rw, 0, 12, imm12); 322 return true; 323 } 324 return false; 325} 326 327static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 328 intptr_t value, intptr_t addend) 329{ 330 tcg_debug_assert(addend == 0); 331 switch (type) { 332 case R_ARM_PC24: 333 return reloc_pc24(code_ptr, (const tcg_insn_unit *)value); 334 case R_ARM_PC13: 335 return reloc_pc13(code_ptr, (const tcg_insn_unit *)value); 336 case R_ARM_PC11: 337 return reloc_pc11(code_ptr, (const tcg_insn_unit *)value); 338 case R_ARM_PC8: 339 return reloc_pc8(code_ptr, (const tcg_insn_unit *)value); 340 default: 341 g_assert_not_reached(); 342 } 343} 344 345#define TCG_CT_CONST_ARM 0x100 346#define TCG_CT_CONST_INV 0x200 347#define TCG_CT_CONST_NEG 0x400 348#define TCG_CT_CONST_ZERO 0x800 349#define TCG_CT_CONST_ORRI 0x1000 350#define TCG_CT_CONST_ANDI 0x2000 351 352#define ALL_GENERAL_REGS 0xffffu 353#define ALL_VECTOR_REGS 0xffff0000u 354 355/* 356 * r0-r2 will be overwritten when reading the tlb entry (softmmu only) 357 * and r0-r1 doing the byte swapping, so don't use these. 358 * r3 is removed for softmmu to avoid clashes with helper arguments. 359 */ 360#ifdef CONFIG_SOFTMMU 361#define ALL_QLOAD_REGS \ 362 (ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1) | \ 363 (1 << TCG_REG_R2) | (1 << TCG_REG_R3) | \ 364 (1 << TCG_REG_R14))) 365#define ALL_QSTORE_REGS \ 366 (ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1) | \ 367 (1 << TCG_REG_R2) | (1 << TCG_REG_R14) | \ 368 ((TARGET_LONG_BITS == 64) << TCG_REG_R3))) 369#else 370#define ALL_QLOAD_REGS ALL_GENERAL_REGS 371#define ALL_QSTORE_REGS \ 372 (ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1))) 373#endif 374 375/* 376 * ARM immediates for ALU instructions are made of an unsigned 8-bit 377 * right-rotated by an even amount between 0 and 30. 378 * 379 * Return < 0 if @imm cannot be encoded, else the entire imm12 field. 380 */ 381static int encode_imm(uint32_t imm) 382{ 383 uint32_t rot, imm8; 384 385 /* Simple case, no rotation required. */ 386 if ((imm & ~0xff) == 0) { 387 return imm; 388 } 389 390 /* Next, try a simple even shift. */ 391 rot = ctz32(imm) & ~1; 392 imm8 = imm >> rot; 393 rot = 32 - rot; 394 if ((imm8 & ~0xff) == 0) { 395 goto found; 396 } 397 398 /* 399 * Finally, try harder with rotations. 400 * The ctz test above will have taken care of rotates >= 8. 401 */ 402 for (rot = 2; rot < 8; rot += 2) { 403 imm8 = rol32(imm, rot); 404 if ((imm8 & ~0xff) == 0) { 405 goto found; 406 } 407 } 408 /* Fail: imm cannot be encoded. */ 409 return -1; 410 411 found: 412 /* Note that rot is even, and we discard bit 0 by shifting by 7. */ 413 return rot << 7 | imm8; 414} 415 416static int encode_imm_nofail(uint32_t imm) 417{ 418 int ret = encode_imm(imm); 419 tcg_debug_assert(ret >= 0); 420 return ret; 421} 422 423static bool check_fit_imm(uint32_t imm) 424{ 425 return encode_imm(imm) >= 0; 426} 427 428/* Return true if v16 is a valid 16-bit shifted immediate. */ 429static bool is_shimm16(uint16_t v16, int *cmode, int *imm8) 430{ 431 if (v16 == (v16 & 0xff)) { 432 *cmode = 0x8; 433 *imm8 = v16 & 0xff; 434 return true; 435 } else if (v16 == (v16 & 0xff00)) { 436 *cmode = 0xa; 437 *imm8 = v16 >> 8; 438 return true; 439 } 440 return false; 441} 442 443/* Return true if v32 is a valid 32-bit shifted immediate. */ 444static bool is_shimm32(uint32_t v32, int *cmode, int *imm8) 445{ 446 if (v32 == (v32 & 0xff)) { 447 *cmode = 0x0; 448 *imm8 = v32 & 0xff; 449 return true; 450 } else if (v32 == (v32 & 0xff00)) { 451 *cmode = 0x2; 452 *imm8 = (v32 >> 8) & 0xff; 453 return true; 454 } else if (v32 == (v32 & 0xff0000)) { 455 *cmode = 0x4; 456 *imm8 = (v32 >> 16) & 0xff; 457 return true; 458 } else if (v32 == (v32 & 0xff000000)) { 459 *cmode = 0x6; 460 *imm8 = v32 >> 24; 461 return true; 462 } 463 return false; 464} 465 466/* Return true if v32 is a valid 32-bit shifting ones immediate. */ 467static bool is_soimm32(uint32_t v32, int *cmode, int *imm8) 468{ 469 if ((v32 & 0xffff00ff) == 0xff) { 470 *cmode = 0xc; 471 *imm8 = (v32 >> 8) & 0xff; 472 return true; 473 } else if ((v32 & 0xff00ffff) == 0xffff) { 474 *cmode = 0xd; 475 *imm8 = (v32 >> 16) & 0xff; 476 return true; 477 } 478 return false; 479} 480 481/* 482 * Return non-zero if v32 can be formed by MOVI+ORR. 483 * Place the parameters for MOVI in (cmode, imm8). 484 * Return the cmode for ORR; the imm8 can be had via extraction from v32. 485 */ 486static int is_shimm32_pair(uint32_t v32, int *cmode, int *imm8) 487{ 488 int i; 489 490 for (i = 6; i > 0; i -= 2) { 491 /* Mask out one byte we can add with ORR. */ 492 uint32_t tmp = v32 & ~(0xffu << (i * 4)); 493 if (is_shimm32(tmp, cmode, imm8) || 494 is_soimm32(tmp, cmode, imm8)) { 495 break; 496 } 497 } 498 return i; 499} 500 501/* Return true if V is a valid 16-bit or 32-bit shifted immediate. */ 502static bool is_shimm1632(uint32_t v32, int *cmode, int *imm8) 503{ 504 if (v32 == deposit32(v32, 16, 16, v32)) { 505 return is_shimm16(v32, cmode, imm8); 506 } else { 507 return is_shimm32(v32, cmode, imm8); 508 } 509} 510 511/* Test if a constant matches the constraint. 512 * TODO: define constraints for: 513 * 514 * ldr/str offset: between -0xfff and 0xfff 515 * ldrh/strh offset: between -0xff and 0xff 516 * mov operand2: values represented with x << (2 * y), x < 0x100 517 * add, sub, eor...: ditto 518 */ 519static bool tcg_target_const_match(int64_t val, TCGType type, int ct) 520{ 521 if (ct & TCG_CT_CONST) { 522 return 1; 523 } else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val)) { 524 return 1; 525 } else if ((ct & TCG_CT_CONST_INV) && check_fit_imm(~val)) { 526 return 1; 527 } else if ((ct & TCG_CT_CONST_NEG) && check_fit_imm(-val)) { 528 return 1; 529 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 530 return 1; 531 } 532 533 switch (ct & (TCG_CT_CONST_ORRI | TCG_CT_CONST_ANDI)) { 534 case 0: 535 break; 536 case TCG_CT_CONST_ANDI: 537 val = ~val; 538 /* fallthru */ 539 case TCG_CT_CONST_ORRI: 540 if (val == deposit64(val, 32, 32, val)) { 541 int cmode, imm8; 542 return is_shimm1632(val, &cmode, &imm8); 543 } 544 break; 545 default: 546 /* Both bits should not be set for the same insn. */ 547 g_assert_not_reached(); 548 } 549 550 return 0; 551} 552 553static void tcg_out_b_imm(TCGContext *s, ARMCond cond, int32_t offset) 554{ 555 tcg_out32(s, (cond << 28) | INSN_B | 556 (((offset - 8) >> 2) & 0x00ffffff)); 557} 558 559static void tcg_out_bl_imm(TCGContext *s, ARMCond cond, int32_t offset) 560{ 561 tcg_out32(s, (cond << 28) | 0x0b000000 | 562 (((offset - 8) >> 2) & 0x00ffffff)); 563} 564 565static void tcg_out_blx_reg(TCGContext *s, ARMCond cond, TCGReg rn) 566{ 567 tcg_out32(s, (cond << 28) | 0x012fff30 | rn); 568} 569 570static void tcg_out_blx_imm(TCGContext *s, int32_t offset) 571{ 572 tcg_out32(s, 0xfa000000 | ((offset & 2) << 23) | 573 (((offset - 8) >> 2) & 0x00ffffff)); 574} 575 576static void tcg_out_dat_reg(TCGContext *s, ARMCond cond, ARMInsn opc, 577 TCGReg rd, TCGReg rn, TCGReg rm, int shift) 578{ 579 tcg_out32(s, (cond << 28) | (0 << 25) | opc | 580 (rn << 16) | (rd << 12) | shift | rm); 581} 582 583static void tcg_out_mov_reg(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rm) 584{ 585 /* Simple reg-reg move, optimising out the 'do nothing' case */ 586 if (rd != rm) { 587 tcg_out_dat_reg(s, cond, ARITH_MOV, rd, 0, rm, SHIFT_IMM_LSL(0)); 588 } 589} 590 591static void tcg_out_bx_reg(TCGContext *s, ARMCond cond, TCGReg rn) 592{ 593 tcg_out32(s, (cond << 28) | 0x012fff10 | rn); 594} 595 596static void tcg_out_b_reg(TCGContext *s, ARMCond cond, TCGReg rn) 597{ 598 /* 599 * Unless the C portion of QEMU is compiled as thumb, we don't need 600 * true BX semantics; merely a branch to an address held in a register. 601 */ 602 tcg_out_bx_reg(s, cond, rn); 603} 604 605static void tcg_out_dat_imm(TCGContext *s, ARMCond cond, ARMInsn opc, 606 TCGReg rd, TCGReg rn, int im) 607{ 608 tcg_out32(s, (cond << 28) | (1 << 25) | opc | 609 (rn << 16) | (rd << 12) | im); 610} 611 612static void tcg_out_ldstm(TCGContext *s, ARMCond cond, ARMInsn opc, 613 TCGReg rn, uint16_t mask) 614{ 615 tcg_out32(s, (cond << 28) | opc | (rn << 16) | mask); 616} 617 618/* Note that this routine is used for both LDR and LDRH formats, so we do 619 not wish to include an immediate shift at this point. */ 620static void tcg_out_memop_r(TCGContext *s, ARMCond cond, ARMInsn opc, TCGReg rt, 621 TCGReg rn, TCGReg rm, bool u, bool p, bool w) 622{ 623 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) 624 | (w << 21) | (rn << 16) | (rt << 12) | rm); 625} 626 627static void tcg_out_memop_8(TCGContext *s, ARMCond cond, ARMInsn opc, TCGReg rt, 628 TCGReg rn, int imm8, bool p, bool w) 629{ 630 bool u = 1; 631 if (imm8 < 0) { 632 imm8 = -imm8; 633 u = 0; 634 } 635 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | 636 (rn << 16) | (rt << 12) | ((imm8 & 0xf0) << 4) | (imm8 & 0xf)); 637} 638 639static void tcg_out_memop_12(TCGContext *s, ARMCond cond, ARMInsn opc, 640 TCGReg rt, TCGReg rn, int imm12, bool p, bool w) 641{ 642 bool u = 1; 643 if (imm12 < 0) { 644 imm12 = -imm12; 645 u = 0; 646 } 647 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | 648 (rn << 16) | (rt << 12) | imm12); 649} 650 651static void tcg_out_ld32_12(TCGContext *s, ARMCond cond, TCGReg rt, 652 TCGReg rn, int imm12) 653{ 654 tcg_out_memop_12(s, cond, INSN_LDR_IMM, rt, rn, imm12, 1, 0); 655} 656 657static void tcg_out_st32_12(TCGContext *s, ARMCond cond, TCGReg rt, 658 TCGReg rn, int imm12) 659{ 660 tcg_out_memop_12(s, cond, INSN_STR_IMM, rt, rn, imm12, 1, 0); 661} 662 663static void tcg_out_ld32_r(TCGContext *s, ARMCond cond, TCGReg rt, 664 TCGReg rn, TCGReg rm) 665{ 666 tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 0); 667} 668 669static void tcg_out_st32_r(TCGContext *s, ARMCond cond, TCGReg rt, 670 TCGReg rn, TCGReg rm) 671{ 672 tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 0); 673} 674 675static void tcg_out_ldrd_8(TCGContext *s, ARMCond cond, TCGReg rt, 676 TCGReg rn, int imm8) 677{ 678 tcg_out_memop_8(s, cond, INSN_LDRD_IMM, rt, rn, imm8, 1, 0); 679} 680 681static void tcg_out_ldrd_r(TCGContext *s, ARMCond cond, TCGReg rt, 682 TCGReg rn, TCGReg rm) 683{ 684 tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 0); 685} 686 687static void __attribute__((unused)) 688tcg_out_ldrd_rwb(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, TCGReg rm) 689{ 690 tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 1); 691} 692 693static void __attribute__((unused)) 694tcg_out_strd_8(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, int imm8) 695{ 696 tcg_out_memop_8(s, cond, INSN_STRD_IMM, rt, rn, imm8, 1, 0); 697} 698 699static void tcg_out_strd_r(TCGContext *s, ARMCond cond, TCGReg rt, 700 TCGReg rn, TCGReg rm) 701{ 702 tcg_out_memop_r(s, cond, INSN_STRD_REG, rt, rn, rm, 1, 1, 0); 703} 704 705/* Register pre-increment with base writeback. */ 706static void tcg_out_ld32_rwb(TCGContext *s, ARMCond cond, TCGReg rt, 707 TCGReg rn, TCGReg rm) 708{ 709 tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 1); 710} 711 712static void tcg_out_st32_rwb(TCGContext *s, ARMCond cond, TCGReg rt, 713 TCGReg rn, TCGReg rm) 714{ 715 tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 1); 716} 717 718static void tcg_out_ld16u_8(TCGContext *s, ARMCond cond, TCGReg rt, 719 TCGReg rn, int imm8) 720{ 721 tcg_out_memop_8(s, cond, INSN_LDRH_IMM, rt, rn, imm8, 1, 0); 722} 723 724static void tcg_out_st16_8(TCGContext *s, ARMCond cond, TCGReg rt, 725 TCGReg rn, int imm8) 726{ 727 tcg_out_memop_8(s, cond, INSN_STRH_IMM, rt, rn, imm8, 1, 0); 728} 729 730static void tcg_out_ld16u_r(TCGContext *s, ARMCond cond, TCGReg rt, 731 TCGReg rn, TCGReg rm) 732{ 733 tcg_out_memop_r(s, cond, INSN_LDRH_REG, rt, rn, rm, 1, 1, 0); 734} 735 736static void tcg_out_st16_r(TCGContext *s, ARMCond cond, TCGReg rt, 737 TCGReg rn, TCGReg rm) 738{ 739 tcg_out_memop_r(s, cond, INSN_STRH_REG, rt, rn, rm, 1, 1, 0); 740} 741 742static void tcg_out_ld16s_8(TCGContext *s, ARMCond cond, TCGReg rt, 743 TCGReg rn, int imm8) 744{ 745 tcg_out_memop_8(s, cond, INSN_LDRSH_IMM, rt, rn, imm8, 1, 0); 746} 747 748static void tcg_out_ld16s_r(TCGContext *s, ARMCond cond, TCGReg rt, 749 TCGReg rn, TCGReg rm) 750{ 751 tcg_out_memop_r(s, cond, INSN_LDRSH_REG, rt, rn, rm, 1, 1, 0); 752} 753 754static void tcg_out_ld8_12(TCGContext *s, ARMCond cond, TCGReg rt, 755 TCGReg rn, int imm12) 756{ 757 tcg_out_memop_12(s, cond, INSN_LDRB_IMM, rt, rn, imm12, 1, 0); 758} 759 760static void tcg_out_st8_12(TCGContext *s, ARMCond cond, TCGReg rt, 761 TCGReg rn, int imm12) 762{ 763 tcg_out_memop_12(s, cond, INSN_STRB_IMM, rt, rn, imm12, 1, 0); 764} 765 766static void tcg_out_ld8_r(TCGContext *s, ARMCond cond, TCGReg rt, 767 TCGReg rn, TCGReg rm) 768{ 769 tcg_out_memop_r(s, cond, INSN_LDRB_REG, rt, rn, rm, 1, 1, 0); 770} 771 772static void tcg_out_st8_r(TCGContext *s, ARMCond cond, TCGReg rt, 773 TCGReg rn, TCGReg rm) 774{ 775 tcg_out_memop_r(s, cond, INSN_STRB_REG, rt, rn, rm, 1, 1, 0); 776} 777 778static void tcg_out_ld8s_8(TCGContext *s, ARMCond cond, TCGReg rt, 779 TCGReg rn, int imm8) 780{ 781 tcg_out_memop_8(s, cond, INSN_LDRSB_IMM, rt, rn, imm8, 1, 0); 782} 783 784static void tcg_out_ld8s_r(TCGContext *s, ARMCond cond, TCGReg rt, 785 TCGReg rn, TCGReg rm) 786{ 787 tcg_out_memop_r(s, cond, INSN_LDRSB_REG, rt, rn, rm, 1, 1, 0); 788} 789 790static void tcg_out_movi_pool(TCGContext *s, ARMCond cond, 791 TCGReg rd, uint32_t arg) 792{ 793 new_pool_label(s, arg, R_ARM_PC13, s->code_ptr, 0); 794 tcg_out_ld32_12(s, cond, rd, TCG_REG_PC, 0); 795} 796 797static void tcg_out_movi32(TCGContext *s, ARMCond cond, 798 TCGReg rd, uint32_t arg) 799{ 800 int imm12, diff, opc, sh1, sh2; 801 uint32_t tt0, tt1, tt2; 802 803 /* Check a single MOV/MVN before anything else. */ 804 imm12 = encode_imm(arg); 805 if (imm12 >= 0) { 806 tcg_out_dat_imm(s, cond, ARITH_MOV, rd, 0, imm12); 807 return; 808 } 809 imm12 = encode_imm(~arg); 810 if (imm12 >= 0) { 811 tcg_out_dat_imm(s, cond, ARITH_MVN, rd, 0, imm12); 812 return; 813 } 814 815 /* Check for a pc-relative address. This will usually be the TB, 816 or within the TB, which is immediately before the code block. */ 817 diff = tcg_pcrel_diff(s, (void *)arg) - 8; 818 if (diff >= 0) { 819 imm12 = encode_imm(diff); 820 if (imm12 >= 0) { 821 tcg_out_dat_imm(s, cond, ARITH_ADD, rd, TCG_REG_PC, imm12); 822 return; 823 } 824 } else { 825 imm12 = encode_imm(-diff); 826 if (imm12 >= 0) { 827 tcg_out_dat_imm(s, cond, ARITH_SUB, rd, TCG_REG_PC, imm12); 828 return; 829 } 830 } 831 832 /* Use movw + movt. */ 833 if (use_armv7_instructions) { 834 /* movw */ 835 tcg_out32(s, (cond << 28) | 0x03000000 | (rd << 12) 836 | ((arg << 4) & 0x000f0000) | (arg & 0xfff)); 837 if (arg & 0xffff0000) { 838 /* movt */ 839 tcg_out32(s, (cond << 28) | 0x03400000 | (rd << 12) 840 | ((arg >> 12) & 0x000f0000) | ((arg >> 16) & 0xfff)); 841 } 842 return; 843 } 844 845 /* Look for sequences of two insns. If we have lots of 1's, we can 846 shorten the sequence by beginning with mvn and then clearing 847 higher bits with eor. */ 848 tt0 = arg; 849 opc = ARITH_MOV; 850 if (ctpop32(arg) > 16) { 851 tt0 = ~arg; 852 opc = ARITH_MVN; 853 } 854 sh1 = ctz32(tt0) & ~1; 855 tt1 = tt0 & ~(0xff << sh1); 856 sh2 = ctz32(tt1) & ~1; 857 tt2 = tt1 & ~(0xff << sh2); 858 if (tt2 == 0) { 859 int rot; 860 861 rot = ((32 - sh1) << 7) & 0xf00; 862 tcg_out_dat_imm(s, cond, opc, rd, 0, ((tt0 >> sh1) & 0xff) | rot); 863 rot = ((32 - sh2) << 7) & 0xf00; 864 tcg_out_dat_imm(s, cond, ARITH_EOR, rd, rd, 865 ((tt0 >> sh2) & 0xff) | rot); 866 return; 867 } 868 869 /* Otherwise, drop it into the constant pool. */ 870 tcg_out_movi_pool(s, cond, rd, arg); 871} 872 873/* 874 * Emit either the reg,imm or reg,reg form of a data-processing insn. 875 * rhs must satisfy the "rI" constraint. 876 */ 877static void tcg_out_dat_rI(TCGContext *s, ARMCond cond, ARMInsn opc, 878 TCGReg dst, TCGReg lhs, TCGArg rhs, int rhs_is_const) 879{ 880 if (rhs_is_const) { 881 tcg_out_dat_imm(s, cond, opc, dst, lhs, encode_imm_nofail(rhs)); 882 } else { 883 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); 884 } 885} 886 887/* 888 * Emit either the reg,imm or reg,reg form of a data-processing insn. 889 * rhs must satisfy the "rIK" constraint. 890 */ 891static void tcg_out_dat_rIK(TCGContext *s, ARMCond cond, ARMInsn opc, 892 ARMInsn opinv, TCGReg dst, TCGReg lhs, TCGArg rhs, 893 bool rhs_is_const) 894{ 895 if (rhs_is_const) { 896 int imm12 = encode_imm(rhs); 897 if (imm12 < 0) { 898 imm12 = encode_imm_nofail(~rhs); 899 opc = opinv; 900 } 901 tcg_out_dat_imm(s, cond, opc, dst, lhs, imm12); 902 } else { 903 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); 904 } 905} 906 907static void tcg_out_dat_rIN(TCGContext *s, ARMCond cond, ARMInsn opc, 908 ARMInsn opneg, TCGReg dst, TCGReg lhs, TCGArg rhs, 909 bool rhs_is_const) 910{ 911 /* Emit either the reg,imm or reg,reg form of a data-processing insn. 912 * rhs must satisfy the "rIN" constraint. 913 */ 914 if (rhs_is_const) { 915 int imm12 = encode_imm(rhs); 916 if (imm12 < 0) { 917 imm12 = encode_imm_nofail(-rhs); 918 opc = opneg; 919 } 920 tcg_out_dat_imm(s, cond, opc, dst, lhs, imm12); 921 } else { 922 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); 923 } 924} 925 926static void tcg_out_mul32(TCGContext *s, ARMCond cond, TCGReg rd, 927 TCGReg rn, TCGReg rm) 928{ 929 /* mul */ 930 tcg_out32(s, (cond << 28) | 0x90 | (rd << 16) | (rm << 8) | rn); 931} 932 933static void tcg_out_umull32(TCGContext *s, ARMCond cond, TCGReg rd0, 934 TCGReg rd1, TCGReg rn, TCGReg rm) 935{ 936 /* umull */ 937 tcg_out32(s, (cond << 28) | 0x00800090 | 938 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); 939} 940 941static void tcg_out_smull32(TCGContext *s, ARMCond cond, TCGReg rd0, 942 TCGReg rd1, TCGReg rn, TCGReg rm) 943{ 944 /* smull */ 945 tcg_out32(s, (cond << 28) | 0x00c00090 | 946 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); 947} 948 949static void tcg_out_sdiv(TCGContext *s, ARMCond cond, 950 TCGReg rd, TCGReg rn, TCGReg rm) 951{ 952 tcg_out32(s, 0x0710f010 | (cond << 28) | (rd << 16) | rn | (rm << 8)); 953} 954 955static void tcg_out_udiv(TCGContext *s, ARMCond cond, 956 TCGReg rd, TCGReg rn, TCGReg rm) 957{ 958 tcg_out32(s, 0x0730f010 | (cond << 28) | (rd << 16) | rn | (rm << 8)); 959} 960 961static void tcg_out_ext8s(TCGContext *s, TCGType t, TCGReg rd, TCGReg rn) 962{ 963 /* sxtb */ 964 tcg_out32(s, 0x06af0070 | (COND_AL << 28) | (rd << 12) | rn); 965} 966 967static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rn) 968{ 969 tcg_out_dat_imm(s, COND_AL, ARITH_AND, rd, rn, 0xff); 970} 971 972static void tcg_out_ext16s(TCGContext *s, TCGType t, TCGReg rd, TCGReg rn) 973{ 974 /* sxth */ 975 tcg_out32(s, 0x06bf0070 | (COND_AL << 28) | (rd << 12) | rn); 976} 977 978static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rn) 979{ 980 /* uxth */ 981 tcg_out32(s, 0x06ff0070 | (COND_AL << 28) | (rd << 12) | rn); 982} 983 984static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rn) 985{ 986 g_assert_not_reached(); 987} 988 989static void tcg_out_ext32u(TCGContext *s, TCGReg rd, TCGReg rn) 990{ 991 g_assert_not_reached(); 992} 993 994static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rn) 995{ 996 g_assert_not_reached(); 997} 998 999static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rn) 1000{ 1001 g_assert_not_reached(); 1002} 1003 1004static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rn) 1005{ 1006 g_assert_not_reached(); 1007} 1008 1009static void tcg_out_bswap16(TCGContext *s, ARMCond cond, 1010 TCGReg rd, TCGReg rn, int flags) 1011{ 1012 if (flags & TCG_BSWAP_OS) { 1013 /* revsh */ 1014 tcg_out32(s, 0x06ff0fb0 | (cond << 28) | (rd << 12) | rn); 1015 return; 1016 } 1017 1018 /* rev16 */ 1019 tcg_out32(s, 0x06bf0fb0 | (cond << 28) | (rd << 12) | rn); 1020 if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 1021 /* uxth */ 1022 tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | rd); 1023 } 1024} 1025 1026static void tcg_out_bswap32(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rn) 1027{ 1028 /* rev */ 1029 tcg_out32(s, 0x06bf0f30 | (cond << 28) | (rd << 12) | rn); 1030} 1031 1032static void tcg_out_deposit(TCGContext *s, ARMCond cond, TCGReg rd, 1033 TCGArg a1, int ofs, int len, bool const_a1) 1034{ 1035 if (const_a1) { 1036 /* bfi becomes bfc with rn == 15. */ 1037 a1 = 15; 1038 } 1039 /* bfi/bfc */ 1040 tcg_out32(s, 0x07c00010 | (cond << 28) | (rd << 12) | a1 1041 | (ofs << 7) | ((ofs + len - 1) << 16)); 1042} 1043 1044static void tcg_out_extract(TCGContext *s, ARMCond cond, TCGReg rd, 1045 TCGReg rn, int ofs, int len) 1046{ 1047 /* ubfx */ 1048 tcg_out32(s, 0x07e00050 | (cond << 28) | (rd << 12) | rn 1049 | (ofs << 7) | ((len - 1) << 16)); 1050} 1051 1052static void tcg_out_sextract(TCGContext *s, ARMCond cond, TCGReg rd, 1053 TCGReg rn, int ofs, int len) 1054{ 1055 /* sbfx */ 1056 tcg_out32(s, 0x07a00050 | (cond << 28) | (rd << 12) | rn 1057 | (ofs << 7) | ((len - 1) << 16)); 1058} 1059 1060static void tcg_out_ld32u(TCGContext *s, ARMCond cond, 1061 TCGReg rd, TCGReg rn, int32_t offset) 1062{ 1063 if (offset > 0xfff || offset < -0xfff) { 1064 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1065 tcg_out_ld32_r(s, cond, rd, rn, TCG_REG_TMP); 1066 } else 1067 tcg_out_ld32_12(s, cond, rd, rn, offset); 1068} 1069 1070static void tcg_out_st32(TCGContext *s, ARMCond cond, 1071 TCGReg rd, TCGReg rn, int32_t offset) 1072{ 1073 if (offset > 0xfff || offset < -0xfff) { 1074 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1075 tcg_out_st32_r(s, cond, rd, rn, TCG_REG_TMP); 1076 } else 1077 tcg_out_st32_12(s, cond, rd, rn, offset); 1078} 1079 1080static void tcg_out_ld16u(TCGContext *s, ARMCond cond, 1081 TCGReg rd, TCGReg rn, int32_t offset) 1082{ 1083 if (offset > 0xff || offset < -0xff) { 1084 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1085 tcg_out_ld16u_r(s, cond, rd, rn, TCG_REG_TMP); 1086 } else 1087 tcg_out_ld16u_8(s, cond, rd, rn, offset); 1088} 1089 1090static void tcg_out_ld16s(TCGContext *s, ARMCond cond, 1091 TCGReg rd, TCGReg rn, int32_t offset) 1092{ 1093 if (offset > 0xff || offset < -0xff) { 1094 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1095 tcg_out_ld16s_r(s, cond, rd, rn, TCG_REG_TMP); 1096 } else 1097 tcg_out_ld16s_8(s, cond, rd, rn, offset); 1098} 1099 1100static void tcg_out_st16(TCGContext *s, ARMCond cond, 1101 TCGReg rd, TCGReg rn, int32_t offset) 1102{ 1103 if (offset > 0xff || offset < -0xff) { 1104 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1105 tcg_out_st16_r(s, cond, rd, rn, TCG_REG_TMP); 1106 } else 1107 tcg_out_st16_8(s, cond, rd, rn, offset); 1108} 1109 1110static void tcg_out_ld8u(TCGContext *s, ARMCond cond, 1111 TCGReg rd, TCGReg rn, int32_t offset) 1112{ 1113 if (offset > 0xfff || offset < -0xfff) { 1114 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1115 tcg_out_ld8_r(s, cond, rd, rn, TCG_REG_TMP); 1116 } else 1117 tcg_out_ld8_12(s, cond, rd, rn, offset); 1118} 1119 1120static void tcg_out_ld8s(TCGContext *s, ARMCond cond, 1121 TCGReg rd, TCGReg rn, int32_t offset) 1122{ 1123 if (offset > 0xff || offset < -0xff) { 1124 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1125 tcg_out_ld8s_r(s, cond, rd, rn, TCG_REG_TMP); 1126 } else 1127 tcg_out_ld8s_8(s, cond, rd, rn, offset); 1128} 1129 1130static void tcg_out_st8(TCGContext *s, ARMCond cond, 1131 TCGReg rd, TCGReg rn, int32_t offset) 1132{ 1133 if (offset > 0xfff || offset < -0xfff) { 1134 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1135 tcg_out_st8_r(s, cond, rd, rn, TCG_REG_TMP); 1136 } else 1137 tcg_out_st8_12(s, cond, rd, rn, offset); 1138} 1139 1140/* 1141 * The _goto case is normally between TBs within the same code buffer, and 1142 * with the code buffer limited to 16MB we wouldn't need the long case. 1143 * But we also use it for the tail-call to the qemu_ld/st helpers, which does. 1144 */ 1145static void tcg_out_goto(TCGContext *s, ARMCond cond, const tcg_insn_unit *addr) 1146{ 1147 intptr_t addri = (intptr_t)addr; 1148 ptrdiff_t disp = tcg_pcrel_diff(s, addr); 1149 bool arm_mode = !(addri & 1); 1150 1151 if (arm_mode && disp - 8 < 0x01fffffd && disp - 8 > -0x01fffffd) { 1152 tcg_out_b_imm(s, cond, disp); 1153 return; 1154 } 1155 1156 /* LDR is interworking from v5t. */ 1157 tcg_out_movi_pool(s, cond, TCG_REG_PC, addri); 1158} 1159 1160/* 1161 * The call case is mostly used for helpers - so it's not unreasonable 1162 * for them to be beyond branch range. 1163 */ 1164static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *addr) 1165{ 1166 intptr_t addri = (intptr_t)addr; 1167 ptrdiff_t disp = tcg_pcrel_diff(s, addr); 1168 bool arm_mode = !(addri & 1); 1169 1170 if (disp - 8 < 0x02000000 && disp - 8 >= -0x02000000) { 1171 if (arm_mode) { 1172 tcg_out_bl_imm(s, COND_AL, disp); 1173 } else { 1174 tcg_out_blx_imm(s, disp); 1175 } 1176 return; 1177 } 1178 1179 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri); 1180 tcg_out_blx_reg(s, COND_AL, TCG_REG_TMP); 1181} 1182 1183static void tcg_out_call(TCGContext *s, const tcg_insn_unit *addr, 1184 const TCGHelperInfo *info) 1185{ 1186 tcg_out_call_int(s, addr); 1187} 1188 1189static void tcg_out_goto_label(TCGContext *s, ARMCond cond, TCGLabel *l) 1190{ 1191 if (l->has_value) { 1192 tcg_out_goto(s, cond, l->u.value_ptr); 1193 } else { 1194 tcg_out_reloc(s, s->code_ptr, R_ARM_PC24, l, 0); 1195 tcg_out_b_imm(s, cond, 0); 1196 } 1197} 1198 1199static void tcg_out_mb(TCGContext *s, TCGArg a0) 1200{ 1201 if (use_armv7_instructions) { 1202 tcg_out32(s, INSN_DMB_ISH); 1203 } else { 1204 tcg_out32(s, INSN_DMB_MCR); 1205 } 1206} 1207 1208static TCGCond tcg_out_cmp2(TCGContext *s, const TCGArg *args, 1209 const int *const_args) 1210{ 1211 TCGReg al = args[0]; 1212 TCGReg ah = args[1]; 1213 TCGArg bl = args[2]; 1214 TCGArg bh = args[3]; 1215 TCGCond cond = args[4]; 1216 int const_bl = const_args[2]; 1217 int const_bh = const_args[3]; 1218 1219 switch (cond) { 1220 case TCG_COND_EQ: 1221 case TCG_COND_NE: 1222 case TCG_COND_LTU: 1223 case TCG_COND_LEU: 1224 case TCG_COND_GTU: 1225 case TCG_COND_GEU: 1226 /* We perform a conditional comparision. If the high half is 1227 equal, then overwrite the flags with the comparison of the 1228 low half. The resulting flags cover the whole. */ 1229 tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, ah, bh, const_bh); 1230 tcg_out_dat_rI(s, COND_EQ, ARITH_CMP, 0, al, bl, const_bl); 1231 return cond; 1232 1233 case TCG_COND_LT: 1234 case TCG_COND_GE: 1235 /* We perform a double-word subtraction and examine the result. 1236 We do not actually need the result of the subtract, so the 1237 low part "subtract" is a compare. For the high half we have 1238 no choice but to compute into a temporary. */ 1239 tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, al, bl, const_bl); 1240 tcg_out_dat_rI(s, COND_AL, ARITH_SBC | TO_CPSR, 1241 TCG_REG_TMP, ah, bh, const_bh); 1242 return cond; 1243 1244 case TCG_COND_LE: 1245 case TCG_COND_GT: 1246 /* Similar, but with swapped arguments, via reversed subtract. */ 1247 tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR, 1248 TCG_REG_TMP, al, bl, const_bl); 1249 tcg_out_dat_rI(s, COND_AL, ARITH_RSC | TO_CPSR, 1250 TCG_REG_TMP, ah, bh, const_bh); 1251 return tcg_swap_cond(cond); 1252 1253 default: 1254 g_assert_not_reached(); 1255 } 1256} 1257 1258/* 1259 * Note that TCGReg references Q-registers. 1260 * Q-regno = 2 * D-regno, so shift left by 1 whlie inserting. 1261 */ 1262static uint32_t encode_vd(TCGReg rd) 1263{ 1264 tcg_debug_assert(rd >= TCG_REG_Q0); 1265 return (extract32(rd, 3, 1) << 22) | (extract32(rd, 0, 3) << 13); 1266} 1267 1268static uint32_t encode_vn(TCGReg rn) 1269{ 1270 tcg_debug_assert(rn >= TCG_REG_Q0); 1271 return (extract32(rn, 3, 1) << 7) | (extract32(rn, 0, 3) << 17); 1272} 1273 1274static uint32_t encode_vm(TCGReg rm) 1275{ 1276 tcg_debug_assert(rm >= TCG_REG_Q0); 1277 return (extract32(rm, 3, 1) << 5) | (extract32(rm, 0, 3) << 1); 1278} 1279 1280static void tcg_out_vreg2(TCGContext *s, ARMInsn insn, int q, int vece, 1281 TCGReg d, TCGReg m) 1282{ 1283 tcg_out32(s, insn | (vece << 18) | (q << 6) | 1284 encode_vd(d) | encode_vm(m)); 1285} 1286 1287static void tcg_out_vreg3(TCGContext *s, ARMInsn insn, int q, int vece, 1288 TCGReg d, TCGReg n, TCGReg m) 1289{ 1290 tcg_out32(s, insn | (vece << 20) | (q << 6) | 1291 encode_vd(d) | encode_vn(n) | encode_vm(m)); 1292} 1293 1294static void tcg_out_vmovi(TCGContext *s, TCGReg rd, 1295 int q, int op, int cmode, uint8_t imm8) 1296{ 1297 tcg_out32(s, INSN_VMOVI | encode_vd(rd) | (q << 6) | (op << 5) 1298 | (cmode << 8) | extract32(imm8, 0, 4) 1299 | (extract32(imm8, 4, 3) << 16) 1300 | (extract32(imm8, 7, 1) << 24)); 1301} 1302 1303static void tcg_out_vshifti(TCGContext *s, ARMInsn insn, int q, 1304 TCGReg rd, TCGReg rm, int l_imm6) 1305{ 1306 tcg_out32(s, insn | (q << 6) | encode_vd(rd) | encode_vm(rm) | 1307 (extract32(l_imm6, 6, 1) << 7) | 1308 (extract32(l_imm6, 0, 6) << 16)); 1309} 1310 1311static void tcg_out_vldst(TCGContext *s, ARMInsn insn, 1312 TCGReg rd, TCGReg rn, int offset) 1313{ 1314 if (offset != 0) { 1315 if (check_fit_imm(offset) || check_fit_imm(-offset)) { 1316 tcg_out_dat_rIN(s, COND_AL, ARITH_ADD, ARITH_SUB, 1317 TCG_REG_TMP, rn, offset, true); 1318 } else { 1319 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, offset); 1320 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, 1321 TCG_REG_TMP, TCG_REG_TMP, rn, 0); 1322 } 1323 rn = TCG_REG_TMP; 1324 } 1325 tcg_out32(s, insn | (rn << 16) | encode_vd(rd) | 0xf); 1326} 1327 1328typedef struct { 1329 ARMCond cond; 1330 TCGReg base; 1331 int index; 1332 bool index_scratch; 1333} HostAddress; 1334 1335#ifdef CONFIG_SOFTMMU 1336static TCGReg ldst_ra_gen(TCGContext *s, const TCGLabelQemuLdst *l, int arg) 1337{ 1338 /* We arrive at the slow path via "BLNE", so R14 contains l->raddr. */ 1339 return TCG_REG_R14; 1340} 1341 1342static const TCGLdstHelperParam ldst_helper_param = { 1343 .ra_gen = ldst_ra_gen, 1344 .ntmp = 1, 1345 .tmp = { TCG_REG_TMP }, 1346}; 1347 1348static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1349{ 1350 MemOp opc = get_memop(lb->oi); 1351 1352 if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1353 return false; 1354 } 1355 1356 tcg_out_ld_helper_args(s, lb, &ldst_helper_param); 1357 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE]); 1358 tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param); 1359 1360 tcg_out_goto(s, COND_AL, lb->raddr); 1361 return true; 1362} 1363 1364static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1365{ 1366 MemOp opc = get_memop(lb->oi); 1367 1368 if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1369 return false; 1370 } 1371 1372 tcg_out_st_helper_args(s, lb, &ldst_helper_param); 1373 1374 /* Tail-call to the helper, which will return to the fast path. */ 1375 tcg_out_goto(s, COND_AL, qemu_st_helpers[opc & MO_SIZE]); 1376 return true; 1377} 1378#else 1379static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) 1380{ 1381 if (!reloc_pc24(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1382 return false; 1383 } 1384 1385 if (TARGET_LONG_BITS == 64) { 1386 /* 64-bit target address is aligned into R2:R3. */ 1387 TCGMovExtend ext[2] = { 1388 { .dst = TCG_REG_R2, .dst_type = TCG_TYPE_I32, 1389 .src = l->addrlo_reg, 1390 .src_type = TCG_TYPE_I32, .src_ext = MO_UL }, 1391 { .dst = TCG_REG_R3, .dst_type = TCG_TYPE_I32, 1392 .src = l->addrhi_reg, 1393 .src_type = TCG_TYPE_I32, .src_ext = MO_UL }, 1394 }; 1395 tcg_out_movext2(s, &ext[0], &ext[1], TCG_REG_TMP); 1396 } else { 1397 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R1, l->addrlo_reg); 1398 } 1399 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_AREG0); 1400 1401 /* 1402 * Tail call to the helper, with the return address back inline, 1403 * just for the clarity of the debugging traceback -- the helper 1404 * cannot return. We have used BLNE to arrive here, so LR is 1405 * already set. 1406 */ 1407 tcg_out_goto(s, COND_AL, (const void *) 1408 (l->is_ld ? helper_unaligned_ld : helper_unaligned_st)); 1409 return true; 1410} 1411 1412static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1413{ 1414 return tcg_out_fail_alignment(s, l); 1415} 1416 1417static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1418{ 1419 return tcg_out_fail_alignment(s, l); 1420} 1421#endif /* SOFTMMU */ 1422 1423static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1424 TCGReg addrlo, TCGReg addrhi, 1425 MemOpIdx oi, bool is_ld) 1426{ 1427 TCGLabelQemuLdst *ldst = NULL; 1428 MemOp opc = get_memop(oi); 1429 MemOp a_bits = get_alignment_bits(opc); 1430 unsigned a_mask = (1 << a_bits) - 1; 1431 1432#ifdef CONFIG_SOFTMMU 1433 int mem_index = get_mmuidx(oi); 1434 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read) 1435 : offsetof(CPUTLBEntry, addr_write); 1436 int fast_off = TLB_MASK_TABLE_OFS(mem_index); 1437 unsigned s_mask = (1 << (opc & MO_SIZE)) - 1; 1438 TCGReg t_addr; 1439 1440 ldst = new_ldst_label(s); 1441 ldst->is_ld = is_ld; 1442 ldst->oi = oi; 1443 ldst->addrlo_reg = addrlo; 1444 ldst->addrhi_reg = addrhi; 1445 1446 /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {r0,r1}. */ 1447 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); 1448 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -256); 1449 QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0); 1450 QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != 4); 1451 tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off); 1452 1453 /* Extract the tlb index from the address into R0. */ 1454 tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, addrlo, 1455 SHIFT_IMM_LSR(TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS)); 1456 1457 /* 1458 * Add the tlb_table pointer, creating the CPUTLBEntry address in R1. 1459 * Load the tlb comparator into R2/R3 and the fast path addend into R1. 1460 */ 1461 if (cmp_off == 0) { 1462 if (TARGET_LONG_BITS == 64) { 1463 tcg_out_ldrd_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0); 1464 } else { 1465 tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0); 1466 } 1467 } else { 1468 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, 1469 TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0); 1470 if (TARGET_LONG_BITS == 64) { 1471 tcg_out_ldrd_8(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); 1472 } else { 1473 tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); 1474 } 1475 } 1476 1477 /* Load the tlb addend. */ 1478 tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R1, 1479 offsetof(CPUTLBEntry, addend)); 1480 1481 /* 1482 * Check alignment, check comparators. 1483 * Do this in 2-4 insns. Use MOVW for v7, if possible, 1484 * to reduce the number of sequential conditional instructions. 1485 * Almost all guests have at least 4k pages, which means that we need 1486 * to clear at least 9 bits even for an 8-byte memory, which means it 1487 * isn't worth checking for an immediate operand for BIC. 1488 * 1489 * For unaligned accesses, test the page of the last unit of alignment. 1490 * This leaves the least significant alignment bits unchanged, and of 1491 * course must be zero. 1492 */ 1493 t_addr = addrlo; 1494 if (a_mask < s_mask) { 1495 t_addr = TCG_REG_R0; 1496 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, t_addr, 1497 addrlo, s_mask - a_mask); 1498 } 1499 if (use_armv7_instructions && TARGET_PAGE_BITS <= 16) { 1500 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, ~(TARGET_PAGE_MASK | a_mask)); 1501 tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP, 1502 t_addr, TCG_REG_TMP, 0); 1503 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R2, TCG_REG_TMP, 0); 1504 } else { 1505 if (a_mask) { 1506 tcg_debug_assert(a_mask <= 0xff); 1507 tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask); 1508 } 1509 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, t_addr, 1510 SHIFT_IMM_LSR(TARGET_PAGE_BITS)); 1511 tcg_out_dat_reg(s, (a_mask ? COND_EQ : COND_AL), ARITH_CMP, 1512 0, TCG_REG_R2, TCG_REG_TMP, 1513 SHIFT_IMM_LSL(TARGET_PAGE_BITS)); 1514 } 1515 1516 if (TARGET_LONG_BITS == 64) { 1517 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R3, addrhi, 0); 1518 } 1519 1520 *h = (HostAddress){ 1521 .cond = COND_AL, 1522 .base = addrlo, 1523 .index = TCG_REG_R1, 1524 .index_scratch = true, 1525 }; 1526#else 1527 if (a_mask) { 1528 ldst = new_ldst_label(s); 1529 ldst->is_ld = is_ld; 1530 ldst->oi = oi; 1531 ldst->addrlo_reg = addrlo; 1532 ldst->addrhi_reg = addrhi; 1533 1534 /* We are expecting a_bits to max out at 7 */ 1535 tcg_debug_assert(a_mask <= 0xff); 1536 /* tst addr, #mask */ 1537 tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask); 1538 } 1539 1540 *h = (HostAddress){ 1541 .cond = COND_AL, 1542 .base = addrlo, 1543 .index = guest_base ? TCG_REG_GUEST_BASE : -1, 1544 .index_scratch = false, 1545 }; 1546#endif 1547 1548 return ldst; 1549} 1550 1551static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo, 1552 TCGReg datahi, HostAddress h) 1553{ 1554 TCGReg base; 1555 1556 /* Byte swapping is left to middle-end expansion. */ 1557 tcg_debug_assert((opc & MO_BSWAP) == 0); 1558 1559 switch (opc & MO_SSIZE) { 1560 case MO_UB: 1561 if (h.index < 0) { 1562 tcg_out_ld8_12(s, h.cond, datalo, h.base, 0); 1563 } else { 1564 tcg_out_ld8_r(s, h.cond, datalo, h.base, h.index); 1565 } 1566 break; 1567 case MO_SB: 1568 if (h.index < 0) { 1569 tcg_out_ld8s_8(s, h.cond, datalo, h.base, 0); 1570 } else { 1571 tcg_out_ld8s_r(s, h.cond, datalo, h.base, h.index); 1572 } 1573 break; 1574 case MO_UW: 1575 if (h.index < 0) { 1576 tcg_out_ld16u_8(s, h.cond, datalo, h.base, 0); 1577 } else { 1578 tcg_out_ld16u_r(s, h.cond, datalo, h.base, h.index); 1579 } 1580 break; 1581 case MO_SW: 1582 if (h.index < 0) { 1583 tcg_out_ld16s_8(s, h.cond, datalo, h.base, 0); 1584 } else { 1585 tcg_out_ld16s_r(s, h.cond, datalo, h.base, h.index); 1586 } 1587 break; 1588 case MO_UL: 1589 if (h.index < 0) { 1590 tcg_out_ld32_12(s, h.cond, datalo, h.base, 0); 1591 } else { 1592 tcg_out_ld32_r(s, h.cond, datalo, h.base, h.index); 1593 } 1594 break; 1595 case MO_UQ: 1596 /* We used pair allocation for datalo, so already should be aligned. */ 1597 tcg_debug_assert((datalo & 1) == 0); 1598 tcg_debug_assert(datahi == datalo + 1); 1599 /* LDRD requires alignment; double-check that. */ 1600 if (get_alignment_bits(opc) >= MO_64) { 1601 if (h.index < 0) { 1602 tcg_out_ldrd_8(s, h.cond, datalo, h.base, 0); 1603 break; 1604 } 1605 /* 1606 * Rm (the second address op) must not overlap Rt or Rt + 1. 1607 * Since datalo is aligned, we can simplify the test via alignment. 1608 * Flip the two address arguments if that works. 1609 */ 1610 if ((h.index & ~1) != datalo) { 1611 tcg_out_ldrd_r(s, h.cond, datalo, h.base, h.index); 1612 break; 1613 } 1614 if ((h.base & ~1) != datalo) { 1615 tcg_out_ldrd_r(s, h.cond, datalo, h.index, h.base); 1616 break; 1617 } 1618 } 1619 if (h.index < 0) { 1620 base = h.base; 1621 if (datalo == h.base) { 1622 tcg_out_mov_reg(s, h.cond, TCG_REG_TMP, base); 1623 base = TCG_REG_TMP; 1624 } 1625 } else if (h.index_scratch) { 1626 tcg_out_ld32_rwb(s, h.cond, datalo, h.index, h.base); 1627 tcg_out_ld32_12(s, h.cond, datahi, h.index, 4); 1628 break; 1629 } else { 1630 tcg_out_dat_reg(s, h.cond, ARITH_ADD, TCG_REG_TMP, 1631 h.base, h.index, SHIFT_IMM_LSL(0)); 1632 base = TCG_REG_TMP; 1633 } 1634 tcg_out_ld32_12(s, h.cond, datalo, base, 0); 1635 tcg_out_ld32_12(s, h.cond, datahi, base, 4); 1636 break; 1637 default: 1638 g_assert_not_reached(); 1639 } 1640} 1641 1642static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, 1643 TCGReg addrlo, TCGReg addrhi, 1644 MemOpIdx oi, TCGType data_type) 1645{ 1646 MemOp opc = get_memop(oi); 1647 TCGLabelQemuLdst *ldst; 1648 HostAddress h; 1649 1650 ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, true); 1651 if (ldst) { 1652 ldst->type = data_type; 1653 ldst->datalo_reg = datalo; 1654 ldst->datahi_reg = datahi; 1655 1656 /* 1657 * This a conditional BL only to load a pointer within this 1658 * opcode into LR for the slow path. We will not be using 1659 * the value for a tail call. 1660 */ 1661 ldst->label_ptr[0] = s->code_ptr; 1662 tcg_out_bl_imm(s, COND_NE, 0); 1663 1664 tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); 1665 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1666 } else { 1667 tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); 1668 } 1669} 1670 1671static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo, 1672 TCGReg datahi, HostAddress h) 1673{ 1674 /* Byte swapping is left to middle-end expansion. */ 1675 tcg_debug_assert((opc & MO_BSWAP) == 0); 1676 1677 switch (opc & MO_SIZE) { 1678 case MO_8: 1679 if (h.index < 0) { 1680 tcg_out_st8_12(s, h.cond, datalo, h.base, 0); 1681 } else { 1682 tcg_out_st8_r(s, h.cond, datalo, h.base, h.index); 1683 } 1684 break; 1685 case MO_16: 1686 if (h.index < 0) { 1687 tcg_out_st16_8(s, h.cond, datalo, h.base, 0); 1688 } else { 1689 tcg_out_st16_r(s, h.cond, datalo, h.base, h.index); 1690 } 1691 break; 1692 case MO_32: 1693 if (h.index < 0) { 1694 tcg_out_st32_12(s, h.cond, datalo, h.base, 0); 1695 } else { 1696 tcg_out_st32_r(s, h.cond, datalo, h.base, h.index); 1697 } 1698 break; 1699 case MO_64: 1700 /* We used pair allocation for datalo, so already should be aligned. */ 1701 tcg_debug_assert((datalo & 1) == 0); 1702 tcg_debug_assert(datahi == datalo + 1); 1703 /* STRD requires alignment; double-check that. */ 1704 if (get_alignment_bits(opc) >= MO_64) { 1705 if (h.index < 0) { 1706 tcg_out_strd_8(s, h.cond, datalo, h.base, 0); 1707 } else { 1708 tcg_out_strd_r(s, h.cond, datalo, h.base, h.index); 1709 } 1710 } else if (h.index_scratch) { 1711 tcg_out_st32_rwb(s, h.cond, datalo, h.index, h.base); 1712 tcg_out_st32_12(s, h.cond, datahi, h.index, 4); 1713 } else { 1714 tcg_out_dat_reg(s, h.cond, ARITH_ADD, TCG_REG_TMP, 1715 h.base, h.index, SHIFT_IMM_LSL(0)); 1716 tcg_out_st32_12(s, h.cond, datalo, TCG_REG_TMP, 0); 1717 tcg_out_st32_12(s, h.cond, datahi, TCG_REG_TMP, 4); 1718 } 1719 break; 1720 default: 1721 g_assert_not_reached(); 1722 } 1723} 1724 1725static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, 1726 TCGReg addrlo, TCGReg addrhi, 1727 MemOpIdx oi, TCGType data_type) 1728{ 1729 MemOp opc = get_memop(oi); 1730 TCGLabelQemuLdst *ldst; 1731 HostAddress h; 1732 1733 ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, false); 1734 if (ldst) { 1735 ldst->type = data_type; 1736 ldst->datalo_reg = datalo; 1737 ldst->datahi_reg = datahi; 1738 1739 h.cond = COND_EQ; 1740 tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); 1741 1742 /* The conditional call is last, as we're going to return here. */ 1743 ldst->label_ptr[0] = s->code_ptr; 1744 tcg_out_bl_imm(s, COND_NE, 0); 1745 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1746 } else { 1747 tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); 1748 } 1749} 1750 1751static void tcg_out_epilogue(TCGContext *s); 1752 1753static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg) 1754{ 1755 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, arg); 1756 tcg_out_epilogue(s); 1757} 1758 1759static void tcg_out_goto_tb(TCGContext *s, int which) 1760{ 1761 uintptr_t i_addr; 1762 intptr_t i_disp; 1763 1764 /* Direct branch will be patched by tb_target_set_jmp_target. */ 1765 set_jmp_insn_offset(s, which); 1766 tcg_out32(s, INSN_NOP); 1767 1768 /* When branch is out of range, fall through to indirect. */ 1769 i_addr = get_jmp_target_addr(s, which); 1770 i_disp = tcg_pcrel_diff(s, (void *)i_addr) - 8; 1771 tcg_debug_assert(i_disp < 0); 1772 if (i_disp >= -0xfff) { 1773 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, i_disp); 1774 } else { 1775 /* 1776 * The TB is close, but outside the 12 bits addressable by 1777 * the load. We can extend this to 20 bits with a sub of a 1778 * shifted immediate from pc. 1779 */ 1780 int h = -i_disp; 1781 int l = h & 0xfff; 1782 1783 h = encode_imm_nofail(h - l); 1784 tcg_out_dat_imm(s, COND_AL, ARITH_SUB, TCG_REG_R0, TCG_REG_PC, h); 1785 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_R0, l); 1786 } 1787 set_jmp_reset_offset(s, which); 1788} 1789 1790void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1791 uintptr_t jmp_rx, uintptr_t jmp_rw) 1792{ 1793 uintptr_t addr = tb->jmp_target_addr[n]; 1794 ptrdiff_t offset = addr - (jmp_rx + 8); 1795 tcg_insn_unit insn; 1796 1797 /* Either directly branch, or fall through to indirect branch. */ 1798 if (offset == sextract64(offset, 0, 26)) { 1799 /* B <addr> */ 1800 insn = deposit32((COND_AL << 28) | INSN_B, 0, 24, offset >> 2); 1801 } else { 1802 insn = INSN_NOP; 1803 } 1804 1805 qatomic_set((uint32_t *)jmp_rw, insn); 1806 flush_idcache_range(jmp_rx, jmp_rw, 4); 1807} 1808 1809static void tcg_out_op(TCGContext *s, TCGOpcode opc, 1810 const TCGArg args[TCG_MAX_OP_ARGS], 1811 const int const_args[TCG_MAX_OP_ARGS]) 1812{ 1813 TCGArg a0, a1, a2, a3, a4, a5; 1814 int c; 1815 1816 switch (opc) { 1817 case INDEX_op_goto_ptr: 1818 tcg_out_b_reg(s, COND_AL, args[0]); 1819 break; 1820 case INDEX_op_br: 1821 tcg_out_goto_label(s, COND_AL, arg_label(args[0])); 1822 break; 1823 1824 case INDEX_op_ld8u_i32: 1825 tcg_out_ld8u(s, COND_AL, args[0], args[1], args[2]); 1826 break; 1827 case INDEX_op_ld8s_i32: 1828 tcg_out_ld8s(s, COND_AL, args[0], args[1], args[2]); 1829 break; 1830 case INDEX_op_ld16u_i32: 1831 tcg_out_ld16u(s, COND_AL, args[0], args[1], args[2]); 1832 break; 1833 case INDEX_op_ld16s_i32: 1834 tcg_out_ld16s(s, COND_AL, args[0], args[1], args[2]); 1835 break; 1836 case INDEX_op_ld_i32: 1837 tcg_out_ld32u(s, COND_AL, args[0], args[1], args[2]); 1838 break; 1839 case INDEX_op_st8_i32: 1840 tcg_out_st8(s, COND_AL, args[0], args[1], args[2]); 1841 break; 1842 case INDEX_op_st16_i32: 1843 tcg_out_st16(s, COND_AL, args[0], args[1], args[2]); 1844 break; 1845 case INDEX_op_st_i32: 1846 tcg_out_st32(s, COND_AL, args[0], args[1], args[2]); 1847 break; 1848 1849 case INDEX_op_movcond_i32: 1850 /* Constraints mean that v2 is always in the same register as dest, 1851 * so we only need to do "if condition passed, move v1 to dest". 1852 */ 1853 tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, 1854 args[1], args[2], const_args[2]); 1855 tcg_out_dat_rIK(s, tcg_cond_to_arm_cond[args[5]], ARITH_MOV, 1856 ARITH_MVN, args[0], 0, args[3], const_args[3]); 1857 break; 1858 case INDEX_op_add_i32: 1859 tcg_out_dat_rIN(s, COND_AL, ARITH_ADD, ARITH_SUB, 1860 args[0], args[1], args[2], const_args[2]); 1861 break; 1862 case INDEX_op_sub_i32: 1863 if (const_args[1]) { 1864 if (const_args[2]) { 1865 tcg_out_movi32(s, COND_AL, args[0], args[1] - args[2]); 1866 } else { 1867 tcg_out_dat_rI(s, COND_AL, ARITH_RSB, 1868 args[0], args[2], args[1], 1); 1869 } 1870 } else { 1871 tcg_out_dat_rIN(s, COND_AL, ARITH_SUB, ARITH_ADD, 1872 args[0], args[1], args[2], const_args[2]); 1873 } 1874 break; 1875 case INDEX_op_and_i32: 1876 tcg_out_dat_rIK(s, COND_AL, ARITH_AND, ARITH_BIC, 1877 args[0], args[1], args[2], const_args[2]); 1878 break; 1879 case INDEX_op_andc_i32: 1880 tcg_out_dat_rIK(s, COND_AL, ARITH_BIC, ARITH_AND, 1881 args[0], args[1], args[2], const_args[2]); 1882 break; 1883 case INDEX_op_or_i32: 1884 c = ARITH_ORR; 1885 goto gen_arith; 1886 case INDEX_op_xor_i32: 1887 c = ARITH_EOR; 1888 /* Fall through. */ 1889 gen_arith: 1890 tcg_out_dat_rI(s, COND_AL, c, args[0], args[1], args[2], const_args[2]); 1891 break; 1892 case INDEX_op_add2_i32: 1893 a0 = args[0], a1 = args[1], a2 = args[2]; 1894 a3 = args[3], a4 = args[4], a5 = args[5]; 1895 if (a0 == a3 || (a0 == a5 && !const_args[5])) { 1896 a0 = TCG_REG_TMP; 1897 } 1898 tcg_out_dat_rIN(s, COND_AL, ARITH_ADD | TO_CPSR, ARITH_SUB | TO_CPSR, 1899 a0, a2, a4, const_args[4]); 1900 tcg_out_dat_rIK(s, COND_AL, ARITH_ADC, ARITH_SBC, 1901 a1, a3, a5, const_args[5]); 1902 tcg_out_mov_reg(s, COND_AL, args[0], a0); 1903 break; 1904 case INDEX_op_sub2_i32: 1905 a0 = args[0], a1 = args[1], a2 = args[2]; 1906 a3 = args[3], a4 = args[4], a5 = args[5]; 1907 if ((a0 == a3 && !const_args[3]) || (a0 == a5 && !const_args[5])) { 1908 a0 = TCG_REG_TMP; 1909 } 1910 if (const_args[2]) { 1911 if (const_args[4]) { 1912 tcg_out_movi32(s, COND_AL, a0, a4); 1913 a4 = a0; 1914 } 1915 tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR, a0, a4, a2, 1); 1916 } else { 1917 tcg_out_dat_rIN(s, COND_AL, ARITH_SUB | TO_CPSR, 1918 ARITH_ADD | TO_CPSR, a0, a2, a4, const_args[4]); 1919 } 1920 if (const_args[3]) { 1921 if (const_args[5]) { 1922 tcg_out_movi32(s, COND_AL, a1, a5); 1923 a5 = a1; 1924 } 1925 tcg_out_dat_rI(s, COND_AL, ARITH_RSC, a1, a5, a3, 1); 1926 } else { 1927 tcg_out_dat_rIK(s, COND_AL, ARITH_SBC, ARITH_ADC, 1928 a1, a3, a5, const_args[5]); 1929 } 1930 tcg_out_mov_reg(s, COND_AL, args[0], a0); 1931 break; 1932 case INDEX_op_neg_i32: 1933 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, args[0], args[1], 0); 1934 break; 1935 case INDEX_op_not_i32: 1936 tcg_out_dat_reg(s, COND_AL, 1937 ARITH_MVN, args[0], 0, args[1], SHIFT_IMM_LSL(0)); 1938 break; 1939 case INDEX_op_mul_i32: 1940 tcg_out_mul32(s, COND_AL, args[0], args[1], args[2]); 1941 break; 1942 case INDEX_op_mulu2_i32: 1943 tcg_out_umull32(s, COND_AL, args[0], args[1], args[2], args[3]); 1944 break; 1945 case INDEX_op_muls2_i32: 1946 tcg_out_smull32(s, COND_AL, args[0], args[1], args[2], args[3]); 1947 break; 1948 /* XXX: Perhaps args[2] & 0x1f is wrong */ 1949 case INDEX_op_shl_i32: 1950 c = const_args[2] ? 1951 SHIFT_IMM_LSL(args[2] & 0x1f) : SHIFT_REG_LSL(args[2]); 1952 goto gen_shift32; 1953 case INDEX_op_shr_i32: 1954 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_LSR(args[2] & 0x1f) : 1955 SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args[2]); 1956 goto gen_shift32; 1957 case INDEX_op_sar_i32: 1958 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ASR(args[2] & 0x1f) : 1959 SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args[2]); 1960 goto gen_shift32; 1961 case INDEX_op_rotr_i32: 1962 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ROR(args[2] & 0x1f) : 1963 SHIFT_IMM_LSL(0) : SHIFT_REG_ROR(args[2]); 1964 /* Fall through. */ 1965 gen_shift32: 1966 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], c); 1967 break; 1968 1969 case INDEX_op_rotl_i32: 1970 if (const_args[2]) { 1971 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], 1972 ((0x20 - args[2]) & 0x1f) ? 1973 SHIFT_IMM_ROR((0x20 - args[2]) & 0x1f) : 1974 SHIFT_IMM_LSL(0)); 1975 } else { 1976 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, TCG_REG_TMP, args[2], 0x20); 1977 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], 1978 SHIFT_REG_ROR(TCG_REG_TMP)); 1979 } 1980 break; 1981 1982 case INDEX_op_ctz_i32: 1983 tcg_out_dat_reg(s, COND_AL, INSN_RBIT, TCG_REG_TMP, 0, args[1], 0); 1984 a1 = TCG_REG_TMP; 1985 goto do_clz; 1986 1987 case INDEX_op_clz_i32: 1988 a1 = args[1]; 1989 do_clz: 1990 a0 = args[0]; 1991 a2 = args[2]; 1992 c = const_args[2]; 1993 if (c && a2 == 32) { 1994 tcg_out_dat_reg(s, COND_AL, INSN_CLZ, a0, 0, a1, 0); 1995 break; 1996 } 1997 tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0, a1, 0); 1998 tcg_out_dat_reg(s, COND_NE, INSN_CLZ, a0, 0, a1, 0); 1999 if (c || a0 != a2) { 2000 tcg_out_dat_rIK(s, COND_EQ, ARITH_MOV, ARITH_MVN, a0, 0, a2, c); 2001 } 2002 break; 2003 2004 case INDEX_op_brcond_i32: 2005 tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, 2006 args[0], args[1], const_args[1]); 2007 tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[2]], 2008 arg_label(args[3])); 2009 break; 2010 case INDEX_op_setcond_i32: 2011 tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, 2012 args[1], args[2], const_args[2]); 2013 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[3]], 2014 ARITH_MOV, args[0], 0, 1); 2015 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[3])], 2016 ARITH_MOV, args[0], 0, 0); 2017 break; 2018 2019 case INDEX_op_brcond2_i32: 2020 c = tcg_out_cmp2(s, args, const_args); 2021 tcg_out_goto_label(s, tcg_cond_to_arm_cond[c], arg_label(args[5])); 2022 break; 2023 case INDEX_op_setcond2_i32: 2024 c = tcg_out_cmp2(s, args + 1, const_args + 1); 2025 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[c], ARITH_MOV, args[0], 0, 1); 2026 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(c)], 2027 ARITH_MOV, args[0], 0, 0); 2028 break; 2029 2030 case INDEX_op_qemu_ld_i32: 2031 if (TARGET_LONG_BITS == 32) { 2032 tcg_out_qemu_ld(s, args[0], -1, args[1], -1, 2033 args[2], TCG_TYPE_I32); 2034 } else { 2035 tcg_out_qemu_ld(s, args[0], -1, args[1], args[2], 2036 args[3], TCG_TYPE_I32); 2037 } 2038 break; 2039 case INDEX_op_qemu_ld_i64: 2040 if (TARGET_LONG_BITS == 32) { 2041 tcg_out_qemu_ld(s, args[0], args[1], args[2], -1, 2042 args[3], TCG_TYPE_I64); 2043 } else { 2044 tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3], 2045 args[4], TCG_TYPE_I64); 2046 } 2047 break; 2048 case INDEX_op_qemu_st_i32: 2049 if (TARGET_LONG_BITS == 32) { 2050 tcg_out_qemu_st(s, args[0], -1, args[1], -1, 2051 args[2], TCG_TYPE_I32); 2052 } else { 2053 tcg_out_qemu_st(s, args[0], -1, args[1], args[2], 2054 args[3], TCG_TYPE_I32); 2055 } 2056 break; 2057 case INDEX_op_qemu_st_i64: 2058 if (TARGET_LONG_BITS == 32) { 2059 tcg_out_qemu_st(s, args[0], args[1], args[2], -1, 2060 args[3], TCG_TYPE_I64); 2061 } else { 2062 tcg_out_qemu_st(s, args[0], args[1], args[2], args[3], 2063 args[4], TCG_TYPE_I64); 2064 } 2065 break; 2066 2067 case INDEX_op_bswap16_i32: 2068 tcg_out_bswap16(s, COND_AL, args[0], args[1], args[2]); 2069 break; 2070 case INDEX_op_bswap32_i32: 2071 tcg_out_bswap32(s, COND_AL, args[0], args[1]); 2072 break; 2073 2074 case INDEX_op_deposit_i32: 2075 tcg_out_deposit(s, COND_AL, args[0], args[2], 2076 args[3], args[4], const_args[2]); 2077 break; 2078 case INDEX_op_extract_i32: 2079 tcg_out_extract(s, COND_AL, args[0], args[1], args[2], args[3]); 2080 break; 2081 case INDEX_op_sextract_i32: 2082 tcg_out_sextract(s, COND_AL, args[0], args[1], args[2], args[3]); 2083 break; 2084 case INDEX_op_extract2_i32: 2085 /* ??? These optimization vs zero should be generic. */ 2086 /* ??? But we can't substitute 2 for 1 in the opcode stream yet. */ 2087 if (const_args[1]) { 2088 if (const_args[2]) { 2089 tcg_out_movi(s, TCG_TYPE_REG, args[0], 0); 2090 } else { 2091 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, 2092 args[2], SHIFT_IMM_LSL(32 - args[3])); 2093 } 2094 } else if (const_args[2]) { 2095 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, 2096 args[1], SHIFT_IMM_LSR(args[3])); 2097 } else { 2098 /* We can do extract2 in 2 insns, vs the 3 required otherwise. */ 2099 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, 2100 args[2], SHIFT_IMM_LSL(32 - args[3])); 2101 tcg_out_dat_reg(s, COND_AL, ARITH_ORR, args[0], TCG_REG_TMP, 2102 args[1], SHIFT_IMM_LSR(args[3])); 2103 } 2104 break; 2105 2106 case INDEX_op_div_i32: 2107 tcg_out_sdiv(s, COND_AL, args[0], args[1], args[2]); 2108 break; 2109 case INDEX_op_divu_i32: 2110 tcg_out_udiv(s, COND_AL, args[0], args[1], args[2]); 2111 break; 2112 2113 case INDEX_op_mb: 2114 tcg_out_mb(s, args[0]); 2115 break; 2116 2117 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ 2118 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2119 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2120 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2121 case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ 2122 case INDEX_op_ext8u_i32: 2123 case INDEX_op_ext16s_i32: 2124 case INDEX_op_ext16u_i32: 2125 default: 2126 g_assert_not_reached(); 2127 } 2128} 2129 2130static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) 2131{ 2132 switch (op) { 2133 case INDEX_op_goto_ptr: 2134 return C_O0_I1(r); 2135 2136 case INDEX_op_ld8u_i32: 2137 case INDEX_op_ld8s_i32: 2138 case INDEX_op_ld16u_i32: 2139 case INDEX_op_ld16s_i32: 2140 case INDEX_op_ld_i32: 2141 case INDEX_op_neg_i32: 2142 case INDEX_op_not_i32: 2143 case INDEX_op_bswap16_i32: 2144 case INDEX_op_bswap32_i32: 2145 case INDEX_op_ext8s_i32: 2146 case INDEX_op_ext16s_i32: 2147 case INDEX_op_ext16u_i32: 2148 case INDEX_op_extract_i32: 2149 case INDEX_op_sextract_i32: 2150 return C_O1_I1(r, r); 2151 2152 case INDEX_op_st8_i32: 2153 case INDEX_op_st16_i32: 2154 case INDEX_op_st_i32: 2155 return C_O0_I2(r, r); 2156 2157 case INDEX_op_add_i32: 2158 case INDEX_op_sub_i32: 2159 case INDEX_op_setcond_i32: 2160 return C_O1_I2(r, r, rIN); 2161 2162 case INDEX_op_and_i32: 2163 case INDEX_op_andc_i32: 2164 case INDEX_op_clz_i32: 2165 case INDEX_op_ctz_i32: 2166 return C_O1_I2(r, r, rIK); 2167 2168 case INDEX_op_mul_i32: 2169 case INDEX_op_div_i32: 2170 case INDEX_op_divu_i32: 2171 return C_O1_I2(r, r, r); 2172 2173 case INDEX_op_mulu2_i32: 2174 case INDEX_op_muls2_i32: 2175 return C_O2_I2(r, r, r, r); 2176 2177 case INDEX_op_or_i32: 2178 case INDEX_op_xor_i32: 2179 return C_O1_I2(r, r, rI); 2180 2181 case INDEX_op_shl_i32: 2182 case INDEX_op_shr_i32: 2183 case INDEX_op_sar_i32: 2184 case INDEX_op_rotl_i32: 2185 case INDEX_op_rotr_i32: 2186 return C_O1_I2(r, r, ri); 2187 2188 case INDEX_op_brcond_i32: 2189 return C_O0_I2(r, rIN); 2190 case INDEX_op_deposit_i32: 2191 return C_O1_I2(r, 0, rZ); 2192 case INDEX_op_extract2_i32: 2193 return C_O1_I2(r, rZ, rZ); 2194 case INDEX_op_movcond_i32: 2195 return C_O1_I4(r, r, rIN, rIK, 0); 2196 case INDEX_op_add2_i32: 2197 return C_O2_I4(r, r, r, r, rIN, rIK); 2198 case INDEX_op_sub2_i32: 2199 return C_O2_I4(r, r, rI, rI, rIN, rIK); 2200 case INDEX_op_brcond2_i32: 2201 return C_O0_I4(r, r, rI, rI); 2202 case INDEX_op_setcond2_i32: 2203 return C_O1_I4(r, r, r, rI, rI); 2204 2205 case INDEX_op_qemu_ld_i32: 2206 return TARGET_LONG_BITS == 32 ? C_O1_I1(r, l) : C_O1_I2(r, l, l); 2207 case INDEX_op_qemu_ld_i64: 2208 return TARGET_LONG_BITS == 32 ? C_O2_I1(e, p, l) : C_O2_I2(e, p, l, l); 2209 case INDEX_op_qemu_st_i32: 2210 return TARGET_LONG_BITS == 32 ? C_O0_I2(s, s) : C_O0_I3(s, s, s); 2211 case INDEX_op_qemu_st_i64: 2212 return TARGET_LONG_BITS == 32 ? C_O0_I3(S, p, s) : C_O0_I4(S, p, s, s); 2213 2214 case INDEX_op_st_vec: 2215 return C_O0_I2(w, r); 2216 case INDEX_op_ld_vec: 2217 case INDEX_op_dupm_vec: 2218 return C_O1_I1(w, r); 2219 case INDEX_op_dup_vec: 2220 return C_O1_I1(w, wr); 2221 case INDEX_op_abs_vec: 2222 case INDEX_op_neg_vec: 2223 case INDEX_op_not_vec: 2224 case INDEX_op_shli_vec: 2225 case INDEX_op_shri_vec: 2226 case INDEX_op_sari_vec: 2227 return C_O1_I1(w, w); 2228 case INDEX_op_dup2_vec: 2229 case INDEX_op_add_vec: 2230 case INDEX_op_mul_vec: 2231 case INDEX_op_smax_vec: 2232 case INDEX_op_smin_vec: 2233 case INDEX_op_ssadd_vec: 2234 case INDEX_op_sssub_vec: 2235 case INDEX_op_sub_vec: 2236 case INDEX_op_umax_vec: 2237 case INDEX_op_umin_vec: 2238 case INDEX_op_usadd_vec: 2239 case INDEX_op_ussub_vec: 2240 case INDEX_op_xor_vec: 2241 case INDEX_op_arm_sshl_vec: 2242 case INDEX_op_arm_ushl_vec: 2243 return C_O1_I2(w, w, w); 2244 case INDEX_op_arm_sli_vec: 2245 return C_O1_I2(w, 0, w); 2246 case INDEX_op_or_vec: 2247 case INDEX_op_andc_vec: 2248 return C_O1_I2(w, w, wO); 2249 case INDEX_op_and_vec: 2250 case INDEX_op_orc_vec: 2251 return C_O1_I2(w, w, wV); 2252 case INDEX_op_cmp_vec: 2253 return C_O1_I2(w, w, wZ); 2254 case INDEX_op_bitsel_vec: 2255 return C_O1_I3(w, w, w, w); 2256 default: 2257 g_assert_not_reached(); 2258 } 2259} 2260 2261static void tcg_target_init(TCGContext *s) 2262{ 2263 /* 2264 * Only probe for the platform and capabilities if we haven't already 2265 * determined maximum values at compile time. 2266 */ 2267#if !defined(use_idiv_instructions) || !defined(use_neon_instructions) 2268 { 2269 unsigned long hwcap = qemu_getauxval(AT_HWCAP); 2270#ifndef use_idiv_instructions 2271 use_idiv_instructions = (hwcap & HWCAP_ARM_IDIVA) != 0; 2272#endif 2273#ifndef use_neon_instructions 2274 use_neon_instructions = (hwcap & HWCAP_ARM_NEON) != 0; 2275#endif 2276 } 2277#endif 2278 2279 if (__ARM_ARCH < 7) { 2280 const char *pl = (const char *)qemu_getauxval(AT_PLATFORM); 2281 if (pl != NULL && pl[0] == 'v' && pl[1] >= '4' && pl[1] <= '9') { 2282 arm_arch = pl[1] - '0'; 2283 } 2284 2285 if (arm_arch < 6) { 2286 error_report("TCG: ARMv%d is unsupported; exiting", arm_arch); 2287 exit(EXIT_FAILURE); 2288 } 2289 } 2290 2291 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS; 2292 2293 tcg_target_call_clobber_regs = 0; 2294 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); 2295 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1); 2296 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2); 2297 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3); 2298 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12); 2299 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14); 2300 2301 if (use_neon_instructions) { 2302 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS; 2303 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS; 2304 2305 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q0); 2306 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q1); 2307 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q2); 2308 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q3); 2309 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q8); 2310 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q9); 2311 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q10); 2312 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q11); 2313 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q12); 2314 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q13); 2315 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q14); 2316 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q15); 2317 } 2318 2319 s->reserved_regs = 0; 2320 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); 2321 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP); 2322 tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC); 2323 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP); 2324} 2325 2326static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 2327 TCGReg arg1, intptr_t arg2) 2328{ 2329 switch (type) { 2330 case TCG_TYPE_I32: 2331 tcg_out_ld32u(s, COND_AL, arg, arg1, arg2); 2332 return; 2333 case TCG_TYPE_V64: 2334 /* regs 1; size 8; align 8 */ 2335 tcg_out_vldst(s, INSN_VLD1 | 0x7d0, arg, arg1, arg2); 2336 return; 2337 case TCG_TYPE_V128: 2338 /* 2339 * We have only 8-byte alignment for the stack per the ABI. 2340 * Rather than dynamically re-align the stack, it's easier 2341 * to simply not request alignment beyond that. So: 2342 * regs 2; size 8; align 8 2343 */ 2344 tcg_out_vldst(s, INSN_VLD1 | 0xad0, arg, arg1, arg2); 2345 return; 2346 default: 2347 g_assert_not_reached(); 2348 } 2349} 2350 2351static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 2352 TCGReg arg1, intptr_t arg2) 2353{ 2354 switch (type) { 2355 case TCG_TYPE_I32: 2356 tcg_out_st32(s, COND_AL, arg, arg1, arg2); 2357 return; 2358 case TCG_TYPE_V64: 2359 /* regs 1; size 8; align 8 */ 2360 tcg_out_vldst(s, INSN_VST1 | 0x7d0, arg, arg1, arg2); 2361 return; 2362 case TCG_TYPE_V128: 2363 /* See tcg_out_ld re alignment: regs 2; size 8; align 8 */ 2364 tcg_out_vldst(s, INSN_VST1 | 0xad0, arg, arg1, arg2); 2365 return; 2366 default: 2367 g_assert_not_reached(); 2368 } 2369} 2370 2371static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 2372 TCGReg base, intptr_t ofs) 2373{ 2374 return false; 2375} 2376 2377static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 2378{ 2379 if (ret == arg) { 2380 return true; 2381 } 2382 switch (type) { 2383 case TCG_TYPE_I32: 2384 if (ret < TCG_REG_Q0 && arg < TCG_REG_Q0) { 2385 tcg_out_mov_reg(s, COND_AL, ret, arg); 2386 return true; 2387 } 2388 return false; 2389 2390 case TCG_TYPE_V64: 2391 case TCG_TYPE_V128: 2392 /* "VMOV D,N" is an alias for "VORR D,N,N". */ 2393 tcg_out_vreg3(s, INSN_VORR, type - TCG_TYPE_V64, 0, ret, arg, arg); 2394 return true; 2395 2396 default: 2397 g_assert_not_reached(); 2398 } 2399} 2400 2401static void tcg_out_movi(TCGContext *s, TCGType type, 2402 TCGReg ret, tcg_target_long arg) 2403{ 2404 tcg_debug_assert(type == TCG_TYPE_I32); 2405 tcg_debug_assert(ret < TCG_REG_Q0); 2406 tcg_out_movi32(s, COND_AL, ret, arg); 2407} 2408 2409static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 2410{ 2411 return false; 2412} 2413 2414static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 2415 tcg_target_long imm) 2416{ 2417 int enc, opc = ARITH_ADD; 2418 2419 /* All of the easiest immediates to encode are positive. */ 2420 if (imm < 0) { 2421 imm = -imm; 2422 opc = ARITH_SUB; 2423 } 2424 enc = encode_imm(imm); 2425 if (enc >= 0) { 2426 tcg_out_dat_imm(s, COND_AL, opc, rd, rs, enc); 2427 } else { 2428 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, imm); 2429 tcg_out_dat_reg(s, COND_AL, opc, rd, rs, 2430 TCG_REG_TMP, SHIFT_IMM_LSL(0)); 2431 } 2432} 2433 2434/* Type is always V128, with I64 elements. */ 2435static void tcg_out_dup2_vec(TCGContext *s, TCGReg rd, TCGReg rl, TCGReg rh) 2436{ 2437 /* Move high element into place first. */ 2438 /* VMOV Dd+1, Ds */ 2439 tcg_out_vreg3(s, INSN_VORR | (1 << 12), 0, 0, rd, rh, rh); 2440 /* Move low element into place; tcg_out_mov will check for nop. */ 2441 tcg_out_mov(s, TCG_TYPE_V64, rd, rl); 2442} 2443 2444static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 2445 TCGReg rd, TCGReg rs) 2446{ 2447 int q = type - TCG_TYPE_V64; 2448 2449 if (vece == MO_64) { 2450 if (type == TCG_TYPE_V128) { 2451 tcg_out_dup2_vec(s, rd, rs, rs); 2452 } else { 2453 tcg_out_mov(s, TCG_TYPE_V64, rd, rs); 2454 } 2455 } else if (rs < TCG_REG_Q0) { 2456 int b = (vece == MO_8); 2457 int e = (vece == MO_16); 2458 tcg_out32(s, INSN_VDUP_G | (b << 22) | (q << 21) | (e << 5) | 2459 encode_vn(rd) | (rs << 12)); 2460 } else { 2461 int imm4 = 1 << vece; 2462 tcg_out32(s, INSN_VDUP_S | (imm4 << 16) | (q << 6) | 2463 encode_vd(rd) | encode_vm(rs)); 2464 } 2465 return true; 2466} 2467 2468static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 2469 TCGReg rd, TCGReg base, intptr_t offset) 2470{ 2471 if (vece == MO_64) { 2472 tcg_out_ld(s, TCG_TYPE_V64, rd, base, offset); 2473 if (type == TCG_TYPE_V128) { 2474 tcg_out_dup2_vec(s, rd, rd, rd); 2475 } 2476 } else { 2477 int q = type - TCG_TYPE_V64; 2478 tcg_out_vldst(s, INSN_VLD1R | (vece << 6) | (q << 5), 2479 rd, base, offset); 2480 } 2481 return true; 2482} 2483 2484static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 2485 TCGReg rd, int64_t v64) 2486{ 2487 int q = type - TCG_TYPE_V64; 2488 int cmode, imm8, i; 2489 2490 /* Test all bytes equal first. */ 2491 if (vece == MO_8) { 2492 tcg_out_vmovi(s, rd, q, 0, 0xe, v64); 2493 return; 2494 } 2495 2496 /* 2497 * Test all bytes 0x00 or 0xff second. This can match cases that 2498 * might otherwise take 2 or 3 insns for MO_16 or MO_32 below. 2499 */ 2500 for (i = imm8 = 0; i < 8; i++) { 2501 uint8_t byte = v64 >> (i * 8); 2502 if (byte == 0xff) { 2503 imm8 |= 1 << i; 2504 } else if (byte != 0) { 2505 goto fail_bytes; 2506 } 2507 } 2508 tcg_out_vmovi(s, rd, q, 1, 0xe, imm8); 2509 return; 2510 fail_bytes: 2511 2512 /* 2513 * Tests for various replications. For each element width, if we 2514 * cannot find an expansion there's no point checking a larger 2515 * width because we already know by replication it cannot match. 2516 */ 2517 if (vece == MO_16) { 2518 uint16_t v16 = v64; 2519 2520 if (is_shimm16(v16, &cmode, &imm8)) { 2521 tcg_out_vmovi(s, rd, q, 0, cmode, imm8); 2522 return; 2523 } 2524 if (is_shimm16(~v16, &cmode, &imm8)) { 2525 tcg_out_vmovi(s, rd, q, 1, cmode, imm8); 2526 return; 2527 } 2528 2529 /* 2530 * Otherwise, all remaining constants can be loaded in two insns: 2531 * rd = v16 & 0xff, rd |= v16 & 0xff00. 2532 */ 2533 tcg_out_vmovi(s, rd, q, 0, 0x8, v16 & 0xff); 2534 tcg_out_vmovi(s, rd, q, 0, 0xb, v16 >> 8); /* VORRI */ 2535 return; 2536 } 2537 2538 if (vece == MO_32) { 2539 uint32_t v32 = v64; 2540 2541 if (is_shimm32(v32, &cmode, &imm8) || 2542 is_soimm32(v32, &cmode, &imm8)) { 2543 tcg_out_vmovi(s, rd, q, 0, cmode, imm8); 2544 return; 2545 } 2546 if (is_shimm32(~v32, &cmode, &imm8) || 2547 is_soimm32(~v32, &cmode, &imm8)) { 2548 tcg_out_vmovi(s, rd, q, 1, cmode, imm8); 2549 return; 2550 } 2551 2552 /* 2553 * Restrict the set of constants to those we can load with 2554 * two instructions. Others we load from the pool. 2555 */ 2556 i = is_shimm32_pair(v32, &cmode, &imm8); 2557 if (i) { 2558 tcg_out_vmovi(s, rd, q, 0, cmode, imm8); 2559 tcg_out_vmovi(s, rd, q, 0, i | 1, extract32(v32, i * 4, 8)); 2560 return; 2561 } 2562 i = is_shimm32_pair(~v32, &cmode, &imm8); 2563 if (i) { 2564 tcg_out_vmovi(s, rd, q, 1, cmode, imm8); 2565 tcg_out_vmovi(s, rd, q, 1, i | 1, extract32(~v32, i * 4, 8)); 2566 return; 2567 } 2568 } 2569 2570 /* 2571 * As a last resort, load from the constant pool. 2572 */ 2573 if (!q || vece == MO_64) { 2574 new_pool_l2(s, R_ARM_PC11, s->code_ptr, 0, v64, v64 >> 32); 2575 /* VLDR Dd, [pc + offset] */ 2576 tcg_out32(s, INSN_VLDR_D | encode_vd(rd) | (0xf << 16)); 2577 if (q) { 2578 tcg_out_dup2_vec(s, rd, rd, rd); 2579 } 2580 } else { 2581 new_pool_label(s, (uint32_t)v64, R_ARM_PC8, s->code_ptr, 0); 2582 /* add tmp, pc, offset */ 2583 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_TMP, TCG_REG_PC, 0); 2584 tcg_out_dupm_vec(s, type, MO_32, rd, TCG_REG_TMP, 0); 2585 } 2586} 2587 2588static const ARMInsn vec_cmp_insn[16] = { 2589 [TCG_COND_EQ] = INSN_VCEQ, 2590 [TCG_COND_GT] = INSN_VCGT, 2591 [TCG_COND_GE] = INSN_VCGE, 2592 [TCG_COND_GTU] = INSN_VCGT_U, 2593 [TCG_COND_GEU] = INSN_VCGE_U, 2594}; 2595 2596static const ARMInsn vec_cmp0_insn[16] = { 2597 [TCG_COND_EQ] = INSN_VCEQ0, 2598 [TCG_COND_GT] = INSN_VCGT0, 2599 [TCG_COND_GE] = INSN_VCGE0, 2600 [TCG_COND_LT] = INSN_VCLT0, 2601 [TCG_COND_LE] = INSN_VCLE0, 2602}; 2603 2604static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 2605 unsigned vecl, unsigned vece, 2606 const TCGArg args[TCG_MAX_OP_ARGS], 2607 const int const_args[TCG_MAX_OP_ARGS]) 2608{ 2609 TCGType type = vecl + TCG_TYPE_V64; 2610 unsigned q = vecl; 2611 TCGArg a0, a1, a2, a3; 2612 int cmode, imm8; 2613 2614 a0 = args[0]; 2615 a1 = args[1]; 2616 a2 = args[2]; 2617 2618 switch (opc) { 2619 case INDEX_op_ld_vec: 2620 tcg_out_ld(s, type, a0, a1, a2); 2621 return; 2622 case INDEX_op_st_vec: 2623 tcg_out_st(s, type, a0, a1, a2); 2624 return; 2625 case INDEX_op_dupm_vec: 2626 tcg_out_dupm_vec(s, type, vece, a0, a1, a2); 2627 return; 2628 case INDEX_op_dup2_vec: 2629 tcg_out_dup2_vec(s, a0, a1, a2); 2630 return; 2631 case INDEX_op_abs_vec: 2632 tcg_out_vreg2(s, INSN_VABS, q, vece, a0, a1); 2633 return; 2634 case INDEX_op_neg_vec: 2635 tcg_out_vreg2(s, INSN_VNEG, q, vece, a0, a1); 2636 return; 2637 case INDEX_op_not_vec: 2638 tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a1); 2639 return; 2640 case INDEX_op_add_vec: 2641 tcg_out_vreg3(s, INSN_VADD, q, vece, a0, a1, a2); 2642 return; 2643 case INDEX_op_mul_vec: 2644 tcg_out_vreg3(s, INSN_VMUL, q, vece, a0, a1, a2); 2645 return; 2646 case INDEX_op_smax_vec: 2647 tcg_out_vreg3(s, INSN_VMAX, q, vece, a0, a1, a2); 2648 return; 2649 case INDEX_op_smin_vec: 2650 tcg_out_vreg3(s, INSN_VMIN, q, vece, a0, a1, a2); 2651 return; 2652 case INDEX_op_sub_vec: 2653 tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2); 2654 return; 2655 case INDEX_op_ssadd_vec: 2656 tcg_out_vreg3(s, INSN_VQADD, q, vece, a0, a1, a2); 2657 return; 2658 case INDEX_op_sssub_vec: 2659 tcg_out_vreg3(s, INSN_VQSUB, q, vece, a0, a1, a2); 2660 return; 2661 case INDEX_op_umax_vec: 2662 tcg_out_vreg3(s, INSN_VMAX_U, q, vece, a0, a1, a2); 2663 return; 2664 case INDEX_op_umin_vec: 2665 tcg_out_vreg3(s, INSN_VMIN_U, q, vece, a0, a1, a2); 2666 return; 2667 case INDEX_op_usadd_vec: 2668 tcg_out_vreg3(s, INSN_VQADD_U, q, vece, a0, a1, a2); 2669 return; 2670 case INDEX_op_ussub_vec: 2671 tcg_out_vreg3(s, INSN_VQSUB_U, q, vece, a0, a1, a2); 2672 return; 2673 case INDEX_op_xor_vec: 2674 tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2); 2675 return; 2676 case INDEX_op_arm_sshl_vec: 2677 /* 2678 * Note that Vm is the data and Vn is the shift count, 2679 * therefore the arguments appear reversed. 2680 */ 2681 tcg_out_vreg3(s, INSN_VSHL_S, q, vece, a0, a2, a1); 2682 return; 2683 case INDEX_op_arm_ushl_vec: 2684 /* See above. */ 2685 tcg_out_vreg3(s, INSN_VSHL_U, q, vece, a0, a2, a1); 2686 return; 2687 case INDEX_op_shli_vec: 2688 tcg_out_vshifti(s, INSN_VSHLI, q, a0, a1, a2 + (8 << vece)); 2689 return; 2690 case INDEX_op_shri_vec: 2691 tcg_out_vshifti(s, INSN_VSHRI, q, a0, a1, (16 << vece) - a2); 2692 return; 2693 case INDEX_op_sari_vec: 2694 tcg_out_vshifti(s, INSN_VSARI, q, a0, a1, (16 << vece) - a2); 2695 return; 2696 case INDEX_op_arm_sli_vec: 2697 tcg_out_vshifti(s, INSN_VSLI, q, a0, a2, args[3] + (8 << vece)); 2698 return; 2699 2700 case INDEX_op_andc_vec: 2701 if (!const_args[2]) { 2702 tcg_out_vreg3(s, INSN_VBIC, q, 0, a0, a1, a2); 2703 return; 2704 } 2705 a2 = ~a2; 2706 /* fall through */ 2707 case INDEX_op_and_vec: 2708 if (const_args[2]) { 2709 is_shimm1632(~a2, &cmode, &imm8); 2710 if (a0 == a1) { 2711 tcg_out_vmovi(s, a0, q, 1, cmode | 1, imm8); /* VBICI */ 2712 return; 2713 } 2714 tcg_out_vmovi(s, a0, q, 1, cmode, imm8); /* VMVNI */ 2715 a2 = a0; 2716 } 2717 tcg_out_vreg3(s, INSN_VAND, q, 0, a0, a1, a2); 2718 return; 2719 2720 case INDEX_op_orc_vec: 2721 if (!const_args[2]) { 2722 tcg_out_vreg3(s, INSN_VORN, q, 0, a0, a1, a2); 2723 return; 2724 } 2725 a2 = ~a2; 2726 /* fall through */ 2727 case INDEX_op_or_vec: 2728 if (const_args[2]) { 2729 is_shimm1632(a2, &cmode, &imm8); 2730 if (a0 == a1) { 2731 tcg_out_vmovi(s, a0, q, 0, cmode | 1, imm8); /* VORRI */ 2732 return; 2733 } 2734 tcg_out_vmovi(s, a0, q, 0, cmode, imm8); /* VMOVI */ 2735 a2 = a0; 2736 } 2737 tcg_out_vreg3(s, INSN_VORR, q, 0, a0, a1, a2); 2738 return; 2739 2740 case INDEX_op_cmp_vec: 2741 { 2742 TCGCond cond = args[3]; 2743 2744 if (cond == TCG_COND_NE) { 2745 if (const_args[2]) { 2746 tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a1); 2747 } else { 2748 tcg_out_vreg3(s, INSN_VCEQ, q, vece, a0, a1, a2); 2749 tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0); 2750 } 2751 } else { 2752 ARMInsn insn; 2753 2754 if (const_args[2]) { 2755 insn = vec_cmp0_insn[cond]; 2756 if (insn) { 2757 tcg_out_vreg2(s, insn, q, vece, a0, a1); 2758 return; 2759 } 2760 tcg_out_dupi_vec(s, type, MO_8, TCG_VEC_TMP, 0); 2761 a2 = TCG_VEC_TMP; 2762 } 2763 insn = vec_cmp_insn[cond]; 2764 if (insn == 0) { 2765 TCGArg t; 2766 t = a1, a1 = a2, a2 = t; 2767 cond = tcg_swap_cond(cond); 2768 insn = vec_cmp_insn[cond]; 2769 tcg_debug_assert(insn != 0); 2770 } 2771 tcg_out_vreg3(s, insn, q, vece, a0, a1, a2); 2772 } 2773 } 2774 return; 2775 2776 case INDEX_op_bitsel_vec: 2777 a3 = args[3]; 2778 if (a0 == a3) { 2779 tcg_out_vreg3(s, INSN_VBIT, q, 0, a0, a2, a1); 2780 } else if (a0 == a2) { 2781 tcg_out_vreg3(s, INSN_VBIF, q, 0, a0, a3, a1); 2782 } else { 2783 tcg_out_mov(s, type, a0, a1); 2784 tcg_out_vreg3(s, INSN_VBSL, q, 0, a0, a2, a3); 2785 } 2786 return; 2787 2788 case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ 2789 case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ 2790 default: 2791 g_assert_not_reached(); 2792 } 2793} 2794 2795int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 2796{ 2797 switch (opc) { 2798 case INDEX_op_add_vec: 2799 case INDEX_op_sub_vec: 2800 case INDEX_op_and_vec: 2801 case INDEX_op_andc_vec: 2802 case INDEX_op_or_vec: 2803 case INDEX_op_orc_vec: 2804 case INDEX_op_xor_vec: 2805 case INDEX_op_not_vec: 2806 case INDEX_op_shli_vec: 2807 case INDEX_op_shri_vec: 2808 case INDEX_op_sari_vec: 2809 case INDEX_op_ssadd_vec: 2810 case INDEX_op_sssub_vec: 2811 case INDEX_op_usadd_vec: 2812 case INDEX_op_ussub_vec: 2813 case INDEX_op_bitsel_vec: 2814 return 1; 2815 case INDEX_op_abs_vec: 2816 case INDEX_op_cmp_vec: 2817 case INDEX_op_mul_vec: 2818 case INDEX_op_neg_vec: 2819 case INDEX_op_smax_vec: 2820 case INDEX_op_smin_vec: 2821 case INDEX_op_umax_vec: 2822 case INDEX_op_umin_vec: 2823 return vece < MO_64; 2824 case INDEX_op_shlv_vec: 2825 case INDEX_op_shrv_vec: 2826 case INDEX_op_sarv_vec: 2827 case INDEX_op_rotli_vec: 2828 case INDEX_op_rotlv_vec: 2829 case INDEX_op_rotrv_vec: 2830 return -1; 2831 default: 2832 return 0; 2833 } 2834} 2835 2836void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 2837 TCGArg a0, ...) 2838{ 2839 va_list va; 2840 TCGv_vec v0, v1, v2, t1, t2, c1; 2841 TCGArg a2; 2842 2843 va_start(va, a0); 2844 v0 = temp_tcgv_vec(arg_temp(a0)); 2845 v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 2846 a2 = va_arg(va, TCGArg); 2847 va_end(va); 2848 2849 switch (opc) { 2850 case INDEX_op_shlv_vec: 2851 /* 2852 * Merely propagate shlv_vec to arm_ushl_vec. 2853 * In this way we don't set TCG_TARGET_HAS_shv_vec 2854 * because everything is done via expansion. 2855 */ 2856 v2 = temp_tcgv_vec(arg_temp(a2)); 2857 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0), 2858 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 2859 break; 2860 2861 case INDEX_op_shrv_vec: 2862 case INDEX_op_sarv_vec: 2863 /* Right shifts are negative left shifts for NEON. */ 2864 v2 = temp_tcgv_vec(arg_temp(a2)); 2865 t1 = tcg_temp_new_vec(type); 2866 tcg_gen_neg_vec(vece, t1, v2); 2867 if (opc == INDEX_op_shrv_vec) { 2868 opc = INDEX_op_arm_ushl_vec; 2869 } else { 2870 opc = INDEX_op_arm_sshl_vec; 2871 } 2872 vec_gen_3(opc, type, vece, tcgv_vec_arg(v0), 2873 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 2874 tcg_temp_free_vec(t1); 2875 break; 2876 2877 case INDEX_op_rotli_vec: 2878 t1 = tcg_temp_new_vec(type); 2879 tcg_gen_shri_vec(vece, t1, v1, -a2 & ((8 << vece) - 1)); 2880 vec_gen_4(INDEX_op_arm_sli_vec, type, vece, 2881 tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(v1), a2); 2882 tcg_temp_free_vec(t1); 2883 break; 2884 2885 case INDEX_op_rotlv_vec: 2886 v2 = temp_tcgv_vec(arg_temp(a2)); 2887 t1 = tcg_temp_new_vec(type); 2888 c1 = tcg_constant_vec(type, vece, 8 << vece); 2889 tcg_gen_sub_vec(vece, t1, v2, c1); 2890 /* Right shifts are negative left shifts for NEON. */ 2891 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1), 2892 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 2893 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0), 2894 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 2895 tcg_gen_or_vec(vece, v0, v0, t1); 2896 tcg_temp_free_vec(t1); 2897 break; 2898 2899 case INDEX_op_rotrv_vec: 2900 v2 = temp_tcgv_vec(arg_temp(a2)); 2901 t1 = tcg_temp_new_vec(type); 2902 t2 = tcg_temp_new_vec(type); 2903 c1 = tcg_constant_vec(type, vece, 8 << vece); 2904 tcg_gen_neg_vec(vece, t1, v2); 2905 tcg_gen_sub_vec(vece, t2, c1, v2); 2906 /* Right shifts are negative left shifts for NEON. */ 2907 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1), 2908 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 2909 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t2), 2910 tcgv_vec_arg(v1), tcgv_vec_arg(t2)); 2911 tcg_gen_or_vec(vece, v0, t1, t2); 2912 tcg_temp_free_vec(t1); 2913 tcg_temp_free_vec(t2); 2914 break; 2915 2916 default: 2917 g_assert_not_reached(); 2918 } 2919} 2920 2921static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 2922{ 2923 int i; 2924 for (i = 0; i < count; ++i) { 2925 p[i] = INSN_NOP; 2926 } 2927} 2928 2929/* Compute frame size via macros, to share between tcg_target_qemu_prologue 2930 and tcg_register_jit. */ 2931 2932#define PUSH_SIZE ((11 - 4 + 1 + 1) * sizeof(tcg_target_long)) 2933 2934#define FRAME_SIZE \ 2935 ((PUSH_SIZE \ 2936 + TCG_STATIC_CALL_ARGS_SIZE \ 2937 + CPU_TEMP_BUF_NLONGS * sizeof(long) \ 2938 + TCG_TARGET_STACK_ALIGN - 1) \ 2939 & -TCG_TARGET_STACK_ALIGN) 2940 2941#define STACK_ADDEND (FRAME_SIZE - PUSH_SIZE) 2942 2943static void tcg_target_qemu_prologue(TCGContext *s) 2944{ 2945 /* Calling convention requires us to save r4-r11 and lr. */ 2946 /* stmdb sp!, { r4 - r11, lr } */ 2947 tcg_out_ldstm(s, COND_AL, INSN_STMDB, TCG_REG_CALL_STACK, 2948 (1 << TCG_REG_R4) | (1 << TCG_REG_R5) | (1 << TCG_REG_R6) | 2949 (1 << TCG_REG_R7) | (1 << TCG_REG_R8) | (1 << TCG_REG_R9) | 2950 (1 << TCG_REG_R10) | (1 << TCG_REG_R11) | (1 << TCG_REG_R14)); 2951 2952 /* Reserve callee argument and tcg temp space. */ 2953 tcg_out_dat_rI(s, COND_AL, ARITH_SUB, TCG_REG_CALL_STACK, 2954 TCG_REG_CALL_STACK, STACK_ADDEND, 1); 2955 tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE, 2956 CPU_TEMP_BUF_NLONGS * sizeof(long)); 2957 2958 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 2959 2960#ifndef CONFIG_SOFTMMU 2961 if (guest_base) { 2962 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_GUEST_BASE, guest_base); 2963 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GUEST_BASE); 2964 } 2965#endif 2966 2967 tcg_out_b_reg(s, COND_AL, tcg_target_call_iarg_regs[1]); 2968 2969 /* 2970 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 2971 * and fall through to the rest of the epilogue. 2972 */ 2973 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 2974 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, 0); 2975 tcg_out_epilogue(s); 2976} 2977 2978static void tcg_out_epilogue(TCGContext *s) 2979{ 2980 /* Release local stack frame. */ 2981 tcg_out_dat_rI(s, COND_AL, ARITH_ADD, TCG_REG_CALL_STACK, 2982 TCG_REG_CALL_STACK, STACK_ADDEND, 1); 2983 2984 /* ldmia sp!, { r4 - r11, pc } */ 2985 tcg_out_ldstm(s, COND_AL, INSN_LDMIA, TCG_REG_CALL_STACK, 2986 (1 << TCG_REG_R4) | (1 << TCG_REG_R5) | (1 << TCG_REG_R6) | 2987 (1 << TCG_REG_R7) | (1 << TCG_REG_R8) | (1 << TCG_REG_R9) | 2988 (1 << TCG_REG_R10) | (1 << TCG_REG_R11) | (1 << TCG_REG_PC)); 2989} 2990 2991typedef struct { 2992 DebugFrameHeader h; 2993 uint8_t fde_def_cfa[4]; 2994 uint8_t fde_reg_ofs[18]; 2995} DebugFrame; 2996 2997#define ELF_HOST_MACHINE EM_ARM 2998 2999/* We're expecting a 2 byte uleb128 encoded value. */ 3000QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); 3001 3002static const DebugFrame debug_frame = { 3003 .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ 3004 .h.cie.id = -1, 3005 .h.cie.version = 1, 3006 .h.cie.code_align = 1, 3007 .h.cie.data_align = 0x7c, /* sleb128 -4 */ 3008 .h.cie.return_column = 14, 3009 3010 /* Total FDE size does not include the "len" member. */ 3011 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 3012 3013 .fde_def_cfa = { 3014 12, 13, /* DW_CFA_def_cfa sp, ... */ 3015 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 3016 (FRAME_SIZE >> 7) 3017 }, 3018 .fde_reg_ofs = { 3019 /* The following must match the stmdb in the prologue. */ 3020 0x8e, 1, /* DW_CFA_offset, lr, -4 */ 3021 0x8b, 2, /* DW_CFA_offset, r11, -8 */ 3022 0x8a, 3, /* DW_CFA_offset, r10, -12 */ 3023 0x89, 4, /* DW_CFA_offset, r9, -16 */ 3024 0x88, 5, /* DW_CFA_offset, r8, -20 */ 3025 0x87, 6, /* DW_CFA_offset, r7, -24 */ 3026 0x86, 7, /* DW_CFA_offset, r6, -28 */ 3027 0x85, 8, /* DW_CFA_offset, r5, -32 */ 3028 0x84, 9, /* DW_CFA_offset, r4, -36 */ 3029 } 3030}; 3031 3032void tcg_register_jit(const void *buf, size_t buf_size) 3033{ 3034 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 3035} 3036