1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Andrzej Zaborowski 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25#include "elf.h" 26 27int arm_arch = __ARM_ARCH; 28 29#ifndef use_idiv_instructions 30bool use_idiv_instructions; 31#endif 32#ifndef use_neon_instructions 33bool use_neon_instructions; 34#endif 35 36/* Used for function call generation. */ 37#define TCG_TARGET_STACK_ALIGN 8 38#define TCG_TARGET_CALL_STACK_OFFSET 0 39#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL 40#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN 41#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN 42#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF 43 44#ifdef CONFIG_DEBUG_TCG 45static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 46 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", 47 "%r8", "%r9", "%r10", "%r11", "%r12", "%sp", "%r14", "%pc", 48 "%q0", "%q1", "%q2", "%q3", "%q4", "%q5", "%q6", "%q7", 49 "%q8", "%q9", "%q10", "%q11", "%q12", "%q13", "%q14", "%q15", 50}; 51#endif 52 53static const int tcg_target_reg_alloc_order[] = { 54 TCG_REG_R4, 55 TCG_REG_R5, 56 TCG_REG_R6, 57 TCG_REG_R7, 58 TCG_REG_R8, 59 TCG_REG_R9, 60 TCG_REG_R10, 61 TCG_REG_R11, 62 TCG_REG_R13, 63 TCG_REG_R0, 64 TCG_REG_R1, 65 TCG_REG_R2, 66 TCG_REG_R3, 67 TCG_REG_R12, 68 TCG_REG_R14, 69 70 TCG_REG_Q0, 71 TCG_REG_Q1, 72 TCG_REG_Q2, 73 TCG_REG_Q3, 74 /* Q4 - Q7 are call-saved, and skipped. */ 75 TCG_REG_Q8, 76 TCG_REG_Q9, 77 TCG_REG_Q10, 78 TCG_REG_Q11, 79 TCG_REG_Q12, 80 TCG_REG_Q13, 81 TCG_REG_Q14, 82 TCG_REG_Q15, 83}; 84 85static const int tcg_target_call_iarg_regs[4] = { 86 TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3 87}; 88 89static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 90{ 91 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 92 tcg_debug_assert(slot >= 0 && slot <= 3); 93 return TCG_REG_R0 + slot; 94} 95 96#define TCG_REG_TMP TCG_REG_R12 97#define TCG_VEC_TMP TCG_REG_Q15 98#define TCG_REG_GUEST_BASE TCG_REG_R11 99 100typedef enum { 101 COND_EQ = 0x0, 102 COND_NE = 0x1, 103 COND_CS = 0x2, /* Unsigned greater or equal */ 104 COND_CC = 0x3, /* Unsigned less than */ 105 COND_MI = 0x4, /* Negative */ 106 COND_PL = 0x5, /* Zero or greater */ 107 COND_VS = 0x6, /* Overflow */ 108 COND_VC = 0x7, /* No overflow */ 109 COND_HI = 0x8, /* Unsigned greater than */ 110 COND_LS = 0x9, /* Unsigned less or equal */ 111 COND_GE = 0xa, 112 COND_LT = 0xb, 113 COND_GT = 0xc, 114 COND_LE = 0xd, 115 COND_AL = 0xe, 116} ARMCond; 117 118#define TO_CPSR (1 << 20) 119 120#define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00) 121#define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20) 122#define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40) 123#define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60) 124#define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10) 125#define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30) 126#define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50) 127#define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70) 128 129typedef enum { 130 ARITH_AND = 0x0 << 21, 131 ARITH_EOR = 0x1 << 21, 132 ARITH_SUB = 0x2 << 21, 133 ARITH_RSB = 0x3 << 21, 134 ARITH_ADD = 0x4 << 21, 135 ARITH_ADC = 0x5 << 21, 136 ARITH_SBC = 0x6 << 21, 137 ARITH_RSC = 0x7 << 21, 138 ARITH_TST = 0x8 << 21 | TO_CPSR, 139 ARITH_CMP = 0xa << 21 | TO_CPSR, 140 ARITH_CMN = 0xb << 21 | TO_CPSR, 141 ARITH_ORR = 0xc << 21, 142 ARITH_MOV = 0xd << 21, 143 ARITH_BIC = 0xe << 21, 144 ARITH_MVN = 0xf << 21, 145 146 INSN_B = 0x0a000000, 147 148 INSN_CLZ = 0x016f0f10, 149 INSN_RBIT = 0x06ff0f30, 150 151 INSN_LDMIA = 0x08b00000, 152 INSN_STMDB = 0x09200000, 153 154 INSN_LDR_IMM = 0x04100000, 155 INSN_LDR_REG = 0x06100000, 156 INSN_STR_IMM = 0x04000000, 157 INSN_STR_REG = 0x06000000, 158 159 INSN_LDRH_IMM = 0x005000b0, 160 INSN_LDRH_REG = 0x001000b0, 161 INSN_LDRSH_IMM = 0x005000f0, 162 INSN_LDRSH_REG = 0x001000f0, 163 INSN_STRH_IMM = 0x004000b0, 164 INSN_STRH_REG = 0x000000b0, 165 166 INSN_LDRB_IMM = 0x04500000, 167 INSN_LDRB_REG = 0x06500000, 168 INSN_LDRSB_IMM = 0x005000d0, 169 INSN_LDRSB_REG = 0x001000d0, 170 INSN_STRB_IMM = 0x04400000, 171 INSN_STRB_REG = 0x06400000, 172 173 INSN_LDRD_IMM = 0x004000d0, 174 INSN_LDRD_REG = 0x000000d0, 175 INSN_STRD_IMM = 0x004000f0, 176 INSN_STRD_REG = 0x000000f0, 177 178 INSN_DMB_ISH = 0xf57ff05b, 179 INSN_DMB_MCR = 0xee070fba, 180 181 /* Architected nop introduced in v6k. */ 182 /* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this 183 also Just So Happened to do nothing on pre-v6k so that we 184 don't need to conditionalize it? */ 185 INSN_NOP_v6k = 0xe320f000, 186 /* Otherwise the assembler uses mov r0,r0 */ 187 INSN_NOP_v4 = (COND_AL << 28) | ARITH_MOV, 188 189 INSN_VADD = 0xf2000800, 190 INSN_VAND = 0xf2000110, 191 INSN_VBIC = 0xf2100110, 192 INSN_VEOR = 0xf3000110, 193 INSN_VORN = 0xf2300110, 194 INSN_VORR = 0xf2200110, 195 INSN_VSUB = 0xf3000800, 196 INSN_VMUL = 0xf2000910, 197 INSN_VQADD = 0xf2000010, 198 INSN_VQADD_U = 0xf3000010, 199 INSN_VQSUB = 0xf2000210, 200 INSN_VQSUB_U = 0xf3000210, 201 INSN_VMAX = 0xf2000600, 202 INSN_VMAX_U = 0xf3000600, 203 INSN_VMIN = 0xf2000610, 204 INSN_VMIN_U = 0xf3000610, 205 206 INSN_VABS = 0xf3b10300, 207 INSN_VMVN = 0xf3b00580, 208 INSN_VNEG = 0xf3b10380, 209 210 INSN_VCEQ0 = 0xf3b10100, 211 INSN_VCGT0 = 0xf3b10000, 212 INSN_VCGE0 = 0xf3b10080, 213 INSN_VCLE0 = 0xf3b10180, 214 INSN_VCLT0 = 0xf3b10200, 215 216 INSN_VCEQ = 0xf3000810, 217 INSN_VCGE = 0xf2000310, 218 INSN_VCGT = 0xf2000300, 219 INSN_VCGE_U = 0xf3000310, 220 INSN_VCGT_U = 0xf3000300, 221 222 INSN_VSHLI = 0xf2800510, /* VSHL (immediate) */ 223 INSN_VSARI = 0xf2800010, /* VSHR.S */ 224 INSN_VSHRI = 0xf3800010, /* VSHR.U */ 225 INSN_VSLI = 0xf3800510, 226 INSN_VSHL_S = 0xf2000400, /* VSHL.S (register) */ 227 INSN_VSHL_U = 0xf3000400, /* VSHL.U (register) */ 228 229 INSN_VBSL = 0xf3100110, 230 INSN_VBIT = 0xf3200110, 231 INSN_VBIF = 0xf3300110, 232 233 INSN_VTST = 0xf2000810, 234 235 INSN_VDUP_G = 0xee800b10, /* VDUP (ARM core register) */ 236 INSN_VDUP_S = 0xf3b00c00, /* VDUP (scalar) */ 237 INSN_VLDR_D = 0xed100b00, /* VLDR.64 */ 238 INSN_VLD1 = 0xf4200000, /* VLD1 (multiple single elements) */ 239 INSN_VLD1R = 0xf4a00c00, /* VLD1 (single element to all lanes) */ 240 INSN_VST1 = 0xf4000000, /* VST1 (multiple single elements) */ 241 INSN_VMOVI = 0xf2800010, /* VMOV (immediate) */ 242} ARMInsn; 243 244#define INSN_NOP (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4) 245 246static const uint8_t tcg_cond_to_arm_cond[] = { 247 [TCG_COND_EQ] = COND_EQ, 248 [TCG_COND_NE] = COND_NE, 249 [TCG_COND_LT] = COND_LT, 250 [TCG_COND_GE] = COND_GE, 251 [TCG_COND_LE] = COND_LE, 252 [TCG_COND_GT] = COND_GT, 253 /* unsigned */ 254 [TCG_COND_LTU] = COND_CC, 255 [TCG_COND_GEU] = COND_CS, 256 [TCG_COND_LEU] = COND_LS, 257 [TCG_COND_GTU] = COND_HI, 258}; 259 260static int encode_imm(uint32_t imm); 261 262/* TCG private relocation type: add with pc+imm8 */ 263#define R_ARM_PC8 11 264 265/* TCG private relocation type: vldr with imm8 << 2 */ 266#define R_ARM_PC11 12 267 268static bool reloc_pc24(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 269{ 270 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 271 ptrdiff_t offset = (tcg_ptr_byte_diff(target, src_rx) - 8) >> 2; 272 273 if (offset == sextract32(offset, 0, 24)) { 274 *src_rw = deposit32(*src_rw, 0, 24, offset); 275 return true; 276 } 277 return false; 278} 279 280static bool reloc_pc13(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 281{ 282 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 283 ptrdiff_t offset = tcg_ptr_byte_diff(target, src_rx) - 8; 284 285 if (offset >= -0xfff && offset <= 0xfff) { 286 tcg_insn_unit insn = *src_rw; 287 bool u = (offset >= 0); 288 if (!u) { 289 offset = -offset; 290 } 291 insn = deposit32(insn, 23, 1, u); 292 insn = deposit32(insn, 0, 12, offset); 293 *src_rw = insn; 294 return true; 295 } 296 return false; 297} 298 299static bool reloc_pc11(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 300{ 301 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 302 ptrdiff_t offset = (tcg_ptr_byte_diff(target, src_rx) - 8) / 4; 303 304 if (offset >= -0xff && offset <= 0xff) { 305 tcg_insn_unit insn = *src_rw; 306 bool u = (offset >= 0); 307 if (!u) { 308 offset = -offset; 309 } 310 insn = deposit32(insn, 23, 1, u); 311 insn = deposit32(insn, 0, 8, offset); 312 *src_rw = insn; 313 return true; 314 } 315 return false; 316} 317 318static bool reloc_pc8(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 319{ 320 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 321 ptrdiff_t offset = tcg_ptr_byte_diff(target, src_rx) - 8; 322 int imm12 = encode_imm(offset); 323 324 if (imm12 >= 0) { 325 *src_rw = deposit32(*src_rw, 0, 12, imm12); 326 return true; 327 } 328 return false; 329} 330 331static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 332 intptr_t value, intptr_t addend) 333{ 334 tcg_debug_assert(addend == 0); 335 switch (type) { 336 case R_ARM_PC24: 337 return reloc_pc24(code_ptr, (const tcg_insn_unit *)value); 338 case R_ARM_PC13: 339 return reloc_pc13(code_ptr, (const tcg_insn_unit *)value); 340 case R_ARM_PC11: 341 return reloc_pc11(code_ptr, (const tcg_insn_unit *)value); 342 case R_ARM_PC8: 343 return reloc_pc8(code_ptr, (const tcg_insn_unit *)value); 344 default: 345 g_assert_not_reached(); 346 } 347} 348 349#define TCG_CT_CONST_ARM 0x100 350#define TCG_CT_CONST_INV 0x200 351#define TCG_CT_CONST_NEG 0x400 352#define TCG_CT_CONST_ZERO 0x800 353#define TCG_CT_CONST_ORRI 0x1000 354#define TCG_CT_CONST_ANDI 0x2000 355 356#define ALL_GENERAL_REGS 0xffffu 357#define ALL_VECTOR_REGS 0xffff0000u 358 359/* 360 * r0-r3 will be overwritten when reading the tlb entry (system-mode only); 361 * r14 will be overwritten by the BLNE branching to the slow path. 362 */ 363#define ALL_QLDST_REGS \ 364 (ALL_GENERAL_REGS & ~((tcg_use_softmmu ? 0xf : 0) | (1 << TCG_REG_R14))) 365 366/* 367 * ARM immediates for ALU instructions are made of an unsigned 8-bit 368 * right-rotated by an even amount between 0 and 30. 369 * 370 * Return < 0 if @imm cannot be encoded, else the entire imm12 field. 371 */ 372static int encode_imm(uint32_t imm) 373{ 374 uint32_t rot, imm8; 375 376 /* Simple case, no rotation required. */ 377 if ((imm & ~0xff) == 0) { 378 return imm; 379 } 380 381 /* Next, try a simple even shift. */ 382 rot = ctz32(imm) & ~1; 383 imm8 = imm >> rot; 384 rot = 32 - rot; 385 if ((imm8 & ~0xff) == 0) { 386 goto found; 387 } 388 389 /* 390 * Finally, try harder with rotations. 391 * The ctz test above will have taken care of rotates >= 8. 392 */ 393 for (rot = 2; rot < 8; rot += 2) { 394 imm8 = rol32(imm, rot); 395 if ((imm8 & ~0xff) == 0) { 396 goto found; 397 } 398 } 399 /* Fail: imm cannot be encoded. */ 400 return -1; 401 402 found: 403 /* Note that rot is even, and we discard bit 0 by shifting by 7. */ 404 return rot << 7 | imm8; 405} 406 407static int encode_imm_nofail(uint32_t imm) 408{ 409 int ret = encode_imm(imm); 410 tcg_debug_assert(ret >= 0); 411 return ret; 412} 413 414static bool check_fit_imm(uint32_t imm) 415{ 416 return encode_imm(imm) >= 0; 417} 418 419/* Return true if v16 is a valid 16-bit shifted immediate. */ 420static bool is_shimm16(uint16_t v16, int *cmode, int *imm8) 421{ 422 if (v16 == (v16 & 0xff)) { 423 *cmode = 0x8; 424 *imm8 = v16 & 0xff; 425 return true; 426 } else if (v16 == (v16 & 0xff00)) { 427 *cmode = 0xa; 428 *imm8 = v16 >> 8; 429 return true; 430 } 431 return false; 432} 433 434/* Return true if v32 is a valid 32-bit shifted immediate. */ 435static bool is_shimm32(uint32_t v32, int *cmode, int *imm8) 436{ 437 if (v32 == (v32 & 0xff)) { 438 *cmode = 0x0; 439 *imm8 = v32 & 0xff; 440 return true; 441 } else if (v32 == (v32 & 0xff00)) { 442 *cmode = 0x2; 443 *imm8 = (v32 >> 8) & 0xff; 444 return true; 445 } else if (v32 == (v32 & 0xff0000)) { 446 *cmode = 0x4; 447 *imm8 = (v32 >> 16) & 0xff; 448 return true; 449 } else if (v32 == (v32 & 0xff000000)) { 450 *cmode = 0x6; 451 *imm8 = v32 >> 24; 452 return true; 453 } 454 return false; 455} 456 457/* Return true if v32 is a valid 32-bit shifting ones immediate. */ 458static bool is_soimm32(uint32_t v32, int *cmode, int *imm8) 459{ 460 if ((v32 & 0xffff00ff) == 0xff) { 461 *cmode = 0xc; 462 *imm8 = (v32 >> 8) & 0xff; 463 return true; 464 } else if ((v32 & 0xff00ffff) == 0xffff) { 465 *cmode = 0xd; 466 *imm8 = (v32 >> 16) & 0xff; 467 return true; 468 } 469 return false; 470} 471 472/* 473 * Return non-zero if v32 can be formed by MOVI+ORR. 474 * Place the parameters for MOVI in (cmode, imm8). 475 * Return the cmode for ORR; the imm8 can be had via extraction from v32. 476 */ 477static int is_shimm32_pair(uint32_t v32, int *cmode, int *imm8) 478{ 479 int i; 480 481 for (i = 6; i > 0; i -= 2) { 482 /* Mask out one byte we can add with ORR. */ 483 uint32_t tmp = v32 & ~(0xffu << (i * 4)); 484 if (is_shimm32(tmp, cmode, imm8) || 485 is_soimm32(tmp, cmode, imm8)) { 486 break; 487 } 488 } 489 return i; 490} 491 492/* Return true if V is a valid 16-bit or 32-bit shifted immediate. */ 493static bool is_shimm1632(uint32_t v32, int *cmode, int *imm8) 494{ 495 if (v32 == deposit32(v32, 16, 16, v32)) { 496 return is_shimm16(v32, cmode, imm8); 497 } else { 498 return is_shimm32(v32, cmode, imm8); 499 } 500} 501 502/* Test if a constant matches the constraint. 503 * TODO: define constraints for: 504 * 505 * ldr/str offset: between -0xfff and 0xfff 506 * ldrh/strh offset: between -0xff and 0xff 507 * mov operand2: values represented with x << (2 * y), x < 0x100 508 * add, sub, eor...: ditto 509 */ 510static bool tcg_target_const_match(int64_t val, int ct, 511 TCGType type, TCGCond cond, int vece) 512{ 513 if (ct & TCG_CT_CONST) { 514 return 1; 515 } else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val)) { 516 return 1; 517 } else if ((ct & TCG_CT_CONST_INV) && check_fit_imm(~val)) { 518 return 1; 519 } else if ((ct & TCG_CT_CONST_NEG) && check_fit_imm(-val)) { 520 return 1; 521 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 522 return 1; 523 } 524 525 switch (ct & (TCG_CT_CONST_ORRI | TCG_CT_CONST_ANDI)) { 526 case 0: 527 break; 528 case TCG_CT_CONST_ANDI: 529 val = ~val; 530 /* fallthru */ 531 case TCG_CT_CONST_ORRI: 532 if (val == deposit64(val, 32, 32, val)) { 533 int cmode, imm8; 534 return is_shimm1632(val, &cmode, &imm8); 535 } 536 break; 537 default: 538 /* Both bits should not be set for the same insn. */ 539 g_assert_not_reached(); 540 } 541 542 return 0; 543} 544 545static void tcg_out_b_imm(TCGContext *s, ARMCond cond, int32_t offset) 546{ 547 tcg_out32(s, (cond << 28) | INSN_B | 548 (((offset - 8) >> 2) & 0x00ffffff)); 549} 550 551static void tcg_out_bl_imm(TCGContext *s, ARMCond cond, int32_t offset) 552{ 553 tcg_out32(s, (cond << 28) | 0x0b000000 | 554 (((offset - 8) >> 2) & 0x00ffffff)); 555} 556 557static void tcg_out_blx_reg(TCGContext *s, ARMCond cond, TCGReg rn) 558{ 559 tcg_out32(s, (cond << 28) | 0x012fff30 | rn); 560} 561 562static void tcg_out_blx_imm(TCGContext *s, int32_t offset) 563{ 564 tcg_out32(s, 0xfa000000 | ((offset & 2) << 23) | 565 (((offset - 8) >> 2) & 0x00ffffff)); 566} 567 568static void tcg_out_dat_reg(TCGContext *s, ARMCond cond, ARMInsn opc, 569 TCGReg rd, TCGReg rn, TCGReg rm, int shift) 570{ 571 tcg_out32(s, (cond << 28) | (0 << 25) | opc | 572 (rn << 16) | (rd << 12) | shift | rm); 573} 574 575static void tcg_out_mov_reg(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rm) 576{ 577 /* Simple reg-reg move, optimising out the 'do nothing' case */ 578 if (rd != rm) { 579 tcg_out_dat_reg(s, cond, ARITH_MOV, rd, 0, rm, SHIFT_IMM_LSL(0)); 580 } 581} 582 583static void tcg_out_bx_reg(TCGContext *s, ARMCond cond, TCGReg rn) 584{ 585 tcg_out32(s, (cond << 28) | 0x012fff10 | rn); 586} 587 588static void tcg_out_b_reg(TCGContext *s, ARMCond cond, TCGReg rn) 589{ 590 /* 591 * Unless the C portion of QEMU is compiled as thumb, we don't need 592 * true BX semantics; merely a branch to an address held in a register. 593 */ 594 tcg_out_bx_reg(s, cond, rn); 595} 596 597static void tcg_out_dat_imm(TCGContext *s, ARMCond cond, ARMInsn opc, 598 TCGReg rd, TCGReg rn, int im) 599{ 600 tcg_out32(s, (cond << 28) | (1 << 25) | opc | 601 (rn << 16) | (rd << 12) | im); 602} 603 604static void tcg_out_ldstm(TCGContext *s, ARMCond cond, ARMInsn opc, 605 TCGReg rn, uint16_t mask) 606{ 607 tcg_out32(s, (cond << 28) | opc | (rn << 16) | mask); 608} 609 610/* Note that this routine is used for both LDR and LDRH formats, so we do 611 not wish to include an immediate shift at this point. */ 612static void tcg_out_memop_r(TCGContext *s, ARMCond cond, ARMInsn opc, TCGReg rt, 613 TCGReg rn, TCGReg rm, bool u, bool p, bool w) 614{ 615 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) 616 | (w << 21) | (rn << 16) | (rt << 12) | rm); 617} 618 619static void tcg_out_memop_8(TCGContext *s, ARMCond cond, ARMInsn opc, TCGReg rt, 620 TCGReg rn, int imm8, bool p, bool w) 621{ 622 bool u = 1; 623 if (imm8 < 0) { 624 imm8 = -imm8; 625 u = 0; 626 } 627 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | 628 (rn << 16) | (rt << 12) | ((imm8 & 0xf0) << 4) | (imm8 & 0xf)); 629} 630 631static void tcg_out_memop_12(TCGContext *s, ARMCond cond, ARMInsn opc, 632 TCGReg rt, TCGReg rn, int imm12, bool p, bool w) 633{ 634 bool u = 1; 635 if (imm12 < 0) { 636 imm12 = -imm12; 637 u = 0; 638 } 639 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | 640 (rn << 16) | (rt << 12) | imm12); 641} 642 643static void tcg_out_ld32_12(TCGContext *s, ARMCond cond, TCGReg rt, 644 TCGReg rn, int imm12) 645{ 646 tcg_out_memop_12(s, cond, INSN_LDR_IMM, rt, rn, imm12, 1, 0); 647} 648 649static void tcg_out_st32_12(TCGContext *s, ARMCond cond, TCGReg rt, 650 TCGReg rn, int imm12) 651{ 652 tcg_out_memop_12(s, cond, INSN_STR_IMM, rt, rn, imm12, 1, 0); 653} 654 655static void tcg_out_ld32_r(TCGContext *s, ARMCond cond, TCGReg rt, 656 TCGReg rn, TCGReg rm) 657{ 658 tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 0); 659} 660 661static void tcg_out_st32_r(TCGContext *s, ARMCond cond, TCGReg rt, 662 TCGReg rn, TCGReg rm) 663{ 664 tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 0); 665} 666 667static void tcg_out_ldrd_8(TCGContext *s, ARMCond cond, TCGReg rt, 668 TCGReg rn, int imm8) 669{ 670 tcg_out_memop_8(s, cond, INSN_LDRD_IMM, rt, rn, imm8, 1, 0); 671} 672 673static void tcg_out_ldrd_r(TCGContext *s, ARMCond cond, TCGReg rt, 674 TCGReg rn, TCGReg rm) 675{ 676 tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 0); 677} 678 679static void tcg_out_strd_8(TCGContext *s, ARMCond cond, TCGReg rt, 680 TCGReg rn, int imm8) 681{ 682 tcg_out_memop_8(s, cond, INSN_STRD_IMM, rt, rn, imm8, 1, 0); 683} 684 685static void tcg_out_strd_r(TCGContext *s, ARMCond cond, TCGReg rt, 686 TCGReg rn, TCGReg rm) 687{ 688 tcg_out_memop_r(s, cond, INSN_STRD_REG, rt, rn, rm, 1, 1, 0); 689} 690 691/* Register pre-increment with base writeback. */ 692static void tcg_out_ld32_rwb(TCGContext *s, ARMCond cond, TCGReg rt, 693 TCGReg rn, TCGReg rm) 694{ 695 tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 1); 696} 697 698static void tcg_out_st32_rwb(TCGContext *s, ARMCond cond, TCGReg rt, 699 TCGReg rn, TCGReg rm) 700{ 701 tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 1); 702} 703 704static void tcg_out_ld16u_8(TCGContext *s, ARMCond cond, TCGReg rt, 705 TCGReg rn, int imm8) 706{ 707 tcg_out_memop_8(s, cond, INSN_LDRH_IMM, rt, rn, imm8, 1, 0); 708} 709 710static void tcg_out_st16_8(TCGContext *s, ARMCond cond, TCGReg rt, 711 TCGReg rn, int imm8) 712{ 713 tcg_out_memop_8(s, cond, INSN_STRH_IMM, rt, rn, imm8, 1, 0); 714} 715 716static void tcg_out_ld16u_r(TCGContext *s, ARMCond cond, TCGReg rt, 717 TCGReg rn, TCGReg rm) 718{ 719 tcg_out_memop_r(s, cond, INSN_LDRH_REG, rt, rn, rm, 1, 1, 0); 720} 721 722static void tcg_out_st16_r(TCGContext *s, ARMCond cond, TCGReg rt, 723 TCGReg rn, TCGReg rm) 724{ 725 tcg_out_memop_r(s, cond, INSN_STRH_REG, rt, rn, rm, 1, 1, 0); 726} 727 728static void tcg_out_ld16s_8(TCGContext *s, ARMCond cond, TCGReg rt, 729 TCGReg rn, int imm8) 730{ 731 tcg_out_memop_8(s, cond, INSN_LDRSH_IMM, rt, rn, imm8, 1, 0); 732} 733 734static void tcg_out_ld16s_r(TCGContext *s, ARMCond cond, TCGReg rt, 735 TCGReg rn, TCGReg rm) 736{ 737 tcg_out_memop_r(s, cond, INSN_LDRSH_REG, rt, rn, rm, 1, 1, 0); 738} 739 740static void tcg_out_ld8_12(TCGContext *s, ARMCond cond, TCGReg rt, 741 TCGReg rn, int imm12) 742{ 743 tcg_out_memop_12(s, cond, INSN_LDRB_IMM, rt, rn, imm12, 1, 0); 744} 745 746static void tcg_out_st8_12(TCGContext *s, ARMCond cond, TCGReg rt, 747 TCGReg rn, int imm12) 748{ 749 tcg_out_memop_12(s, cond, INSN_STRB_IMM, rt, rn, imm12, 1, 0); 750} 751 752static void tcg_out_ld8_r(TCGContext *s, ARMCond cond, TCGReg rt, 753 TCGReg rn, TCGReg rm) 754{ 755 tcg_out_memop_r(s, cond, INSN_LDRB_REG, rt, rn, rm, 1, 1, 0); 756} 757 758static void tcg_out_st8_r(TCGContext *s, ARMCond cond, TCGReg rt, 759 TCGReg rn, TCGReg rm) 760{ 761 tcg_out_memop_r(s, cond, INSN_STRB_REG, rt, rn, rm, 1, 1, 0); 762} 763 764static void tcg_out_ld8s_8(TCGContext *s, ARMCond cond, TCGReg rt, 765 TCGReg rn, int imm8) 766{ 767 tcg_out_memop_8(s, cond, INSN_LDRSB_IMM, rt, rn, imm8, 1, 0); 768} 769 770static void tcg_out_ld8s_r(TCGContext *s, ARMCond cond, TCGReg rt, 771 TCGReg rn, TCGReg rm) 772{ 773 tcg_out_memop_r(s, cond, INSN_LDRSB_REG, rt, rn, rm, 1, 1, 0); 774} 775 776static void tcg_out_movi_pool(TCGContext *s, ARMCond cond, 777 TCGReg rd, uint32_t arg) 778{ 779 new_pool_label(s, arg, R_ARM_PC13, s->code_ptr, 0); 780 tcg_out_ld32_12(s, cond, rd, TCG_REG_PC, 0); 781} 782 783static void tcg_out_movi32(TCGContext *s, ARMCond cond, 784 TCGReg rd, uint32_t arg) 785{ 786 int imm12, diff, opc, sh1, sh2; 787 uint32_t tt0, tt1, tt2; 788 789 /* Check a single MOV/MVN before anything else. */ 790 imm12 = encode_imm(arg); 791 if (imm12 >= 0) { 792 tcg_out_dat_imm(s, cond, ARITH_MOV, rd, 0, imm12); 793 return; 794 } 795 imm12 = encode_imm(~arg); 796 if (imm12 >= 0) { 797 tcg_out_dat_imm(s, cond, ARITH_MVN, rd, 0, imm12); 798 return; 799 } 800 801 /* Check for a pc-relative address. This will usually be the TB, 802 or within the TB, which is immediately before the code block. */ 803 diff = tcg_pcrel_diff(s, (void *)arg) - 8; 804 if (diff >= 0) { 805 imm12 = encode_imm(diff); 806 if (imm12 >= 0) { 807 tcg_out_dat_imm(s, cond, ARITH_ADD, rd, TCG_REG_PC, imm12); 808 return; 809 } 810 } else { 811 imm12 = encode_imm(-diff); 812 if (imm12 >= 0) { 813 tcg_out_dat_imm(s, cond, ARITH_SUB, rd, TCG_REG_PC, imm12); 814 return; 815 } 816 } 817 818 /* Use movw + movt. */ 819 if (use_armv7_instructions) { 820 /* movw */ 821 tcg_out32(s, (cond << 28) | 0x03000000 | (rd << 12) 822 | ((arg << 4) & 0x000f0000) | (arg & 0xfff)); 823 if (arg & 0xffff0000) { 824 /* movt */ 825 tcg_out32(s, (cond << 28) | 0x03400000 | (rd << 12) 826 | ((arg >> 12) & 0x000f0000) | ((arg >> 16) & 0xfff)); 827 } 828 return; 829 } 830 831 /* Look for sequences of two insns. If we have lots of 1's, we can 832 shorten the sequence by beginning with mvn and then clearing 833 higher bits with eor. */ 834 tt0 = arg; 835 opc = ARITH_MOV; 836 if (ctpop32(arg) > 16) { 837 tt0 = ~arg; 838 opc = ARITH_MVN; 839 } 840 sh1 = ctz32(tt0) & ~1; 841 tt1 = tt0 & ~(0xff << sh1); 842 sh2 = ctz32(tt1) & ~1; 843 tt2 = tt1 & ~(0xff << sh2); 844 if (tt2 == 0) { 845 int rot; 846 847 rot = ((32 - sh1) << 7) & 0xf00; 848 tcg_out_dat_imm(s, cond, opc, rd, 0, ((tt0 >> sh1) & 0xff) | rot); 849 rot = ((32 - sh2) << 7) & 0xf00; 850 tcg_out_dat_imm(s, cond, ARITH_EOR, rd, rd, 851 ((tt0 >> sh2) & 0xff) | rot); 852 return; 853 } 854 855 /* Otherwise, drop it into the constant pool. */ 856 tcg_out_movi_pool(s, cond, rd, arg); 857} 858 859/* 860 * Emit either the reg,imm or reg,reg form of a data-processing insn. 861 * rhs must satisfy the "rI" constraint. 862 */ 863static void tcg_out_dat_rI(TCGContext *s, ARMCond cond, ARMInsn opc, 864 TCGReg dst, TCGReg lhs, TCGArg rhs, int rhs_is_const) 865{ 866 if (rhs_is_const) { 867 tcg_out_dat_imm(s, cond, opc, dst, lhs, encode_imm_nofail(rhs)); 868 } else { 869 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); 870 } 871} 872 873/* 874 * Emit either the reg,imm or reg,reg form of a data-processing insn. 875 * rhs must satisfy the "rIK" constraint. 876 */ 877static void tcg_out_dat_IK(TCGContext *s, ARMCond cond, ARMInsn opc, 878 ARMInsn opinv, TCGReg dst, TCGReg lhs, TCGArg rhs) 879{ 880 int imm12 = encode_imm(rhs); 881 if (imm12 < 0) { 882 imm12 = encode_imm_nofail(~rhs); 883 opc = opinv; 884 } 885 tcg_out_dat_imm(s, cond, opc, dst, lhs, imm12); 886} 887 888static void tcg_out_dat_rIK(TCGContext *s, ARMCond cond, ARMInsn opc, 889 ARMInsn opinv, TCGReg dst, TCGReg lhs, TCGArg rhs, 890 bool rhs_is_const) 891{ 892 if (rhs_is_const) { 893 tcg_out_dat_IK(s, cond, opc, opinv, dst, lhs, rhs); 894 } else { 895 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); 896 } 897} 898 899static void tcg_out_dat_IN(TCGContext *s, ARMCond cond, ARMInsn opc, 900 ARMInsn opneg, TCGReg dst, TCGReg lhs, TCGArg rhs) 901{ 902 int imm12 = encode_imm(rhs); 903 if (imm12 < 0) { 904 imm12 = encode_imm_nofail(-rhs); 905 opc = opneg; 906 } 907 tcg_out_dat_imm(s, cond, opc, dst, lhs, imm12); 908} 909 910static void tcg_out_dat_rIN(TCGContext *s, ARMCond cond, ARMInsn opc, 911 ARMInsn opneg, TCGReg dst, TCGReg lhs, TCGArg rhs, 912 bool rhs_is_const) 913{ 914 /* Emit either the reg,imm or reg,reg form of a data-processing insn. 915 * rhs must satisfy the "rIN" constraint. 916 */ 917 if (rhs_is_const) { 918 tcg_out_dat_IN(s, cond, opc, opneg, dst, lhs, rhs); 919 } else { 920 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); 921 } 922} 923 924static void tcg_out_ext8s(TCGContext *s, TCGType t, TCGReg rd, TCGReg rn) 925{ 926 /* sxtb */ 927 tcg_out32(s, 0x06af0070 | (COND_AL << 28) | (rd << 12) | rn); 928} 929 930static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rn) 931{ 932 tcg_out_dat_imm(s, COND_AL, ARITH_AND, rd, rn, 0xff); 933} 934 935static void tcg_out_ext16s(TCGContext *s, TCGType t, TCGReg rd, TCGReg rn) 936{ 937 /* sxth */ 938 tcg_out32(s, 0x06bf0070 | (COND_AL << 28) | (rd << 12) | rn); 939} 940 941static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rn) 942{ 943 /* uxth */ 944 tcg_out32(s, 0x06ff0070 | (COND_AL << 28) | (rd << 12) | rn); 945} 946 947static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rn) 948{ 949 g_assert_not_reached(); 950} 951 952static void tcg_out_ext32u(TCGContext *s, TCGReg rd, TCGReg rn) 953{ 954 g_assert_not_reached(); 955} 956 957static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rn) 958{ 959 g_assert_not_reached(); 960} 961 962static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rn) 963{ 964 g_assert_not_reached(); 965} 966 967static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rn) 968{ 969 g_assert_not_reached(); 970} 971 972static void tcg_out_deposit(TCGContext *s, ARMCond cond, TCGReg rd, 973 TCGArg a1, int ofs, int len, bool const_a1) 974{ 975 if (const_a1) { 976 /* bfi becomes bfc with rn == 15. */ 977 a1 = 15; 978 } 979 /* bfi/bfc */ 980 tcg_out32(s, 0x07c00010 | (cond << 28) | (rd << 12) | a1 981 | (ofs << 7) | ((ofs + len - 1) << 16)); 982} 983 984static void tgen_extract(TCGContext *s, TCGType type, TCGReg rd, TCGReg rn, 985 unsigned ofs, unsigned len) 986{ 987 /* According to gcc, AND can be faster. */ 988 if (ofs == 0 && len <= 8) { 989 tcg_out_dat_imm(s, COND_AL, ARITH_AND, rd, rn, 990 encode_imm_nofail((1 << len) - 1)); 991 return; 992 } 993 994 if (use_armv7_instructions) { 995 /* ubfx */ 996 tcg_out32(s, 0x07e00050 | (COND_AL << 28) | (rd << 12) | rn 997 | (ofs << 7) | ((len - 1) << 16)); 998 return; 999 } 1000 1001 assert(ofs % 8 == 0); 1002 switch (len) { 1003 case 8: 1004 /* uxtb */ 1005 tcg_out32(s, 0x06ef0070 | (COND_AL << 28) | 1006 (rd << 12) | (ofs << 7) | rn); 1007 break; 1008 case 16: 1009 /* uxth */ 1010 tcg_out32(s, 0x06ff0070 | (COND_AL << 28) | 1011 (rd << 12) | (ofs << 7) | rn); 1012 break; 1013 default: 1014 g_assert_not_reached(); 1015 } 1016} 1017 1018static const TCGOutOpExtract outop_extract = { 1019 .base.static_constraint = C_O1_I1(r, r), 1020 .out_rr = tgen_extract, 1021}; 1022 1023static void tcg_out_sextract(TCGContext *s, ARMCond cond, TCGReg rd, 1024 TCGReg rn, int ofs, int len) 1025{ 1026 if (use_armv7_instructions) { 1027 /* sbfx */ 1028 tcg_out32(s, 0x07a00050 | (cond << 28) | (rd << 12) | rn 1029 | (ofs << 7) | ((len - 1) << 16)); 1030 return; 1031 } 1032 1033 assert(ofs % 8 == 0); 1034 switch (len) { 1035 case 8: 1036 /* sxtb */ 1037 tcg_out32(s, 0x06af0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn); 1038 break; 1039 case 16: 1040 /* sxth */ 1041 tcg_out32(s, 0x06bf0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn); 1042 break; 1043 default: 1044 g_assert_not_reached(); 1045 } 1046} 1047 1048 1049static void tcg_out_ld32u(TCGContext *s, ARMCond cond, 1050 TCGReg rd, TCGReg rn, int32_t offset) 1051{ 1052 if (offset > 0xfff || offset < -0xfff) { 1053 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1054 tcg_out_ld32_r(s, cond, rd, rn, TCG_REG_TMP); 1055 } else 1056 tcg_out_ld32_12(s, cond, rd, rn, offset); 1057} 1058 1059static void tcg_out_st32(TCGContext *s, ARMCond cond, 1060 TCGReg rd, TCGReg rn, int32_t offset) 1061{ 1062 if (offset > 0xfff || offset < -0xfff) { 1063 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1064 tcg_out_st32_r(s, cond, rd, rn, TCG_REG_TMP); 1065 } else 1066 tcg_out_st32_12(s, cond, rd, rn, offset); 1067} 1068 1069static void tcg_out_ld16u(TCGContext *s, ARMCond cond, 1070 TCGReg rd, TCGReg rn, int32_t offset) 1071{ 1072 if (offset > 0xff || offset < -0xff) { 1073 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1074 tcg_out_ld16u_r(s, cond, rd, rn, TCG_REG_TMP); 1075 } else 1076 tcg_out_ld16u_8(s, cond, rd, rn, offset); 1077} 1078 1079static void tcg_out_ld16s(TCGContext *s, ARMCond cond, 1080 TCGReg rd, TCGReg rn, int32_t offset) 1081{ 1082 if (offset > 0xff || offset < -0xff) { 1083 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1084 tcg_out_ld16s_r(s, cond, rd, rn, TCG_REG_TMP); 1085 } else 1086 tcg_out_ld16s_8(s, cond, rd, rn, offset); 1087} 1088 1089static void tcg_out_st16(TCGContext *s, ARMCond cond, 1090 TCGReg rd, TCGReg rn, int32_t offset) 1091{ 1092 if (offset > 0xff || offset < -0xff) { 1093 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1094 tcg_out_st16_r(s, cond, rd, rn, TCG_REG_TMP); 1095 } else 1096 tcg_out_st16_8(s, cond, rd, rn, offset); 1097} 1098 1099static void tcg_out_ld8u(TCGContext *s, ARMCond cond, 1100 TCGReg rd, TCGReg rn, int32_t offset) 1101{ 1102 if (offset > 0xfff || offset < -0xfff) { 1103 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1104 tcg_out_ld8_r(s, cond, rd, rn, TCG_REG_TMP); 1105 } else 1106 tcg_out_ld8_12(s, cond, rd, rn, offset); 1107} 1108 1109static void tcg_out_ld8s(TCGContext *s, ARMCond cond, 1110 TCGReg rd, TCGReg rn, int32_t offset) 1111{ 1112 if (offset > 0xff || offset < -0xff) { 1113 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1114 tcg_out_ld8s_r(s, cond, rd, rn, TCG_REG_TMP); 1115 } else 1116 tcg_out_ld8s_8(s, cond, rd, rn, offset); 1117} 1118 1119static void tcg_out_st8(TCGContext *s, ARMCond cond, 1120 TCGReg rd, TCGReg rn, int32_t offset) 1121{ 1122 if (offset > 0xfff || offset < -0xfff) { 1123 tcg_out_movi32(s, cond, TCG_REG_TMP, offset); 1124 tcg_out_st8_r(s, cond, rd, rn, TCG_REG_TMP); 1125 } else 1126 tcg_out_st8_12(s, cond, rd, rn, offset); 1127} 1128 1129/* 1130 * The _goto case is normally between TBs within the same code buffer, and 1131 * with the code buffer limited to 16MB we wouldn't need the long case. 1132 * But we also use it for the tail-call to the qemu_ld/st helpers, which does. 1133 */ 1134static void tcg_out_goto(TCGContext *s, ARMCond cond, const tcg_insn_unit *addr) 1135{ 1136 intptr_t addri = (intptr_t)addr; 1137 ptrdiff_t disp = tcg_pcrel_diff(s, addr); 1138 bool arm_mode = !(addri & 1); 1139 1140 if (arm_mode && disp - 8 < 0x01fffffd && disp - 8 > -0x01fffffd) { 1141 tcg_out_b_imm(s, cond, disp); 1142 return; 1143 } 1144 1145 /* LDR is interworking from v5t. */ 1146 tcg_out_movi_pool(s, cond, TCG_REG_PC, addri); 1147} 1148 1149/* 1150 * The call case is mostly used for helpers - so it's not unreasonable 1151 * for them to be beyond branch range. 1152 */ 1153static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *addr) 1154{ 1155 intptr_t addri = (intptr_t)addr; 1156 ptrdiff_t disp = tcg_pcrel_diff(s, addr); 1157 bool arm_mode = !(addri & 1); 1158 1159 if (disp - 8 < 0x02000000 && disp - 8 >= -0x02000000) { 1160 if (arm_mode) { 1161 tcg_out_bl_imm(s, COND_AL, disp); 1162 } else { 1163 tcg_out_blx_imm(s, disp); 1164 } 1165 return; 1166 } 1167 1168 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri); 1169 tcg_out_blx_reg(s, COND_AL, TCG_REG_TMP); 1170} 1171 1172static void tcg_out_call(TCGContext *s, const tcg_insn_unit *addr, 1173 const TCGHelperInfo *info) 1174{ 1175 tcg_out_call_int(s, addr); 1176} 1177 1178static void tcg_out_goto_label(TCGContext *s, ARMCond cond, TCGLabel *l) 1179{ 1180 if (l->has_value) { 1181 tcg_out_goto(s, cond, l->u.value_ptr); 1182 } else { 1183 tcg_out_reloc(s, s->code_ptr, R_ARM_PC24, l, 0); 1184 tcg_out_b_imm(s, cond, 0); 1185 } 1186} 1187 1188static void tcg_out_mb(TCGContext *s, TCGArg a0) 1189{ 1190 if (use_armv7_instructions) { 1191 tcg_out32(s, INSN_DMB_ISH); 1192 } else { 1193 tcg_out32(s, INSN_DMB_MCR); 1194 } 1195} 1196 1197static TCGCond tgen_cmp(TCGContext *s, TCGCond cond, TCGReg a, TCGReg b) 1198{ 1199 if (is_tst_cond(cond)) { 1200 tcg_out_dat_reg(s, COND_AL, ARITH_TST, 0, a, b, SHIFT_IMM_LSL(0)); 1201 return tcg_tst_eqne_cond(cond); 1202 } 1203 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, a, b, SHIFT_IMM_LSL(0)); 1204 return cond; 1205} 1206 1207static TCGCond tgen_cmpi(TCGContext *s, TCGCond cond, TCGReg a, TCGArg b) 1208{ 1209 int imm12; 1210 1211 if (!is_tst_cond(cond)) { 1212 tcg_out_dat_IN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, a, b); 1213 return cond; 1214 } 1215 1216 /* 1217 * The compare constraints allow rIN, but TST does not support N. 1218 * Be prepared to load the constant into a scratch register. 1219 */ 1220 imm12 = encode_imm(b); 1221 if (imm12 >= 0) { 1222 tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, a, imm12); 1223 } else { 1224 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, b); 1225 tcg_out_dat_reg(s, COND_AL, ARITH_TST, 0, 1226 a, TCG_REG_TMP, SHIFT_IMM_LSL(0)); 1227 } 1228 return tcg_tst_eqne_cond(cond); 1229} 1230 1231static TCGCond tcg_out_cmp(TCGContext *s, TCGCond cond, TCGReg a, 1232 TCGArg b, int b_const) 1233{ 1234 if (b_const) { 1235 return tgen_cmpi(s, cond, a, b); 1236 } else { 1237 return tgen_cmp(s, cond, a, b); 1238 } 1239} 1240 1241static TCGCond tcg_out_cmp2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, 1242 TCGArg bl, bool const_bl, TCGArg bh, bool const_bh) 1243{ 1244 switch (cond) { 1245 case TCG_COND_EQ: 1246 case TCG_COND_NE: 1247 case TCG_COND_LTU: 1248 case TCG_COND_LEU: 1249 case TCG_COND_GTU: 1250 case TCG_COND_GEU: 1251 /* 1252 * We perform a conditional comparison. If the high half is 1253 * equal, then overwrite the flags with the comparison of the 1254 * low half. The resulting flags cover the whole. 1255 */ 1256 tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, ah, bh, const_bh); 1257 tcg_out_dat_rI(s, COND_EQ, ARITH_CMP, 0, al, bl, const_bl); 1258 return cond; 1259 1260 case TCG_COND_TSTEQ: 1261 case TCG_COND_TSTNE: 1262 /* Similar, but with TST instead of CMP. */ 1263 tcg_out_dat_rI(s, COND_AL, ARITH_TST, 0, ah, bh, const_bh); 1264 tcg_out_dat_rI(s, COND_EQ, ARITH_TST, 0, al, bl, const_bl); 1265 return tcg_tst_eqne_cond(cond); 1266 1267 case TCG_COND_LT: 1268 case TCG_COND_GE: 1269 /* We perform a double-word subtraction and examine the result. 1270 We do not actually need the result of the subtract, so the 1271 low part "subtract" is a compare. For the high half we have 1272 no choice but to compute into a temporary. */ 1273 tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, al, bl, const_bl); 1274 tcg_out_dat_rI(s, COND_AL, ARITH_SBC | TO_CPSR, 1275 TCG_REG_TMP, ah, bh, const_bh); 1276 return cond; 1277 1278 case TCG_COND_LE: 1279 case TCG_COND_GT: 1280 /* Similar, but with swapped arguments, via reversed subtract. */ 1281 tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR, 1282 TCG_REG_TMP, al, bl, const_bl); 1283 tcg_out_dat_rI(s, COND_AL, ARITH_RSC | TO_CPSR, 1284 TCG_REG_TMP, ah, bh, const_bh); 1285 return tcg_swap_cond(cond); 1286 1287 default: 1288 g_assert_not_reached(); 1289 } 1290} 1291 1292/* 1293 * Note that TCGReg references Q-registers. 1294 * Q-regno = 2 * D-regno, so shift left by 1 while inserting. 1295 */ 1296static uint32_t encode_vd(TCGReg rd) 1297{ 1298 tcg_debug_assert(rd >= TCG_REG_Q0); 1299 return (extract32(rd, 3, 1) << 22) | (extract32(rd, 0, 3) << 13); 1300} 1301 1302static uint32_t encode_vn(TCGReg rn) 1303{ 1304 tcg_debug_assert(rn >= TCG_REG_Q0); 1305 return (extract32(rn, 3, 1) << 7) | (extract32(rn, 0, 3) << 17); 1306} 1307 1308static uint32_t encode_vm(TCGReg rm) 1309{ 1310 tcg_debug_assert(rm >= TCG_REG_Q0); 1311 return (extract32(rm, 3, 1) << 5) | (extract32(rm, 0, 3) << 1); 1312} 1313 1314static void tcg_out_vreg2(TCGContext *s, ARMInsn insn, int q, int vece, 1315 TCGReg d, TCGReg m) 1316{ 1317 tcg_out32(s, insn | (vece << 18) | (q << 6) | 1318 encode_vd(d) | encode_vm(m)); 1319} 1320 1321static void tcg_out_vreg3(TCGContext *s, ARMInsn insn, int q, int vece, 1322 TCGReg d, TCGReg n, TCGReg m) 1323{ 1324 tcg_out32(s, insn | (vece << 20) | (q << 6) | 1325 encode_vd(d) | encode_vn(n) | encode_vm(m)); 1326} 1327 1328static void tcg_out_vmovi(TCGContext *s, TCGReg rd, 1329 int q, int op, int cmode, uint8_t imm8) 1330{ 1331 tcg_out32(s, INSN_VMOVI | encode_vd(rd) | (q << 6) | (op << 5) 1332 | (cmode << 8) | extract32(imm8, 0, 4) 1333 | (extract32(imm8, 4, 3) << 16) 1334 | (extract32(imm8, 7, 1) << 24)); 1335} 1336 1337static void tcg_out_vshifti(TCGContext *s, ARMInsn insn, int q, 1338 TCGReg rd, TCGReg rm, int l_imm6) 1339{ 1340 tcg_out32(s, insn | (q << 6) | encode_vd(rd) | encode_vm(rm) | 1341 (extract32(l_imm6, 6, 1) << 7) | 1342 (extract32(l_imm6, 0, 6) << 16)); 1343} 1344 1345static void tcg_out_vldst(TCGContext *s, ARMInsn insn, 1346 TCGReg rd, TCGReg rn, int offset) 1347{ 1348 if (offset != 0) { 1349 if (check_fit_imm(offset) || check_fit_imm(-offset)) { 1350 tcg_out_dat_rIN(s, COND_AL, ARITH_ADD, ARITH_SUB, 1351 TCG_REG_TMP, rn, offset, true); 1352 } else { 1353 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, offset); 1354 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, 1355 TCG_REG_TMP, TCG_REG_TMP, rn, 0); 1356 } 1357 rn = TCG_REG_TMP; 1358 } 1359 tcg_out32(s, insn | (rn << 16) | encode_vd(rd) | 0xf); 1360} 1361 1362typedef struct { 1363 ARMCond cond; 1364 TCGReg base; 1365 int index; 1366 bool index_scratch; 1367 TCGAtomAlign aa; 1368} HostAddress; 1369 1370bool tcg_target_has_memory_bswap(MemOp memop) 1371{ 1372 return false; 1373} 1374 1375static TCGReg ldst_ra_gen(TCGContext *s, const TCGLabelQemuLdst *l, int arg) 1376{ 1377 /* We arrive at the slow path via "BLNE", so R14 contains l->raddr. */ 1378 return TCG_REG_R14; 1379} 1380 1381static const TCGLdstHelperParam ldst_helper_param = { 1382 .ra_gen = ldst_ra_gen, 1383 .ntmp = 1, 1384 .tmp = { TCG_REG_TMP }, 1385}; 1386 1387static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1388{ 1389 MemOp opc = get_memop(lb->oi); 1390 1391 if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1392 return false; 1393 } 1394 1395 tcg_out_ld_helper_args(s, lb, &ldst_helper_param); 1396 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE]); 1397 tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param); 1398 1399 tcg_out_goto(s, COND_AL, lb->raddr); 1400 return true; 1401} 1402 1403static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1404{ 1405 MemOp opc = get_memop(lb->oi); 1406 1407 if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1408 return false; 1409 } 1410 1411 tcg_out_st_helper_args(s, lb, &ldst_helper_param); 1412 1413 /* Tail-call to the helper, which will return to the fast path. */ 1414 tcg_out_goto(s, COND_AL, qemu_st_helpers[opc & MO_SIZE]); 1415 return true; 1416} 1417 1418/* We expect to use an 9-bit sign-magnitude negative offset from ENV. */ 1419#define MIN_TLB_MASK_TABLE_OFS -256 1420 1421static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1422 TCGReg addr, MemOpIdx oi, bool is_ld) 1423{ 1424 TCGLabelQemuLdst *ldst = NULL; 1425 MemOp opc = get_memop(oi); 1426 unsigned a_mask; 1427 1428 if (tcg_use_softmmu) { 1429 *h = (HostAddress){ 1430 .cond = COND_AL, 1431 .base = addr, 1432 .index = TCG_REG_R1, 1433 .index_scratch = true, 1434 }; 1435 } else { 1436 *h = (HostAddress){ 1437 .cond = COND_AL, 1438 .base = addr, 1439 .index = guest_base ? TCG_REG_GUEST_BASE : -1, 1440 .index_scratch = false, 1441 }; 1442 } 1443 1444 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); 1445 a_mask = (1 << h->aa.align) - 1; 1446 1447 if (tcg_use_softmmu) { 1448 int mem_index = get_mmuidx(oi); 1449 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read) 1450 : offsetof(CPUTLBEntry, addr_write); 1451 int fast_off = tlb_mask_table_ofs(s, mem_index); 1452 unsigned s_mask = (1 << (opc & MO_SIZE)) - 1; 1453 TCGReg t_addr; 1454 1455 ldst = new_ldst_label(s); 1456 ldst->is_ld = is_ld; 1457 ldst->oi = oi; 1458 ldst->addr_reg = addr; 1459 1460 /* Load cpu->neg.tlb.f[mmu_idx].{mask,table} into {r0,r1}. */ 1461 QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0); 1462 QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != 4); 1463 tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off); 1464 1465 /* Extract the tlb index from the address into R0. */ 1466 tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, addr, 1467 SHIFT_IMM_LSR(s->page_bits - CPU_TLB_ENTRY_BITS)); 1468 1469 /* 1470 * Add the tlb_table pointer, creating the CPUTLBEntry address in R1. 1471 * Load the tlb comparator into R2 and the fast path addend into R1. 1472 */ 1473 if (cmp_off == 0) { 1474 tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0); 1475 } else { 1476 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, 1477 TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0); 1478 tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); 1479 } 1480 1481 /* Load the tlb addend. */ 1482 tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R1, 1483 offsetof(CPUTLBEntry, addend)); 1484 1485 /* 1486 * Check alignment, check comparators. 1487 * Do this in 2-4 insns. Use MOVW for v7, if possible, 1488 * to reduce the number of sequential conditional instructions. 1489 * Almost all guests have at least 4k pages, which means that we need 1490 * to clear at least 9 bits even for an 8-byte memory, which means it 1491 * isn't worth checking for an immediate operand for BIC. 1492 * 1493 * For unaligned accesses, test the page of the last unit of alignment. 1494 * This leaves the least significant alignment bits unchanged, and of 1495 * course must be zero. 1496 */ 1497 t_addr = addr; 1498 if (a_mask < s_mask) { 1499 t_addr = TCG_REG_R0; 1500 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, t_addr, 1501 addr, s_mask - a_mask); 1502 } 1503 if (use_armv7_instructions && s->page_bits <= 16) { 1504 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, ~(s->page_mask | a_mask)); 1505 tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP, 1506 t_addr, TCG_REG_TMP, 0); 1507 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, 1508 TCG_REG_R2, TCG_REG_TMP, 0); 1509 } else { 1510 if (a_mask) { 1511 tcg_debug_assert(a_mask <= 0xff); 1512 tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addr, a_mask); 1513 } 1514 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, t_addr, 1515 SHIFT_IMM_LSR(s->page_bits)); 1516 tcg_out_dat_reg(s, (a_mask ? COND_EQ : COND_AL), ARITH_CMP, 1517 0, TCG_REG_R2, TCG_REG_TMP, 1518 SHIFT_IMM_LSL(s->page_bits)); 1519 } 1520 } else if (a_mask) { 1521 ldst = new_ldst_label(s); 1522 ldst->is_ld = is_ld; 1523 ldst->oi = oi; 1524 ldst->addr_reg = addr; 1525 1526 /* We are expecting alignment to max out at 7 */ 1527 tcg_debug_assert(a_mask <= 0xff); 1528 /* tst addr, #mask */ 1529 tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addr, a_mask); 1530 } 1531 1532 return ldst; 1533} 1534 1535static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo, 1536 TCGReg datahi, HostAddress h) 1537{ 1538 TCGReg base; 1539 1540 /* Byte swapping is left to middle-end expansion. */ 1541 tcg_debug_assert((opc & MO_BSWAP) == 0); 1542 1543 switch (opc & MO_SSIZE) { 1544 case MO_UB: 1545 if (h.index < 0) { 1546 tcg_out_ld8_12(s, h.cond, datalo, h.base, 0); 1547 } else { 1548 tcg_out_ld8_r(s, h.cond, datalo, h.base, h.index); 1549 } 1550 break; 1551 case MO_SB: 1552 if (h.index < 0) { 1553 tcg_out_ld8s_8(s, h.cond, datalo, h.base, 0); 1554 } else { 1555 tcg_out_ld8s_r(s, h.cond, datalo, h.base, h.index); 1556 } 1557 break; 1558 case MO_UW: 1559 if (h.index < 0) { 1560 tcg_out_ld16u_8(s, h.cond, datalo, h.base, 0); 1561 } else { 1562 tcg_out_ld16u_r(s, h.cond, datalo, h.base, h.index); 1563 } 1564 break; 1565 case MO_SW: 1566 if (h.index < 0) { 1567 tcg_out_ld16s_8(s, h.cond, datalo, h.base, 0); 1568 } else { 1569 tcg_out_ld16s_r(s, h.cond, datalo, h.base, h.index); 1570 } 1571 break; 1572 case MO_UL: 1573 if (h.index < 0) { 1574 tcg_out_ld32_12(s, h.cond, datalo, h.base, 0); 1575 } else { 1576 tcg_out_ld32_r(s, h.cond, datalo, h.base, h.index); 1577 } 1578 break; 1579 case MO_UQ: 1580 /* We used pair allocation for datalo, so already should be aligned. */ 1581 tcg_debug_assert((datalo & 1) == 0); 1582 tcg_debug_assert(datahi == datalo + 1); 1583 /* LDRD requires alignment; double-check that. */ 1584 if (memop_alignment_bits(opc) >= MO_64) { 1585 if (h.index < 0) { 1586 tcg_out_ldrd_8(s, h.cond, datalo, h.base, 0); 1587 break; 1588 } 1589 /* 1590 * Rm (the second address op) must not overlap Rt or Rt + 1. 1591 * Since datalo is aligned, we can simplify the test via alignment. 1592 * Flip the two address arguments if that works. 1593 */ 1594 if ((h.index & ~1) != datalo) { 1595 tcg_out_ldrd_r(s, h.cond, datalo, h.base, h.index); 1596 break; 1597 } 1598 if ((h.base & ~1) != datalo) { 1599 tcg_out_ldrd_r(s, h.cond, datalo, h.index, h.base); 1600 break; 1601 } 1602 } 1603 if (h.index < 0) { 1604 base = h.base; 1605 if (datalo == h.base) { 1606 tcg_out_mov_reg(s, h.cond, TCG_REG_TMP, base); 1607 base = TCG_REG_TMP; 1608 } 1609 } else if (h.index_scratch) { 1610 tcg_out_ld32_rwb(s, h.cond, datalo, h.index, h.base); 1611 tcg_out_ld32_12(s, h.cond, datahi, h.index, 4); 1612 break; 1613 } else { 1614 tcg_out_dat_reg(s, h.cond, ARITH_ADD, TCG_REG_TMP, 1615 h.base, h.index, SHIFT_IMM_LSL(0)); 1616 base = TCG_REG_TMP; 1617 } 1618 tcg_out_ld32_12(s, h.cond, datalo, base, 0); 1619 tcg_out_ld32_12(s, h.cond, datahi, base, 4); 1620 break; 1621 default: 1622 g_assert_not_reached(); 1623 } 1624} 1625 1626static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, 1627 TCGReg addr, MemOpIdx oi, TCGType data_type) 1628{ 1629 MemOp opc = get_memop(oi); 1630 TCGLabelQemuLdst *ldst; 1631 HostAddress h; 1632 1633 ldst = prepare_host_addr(s, &h, addr, oi, true); 1634 if (ldst) { 1635 ldst->type = data_type; 1636 ldst->datalo_reg = datalo; 1637 ldst->datahi_reg = datahi; 1638 1639 /* 1640 * This a conditional BL only to load a pointer within this 1641 * opcode into LR for the slow path. We will not be using 1642 * the value for a tail call. 1643 */ 1644 ldst->label_ptr[0] = s->code_ptr; 1645 tcg_out_bl_imm(s, COND_NE, 0); 1646 1647 tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); 1648 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1649 } else { 1650 tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); 1651 } 1652} 1653 1654static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo, 1655 TCGReg datahi, HostAddress h) 1656{ 1657 /* Byte swapping is left to middle-end expansion. */ 1658 tcg_debug_assert((opc & MO_BSWAP) == 0); 1659 1660 switch (opc & MO_SIZE) { 1661 case MO_8: 1662 if (h.index < 0) { 1663 tcg_out_st8_12(s, h.cond, datalo, h.base, 0); 1664 } else { 1665 tcg_out_st8_r(s, h.cond, datalo, h.base, h.index); 1666 } 1667 break; 1668 case MO_16: 1669 if (h.index < 0) { 1670 tcg_out_st16_8(s, h.cond, datalo, h.base, 0); 1671 } else { 1672 tcg_out_st16_r(s, h.cond, datalo, h.base, h.index); 1673 } 1674 break; 1675 case MO_32: 1676 if (h.index < 0) { 1677 tcg_out_st32_12(s, h.cond, datalo, h.base, 0); 1678 } else { 1679 tcg_out_st32_r(s, h.cond, datalo, h.base, h.index); 1680 } 1681 break; 1682 case MO_64: 1683 /* We used pair allocation for datalo, so already should be aligned. */ 1684 tcg_debug_assert((datalo & 1) == 0); 1685 tcg_debug_assert(datahi == datalo + 1); 1686 /* STRD requires alignment; double-check that. */ 1687 if (memop_alignment_bits(opc) >= MO_64) { 1688 if (h.index < 0) { 1689 tcg_out_strd_8(s, h.cond, datalo, h.base, 0); 1690 } else { 1691 tcg_out_strd_r(s, h.cond, datalo, h.base, h.index); 1692 } 1693 } else if (h.index < 0) { 1694 tcg_out_st32_12(s, h.cond, datalo, h.base, 0); 1695 tcg_out_st32_12(s, h.cond, datahi, h.base, 4); 1696 } else if (h.index_scratch) { 1697 tcg_out_st32_rwb(s, h.cond, datalo, h.index, h.base); 1698 tcg_out_st32_12(s, h.cond, datahi, h.index, 4); 1699 } else { 1700 tcg_out_dat_reg(s, h.cond, ARITH_ADD, TCG_REG_TMP, 1701 h.base, h.index, SHIFT_IMM_LSL(0)); 1702 tcg_out_st32_12(s, h.cond, datalo, TCG_REG_TMP, 0); 1703 tcg_out_st32_12(s, h.cond, datahi, TCG_REG_TMP, 4); 1704 } 1705 break; 1706 default: 1707 g_assert_not_reached(); 1708 } 1709} 1710 1711static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, 1712 TCGReg addr, MemOpIdx oi, TCGType data_type) 1713{ 1714 MemOp opc = get_memop(oi); 1715 TCGLabelQemuLdst *ldst; 1716 HostAddress h; 1717 1718 ldst = prepare_host_addr(s, &h, addr, oi, false); 1719 if (ldst) { 1720 ldst->type = data_type; 1721 ldst->datalo_reg = datalo; 1722 ldst->datahi_reg = datahi; 1723 1724 h.cond = COND_EQ; 1725 tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); 1726 1727 /* The conditional call is last, as we're going to return here. */ 1728 ldst->label_ptr[0] = s->code_ptr; 1729 tcg_out_bl_imm(s, COND_NE, 0); 1730 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1731 } else { 1732 tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); 1733 } 1734} 1735 1736static void tcg_out_epilogue(TCGContext *s); 1737 1738static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg) 1739{ 1740 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, arg); 1741 tcg_out_epilogue(s); 1742} 1743 1744static void tcg_out_goto_tb(TCGContext *s, int which) 1745{ 1746 uintptr_t i_addr; 1747 intptr_t i_disp; 1748 1749 /* Direct branch will be patched by tb_target_set_jmp_target. */ 1750 set_jmp_insn_offset(s, which); 1751 tcg_out32(s, INSN_NOP); 1752 1753 /* When branch is out of range, fall through to indirect. */ 1754 i_addr = get_jmp_target_addr(s, which); 1755 i_disp = tcg_pcrel_diff(s, (void *)i_addr) - 8; 1756 tcg_debug_assert(i_disp < 0); 1757 if (i_disp >= -0xfff) { 1758 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, i_disp); 1759 } else { 1760 /* 1761 * The TB is close, but outside the 12 bits addressable by 1762 * the load. We can extend this to 20 bits with a sub of a 1763 * shifted immediate from pc. 1764 */ 1765 int h = -i_disp; 1766 int l = -(h & 0xfff); 1767 1768 h = encode_imm_nofail(h + l); 1769 tcg_out_dat_imm(s, COND_AL, ARITH_SUB, TCG_REG_R0, TCG_REG_PC, h); 1770 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_R0, l); 1771 } 1772 set_jmp_reset_offset(s, which); 1773} 1774 1775void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1776 uintptr_t jmp_rx, uintptr_t jmp_rw) 1777{ 1778 uintptr_t addr = tb->jmp_target_addr[n]; 1779 ptrdiff_t offset = addr - (jmp_rx + 8); 1780 tcg_insn_unit insn; 1781 1782 /* Either directly branch, or fall through to indirect branch. */ 1783 if (offset == sextract64(offset, 0, 26)) { 1784 /* B <addr> */ 1785 insn = deposit32((COND_AL << 28) | INSN_B, 0, 24, offset >> 2); 1786 } else { 1787 insn = INSN_NOP; 1788 } 1789 1790 qatomic_set((uint32_t *)jmp_rw, insn); 1791 flush_idcache_range(jmp_rx, jmp_rw, 4); 1792} 1793 1794 1795static void tgen_add(TCGContext *s, TCGType type, 1796 TCGReg a0, TCGReg a1, TCGReg a2) 1797{ 1798 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, a0, a1, a2, SHIFT_IMM_LSL(0)); 1799} 1800 1801static void tgen_addi(TCGContext *s, TCGType type, 1802 TCGReg a0, TCGReg a1, tcg_target_long a2) 1803{ 1804 tcg_out_dat_IN(s, COND_AL, ARITH_ADD, ARITH_SUB, a0, a1, a2); 1805} 1806 1807static const TCGOutOpBinary outop_add = { 1808 .base.static_constraint = C_O1_I2(r, r, rIN), 1809 .out_rrr = tgen_add, 1810 .out_rri = tgen_addi, 1811}; 1812 1813static void tgen_and(TCGContext *s, TCGType type, 1814 TCGReg a0, TCGReg a1, TCGReg a2) 1815{ 1816 tcg_out_dat_reg(s, COND_AL, ARITH_AND, a0, a1, a2, SHIFT_IMM_LSL(0)); 1817} 1818 1819static void tgen_andi(TCGContext *s, TCGType type, 1820 TCGReg a0, TCGReg a1, tcg_target_long a2) 1821{ 1822 tcg_out_dat_IK(s, COND_AL, ARITH_AND, ARITH_BIC, a0, a1, a2); 1823} 1824 1825static const TCGOutOpBinary outop_and = { 1826 .base.static_constraint = C_O1_I2(r, r, rIK), 1827 .out_rrr = tgen_and, 1828 .out_rri = tgen_andi, 1829}; 1830 1831static void tgen_andc(TCGContext *s, TCGType type, 1832 TCGReg a0, TCGReg a1, TCGReg a2) 1833{ 1834 tcg_out_dat_reg(s, COND_AL, ARITH_BIC, a0, a1, a2, SHIFT_IMM_LSL(0)); 1835} 1836 1837static const TCGOutOpBinary outop_andc = { 1838 .base.static_constraint = C_O1_I2(r, r, r), 1839 .out_rrr = tgen_andc, 1840}; 1841 1842static void tgen_clz(TCGContext *s, TCGType type, 1843 TCGReg a0, TCGReg a1, TCGReg a2) 1844{ 1845 tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0, a1, 0); 1846 tcg_out_dat_reg(s, COND_NE, INSN_CLZ, a0, 0, a1, 0); 1847 tcg_out_mov_reg(s, COND_EQ, a0, a2); 1848} 1849 1850static void tgen_clzi(TCGContext *s, TCGType type, 1851 TCGReg a0, TCGReg a1, tcg_target_long a2) 1852{ 1853 if (a2 == 32) { 1854 tcg_out_dat_reg(s, COND_AL, INSN_CLZ, a0, 0, a1, 0); 1855 } else { 1856 tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0, a1, 0); 1857 tcg_out_dat_reg(s, COND_NE, INSN_CLZ, a0, 0, a1, 0); 1858 tcg_out_movi32(s, COND_EQ, a0, a2); 1859 } 1860} 1861 1862static const TCGOutOpBinary outop_clz = { 1863 .base.static_constraint = C_O1_I2(r, r, rIK), 1864 .out_rrr = tgen_clz, 1865 .out_rri = tgen_clzi, 1866}; 1867 1868static const TCGOutOpUnary outop_ctpop = { 1869 .base.static_constraint = C_NotImplemented, 1870}; 1871 1872static void tgen_ctz(TCGContext *s, TCGType type, 1873 TCGReg a0, TCGReg a1, TCGReg a2) 1874{ 1875 tcg_out_dat_reg(s, COND_AL, INSN_RBIT, TCG_REG_TMP, 0, a1, 0); 1876 tgen_clz(s, TCG_TYPE_I32, a0, TCG_REG_TMP, a2); 1877} 1878 1879static void tgen_ctzi(TCGContext *s, TCGType type, 1880 TCGReg a0, TCGReg a1, tcg_target_long a2) 1881{ 1882 tcg_out_dat_reg(s, COND_AL, INSN_RBIT, TCG_REG_TMP, 0, a1, 0); 1883 tgen_clzi(s, TCG_TYPE_I32, a0, TCG_REG_TMP, a2); 1884} 1885 1886static TCGConstraintSetIndex cset_ctz(TCGType type, unsigned flags) 1887{ 1888 return use_armv7_instructions ? C_O1_I2(r, r, rIK) : C_NotImplemented; 1889} 1890 1891static const TCGOutOpBinary outop_ctz = { 1892 .base.static_constraint = C_Dynamic, 1893 .base.dynamic_constraint = cset_ctz, 1894 .out_rrr = tgen_ctz, 1895 .out_rri = tgen_ctzi, 1896}; 1897 1898static TCGConstraintSetIndex cset_idiv(TCGType type, unsigned flags) 1899{ 1900 return use_idiv_instructions ? C_O1_I2(r, r, r) : C_NotImplemented; 1901} 1902 1903static void tgen_divs(TCGContext *s, TCGType type, 1904 TCGReg a0, TCGReg a1, TCGReg a2) 1905{ 1906 /* sdiv */ 1907 tcg_out32(s, 0x0710f010 | (COND_AL << 28) | (a0 << 16) | a1 | (a2 << 8)); 1908} 1909 1910static const TCGOutOpBinary outop_divs = { 1911 .base.static_constraint = C_Dynamic, 1912 .base.dynamic_constraint = cset_idiv, 1913 .out_rrr = tgen_divs, 1914}; 1915 1916static const TCGOutOpDivRem outop_divs2 = { 1917 .base.static_constraint = C_NotImplemented, 1918}; 1919 1920static void tgen_divu(TCGContext *s, TCGType type, 1921 TCGReg a0, TCGReg a1, TCGReg a2) 1922{ 1923 /* udiv */ 1924 tcg_out32(s, 0x0730f010 | (COND_AL << 28) | (a0 << 16) | a1 | (a2 << 8)); 1925} 1926 1927static const TCGOutOpBinary outop_divu = { 1928 .base.static_constraint = C_Dynamic, 1929 .base.dynamic_constraint = cset_idiv, 1930 .out_rrr = tgen_divu, 1931}; 1932 1933static const TCGOutOpDivRem outop_divu2 = { 1934 .base.static_constraint = C_NotImplemented, 1935}; 1936 1937static const TCGOutOpBinary outop_eqv = { 1938 .base.static_constraint = C_NotImplemented, 1939}; 1940 1941static void tgen_mul(TCGContext *s, TCGType type, 1942 TCGReg a0, TCGReg a1, TCGReg a2) 1943{ 1944 /* mul */ 1945 tcg_out32(s, (COND_AL << 28) | 0x90 | (a0 << 16) | (a1 << 8) | a2); 1946} 1947 1948static const TCGOutOpBinary outop_mul = { 1949 .base.static_constraint = C_O1_I2(r, r, r), 1950 .out_rrr = tgen_mul, 1951}; 1952 1953static void tgen_muls2(TCGContext *s, TCGType type, 1954 TCGReg rd0, TCGReg rd1, TCGReg rn, TCGReg rm) 1955{ 1956 /* smull */ 1957 tcg_out32(s, (COND_AL << 28) | 0x00c00090 | 1958 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); 1959} 1960 1961static const TCGOutOpMul2 outop_muls2 = { 1962 .base.static_constraint = C_O2_I2(r, r, r, r), 1963 .out_rrrr = tgen_muls2, 1964}; 1965 1966static const TCGOutOpBinary outop_mulsh = { 1967 .base.static_constraint = C_NotImplemented, 1968}; 1969 1970static void tgen_mulu2(TCGContext *s, TCGType type, 1971 TCGReg rd0, TCGReg rd1, TCGReg rn, TCGReg rm) 1972{ 1973 /* umull */ 1974 tcg_out32(s, (COND_AL << 28) | 0x00800090 | 1975 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); 1976} 1977 1978static const TCGOutOpMul2 outop_mulu2 = { 1979 .base.static_constraint = C_O2_I2(r, r, r, r), 1980 .out_rrrr = tgen_mulu2, 1981}; 1982 1983static const TCGOutOpBinary outop_muluh = { 1984 .base.static_constraint = C_NotImplemented, 1985}; 1986 1987static const TCGOutOpBinary outop_nand = { 1988 .base.static_constraint = C_NotImplemented, 1989}; 1990 1991static const TCGOutOpBinary outop_nor = { 1992 .base.static_constraint = C_NotImplemented, 1993}; 1994 1995static void tgen_or(TCGContext *s, TCGType type, 1996 TCGReg a0, TCGReg a1, TCGReg a2) 1997{ 1998 tcg_out_dat_reg(s, COND_AL, ARITH_ORR, a0, a1, a2, SHIFT_IMM_LSL(0)); 1999} 2000 2001static void tgen_ori(TCGContext *s, TCGType type, 2002 TCGReg a0, TCGReg a1, tcg_target_long a2) 2003{ 2004 tcg_out_dat_imm(s, COND_AL, ARITH_ORR, a0, a1, encode_imm_nofail(a2)); 2005} 2006 2007static const TCGOutOpBinary outop_or = { 2008 .base.static_constraint = C_O1_I2(r, r, rI), 2009 .out_rrr = tgen_or, 2010 .out_rri = tgen_ori, 2011}; 2012 2013static const TCGOutOpBinary outop_orc = { 2014 .base.static_constraint = C_NotImplemented, 2015}; 2016 2017static const TCGOutOpBinary outop_rems = { 2018 .base.static_constraint = C_NotImplemented, 2019}; 2020 2021static const TCGOutOpBinary outop_remu = { 2022 .base.static_constraint = C_NotImplemented, 2023}; 2024 2025static const TCGOutOpBinary outop_rotl = { 2026 .base.static_constraint = C_NotImplemented, 2027}; 2028 2029static void tgen_rotr(TCGContext *s, TCGType type, 2030 TCGReg a0, TCGReg a1, TCGReg a2) 2031{ 2032 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, SHIFT_REG_ROR(a2)); 2033} 2034 2035static void tgen_rotri(TCGContext *s, TCGType type, 2036 TCGReg a0, TCGReg a1, tcg_target_long a2) 2037{ 2038 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, SHIFT_IMM_ROR(a2 & 0x1f)); 2039} 2040 2041static const TCGOutOpBinary outop_rotr = { 2042 .base.static_constraint = C_O1_I2(r, r, ri), 2043 .out_rrr = tgen_rotr, 2044 .out_rri = tgen_rotri, 2045}; 2046 2047static void tgen_sar(TCGContext *s, TCGType type, 2048 TCGReg a0, TCGReg a1, TCGReg a2) 2049{ 2050 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, SHIFT_REG_ASR(a2)); 2051} 2052 2053static void tgen_sari(TCGContext *s, TCGType type, 2054 TCGReg a0, TCGReg a1, tcg_target_long a2) 2055{ 2056 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, 2057 SHIFT_IMM_ASR(a2 & 0x1f)); 2058} 2059 2060static const TCGOutOpBinary outop_sar = { 2061 .base.static_constraint = C_O1_I2(r, r, ri), 2062 .out_rrr = tgen_sar, 2063 .out_rri = tgen_sari, 2064}; 2065 2066static void tgen_shl(TCGContext *s, TCGType type, 2067 TCGReg a0, TCGReg a1, TCGReg a2) 2068{ 2069 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, SHIFT_REG_LSL(a2)); 2070} 2071 2072static void tgen_shli(TCGContext *s, TCGType type, 2073 TCGReg a0, TCGReg a1, tcg_target_long a2) 2074{ 2075 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, 2076 SHIFT_IMM_LSL(a2 & 0x1f)); 2077} 2078 2079static const TCGOutOpBinary outop_shl = { 2080 .base.static_constraint = C_O1_I2(r, r, ri), 2081 .out_rrr = tgen_shl, 2082 .out_rri = tgen_shli, 2083}; 2084 2085static void tgen_shr(TCGContext *s, TCGType type, 2086 TCGReg a0, TCGReg a1, TCGReg a2) 2087{ 2088 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, SHIFT_REG_LSR(a2)); 2089} 2090 2091static void tgen_shri(TCGContext *s, TCGType type, 2092 TCGReg a0, TCGReg a1, tcg_target_long a2) 2093{ 2094 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, 2095 SHIFT_IMM_LSR(a2 & 0x1f)); 2096} 2097 2098static const TCGOutOpBinary outop_shr = { 2099 .base.static_constraint = C_O1_I2(r, r, ri), 2100 .out_rrr = tgen_shr, 2101 .out_rri = tgen_shri, 2102}; 2103 2104static void tgen_sub(TCGContext *s, TCGType type, 2105 TCGReg a0, TCGReg a1, TCGReg a2) 2106{ 2107 tcg_out_dat_reg(s, COND_AL, ARITH_SUB, a0, a1, a2, SHIFT_IMM_LSL(0)); 2108} 2109 2110static void tgen_subfi(TCGContext *s, TCGType type, 2111 TCGReg a0, tcg_target_long a1, TCGReg a2) 2112{ 2113 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, a0, a2, encode_imm_nofail(a1)); 2114} 2115 2116static const TCGOutOpSubtract outop_sub = { 2117 .base.static_constraint = C_O1_I2(r, rI, r), 2118 .out_rrr = tgen_sub, 2119 .out_rir = tgen_subfi, 2120}; 2121 2122static void tgen_xor(TCGContext *s, TCGType type, 2123 TCGReg a0, TCGReg a1, TCGReg a2) 2124{ 2125 tcg_out_dat_reg(s, COND_AL, ARITH_EOR, a0, a1, a2, SHIFT_IMM_LSL(0)); 2126} 2127 2128static void tgen_xori(TCGContext *s, TCGType type, 2129 TCGReg a0, TCGReg a1, tcg_target_long a2) 2130{ 2131 tcg_out_dat_imm(s, COND_AL, ARITH_EOR, a0, a1, encode_imm_nofail(a2)); 2132} 2133 2134static const TCGOutOpBinary outop_xor = { 2135 .base.static_constraint = C_O1_I2(r, r, rI), 2136 .out_rrr = tgen_xor, 2137 .out_rri = tgen_xori, 2138}; 2139 2140static void tgen_bswap16(TCGContext *s, TCGType type, 2141 TCGReg rd, TCGReg rn, unsigned flags) 2142{ 2143 if (flags & TCG_BSWAP_OS) { 2144 /* revsh */ 2145 tcg_out32(s, 0x06ff0fb0 | (COND_AL << 28) | (rd << 12) | rn); 2146 return; 2147 } 2148 2149 /* rev16 */ 2150 tcg_out32(s, 0x06bf0fb0 | (COND_AL << 28) | (rd << 12) | rn); 2151 if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 2152 tcg_out_ext16u(s, rd, rd); 2153 } 2154} 2155 2156static const TCGOutOpBswap outop_bswap16 = { 2157 .base.static_constraint = C_O1_I1(r, r), 2158 .out_rr = tgen_bswap16, 2159}; 2160 2161static void tgen_bswap32(TCGContext *s, TCGType type, 2162 TCGReg rd, TCGReg rn, unsigned flags) 2163{ 2164 /* rev */ 2165 tcg_out32(s, 0x06bf0f30 | (COND_AL << 28) | (rd << 12) | rn); 2166} 2167 2168static const TCGOutOpBswap outop_bswap32 = { 2169 .base.static_constraint = C_O1_I1(r, r), 2170 .out_rr = tgen_bswap32, 2171}; 2172 2173static const TCGOutOpUnary outop_bswap64 = { 2174 .base.static_constraint = C_NotImplemented, 2175}; 2176 2177static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2178{ 2179 tgen_subfi(s, type, a0, 0, a1); 2180} 2181 2182static const TCGOutOpUnary outop_neg = { 2183 .base.static_constraint = C_O1_I1(r, r), 2184 .out_rr = tgen_neg, 2185}; 2186 2187static void tgen_not(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2188{ 2189 tcg_out_dat_reg(s, COND_AL, ARITH_MVN, a0, 0, a1, SHIFT_IMM_LSL(0)); 2190} 2191 2192static const TCGOutOpUnary outop_not = { 2193 .base.static_constraint = C_O1_I1(r, r), 2194 .out_rr = tgen_not, 2195}; 2196 2197static void tgen_brcond(TCGContext *s, TCGType type, TCGCond cond, 2198 TCGReg a0, TCGReg a1, TCGLabel *l) 2199{ 2200 cond = tgen_cmp(s, cond, a0, a1); 2201 tcg_out_goto_label(s, tcg_cond_to_arm_cond[cond], l); 2202} 2203 2204static void tgen_brcondi(TCGContext *s, TCGType type, TCGCond cond, 2205 TCGReg a0, tcg_target_long a1, TCGLabel *l) 2206{ 2207 cond = tgen_cmpi(s, cond, a0, a1); 2208 tcg_out_goto_label(s, tcg_cond_to_arm_cond[cond], l); 2209} 2210 2211static const TCGOutOpBrcond outop_brcond = { 2212 .base.static_constraint = C_O0_I2(r, rIN), 2213 .out_rr = tgen_brcond, 2214 .out_ri = tgen_brcondi, 2215}; 2216 2217static void finish_setcond(TCGContext *s, TCGCond cond, TCGReg ret, bool neg) 2218{ 2219 tcg_out_movi32(s, tcg_cond_to_arm_cond[tcg_invert_cond(cond)], ret, 0); 2220 tcg_out_movi32(s, tcg_cond_to_arm_cond[cond], ret, neg ? -1 : 1); 2221} 2222 2223static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, 2224 TCGReg a0, TCGReg a1, TCGReg a2) 2225{ 2226 cond = tgen_cmp(s, cond, a1, a2); 2227 finish_setcond(s, cond, a0, false); 2228} 2229 2230static void tgen_setcondi(TCGContext *s, TCGType type, TCGCond cond, 2231 TCGReg a0, TCGReg a1, tcg_target_long a2) 2232{ 2233 cond = tgen_cmpi(s, cond, a1, a2); 2234 finish_setcond(s, cond, a0, false); 2235} 2236 2237static const TCGOutOpSetcond outop_setcond = { 2238 .base.static_constraint = C_O1_I2(r, r, rIN), 2239 .out_rrr = tgen_setcond, 2240 .out_rri = tgen_setcondi, 2241}; 2242 2243static void tgen_negsetcond(TCGContext *s, TCGType type, TCGCond cond, 2244 TCGReg a0, TCGReg a1, TCGReg a2) 2245{ 2246 cond = tgen_cmp(s, cond, a1, a2); 2247 finish_setcond(s, cond, a0, true); 2248} 2249 2250static void tgen_negsetcondi(TCGContext *s, TCGType type, TCGCond cond, 2251 TCGReg a0, TCGReg a1, tcg_target_long a2) 2252{ 2253 cond = tgen_cmpi(s, cond, a1, a2); 2254 finish_setcond(s, cond, a0, true); 2255} 2256 2257static const TCGOutOpSetcond outop_negsetcond = { 2258 .base.static_constraint = C_O1_I2(r, r, rIN), 2259 .out_rrr = tgen_negsetcond, 2260 .out_rri = tgen_negsetcondi, 2261}; 2262 2263static void tgen_movcond(TCGContext *s, TCGType type, TCGCond cond, 2264 TCGReg ret, TCGReg c1, TCGArg c2, bool const_c2, 2265 TCGArg vt, bool const_vt, TCGArg vf, bool consf_vf) 2266{ 2267 cond = tcg_out_cmp(s, cond, c1, c2, const_c2); 2268 tcg_out_dat_rIK(s, tcg_cond_to_arm_cond[cond], ARITH_MOV, ARITH_MVN, 2269 ret, 0, vt, const_vt); 2270} 2271 2272static const TCGOutOpMovcond outop_movcond = { 2273 .base.static_constraint = C_O1_I4(r, r, rIN, rIK, 0), 2274 .out = tgen_movcond, 2275}; 2276 2277static void tgen_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, 2278 TCGArg bl, bool const_bl, TCGArg bh, bool const_bh, 2279 TCGLabel *l) 2280{ 2281 cond = tcg_out_cmp2(s, cond, al, ah, bl, const_bl, bh, const_bh); 2282 tcg_out_goto_label(s, tcg_cond_to_arm_cond[cond], l); 2283} 2284 2285static const TCGOutOpBrcond2 outop_brcond2 = { 2286 .base.static_constraint = C_O0_I4(r, r, rI, rI), 2287 .out = tgen_brcond2, 2288}; 2289 2290static void tgen_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, 2291 TCGReg al, TCGReg ah, 2292 TCGArg bl, bool const_bl, 2293 TCGArg bh, bool const_bh) 2294{ 2295 cond = tcg_out_cmp2(s, cond, al, ah, bl, const_bl, bh, const_bh); 2296 finish_setcond(s, cond, ret, false); 2297} 2298 2299static const TCGOutOpSetcond2 outop_setcond2 = { 2300 .base.static_constraint = C_O1_I4(r, r, r, rI, rI), 2301 .out = tgen_setcond2, 2302}; 2303 2304static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, 2305 const TCGArg args[TCG_MAX_OP_ARGS], 2306 const int const_args[TCG_MAX_OP_ARGS]) 2307{ 2308 TCGArg a0, a1, a2, a3, a4, a5; 2309 2310 switch (opc) { 2311 case INDEX_op_goto_ptr: 2312 tcg_out_b_reg(s, COND_AL, args[0]); 2313 break; 2314 case INDEX_op_br: 2315 tcg_out_goto_label(s, COND_AL, arg_label(args[0])); 2316 break; 2317 2318 case INDEX_op_ld8u_i32: 2319 tcg_out_ld8u(s, COND_AL, args[0], args[1], args[2]); 2320 break; 2321 case INDEX_op_ld8s_i32: 2322 tcg_out_ld8s(s, COND_AL, args[0], args[1], args[2]); 2323 break; 2324 case INDEX_op_ld16u_i32: 2325 tcg_out_ld16u(s, COND_AL, args[0], args[1], args[2]); 2326 break; 2327 case INDEX_op_ld16s_i32: 2328 tcg_out_ld16s(s, COND_AL, args[0], args[1], args[2]); 2329 break; 2330 case INDEX_op_ld_i32: 2331 tcg_out_ld32u(s, COND_AL, args[0], args[1], args[2]); 2332 break; 2333 case INDEX_op_st8_i32: 2334 tcg_out_st8(s, COND_AL, args[0], args[1], args[2]); 2335 break; 2336 case INDEX_op_st16_i32: 2337 tcg_out_st16(s, COND_AL, args[0], args[1], args[2]); 2338 break; 2339 case INDEX_op_st_i32: 2340 tcg_out_st32(s, COND_AL, args[0], args[1], args[2]); 2341 break; 2342 2343 case INDEX_op_add2_i32: 2344 a0 = args[0], a1 = args[1], a2 = args[2]; 2345 a3 = args[3], a4 = args[4], a5 = args[5]; 2346 if (a0 == a3 || (a0 == a5 && !const_args[5])) { 2347 a0 = TCG_REG_TMP; 2348 } 2349 tcg_out_dat_rIN(s, COND_AL, ARITH_ADD | TO_CPSR, ARITH_SUB | TO_CPSR, 2350 a0, a2, a4, const_args[4]); 2351 tcg_out_dat_rIK(s, COND_AL, ARITH_ADC, ARITH_SBC, 2352 a1, a3, a5, const_args[5]); 2353 tcg_out_mov_reg(s, COND_AL, args[0], a0); 2354 break; 2355 case INDEX_op_sub2_i32: 2356 a0 = args[0], a1 = args[1], a2 = args[2]; 2357 a3 = args[3], a4 = args[4], a5 = args[5]; 2358 if ((a0 == a3 && !const_args[3]) || (a0 == a5 && !const_args[5])) { 2359 a0 = TCG_REG_TMP; 2360 } 2361 if (const_args[2]) { 2362 if (const_args[4]) { 2363 tcg_out_movi32(s, COND_AL, a0, a4); 2364 a4 = a0; 2365 } 2366 tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR, a0, a4, a2, 1); 2367 } else { 2368 tcg_out_dat_rIN(s, COND_AL, ARITH_SUB | TO_CPSR, 2369 ARITH_ADD | TO_CPSR, a0, a2, a4, const_args[4]); 2370 } 2371 if (const_args[3]) { 2372 if (const_args[5]) { 2373 tcg_out_movi32(s, COND_AL, a1, a5); 2374 a5 = a1; 2375 } 2376 tcg_out_dat_rI(s, COND_AL, ARITH_RSC, a1, a5, a3, 1); 2377 } else { 2378 tcg_out_dat_rIK(s, COND_AL, ARITH_SBC, ARITH_ADC, 2379 a1, a3, a5, const_args[5]); 2380 } 2381 tcg_out_mov_reg(s, COND_AL, args[0], a0); 2382 break; 2383 2384 case INDEX_op_qemu_ld_i32: 2385 tcg_out_qemu_ld(s, args[0], -1, args[1], args[2], TCG_TYPE_I32); 2386 break; 2387 case INDEX_op_qemu_ld_i64: 2388 tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3], TCG_TYPE_I64); 2389 break; 2390 2391 case INDEX_op_qemu_st_i32: 2392 tcg_out_qemu_st(s, args[0], -1, args[1], args[2], TCG_TYPE_I32); 2393 break; 2394 case INDEX_op_qemu_st_i64: 2395 tcg_out_qemu_st(s, args[0], args[1], args[2], args[3], TCG_TYPE_I64); 2396 break; 2397 2398 case INDEX_op_deposit_i32: 2399 tcg_out_deposit(s, COND_AL, args[0], args[2], 2400 args[3], args[4], const_args[2]); 2401 break; 2402 case INDEX_op_sextract_i32: 2403 tcg_out_sextract(s, COND_AL, args[0], args[1], args[2], args[3]); 2404 break; 2405 case INDEX_op_extract2_i32: 2406 /* ??? These optimization vs zero should be generic. */ 2407 /* ??? But we can't substitute 2 for 1 in the opcode stream yet. */ 2408 if (const_args[1]) { 2409 if (const_args[2]) { 2410 tcg_out_movi(s, TCG_TYPE_REG, args[0], 0); 2411 } else { 2412 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, 2413 args[2], SHIFT_IMM_LSL(32 - args[3])); 2414 } 2415 } else if (const_args[2]) { 2416 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, 2417 args[1], SHIFT_IMM_LSR(args[3])); 2418 } else { 2419 /* We can do extract2 in 2 insns, vs the 3 required otherwise. */ 2420 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, 2421 args[2], SHIFT_IMM_LSL(32 - args[3])); 2422 tcg_out_dat_reg(s, COND_AL, ARITH_ORR, args[0], TCG_REG_TMP, 2423 args[1], SHIFT_IMM_LSR(args[3])); 2424 } 2425 break; 2426 2427 case INDEX_op_mb: 2428 tcg_out_mb(s, args[0]); 2429 break; 2430 2431 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2432 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2433 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2434 default: 2435 g_assert_not_reached(); 2436 } 2437} 2438 2439static TCGConstraintSetIndex 2440tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) 2441{ 2442 switch (op) { 2443 case INDEX_op_goto_ptr: 2444 return C_O0_I1(r); 2445 2446 case INDEX_op_ld8u_i32: 2447 case INDEX_op_ld8s_i32: 2448 case INDEX_op_ld16u_i32: 2449 case INDEX_op_ld16s_i32: 2450 case INDEX_op_ld_i32: 2451 case INDEX_op_sextract_i32: 2452 return C_O1_I1(r, r); 2453 2454 case INDEX_op_st8_i32: 2455 case INDEX_op_st16_i32: 2456 case INDEX_op_st_i32: 2457 return C_O0_I2(r, r); 2458 2459 case INDEX_op_deposit_i32: 2460 return C_O1_I2(r, 0, rZ); 2461 case INDEX_op_extract2_i32: 2462 return C_O1_I2(r, rZ, rZ); 2463 case INDEX_op_add2_i32: 2464 return C_O2_I4(r, r, r, r, rIN, rIK); 2465 case INDEX_op_sub2_i32: 2466 return C_O2_I4(r, r, rI, rI, rIN, rIK); 2467 case INDEX_op_qemu_ld_i32: 2468 return C_O1_I1(r, q); 2469 case INDEX_op_qemu_ld_i64: 2470 return C_O2_I1(e, p, q); 2471 case INDEX_op_qemu_st_i32: 2472 return C_O0_I2(q, q); 2473 case INDEX_op_qemu_st_i64: 2474 return C_O0_I3(Q, p, q); 2475 2476 case INDEX_op_st_vec: 2477 return C_O0_I2(w, r); 2478 case INDEX_op_ld_vec: 2479 case INDEX_op_dupm_vec: 2480 return C_O1_I1(w, r); 2481 case INDEX_op_dup_vec: 2482 return C_O1_I1(w, wr); 2483 case INDEX_op_abs_vec: 2484 case INDEX_op_neg_vec: 2485 case INDEX_op_not_vec: 2486 case INDEX_op_shli_vec: 2487 case INDEX_op_shri_vec: 2488 case INDEX_op_sari_vec: 2489 return C_O1_I1(w, w); 2490 case INDEX_op_dup2_vec: 2491 case INDEX_op_add_vec: 2492 case INDEX_op_mul_vec: 2493 case INDEX_op_smax_vec: 2494 case INDEX_op_smin_vec: 2495 case INDEX_op_ssadd_vec: 2496 case INDEX_op_sssub_vec: 2497 case INDEX_op_sub_vec: 2498 case INDEX_op_umax_vec: 2499 case INDEX_op_umin_vec: 2500 case INDEX_op_usadd_vec: 2501 case INDEX_op_ussub_vec: 2502 case INDEX_op_xor_vec: 2503 case INDEX_op_arm_sshl_vec: 2504 case INDEX_op_arm_ushl_vec: 2505 return C_O1_I2(w, w, w); 2506 case INDEX_op_arm_sli_vec: 2507 return C_O1_I2(w, 0, w); 2508 case INDEX_op_or_vec: 2509 case INDEX_op_andc_vec: 2510 return C_O1_I2(w, w, wO); 2511 case INDEX_op_and_vec: 2512 case INDEX_op_orc_vec: 2513 return C_O1_I2(w, w, wV); 2514 case INDEX_op_cmp_vec: 2515 return C_O1_I2(w, w, wZ); 2516 case INDEX_op_bitsel_vec: 2517 return C_O1_I3(w, w, w, w); 2518 default: 2519 return C_NotImplemented; 2520 } 2521} 2522 2523static void tcg_target_init(TCGContext *s) 2524{ 2525 /* 2526 * Only probe for the platform and capabilities if we haven't already 2527 * determined maximum values at compile time. 2528 */ 2529#if !defined(use_idiv_instructions) || !defined(use_neon_instructions) 2530 { 2531 unsigned long hwcap = qemu_getauxval(AT_HWCAP); 2532#ifndef use_idiv_instructions 2533 use_idiv_instructions = (hwcap & HWCAP_ARM_IDIVA) != 0; 2534#endif 2535#ifndef use_neon_instructions 2536 use_neon_instructions = (hwcap & HWCAP_ARM_NEON) != 0; 2537#endif 2538 } 2539#endif 2540 2541 if (__ARM_ARCH < 7) { 2542 const char *pl = (const char *)qemu_getauxval(AT_PLATFORM); 2543 if (pl != NULL && pl[0] == 'v' && pl[1] >= '4' && pl[1] <= '9') { 2544 arm_arch = pl[1] - '0'; 2545 } 2546 2547 if (arm_arch < 6) { 2548 error_report("TCG: ARMv%d is unsupported; exiting", arm_arch); 2549 exit(EXIT_FAILURE); 2550 } 2551 } 2552 2553 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS; 2554 2555 tcg_target_call_clobber_regs = 0; 2556 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); 2557 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1); 2558 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2); 2559 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3); 2560 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12); 2561 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14); 2562 2563 if (use_neon_instructions) { 2564 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS; 2565 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS; 2566 2567 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q0); 2568 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q1); 2569 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q2); 2570 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q3); 2571 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q8); 2572 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q9); 2573 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q10); 2574 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q11); 2575 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q12); 2576 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q13); 2577 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q14); 2578 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q15); 2579 } 2580 2581 s->reserved_regs = 0; 2582 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); 2583 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP); 2584 tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC); 2585 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP); 2586} 2587 2588static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 2589 TCGReg arg1, intptr_t arg2) 2590{ 2591 switch (type) { 2592 case TCG_TYPE_I32: 2593 tcg_out_ld32u(s, COND_AL, arg, arg1, arg2); 2594 return; 2595 case TCG_TYPE_V64: 2596 /* regs 1; size 8; align 8 */ 2597 tcg_out_vldst(s, INSN_VLD1 | 0x7d0, arg, arg1, arg2); 2598 return; 2599 case TCG_TYPE_V128: 2600 /* 2601 * We have only 8-byte alignment for the stack per the ABI. 2602 * Rather than dynamically re-align the stack, it's easier 2603 * to simply not request alignment beyond that. So: 2604 * regs 2; size 8; align 8 2605 */ 2606 tcg_out_vldst(s, INSN_VLD1 | 0xad0, arg, arg1, arg2); 2607 return; 2608 default: 2609 g_assert_not_reached(); 2610 } 2611} 2612 2613static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 2614 TCGReg arg1, intptr_t arg2) 2615{ 2616 switch (type) { 2617 case TCG_TYPE_I32: 2618 tcg_out_st32(s, COND_AL, arg, arg1, arg2); 2619 return; 2620 case TCG_TYPE_V64: 2621 /* regs 1; size 8; align 8 */ 2622 tcg_out_vldst(s, INSN_VST1 | 0x7d0, arg, arg1, arg2); 2623 return; 2624 case TCG_TYPE_V128: 2625 /* See tcg_out_ld re alignment: regs 2; size 8; align 8 */ 2626 tcg_out_vldst(s, INSN_VST1 | 0xad0, arg, arg1, arg2); 2627 return; 2628 default: 2629 g_assert_not_reached(); 2630 } 2631} 2632 2633static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 2634 TCGReg base, intptr_t ofs) 2635{ 2636 return false; 2637} 2638 2639static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 2640{ 2641 if (ret == arg) { 2642 return true; 2643 } 2644 switch (type) { 2645 case TCG_TYPE_I32: 2646 if (ret < TCG_REG_Q0 && arg < TCG_REG_Q0) { 2647 tcg_out_mov_reg(s, COND_AL, ret, arg); 2648 return true; 2649 } 2650 return false; 2651 2652 case TCG_TYPE_V64: 2653 case TCG_TYPE_V128: 2654 /* "VMOV D,N" is an alias for "VORR D,N,N". */ 2655 tcg_out_vreg3(s, INSN_VORR, type - TCG_TYPE_V64, 0, ret, arg, arg); 2656 return true; 2657 2658 default: 2659 g_assert_not_reached(); 2660 } 2661} 2662 2663static void tcg_out_movi(TCGContext *s, TCGType type, 2664 TCGReg ret, tcg_target_long arg) 2665{ 2666 tcg_debug_assert(type == TCG_TYPE_I32); 2667 tcg_debug_assert(ret < TCG_REG_Q0); 2668 tcg_out_movi32(s, COND_AL, ret, arg); 2669} 2670 2671static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 2672{ 2673 return false; 2674} 2675 2676static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 2677 tcg_target_long imm) 2678{ 2679 int enc, opc = ARITH_ADD; 2680 2681 /* All of the easiest immediates to encode are positive. */ 2682 if (imm < 0) { 2683 imm = -imm; 2684 opc = ARITH_SUB; 2685 } 2686 enc = encode_imm(imm); 2687 if (enc >= 0) { 2688 tcg_out_dat_imm(s, COND_AL, opc, rd, rs, enc); 2689 } else { 2690 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, imm); 2691 tcg_out_dat_reg(s, COND_AL, opc, rd, rs, 2692 TCG_REG_TMP, SHIFT_IMM_LSL(0)); 2693 } 2694} 2695 2696/* Type is always V128, with I64 elements. */ 2697static void tcg_out_dup2_vec(TCGContext *s, TCGReg rd, TCGReg rl, TCGReg rh) 2698{ 2699 /* Move high element into place first. */ 2700 /* VMOV Dd+1, Ds */ 2701 tcg_out_vreg3(s, INSN_VORR | (1 << 12), 0, 0, rd, rh, rh); 2702 /* Move low element into place; tcg_out_mov will check for nop. */ 2703 tcg_out_mov(s, TCG_TYPE_V64, rd, rl); 2704} 2705 2706static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 2707 TCGReg rd, TCGReg rs) 2708{ 2709 int q = type - TCG_TYPE_V64; 2710 2711 if (vece == MO_64) { 2712 if (type == TCG_TYPE_V128) { 2713 tcg_out_dup2_vec(s, rd, rs, rs); 2714 } else { 2715 tcg_out_mov(s, TCG_TYPE_V64, rd, rs); 2716 } 2717 } else if (rs < TCG_REG_Q0) { 2718 int b = (vece == MO_8); 2719 int e = (vece == MO_16); 2720 tcg_out32(s, INSN_VDUP_G | (b << 22) | (q << 21) | (e << 5) | 2721 encode_vn(rd) | (rs << 12)); 2722 } else { 2723 int imm4 = 1 << vece; 2724 tcg_out32(s, INSN_VDUP_S | (imm4 << 16) | (q << 6) | 2725 encode_vd(rd) | encode_vm(rs)); 2726 } 2727 return true; 2728} 2729 2730static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 2731 TCGReg rd, TCGReg base, intptr_t offset) 2732{ 2733 if (vece == MO_64) { 2734 tcg_out_ld(s, TCG_TYPE_V64, rd, base, offset); 2735 if (type == TCG_TYPE_V128) { 2736 tcg_out_dup2_vec(s, rd, rd, rd); 2737 } 2738 } else { 2739 int q = type - TCG_TYPE_V64; 2740 tcg_out_vldst(s, INSN_VLD1R | (vece << 6) | (q << 5), 2741 rd, base, offset); 2742 } 2743 return true; 2744} 2745 2746static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 2747 TCGReg rd, int64_t v64) 2748{ 2749 int q = type - TCG_TYPE_V64; 2750 int cmode, imm8, i; 2751 2752 /* Test all bytes equal first. */ 2753 if (vece == MO_8) { 2754 tcg_out_vmovi(s, rd, q, 0, 0xe, v64); 2755 return; 2756 } 2757 2758 /* 2759 * Test all bytes 0x00 or 0xff second. This can match cases that 2760 * might otherwise take 2 or 3 insns for MO_16 or MO_32 below. 2761 */ 2762 for (i = imm8 = 0; i < 8; i++) { 2763 uint8_t byte = v64 >> (i * 8); 2764 if (byte == 0xff) { 2765 imm8 |= 1 << i; 2766 } else if (byte != 0) { 2767 goto fail_bytes; 2768 } 2769 } 2770 tcg_out_vmovi(s, rd, q, 1, 0xe, imm8); 2771 return; 2772 fail_bytes: 2773 2774 /* 2775 * Tests for various replications. For each element width, if we 2776 * cannot find an expansion there's no point checking a larger 2777 * width because we already know by replication it cannot match. 2778 */ 2779 if (vece == MO_16) { 2780 uint16_t v16 = v64; 2781 2782 if (is_shimm16(v16, &cmode, &imm8)) { 2783 tcg_out_vmovi(s, rd, q, 0, cmode, imm8); 2784 return; 2785 } 2786 if (is_shimm16(~v16, &cmode, &imm8)) { 2787 tcg_out_vmovi(s, rd, q, 1, cmode, imm8); 2788 return; 2789 } 2790 2791 /* 2792 * Otherwise, all remaining constants can be loaded in two insns: 2793 * rd = v16 & 0xff, rd |= v16 & 0xff00. 2794 */ 2795 tcg_out_vmovi(s, rd, q, 0, 0x8, v16 & 0xff); 2796 tcg_out_vmovi(s, rd, q, 0, 0xb, v16 >> 8); /* VORRI */ 2797 return; 2798 } 2799 2800 if (vece == MO_32) { 2801 uint32_t v32 = v64; 2802 2803 if (is_shimm32(v32, &cmode, &imm8) || 2804 is_soimm32(v32, &cmode, &imm8)) { 2805 tcg_out_vmovi(s, rd, q, 0, cmode, imm8); 2806 return; 2807 } 2808 if (is_shimm32(~v32, &cmode, &imm8) || 2809 is_soimm32(~v32, &cmode, &imm8)) { 2810 tcg_out_vmovi(s, rd, q, 1, cmode, imm8); 2811 return; 2812 } 2813 2814 /* 2815 * Restrict the set of constants to those we can load with 2816 * two instructions. Others we load from the pool. 2817 */ 2818 i = is_shimm32_pair(v32, &cmode, &imm8); 2819 if (i) { 2820 tcg_out_vmovi(s, rd, q, 0, cmode, imm8); 2821 tcg_out_vmovi(s, rd, q, 0, i | 1, extract32(v32, i * 4, 8)); 2822 return; 2823 } 2824 i = is_shimm32_pair(~v32, &cmode, &imm8); 2825 if (i) { 2826 tcg_out_vmovi(s, rd, q, 1, cmode, imm8); 2827 tcg_out_vmovi(s, rd, q, 1, i | 1, extract32(~v32, i * 4, 8)); 2828 return; 2829 } 2830 } 2831 2832 /* 2833 * As a last resort, load from the constant pool. 2834 */ 2835 if (!q || vece == MO_64) { 2836 new_pool_l2(s, R_ARM_PC11, s->code_ptr, 0, v64, v64 >> 32); 2837 /* VLDR Dd, [pc + offset] */ 2838 tcg_out32(s, INSN_VLDR_D | encode_vd(rd) | (0xf << 16)); 2839 if (q) { 2840 tcg_out_dup2_vec(s, rd, rd, rd); 2841 } 2842 } else { 2843 new_pool_label(s, (uint32_t)v64, R_ARM_PC8, s->code_ptr, 0); 2844 /* add tmp, pc, offset */ 2845 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_TMP, TCG_REG_PC, 0); 2846 tcg_out_dupm_vec(s, type, MO_32, rd, TCG_REG_TMP, 0); 2847 } 2848} 2849 2850static const ARMInsn vec_cmp_insn[16] = { 2851 [TCG_COND_EQ] = INSN_VCEQ, 2852 [TCG_COND_GT] = INSN_VCGT, 2853 [TCG_COND_GE] = INSN_VCGE, 2854 [TCG_COND_GTU] = INSN_VCGT_U, 2855 [TCG_COND_GEU] = INSN_VCGE_U, 2856}; 2857 2858static const ARMInsn vec_cmp0_insn[16] = { 2859 [TCG_COND_EQ] = INSN_VCEQ0, 2860 [TCG_COND_GT] = INSN_VCGT0, 2861 [TCG_COND_GE] = INSN_VCGE0, 2862 [TCG_COND_LT] = INSN_VCLT0, 2863 [TCG_COND_LE] = INSN_VCLE0, 2864}; 2865 2866static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 2867 unsigned vecl, unsigned vece, 2868 const TCGArg args[TCG_MAX_OP_ARGS], 2869 const int const_args[TCG_MAX_OP_ARGS]) 2870{ 2871 TCGType type = vecl + TCG_TYPE_V64; 2872 unsigned q = vecl; 2873 TCGArg a0, a1, a2, a3; 2874 int cmode, imm8; 2875 2876 a0 = args[0]; 2877 a1 = args[1]; 2878 a2 = args[2]; 2879 2880 switch (opc) { 2881 case INDEX_op_ld_vec: 2882 tcg_out_ld(s, type, a0, a1, a2); 2883 return; 2884 case INDEX_op_st_vec: 2885 tcg_out_st(s, type, a0, a1, a2); 2886 return; 2887 case INDEX_op_dupm_vec: 2888 tcg_out_dupm_vec(s, type, vece, a0, a1, a2); 2889 return; 2890 case INDEX_op_dup2_vec: 2891 tcg_out_dup2_vec(s, a0, a1, a2); 2892 return; 2893 case INDEX_op_abs_vec: 2894 tcg_out_vreg2(s, INSN_VABS, q, vece, a0, a1); 2895 return; 2896 case INDEX_op_neg_vec: 2897 tcg_out_vreg2(s, INSN_VNEG, q, vece, a0, a1); 2898 return; 2899 case INDEX_op_not_vec: 2900 tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a1); 2901 return; 2902 case INDEX_op_add_vec: 2903 tcg_out_vreg3(s, INSN_VADD, q, vece, a0, a1, a2); 2904 return; 2905 case INDEX_op_mul_vec: 2906 tcg_out_vreg3(s, INSN_VMUL, q, vece, a0, a1, a2); 2907 return; 2908 case INDEX_op_smax_vec: 2909 tcg_out_vreg3(s, INSN_VMAX, q, vece, a0, a1, a2); 2910 return; 2911 case INDEX_op_smin_vec: 2912 tcg_out_vreg3(s, INSN_VMIN, q, vece, a0, a1, a2); 2913 return; 2914 case INDEX_op_sub_vec: 2915 tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2); 2916 return; 2917 case INDEX_op_ssadd_vec: 2918 tcg_out_vreg3(s, INSN_VQADD, q, vece, a0, a1, a2); 2919 return; 2920 case INDEX_op_sssub_vec: 2921 tcg_out_vreg3(s, INSN_VQSUB, q, vece, a0, a1, a2); 2922 return; 2923 case INDEX_op_umax_vec: 2924 tcg_out_vreg3(s, INSN_VMAX_U, q, vece, a0, a1, a2); 2925 return; 2926 case INDEX_op_umin_vec: 2927 tcg_out_vreg3(s, INSN_VMIN_U, q, vece, a0, a1, a2); 2928 return; 2929 case INDEX_op_usadd_vec: 2930 tcg_out_vreg3(s, INSN_VQADD_U, q, vece, a0, a1, a2); 2931 return; 2932 case INDEX_op_ussub_vec: 2933 tcg_out_vreg3(s, INSN_VQSUB_U, q, vece, a0, a1, a2); 2934 return; 2935 case INDEX_op_xor_vec: 2936 tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2); 2937 return; 2938 case INDEX_op_arm_sshl_vec: 2939 /* 2940 * Note that Vm is the data and Vn is the shift count, 2941 * therefore the arguments appear reversed. 2942 */ 2943 tcg_out_vreg3(s, INSN_VSHL_S, q, vece, a0, a2, a1); 2944 return; 2945 case INDEX_op_arm_ushl_vec: 2946 /* See above. */ 2947 tcg_out_vreg3(s, INSN_VSHL_U, q, vece, a0, a2, a1); 2948 return; 2949 case INDEX_op_shli_vec: 2950 tcg_out_vshifti(s, INSN_VSHLI, q, a0, a1, a2 + (8 << vece)); 2951 return; 2952 case INDEX_op_shri_vec: 2953 tcg_out_vshifti(s, INSN_VSHRI, q, a0, a1, (16 << vece) - a2); 2954 return; 2955 case INDEX_op_sari_vec: 2956 tcg_out_vshifti(s, INSN_VSARI, q, a0, a1, (16 << vece) - a2); 2957 return; 2958 case INDEX_op_arm_sli_vec: 2959 tcg_out_vshifti(s, INSN_VSLI, q, a0, a2, args[3] + (8 << vece)); 2960 return; 2961 2962 case INDEX_op_andc_vec: 2963 if (!const_args[2]) { 2964 tcg_out_vreg3(s, INSN_VBIC, q, 0, a0, a1, a2); 2965 return; 2966 } 2967 a2 = ~a2; 2968 /* fall through */ 2969 case INDEX_op_and_vec: 2970 if (const_args[2]) { 2971 is_shimm1632(~a2, &cmode, &imm8); 2972 if (a0 == a1) { 2973 tcg_out_vmovi(s, a0, q, 1, cmode | 1, imm8); /* VBICI */ 2974 return; 2975 } 2976 tcg_out_vmovi(s, a0, q, 1, cmode, imm8); /* VMVNI */ 2977 a2 = a0; 2978 } 2979 tcg_out_vreg3(s, INSN_VAND, q, 0, a0, a1, a2); 2980 return; 2981 2982 case INDEX_op_orc_vec: 2983 if (!const_args[2]) { 2984 tcg_out_vreg3(s, INSN_VORN, q, 0, a0, a1, a2); 2985 return; 2986 } 2987 a2 = ~a2; 2988 /* fall through */ 2989 case INDEX_op_or_vec: 2990 if (const_args[2]) { 2991 is_shimm1632(a2, &cmode, &imm8); 2992 if (a0 == a1) { 2993 tcg_out_vmovi(s, a0, q, 0, cmode | 1, imm8); /* VORRI */ 2994 return; 2995 } 2996 tcg_out_vmovi(s, a0, q, 0, cmode, imm8); /* VMOVI */ 2997 a2 = a0; 2998 } 2999 tcg_out_vreg3(s, INSN_VORR, q, 0, a0, a1, a2); 3000 return; 3001 3002 case INDEX_op_cmp_vec: 3003 { 3004 TCGCond cond = args[3]; 3005 ARMInsn insn; 3006 3007 switch (cond) { 3008 case TCG_COND_NE: 3009 if (const_args[2]) { 3010 tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a1); 3011 } else { 3012 tcg_out_vreg3(s, INSN_VCEQ, q, vece, a0, a1, a2); 3013 tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0); 3014 } 3015 break; 3016 3017 case TCG_COND_TSTNE: 3018 case TCG_COND_TSTEQ: 3019 if (const_args[2]) { 3020 /* (x & 0) == 0 */ 3021 tcg_out_dupi_vec(s, type, MO_8, a0, 3022 -(cond == TCG_COND_TSTEQ)); 3023 break; 3024 } 3025 tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a2); 3026 if (cond == TCG_COND_TSTEQ) { 3027 tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0); 3028 } 3029 break; 3030 3031 default: 3032 if (const_args[2]) { 3033 insn = vec_cmp0_insn[cond]; 3034 if (insn) { 3035 tcg_out_vreg2(s, insn, q, vece, a0, a1); 3036 return; 3037 } 3038 tcg_out_dupi_vec(s, type, MO_8, TCG_VEC_TMP, 0); 3039 a2 = TCG_VEC_TMP; 3040 } 3041 insn = vec_cmp_insn[cond]; 3042 if (insn == 0) { 3043 TCGArg t; 3044 t = a1, a1 = a2, a2 = t; 3045 cond = tcg_swap_cond(cond); 3046 insn = vec_cmp_insn[cond]; 3047 tcg_debug_assert(insn != 0); 3048 } 3049 tcg_out_vreg3(s, insn, q, vece, a0, a1, a2); 3050 break; 3051 } 3052 } 3053 return; 3054 3055 case INDEX_op_bitsel_vec: 3056 a3 = args[3]; 3057 if (a0 == a3) { 3058 tcg_out_vreg3(s, INSN_VBIT, q, 0, a0, a2, a1); 3059 } else if (a0 == a2) { 3060 tcg_out_vreg3(s, INSN_VBIF, q, 0, a0, a3, a1); 3061 } else { 3062 tcg_out_mov(s, type, a0, a1); 3063 tcg_out_vreg3(s, INSN_VBSL, q, 0, a0, a2, a3); 3064 } 3065 return; 3066 3067 case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ 3068 case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ 3069 default: 3070 g_assert_not_reached(); 3071 } 3072} 3073 3074int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 3075{ 3076 switch (opc) { 3077 case INDEX_op_add_vec: 3078 case INDEX_op_sub_vec: 3079 case INDEX_op_and_vec: 3080 case INDEX_op_andc_vec: 3081 case INDEX_op_or_vec: 3082 case INDEX_op_orc_vec: 3083 case INDEX_op_xor_vec: 3084 case INDEX_op_not_vec: 3085 case INDEX_op_shli_vec: 3086 case INDEX_op_shri_vec: 3087 case INDEX_op_sari_vec: 3088 case INDEX_op_ssadd_vec: 3089 case INDEX_op_sssub_vec: 3090 case INDEX_op_usadd_vec: 3091 case INDEX_op_ussub_vec: 3092 case INDEX_op_bitsel_vec: 3093 return 1; 3094 case INDEX_op_abs_vec: 3095 case INDEX_op_cmp_vec: 3096 case INDEX_op_mul_vec: 3097 case INDEX_op_neg_vec: 3098 case INDEX_op_smax_vec: 3099 case INDEX_op_smin_vec: 3100 case INDEX_op_umax_vec: 3101 case INDEX_op_umin_vec: 3102 return vece < MO_64; 3103 case INDEX_op_shlv_vec: 3104 case INDEX_op_shrv_vec: 3105 case INDEX_op_sarv_vec: 3106 case INDEX_op_rotli_vec: 3107 case INDEX_op_rotlv_vec: 3108 case INDEX_op_rotrv_vec: 3109 return -1; 3110 default: 3111 return 0; 3112 } 3113} 3114 3115void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 3116 TCGArg a0, ...) 3117{ 3118 va_list va; 3119 TCGv_vec v0, v1, v2, t1, t2, c1; 3120 TCGArg a2; 3121 3122 va_start(va, a0); 3123 v0 = temp_tcgv_vec(arg_temp(a0)); 3124 v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 3125 a2 = va_arg(va, TCGArg); 3126 va_end(va); 3127 3128 switch (opc) { 3129 case INDEX_op_shlv_vec: 3130 /* 3131 * Merely propagate shlv_vec to arm_ushl_vec. 3132 * In this way we don't set TCG_TARGET_HAS_shv_vec 3133 * because everything is done via expansion. 3134 */ 3135 v2 = temp_tcgv_vec(arg_temp(a2)); 3136 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0), 3137 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 3138 break; 3139 3140 case INDEX_op_shrv_vec: 3141 case INDEX_op_sarv_vec: 3142 /* Right shifts are negative left shifts for NEON. */ 3143 v2 = temp_tcgv_vec(arg_temp(a2)); 3144 t1 = tcg_temp_new_vec(type); 3145 tcg_gen_neg_vec(vece, t1, v2); 3146 if (opc == INDEX_op_shrv_vec) { 3147 opc = INDEX_op_arm_ushl_vec; 3148 } else { 3149 opc = INDEX_op_arm_sshl_vec; 3150 } 3151 vec_gen_3(opc, type, vece, tcgv_vec_arg(v0), 3152 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 3153 tcg_temp_free_vec(t1); 3154 break; 3155 3156 case INDEX_op_rotli_vec: 3157 t1 = tcg_temp_new_vec(type); 3158 tcg_gen_shri_vec(vece, t1, v1, -a2 & ((8 << vece) - 1)); 3159 vec_gen_4(INDEX_op_arm_sli_vec, type, vece, 3160 tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(v1), a2); 3161 tcg_temp_free_vec(t1); 3162 break; 3163 3164 case INDEX_op_rotlv_vec: 3165 v2 = temp_tcgv_vec(arg_temp(a2)); 3166 t1 = tcg_temp_new_vec(type); 3167 c1 = tcg_constant_vec(type, vece, 8 << vece); 3168 tcg_gen_sub_vec(vece, t1, v2, c1); 3169 /* Right shifts are negative left shifts for NEON. */ 3170 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1), 3171 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 3172 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0), 3173 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 3174 tcg_gen_or_vec(vece, v0, v0, t1); 3175 tcg_temp_free_vec(t1); 3176 break; 3177 3178 case INDEX_op_rotrv_vec: 3179 v2 = temp_tcgv_vec(arg_temp(a2)); 3180 t1 = tcg_temp_new_vec(type); 3181 t2 = tcg_temp_new_vec(type); 3182 c1 = tcg_constant_vec(type, vece, 8 << vece); 3183 tcg_gen_neg_vec(vece, t1, v2); 3184 tcg_gen_sub_vec(vece, t2, c1, v2); 3185 /* Right shifts are negative left shifts for NEON. */ 3186 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1), 3187 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 3188 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t2), 3189 tcgv_vec_arg(v1), tcgv_vec_arg(t2)); 3190 tcg_gen_or_vec(vece, v0, t1, t2); 3191 tcg_temp_free_vec(t1); 3192 tcg_temp_free_vec(t2); 3193 break; 3194 3195 default: 3196 g_assert_not_reached(); 3197 } 3198} 3199 3200static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 3201{ 3202 int i; 3203 for (i = 0; i < count; ++i) { 3204 p[i] = INSN_NOP; 3205 } 3206} 3207 3208/* Compute frame size via macros, to share between tcg_target_qemu_prologue 3209 and tcg_register_jit. */ 3210 3211#define PUSH_SIZE ((11 - 4 + 1 + 1) * sizeof(tcg_target_long)) 3212 3213#define FRAME_SIZE \ 3214 ((PUSH_SIZE \ 3215 + TCG_STATIC_CALL_ARGS_SIZE \ 3216 + CPU_TEMP_BUF_NLONGS * sizeof(long) \ 3217 + TCG_TARGET_STACK_ALIGN - 1) \ 3218 & -TCG_TARGET_STACK_ALIGN) 3219 3220#define STACK_ADDEND (FRAME_SIZE - PUSH_SIZE) 3221 3222static void tcg_target_qemu_prologue(TCGContext *s) 3223{ 3224 /* Calling convention requires us to save r4-r11 and lr. */ 3225 /* stmdb sp!, { r4 - r11, lr } */ 3226 tcg_out_ldstm(s, COND_AL, INSN_STMDB, TCG_REG_CALL_STACK, 3227 (1 << TCG_REG_R4) | (1 << TCG_REG_R5) | (1 << TCG_REG_R6) | 3228 (1 << TCG_REG_R7) | (1 << TCG_REG_R8) | (1 << TCG_REG_R9) | 3229 (1 << TCG_REG_R10) | (1 << TCG_REG_R11) | (1 << TCG_REG_R14)); 3230 3231 /* Reserve callee argument and tcg temp space. */ 3232 tcg_out_dat_rI(s, COND_AL, ARITH_SUB, TCG_REG_CALL_STACK, 3233 TCG_REG_CALL_STACK, STACK_ADDEND, 1); 3234 tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE, 3235 CPU_TEMP_BUF_NLONGS * sizeof(long)); 3236 3237 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 3238 3239 if (!tcg_use_softmmu && guest_base) { 3240 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_GUEST_BASE, guest_base); 3241 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GUEST_BASE); 3242 } 3243 3244 tcg_out_b_reg(s, COND_AL, tcg_target_call_iarg_regs[1]); 3245 3246 /* 3247 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 3248 * and fall through to the rest of the epilogue. 3249 */ 3250 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 3251 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, 0); 3252 tcg_out_epilogue(s); 3253} 3254 3255static void tcg_out_epilogue(TCGContext *s) 3256{ 3257 /* Release local stack frame. */ 3258 tcg_out_dat_rI(s, COND_AL, ARITH_ADD, TCG_REG_CALL_STACK, 3259 TCG_REG_CALL_STACK, STACK_ADDEND, 1); 3260 3261 /* ldmia sp!, { r4 - r11, pc } */ 3262 tcg_out_ldstm(s, COND_AL, INSN_LDMIA, TCG_REG_CALL_STACK, 3263 (1 << TCG_REG_R4) | (1 << TCG_REG_R5) | (1 << TCG_REG_R6) | 3264 (1 << TCG_REG_R7) | (1 << TCG_REG_R8) | (1 << TCG_REG_R9) | 3265 (1 << TCG_REG_R10) | (1 << TCG_REG_R11) | (1 << TCG_REG_PC)); 3266} 3267 3268static void tcg_out_tb_start(TCGContext *s) 3269{ 3270 /* nothing to do */ 3271} 3272 3273typedef struct { 3274 DebugFrameHeader h; 3275 uint8_t fde_def_cfa[4]; 3276 uint8_t fde_reg_ofs[18]; 3277} DebugFrame; 3278 3279#define ELF_HOST_MACHINE EM_ARM 3280 3281/* We're expecting a 2 byte uleb128 encoded value. */ 3282QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); 3283 3284static const DebugFrame debug_frame = { 3285 .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ 3286 .h.cie.id = -1, 3287 .h.cie.version = 1, 3288 .h.cie.code_align = 1, 3289 .h.cie.data_align = 0x7c, /* sleb128 -4 */ 3290 .h.cie.return_column = 14, 3291 3292 /* Total FDE size does not include the "len" member. */ 3293 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 3294 3295 .fde_def_cfa = { 3296 12, 13, /* DW_CFA_def_cfa sp, ... */ 3297 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 3298 (FRAME_SIZE >> 7) 3299 }, 3300 .fde_reg_ofs = { 3301 /* The following must match the stmdb in the prologue. */ 3302 0x8e, 1, /* DW_CFA_offset, lr, -4 */ 3303 0x8b, 2, /* DW_CFA_offset, r11, -8 */ 3304 0x8a, 3, /* DW_CFA_offset, r10, -12 */ 3305 0x89, 4, /* DW_CFA_offset, r9, -16 */ 3306 0x88, 5, /* DW_CFA_offset, r8, -20 */ 3307 0x87, 6, /* DW_CFA_offset, r7, -24 */ 3308 0x86, 7, /* DW_CFA_offset, r6, -28 */ 3309 0x85, 8, /* DW_CFA_offset, r5, -32 */ 3310 0x84, 9, /* DW_CFA_offset, r4, -36 */ 3311 } 3312}; 3313 3314void tcg_register_jit(const void *buf, size_t buf_size) 3315{ 3316 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 3317} 3318