1 /* 2 * Initial TCG Implementation for aarch64 3 * 4 * Copyright (c) 2013 Huawei Technologies Duesseldorf GmbH 5 * Written by Claudio Fontana 6 * 7 * This work is licensed under the terms of the GNU GPL, version 2 or 8 * (at your option) any later version. 9 * 10 * See the COPYING file in the top-level directory for details. 11 */ 12 13 #ifndef TCG_TARGET_AARCH64 14 #define TCG_TARGET_AARCH64 1 15 16 #undef TCG_TARGET_WORDS_BIGENDIAN 17 #undef TCG_TARGET_STACK_GROWSUP 18 19 typedef enum { 20 TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3, TCG_REG_X4, 21 TCG_REG_X5, TCG_REG_X6, TCG_REG_X7, TCG_REG_X8, TCG_REG_X9, 22 TCG_REG_X10, TCG_REG_X11, TCG_REG_X12, TCG_REG_X13, TCG_REG_X14, 23 TCG_REG_X15, TCG_REG_X16, TCG_REG_X17, TCG_REG_X18, TCG_REG_X19, 24 TCG_REG_X20, TCG_REG_X21, TCG_REG_X22, TCG_REG_X23, TCG_REG_X24, 25 TCG_REG_X25, TCG_REG_X26, TCG_REG_X27, TCG_REG_X28, 26 TCG_REG_FP, /* frame pointer */ 27 TCG_REG_LR, /* link register */ 28 TCG_REG_SP, /* stack pointer or zero register */ 29 TCG_REG_XZR = TCG_REG_SP /* same register number */ 30 /* program counter is not directly accessible! */ 31 } TCGReg; 32 33 #define TCG_TARGET_NB_REGS 32 34 35 /* used for function call generation */ 36 #define TCG_REG_CALL_STACK TCG_REG_SP 37 #define TCG_TARGET_STACK_ALIGN 16 38 #define TCG_TARGET_CALL_ALIGN_ARGS 1 39 #define TCG_TARGET_CALL_STACK_OFFSET 0 40 41 /* optional instructions */ 42 #define TCG_TARGET_HAS_div_i32 0 43 #define TCG_TARGET_HAS_rem_i32 0 44 #define TCG_TARGET_HAS_ext8s_i32 1 45 #define TCG_TARGET_HAS_ext16s_i32 1 46 #define TCG_TARGET_HAS_ext8u_i32 1 47 #define TCG_TARGET_HAS_ext16u_i32 1 48 #define TCG_TARGET_HAS_bswap16_i32 1 49 #define TCG_TARGET_HAS_bswap32_i32 1 50 #define TCG_TARGET_HAS_not_i32 0 51 #define TCG_TARGET_HAS_neg_i32 0 52 #define TCG_TARGET_HAS_rot_i32 1 53 #define TCG_TARGET_HAS_andc_i32 0 54 #define TCG_TARGET_HAS_orc_i32 0 55 #define TCG_TARGET_HAS_eqv_i32 0 56 #define TCG_TARGET_HAS_nand_i32 0 57 #define TCG_TARGET_HAS_nor_i32 0 58 #define TCG_TARGET_HAS_deposit_i32 0 59 #define TCG_TARGET_HAS_movcond_i32 0 60 #define TCG_TARGET_HAS_add2_i32 0 61 #define TCG_TARGET_HAS_sub2_i32 0 62 #define TCG_TARGET_HAS_mulu2_i32 0 63 #define TCG_TARGET_HAS_muls2_i32 0 64 #define TCG_TARGET_HAS_muluh_i32 0 65 #define TCG_TARGET_HAS_mulsh_i32 0 66 67 #define TCG_TARGET_HAS_div_i64 0 68 #define TCG_TARGET_HAS_rem_i64 0 69 #define TCG_TARGET_HAS_ext8s_i64 1 70 #define TCG_TARGET_HAS_ext16s_i64 1 71 #define TCG_TARGET_HAS_ext32s_i64 1 72 #define TCG_TARGET_HAS_ext8u_i64 1 73 #define TCG_TARGET_HAS_ext16u_i64 1 74 #define TCG_TARGET_HAS_ext32u_i64 1 75 #define TCG_TARGET_HAS_bswap16_i64 1 76 #define TCG_TARGET_HAS_bswap32_i64 1 77 #define TCG_TARGET_HAS_bswap64_i64 1 78 #define TCG_TARGET_HAS_not_i64 0 79 #define TCG_TARGET_HAS_neg_i64 0 80 #define TCG_TARGET_HAS_rot_i64 1 81 #define TCG_TARGET_HAS_andc_i64 0 82 #define TCG_TARGET_HAS_orc_i64 0 83 #define TCG_TARGET_HAS_eqv_i64 0 84 #define TCG_TARGET_HAS_nand_i64 0 85 #define TCG_TARGET_HAS_nor_i64 0 86 #define TCG_TARGET_HAS_deposit_i64 0 87 #define TCG_TARGET_HAS_movcond_i64 0 88 #define TCG_TARGET_HAS_add2_i64 0 89 #define TCG_TARGET_HAS_sub2_i64 0 90 #define TCG_TARGET_HAS_mulu2_i64 0 91 #define TCG_TARGET_HAS_muls2_i64 0 92 #define TCG_TARGET_HAS_muluh_i64 0 93 #define TCG_TARGET_HAS_mulsh_i64 0 94 95 enum { 96 TCG_AREG0 = TCG_REG_X19, 97 }; 98 99 static inline void flush_icache_range(uintptr_t start, uintptr_t stop) 100 { 101 __builtin___clear_cache((char *)start, (char *)stop); 102 } 103 104 #endif /* TCG_TARGET_AARCH64 */ 105