1/* 2 * Initial TCG Implementation for aarch64 3 * 4 * Copyright (c) 2013 Huawei Technologies Duesseldorf GmbH 5 * Written by Claudio Fontana 6 * 7 * This work is licensed under the terms of the GNU GPL, version 2 or 8 * (at your option) any later version. 9 * 10 * See the COPYING file in the top-level directory for details. 11 */ 12 13#include "qemu/bitops.h" 14 15/* Used for function call generation. */ 16#define TCG_REG_CALL_STACK TCG_REG_SP 17#define TCG_TARGET_STACK_ALIGN 16 18#define TCG_TARGET_CALL_STACK_OFFSET 0 19#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL 20#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL 21#ifdef CONFIG_DARWIN 22# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL 23#else 24# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN 25#endif 26#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL 27 28/* We're going to re-use TCGType in setting of the SF bit, which controls 29 the size of the operation performed. If we know the values match, it 30 makes things much cleaner. */ 31QEMU_BUILD_BUG_ON(TCG_TYPE_I32 != 0 || TCG_TYPE_I64 != 1); 32 33#ifdef CONFIG_DEBUG_TCG 34static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 35 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", 36 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", 37 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", 38 "x24", "x25", "x26", "x27", "x28", "fp", "x30", "sp", 39 40 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 41 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 42 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 43 "v24", "v25", "v26", "v27", "v28", "fp", "v30", "v31", 44}; 45#endif /* CONFIG_DEBUG_TCG */ 46 47static const int tcg_target_reg_alloc_order[] = { 48 TCG_REG_X20, TCG_REG_X21, TCG_REG_X22, TCG_REG_X23, 49 TCG_REG_X24, TCG_REG_X25, TCG_REG_X26, TCG_REG_X27, 50 TCG_REG_X28, /* we will reserve this for guest_base if configured */ 51 52 TCG_REG_X8, TCG_REG_X9, TCG_REG_X10, TCG_REG_X11, 53 TCG_REG_X12, TCG_REG_X13, TCG_REG_X14, TCG_REG_X15, 54 55 TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3, 56 TCG_REG_X4, TCG_REG_X5, TCG_REG_X6, TCG_REG_X7, 57 58 /* X16 reserved as temporary */ 59 /* X17 reserved as temporary */ 60 /* X18 reserved by system */ 61 /* X19 reserved for AREG0 */ 62 /* X29 reserved as fp */ 63 /* X30 reserved as temporary */ 64 65 TCG_REG_V0, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3, 66 TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7, 67 /* V8 - V15 are call-saved, and skipped. */ 68 TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19, 69 TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23, 70 TCG_REG_V24, TCG_REG_V25, TCG_REG_V26, TCG_REG_V27, 71 TCG_REG_V28, TCG_REG_V29, TCG_REG_V30, TCG_REG_V31, 72}; 73 74static const int tcg_target_call_iarg_regs[8] = { 75 TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3, 76 TCG_REG_X4, TCG_REG_X5, TCG_REG_X6, TCG_REG_X7 77}; 78 79static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 80{ 81 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 82 tcg_debug_assert(slot >= 0 && slot <= 1); 83 return TCG_REG_X0 + slot; 84} 85 86#define TCG_REG_TMP0 TCG_REG_X16 87#define TCG_REG_TMP1 TCG_REG_X17 88#define TCG_REG_TMP2 TCG_REG_X30 89#define TCG_VEC_TMP0 TCG_REG_V31 90 91#define TCG_REG_GUEST_BASE TCG_REG_X28 92 93static bool reloc_pc26(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 94{ 95 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 96 ptrdiff_t offset = target - src_rx; 97 98 if (offset == sextract64(offset, 0, 26)) { 99 /* read instruction, mask away previous PC_REL26 parameter contents, 100 set the proper offset, then write back the instruction. */ 101 *src_rw = deposit32(*src_rw, 0, 26, offset); 102 return true; 103 } 104 return false; 105} 106 107static bool reloc_pc19(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 108{ 109 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 110 ptrdiff_t offset = target - src_rx; 111 112 if (offset == sextract64(offset, 0, 19)) { 113 *src_rw = deposit32(*src_rw, 5, 19, offset); 114 return true; 115 } 116 return false; 117} 118 119static bool reloc_pc14(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 120{ 121 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 122 ptrdiff_t offset = target - src_rx; 123 124 if (offset == sextract64(offset, 0, 14)) { 125 *src_rw = deposit32(*src_rw, 5, 14, offset); 126 return true; 127 } 128 return false; 129} 130 131static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 132 intptr_t value, intptr_t addend) 133{ 134 tcg_debug_assert(addend == 0); 135 switch (type) { 136 case R_AARCH64_JUMP26: 137 case R_AARCH64_CALL26: 138 return reloc_pc26(code_ptr, (const tcg_insn_unit *)value); 139 case R_AARCH64_CONDBR19: 140 return reloc_pc19(code_ptr, (const tcg_insn_unit *)value); 141 case R_AARCH64_TSTBR14: 142 return reloc_pc14(code_ptr, (const tcg_insn_unit *)value); 143 default: 144 g_assert_not_reached(); 145 } 146} 147 148#define TCG_CT_CONST_AIMM 0x100 149#define TCG_CT_CONST_LIMM 0x200 150#define TCG_CT_CONST_ZERO 0x400 151#define TCG_CT_CONST_MONE 0x800 152#define TCG_CT_CONST_ORRI 0x1000 153#define TCG_CT_CONST_ANDI 0x2000 154#define TCG_CT_CONST_CMP 0x4000 155 156#define ALL_GENERAL_REGS 0xffffffffu 157#define ALL_VECTOR_REGS 0xffffffff00000000ull 158 159/* Match a constant valid for addition (12-bit, optionally shifted). */ 160static inline bool is_aimm(uint64_t val) 161{ 162 return (val & ~0xfff) == 0 || (val & ~0xfff000) == 0; 163} 164 165/* Match a constant valid for logical operations. */ 166static inline bool is_limm(uint64_t val) 167{ 168 /* Taking a simplified view of the logical immediates for now, ignoring 169 the replication that can happen across the field. Match bit patterns 170 of the forms 171 0....01....1 172 0..01..10..0 173 and their inverses. */ 174 175 /* Make things easier below, by testing the form with msb clear. */ 176 if ((int64_t)val < 0) { 177 val = ~val; 178 } 179 if (val == 0) { 180 return false; 181 } 182 val += val & -val; 183 return (val & (val - 1)) == 0; 184} 185 186/* Return true if v16 is a valid 16-bit shifted immediate. */ 187static bool is_shimm16(uint16_t v16, int *cmode, int *imm8) 188{ 189 if (v16 == (v16 & 0xff)) { 190 *cmode = 0x8; 191 *imm8 = v16 & 0xff; 192 return true; 193 } else if (v16 == (v16 & 0xff00)) { 194 *cmode = 0xa; 195 *imm8 = v16 >> 8; 196 return true; 197 } 198 return false; 199} 200 201/* Return true if v32 is a valid 32-bit shifted immediate. */ 202static bool is_shimm32(uint32_t v32, int *cmode, int *imm8) 203{ 204 if (v32 == (v32 & 0xff)) { 205 *cmode = 0x0; 206 *imm8 = v32 & 0xff; 207 return true; 208 } else if (v32 == (v32 & 0xff00)) { 209 *cmode = 0x2; 210 *imm8 = (v32 >> 8) & 0xff; 211 return true; 212 } else if (v32 == (v32 & 0xff0000)) { 213 *cmode = 0x4; 214 *imm8 = (v32 >> 16) & 0xff; 215 return true; 216 } else if (v32 == (v32 & 0xff000000)) { 217 *cmode = 0x6; 218 *imm8 = v32 >> 24; 219 return true; 220 } 221 return false; 222} 223 224/* Return true if v32 is a valid 32-bit shifting ones immediate. */ 225static bool is_soimm32(uint32_t v32, int *cmode, int *imm8) 226{ 227 if ((v32 & 0xffff00ff) == 0xff) { 228 *cmode = 0xc; 229 *imm8 = (v32 >> 8) & 0xff; 230 return true; 231 } else if ((v32 & 0xff00ffff) == 0xffff) { 232 *cmode = 0xd; 233 *imm8 = (v32 >> 16) & 0xff; 234 return true; 235 } 236 return false; 237} 238 239/* Return true if v32 is a valid float32 immediate. */ 240static bool is_fimm32(uint32_t v32, int *cmode, int *imm8) 241{ 242 if (extract32(v32, 0, 19) == 0 243 && (extract32(v32, 25, 6) == 0x20 244 || extract32(v32, 25, 6) == 0x1f)) { 245 *cmode = 0xf; 246 *imm8 = (extract32(v32, 31, 1) << 7) 247 | (extract32(v32, 25, 1) << 6) 248 | extract32(v32, 19, 6); 249 return true; 250 } 251 return false; 252} 253 254/* Return true if v64 is a valid float64 immediate. */ 255static bool is_fimm64(uint64_t v64, int *cmode, int *imm8) 256{ 257 if (extract64(v64, 0, 48) == 0 258 && (extract64(v64, 54, 9) == 0x100 259 || extract64(v64, 54, 9) == 0x0ff)) { 260 *cmode = 0xf; 261 *imm8 = (extract64(v64, 63, 1) << 7) 262 | (extract64(v64, 54, 1) << 6) 263 | extract64(v64, 48, 6); 264 return true; 265 } 266 return false; 267} 268 269/* 270 * Return non-zero if v32 can be formed by MOVI+ORR. 271 * Place the parameters for MOVI in (cmode, imm8). 272 * Return the cmode for ORR; the imm8 can be had via extraction from v32. 273 */ 274static int is_shimm32_pair(uint32_t v32, int *cmode, int *imm8) 275{ 276 int i; 277 278 for (i = 6; i > 0; i -= 2) { 279 /* Mask out one byte we can add with ORR. */ 280 uint32_t tmp = v32 & ~(0xffu << (i * 4)); 281 if (is_shimm32(tmp, cmode, imm8) || 282 is_soimm32(tmp, cmode, imm8)) { 283 break; 284 } 285 } 286 return i; 287} 288 289/* Return true if V is a valid 16-bit or 32-bit shifted immediate. */ 290static bool is_shimm1632(uint32_t v32, int *cmode, int *imm8) 291{ 292 if (v32 == deposit32(v32, 16, 16, v32)) { 293 return is_shimm16(v32, cmode, imm8); 294 } else { 295 return is_shimm32(v32, cmode, imm8); 296 } 297} 298 299static bool tcg_target_const_match(int64_t val, int ct, 300 TCGType type, TCGCond cond, int vece) 301{ 302 if (ct & TCG_CT_CONST) { 303 return 1; 304 } 305 if (type == TCG_TYPE_I32) { 306 val = (int32_t)val; 307 } 308 309 if (ct & TCG_CT_CONST_CMP) { 310 if (is_tst_cond(cond)) { 311 ct |= TCG_CT_CONST_LIMM; 312 } else { 313 ct |= TCG_CT_CONST_AIMM; 314 } 315 } 316 317 if ((ct & TCG_CT_CONST_AIMM) && (is_aimm(val) || is_aimm(-val))) { 318 return 1; 319 } 320 if ((ct & TCG_CT_CONST_LIMM) && is_limm(val)) { 321 return 1; 322 } 323 if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 324 return 1; 325 } 326 if ((ct & TCG_CT_CONST_MONE) && val == -1) { 327 return 1; 328 } 329 330 switch (ct & (TCG_CT_CONST_ORRI | TCG_CT_CONST_ANDI)) { 331 case 0: 332 break; 333 case TCG_CT_CONST_ANDI: 334 val = ~val; 335 /* fallthru */ 336 case TCG_CT_CONST_ORRI: 337 if (val == deposit64(val, 32, 32, val)) { 338 int cmode, imm8; 339 return is_shimm1632(val, &cmode, &imm8); 340 } 341 break; 342 default: 343 /* Both bits should not be set for the same insn. */ 344 g_assert_not_reached(); 345 } 346 347 return 0; 348} 349 350enum aarch64_cond_code { 351 COND_EQ = 0x0, 352 COND_NE = 0x1, 353 COND_CS = 0x2, /* Unsigned greater or equal */ 354 COND_HS = COND_CS, /* ALIAS greater or equal */ 355 COND_CC = 0x3, /* Unsigned less than */ 356 COND_LO = COND_CC, /* ALIAS Lower */ 357 COND_MI = 0x4, /* Negative */ 358 COND_PL = 0x5, /* Zero or greater */ 359 COND_VS = 0x6, /* Overflow */ 360 COND_VC = 0x7, /* No overflow */ 361 COND_HI = 0x8, /* Unsigned greater than */ 362 COND_LS = 0x9, /* Unsigned less or equal */ 363 COND_GE = 0xa, 364 COND_LT = 0xb, 365 COND_GT = 0xc, 366 COND_LE = 0xd, 367 COND_AL = 0xe, 368 COND_NV = 0xf, /* behaves like COND_AL here */ 369}; 370 371static const enum aarch64_cond_code tcg_cond_to_aarch64[] = { 372 [TCG_COND_EQ] = COND_EQ, 373 [TCG_COND_NE] = COND_NE, 374 [TCG_COND_LT] = COND_LT, 375 [TCG_COND_GE] = COND_GE, 376 [TCG_COND_LE] = COND_LE, 377 [TCG_COND_GT] = COND_GT, 378 /* unsigned */ 379 [TCG_COND_LTU] = COND_LO, 380 [TCG_COND_GTU] = COND_HI, 381 [TCG_COND_GEU] = COND_HS, 382 [TCG_COND_LEU] = COND_LS, 383 /* bit test */ 384 [TCG_COND_TSTEQ] = COND_EQ, 385 [TCG_COND_TSTNE] = COND_NE, 386}; 387 388typedef enum { 389 LDST_ST = 0, /* store */ 390 LDST_LD = 1, /* load */ 391 LDST_LD_S_X = 2, /* load and sign-extend into Xt */ 392 LDST_LD_S_W = 3, /* load and sign-extend into Wt */ 393} AArch64LdstType; 394 395/* We encode the format of the insn into the beginning of the name, so that 396 we can have the preprocessor help "typecheck" the insn vs the output 397 function. Arm didn't provide us with nice names for the formats, so we 398 use the section number of the architecture reference manual in which the 399 instruction group is described. */ 400typedef enum { 401 /* Compare and branch (immediate). */ 402 I3201_CBZ = 0x34000000, 403 I3201_CBNZ = 0x35000000, 404 405 /* Conditional branch (immediate). */ 406 I3202_B_C = 0x54000000, 407 408 /* Test and branch (immediate). */ 409 I3205_TBZ = 0x36000000, 410 I3205_TBNZ = 0x37000000, 411 412 /* Unconditional branch (immediate). */ 413 I3206_B = 0x14000000, 414 I3206_BL = 0x94000000, 415 416 /* Unconditional branch (register). */ 417 I3207_BR = 0xd61f0000, 418 I3207_BLR = 0xd63f0000, 419 I3207_RET = 0xd65f0000, 420 421 /* AdvSIMD load/store single structure. */ 422 I3303_LD1R = 0x0d40c000, 423 424 /* Load literal for loading the address at pc-relative offset */ 425 I3305_LDR = 0x58000000, 426 I3305_LDR_v64 = 0x5c000000, 427 I3305_LDR_v128 = 0x9c000000, 428 429 /* Load/store exclusive. */ 430 I3306_LDXP = 0xc8600000, 431 I3306_STXP = 0xc8200000, 432 433 /* Load/store register. Described here as 3.3.12, but the helper 434 that emits them can transform to 3.3.10 or 3.3.13. */ 435 I3312_STRB = 0x38000000 | LDST_ST << 22 | MO_8 << 30, 436 I3312_STRH = 0x38000000 | LDST_ST << 22 | MO_16 << 30, 437 I3312_STRW = 0x38000000 | LDST_ST << 22 | MO_32 << 30, 438 I3312_STRX = 0x38000000 | LDST_ST << 22 | MO_64 << 30, 439 440 I3312_LDRB = 0x38000000 | LDST_LD << 22 | MO_8 << 30, 441 I3312_LDRH = 0x38000000 | LDST_LD << 22 | MO_16 << 30, 442 I3312_LDRW = 0x38000000 | LDST_LD << 22 | MO_32 << 30, 443 I3312_LDRX = 0x38000000 | LDST_LD << 22 | MO_64 << 30, 444 445 I3312_LDRSBW = 0x38000000 | LDST_LD_S_W << 22 | MO_8 << 30, 446 I3312_LDRSHW = 0x38000000 | LDST_LD_S_W << 22 | MO_16 << 30, 447 448 I3312_LDRSBX = 0x38000000 | LDST_LD_S_X << 22 | MO_8 << 30, 449 I3312_LDRSHX = 0x38000000 | LDST_LD_S_X << 22 | MO_16 << 30, 450 I3312_LDRSWX = 0x38000000 | LDST_LD_S_X << 22 | MO_32 << 30, 451 452 I3312_LDRVS = 0x3c000000 | LDST_LD << 22 | MO_32 << 30, 453 I3312_STRVS = 0x3c000000 | LDST_ST << 22 | MO_32 << 30, 454 455 I3312_LDRVD = 0x3c000000 | LDST_LD << 22 | MO_64 << 30, 456 I3312_STRVD = 0x3c000000 | LDST_ST << 22 | MO_64 << 30, 457 458 I3312_LDRVQ = 0x3c000000 | 3 << 22 | 0 << 30, 459 I3312_STRVQ = 0x3c000000 | 2 << 22 | 0 << 30, 460 461 I3312_TO_I3310 = 0x00200800, 462 I3312_TO_I3313 = 0x01000000, 463 464 /* Load/store register pair instructions. */ 465 I3314_LDP = 0x28400000, 466 I3314_STP = 0x28000000, 467 468 /* Add/subtract immediate instructions. */ 469 I3401_ADDI = 0x11000000, 470 I3401_ADDSI = 0x31000000, 471 I3401_SUBI = 0x51000000, 472 I3401_SUBSI = 0x71000000, 473 474 /* Bitfield instructions. */ 475 I3402_BFM = 0x33000000, 476 I3402_SBFM = 0x13000000, 477 I3402_UBFM = 0x53000000, 478 479 /* Extract instruction. */ 480 I3403_EXTR = 0x13800000, 481 482 /* Logical immediate instructions. */ 483 I3404_ANDI = 0x12000000, 484 I3404_ORRI = 0x32000000, 485 I3404_EORI = 0x52000000, 486 I3404_ANDSI = 0x72000000, 487 488 /* Move wide immediate instructions. */ 489 I3405_MOVN = 0x12800000, 490 I3405_MOVZ = 0x52800000, 491 I3405_MOVK = 0x72800000, 492 493 /* PC relative addressing instructions. */ 494 I3406_ADR = 0x10000000, 495 I3406_ADRP = 0x90000000, 496 497 /* Add/subtract extended register instructions. */ 498 I3501_ADD = 0x0b200000, 499 500 /* Add/subtract shifted register instructions (without a shift). */ 501 I3502_ADD = 0x0b000000, 502 I3502_ADDS = 0x2b000000, 503 I3502_SUB = 0x4b000000, 504 I3502_SUBS = 0x6b000000, 505 506 /* Add/subtract shifted register instructions (with a shift). */ 507 I3502S_ADD_LSL = I3502_ADD, 508 509 /* Add/subtract with carry instructions. */ 510 I3503_ADC = 0x1a000000, 511 I3503_SBC = 0x5a000000, 512 513 /* Conditional select instructions. */ 514 I3506_CSEL = 0x1a800000, 515 I3506_CSINC = 0x1a800400, 516 I3506_CSINV = 0x5a800000, 517 I3506_CSNEG = 0x5a800400, 518 519 /* Data-processing (1 source) instructions. */ 520 I3507_CLZ = 0x5ac01000, 521 I3507_RBIT = 0x5ac00000, 522 I3507_REV = 0x5ac00000, /* + size << 10 */ 523 524 /* Data-processing (2 source) instructions. */ 525 I3508_LSLV = 0x1ac02000, 526 I3508_LSRV = 0x1ac02400, 527 I3508_ASRV = 0x1ac02800, 528 I3508_RORV = 0x1ac02c00, 529 I3508_SMULH = 0x9b407c00, 530 I3508_UMULH = 0x9bc07c00, 531 I3508_UDIV = 0x1ac00800, 532 I3508_SDIV = 0x1ac00c00, 533 534 /* Data-processing (3 source) instructions. */ 535 I3509_MADD = 0x1b000000, 536 I3509_MSUB = 0x1b008000, 537 538 /* Logical shifted register instructions (without a shift). */ 539 I3510_AND = 0x0a000000, 540 I3510_BIC = 0x0a200000, 541 I3510_ORR = 0x2a000000, 542 I3510_ORN = 0x2a200000, 543 I3510_EOR = 0x4a000000, 544 I3510_EON = 0x4a200000, 545 I3510_ANDS = 0x6a000000, 546 547 /* Logical shifted register instructions (with a shift). */ 548 I3502S_AND_LSR = I3510_AND | (1 << 22), 549 550 /* AdvSIMD copy */ 551 I3605_DUP = 0x0e000400, 552 I3605_INS = 0x4e001c00, 553 I3605_UMOV = 0x0e003c00, 554 555 /* AdvSIMD modified immediate */ 556 I3606_MOVI = 0x0f000400, 557 I3606_MVNI = 0x2f000400, 558 I3606_BIC = 0x2f001400, 559 I3606_ORR = 0x0f001400, 560 561 /* AdvSIMD scalar shift by immediate */ 562 I3609_SSHR = 0x5f000400, 563 I3609_SSRA = 0x5f001400, 564 I3609_SHL = 0x5f005400, 565 I3609_USHR = 0x7f000400, 566 I3609_USRA = 0x7f001400, 567 I3609_SLI = 0x7f005400, 568 569 /* AdvSIMD scalar three same */ 570 I3611_SQADD = 0x5e200c00, 571 I3611_SQSUB = 0x5e202c00, 572 I3611_CMGT = 0x5e203400, 573 I3611_CMGE = 0x5e203c00, 574 I3611_SSHL = 0x5e204400, 575 I3611_ADD = 0x5e208400, 576 I3611_CMTST = 0x5e208c00, 577 I3611_UQADD = 0x7e200c00, 578 I3611_UQSUB = 0x7e202c00, 579 I3611_CMHI = 0x7e203400, 580 I3611_CMHS = 0x7e203c00, 581 I3611_USHL = 0x7e204400, 582 I3611_SUB = 0x7e208400, 583 I3611_CMEQ = 0x7e208c00, 584 585 /* AdvSIMD scalar two-reg misc */ 586 I3612_CMGT0 = 0x5e208800, 587 I3612_CMEQ0 = 0x5e209800, 588 I3612_CMLT0 = 0x5e20a800, 589 I3612_ABS = 0x5e20b800, 590 I3612_CMGE0 = 0x7e208800, 591 I3612_CMLE0 = 0x7e209800, 592 I3612_NEG = 0x7e20b800, 593 594 /* AdvSIMD shift by immediate */ 595 I3614_SSHR = 0x0f000400, 596 I3614_SSRA = 0x0f001400, 597 I3614_SHL = 0x0f005400, 598 I3614_SLI = 0x2f005400, 599 I3614_USHR = 0x2f000400, 600 I3614_USRA = 0x2f001400, 601 602 /* AdvSIMD three same. */ 603 I3616_ADD = 0x0e208400, 604 I3616_AND = 0x0e201c00, 605 I3616_BIC = 0x0e601c00, 606 I3616_BIF = 0x2ee01c00, 607 I3616_BIT = 0x2ea01c00, 608 I3616_BSL = 0x2e601c00, 609 I3616_EOR = 0x2e201c00, 610 I3616_MUL = 0x0e209c00, 611 I3616_ORR = 0x0ea01c00, 612 I3616_ORN = 0x0ee01c00, 613 I3616_SUB = 0x2e208400, 614 I3616_CMGT = 0x0e203400, 615 I3616_CMGE = 0x0e203c00, 616 I3616_CMTST = 0x0e208c00, 617 I3616_CMHI = 0x2e203400, 618 I3616_CMHS = 0x2e203c00, 619 I3616_CMEQ = 0x2e208c00, 620 I3616_SMAX = 0x0e206400, 621 I3616_SMIN = 0x0e206c00, 622 I3616_SSHL = 0x0e204400, 623 I3616_SQADD = 0x0e200c00, 624 I3616_SQSUB = 0x0e202c00, 625 I3616_UMAX = 0x2e206400, 626 I3616_UMIN = 0x2e206c00, 627 I3616_UQADD = 0x2e200c00, 628 I3616_UQSUB = 0x2e202c00, 629 I3616_USHL = 0x2e204400, 630 631 /* AdvSIMD two-reg misc. */ 632 I3617_CMGT0 = 0x0e208800, 633 I3617_CMEQ0 = 0x0e209800, 634 I3617_CMLT0 = 0x0e20a800, 635 I3617_CMGE0 = 0x2e208800, 636 I3617_CMLE0 = 0x2e209800, 637 I3617_NOT = 0x2e205800, 638 I3617_ABS = 0x0e20b800, 639 I3617_NEG = 0x2e20b800, 640 641 /* System instructions. */ 642 NOP = 0xd503201f, 643 DMB_ISH = 0xd50338bf, 644 DMB_LD = 0x00000100, 645 DMB_ST = 0x00000200, 646 647 BTI_C = 0xd503245f, 648 BTI_J = 0xd503249f, 649 BTI_JC = 0xd50324df, 650} AArch64Insn; 651 652static inline uint32_t tcg_in32(TCGContext *s) 653{ 654 uint32_t v = *(uint32_t *)s->code_ptr; 655 return v; 656} 657 658/* Emit an opcode with "type-checking" of the format. */ 659#define tcg_out_insn(S, FMT, OP, ...) \ 660 glue(tcg_out_insn_,FMT)(S, glue(glue(glue(I,FMT),_),OP), ## __VA_ARGS__) 661 662static void tcg_out_insn_3303(TCGContext *s, AArch64Insn insn, bool q, 663 TCGReg rt, TCGReg rn, unsigned size) 664{ 665 tcg_out32(s, insn | (rt & 0x1f) | (rn << 5) | (size << 10) | (q << 30)); 666} 667 668static void tcg_out_insn_3305(TCGContext *s, AArch64Insn insn, 669 int imm19, TCGReg rt) 670{ 671 tcg_out32(s, insn | (imm19 & 0x7ffff) << 5 | rt); 672} 673 674static void tcg_out_insn_3306(TCGContext *s, AArch64Insn insn, TCGReg rs, 675 TCGReg rt, TCGReg rt2, TCGReg rn) 676{ 677 tcg_out32(s, insn | rs << 16 | rt2 << 10 | rn << 5 | rt); 678} 679 680static void tcg_out_insn_3201(TCGContext *s, AArch64Insn insn, TCGType ext, 681 TCGReg rt, int imm19) 682{ 683 tcg_out32(s, insn | ext << 31 | (imm19 & 0x7ffff) << 5 | rt); 684} 685 686static void tcg_out_insn_3202(TCGContext *s, AArch64Insn insn, 687 TCGCond c, int imm19) 688{ 689 tcg_out32(s, insn | tcg_cond_to_aarch64[c] | (imm19 & 0x7ffff) << 5); 690} 691 692static void tcg_out_insn_3205(TCGContext *s, AArch64Insn insn, 693 TCGReg rt, int imm6, int imm14) 694{ 695 insn |= (imm6 & 0x20) << (31 - 5); 696 insn |= (imm6 & 0x1f) << 19; 697 tcg_out32(s, insn | (imm14 & 0x3fff) << 5 | rt); 698} 699 700static void tcg_out_insn_3206(TCGContext *s, AArch64Insn insn, int imm26) 701{ 702 tcg_out32(s, insn | (imm26 & 0x03ffffff)); 703} 704 705static void tcg_out_insn_3207(TCGContext *s, AArch64Insn insn, TCGReg rn) 706{ 707 tcg_out32(s, insn | rn << 5); 708} 709 710static void tcg_out_insn_3314(TCGContext *s, AArch64Insn insn, 711 TCGReg r1, TCGReg r2, TCGReg rn, 712 tcg_target_long ofs, bool pre, bool w) 713{ 714 insn |= 1u << 31; /* ext */ 715 insn |= pre << 24; 716 insn |= w << 23; 717 718 tcg_debug_assert(ofs >= -0x200 && ofs < 0x200 && (ofs & 7) == 0); 719 insn |= (ofs & (0x7f << 3)) << (15 - 3); 720 721 tcg_out32(s, insn | r2 << 10 | rn << 5 | r1); 722} 723 724static void tcg_out_insn_3401(TCGContext *s, AArch64Insn insn, TCGType ext, 725 TCGReg rd, TCGReg rn, uint64_t aimm) 726{ 727 if (aimm > 0xfff) { 728 tcg_debug_assert((aimm & 0xfff) == 0); 729 aimm >>= 12; 730 tcg_debug_assert(aimm <= 0xfff); 731 aimm |= 1 << 12; /* apply LSL 12 */ 732 } 733 tcg_out32(s, insn | ext << 31 | aimm << 10 | rn << 5 | rd); 734} 735 736/* This function can be used for both 3.4.2 (Bitfield) and 3.4.4 737 (Logical immediate). Both insn groups have N, IMMR and IMMS fields 738 that feed the DecodeBitMasks pseudo function. */ 739static void tcg_out_insn_3402(TCGContext *s, AArch64Insn insn, TCGType ext, 740 TCGReg rd, TCGReg rn, int n, int immr, int imms) 741{ 742 tcg_out32(s, insn | ext << 31 | n << 22 | immr << 16 | imms << 10 743 | rn << 5 | rd); 744} 745 746#define tcg_out_insn_3404 tcg_out_insn_3402 747 748static void tcg_out_insn_3403(TCGContext *s, AArch64Insn insn, TCGType ext, 749 TCGReg rd, TCGReg rn, TCGReg rm, int imms) 750{ 751 tcg_out32(s, insn | ext << 31 | ext << 22 | rm << 16 | imms << 10 752 | rn << 5 | rd); 753} 754 755/* This function is used for the Move (wide immediate) instruction group. 756 Note that SHIFT is a full shift count, not the 2 bit HW field. */ 757static void tcg_out_insn_3405(TCGContext *s, AArch64Insn insn, TCGType ext, 758 TCGReg rd, uint16_t half, unsigned shift) 759{ 760 tcg_debug_assert((shift & ~0x30) == 0); 761 tcg_out32(s, insn | ext << 31 | shift << (21 - 4) | half << 5 | rd); 762} 763 764static void tcg_out_insn_3406(TCGContext *s, AArch64Insn insn, 765 TCGReg rd, int64_t disp) 766{ 767 tcg_out32(s, insn | (disp & 3) << 29 | (disp & 0x1ffffc) << (5 - 2) | rd); 768} 769 770static inline void tcg_out_insn_3501(TCGContext *s, AArch64Insn insn, 771 TCGType sf, TCGReg rd, TCGReg rn, 772 TCGReg rm, int opt, int imm3) 773{ 774 tcg_out32(s, insn | sf << 31 | rm << 16 | opt << 13 | 775 imm3 << 10 | rn << 5 | rd); 776} 777 778/* This function is for both 3.5.2 (Add/Subtract shifted register), for 779 the rare occasion when we actually want to supply a shift amount. */ 780static inline void tcg_out_insn_3502S(TCGContext *s, AArch64Insn insn, 781 TCGType ext, TCGReg rd, TCGReg rn, 782 TCGReg rm, int imm6) 783{ 784 tcg_out32(s, insn | ext << 31 | rm << 16 | imm6 << 10 | rn << 5 | rd); 785} 786 787/* This function is for 3.5.2 (Add/subtract shifted register), 788 and 3.5.10 (Logical shifted register), for the vast majorty of cases 789 when we don't want to apply a shift. Thus it can also be used for 790 3.5.3 (Add/subtract with carry) and 3.5.8 (Data processing 2 source). */ 791static void tcg_out_insn_3502(TCGContext *s, AArch64Insn insn, TCGType ext, 792 TCGReg rd, TCGReg rn, TCGReg rm) 793{ 794 tcg_out32(s, insn | ext << 31 | rm << 16 | rn << 5 | rd); 795} 796 797#define tcg_out_insn_3503 tcg_out_insn_3502 798#define tcg_out_insn_3508 tcg_out_insn_3502 799#define tcg_out_insn_3510 tcg_out_insn_3502 800 801static void tcg_out_insn_3506(TCGContext *s, AArch64Insn insn, TCGType ext, 802 TCGReg rd, TCGReg rn, TCGReg rm, TCGCond c) 803{ 804 tcg_out32(s, insn | ext << 31 | rm << 16 | rn << 5 | rd 805 | tcg_cond_to_aarch64[c] << 12); 806} 807 808static void tcg_out_insn_3507(TCGContext *s, AArch64Insn insn, TCGType ext, 809 TCGReg rd, TCGReg rn) 810{ 811 tcg_out32(s, insn | ext << 31 | rn << 5 | rd); 812} 813 814static void tcg_out_insn_3509(TCGContext *s, AArch64Insn insn, TCGType ext, 815 TCGReg rd, TCGReg rn, TCGReg rm, TCGReg ra) 816{ 817 tcg_out32(s, insn | ext << 31 | rm << 16 | ra << 10 | rn << 5 | rd); 818} 819 820static void tcg_out_insn_3605(TCGContext *s, AArch64Insn insn, bool q, 821 TCGReg rd, TCGReg rn, int dst_idx, int src_idx) 822{ 823 /* Note that bit 11 set means general register input. Therefore 824 we can handle both register sets with one function. */ 825 tcg_out32(s, insn | q << 30 | (dst_idx << 16) | (src_idx << 11) 826 | (rd & 0x1f) | (~rn & 0x20) << 6 | (rn & 0x1f) << 5); 827} 828 829static void tcg_out_insn_3606(TCGContext *s, AArch64Insn insn, bool q, 830 TCGReg rd, bool op, int cmode, uint8_t imm8) 831{ 832 tcg_out32(s, insn | q << 30 | op << 29 | cmode << 12 | (rd & 0x1f) 833 | (imm8 & 0xe0) << (16 - 5) | (imm8 & 0x1f) << 5); 834} 835 836static void tcg_out_insn_3609(TCGContext *s, AArch64Insn insn, 837 TCGReg rd, TCGReg rn, unsigned immhb) 838{ 839 tcg_out32(s, insn | immhb << 16 | (rn & 0x1f) << 5 | (rd & 0x1f)); 840} 841 842static void tcg_out_insn_3611(TCGContext *s, AArch64Insn insn, 843 unsigned size, TCGReg rd, TCGReg rn, TCGReg rm) 844{ 845 tcg_out32(s, insn | (size << 22) | (rm & 0x1f) << 16 846 | (rn & 0x1f) << 5 | (rd & 0x1f)); 847} 848 849static void tcg_out_insn_3612(TCGContext *s, AArch64Insn insn, 850 unsigned size, TCGReg rd, TCGReg rn) 851{ 852 tcg_out32(s, insn | (size << 22) | (rn & 0x1f) << 5 | (rd & 0x1f)); 853} 854 855static void tcg_out_insn_3614(TCGContext *s, AArch64Insn insn, bool q, 856 TCGReg rd, TCGReg rn, unsigned immhb) 857{ 858 tcg_out32(s, insn | q << 30 | immhb << 16 859 | (rn & 0x1f) << 5 | (rd & 0x1f)); 860} 861 862static void tcg_out_insn_3616(TCGContext *s, AArch64Insn insn, bool q, 863 unsigned size, TCGReg rd, TCGReg rn, TCGReg rm) 864{ 865 tcg_out32(s, insn | q << 30 | (size << 22) | (rm & 0x1f) << 16 866 | (rn & 0x1f) << 5 | (rd & 0x1f)); 867} 868 869static void tcg_out_insn_3617(TCGContext *s, AArch64Insn insn, bool q, 870 unsigned size, TCGReg rd, TCGReg rn) 871{ 872 tcg_out32(s, insn | q << 30 | (size << 22) 873 | (rn & 0x1f) << 5 | (rd & 0x1f)); 874} 875 876static void tcg_out_insn_3310(TCGContext *s, AArch64Insn insn, 877 TCGReg rd, TCGReg base, TCGType ext, 878 TCGReg regoff) 879{ 880 /* Note the AArch64Insn constants above are for C3.3.12. Adjust. */ 881 tcg_out32(s, insn | I3312_TO_I3310 | regoff << 16 | 882 0x4000 | ext << 13 | base << 5 | (rd & 0x1f)); 883} 884 885static void tcg_out_insn_3312(TCGContext *s, AArch64Insn insn, 886 TCGReg rd, TCGReg rn, intptr_t offset) 887{ 888 tcg_out32(s, insn | (offset & 0x1ff) << 12 | rn << 5 | (rd & 0x1f)); 889} 890 891static void tcg_out_insn_3313(TCGContext *s, AArch64Insn insn, 892 TCGReg rd, TCGReg rn, uintptr_t scaled_uimm) 893{ 894 /* Note the AArch64Insn constants above are for C3.3.12. Adjust. */ 895 tcg_out32(s, insn | I3312_TO_I3313 | scaled_uimm << 10 896 | rn << 5 | (rd & 0x1f)); 897} 898 899static void tcg_out_bti(TCGContext *s, AArch64Insn insn) 900{ 901 /* 902 * While BTI insns are nops on hosts without FEAT_BTI, 903 * there is no point in emitting them in that case either. 904 */ 905 if (cpuinfo & CPUINFO_BTI) { 906 tcg_out32(s, insn); 907 } 908} 909 910/* Register to register move using ORR (shifted register with no shift). */ 911static void tcg_out_movr(TCGContext *s, TCGType ext, TCGReg rd, TCGReg rm) 912{ 913 tcg_out_insn(s, 3510, ORR, ext, rd, TCG_REG_XZR, rm); 914} 915 916/* Register to register move using ADDI (move to/from SP). */ 917static void tcg_out_movr_sp(TCGContext *s, TCGType ext, TCGReg rd, TCGReg rn) 918{ 919 tcg_out_insn(s, 3401, ADDI, ext, rd, rn, 0); 920} 921 922/* This function is used for the Logical (immediate) instruction group. 923 The value of LIMM must satisfy IS_LIMM. See the comment above about 924 only supporting simplified logical immediates. */ 925static void tcg_out_logicali(TCGContext *s, AArch64Insn insn, TCGType ext, 926 TCGReg rd, TCGReg rn, uint64_t limm) 927{ 928 unsigned h, l, r, c; 929 930 tcg_debug_assert(is_limm(limm)); 931 932 h = clz64(limm); 933 l = ctz64(limm); 934 if (l == 0) { 935 r = 0; /* form 0....01....1 */ 936 c = ctz64(~limm) - 1; 937 if (h == 0) { 938 r = clz64(~limm); /* form 1..10..01..1 */ 939 c += r; 940 } 941 } else { 942 r = 64 - l; /* form 1....10....0 or 0..01..10..0 */ 943 c = r - h - 1; 944 } 945 if (ext == TCG_TYPE_I32) { 946 r &= 31; 947 c &= 31; 948 } 949 950 tcg_out_insn_3404(s, insn, ext, rd, rn, ext, r, c); 951} 952 953static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 954 TCGReg rd, int64_t v64) 955{ 956 bool q = type == TCG_TYPE_V128; 957 int cmode, imm8, i; 958 959 /* Test all bytes equal first. */ 960 if (vece == MO_8) { 961 imm8 = (uint8_t)v64; 962 tcg_out_insn(s, 3606, MOVI, q, rd, 0, 0xe, imm8); 963 return; 964 } 965 966 /* 967 * Test all bytes 0x00 or 0xff second. This can match cases that 968 * might otherwise take 2 or 3 insns for MO_16 or MO_32 below. 969 */ 970 for (i = imm8 = 0; i < 8; i++) { 971 uint8_t byte = v64 >> (i * 8); 972 if (byte == 0xff) { 973 imm8 |= 1 << i; 974 } else if (byte != 0) { 975 goto fail_bytes; 976 } 977 } 978 tcg_out_insn(s, 3606, MOVI, q, rd, 1, 0xe, imm8); 979 return; 980 fail_bytes: 981 982 /* 983 * Tests for various replications. For each element width, if we 984 * cannot find an expansion there's no point checking a larger 985 * width because we already know by replication it cannot match. 986 */ 987 if (vece == MO_16) { 988 uint16_t v16 = v64; 989 990 if (is_shimm16(v16, &cmode, &imm8)) { 991 tcg_out_insn(s, 3606, MOVI, q, rd, 0, cmode, imm8); 992 return; 993 } 994 if (is_shimm16(~v16, &cmode, &imm8)) { 995 tcg_out_insn(s, 3606, MVNI, q, rd, 0, cmode, imm8); 996 return; 997 } 998 999 /* 1000 * Otherwise, all remaining constants can be loaded in two insns: 1001 * rd = v16 & 0xff, rd |= v16 & 0xff00. 1002 */ 1003 tcg_out_insn(s, 3606, MOVI, q, rd, 0, 0x8, v16 & 0xff); 1004 tcg_out_insn(s, 3606, ORR, q, rd, 0, 0xa, v16 >> 8); 1005 return; 1006 } else if (vece == MO_32) { 1007 uint32_t v32 = v64; 1008 uint32_t n32 = ~v32; 1009 1010 if (is_shimm32(v32, &cmode, &imm8) || 1011 is_soimm32(v32, &cmode, &imm8) || 1012 is_fimm32(v32, &cmode, &imm8)) { 1013 tcg_out_insn(s, 3606, MOVI, q, rd, 0, cmode, imm8); 1014 return; 1015 } 1016 if (is_shimm32(n32, &cmode, &imm8) || 1017 is_soimm32(n32, &cmode, &imm8)) { 1018 tcg_out_insn(s, 3606, MVNI, q, rd, 0, cmode, imm8); 1019 return; 1020 } 1021 1022 /* 1023 * Restrict the set of constants to those we can load with 1024 * two instructions. Others we load from the pool. 1025 */ 1026 i = is_shimm32_pair(v32, &cmode, &imm8); 1027 if (i) { 1028 tcg_out_insn(s, 3606, MOVI, q, rd, 0, cmode, imm8); 1029 tcg_out_insn(s, 3606, ORR, q, rd, 0, i, extract32(v32, i * 4, 8)); 1030 return; 1031 } 1032 i = is_shimm32_pair(n32, &cmode, &imm8); 1033 if (i) { 1034 tcg_out_insn(s, 3606, MVNI, q, rd, 0, cmode, imm8); 1035 tcg_out_insn(s, 3606, BIC, q, rd, 0, i, extract32(n32, i * 4, 8)); 1036 return; 1037 } 1038 } else if (is_fimm64(v64, &cmode, &imm8)) { 1039 tcg_out_insn(s, 3606, MOVI, q, rd, 1, cmode, imm8); 1040 return; 1041 } 1042 1043 /* 1044 * As a last resort, load from the constant pool. Sadly there 1045 * is no LD1R (literal), so store the full 16-byte vector. 1046 */ 1047 if (type == TCG_TYPE_V128) { 1048 new_pool_l2(s, R_AARCH64_CONDBR19, s->code_ptr, 0, v64, v64); 1049 tcg_out_insn(s, 3305, LDR_v128, 0, rd); 1050 } else { 1051 new_pool_label(s, v64, R_AARCH64_CONDBR19, s->code_ptr, 0); 1052 tcg_out_insn(s, 3305, LDR_v64, 0, rd); 1053 } 1054} 1055 1056static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 1057 TCGReg rd, TCGReg rs) 1058{ 1059 int is_q = type - TCG_TYPE_V64; 1060 tcg_out_insn(s, 3605, DUP, is_q, rd, rs, 1 << vece, 0); 1061 return true; 1062} 1063 1064static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 1065 TCGReg r, TCGReg base, intptr_t offset) 1066{ 1067 TCGReg temp = TCG_REG_TMP0; 1068 1069 if (offset < -0xffffff || offset > 0xffffff) { 1070 tcg_out_movi(s, TCG_TYPE_PTR, temp, offset); 1071 tcg_out_insn(s, 3502, ADD, 1, temp, temp, base); 1072 base = temp; 1073 } else { 1074 AArch64Insn add_insn = I3401_ADDI; 1075 1076 if (offset < 0) { 1077 add_insn = I3401_SUBI; 1078 offset = -offset; 1079 } 1080 if (offset & 0xfff000) { 1081 tcg_out_insn_3401(s, add_insn, 1, temp, base, offset & 0xfff000); 1082 base = temp; 1083 } 1084 if (offset & 0xfff) { 1085 tcg_out_insn_3401(s, add_insn, 1, temp, base, offset & 0xfff); 1086 base = temp; 1087 } 1088 } 1089 tcg_out_insn(s, 3303, LD1R, type == TCG_TYPE_V128, r, base, vece); 1090 return true; 1091} 1092 1093static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, 1094 tcg_target_long value) 1095{ 1096 tcg_target_long svalue = value; 1097 tcg_target_long ivalue = ~value; 1098 tcg_target_long t0, t1, t2; 1099 int s0, s1; 1100 AArch64Insn opc; 1101 1102 switch (type) { 1103 case TCG_TYPE_I32: 1104 case TCG_TYPE_I64: 1105 tcg_debug_assert(rd < 32); 1106 break; 1107 default: 1108 g_assert_not_reached(); 1109 } 1110 1111 /* For 32-bit values, discard potential garbage in value. For 64-bit 1112 values within [2**31, 2**32-1], we can create smaller sequences by 1113 interpreting this as a negative 32-bit number, while ensuring that 1114 the high 32 bits are cleared by setting SF=0. */ 1115 if (type == TCG_TYPE_I32 || (value & ~0xffffffffull) == 0) { 1116 svalue = (int32_t)value; 1117 value = (uint32_t)value; 1118 ivalue = (uint32_t)ivalue; 1119 type = TCG_TYPE_I32; 1120 } 1121 1122 /* Speed things up by handling the common case of small positive 1123 and negative values specially. */ 1124 if ((value & ~0xffffull) == 0) { 1125 tcg_out_insn(s, 3405, MOVZ, type, rd, value, 0); 1126 return; 1127 } else if ((ivalue & ~0xffffull) == 0) { 1128 tcg_out_insn(s, 3405, MOVN, type, rd, ivalue, 0); 1129 return; 1130 } 1131 1132 /* Check for bitfield immediates. For the benefit of 32-bit quantities, 1133 use the sign-extended value. That lets us match rotated values such 1134 as 0xff0000ff with the same 64-bit logic matching 0xffffffffff0000ff. */ 1135 if (is_limm(svalue)) { 1136 tcg_out_logicali(s, I3404_ORRI, type, rd, TCG_REG_XZR, svalue); 1137 return; 1138 } 1139 1140 /* Look for host pointer values within 4G of the PC. This happens 1141 often when loading pointers to QEMU's own data structures. */ 1142 if (type == TCG_TYPE_I64) { 1143 intptr_t src_rx = (intptr_t)tcg_splitwx_to_rx(s->code_ptr); 1144 tcg_target_long disp = value - src_rx; 1145 if (disp == sextract64(disp, 0, 21)) { 1146 tcg_out_insn(s, 3406, ADR, rd, disp); 1147 return; 1148 } 1149 disp = (value >> 12) - (src_rx >> 12); 1150 if (disp == sextract64(disp, 0, 21)) { 1151 tcg_out_insn(s, 3406, ADRP, rd, disp); 1152 if (value & 0xfff) { 1153 tcg_out_insn(s, 3401, ADDI, type, rd, rd, value & 0xfff); 1154 } 1155 return; 1156 } 1157 } 1158 1159 /* Would it take fewer insns to begin with MOVN? */ 1160 if (ctpop64(value) >= 32) { 1161 t0 = ivalue; 1162 opc = I3405_MOVN; 1163 } else { 1164 t0 = value; 1165 opc = I3405_MOVZ; 1166 } 1167 s0 = ctz64(t0) & (63 & -16); 1168 t1 = t0 & ~(0xffffull << s0); 1169 s1 = ctz64(t1) & (63 & -16); 1170 t2 = t1 & ~(0xffffull << s1); 1171 if (t2 == 0) { 1172 tcg_out_insn_3405(s, opc, type, rd, t0 >> s0, s0); 1173 if (t1 != 0) { 1174 tcg_out_insn(s, 3405, MOVK, type, rd, value >> s1, s1); 1175 } 1176 return; 1177 } 1178 1179 /* For more than 2 insns, dump it into the constant pool. */ 1180 new_pool_label(s, value, R_AARCH64_CONDBR19, s->code_ptr, 0); 1181 tcg_out_insn(s, 3305, LDR, 0, rd); 1182} 1183 1184static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 1185{ 1186 return false; 1187} 1188 1189static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 1190 tcg_target_long imm) 1191{ 1192 /* This function is only used for passing structs by reference. */ 1193 g_assert_not_reached(); 1194} 1195 1196/* Define something more legible for general use. */ 1197#define tcg_out_ldst_r tcg_out_insn_3310 1198 1199static void tcg_out_ldst(TCGContext *s, AArch64Insn insn, TCGReg rd, 1200 TCGReg rn, intptr_t offset, int lgsize) 1201{ 1202 /* If the offset is naturally aligned and in range, then we can 1203 use the scaled uimm12 encoding */ 1204 if (offset >= 0 && !(offset & ((1 << lgsize) - 1))) { 1205 uintptr_t scaled_uimm = offset >> lgsize; 1206 if (scaled_uimm <= 0xfff) { 1207 tcg_out_insn_3313(s, insn, rd, rn, scaled_uimm); 1208 return; 1209 } 1210 } 1211 1212 /* Small signed offsets can use the unscaled encoding. */ 1213 if (offset >= -256 && offset < 256) { 1214 tcg_out_insn_3312(s, insn, rd, rn, offset); 1215 return; 1216 } 1217 1218 /* Worst-case scenario, move offset to temp register, use reg offset. */ 1219 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP0, offset); 1220 tcg_out_ldst_r(s, insn, rd, rn, TCG_TYPE_I64, TCG_REG_TMP0); 1221} 1222 1223static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 1224{ 1225 if (ret == arg) { 1226 return true; 1227 } 1228 switch (type) { 1229 case TCG_TYPE_I32: 1230 case TCG_TYPE_I64: 1231 if (ret < 32 && arg < 32) { 1232 tcg_out_movr(s, type, ret, arg); 1233 break; 1234 } else if (ret < 32) { 1235 tcg_out_insn(s, 3605, UMOV, type, ret, arg, 0, 0); 1236 break; 1237 } else if (arg < 32) { 1238 tcg_out_insn(s, 3605, INS, 0, ret, arg, 4 << type, 0); 1239 break; 1240 } 1241 /* FALLTHRU */ 1242 1243 case TCG_TYPE_V64: 1244 tcg_debug_assert(ret >= 32 && arg >= 32); 1245 tcg_out_insn(s, 3616, ORR, 0, 0, ret, arg, arg); 1246 break; 1247 case TCG_TYPE_V128: 1248 tcg_debug_assert(ret >= 32 && arg >= 32); 1249 tcg_out_insn(s, 3616, ORR, 1, 0, ret, arg, arg); 1250 break; 1251 1252 default: 1253 g_assert_not_reached(); 1254 } 1255 return true; 1256} 1257 1258static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, 1259 TCGReg base, intptr_t ofs) 1260{ 1261 AArch64Insn insn; 1262 int lgsz; 1263 1264 switch (type) { 1265 case TCG_TYPE_I32: 1266 insn = (ret < 32 ? I3312_LDRW : I3312_LDRVS); 1267 lgsz = 2; 1268 break; 1269 case TCG_TYPE_I64: 1270 insn = (ret < 32 ? I3312_LDRX : I3312_LDRVD); 1271 lgsz = 3; 1272 break; 1273 case TCG_TYPE_V64: 1274 insn = I3312_LDRVD; 1275 lgsz = 3; 1276 break; 1277 case TCG_TYPE_V128: 1278 insn = I3312_LDRVQ; 1279 lgsz = 4; 1280 break; 1281 default: 1282 g_assert_not_reached(); 1283 } 1284 tcg_out_ldst(s, insn, ret, base, ofs, lgsz); 1285} 1286 1287static void tcg_out_st(TCGContext *s, TCGType type, TCGReg src, 1288 TCGReg base, intptr_t ofs) 1289{ 1290 AArch64Insn insn; 1291 int lgsz; 1292 1293 switch (type) { 1294 case TCG_TYPE_I32: 1295 insn = (src < 32 ? I3312_STRW : I3312_STRVS); 1296 lgsz = 2; 1297 break; 1298 case TCG_TYPE_I64: 1299 insn = (src < 32 ? I3312_STRX : I3312_STRVD); 1300 lgsz = 3; 1301 break; 1302 case TCG_TYPE_V64: 1303 insn = I3312_STRVD; 1304 lgsz = 3; 1305 break; 1306 case TCG_TYPE_V128: 1307 insn = I3312_STRVQ; 1308 lgsz = 4; 1309 break; 1310 default: 1311 g_assert_not_reached(); 1312 } 1313 tcg_out_ldst(s, insn, src, base, ofs, lgsz); 1314} 1315 1316static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 1317 TCGReg base, intptr_t ofs) 1318{ 1319 if (type <= TCG_TYPE_I64 && val == 0) { 1320 tcg_out_st(s, type, TCG_REG_XZR, base, ofs); 1321 return true; 1322 } 1323 return false; 1324} 1325 1326static inline void tcg_out_bfm(TCGContext *s, TCGType ext, TCGReg rd, 1327 TCGReg rn, unsigned int a, unsigned int b) 1328{ 1329 tcg_out_insn(s, 3402, BFM, ext, rd, rn, ext, a, b); 1330} 1331 1332static inline void tcg_out_ubfm(TCGContext *s, TCGType ext, TCGReg rd, 1333 TCGReg rn, unsigned int a, unsigned int b) 1334{ 1335 tcg_out_insn(s, 3402, UBFM, ext, rd, rn, ext, a, b); 1336} 1337 1338static inline void tcg_out_sbfm(TCGContext *s, TCGType ext, TCGReg rd, 1339 TCGReg rn, unsigned int a, unsigned int b) 1340{ 1341 tcg_out_insn(s, 3402, SBFM, ext, rd, rn, ext, a, b); 1342} 1343 1344static inline void tcg_out_extr(TCGContext *s, TCGType ext, TCGReg rd, 1345 TCGReg rn, TCGReg rm, unsigned int a) 1346{ 1347 tcg_out_insn(s, 3403, EXTR, ext, rd, rn, rm, a); 1348} 1349 1350static inline void tcg_out_sar(TCGContext *s, TCGType ext, 1351 TCGReg rd, TCGReg rn, unsigned int m) 1352{ 1353 int max = ext ? 63 : 31; 1354 tcg_out_sbfm(s, ext, rd, rn, m & max, max); 1355} 1356 1357static inline void tcg_out_rotr(TCGContext *s, TCGType ext, 1358 TCGReg rd, TCGReg rn, unsigned int m) 1359{ 1360 int max = ext ? 63 : 31; 1361 tcg_out_extr(s, ext, rd, rn, rn, m & max); 1362} 1363 1364static inline void tcg_out_rotl(TCGContext *s, TCGType ext, 1365 TCGReg rd, TCGReg rn, unsigned int m) 1366{ 1367 int max = ext ? 63 : 31; 1368 tcg_out_extr(s, ext, rd, rn, rn, -m & max); 1369} 1370 1371static inline void tcg_out_dep(TCGContext *s, TCGType ext, TCGReg rd, 1372 TCGReg rn, unsigned lsb, unsigned width) 1373{ 1374 unsigned size = ext ? 64 : 32; 1375 unsigned a = (size - lsb) & (size - 1); 1376 unsigned b = width - 1; 1377 tcg_out_bfm(s, ext, rd, rn, a, b); 1378} 1379 1380static void tcg_out_cmp(TCGContext *s, TCGType ext, TCGCond cond, TCGReg a, 1381 tcg_target_long b, bool const_b) 1382{ 1383 if (is_tst_cond(cond)) { 1384 if (!const_b) { 1385 tcg_out_insn(s, 3510, ANDS, ext, TCG_REG_XZR, a, b); 1386 } else { 1387 tcg_out_logicali(s, I3404_ANDSI, ext, TCG_REG_XZR, a, b); 1388 } 1389 } else { 1390 if (!const_b) { 1391 tcg_out_insn(s, 3502, SUBS, ext, TCG_REG_XZR, a, b); 1392 } else if (b >= 0) { 1393 tcg_debug_assert(is_aimm(b)); 1394 tcg_out_insn(s, 3401, SUBSI, ext, TCG_REG_XZR, a, b); 1395 } else { 1396 tcg_debug_assert(is_aimm(-b)); 1397 tcg_out_insn(s, 3401, ADDSI, ext, TCG_REG_XZR, a, -b); 1398 } 1399 } 1400} 1401 1402static void tcg_out_goto(TCGContext *s, const tcg_insn_unit *target) 1403{ 1404 ptrdiff_t offset = tcg_pcrel_diff(s, target) >> 2; 1405 tcg_debug_assert(offset == sextract64(offset, 0, 26)); 1406 tcg_out_insn(s, 3206, B, offset); 1407} 1408 1409static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *target) 1410{ 1411 ptrdiff_t offset = tcg_pcrel_diff(s, target) >> 2; 1412 if (offset == sextract64(offset, 0, 26)) { 1413 tcg_out_insn(s, 3206, BL, offset); 1414 } else { 1415 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP0, (intptr_t)target); 1416 tcg_out_insn(s, 3207, BLR, TCG_REG_TMP0); 1417 } 1418} 1419 1420static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target, 1421 const TCGHelperInfo *info) 1422{ 1423 tcg_out_call_int(s, target); 1424} 1425 1426static inline void tcg_out_goto_label(TCGContext *s, TCGLabel *l) 1427{ 1428 if (!l->has_value) { 1429 tcg_out_reloc(s, s->code_ptr, R_AARCH64_JUMP26, l, 0); 1430 tcg_out_insn(s, 3206, B, 0); 1431 } else { 1432 tcg_out_goto(s, l->u.value_ptr); 1433 } 1434} 1435 1436static void tcg_out_brcond(TCGContext *s, TCGType ext, TCGCond c, TCGArg a, 1437 TCGArg b, bool b_const, TCGLabel *l) 1438{ 1439 int tbit = -1; 1440 bool need_cmp = true; 1441 1442 switch (c) { 1443 case TCG_COND_EQ: 1444 case TCG_COND_NE: 1445 /* cmp xN,0; b.ne L -> cbnz xN,L */ 1446 if (b_const && b == 0) { 1447 need_cmp = false; 1448 } 1449 break; 1450 case TCG_COND_LT: 1451 case TCG_COND_GE: 1452 /* cmp xN,0; b.mi L -> tbnz xN,63,L */ 1453 if (b_const && b == 0) { 1454 c = (c == TCG_COND_LT ? TCG_COND_TSTNE : TCG_COND_TSTEQ); 1455 tbit = ext ? 63 : 31; 1456 need_cmp = false; 1457 } 1458 break; 1459 case TCG_COND_TSTEQ: 1460 case TCG_COND_TSTNE: 1461 /* tst xN,0xffffffff; b.ne L -> cbnz wN,L */ 1462 if (b_const && b == UINT32_MAX) { 1463 c = tcg_tst_eqne_cond(c); 1464 ext = TCG_TYPE_I32; 1465 need_cmp = false; 1466 break; 1467 } 1468 /* tst xN,1<<B; b.ne L -> tbnz xN,B,L */ 1469 if (b_const && is_power_of_2(b)) { 1470 tbit = ctz64(b); 1471 need_cmp = false; 1472 } 1473 break; 1474 default: 1475 break; 1476 } 1477 1478 if (need_cmp) { 1479 tcg_out_cmp(s, ext, c, a, b, b_const); 1480 tcg_out_reloc(s, s->code_ptr, R_AARCH64_CONDBR19, l, 0); 1481 tcg_out_insn(s, 3202, B_C, c, 0); 1482 return; 1483 } 1484 1485 if (tbit >= 0) { 1486 tcg_out_reloc(s, s->code_ptr, R_AARCH64_TSTBR14, l, 0); 1487 switch (c) { 1488 case TCG_COND_TSTEQ: 1489 tcg_out_insn(s, 3205, TBZ, a, tbit, 0); 1490 break; 1491 case TCG_COND_TSTNE: 1492 tcg_out_insn(s, 3205, TBNZ, a, tbit, 0); 1493 break; 1494 default: 1495 g_assert_not_reached(); 1496 } 1497 } else { 1498 tcg_out_reloc(s, s->code_ptr, R_AARCH64_CONDBR19, l, 0); 1499 switch (c) { 1500 case TCG_COND_EQ: 1501 tcg_out_insn(s, 3201, CBZ, ext, a, 0); 1502 break; 1503 case TCG_COND_NE: 1504 tcg_out_insn(s, 3201, CBNZ, ext, a, 0); 1505 break; 1506 default: 1507 g_assert_not_reached(); 1508 } 1509 } 1510} 1511 1512static inline void tcg_out_rev(TCGContext *s, int ext, MemOp s_bits, 1513 TCGReg rd, TCGReg rn) 1514{ 1515 /* REV, REV16, REV32 */ 1516 tcg_out_insn_3507(s, I3507_REV | (s_bits << 10), ext, rd, rn); 1517} 1518 1519static inline void tcg_out_sxt(TCGContext *s, TCGType ext, MemOp s_bits, 1520 TCGReg rd, TCGReg rn) 1521{ 1522 /* Using ALIASes SXTB, SXTH, SXTW, of SBFM Xd, Xn, #0, #7|15|31 */ 1523 int bits = (8 << s_bits) - 1; 1524 tcg_out_sbfm(s, ext, rd, rn, 0, bits); 1525} 1526 1527static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rn) 1528{ 1529 tcg_out_sxt(s, type, MO_8, rd, rn); 1530} 1531 1532static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rn) 1533{ 1534 tcg_out_sxt(s, type, MO_16, rd, rn); 1535} 1536 1537static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rn) 1538{ 1539 tcg_out_sxt(s, TCG_TYPE_I64, MO_32, rd, rn); 1540} 1541 1542static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rn) 1543{ 1544 tcg_out_ext32s(s, rd, rn); 1545} 1546 1547static inline void tcg_out_uxt(TCGContext *s, MemOp s_bits, 1548 TCGReg rd, TCGReg rn) 1549{ 1550 /* Using ALIASes UXTB, UXTH of UBFM Wd, Wn, #0, #7|15 */ 1551 int bits = (8 << s_bits) - 1; 1552 tcg_out_ubfm(s, 0, rd, rn, 0, bits); 1553} 1554 1555static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rn) 1556{ 1557 tcg_out_uxt(s, MO_8, rd, rn); 1558} 1559 1560static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rn) 1561{ 1562 tcg_out_uxt(s, MO_16, rd, rn); 1563} 1564 1565static void tcg_out_ext32u(TCGContext *s, TCGReg rd, TCGReg rn) 1566{ 1567 tcg_out_movr(s, TCG_TYPE_I32, rd, rn); 1568} 1569 1570static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rn) 1571{ 1572 tcg_out_ext32u(s, rd, rn); 1573} 1574 1575static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rn) 1576{ 1577 tcg_out_mov(s, TCG_TYPE_I32, rd, rn); 1578} 1579 1580static void tcg_out_addsub2(TCGContext *s, TCGType ext, TCGReg rl, 1581 TCGReg rh, TCGReg al, TCGReg ah, 1582 tcg_target_long bl, tcg_target_long bh, 1583 bool const_bl, bool const_bh, bool sub) 1584{ 1585 TCGReg orig_rl = rl; 1586 AArch64Insn insn; 1587 1588 if (rl == ah || (!const_bh && rl == bh)) { 1589 rl = TCG_REG_TMP0; 1590 } 1591 1592 if (const_bl) { 1593 if (bl < 0) { 1594 bl = -bl; 1595 insn = sub ? I3401_ADDSI : I3401_SUBSI; 1596 } else { 1597 insn = sub ? I3401_SUBSI : I3401_ADDSI; 1598 } 1599 1600 if (unlikely(al == TCG_REG_XZR)) { 1601 /* ??? We want to allow al to be zero for the benefit of 1602 negation via subtraction. However, that leaves open the 1603 possibility of adding 0+const in the low part, and the 1604 immediate add instructions encode XSP not XZR. Don't try 1605 anything more elaborate here than loading another zero. */ 1606 al = TCG_REG_TMP0; 1607 tcg_out_movi(s, ext, al, 0); 1608 } 1609 tcg_out_insn_3401(s, insn, ext, rl, al, bl); 1610 } else { 1611 tcg_out_insn_3502(s, sub ? I3502_SUBS : I3502_ADDS, ext, rl, al, bl); 1612 } 1613 1614 insn = I3503_ADC; 1615 if (const_bh) { 1616 /* Note that the only two constants we support are 0 and -1, and 1617 that SBC = rn + ~rm + c, so adc -1 is sbc 0, and vice-versa. */ 1618 if ((bh != 0) ^ sub) { 1619 insn = I3503_SBC; 1620 } 1621 bh = TCG_REG_XZR; 1622 } else if (sub) { 1623 insn = I3503_SBC; 1624 } 1625 tcg_out_insn_3503(s, insn, ext, rh, ah, bh); 1626 1627 tcg_out_mov(s, ext, orig_rl, rl); 1628} 1629 1630static inline void tcg_out_mb(TCGContext *s, TCGArg a0) 1631{ 1632 static const uint32_t sync[] = { 1633 [0 ... TCG_MO_ALL] = DMB_ISH | DMB_LD | DMB_ST, 1634 [TCG_MO_ST_ST] = DMB_ISH | DMB_ST, 1635 [TCG_MO_LD_LD] = DMB_ISH | DMB_LD, 1636 [TCG_MO_LD_ST] = DMB_ISH | DMB_LD, 1637 [TCG_MO_LD_ST | TCG_MO_LD_LD] = DMB_ISH | DMB_LD, 1638 }; 1639 tcg_out32(s, sync[a0 & TCG_MO_ALL]); 1640} 1641 1642static void tcg_out_cltz(TCGContext *s, TCGType ext, TCGReg d, 1643 TCGReg a0, TCGArg b, bool const_b, bool is_ctz) 1644{ 1645 TCGReg a1 = a0; 1646 if (is_ctz) { 1647 a1 = TCG_REG_TMP0; 1648 tcg_out_insn(s, 3507, RBIT, ext, a1, a0); 1649 } 1650 if (const_b && b == (ext ? 64 : 32)) { 1651 tcg_out_insn(s, 3507, CLZ, ext, d, a1); 1652 } else { 1653 AArch64Insn sel = I3506_CSEL; 1654 1655 tcg_out_cmp(s, ext, TCG_COND_NE, a0, 0, 1); 1656 tcg_out_insn(s, 3507, CLZ, ext, TCG_REG_TMP0, a1); 1657 1658 if (const_b) { 1659 if (b == -1) { 1660 b = TCG_REG_XZR; 1661 sel = I3506_CSINV; 1662 } else if (b == 0) { 1663 b = TCG_REG_XZR; 1664 } else { 1665 tcg_out_movi(s, ext, d, b); 1666 b = d; 1667 } 1668 } 1669 tcg_out_insn_3506(s, sel, ext, d, TCG_REG_TMP0, b, TCG_COND_NE); 1670 } 1671} 1672 1673typedef struct { 1674 TCGReg base; 1675 TCGReg index; 1676 TCGType index_ext; 1677 TCGAtomAlign aa; 1678} HostAddress; 1679 1680bool tcg_target_has_memory_bswap(MemOp memop) 1681{ 1682 return false; 1683} 1684 1685static const TCGLdstHelperParam ldst_helper_param = { 1686 .ntmp = 1, .tmp = { TCG_REG_TMP0 } 1687}; 1688 1689static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1690{ 1691 MemOp opc = get_memop(lb->oi); 1692 1693 if (!reloc_pc19(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1694 return false; 1695 } 1696 1697 tcg_out_ld_helper_args(s, lb, &ldst_helper_param); 1698 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE]); 1699 tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param); 1700 tcg_out_goto(s, lb->raddr); 1701 return true; 1702} 1703 1704static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1705{ 1706 MemOp opc = get_memop(lb->oi); 1707 1708 if (!reloc_pc19(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1709 return false; 1710 } 1711 1712 tcg_out_st_helper_args(s, lb, &ldst_helper_param); 1713 tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE]); 1714 tcg_out_goto(s, lb->raddr); 1715 return true; 1716} 1717 1718/* We expect to use a 7-bit scaled negative offset from ENV. */ 1719#define MIN_TLB_MASK_TABLE_OFS -512 1720 1721/* 1722 * For system-mode, perform the TLB load and compare. 1723 * For user-mode, perform any required alignment tests. 1724 * In both cases, return a TCGLabelQemuLdst structure if the slow path 1725 * is required and fill in @h with the host address for the fast path. 1726 */ 1727static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1728 TCGReg addr_reg, MemOpIdx oi, 1729 bool is_ld) 1730{ 1731 TCGType addr_type = s->addr_type; 1732 TCGLabelQemuLdst *ldst = NULL; 1733 MemOp opc = get_memop(oi); 1734 MemOp s_bits = opc & MO_SIZE; 1735 unsigned a_mask; 1736 1737 h->aa = atom_and_align_for_opc(s, opc, 1738 have_lse2 ? MO_ATOM_WITHIN16 1739 : MO_ATOM_IFALIGN, 1740 s_bits == MO_128); 1741 a_mask = (1 << h->aa.align) - 1; 1742 1743 if (tcg_use_softmmu) { 1744 unsigned s_mask = (1u << s_bits) - 1; 1745 unsigned mem_index = get_mmuidx(oi); 1746 TCGReg addr_adj; 1747 TCGType mask_type; 1748 uint64_t compare_mask; 1749 1750 ldst = new_ldst_label(s); 1751 ldst->is_ld = is_ld; 1752 ldst->oi = oi; 1753 ldst->addr_reg = addr_reg; 1754 1755 mask_type = (s->page_bits + s->tlb_dyn_max_bits > 32 1756 ? TCG_TYPE_I64 : TCG_TYPE_I32); 1757 1758 /* Load cpu->neg.tlb.f[mmu_idx].{mask,table} into {tmp0,tmp1}. */ 1759 QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0); 1760 QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != 8); 1761 tcg_out_insn(s, 3314, LDP, TCG_REG_TMP0, TCG_REG_TMP1, TCG_AREG0, 1762 tlb_mask_table_ofs(s, mem_index), 1, 0); 1763 1764 /* Extract the TLB index from the address into X0. */ 1765 tcg_out_insn(s, 3502S, AND_LSR, mask_type == TCG_TYPE_I64, 1766 TCG_REG_TMP0, TCG_REG_TMP0, addr_reg, 1767 s->page_bits - CPU_TLB_ENTRY_BITS); 1768 1769 /* Add the tlb_table pointer, forming the CPUTLBEntry address. */ 1770 tcg_out_insn(s, 3502, ADD, 1, TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_TMP0); 1771 1772 /* Load the tlb comparator into TMP0, and the fast path addend. */ 1773 QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN); 1774 tcg_out_ld(s, addr_type, TCG_REG_TMP0, TCG_REG_TMP1, 1775 is_ld ? offsetof(CPUTLBEntry, addr_read) 1776 : offsetof(CPUTLBEntry, addr_write)); 1777 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, 1778 offsetof(CPUTLBEntry, addend)); 1779 1780 /* 1781 * For aligned accesses, we check the first byte and include 1782 * the alignment bits within the address. For unaligned access, 1783 * we check that we don't cross pages using the address of the 1784 * last byte of the access. 1785 */ 1786 if (a_mask >= s_mask) { 1787 addr_adj = addr_reg; 1788 } else { 1789 addr_adj = TCG_REG_TMP2; 1790 tcg_out_insn(s, 3401, ADDI, addr_type, 1791 addr_adj, addr_reg, s_mask - a_mask); 1792 } 1793 compare_mask = (uint64_t)s->page_mask | a_mask; 1794 1795 /* Store the page mask part of the address into TMP2. */ 1796 tcg_out_logicali(s, I3404_ANDI, addr_type, TCG_REG_TMP2, 1797 addr_adj, compare_mask); 1798 1799 /* Perform the address comparison. */ 1800 tcg_out_cmp(s, addr_type, TCG_COND_NE, TCG_REG_TMP0, TCG_REG_TMP2, 0); 1801 1802 /* If not equal, we jump to the slow path. */ 1803 ldst->label_ptr[0] = s->code_ptr; 1804 tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0); 1805 1806 h->base = TCG_REG_TMP1; 1807 h->index = addr_reg; 1808 h->index_ext = addr_type; 1809 } else { 1810 if (a_mask) { 1811 ldst = new_ldst_label(s); 1812 1813 ldst->is_ld = is_ld; 1814 ldst->oi = oi; 1815 ldst->addr_reg = addr_reg; 1816 1817 /* tst addr, #mask */ 1818 tcg_out_logicali(s, I3404_ANDSI, 0, TCG_REG_XZR, addr_reg, a_mask); 1819 1820 /* b.ne slow_path */ 1821 ldst->label_ptr[0] = s->code_ptr; 1822 tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0); 1823 } 1824 1825 if (guest_base || addr_type == TCG_TYPE_I32) { 1826 h->base = TCG_REG_GUEST_BASE; 1827 h->index = addr_reg; 1828 h->index_ext = addr_type; 1829 } else { 1830 h->base = addr_reg; 1831 h->index = TCG_REG_XZR; 1832 h->index_ext = TCG_TYPE_I64; 1833 } 1834 } 1835 1836 return ldst; 1837} 1838 1839static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext, 1840 TCGReg data_r, HostAddress h) 1841{ 1842 switch (memop & MO_SSIZE) { 1843 case MO_UB: 1844 tcg_out_ldst_r(s, I3312_LDRB, data_r, h.base, h.index_ext, h.index); 1845 break; 1846 case MO_SB: 1847 tcg_out_ldst_r(s, ext ? I3312_LDRSBX : I3312_LDRSBW, 1848 data_r, h.base, h.index_ext, h.index); 1849 break; 1850 case MO_UW: 1851 tcg_out_ldst_r(s, I3312_LDRH, data_r, h.base, h.index_ext, h.index); 1852 break; 1853 case MO_SW: 1854 tcg_out_ldst_r(s, (ext ? I3312_LDRSHX : I3312_LDRSHW), 1855 data_r, h.base, h.index_ext, h.index); 1856 break; 1857 case MO_UL: 1858 tcg_out_ldst_r(s, I3312_LDRW, data_r, h.base, h.index_ext, h.index); 1859 break; 1860 case MO_SL: 1861 tcg_out_ldst_r(s, I3312_LDRSWX, data_r, h.base, h.index_ext, h.index); 1862 break; 1863 case MO_UQ: 1864 tcg_out_ldst_r(s, I3312_LDRX, data_r, h.base, h.index_ext, h.index); 1865 break; 1866 default: 1867 g_assert_not_reached(); 1868 } 1869} 1870 1871static void tcg_out_qemu_st_direct(TCGContext *s, MemOp memop, 1872 TCGReg data_r, HostAddress h) 1873{ 1874 switch (memop & MO_SIZE) { 1875 case MO_8: 1876 tcg_out_ldst_r(s, I3312_STRB, data_r, h.base, h.index_ext, h.index); 1877 break; 1878 case MO_16: 1879 tcg_out_ldst_r(s, I3312_STRH, data_r, h.base, h.index_ext, h.index); 1880 break; 1881 case MO_32: 1882 tcg_out_ldst_r(s, I3312_STRW, data_r, h.base, h.index_ext, h.index); 1883 break; 1884 case MO_64: 1885 tcg_out_ldst_r(s, I3312_STRX, data_r, h.base, h.index_ext, h.index); 1886 break; 1887 default: 1888 g_assert_not_reached(); 1889 } 1890} 1891 1892static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, 1893 MemOpIdx oi, TCGType data_type) 1894{ 1895 TCGLabelQemuLdst *ldst; 1896 HostAddress h; 1897 1898 ldst = prepare_host_addr(s, &h, addr_reg, oi, true); 1899 tcg_out_qemu_ld_direct(s, get_memop(oi), data_type, data_reg, h); 1900 1901 if (ldst) { 1902 ldst->type = data_type; 1903 ldst->datalo_reg = data_reg; 1904 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1905 } 1906} 1907 1908static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, 1909 MemOpIdx oi, TCGType data_type) 1910{ 1911 TCGLabelQemuLdst *ldst; 1912 HostAddress h; 1913 1914 ldst = prepare_host_addr(s, &h, addr_reg, oi, false); 1915 tcg_out_qemu_st_direct(s, get_memop(oi), data_reg, h); 1916 1917 if (ldst) { 1918 ldst->type = data_type; 1919 ldst->datalo_reg = data_reg; 1920 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1921 } 1922} 1923 1924static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg datalo, TCGReg datahi, 1925 TCGReg addr_reg, MemOpIdx oi, bool is_ld) 1926{ 1927 TCGLabelQemuLdst *ldst; 1928 HostAddress h; 1929 TCGReg base; 1930 bool use_pair; 1931 1932 ldst = prepare_host_addr(s, &h, addr_reg, oi, is_ld); 1933 1934 /* Compose the final address, as LDP/STP have no indexing. */ 1935 if (h.index == TCG_REG_XZR) { 1936 base = h.base; 1937 } else { 1938 base = TCG_REG_TMP2; 1939 if (h.index_ext == TCG_TYPE_I32) { 1940 /* add base, base, index, uxtw */ 1941 tcg_out_insn(s, 3501, ADD, TCG_TYPE_I64, base, 1942 h.base, h.index, MO_32, 0); 1943 } else { 1944 /* add base, base, index */ 1945 tcg_out_insn(s, 3502, ADD, 1, base, h.base, h.index); 1946 } 1947 } 1948 1949 use_pair = h.aa.atom < MO_128 || have_lse2; 1950 1951 if (!use_pair) { 1952 tcg_insn_unit *branch = NULL; 1953 TCGReg ll, lh, sl, sh; 1954 1955 /* 1956 * If we have already checked for 16-byte alignment, that's all 1957 * we need. Otherwise we have determined that misaligned atomicity 1958 * may be handled with two 8-byte loads. 1959 */ 1960 if (h.aa.align < MO_128) { 1961 /* 1962 * TODO: align should be MO_64, so we only need test bit 3, 1963 * which means we could use TBNZ instead of ANDS+B_C. 1964 */ 1965 tcg_out_logicali(s, I3404_ANDSI, 0, TCG_REG_XZR, addr_reg, 15); 1966 branch = s->code_ptr; 1967 tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0); 1968 use_pair = true; 1969 } 1970 1971 if (is_ld) { 1972 /* 1973 * 16-byte atomicity without LSE2 requires LDXP+STXP loop: 1974 * ldxp lo, hi, [base] 1975 * stxp t0, lo, hi, [base] 1976 * cbnz t0, .-8 1977 * Require no overlap between data{lo,hi} and base. 1978 */ 1979 if (datalo == base || datahi == base) { 1980 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_TMP2, base); 1981 base = TCG_REG_TMP2; 1982 } 1983 ll = sl = datalo; 1984 lh = sh = datahi; 1985 } else { 1986 /* 1987 * 16-byte atomicity without LSE2 requires LDXP+STXP loop: 1988 * 1: ldxp t0, t1, [base] 1989 * stxp t0, lo, hi, [base] 1990 * cbnz t0, 1b 1991 */ 1992 tcg_debug_assert(base != TCG_REG_TMP0 && base != TCG_REG_TMP1); 1993 ll = TCG_REG_TMP0; 1994 lh = TCG_REG_TMP1; 1995 sl = datalo; 1996 sh = datahi; 1997 } 1998 1999 tcg_out_insn(s, 3306, LDXP, TCG_REG_XZR, ll, lh, base); 2000 tcg_out_insn(s, 3306, STXP, TCG_REG_TMP0, sl, sh, base); 2001 tcg_out_insn(s, 3201, CBNZ, 0, TCG_REG_TMP0, -2); 2002 2003 if (use_pair) { 2004 /* "b .+8", branching across the one insn of use_pair. */ 2005 tcg_out_insn(s, 3206, B, 2); 2006 reloc_pc19(branch, tcg_splitwx_to_rx(s->code_ptr)); 2007 } 2008 } 2009 2010 if (use_pair) { 2011 if (is_ld) { 2012 tcg_out_insn(s, 3314, LDP, datalo, datahi, base, 0, 1, 0); 2013 } else { 2014 tcg_out_insn(s, 3314, STP, datalo, datahi, base, 0, 1, 0); 2015 } 2016 } 2017 2018 if (ldst) { 2019 ldst->type = TCG_TYPE_I128; 2020 ldst->datalo_reg = datalo; 2021 ldst->datahi_reg = datahi; 2022 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 2023 } 2024} 2025 2026static const tcg_insn_unit *tb_ret_addr; 2027 2028static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 2029{ 2030 const tcg_insn_unit *target; 2031 ptrdiff_t offset; 2032 2033 /* Reuse the zeroing that exists for goto_ptr. */ 2034 if (a0 == 0) { 2035 target = tcg_code_gen_epilogue; 2036 } else { 2037 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_X0, a0); 2038 target = tb_ret_addr; 2039 } 2040 2041 offset = tcg_pcrel_diff(s, target) >> 2; 2042 if (offset == sextract64(offset, 0, 26)) { 2043 tcg_out_insn(s, 3206, B, offset); 2044 } else { 2045 /* 2046 * Only x16/x17 generate BTI type Jump (2), 2047 * other registers generate BTI type Jump|Call (3). 2048 */ 2049 QEMU_BUILD_BUG_ON(TCG_REG_TMP0 != TCG_REG_X16); 2050 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP0, (intptr_t)target); 2051 tcg_out_insn(s, 3207, BR, TCG_REG_TMP0); 2052 } 2053} 2054 2055static void tcg_out_goto_tb(TCGContext *s, int which) 2056{ 2057 /* 2058 * Direct branch, or indirect address load, will be patched 2059 * by tb_target_set_jmp_target. Assert indirect load offset 2060 * in range early, regardless of direct branch distance. 2061 */ 2062 intptr_t i_off = tcg_pcrel_diff(s, (void *)get_jmp_target_addr(s, which)); 2063 tcg_debug_assert(i_off == sextract64(i_off, 0, 21)); 2064 2065 set_jmp_insn_offset(s, which); 2066 tcg_out32(s, I3206_B); 2067 tcg_out_insn(s, 3207, BR, TCG_REG_TMP0); 2068 set_jmp_reset_offset(s, which); 2069 tcg_out_bti(s, BTI_J); 2070} 2071 2072void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 2073 uintptr_t jmp_rx, uintptr_t jmp_rw) 2074{ 2075 uintptr_t d_addr = tb->jmp_target_addr[n]; 2076 ptrdiff_t d_offset = d_addr - jmp_rx; 2077 tcg_insn_unit insn; 2078 2079 /* Either directly branch, or indirect branch load. */ 2080 if (d_offset == sextract64(d_offset, 0, 28)) { 2081 insn = deposit32(I3206_B, 0, 26, d_offset >> 2); 2082 } else { 2083 uintptr_t i_addr = (uintptr_t)&tb->jmp_target_addr[n]; 2084 ptrdiff_t i_offset = i_addr - jmp_rx; 2085 2086 /* Note that we asserted this in range in tcg_out_goto_tb. */ 2087 insn = deposit32(I3305_LDR | TCG_REG_TMP0, 5, 19, i_offset >> 2); 2088 } 2089 qatomic_set((uint32_t *)jmp_rw, insn); 2090 flush_idcache_range(jmp_rx, jmp_rw, 4); 2091} 2092 2093 2094static void tgen_add(TCGContext *s, TCGType type, 2095 TCGReg a0, TCGReg a1, TCGReg a2) 2096{ 2097 tcg_out_insn(s, 3502, ADD, type, a0, a1, a2); 2098} 2099 2100static void tgen_addi(TCGContext *s, TCGType type, 2101 TCGReg a0, TCGReg a1, tcg_target_long a2) 2102{ 2103 if (a2 >= 0) { 2104 tcg_out_insn(s, 3401, ADDI, type, a0, a1, a2); 2105 } else { 2106 tcg_out_insn(s, 3401, SUBI, type, a0, a1, -a2); 2107 } 2108} 2109 2110static const TCGOutOpBinary outop_add = { 2111 .base.static_constraint = C_O1_I2(r, r, rA), 2112 .out_rrr = tgen_add, 2113 .out_rri = tgen_addi, 2114}; 2115 2116static void tgen_and(TCGContext *s, TCGType type, 2117 TCGReg a0, TCGReg a1, TCGReg a2) 2118{ 2119 tcg_out_insn(s, 3510, AND, type, a0, a1, a2); 2120} 2121 2122static void tgen_andi(TCGContext *s, TCGType type, 2123 TCGReg a0, TCGReg a1, tcg_target_long a2) 2124{ 2125 tcg_out_logicali(s, I3404_ANDI, type, a0, a1, a2); 2126} 2127 2128static const TCGOutOpBinary outop_and = { 2129 .base.static_constraint = C_O1_I2(r, r, rL), 2130 .out_rrr = tgen_and, 2131 .out_rri = tgen_andi, 2132}; 2133 2134static void tgen_andc(TCGContext *s, TCGType type, 2135 TCGReg a0, TCGReg a1, TCGReg a2) 2136{ 2137 tcg_out_insn(s, 3510, BIC, type, a0, a1, a2); 2138} 2139 2140static const TCGOutOpBinary outop_andc = { 2141 .base.static_constraint = C_O1_I2(r, r, r), 2142 .out_rrr = tgen_andc, 2143}; 2144 2145static void tgen_divs(TCGContext *s, TCGType type, 2146 TCGReg a0, TCGReg a1, TCGReg a2) 2147{ 2148 tcg_out_insn(s, 3508, SDIV, type, a0, a1, a2); 2149} 2150 2151static const TCGOutOpBinary outop_divs = { 2152 .base.static_constraint = C_O1_I2(r, r, r), 2153 .out_rrr = tgen_divs, 2154}; 2155 2156static const TCGOutOpDivRem outop_divs2 = { 2157 .base.static_constraint = C_NotImplemented, 2158}; 2159 2160static void tgen_divu(TCGContext *s, TCGType type, 2161 TCGReg a0, TCGReg a1, TCGReg a2) 2162{ 2163 tcg_out_insn(s, 3508, UDIV, type, a0, a1, a2); 2164} 2165 2166static const TCGOutOpBinary outop_divu = { 2167 .base.static_constraint = C_O1_I2(r, r, r), 2168 .out_rrr = tgen_divu, 2169}; 2170 2171static const TCGOutOpDivRem outop_divu2 = { 2172 .base.static_constraint = C_NotImplemented, 2173}; 2174 2175static void tgen_eqv(TCGContext *s, TCGType type, 2176 TCGReg a0, TCGReg a1, TCGReg a2) 2177{ 2178 tcg_out_insn(s, 3510, EON, type, a0, a1, a2); 2179} 2180 2181static const TCGOutOpBinary outop_eqv = { 2182 .base.static_constraint = C_O1_I2(r, r, r), 2183 .out_rrr = tgen_eqv, 2184}; 2185 2186static void tgen_mul(TCGContext *s, TCGType type, 2187 TCGReg a0, TCGReg a1, TCGReg a2) 2188{ 2189 tcg_out_insn(s, 3509, MADD, type, a0, a1, a2, TCG_REG_XZR); 2190} 2191 2192static const TCGOutOpBinary outop_mul = { 2193 .base.static_constraint = C_O1_I2(r, r, r), 2194 .out_rrr = tgen_mul, 2195}; 2196 2197static TCGConstraintSetIndex cset_mulh(TCGType type, unsigned flags) 2198{ 2199 return type == TCG_TYPE_I64 ? C_O1_I2(r, r, r) : C_NotImplemented; 2200} 2201 2202static void tgen_mulsh(TCGContext *s, TCGType type, 2203 TCGReg a0, TCGReg a1, TCGReg a2) 2204{ 2205 tcg_out_insn(s, 3508, SMULH, TCG_TYPE_I64, a0, a1, a2); 2206} 2207 2208static const TCGOutOpBinary outop_mulsh = { 2209 .base.static_constraint = C_Dynamic, 2210 .base.dynamic_constraint = cset_mulh, 2211 .out_rrr = tgen_mulsh, 2212}; 2213 2214static void tgen_muluh(TCGContext *s, TCGType type, 2215 TCGReg a0, TCGReg a1, TCGReg a2) 2216{ 2217 tcg_out_insn(s, 3508, UMULH, TCG_TYPE_I64, a0, a1, a2); 2218} 2219 2220static const TCGOutOpBinary outop_muluh = { 2221 .base.static_constraint = C_Dynamic, 2222 .base.dynamic_constraint = cset_mulh, 2223 .out_rrr = tgen_muluh, 2224}; 2225 2226static const TCGOutOpBinary outop_nand = { 2227 .base.static_constraint = C_NotImplemented, 2228}; 2229 2230static const TCGOutOpBinary outop_nor = { 2231 .base.static_constraint = C_NotImplemented, 2232}; 2233 2234static void tgen_or(TCGContext *s, TCGType type, 2235 TCGReg a0, TCGReg a1, TCGReg a2) 2236{ 2237 tcg_out_insn(s, 3510, ORR, type, a0, a1, a2); 2238} 2239 2240static void tgen_ori(TCGContext *s, TCGType type, 2241 TCGReg a0, TCGReg a1, tcg_target_long a2) 2242{ 2243 tcg_out_logicali(s, I3404_ORRI, type, a0, a1, a2); 2244} 2245 2246static const TCGOutOpBinary outop_or = { 2247 .base.static_constraint = C_O1_I2(r, r, rL), 2248 .out_rrr = tgen_or, 2249 .out_rri = tgen_ori, 2250}; 2251 2252static void tgen_orc(TCGContext *s, TCGType type, 2253 TCGReg a0, TCGReg a1, TCGReg a2) 2254{ 2255 tcg_out_insn(s, 3510, ORN, type, a0, a1, a2); 2256} 2257 2258static const TCGOutOpBinary outop_orc = { 2259 .base.static_constraint = C_O1_I2(r, r, r), 2260 .out_rrr = tgen_orc, 2261}; 2262 2263static void tgen_rems(TCGContext *s, TCGType type, 2264 TCGReg a0, TCGReg a1, TCGReg a2) 2265{ 2266 tcg_out_insn(s, 3508, SDIV, type, TCG_REG_TMP0, a1, a2); 2267 tcg_out_insn(s, 3509, MSUB, type, a0, TCG_REG_TMP0, a2, a1); 2268} 2269 2270static const TCGOutOpBinary outop_rems = { 2271 .base.static_constraint = C_O1_I2(r, r, r), 2272 .out_rrr = tgen_rems, 2273}; 2274 2275static void tgen_remu(TCGContext *s, TCGType type, 2276 TCGReg a0, TCGReg a1, TCGReg a2) 2277{ 2278 tcg_out_insn(s, 3508, UDIV, type, TCG_REG_TMP0, a1, a2); 2279 tcg_out_insn(s, 3509, MSUB, type, a0, TCG_REG_TMP0, a2, a1); 2280} 2281 2282static const TCGOutOpBinary outop_remu = { 2283 .base.static_constraint = C_O1_I2(r, r, r), 2284 .out_rrr = tgen_remu, 2285}; 2286 2287static void tgen_shl(TCGContext *s, TCGType type, 2288 TCGReg a0, TCGReg a1, TCGReg a2) 2289{ 2290 tcg_out_insn(s, 3508, LSLV, type, a0, a1, a2); 2291} 2292 2293static void tgen_shli(TCGContext *s, TCGType type, 2294 TCGReg a0, TCGReg a1, tcg_target_long a2) 2295{ 2296 int max = type == TCG_TYPE_I32 ? 31 : 63; 2297 tcg_out_ubfm(s, type, a0, a1, -a2 & max, ~a2 & max); 2298} 2299 2300static const TCGOutOpBinary outop_shl = { 2301 .base.static_constraint = C_O1_I2(r, r, ri), 2302 .out_rrr = tgen_shl, 2303 .out_rri = tgen_shli, 2304}; 2305 2306static void tgen_shr(TCGContext *s, TCGType type, 2307 TCGReg a0, TCGReg a1, TCGReg a2) 2308{ 2309 tcg_out_insn(s, 3508, LSRV, type, a0, a1, a2); 2310} 2311 2312static void tgen_shri(TCGContext *s, TCGType type, 2313 TCGReg a0, TCGReg a1, tcg_target_long a2) 2314{ 2315 int max = type == TCG_TYPE_I32 ? 31 : 63; 2316 tcg_out_ubfm(s, type, a0, a1, a2 & max, max); 2317} 2318 2319static const TCGOutOpBinary outop_shr = { 2320 .base.static_constraint = C_O1_I2(r, r, ri), 2321 .out_rrr = tgen_shr, 2322 .out_rri = tgen_shri, 2323}; 2324 2325static void tgen_sub(TCGContext *s, TCGType type, 2326 TCGReg a0, TCGReg a1, TCGReg a2) 2327{ 2328 tcg_out_insn(s, 3502, SUB, type, a0, a1, a2); 2329} 2330 2331static const TCGOutOpSubtract outop_sub = { 2332 .base.static_constraint = C_O1_I2(r, r, r), 2333 .out_rrr = tgen_sub, 2334}; 2335 2336static void tgen_xor(TCGContext *s, TCGType type, 2337 TCGReg a0, TCGReg a1, TCGReg a2) 2338{ 2339 tcg_out_insn(s, 3510, EOR, type, a0, a1, a2); 2340} 2341 2342static void tgen_xori(TCGContext *s, TCGType type, 2343 TCGReg a0, TCGReg a1, tcg_target_long a2) 2344{ 2345 tcg_out_logicali(s, I3404_EORI, type, a0, a1, a2); 2346} 2347 2348static const TCGOutOpBinary outop_xor = { 2349 .base.static_constraint = C_O1_I2(r, r, rL), 2350 .out_rrr = tgen_xor, 2351 .out_rri = tgen_xori, 2352}; 2353 2354 2355static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2356{ 2357 tgen_sub(s, type, a0, TCG_REG_XZR, a1); 2358} 2359 2360static const TCGOutOpUnary outop_neg = { 2361 .base.static_constraint = C_O1_I1(r, r), 2362 .out_rr = tgen_neg, 2363}; 2364 2365static void tgen_not(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2366{ 2367 tgen_orc(s, type, a0, TCG_REG_XZR, a1); 2368} 2369 2370static const TCGOutOpUnary outop_not = { 2371 .base.static_constraint = C_O1_I1(r, r), 2372 .out_rr = tgen_not, 2373}; 2374 2375 2376static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext, 2377 const TCGArg args[TCG_MAX_OP_ARGS], 2378 const int const_args[TCG_MAX_OP_ARGS]) 2379{ 2380 /* Hoist the loads of the most common arguments. */ 2381 TCGArg a0 = args[0]; 2382 TCGArg a1 = args[1]; 2383 TCGArg a2 = args[2]; 2384 int c2 = const_args[2]; 2385 2386 switch (opc) { 2387 case INDEX_op_goto_ptr: 2388 tcg_out_insn(s, 3207, BR, a0); 2389 break; 2390 2391 case INDEX_op_br: 2392 tcg_out_goto_label(s, arg_label(a0)); 2393 break; 2394 2395 case INDEX_op_ld8u_i32: 2396 case INDEX_op_ld8u_i64: 2397 tcg_out_ldst(s, I3312_LDRB, a0, a1, a2, 0); 2398 break; 2399 case INDEX_op_ld8s_i32: 2400 tcg_out_ldst(s, I3312_LDRSBW, a0, a1, a2, 0); 2401 break; 2402 case INDEX_op_ld8s_i64: 2403 tcg_out_ldst(s, I3312_LDRSBX, a0, a1, a2, 0); 2404 break; 2405 case INDEX_op_ld16u_i32: 2406 case INDEX_op_ld16u_i64: 2407 tcg_out_ldst(s, I3312_LDRH, a0, a1, a2, 1); 2408 break; 2409 case INDEX_op_ld16s_i32: 2410 tcg_out_ldst(s, I3312_LDRSHW, a0, a1, a2, 1); 2411 break; 2412 case INDEX_op_ld16s_i64: 2413 tcg_out_ldst(s, I3312_LDRSHX, a0, a1, a2, 1); 2414 break; 2415 case INDEX_op_ld_i32: 2416 case INDEX_op_ld32u_i64: 2417 tcg_out_ldst(s, I3312_LDRW, a0, a1, a2, 2); 2418 break; 2419 case INDEX_op_ld32s_i64: 2420 tcg_out_ldst(s, I3312_LDRSWX, a0, a1, a2, 2); 2421 break; 2422 case INDEX_op_ld_i64: 2423 tcg_out_ldst(s, I3312_LDRX, a0, a1, a2, 3); 2424 break; 2425 2426 case INDEX_op_st8_i32: 2427 case INDEX_op_st8_i64: 2428 tcg_out_ldst(s, I3312_STRB, a0, a1, a2, 0); 2429 break; 2430 case INDEX_op_st16_i32: 2431 case INDEX_op_st16_i64: 2432 tcg_out_ldst(s, I3312_STRH, a0, a1, a2, 1); 2433 break; 2434 case INDEX_op_st_i32: 2435 case INDEX_op_st32_i64: 2436 tcg_out_ldst(s, I3312_STRW, a0, a1, a2, 2); 2437 break; 2438 case INDEX_op_st_i64: 2439 tcg_out_ldst(s, I3312_STRX, a0, a1, a2, 3); 2440 break; 2441 2442 case INDEX_op_sar_i64: 2443 case INDEX_op_sar_i32: 2444 if (c2) { 2445 tcg_out_sar(s, ext, a0, a1, a2); 2446 } else { 2447 tcg_out_insn(s, 3508, ASRV, ext, a0, a1, a2); 2448 } 2449 break; 2450 2451 case INDEX_op_rotr_i64: 2452 case INDEX_op_rotr_i32: 2453 if (c2) { 2454 tcg_out_rotr(s, ext, a0, a1, a2); 2455 } else { 2456 tcg_out_insn(s, 3508, RORV, ext, a0, a1, a2); 2457 } 2458 break; 2459 2460 case INDEX_op_rotl_i64: 2461 case INDEX_op_rotl_i32: 2462 if (c2) { 2463 tcg_out_rotl(s, ext, a0, a1, a2); 2464 } else { 2465 tcg_out_insn(s, 3502, SUB, 0, TCG_REG_TMP0, TCG_REG_XZR, a2); 2466 tcg_out_insn(s, 3508, RORV, ext, a0, a1, TCG_REG_TMP0); 2467 } 2468 break; 2469 2470 case INDEX_op_clz_i64: 2471 case INDEX_op_clz_i32: 2472 tcg_out_cltz(s, ext, a0, a1, a2, c2, false); 2473 break; 2474 case INDEX_op_ctz_i64: 2475 case INDEX_op_ctz_i32: 2476 tcg_out_cltz(s, ext, a0, a1, a2, c2, true); 2477 break; 2478 2479 case INDEX_op_brcond_i32: 2480 a1 = (int32_t)a1; 2481 /* FALLTHRU */ 2482 case INDEX_op_brcond_i64: 2483 tcg_out_brcond(s, ext, a2, a0, a1, const_args[1], arg_label(args[3])); 2484 break; 2485 2486 case INDEX_op_setcond_i32: 2487 a2 = (int32_t)a2; 2488 /* FALLTHRU */ 2489 case INDEX_op_setcond_i64: 2490 tcg_out_cmp(s, ext, args[3], a1, a2, c2); 2491 /* Use CSET alias of CSINC Wd, WZR, WZR, invert(cond). */ 2492 tcg_out_insn(s, 3506, CSINC, TCG_TYPE_I32, a0, TCG_REG_XZR, 2493 TCG_REG_XZR, tcg_invert_cond(args[3])); 2494 break; 2495 2496 case INDEX_op_negsetcond_i32: 2497 a2 = (int32_t)a2; 2498 /* FALLTHRU */ 2499 case INDEX_op_negsetcond_i64: 2500 tcg_out_cmp(s, ext, args[3], a1, a2, c2); 2501 /* Use CSETM alias of CSINV Wd, WZR, WZR, invert(cond). */ 2502 tcg_out_insn(s, 3506, CSINV, ext, a0, TCG_REG_XZR, 2503 TCG_REG_XZR, tcg_invert_cond(args[3])); 2504 break; 2505 2506 case INDEX_op_movcond_i32: 2507 a2 = (int32_t)a2; 2508 /* FALLTHRU */ 2509 case INDEX_op_movcond_i64: 2510 tcg_out_cmp(s, ext, args[5], a1, a2, c2); 2511 tcg_out_insn(s, 3506, CSEL, ext, a0, args[3], args[4], args[5]); 2512 break; 2513 2514 case INDEX_op_qemu_ld_i32: 2515 case INDEX_op_qemu_ld_i64: 2516 tcg_out_qemu_ld(s, a0, a1, a2, ext); 2517 break; 2518 case INDEX_op_qemu_st_i32: 2519 case INDEX_op_qemu_st_i64: 2520 tcg_out_qemu_st(s, a0, a1, a2, ext); 2521 break; 2522 case INDEX_op_qemu_ld_i128: 2523 tcg_out_qemu_ldst_i128(s, a0, a1, a2, args[3], true); 2524 break; 2525 case INDEX_op_qemu_st_i128: 2526 tcg_out_qemu_ldst_i128(s, a0, a1, a2, args[3], false); 2527 break; 2528 2529 case INDEX_op_bswap64_i64: 2530 tcg_out_rev(s, TCG_TYPE_I64, MO_64, a0, a1); 2531 break; 2532 case INDEX_op_bswap32_i64: 2533 tcg_out_rev(s, TCG_TYPE_I32, MO_32, a0, a1); 2534 if (a2 & TCG_BSWAP_OS) { 2535 tcg_out_ext32s(s, a0, a0); 2536 } 2537 break; 2538 case INDEX_op_bswap32_i32: 2539 tcg_out_rev(s, TCG_TYPE_I32, MO_32, a0, a1); 2540 break; 2541 case INDEX_op_bswap16_i64: 2542 case INDEX_op_bswap16_i32: 2543 tcg_out_rev(s, TCG_TYPE_I32, MO_16, a0, a1); 2544 if (a2 & TCG_BSWAP_OS) { 2545 /* Output must be sign-extended. */ 2546 tcg_out_ext16s(s, ext, a0, a0); 2547 } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 2548 /* Output must be zero-extended, but input isn't. */ 2549 tcg_out_ext16u(s, a0, a0); 2550 } 2551 break; 2552 2553 case INDEX_op_deposit_i64: 2554 case INDEX_op_deposit_i32: 2555 tcg_out_dep(s, ext, a0, a2, args[3], args[4]); 2556 break; 2557 2558 case INDEX_op_extract_i64: 2559 case INDEX_op_extract_i32: 2560 if (a2 == 0) { 2561 uint64_t mask = MAKE_64BIT_MASK(0, args[3]); 2562 tcg_out_logicali(s, I3404_ANDI, ext, a0, a1, mask); 2563 } else { 2564 tcg_out_ubfm(s, ext, a0, a1, a2, a2 + args[3] - 1); 2565 } 2566 break; 2567 2568 case INDEX_op_sextract_i64: 2569 case INDEX_op_sextract_i32: 2570 tcg_out_sbfm(s, ext, a0, a1, a2, a2 + args[3] - 1); 2571 break; 2572 2573 case INDEX_op_extract2_i64: 2574 case INDEX_op_extract2_i32: 2575 tcg_out_extr(s, ext, a0, a2, a1, args[3]); 2576 break; 2577 2578 case INDEX_op_add2_i32: 2579 tcg_out_addsub2(s, TCG_TYPE_I32, a0, a1, a2, args[3], 2580 (int32_t)args[4], args[5], const_args[4], 2581 const_args[5], false); 2582 break; 2583 case INDEX_op_add2_i64: 2584 tcg_out_addsub2(s, TCG_TYPE_I64, a0, a1, a2, args[3], args[4], 2585 args[5], const_args[4], const_args[5], false); 2586 break; 2587 case INDEX_op_sub2_i32: 2588 tcg_out_addsub2(s, TCG_TYPE_I32, a0, a1, a2, args[3], 2589 (int32_t)args[4], args[5], const_args[4], 2590 const_args[5], true); 2591 break; 2592 case INDEX_op_sub2_i64: 2593 tcg_out_addsub2(s, TCG_TYPE_I64, a0, a1, a2, args[3], args[4], 2594 args[5], const_args[4], const_args[5], true); 2595 break; 2596 2597 case INDEX_op_mb: 2598 tcg_out_mb(s, a0); 2599 break; 2600 2601 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2602 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2603 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2604 case INDEX_op_ext_i32_i64: /* Always emitted via tcg_reg_alloc_op. */ 2605 case INDEX_op_extu_i32_i64: 2606 case INDEX_op_extrl_i64_i32: 2607 default: 2608 g_assert_not_reached(); 2609 } 2610} 2611 2612static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 2613 unsigned vecl, unsigned vece, 2614 const TCGArg args[TCG_MAX_OP_ARGS], 2615 const int const_args[TCG_MAX_OP_ARGS]) 2616{ 2617 static const AArch64Insn cmp_vec_insn[16] = { 2618 [TCG_COND_EQ] = I3616_CMEQ, 2619 [TCG_COND_GT] = I3616_CMGT, 2620 [TCG_COND_GE] = I3616_CMGE, 2621 [TCG_COND_GTU] = I3616_CMHI, 2622 [TCG_COND_GEU] = I3616_CMHS, 2623 }; 2624 static const AArch64Insn cmp_scalar_insn[16] = { 2625 [TCG_COND_EQ] = I3611_CMEQ, 2626 [TCG_COND_GT] = I3611_CMGT, 2627 [TCG_COND_GE] = I3611_CMGE, 2628 [TCG_COND_GTU] = I3611_CMHI, 2629 [TCG_COND_GEU] = I3611_CMHS, 2630 }; 2631 static const AArch64Insn cmp0_vec_insn[16] = { 2632 [TCG_COND_EQ] = I3617_CMEQ0, 2633 [TCG_COND_GT] = I3617_CMGT0, 2634 [TCG_COND_GE] = I3617_CMGE0, 2635 [TCG_COND_LT] = I3617_CMLT0, 2636 [TCG_COND_LE] = I3617_CMLE0, 2637 }; 2638 static const AArch64Insn cmp0_scalar_insn[16] = { 2639 [TCG_COND_EQ] = I3612_CMEQ0, 2640 [TCG_COND_GT] = I3612_CMGT0, 2641 [TCG_COND_GE] = I3612_CMGE0, 2642 [TCG_COND_LT] = I3612_CMLT0, 2643 [TCG_COND_LE] = I3612_CMLE0, 2644 }; 2645 2646 TCGType type = vecl + TCG_TYPE_V64; 2647 unsigned is_q = vecl; 2648 bool is_scalar = !is_q && vece == MO_64; 2649 TCGArg a0, a1, a2, a3; 2650 int cmode, imm8; 2651 2652 a0 = args[0]; 2653 a1 = args[1]; 2654 a2 = args[2]; 2655 2656 switch (opc) { 2657 case INDEX_op_ld_vec: 2658 tcg_out_ld(s, type, a0, a1, a2); 2659 break; 2660 case INDEX_op_st_vec: 2661 tcg_out_st(s, type, a0, a1, a2); 2662 break; 2663 case INDEX_op_dupm_vec: 2664 tcg_out_dupm_vec(s, type, vece, a0, a1, a2); 2665 break; 2666 case INDEX_op_add_vec: 2667 if (is_scalar) { 2668 tcg_out_insn(s, 3611, ADD, vece, a0, a1, a2); 2669 } else { 2670 tcg_out_insn(s, 3616, ADD, is_q, vece, a0, a1, a2); 2671 } 2672 break; 2673 case INDEX_op_sub_vec: 2674 if (is_scalar) { 2675 tcg_out_insn(s, 3611, SUB, vece, a0, a1, a2); 2676 } else { 2677 tcg_out_insn(s, 3616, SUB, is_q, vece, a0, a1, a2); 2678 } 2679 break; 2680 case INDEX_op_mul_vec: 2681 tcg_out_insn(s, 3616, MUL, is_q, vece, a0, a1, a2); 2682 break; 2683 case INDEX_op_neg_vec: 2684 if (is_scalar) { 2685 tcg_out_insn(s, 3612, NEG, vece, a0, a1); 2686 } else { 2687 tcg_out_insn(s, 3617, NEG, is_q, vece, a0, a1); 2688 } 2689 break; 2690 case INDEX_op_abs_vec: 2691 if (is_scalar) { 2692 tcg_out_insn(s, 3612, ABS, vece, a0, a1); 2693 } else { 2694 tcg_out_insn(s, 3617, ABS, is_q, vece, a0, a1); 2695 } 2696 break; 2697 case INDEX_op_and_vec: 2698 if (const_args[2]) { 2699 is_shimm1632(~a2, &cmode, &imm8); 2700 if (a0 == a1) { 2701 tcg_out_insn(s, 3606, BIC, is_q, a0, 0, cmode, imm8); 2702 return; 2703 } 2704 tcg_out_insn(s, 3606, MVNI, is_q, a0, 0, cmode, imm8); 2705 a2 = a0; 2706 } 2707 tcg_out_insn(s, 3616, AND, is_q, 0, a0, a1, a2); 2708 break; 2709 case INDEX_op_or_vec: 2710 if (const_args[2]) { 2711 is_shimm1632(a2, &cmode, &imm8); 2712 if (a0 == a1) { 2713 tcg_out_insn(s, 3606, ORR, is_q, a0, 0, cmode, imm8); 2714 return; 2715 } 2716 tcg_out_insn(s, 3606, MOVI, is_q, a0, 0, cmode, imm8); 2717 a2 = a0; 2718 } 2719 tcg_out_insn(s, 3616, ORR, is_q, 0, a0, a1, a2); 2720 break; 2721 case INDEX_op_andc_vec: 2722 if (const_args[2]) { 2723 is_shimm1632(a2, &cmode, &imm8); 2724 if (a0 == a1) { 2725 tcg_out_insn(s, 3606, BIC, is_q, a0, 0, cmode, imm8); 2726 return; 2727 } 2728 tcg_out_insn(s, 3606, MOVI, is_q, a0, 0, cmode, imm8); 2729 a2 = a0; 2730 } 2731 tcg_out_insn(s, 3616, BIC, is_q, 0, a0, a1, a2); 2732 break; 2733 case INDEX_op_orc_vec: 2734 if (const_args[2]) { 2735 is_shimm1632(~a2, &cmode, &imm8); 2736 if (a0 == a1) { 2737 tcg_out_insn(s, 3606, ORR, is_q, a0, 0, cmode, imm8); 2738 return; 2739 } 2740 tcg_out_insn(s, 3606, MVNI, is_q, a0, 0, cmode, imm8); 2741 a2 = a0; 2742 } 2743 tcg_out_insn(s, 3616, ORN, is_q, 0, a0, a1, a2); 2744 break; 2745 case INDEX_op_xor_vec: 2746 tcg_out_insn(s, 3616, EOR, is_q, 0, a0, a1, a2); 2747 break; 2748 case INDEX_op_ssadd_vec: 2749 if (is_scalar) { 2750 tcg_out_insn(s, 3611, SQADD, vece, a0, a1, a2); 2751 } else { 2752 tcg_out_insn(s, 3616, SQADD, is_q, vece, a0, a1, a2); 2753 } 2754 break; 2755 case INDEX_op_sssub_vec: 2756 if (is_scalar) { 2757 tcg_out_insn(s, 3611, SQSUB, vece, a0, a1, a2); 2758 } else { 2759 tcg_out_insn(s, 3616, SQSUB, is_q, vece, a0, a1, a2); 2760 } 2761 break; 2762 case INDEX_op_usadd_vec: 2763 if (is_scalar) { 2764 tcg_out_insn(s, 3611, UQADD, vece, a0, a1, a2); 2765 } else { 2766 tcg_out_insn(s, 3616, UQADD, is_q, vece, a0, a1, a2); 2767 } 2768 break; 2769 case INDEX_op_ussub_vec: 2770 if (is_scalar) { 2771 tcg_out_insn(s, 3611, UQSUB, vece, a0, a1, a2); 2772 } else { 2773 tcg_out_insn(s, 3616, UQSUB, is_q, vece, a0, a1, a2); 2774 } 2775 break; 2776 case INDEX_op_smax_vec: 2777 tcg_out_insn(s, 3616, SMAX, is_q, vece, a0, a1, a2); 2778 break; 2779 case INDEX_op_smin_vec: 2780 tcg_out_insn(s, 3616, SMIN, is_q, vece, a0, a1, a2); 2781 break; 2782 case INDEX_op_umax_vec: 2783 tcg_out_insn(s, 3616, UMAX, is_q, vece, a0, a1, a2); 2784 break; 2785 case INDEX_op_umin_vec: 2786 tcg_out_insn(s, 3616, UMIN, is_q, vece, a0, a1, a2); 2787 break; 2788 case INDEX_op_not_vec: 2789 tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a1); 2790 break; 2791 case INDEX_op_shli_vec: 2792 if (is_scalar) { 2793 tcg_out_insn(s, 3609, SHL, a0, a1, a2 + (8 << vece)); 2794 } else { 2795 tcg_out_insn(s, 3614, SHL, is_q, a0, a1, a2 + (8 << vece)); 2796 } 2797 break; 2798 case INDEX_op_shri_vec: 2799 if (is_scalar) { 2800 tcg_out_insn(s, 3609, USHR, a0, a1, (16 << vece) - a2); 2801 } else { 2802 tcg_out_insn(s, 3614, USHR, is_q, a0, a1, (16 << vece) - a2); 2803 } 2804 break; 2805 case INDEX_op_sari_vec: 2806 if (is_scalar) { 2807 tcg_out_insn(s, 3609, SSHR, a0, a1, (16 << vece) - a2); 2808 } else { 2809 tcg_out_insn(s, 3614, SSHR, is_q, a0, a1, (16 << vece) - a2); 2810 } 2811 break; 2812 case INDEX_op_aa64_sli_vec: 2813 if (is_scalar) { 2814 tcg_out_insn(s, 3609, SLI, a0, a2, args[3] + (8 << vece)); 2815 } else { 2816 tcg_out_insn(s, 3614, SLI, is_q, a0, a2, args[3] + (8 << vece)); 2817 } 2818 break; 2819 case INDEX_op_shlv_vec: 2820 if (is_scalar) { 2821 tcg_out_insn(s, 3611, USHL, vece, a0, a1, a2); 2822 } else { 2823 tcg_out_insn(s, 3616, USHL, is_q, vece, a0, a1, a2); 2824 } 2825 break; 2826 case INDEX_op_aa64_sshl_vec: 2827 if (is_scalar) { 2828 tcg_out_insn(s, 3611, SSHL, vece, a0, a1, a2); 2829 } else { 2830 tcg_out_insn(s, 3616, SSHL, is_q, vece, a0, a1, a2); 2831 } 2832 break; 2833 case INDEX_op_cmp_vec: 2834 { 2835 TCGCond cond = args[3]; 2836 AArch64Insn insn; 2837 2838 switch (cond) { 2839 case TCG_COND_NE: 2840 if (const_args[2]) { 2841 if (is_scalar) { 2842 tcg_out_insn(s, 3611, CMTST, vece, a0, a1, a1); 2843 } else { 2844 tcg_out_insn(s, 3616, CMTST, is_q, vece, a0, a1, a1); 2845 } 2846 } else { 2847 if (is_scalar) { 2848 tcg_out_insn(s, 3611, CMEQ, vece, a0, a1, a2); 2849 } else { 2850 tcg_out_insn(s, 3616, CMEQ, is_q, vece, a0, a1, a2); 2851 } 2852 tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a0); 2853 } 2854 break; 2855 2856 case TCG_COND_TSTNE: 2857 case TCG_COND_TSTEQ: 2858 if (const_args[2]) { 2859 /* (x & 0) == 0 */ 2860 tcg_out_dupi_vec(s, type, MO_8, a0, 2861 -(cond == TCG_COND_TSTEQ)); 2862 break; 2863 } 2864 if (is_scalar) { 2865 tcg_out_insn(s, 3611, CMTST, vece, a0, a1, a2); 2866 } else { 2867 tcg_out_insn(s, 3616, CMTST, is_q, vece, a0, a1, a2); 2868 } 2869 if (cond == TCG_COND_TSTEQ) { 2870 tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a0); 2871 } 2872 break; 2873 2874 default: 2875 if (const_args[2]) { 2876 if (is_scalar) { 2877 insn = cmp0_scalar_insn[cond]; 2878 if (insn) { 2879 tcg_out_insn_3612(s, insn, vece, a0, a1); 2880 break; 2881 } 2882 } else { 2883 insn = cmp0_vec_insn[cond]; 2884 if (insn) { 2885 tcg_out_insn_3617(s, insn, is_q, vece, a0, a1); 2886 break; 2887 } 2888 } 2889 tcg_out_dupi_vec(s, type, MO_8, TCG_VEC_TMP0, 0); 2890 a2 = TCG_VEC_TMP0; 2891 } 2892 if (is_scalar) { 2893 insn = cmp_scalar_insn[cond]; 2894 if (insn == 0) { 2895 TCGArg t; 2896 t = a1, a1 = a2, a2 = t; 2897 cond = tcg_swap_cond(cond); 2898 insn = cmp_scalar_insn[cond]; 2899 tcg_debug_assert(insn != 0); 2900 } 2901 tcg_out_insn_3611(s, insn, vece, a0, a1, a2); 2902 } else { 2903 insn = cmp_vec_insn[cond]; 2904 if (insn == 0) { 2905 TCGArg t; 2906 t = a1, a1 = a2, a2 = t; 2907 cond = tcg_swap_cond(cond); 2908 insn = cmp_vec_insn[cond]; 2909 tcg_debug_assert(insn != 0); 2910 } 2911 tcg_out_insn_3616(s, insn, is_q, vece, a0, a1, a2); 2912 } 2913 break; 2914 } 2915 } 2916 break; 2917 2918 case INDEX_op_bitsel_vec: 2919 a3 = args[3]; 2920 if (a0 == a3) { 2921 tcg_out_insn(s, 3616, BIT, is_q, 0, a0, a2, a1); 2922 } else if (a0 == a2) { 2923 tcg_out_insn(s, 3616, BIF, is_q, 0, a0, a3, a1); 2924 } else { 2925 if (a0 != a1) { 2926 tcg_out_mov(s, type, a0, a1); 2927 } 2928 tcg_out_insn(s, 3616, BSL, is_q, 0, a0, a2, a3); 2929 } 2930 break; 2931 2932 case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ 2933 case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ 2934 default: 2935 g_assert_not_reached(); 2936 } 2937} 2938 2939int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 2940{ 2941 switch (opc) { 2942 case INDEX_op_add_vec: 2943 case INDEX_op_sub_vec: 2944 case INDEX_op_and_vec: 2945 case INDEX_op_or_vec: 2946 case INDEX_op_xor_vec: 2947 case INDEX_op_andc_vec: 2948 case INDEX_op_orc_vec: 2949 case INDEX_op_neg_vec: 2950 case INDEX_op_abs_vec: 2951 case INDEX_op_not_vec: 2952 case INDEX_op_cmp_vec: 2953 case INDEX_op_shli_vec: 2954 case INDEX_op_shri_vec: 2955 case INDEX_op_sari_vec: 2956 case INDEX_op_ssadd_vec: 2957 case INDEX_op_sssub_vec: 2958 case INDEX_op_usadd_vec: 2959 case INDEX_op_ussub_vec: 2960 case INDEX_op_shlv_vec: 2961 case INDEX_op_bitsel_vec: 2962 return 1; 2963 case INDEX_op_rotli_vec: 2964 case INDEX_op_shrv_vec: 2965 case INDEX_op_sarv_vec: 2966 case INDEX_op_rotlv_vec: 2967 case INDEX_op_rotrv_vec: 2968 return -1; 2969 case INDEX_op_mul_vec: 2970 case INDEX_op_smax_vec: 2971 case INDEX_op_smin_vec: 2972 case INDEX_op_umax_vec: 2973 case INDEX_op_umin_vec: 2974 return vece < MO_64; 2975 2976 default: 2977 return 0; 2978 } 2979} 2980 2981void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 2982 TCGArg a0, ...) 2983{ 2984 va_list va; 2985 TCGv_vec v0, v1, v2, t1, t2, c1; 2986 TCGArg a2; 2987 2988 va_start(va, a0); 2989 v0 = temp_tcgv_vec(arg_temp(a0)); 2990 v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 2991 a2 = va_arg(va, TCGArg); 2992 va_end(va); 2993 2994 switch (opc) { 2995 case INDEX_op_rotli_vec: 2996 t1 = tcg_temp_new_vec(type); 2997 tcg_gen_shri_vec(vece, t1, v1, -a2 & ((8 << vece) - 1)); 2998 vec_gen_4(INDEX_op_aa64_sli_vec, type, vece, 2999 tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(v1), a2); 3000 tcg_temp_free_vec(t1); 3001 break; 3002 3003 case INDEX_op_shrv_vec: 3004 case INDEX_op_sarv_vec: 3005 /* Right shifts are negative left shifts for AArch64. */ 3006 v2 = temp_tcgv_vec(arg_temp(a2)); 3007 t1 = tcg_temp_new_vec(type); 3008 tcg_gen_neg_vec(vece, t1, v2); 3009 opc = (opc == INDEX_op_shrv_vec 3010 ? INDEX_op_shlv_vec : INDEX_op_aa64_sshl_vec); 3011 vec_gen_3(opc, type, vece, tcgv_vec_arg(v0), 3012 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 3013 tcg_temp_free_vec(t1); 3014 break; 3015 3016 case INDEX_op_rotlv_vec: 3017 v2 = temp_tcgv_vec(arg_temp(a2)); 3018 t1 = tcg_temp_new_vec(type); 3019 c1 = tcg_constant_vec(type, vece, 8 << vece); 3020 tcg_gen_sub_vec(vece, t1, v2, c1); 3021 /* Right shifts are negative left shifts for AArch64. */ 3022 vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t1), 3023 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 3024 vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(v0), 3025 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 3026 tcg_gen_or_vec(vece, v0, v0, t1); 3027 tcg_temp_free_vec(t1); 3028 break; 3029 3030 case INDEX_op_rotrv_vec: 3031 v2 = temp_tcgv_vec(arg_temp(a2)); 3032 t1 = tcg_temp_new_vec(type); 3033 t2 = tcg_temp_new_vec(type); 3034 c1 = tcg_constant_vec(type, vece, 8 << vece); 3035 tcg_gen_neg_vec(vece, t1, v2); 3036 tcg_gen_sub_vec(vece, t2, c1, v2); 3037 /* Right shifts are negative left shifts for AArch64. */ 3038 vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t1), 3039 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 3040 vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t2), 3041 tcgv_vec_arg(v1), tcgv_vec_arg(t2)); 3042 tcg_gen_or_vec(vece, v0, t1, t2); 3043 tcg_temp_free_vec(t1); 3044 tcg_temp_free_vec(t2); 3045 break; 3046 3047 default: 3048 g_assert_not_reached(); 3049 } 3050} 3051 3052static TCGConstraintSetIndex 3053tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) 3054{ 3055 switch (op) { 3056 case INDEX_op_goto_ptr: 3057 return C_O0_I1(r); 3058 3059 case INDEX_op_ld8u_i32: 3060 case INDEX_op_ld8s_i32: 3061 case INDEX_op_ld16u_i32: 3062 case INDEX_op_ld16s_i32: 3063 case INDEX_op_ld_i32: 3064 case INDEX_op_ld8u_i64: 3065 case INDEX_op_ld8s_i64: 3066 case INDEX_op_ld16u_i64: 3067 case INDEX_op_ld16s_i64: 3068 case INDEX_op_ld32u_i64: 3069 case INDEX_op_ld32s_i64: 3070 case INDEX_op_ld_i64: 3071 case INDEX_op_bswap16_i32: 3072 case INDEX_op_bswap32_i32: 3073 case INDEX_op_bswap16_i64: 3074 case INDEX_op_bswap32_i64: 3075 case INDEX_op_bswap64_i64: 3076 case INDEX_op_ext_i32_i64: 3077 case INDEX_op_extu_i32_i64: 3078 case INDEX_op_extract_i32: 3079 case INDEX_op_extract_i64: 3080 case INDEX_op_sextract_i32: 3081 case INDEX_op_sextract_i64: 3082 return C_O1_I1(r, r); 3083 3084 case INDEX_op_st8_i32: 3085 case INDEX_op_st16_i32: 3086 case INDEX_op_st_i32: 3087 case INDEX_op_st8_i64: 3088 case INDEX_op_st16_i64: 3089 case INDEX_op_st32_i64: 3090 case INDEX_op_st_i64: 3091 return C_O0_I2(rz, r); 3092 3093 case INDEX_op_setcond_i32: 3094 case INDEX_op_setcond_i64: 3095 case INDEX_op_negsetcond_i32: 3096 case INDEX_op_negsetcond_i64: 3097 return C_O1_I2(r, r, rC); 3098 3099 case INDEX_op_sar_i32: 3100 case INDEX_op_rotl_i32: 3101 case INDEX_op_rotr_i32: 3102 case INDEX_op_sar_i64: 3103 case INDEX_op_rotl_i64: 3104 case INDEX_op_rotr_i64: 3105 return C_O1_I2(r, r, ri); 3106 3107 case INDEX_op_clz_i32: 3108 case INDEX_op_ctz_i32: 3109 case INDEX_op_clz_i64: 3110 case INDEX_op_ctz_i64: 3111 return C_O1_I2(r, r, rAL); 3112 3113 case INDEX_op_brcond_i32: 3114 case INDEX_op_brcond_i64: 3115 return C_O0_I2(r, rC); 3116 3117 case INDEX_op_movcond_i32: 3118 case INDEX_op_movcond_i64: 3119 return C_O1_I4(r, r, rC, rz, rz); 3120 3121 case INDEX_op_qemu_ld_i32: 3122 case INDEX_op_qemu_ld_i64: 3123 return C_O1_I1(r, r); 3124 case INDEX_op_qemu_ld_i128: 3125 return C_O2_I1(r, r, r); 3126 case INDEX_op_qemu_st_i32: 3127 case INDEX_op_qemu_st_i64: 3128 return C_O0_I2(rz, r); 3129 case INDEX_op_qemu_st_i128: 3130 return C_O0_I3(rz, rz, r); 3131 3132 case INDEX_op_deposit_i32: 3133 case INDEX_op_deposit_i64: 3134 return C_O1_I2(r, 0, rz); 3135 3136 case INDEX_op_extract2_i32: 3137 case INDEX_op_extract2_i64: 3138 return C_O1_I2(r, rz, rz); 3139 3140 case INDEX_op_add2_i32: 3141 case INDEX_op_add2_i64: 3142 case INDEX_op_sub2_i32: 3143 case INDEX_op_sub2_i64: 3144 return C_O2_I4(r, r, rz, rz, rA, rMZ); 3145 3146 case INDEX_op_add_vec: 3147 case INDEX_op_sub_vec: 3148 case INDEX_op_mul_vec: 3149 case INDEX_op_xor_vec: 3150 case INDEX_op_ssadd_vec: 3151 case INDEX_op_sssub_vec: 3152 case INDEX_op_usadd_vec: 3153 case INDEX_op_ussub_vec: 3154 case INDEX_op_smax_vec: 3155 case INDEX_op_smin_vec: 3156 case INDEX_op_umax_vec: 3157 case INDEX_op_umin_vec: 3158 case INDEX_op_shlv_vec: 3159 case INDEX_op_shrv_vec: 3160 case INDEX_op_sarv_vec: 3161 case INDEX_op_aa64_sshl_vec: 3162 return C_O1_I2(w, w, w); 3163 case INDEX_op_not_vec: 3164 case INDEX_op_neg_vec: 3165 case INDEX_op_abs_vec: 3166 case INDEX_op_shli_vec: 3167 case INDEX_op_shri_vec: 3168 case INDEX_op_sari_vec: 3169 return C_O1_I1(w, w); 3170 case INDEX_op_ld_vec: 3171 case INDEX_op_dupm_vec: 3172 return C_O1_I1(w, r); 3173 case INDEX_op_st_vec: 3174 return C_O0_I2(w, r); 3175 case INDEX_op_dup_vec: 3176 return C_O1_I1(w, wr); 3177 case INDEX_op_or_vec: 3178 case INDEX_op_andc_vec: 3179 return C_O1_I2(w, w, wO); 3180 case INDEX_op_and_vec: 3181 case INDEX_op_orc_vec: 3182 return C_O1_I2(w, w, wN); 3183 case INDEX_op_cmp_vec: 3184 return C_O1_I2(w, w, wZ); 3185 case INDEX_op_bitsel_vec: 3186 return C_O1_I3(w, w, w, w); 3187 case INDEX_op_aa64_sli_vec: 3188 return C_O1_I2(w, 0, w); 3189 3190 default: 3191 return C_NotImplemented; 3192 } 3193} 3194 3195static void tcg_target_init(TCGContext *s) 3196{ 3197 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffffu; 3198 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffffu; 3199 tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull; 3200 tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull; 3201 3202 tcg_target_call_clobber_regs = -1ull; 3203 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X19); 3204 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X20); 3205 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X21); 3206 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X22); 3207 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X23); 3208 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X24); 3209 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X25); 3210 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X26); 3211 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X27); 3212 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X28); 3213 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X29); 3214 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V8); 3215 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V9); 3216 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V10); 3217 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V11); 3218 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V12); 3219 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V13); 3220 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V14); 3221 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V15); 3222 3223 s->reserved_regs = 0; 3224 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); 3225 tcg_regset_set_reg(s->reserved_regs, TCG_REG_FP); 3226 tcg_regset_set_reg(s->reserved_regs, TCG_REG_X18); /* platform register */ 3227 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP0); 3228 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); 3229 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2); 3230 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP0); 3231} 3232 3233/* Saving pairs: (X19, X20) .. (X27, X28), (X29(fp), X30(lr)). */ 3234#define PUSH_SIZE ((30 - 19 + 1) * 8) 3235 3236#define FRAME_SIZE \ 3237 ((PUSH_SIZE \ 3238 + TCG_STATIC_CALL_ARGS_SIZE \ 3239 + CPU_TEMP_BUF_NLONGS * sizeof(long) \ 3240 + TCG_TARGET_STACK_ALIGN - 1) \ 3241 & ~(TCG_TARGET_STACK_ALIGN - 1)) 3242 3243/* We're expecting a 2 byte uleb128 encoded value. */ 3244QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); 3245 3246/* We're expecting to use a single ADDI insn. */ 3247QEMU_BUILD_BUG_ON(FRAME_SIZE - PUSH_SIZE > 0xfff); 3248 3249static void tcg_target_qemu_prologue(TCGContext *s) 3250{ 3251 TCGReg r; 3252 3253 tcg_out_bti(s, BTI_C); 3254 3255 /* Push (FP, LR) and allocate space for all saved registers. */ 3256 tcg_out_insn(s, 3314, STP, TCG_REG_FP, TCG_REG_LR, 3257 TCG_REG_SP, -PUSH_SIZE, 1, 1); 3258 3259 /* Set up frame pointer for canonical unwinding. */ 3260 tcg_out_movr_sp(s, TCG_TYPE_I64, TCG_REG_FP, TCG_REG_SP); 3261 3262 /* Store callee-preserved regs x19..x28. */ 3263 for (r = TCG_REG_X19; r <= TCG_REG_X27; r += 2) { 3264 int ofs = (r - TCG_REG_X19 + 2) * 8; 3265 tcg_out_insn(s, 3314, STP, r, r + 1, TCG_REG_SP, ofs, 1, 0); 3266 } 3267 3268 /* Make stack space for TCG locals. */ 3269 tcg_out_insn(s, 3401, SUBI, TCG_TYPE_I64, TCG_REG_SP, TCG_REG_SP, 3270 FRAME_SIZE - PUSH_SIZE); 3271 3272 /* Inform TCG about how to find TCG locals with register, offset, size. */ 3273 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, 3274 CPU_TEMP_BUF_NLONGS * sizeof(long)); 3275 3276 if (!tcg_use_softmmu) { 3277 /* 3278 * Note that XZR cannot be encoded in the address base register slot, 3279 * as that actually encodes SP. Depending on the guest, we may need 3280 * to zero-extend the guest address via the address index register slot, 3281 * therefore we need to load even a zero guest base into a register. 3282 */ 3283 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_GUEST_BASE, guest_base); 3284 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GUEST_BASE); 3285 } 3286 3287 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 3288 tcg_out_insn(s, 3207, BR, tcg_target_call_iarg_regs[1]); 3289 3290 /* 3291 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 3292 * and fall through to the rest of the epilogue. 3293 */ 3294 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 3295 tcg_out_bti(s, BTI_J); 3296 tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_X0, 0); 3297 3298 /* TB epilogue */ 3299 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 3300 tcg_out_bti(s, BTI_J); 3301 3302 /* Remove TCG locals stack space. */ 3303 tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64, TCG_REG_SP, TCG_REG_SP, 3304 FRAME_SIZE - PUSH_SIZE); 3305 3306 /* Restore registers x19..x28. */ 3307 for (r = TCG_REG_X19; r <= TCG_REG_X27; r += 2) { 3308 int ofs = (r - TCG_REG_X19 + 2) * 8; 3309 tcg_out_insn(s, 3314, LDP, r, r + 1, TCG_REG_SP, ofs, 1, 0); 3310 } 3311 3312 /* Pop (FP, LR), restore SP to previous frame. */ 3313 tcg_out_insn(s, 3314, LDP, TCG_REG_FP, TCG_REG_LR, 3314 TCG_REG_SP, PUSH_SIZE, 0, 1); 3315 tcg_out_insn(s, 3207, RET, TCG_REG_LR); 3316} 3317 3318static void tcg_out_tb_start(TCGContext *s) 3319{ 3320 tcg_out_bti(s, BTI_J); 3321} 3322 3323static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 3324{ 3325 int i; 3326 for (i = 0; i < count; ++i) { 3327 p[i] = NOP; 3328 } 3329} 3330 3331typedef struct { 3332 DebugFrameHeader h; 3333 uint8_t fde_def_cfa[4]; 3334 uint8_t fde_reg_ofs[24]; 3335} DebugFrame; 3336 3337#define ELF_HOST_MACHINE EM_AARCH64 3338 3339static const DebugFrame debug_frame = { 3340 .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ 3341 .h.cie.id = -1, 3342 .h.cie.version = 1, 3343 .h.cie.code_align = 1, 3344 .h.cie.data_align = 0x78, /* sleb128 -8 */ 3345 .h.cie.return_column = TCG_REG_LR, 3346 3347 /* Total FDE size does not include the "len" member. */ 3348 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 3349 3350 .fde_def_cfa = { 3351 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ 3352 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 3353 (FRAME_SIZE >> 7) 3354 }, 3355 .fde_reg_ofs = { 3356 0x80 + 28, 1, /* DW_CFA_offset, x28, -8 */ 3357 0x80 + 27, 2, /* DW_CFA_offset, x27, -16 */ 3358 0x80 + 26, 3, /* DW_CFA_offset, x26, -24 */ 3359 0x80 + 25, 4, /* DW_CFA_offset, x25, -32 */ 3360 0x80 + 24, 5, /* DW_CFA_offset, x24, -40 */ 3361 0x80 + 23, 6, /* DW_CFA_offset, x23, -48 */ 3362 0x80 + 22, 7, /* DW_CFA_offset, x22, -56 */ 3363 0x80 + 21, 8, /* DW_CFA_offset, x21, -64 */ 3364 0x80 + 20, 9, /* DW_CFA_offset, x20, -72 */ 3365 0x80 + 19, 10, /* DW_CFA_offset, x1p, -80 */ 3366 0x80 + 30, 11, /* DW_CFA_offset, lr, -88 */ 3367 0x80 + 29, 12, /* DW_CFA_offset, fp, -96 */ 3368 } 3369}; 3370 3371void tcg_register_jit(const void *buf, size_t buf_size) 3372{ 3373 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 3374} 3375