xref: /openbmc/qemu/tcg/aarch64/tcg-target-has.h (revision a363e1e179445102d7940e92d394d6c00c126f13)
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Define target-specific opcode support
4  * Copyright (c) 2013 Huawei Technologies Duesseldorf GmbH
5  */
6 
7 #ifndef TCG_TARGET_HAS_H
8 #define TCG_TARGET_HAS_H
9 
10 #include "host/cpuinfo.h"
11 
12 #define have_lse    (cpuinfo & CPUINFO_LSE)
13 #define have_lse2   (cpuinfo & CPUINFO_LSE2)
14 
15 /* optional instructions */
16 #define TCG_TARGET_HAS_bswap16_i32      1
17 #define TCG_TARGET_HAS_bswap32_i32      1
18 #define TCG_TARGET_HAS_extract2_i32     1
19 #define TCG_TARGET_HAS_add2_i32         1
20 #define TCG_TARGET_HAS_sub2_i32         1
21 #define TCG_TARGET_HAS_extr_i64_i32     0
22 #define TCG_TARGET_HAS_qemu_st8_i32     0
23 
24 #define TCG_TARGET_HAS_bswap16_i64      1
25 #define TCG_TARGET_HAS_bswap32_i64      1
26 #define TCG_TARGET_HAS_bswap64_i64      1
27 #define TCG_TARGET_HAS_extract2_i64     1
28 #define TCG_TARGET_HAS_add2_i64         1
29 #define TCG_TARGET_HAS_sub2_i64         1
30 
31 /*
32  * Without FEAT_LSE2, we must use LDXP+STXP to implement atomic 128-bit load,
33  * which requires writable pages.  We must defer to the helper for user-only,
34  * but in system mode all ram is writable for the host.
35  */
36 #ifdef CONFIG_USER_ONLY
37 #define TCG_TARGET_HAS_qemu_ldst_i128   have_lse2
38 #else
39 #define TCG_TARGET_HAS_qemu_ldst_i128   1
40 #endif
41 
42 #define TCG_TARGET_HAS_tst              1
43 
44 #define TCG_TARGET_HAS_v64              1
45 #define TCG_TARGET_HAS_v128             1
46 #define TCG_TARGET_HAS_v256             0
47 
48 #define TCG_TARGET_HAS_andc_vec         1
49 #define TCG_TARGET_HAS_orc_vec          1
50 #define TCG_TARGET_HAS_nand_vec         0
51 #define TCG_TARGET_HAS_nor_vec          0
52 #define TCG_TARGET_HAS_eqv_vec          0
53 #define TCG_TARGET_HAS_not_vec          1
54 #define TCG_TARGET_HAS_neg_vec          1
55 #define TCG_TARGET_HAS_abs_vec          1
56 #define TCG_TARGET_HAS_roti_vec         0
57 #define TCG_TARGET_HAS_rots_vec         0
58 #define TCG_TARGET_HAS_rotv_vec         0
59 #define TCG_TARGET_HAS_shi_vec          1
60 #define TCG_TARGET_HAS_shs_vec          0
61 #define TCG_TARGET_HAS_shv_vec          1
62 #define TCG_TARGET_HAS_mul_vec          1
63 #define TCG_TARGET_HAS_sat_vec          1
64 #define TCG_TARGET_HAS_minmax_vec       1
65 #define TCG_TARGET_HAS_bitsel_vec       1
66 #define TCG_TARGET_HAS_cmpsel_vec       0
67 #define TCG_TARGET_HAS_tst_vec          1
68 
69 #define TCG_TARGET_extract_valid(type, ofs, len)   1
70 #define TCG_TARGET_sextract_valid(type, ofs, len)  1
71 #define TCG_TARGET_deposit_valid(type, ofs, len)   1
72 
73 #endif
74