1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Define target-specific opcode support 4 * Copyright (c) 2013 Huawei Technologies Duesseldorf GmbH 5 */ 6 7 #ifndef TCG_TARGET_HAS_H 8 #define TCG_TARGET_HAS_H 9 10 #include "host/cpuinfo.h" 11 12 #define have_lse (cpuinfo & CPUINFO_LSE) 13 #define have_lse2 (cpuinfo & CPUINFO_LSE2) 14 15 /* optional instructions */ 16 #define TCG_TARGET_HAS_div_i32 1 17 #define TCG_TARGET_HAS_rem_i32 1 18 #define TCG_TARGET_HAS_bswap16_i32 1 19 #define TCG_TARGET_HAS_bswap32_i32 1 20 #define TCG_TARGET_HAS_not_i32 1 21 #define TCG_TARGET_HAS_rot_i32 1 22 #define TCG_TARGET_HAS_orc_i32 1 23 #define TCG_TARGET_HAS_eqv_i32 1 24 #define TCG_TARGET_HAS_nand_i32 0 25 #define TCG_TARGET_HAS_nor_i32 0 26 #define TCG_TARGET_HAS_clz_i32 1 27 #define TCG_TARGET_HAS_ctz_i32 1 28 #define TCG_TARGET_HAS_ctpop_i32 0 29 #define TCG_TARGET_HAS_extract2_i32 1 30 #define TCG_TARGET_HAS_negsetcond_i32 1 31 #define TCG_TARGET_HAS_add2_i32 1 32 #define TCG_TARGET_HAS_sub2_i32 1 33 #define TCG_TARGET_HAS_mulu2_i32 0 34 #define TCG_TARGET_HAS_muls2_i32 0 35 #define TCG_TARGET_HAS_muluh_i32 0 36 #define TCG_TARGET_HAS_mulsh_i32 0 37 #define TCG_TARGET_HAS_extr_i64_i32 0 38 #define TCG_TARGET_HAS_qemu_st8_i32 0 39 40 #define TCG_TARGET_HAS_div_i64 1 41 #define TCG_TARGET_HAS_rem_i64 1 42 #define TCG_TARGET_HAS_bswap16_i64 1 43 #define TCG_TARGET_HAS_bswap32_i64 1 44 #define TCG_TARGET_HAS_bswap64_i64 1 45 #define TCG_TARGET_HAS_not_i64 1 46 #define TCG_TARGET_HAS_rot_i64 1 47 #define TCG_TARGET_HAS_orc_i64 1 48 #define TCG_TARGET_HAS_eqv_i64 1 49 #define TCG_TARGET_HAS_nand_i64 0 50 #define TCG_TARGET_HAS_nor_i64 0 51 #define TCG_TARGET_HAS_clz_i64 1 52 #define TCG_TARGET_HAS_ctz_i64 1 53 #define TCG_TARGET_HAS_ctpop_i64 0 54 #define TCG_TARGET_HAS_extract2_i64 1 55 #define TCG_TARGET_HAS_negsetcond_i64 1 56 #define TCG_TARGET_HAS_add2_i64 1 57 #define TCG_TARGET_HAS_sub2_i64 1 58 #define TCG_TARGET_HAS_mulu2_i64 0 59 #define TCG_TARGET_HAS_muls2_i64 0 60 #define TCG_TARGET_HAS_muluh_i64 1 61 #define TCG_TARGET_HAS_mulsh_i64 1 62 63 /* 64 * Without FEAT_LSE2, we must use LDXP+STXP to implement atomic 128-bit load, 65 * which requires writable pages. We must defer to the helper for user-only, 66 * but in system mode all ram is writable for the host. 67 */ 68 #ifdef CONFIG_USER_ONLY 69 #define TCG_TARGET_HAS_qemu_ldst_i128 have_lse2 70 #else 71 #define TCG_TARGET_HAS_qemu_ldst_i128 1 72 #endif 73 74 #define TCG_TARGET_HAS_tst 1 75 76 #define TCG_TARGET_HAS_v64 1 77 #define TCG_TARGET_HAS_v128 1 78 #define TCG_TARGET_HAS_v256 0 79 80 #define TCG_TARGET_HAS_andc_vec 1 81 #define TCG_TARGET_HAS_orc_vec 1 82 #define TCG_TARGET_HAS_nand_vec 0 83 #define TCG_TARGET_HAS_nor_vec 0 84 #define TCG_TARGET_HAS_eqv_vec 0 85 #define TCG_TARGET_HAS_not_vec 1 86 #define TCG_TARGET_HAS_neg_vec 1 87 #define TCG_TARGET_HAS_abs_vec 1 88 #define TCG_TARGET_HAS_roti_vec 0 89 #define TCG_TARGET_HAS_rots_vec 0 90 #define TCG_TARGET_HAS_rotv_vec 0 91 #define TCG_TARGET_HAS_shi_vec 1 92 #define TCG_TARGET_HAS_shs_vec 0 93 #define TCG_TARGET_HAS_shv_vec 1 94 #define TCG_TARGET_HAS_mul_vec 1 95 #define TCG_TARGET_HAS_sat_vec 1 96 #define TCG_TARGET_HAS_minmax_vec 1 97 #define TCG_TARGET_HAS_bitsel_vec 1 98 #define TCG_TARGET_HAS_cmpsel_vec 0 99 #define TCG_TARGET_HAS_tst_vec 1 100 101 #define TCG_TARGET_extract_valid(type, ofs, len) 1 102 #define TCG_TARGET_sextract_valid(type, ofs, len) 1 103 #define TCG_TARGET_deposit_valid(type, ofs, len) 1 104 105 #endif 106