1 /* 2 * Xtensa ISA: 3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm 4 * 5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * * Neither the name of the Open Source and Linux Lab nor the 16 * names of its contributors may be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include "qemu/osdep.h" 32 33 #include "cpu.h" 34 #include "exec/exec-all.h" 35 #include "disas/disas.h" 36 #include "tcg-op.h" 37 #include "qemu/log.h" 38 #include "sysemu/sysemu.h" 39 #include "exec/cpu_ldst.h" 40 #include "exec/semihost.h" 41 #include "exec/translator.h" 42 43 #include "exec/helper-proto.h" 44 #include "exec/helper-gen.h" 45 46 #include "trace-tcg.h" 47 #include "exec/log.h" 48 49 50 /* is_jmp field values */ 51 #define DISAS_UPDATE DISAS_TARGET_0 /* cpu state was modified dynamically */ 52 53 typedef struct DisasContext { 54 const XtensaConfig *config; 55 TranslationBlock *tb; 56 uint32_t pc; 57 uint32_t next_pc; 58 int cring; 59 int ring; 60 uint32_t lbeg; 61 uint32_t lend; 62 TCGv_i32 litbase; 63 int is_jmp; 64 int singlestep_enabled; 65 66 bool sar_5bit; 67 bool sar_m32_5bit; 68 bool sar_m32_allocated; 69 TCGv_i32 sar_m32; 70 71 unsigned window; 72 73 bool debug; 74 bool icount; 75 TCGv_i32 next_icount; 76 77 unsigned cpenable; 78 } DisasContext; 79 80 static TCGv_env cpu_env; 81 static TCGv_i32 cpu_pc; 82 static TCGv_i32 cpu_R[16]; 83 static TCGv_i32 cpu_FR[16]; 84 static TCGv_i32 cpu_SR[256]; 85 static TCGv_i32 cpu_UR[256]; 86 87 #include "exec/gen-icount.h" 88 89 typedef struct XtensaReg { 90 const char *name; 91 uint64_t opt_bits; 92 enum { 93 SR_R = 1, 94 SR_W = 2, 95 SR_X = 4, 96 SR_RW = 3, 97 SR_RWX = 7, 98 } access; 99 } XtensaReg; 100 101 #define XTENSA_REG_ACCESS(regname, opt, acc) { \ 102 .name = (regname), \ 103 .opt_bits = XTENSA_OPTION_BIT(opt), \ 104 .access = (acc), \ 105 } 106 107 #define XTENSA_REG(regname, opt) XTENSA_REG_ACCESS(regname, opt, SR_RWX) 108 109 #define XTENSA_REG_BITS_ACCESS(regname, opt, acc) { \ 110 .name = (regname), \ 111 .opt_bits = (opt), \ 112 .access = (acc), \ 113 } 114 115 #define XTENSA_REG_BITS(regname, opt) \ 116 XTENSA_REG_BITS_ACCESS(regname, opt, SR_RWX) 117 118 static const XtensaReg sregnames[256] = { 119 [LBEG] = XTENSA_REG("LBEG", XTENSA_OPTION_LOOP), 120 [LEND] = XTENSA_REG("LEND", XTENSA_OPTION_LOOP), 121 [LCOUNT] = XTENSA_REG("LCOUNT", XTENSA_OPTION_LOOP), 122 [SAR] = XTENSA_REG_BITS("SAR", XTENSA_OPTION_ALL), 123 [BR] = XTENSA_REG("BR", XTENSA_OPTION_BOOLEAN), 124 [LITBASE] = XTENSA_REG("LITBASE", XTENSA_OPTION_EXTENDED_L32R), 125 [SCOMPARE1] = XTENSA_REG("SCOMPARE1", XTENSA_OPTION_CONDITIONAL_STORE), 126 [ACCLO] = XTENSA_REG("ACCLO", XTENSA_OPTION_MAC16), 127 [ACCHI] = XTENSA_REG("ACCHI", XTENSA_OPTION_MAC16), 128 [MR] = XTENSA_REG("MR0", XTENSA_OPTION_MAC16), 129 [MR + 1] = XTENSA_REG("MR1", XTENSA_OPTION_MAC16), 130 [MR + 2] = XTENSA_REG("MR2", XTENSA_OPTION_MAC16), 131 [MR + 3] = XTENSA_REG("MR3", XTENSA_OPTION_MAC16), 132 [WINDOW_BASE] = XTENSA_REG("WINDOW_BASE", XTENSA_OPTION_WINDOWED_REGISTER), 133 [WINDOW_START] = XTENSA_REG("WINDOW_START", 134 XTENSA_OPTION_WINDOWED_REGISTER), 135 [PTEVADDR] = XTENSA_REG("PTEVADDR", XTENSA_OPTION_MMU), 136 [RASID] = XTENSA_REG("RASID", XTENSA_OPTION_MMU), 137 [ITLBCFG] = XTENSA_REG("ITLBCFG", XTENSA_OPTION_MMU), 138 [DTLBCFG] = XTENSA_REG("DTLBCFG", XTENSA_OPTION_MMU), 139 [IBREAKENABLE] = XTENSA_REG("IBREAKENABLE", XTENSA_OPTION_DEBUG), 140 [MEMCTL] = XTENSA_REG_BITS("MEMCTL", XTENSA_OPTION_ALL), 141 [CACHEATTR] = XTENSA_REG("CACHEATTR", XTENSA_OPTION_CACHEATTR), 142 [ATOMCTL] = XTENSA_REG("ATOMCTL", XTENSA_OPTION_ATOMCTL), 143 [IBREAKA] = XTENSA_REG("IBREAKA0", XTENSA_OPTION_DEBUG), 144 [IBREAKA + 1] = XTENSA_REG("IBREAKA1", XTENSA_OPTION_DEBUG), 145 [DBREAKA] = XTENSA_REG("DBREAKA0", XTENSA_OPTION_DEBUG), 146 [DBREAKA + 1] = XTENSA_REG("DBREAKA1", XTENSA_OPTION_DEBUG), 147 [DBREAKC] = XTENSA_REG("DBREAKC0", XTENSA_OPTION_DEBUG), 148 [DBREAKC + 1] = XTENSA_REG("DBREAKC1", XTENSA_OPTION_DEBUG), 149 [CONFIGID0] = XTENSA_REG_BITS_ACCESS("CONFIGID0", XTENSA_OPTION_ALL, SR_R), 150 [EPC1] = XTENSA_REG("EPC1", XTENSA_OPTION_EXCEPTION), 151 [EPC1 + 1] = XTENSA_REG("EPC2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 152 [EPC1 + 2] = XTENSA_REG("EPC3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 153 [EPC1 + 3] = XTENSA_REG("EPC4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 154 [EPC1 + 4] = XTENSA_REG("EPC5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 155 [EPC1 + 5] = XTENSA_REG("EPC6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 156 [EPC1 + 6] = XTENSA_REG("EPC7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 157 [DEPC] = XTENSA_REG("DEPC", XTENSA_OPTION_EXCEPTION), 158 [EPS2] = XTENSA_REG("EPS2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 159 [EPS2 + 1] = XTENSA_REG("EPS3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 160 [EPS2 + 2] = XTENSA_REG("EPS4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 161 [EPS2 + 3] = XTENSA_REG("EPS5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 162 [EPS2 + 4] = XTENSA_REG("EPS6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 163 [EPS2 + 5] = XTENSA_REG("EPS7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 164 [CONFIGID1] = XTENSA_REG_BITS_ACCESS("CONFIGID1", XTENSA_OPTION_ALL, SR_R), 165 [EXCSAVE1] = XTENSA_REG("EXCSAVE1", XTENSA_OPTION_EXCEPTION), 166 [EXCSAVE1 + 1] = XTENSA_REG("EXCSAVE2", 167 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 168 [EXCSAVE1 + 2] = XTENSA_REG("EXCSAVE3", 169 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 170 [EXCSAVE1 + 3] = XTENSA_REG("EXCSAVE4", 171 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 172 [EXCSAVE1 + 4] = XTENSA_REG("EXCSAVE5", 173 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 174 [EXCSAVE1 + 5] = XTENSA_REG("EXCSAVE6", 175 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 176 [EXCSAVE1 + 6] = XTENSA_REG("EXCSAVE7", 177 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 178 [CPENABLE] = XTENSA_REG("CPENABLE", XTENSA_OPTION_COPROCESSOR), 179 [INTSET] = XTENSA_REG_ACCESS("INTSET", XTENSA_OPTION_INTERRUPT, SR_RW), 180 [INTCLEAR] = XTENSA_REG_ACCESS("INTCLEAR", XTENSA_OPTION_INTERRUPT, SR_W), 181 [INTENABLE] = XTENSA_REG("INTENABLE", XTENSA_OPTION_INTERRUPT), 182 [PS] = XTENSA_REG_BITS("PS", XTENSA_OPTION_ALL), 183 [VECBASE] = XTENSA_REG("VECBASE", XTENSA_OPTION_RELOCATABLE_VECTOR), 184 [EXCCAUSE] = XTENSA_REG("EXCCAUSE", XTENSA_OPTION_EXCEPTION), 185 [DEBUGCAUSE] = XTENSA_REG_ACCESS("DEBUGCAUSE", XTENSA_OPTION_DEBUG, SR_R), 186 [CCOUNT] = XTENSA_REG("CCOUNT", XTENSA_OPTION_TIMER_INTERRUPT), 187 [PRID] = XTENSA_REG_ACCESS("PRID", XTENSA_OPTION_PROCESSOR_ID, SR_R), 188 [ICOUNT] = XTENSA_REG("ICOUNT", XTENSA_OPTION_DEBUG), 189 [ICOUNTLEVEL] = XTENSA_REG("ICOUNTLEVEL", XTENSA_OPTION_DEBUG), 190 [EXCVADDR] = XTENSA_REG("EXCVADDR", XTENSA_OPTION_EXCEPTION), 191 [CCOMPARE] = XTENSA_REG("CCOMPARE0", XTENSA_OPTION_TIMER_INTERRUPT), 192 [CCOMPARE + 1] = XTENSA_REG("CCOMPARE1", 193 XTENSA_OPTION_TIMER_INTERRUPT), 194 [CCOMPARE + 2] = XTENSA_REG("CCOMPARE2", 195 XTENSA_OPTION_TIMER_INTERRUPT), 196 [MISC] = XTENSA_REG("MISC0", XTENSA_OPTION_MISC_SR), 197 [MISC + 1] = XTENSA_REG("MISC1", XTENSA_OPTION_MISC_SR), 198 [MISC + 2] = XTENSA_REG("MISC2", XTENSA_OPTION_MISC_SR), 199 [MISC + 3] = XTENSA_REG("MISC3", XTENSA_OPTION_MISC_SR), 200 }; 201 202 static const XtensaReg uregnames[256] = { 203 [THREADPTR] = XTENSA_REG("THREADPTR", XTENSA_OPTION_THREAD_POINTER), 204 [FCR] = XTENSA_REG("FCR", XTENSA_OPTION_FP_COPROCESSOR), 205 [FSR] = XTENSA_REG("FSR", XTENSA_OPTION_FP_COPROCESSOR), 206 }; 207 208 void xtensa_translate_init(void) 209 { 210 static const char * const regnames[] = { 211 "ar0", "ar1", "ar2", "ar3", 212 "ar4", "ar5", "ar6", "ar7", 213 "ar8", "ar9", "ar10", "ar11", 214 "ar12", "ar13", "ar14", "ar15", 215 }; 216 static const char * const fregnames[] = { 217 "f0", "f1", "f2", "f3", 218 "f4", "f5", "f6", "f7", 219 "f8", "f9", "f10", "f11", 220 "f12", "f13", "f14", "f15", 221 }; 222 int i; 223 224 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); 225 tcg_ctx.tcg_env = cpu_env; 226 cpu_pc = tcg_global_mem_new_i32(cpu_env, 227 offsetof(CPUXtensaState, pc), "pc"); 228 229 for (i = 0; i < 16; i++) { 230 cpu_R[i] = tcg_global_mem_new_i32(cpu_env, 231 offsetof(CPUXtensaState, regs[i]), 232 regnames[i]); 233 } 234 235 for (i = 0; i < 16; i++) { 236 cpu_FR[i] = tcg_global_mem_new_i32(cpu_env, 237 offsetof(CPUXtensaState, fregs[i].f32[FP_F32_LOW]), 238 fregnames[i]); 239 } 240 241 for (i = 0; i < 256; ++i) { 242 if (sregnames[i].name) { 243 cpu_SR[i] = tcg_global_mem_new_i32(cpu_env, 244 offsetof(CPUXtensaState, sregs[i]), 245 sregnames[i].name); 246 } 247 } 248 249 for (i = 0; i < 256; ++i) { 250 if (uregnames[i].name) { 251 cpu_UR[i] = tcg_global_mem_new_i32(cpu_env, 252 offsetof(CPUXtensaState, uregs[i]), 253 uregnames[i].name); 254 } 255 } 256 } 257 258 static inline bool option_bits_enabled(DisasContext *dc, uint64_t opt) 259 { 260 return xtensa_option_bits_enabled(dc->config, opt); 261 } 262 263 static inline bool option_enabled(DisasContext *dc, int opt) 264 { 265 return xtensa_option_enabled(dc->config, opt); 266 } 267 268 static void init_litbase(DisasContext *dc) 269 { 270 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) { 271 dc->litbase = tcg_temp_local_new_i32(); 272 tcg_gen_andi_i32(dc->litbase, cpu_SR[LITBASE], 0xfffff000); 273 } 274 } 275 276 static void reset_litbase(DisasContext *dc) 277 { 278 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) { 279 tcg_temp_free(dc->litbase); 280 } 281 } 282 283 static void init_sar_tracker(DisasContext *dc) 284 { 285 dc->sar_5bit = false; 286 dc->sar_m32_5bit = false; 287 dc->sar_m32_allocated = false; 288 } 289 290 static void reset_sar_tracker(DisasContext *dc) 291 { 292 if (dc->sar_m32_allocated) { 293 tcg_temp_free(dc->sar_m32); 294 } 295 } 296 297 static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa) 298 { 299 tcg_gen_andi_i32(cpu_SR[SAR], sa, 0x1f); 300 if (dc->sar_m32_5bit) { 301 tcg_gen_discard_i32(dc->sar_m32); 302 } 303 dc->sar_5bit = true; 304 dc->sar_m32_5bit = false; 305 } 306 307 static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa) 308 { 309 TCGv_i32 tmp = tcg_const_i32(32); 310 if (!dc->sar_m32_allocated) { 311 dc->sar_m32 = tcg_temp_local_new_i32(); 312 dc->sar_m32_allocated = true; 313 } 314 tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f); 315 tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32); 316 dc->sar_5bit = false; 317 dc->sar_m32_5bit = true; 318 tcg_temp_free(tmp); 319 } 320 321 static void gen_exception(DisasContext *dc, int excp) 322 { 323 TCGv_i32 tmp = tcg_const_i32(excp); 324 gen_helper_exception(cpu_env, tmp); 325 tcg_temp_free(tmp); 326 } 327 328 static void gen_exception_cause(DisasContext *dc, uint32_t cause) 329 { 330 TCGv_i32 tpc = tcg_const_i32(dc->pc); 331 TCGv_i32 tcause = tcg_const_i32(cause); 332 gen_helper_exception_cause(cpu_env, tpc, tcause); 333 tcg_temp_free(tpc); 334 tcg_temp_free(tcause); 335 if (cause == ILLEGAL_INSTRUCTION_CAUSE || 336 cause == SYSCALL_CAUSE) { 337 dc->is_jmp = DISAS_UPDATE; 338 } 339 } 340 341 static void gen_exception_cause_vaddr(DisasContext *dc, uint32_t cause, 342 TCGv_i32 vaddr) 343 { 344 TCGv_i32 tpc = tcg_const_i32(dc->pc); 345 TCGv_i32 tcause = tcg_const_i32(cause); 346 gen_helper_exception_cause_vaddr(cpu_env, tpc, tcause, vaddr); 347 tcg_temp_free(tpc); 348 tcg_temp_free(tcause); 349 } 350 351 static void gen_debug_exception(DisasContext *dc, uint32_t cause) 352 { 353 TCGv_i32 tpc = tcg_const_i32(dc->pc); 354 TCGv_i32 tcause = tcg_const_i32(cause); 355 gen_helper_debug_exception(cpu_env, tpc, tcause); 356 tcg_temp_free(tpc); 357 tcg_temp_free(tcause); 358 if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) { 359 dc->is_jmp = DISAS_UPDATE; 360 } 361 } 362 363 static bool gen_check_privilege(DisasContext *dc) 364 { 365 if (dc->cring) { 366 gen_exception_cause(dc, PRIVILEGED_CAUSE); 367 dc->is_jmp = DISAS_UPDATE; 368 return false; 369 } 370 return true; 371 } 372 373 static bool gen_check_cpenable(DisasContext *dc, unsigned cp) 374 { 375 if (option_enabled(dc, XTENSA_OPTION_COPROCESSOR) && 376 !(dc->cpenable & (1 << cp))) { 377 gen_exception_cause(dc, COPROCESSOR0_DISABLED + cp); 378 dc->is_jmp = DISAS_UPDATE; 379 return false; 380 } 381 return true; 382 } 383 384 static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot) 385 { 386 tcg_gen_mov_i32(cpu_pc, dest); 387 if (dc->icount) { 388 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount); 389 } 390 if (dc->singlestep_enabled) { 391 gen_exception(dc, EXCP_DEBUG); 392 } else { 393 if (slot >= 0) { 394 tcg_gen_goto_tb(slot); 395 tcg_gen_exit_tb((uintptr_t)dc->tb + slot); 396 } else { 397 tcg_gen_exit_tb(0); 398 } 399 } 400 dc->is_jmp = DISAS_UPDATE; 401 } 402 403 static void gen_jump(DisasContext *dc, TCGv dest) 404 { 405 gen_jump_slot(dc, dest, -1); 406 } 407 408 static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot) 409 { 410 TCGv_i32 tmp = tcg_const_i32(dest); 411 #ifndef CONFIG_USER_ONLY 412 if (((dc->tb->pc ^ dest) & TARGET_PAGE_MASK) != 0) { 413 slot = -1; 414 } 415 #endif 416 gen_jump_slot(dc, tmp, slot); 417 tcg_temp_free(tmp); 418 } 419 420 static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest, 421 int slot) 422 { 423 TCGv_i32 tcallinc = tcg_const_i32(callinc); 424 425 tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS], 426 tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN); 427 tcg_temp_free(tcallinc); 428 tcg_gen_movi_i32(cpu_R[callinc << 2], 429 (callinc << 30) | (dc->next_pc & 0x3fffffff)); 430 gen_jump_slot(dc, dest, slot); 431 } 432 433 static void gen_callw(DisasContext *dc, int callinc, TCGv_i32 dest) 434 { 435 gen_callw_slot(dc, callinc, dest, -1); 436 } 437 438 static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot) 439 { 440 TCGv_i32 tmp = tcg_const_i32(dest); 441 #ifndef CONFIG_USER_ONLY 442 if (((dc->tb->pc ^ dest) & TARGET_PAGE_MASK) != 0) { 443 slot = -1; 444 } 445 #endif 446 gen_callw_slot(dc, callinc, tmp, slot); 447 tcg_temp_free(tmp); 448 } 449 450 static bool gen_check_loop_end(DisasContext *dc, int slot) 451 { 452 if (option_enabled(dc, XTENSA_OPTION_LOOP) && 453 !(dc->tb->flags & XTENSA_TBFLAG_EXCM) && 454 dc->next_pc == dc->lend) { 455 TCGLabel *label = gen_new_label(); 456 457 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label); 458 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1); 459 gen_jumpi(dc, dc->lbeg, slot); 460 gen_set_label(label); 461 gen_jumpi(dc, dc->next_pc, -1); 462 return true; 463 } 464 return false; 465 } 466 467 static void gen_jumpi_check_loop_end(DisasContext *dc, int slot) 468 { 469 if (!gen_check_loop_end(dc, slot)) { 470 gen_jumpi(dc, dc->next_pc, slot); 471 } 472 } 473 474 static void gen_brcond(DisasContext *dc, TCGCond cond, 475 TCGv_i32 t0, TCGv_i32 t1, uint32_t offset) 476 { 477 TCGLabel *label = gen_new_label(); 478 479 tcg_gen_brcond_i32(cond, t0, t1, label); 480 gen_jumpi_check_loop_end(dc, 0); 481 gen_set_label(label); 482 gen_jumpi(dc, dc->pc + offset, 1); 483 } 484 485 static void gen_brcondi(DisasContext *dc, TCGCond cond, 486 TCGv_i32 t0, uint32_t t1, uint32_t offset) 487 { 488 TCGv_i32 tmp = tcg_const_i32(t1); 489 gen_brcond(dc, cond, t0, tmp, offset); 490 tcg_temp_free(tmp); 491 } 492 493 static bool gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access) 494 { 495 if (!xtensa_option_bits_enabled(dc->config, sregnames[sr].opt_bits)) { 496 if (sregnames[sr].name) { 497 qemu_log_mask(LOG_GUEST_ERROR, "SR %s is not configured\n", sregnames[sr].name); 498 } else { 499 qemu_log_mask(LOG_UNIMP, "SR %d is not implemented\n", sr); 500 } 501 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); 502 return false; 503 } else if (!(sregnames[sr].access & access)) { 504 static const char * const access_text[] = { 505 [SR_R] = "rsr", 506 [SR_W] = "wsr", 507 [SR_X] = "xsr", 508 }; 509 assert(access < ARRAY_SIZE(access_text) && access_text[access]); 510 qemu_log_mask(LOG_GUEST_ERROR, "SR %s is not available for %s\n", sregnames[sr].name, 511 access_text[access]); 512 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); 513 return false; 514 } 515 return true; 516 } 517 518 static bool gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr) 519 { 520 if (dc->tb->cflags & CF_USE_ICOUNT) { 521 gen_io_start(); 522 } 523 gen_helper_update_ccount(cpu_env); 524 tcg_gen_mov_i32(d, cpu_SR[sr]); 525 if (dc->tb->cflags & CF_USE_ICOUNT) { 526 gen_io_end(); 527 return true; 528 } 529 return false; 530 } 531 532 static bool gen_rsr_ptevaddr(DisasContext *dc, TCGv_i32 d, uint32_t sr) 533 { 534 tcg_gen_shri_i32(d, cpu_SR[EXCVADDR], 10); 535 tcg_gen_or_i32(d, d, cpu_SR[sr]); 536 tcg_gen_andi_i32(d, d, 0xfffffffc); 537 return false; 538 } 539 540 static bool gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr) 541 { 542 static bool (* const rsr_handler[256])(DisasContext *dc, 543 TCGv_i32 d, uint32_t sr) = { 544 [CCOUNT] = gen_rsr_ccount, 545 [INTSET] = gen_rsr_ccount, 546 [PTEVADDR] = gen_rsr_ptevaddr, 547 }; 548 549 if (rsr_handler[sr]) { 550 return rsr_handler[sr](dc, d, sr); 551 } else { 552 tcg_gen_mov_i32(d, cpu_SR[sr]); 553 return false; 554 } 555 } 556 557 static bool gen_wsr_lbeg(DisasContext *dc, uint32_t sr, TCGv_i32 s) 558 { 559 gen_helper_wsr_lbeg(cpu_env, s); 560 gen_jumpi_check_loop_end(dc, 0); 561 return false; 562 } 563 564 static bool gen_wsr_lend(DisasContext *dc, uint32_t sr, TCGv_i32 s) 565 { 566 gen_helper_wsr_lend(cpu_env, s); 567 gen_jumpi_check_loop_end(dc, 0); 568 return false; 569 } 570 571 static bool gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s) 572 { 573 tcg_gen_andi_i32(cpu_SR[sr], s, 0x3f); 574 if (dc->sar_m32_5bit) { 575 tcg_gen_discard_i32(dc->sar_m32); 576 } 577 dc->sar_5bit = false; 578 dc->sar_m32_5bit = false; 579 return false; 580 } 581 582 static bool gen_wsr_br(DisasContext *dc, uint32_t sr, TCGv_i32 s) 583 { 584 tcg_gen_andi_i32(cpu_SR[sr], s, 0xffff); 585 return false; 586 } 587 588 static bool gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s) 589 { 590 tcg_gen_andi_i32(cpu_SR[sr], s, 0xfffff001); 591 /* This can change tb->flags, so exit tb */ 592 gen_jumpi_check_loop_end(dc, -1); 593 return true; 594 } 595 596 static bool gen_wsr_acchi(DisasContext *dc, uint32_t sr, TCGv_i32 s) 597 { 598 tcg_gen_ext8s_i32(cpu_SR[sr], s); 599 return false; 600 } 601 602 static bool gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v) 603 { 604 gen_helper_wsr_windowbase(cpu_env, v); 605 /* This can change tb->flags, so exit tb */ 606 gen_jumpi_check_loop_end(dc, -1); 607 return true; 608 } 609 610 static bool gen_wsr_windowstart(DisasContext *dc, uint32_t sr, TCGv_i32 v) 611 { 612 tcg_gen_andi_i32(cpu_SR[sr], v, (1 << dc->config->nareg / 4) - 1); 613 /* This can change tb->flags, so exit tb */ 614 gen_jumpi_check_loop_end(dc, -1); 615 return true; 616 } 617 618 static bool gen_wsr_ptevaddr(DisasContext *dc, uint32_t sr, TCGv_i32 v) 619 { 620 tcg_gen_andi_i32(cpu_SR[sr], v, 0xffc00000); 621 return false; 622 } 623 624 static bool gen_wsr_rasid(DisasContext *dc, uint32_t sr, TCGv_i32 v) 625 { 626 gen_helper_wsr_rasid(cpu_env, v); 627 /* This can change tb->flags, so exit tb */ 628 gen_jumpi_check_loop_end(dc, -1); 629 return true; 630 } 631 632 static bool gen_wsr_tlbcfg(DisasContext *dc, uint32_t sr, TCGv_i32 v) 633 { 634 tcg_gen_andi_i32(cpu_SR[sr], v, 0x01130000); 635 return false; 636 } 637 638 static bool gen_wsr_ibreakenable(DisasContext *dc, uint32_t sr, TCGv_i32 v) 639 { 640 gen_helper_wsr_ibreakenable(cpu_env, v); 641 gen_jumpi_check_loop_end(dc, 0); 642 return true; 643 } 644 645 static bool gen_wsr_memctl(DisasContext *dc, uint32_t sr, TCGv_i32 v) 646 { 647 gen_helper_wsr_memctl(cpu_env, v); 648 return false; 649 } 650 651 static bool gen_wsr_atomctl(DisasContext *dc, uint32_t sr, TCGv_i32 v) 652 { 653 tcg_gen_andi_i32(cpu_SR[sr], v, 0x3f); 654 return false; 655 } 656 657 static bool gen_wsr_ibreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v) 658 { 659 unsigned id = sr - IBREAKA; 660 661 if (id < dc->config->nibreak) { 662 TCGv_i32 tmp = tcg_const_i32(id); 663 gen_helper_wsr_ibreaka(cpu_env, tmp, v); 664 tcg_temp_free(tmp); 665 gen_jumpi_check_loop_end(dc, 0); 666 return true; 667 } 668 return false; 669 } 670 671 static bool gen_wsr_dbreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v) 672 { 673 unsigned id = sr - DBREAKA; 674 675 if (id < dc->config->ndbreak) { 676 TCGv_i32 tmp = tcg_const_i32(id); 677 gen_helper_wsr_dbreaka(cpu_env, tmp, v); 678 tcg_temp_free(tmp); 679 } 680 return false; 681 } 682 683 static bool gen_wsr_dbreakc(DisasContext *dc, uint32_t sr, TCGv_i32 v) 684 { 685 unsigned id = sr - DBREAKC; 686 687 if (id < dc->config->ndbreak) { 688 TCGv_i32 tmp = tcg_const_i32(id); 689 gen_helper_wsr_dbreakc(cpu_env, tmp, v); 690 tcg_temp_free(tmp); 691 } 692 return false; 693 } 694 695 static bool gen_wsr_cpenable(DisasContext *dc, uint32_t sr, TCGv_i32 v) 696 { 697 tcg_gen_andi_i32(cpu_SR[sr], v, 0xff); 698 /* This can change tb->flags, so exit tb */ 699 gen_jumpi_check_loop_end(dc, -1); 700 return true; 701 } 702 703 static void gen_check_interrupts(DisasContext *dc) 704 { 705 if (dc->tb->cflags & CF_USE_ICOUNT) { 706 gen_io_start(); 707 } 708 gen_helper_check_interrupts(cpu_env); 709 if (dc->tb->cflags & CF_USE_ICOUNT) { 710 gen_io_end(); 711 } 712 } 713 714 static bool gen_wsr_intset(DisasContext *dc, uint32_t sr, TCGv_i32 v) 715 { 716 tcg_gen_andi_i32(cpu_SR[sr], v, 717 dc->config->inttype_mask[INTTYPE_SOFTWARE]); 718 gen_check_interrupts(dc); 719 gen_jumpi_check_loop_end(dc, 0); 720 return true; 721 } 722 723 static bool gen_wsr_intclear(DisasContext *dc, uint32_t sr, TCGv_i32 v) 724 { 725 TCGv_i32 tmp = tcg_temp_new_i32(); 726 727 tcg_gen_andi_i32(tmp, v, 728 dc->config->inttype_mask[INTTYPE_EDGE] | 729 dc->config->inttype_mask[INTTYPE_NMI] | 730 dc->config->inttype_mask[INTTYPE_SOFTWARE]); 731 tcg_gen_andc_i32(cpu_SR[INTSET], cpu_SR[INTSET], tmp); 732 tcg_temp_free(tmp); 733 gen_check_interrupts(dc); 734 gen_jumpi_check_loop_end(dc, 0); 735 return true; 736 } 737 738 static bool gen_wsr_intenable(DisasContext *dc, uint32_t sr, TCGv_i32 v) 739 { 740 tcg_gen_mov_i32(cpu_SR[sr], v); 741 gen_check_interrupts(dc); 742 gen_jumpi_check_loop_end(dc, 0); 743 return true; 744 } 745 746 static bool gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v) 747 { 748 uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB | 749 PS_UM | PS_EXCM | PS_INTLEVEL; 750 751 if (option_enabled(dc, XTENSA_OPTION_MMU)) { 752 mask |= PS_RING; 753 } 754 tcg_gen_andi_i32(cpu_SR[sr], v, mask); 755 gen_check_interrupts(dc); 756 /* This can change mmu index and tb->flags, so exit tb */ 757 gen_jumpi_check_loop_end(dc, -1); 758 return true; 759 } 760 761 static bool gen_wsr_ccount(DisasContext *dc, uint32_t sr, TCGv_i32 v) 762 { 763 if (dc->tb->cflags & CF_USE_ICOUNT) { 764 gen_io_start(); 765 } 766 gen_helper_wsr_ccount(cpu_env, v); 767 if (dc->tb->cflags & CF_USE_ICOUNT) { 768 gen_io_end(); 769 gen_jumpi_check_loop_end(dc, 0); 770 return true; 771 } 772 return false; 773 } 774 775 static bool gen_wsr_icount(DisasContext *dc, uint32_t sr, TCGv_i32 v) 776 { 777 if (dc->icount) { 778 tcg_gen_mov_i32(dc->next_icount, v); 779 } else { 780 tcg_gen_mov_i32(cpu_SR[sr], v); 781 } 782 return false; 783 } 784 785 static bool gen_wsr_icountlevel(DisasContext *dc, uint32_t sr, TCGv_i32 v) 786 { 787 tcg_gen_andi_i32(cpu_SR[sr], v, 0xf); 788 /* This can change tb->flags, so exit tb */ 789 gen_jumpi_check_loop_end(dc, -1); 790 return true; 791 } 792 793 static bool gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v) 794 { 795 uint32_t id = sr - CCOMPARE; 796 bool ret = false; 797 798 if (id < dc->config->nccompare) { 799 uint32_t int_bit = 1 << dc->config->timerint[id]; 800 TCGv_i32 tmp = tcg_const_i32(id); 801 802 tcg_gen_mov_i32(cpu_SR[sr], v); 803 tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit); 804 if (dc->tb->cflags & CF_USE_ICOUNT) { 805 gen_io_start(); 806 } 807 gen_helper_update_ccompare(cpu_env, tmp); 808 if (dc->tb->cflags & CF_USE_ICOUNT) { 809 gen_io_end(); 810 gen_jumpi_check_loop_end(dc, 0); 811 ret = true; 812 } 813 tcg_temp_free(tmp); 814 } 815 return ret; 816 } 817 818 static bool gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s) 819 { 820 static bool (* const wsr_handler[256])(DisasContext *dc, 821 uint32_t sr, TCGv_i32 v) = { 822 [LBEG] = gen_wsr_lbeg, 823 [LEND] = gen_wsr_lend, 824 [SAR] = gen_wsr_sar, 825 [BR] = gen_wsr_br, 826 [LITBASE] = gen_wsr_litbase, 827 [ACCHI] = gen_wsr_acchi, 828 [WINDOW_BASE] = gen_wsr_windowbase, 829 [WINDOW_START] = gen_wsr_windowstart, 830 [PTEVADDR] = gen_wsr_ptevaddr, 831 [RASID] = gen_wsr_rasid, 832 [ITLBCFG] = gen_wsr_tlbcfg, 833 [DTLBCFG] = gen_wsr_tlbcfg, 834 [IBREAKENABLE] = gen_wsr_ibreakenable, 835 [MEMCTL] = gen_wsr_memctl, 836 [ATOMCTL] = gen_wsr_atomctl, 837 [IBREAKA] = gen_wsr_ibreaka, 838 [IBREAKA + 1] = gen_wsr_ibreaka, 839 [DBREAKA] = gen_wsr_dbreaka, 840 [DBREAKA + 1] = gen_wsr_dbreaka, 841 [DBREAKC] = gen_wsr_dbreakc, 842 [DBREAKC + 1] = gen_wsr_dbreakc, 843 [CPENABLE] = gen_wsr_cpenable, 844 [INTSET] = gen_wsr_intset, 845 [INTCLEAR] = gen_wsr_intclear, 846 [INTENABLE] = gen_wsr_intenable, 847 [PS] = gen_wsr_ps, 848 [CCOUNT] = gen_wsr_ccount, 849 [ICOUNT] = gen_wsr_icount, 850 [ICOUNTLEVEL] = gen_wsr_icountlevel, 851 [CCOMPARE] = gen_wsr_ccompare, 852 [CCOMPARE + 1] = gen_wsr_ccompare, 853 [CCOMPARE + 2] = gen_wsr_ccompare, 854 }; 855 856 if (wsr_handler[sr]) { 857 return wsr_handler[sr](dc, sr, s); 858 } else { 859 tcg_gen_mov_i32(cpu_SR[sr], s); 860 return false; 861 } 862 } 863 864 static void gen_wur(uint32_t ur, TCGv_i32 s) 865 { 866 switch (ur) { 867 case FCR: 868 gen_helper_wur_fcr(cpu_env, s); 869 break; 870 871 case FSR: 872 tcg_gen_andi_i32(cpu_UR[ur], s, 0xffffff80); 873 break; 874 875 default: 876 tcg_gen_mov_i32(cpu_UR[ur], s); 877 break; 878 } 879 } 880 881 static void gen_load_store_alignment(DisasContext *dc, int shift, 882 TCGv_i32 addr, bool no_hw_alignment) 883 { 884 if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) { 885 tcg_gen_andi_i32(addr, addr, ~0 << shift); 886 } else if (option_enabled(dc, XTENSA_OPTION_HW_ALIGNMENT) && 887 no_hw_alignment) { 888 TCGLabel *label = gen_new_label(); 889 TCGv_i32 tmp = tcg_temp_new_i32(); 890 tcg_gen_andi_i32(tmp, addr, ~(~0 << shift)); 891 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label); 892 gen_exception_cause_vaddr(dc, LOAD_STORE_ALIGNMENT_CAUSE, addr); 893 gen_set_label(label); 894 tcg_temp_free(tmp); 895 } 896 } 897 898 static void gen_waiti(DisasContext *dc, uint32_t imm4) 899 { 900 TCGv_i32 pc = tcg_const_i32(dc->next_pc); 901 TCGv_i32 intlevel = tcg_const_i32(imm4); 902 903 if (dc->tb->cflags & CF_USE_ICOUNT) { 904 gen_io_start(); 905 } 906 gen_helper_waiti(cpu_env, pc, intlevel); 907 if (dc->tb->cflags & CF_USE_ICOUNT) { 908 gen_io_end(); 909 } 910 tcg_temp_free(pc); 911 tcg_temp_free(intlevel); 912 gen_jumpi_check_loop_end(dc, 0); 913 } 914 915 static bool gen_window_check1(DisasContext *dc, unsigned r1) 916 { 917 if (r1 / 4 > dc->window) { 918 TCGv_i32 pc = tcg_const_i32(dc->pc); 919 TCGv_i32 w = tcg_const_i32(r1 / 4); 920 921 gen_helper_window_check(cpu_env, pc, w); 922 dc->is_jmp = DISAS_UPDATE; 923 return false; 924 } 925 return true; 926 } 927 928 static bool gen_window_check2(DisasContext *dc, unsigned r1, unsigned r2) 929 { 930 return gen_window_check1(dc, r1 > r2 ? r1 : r2); 931 } 932 933 static bool gen_window_check3(DisasContext *dc, unsigned r1, unsigned r2, 934 unsigned r3) 935 { 936 return gen_window_check2(dc, r1, r2 > r3 ? r2 : r3); 937 } 938 939 static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned) 940 { 941 TCGv_i32 m = tcg_temp_new_i32(); 942 943 if (hi) { 944 (is_unsigned ? tcg_gen_shri_i32 : tcg_gen_sari_i32)(m, v, 16); 945 } else { 946 (is_unsigned ? tcg_gen_ext16u_i32 : tcg_gen_ext16s_i32)(m, v); 947 } 948 return m; 949 } 950 951 static inline unsigned xtensa_op0_insn_len(unsigned op0) 952 { 953 return op0 >= 8 ? 2 : 3; 954 } 955 956 static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) 957 { 958 #define HAS_OPTION_BITS(opt) do { \ 959 if (!option_bits_enabled(dc, opt)) { \ 960 qemu_log_mask(LOG_GUEST_ERROR, "Option is not enabled %s:%d\n", \ 961 __FILE__, __LINE__); \ 962 goto invalid_opcode; \ 963 } \ 964 } while (0) 965 966 #define HAS_OPTION(opt) HAS_OPTION_BITS(XTENSA_OPTION_BIT(opt)) 967 968 #define TBD() qemu_log_mask(LOG_UNIMP, "TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__) 969 #define RESERVED() do { \ 970 qemu_log_mask(LOG_GUEST_ERROR, "RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \ 971 dc->pc, b0, b1, b2, __FILE__, __LINE__); \ 972 goto invalid_opcode; \ 973 } while (0) 974 975 976 #ifdef TARGET_WORDS_BIGENDIAN 977 #define OP0 (((b0) & 0xf0) >> 4) 978 #define OP1 (((b2) & 0xf0) >> 4) 979 #define OP2 ((b2) & 0xf) 980 #define RRR_R ((b1) & 0xf) 981 #define RRR_S (((b1) & 0xf0) >> 4) 982 #define RRR_T ((b0) & 0xf) 983 #else 984 #define OP0 (((b0) & 0xf)) 985 #define OP1 (((b2) & 0xf)) 986 #define OP2 (((b2) & 0xf0) >> 4) 987 #define RRR_R (((b1) & 0xf0) >> 4) 988 #define RRR_S (((b1) & 0xf)) 989 #define RRR_T (((b0) & 0xf0) >> 4) 990 #endif 991 #define RRR_X ((RRR_R & 0x4) >> 2) 992 #define RRR_Y ((RRR_T & 0x4) >> 2) 993 #define RRR_W (RRR_R & 0x3) 994 995 #define RRRN_R RRR_R 996 #define RRRN_S RRR_S 997 #define RRRN_T RRR_T 998 999 #define RRI4_R RRR_R 1000 #define RRI4_S RRR_S 1001 #define RRI4_T RRR_T 1002 #ifdef TARGET_WORDS_BIGENDIAN 1003 #define RRI4_IMM4 ((b2) & 0xf) 1004 #else 1005 #define RRI4_IMM4 (((b2) & 0xf0) >> 4) 1006 #endif 1007 1008 #define RRI8_R RRR_R 1009 #define RRI8_S RRR_S 1010 #define RRI8_T RRR_T 1011 #define RRI8_IMM8 (b2) 1012 #define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8) 1013 1014 #ifdef TARGET_WORDS_BIGENDIAN 1015 #define RI16_IMM16 (((b1) << 8) | (b2)) 1016 #else 1017 #define RI16_IMM16 (((b2) << 8) | (b1)) 1018 #endif 1019 1020 #ifdef TARGET_WORDS_BIGENDIAN 1021 #define CALL_N (((b0) & 0xc) >> 2) 1022 #define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2)) 1023 #else 1024 #define CALL_N (((b0) & 0x30) >> 4) 1025 #define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10)) 1026 #endif 1027 #define CALL_OFFSET_SE \ 1028 (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET) 1029 1030 #define CALLX_N CALL_N 1031 #ifdef TARGET_WORDS_BIGENDIAN 1032 #define CALLX_M ((b0) & 0x3) 1033 #else 1034 #define CALLX_M (((b0) & 0xc0) >> 6) 1035 #endif 1036 #define CALLX_S RRR_S 1037 1038 #define BRI12_M CALLX_M 1039 #define BRI12_S RRR_S 1040 #ifdef TARGET_WORDS_BIGENDIAN 1041 #define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2)) 1042 #else 1043 #define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4)) 1044 #endif 1045 #define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12) 1046 1047 #define BRI8_M BRI12_M 1048 #define BRI8_R RRI8_R 1049 #define BRI8_S RRI8_S 1050 #define BRI8_IMM8 RRI8_IMM8 1051 #define BRI8_IMM8_SE RRI8_IMM8_SE 1052 1053 #define RSR_SR (b1) 1054 1055 uint8_t b0 = cpu_ldub_code(env, dc->pc); 1056 uint8_t b1 = cpu_ldub_code(env, dc->pc + 1); 1057 uint8_t b2 = 0; 1058 unsigned len = xtensa_op0_insn_len(OP0); 1059 1060 static const uint32_t B4CONST[] = { 1061 0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256 1062 }; 1063 1064 static const uint32_t B4CONSTU[] = { 1065 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256 1066 }; 1067 1068 switch (len) { 1069 case 2: 1070 HAS_OPTION(XTENSA_OPTION_CODE_DENSITY); 1071 break; 1072 1073 case 3: 1074 b2 = cpu_ldub_code(env, dc->pc + 2); 1075 break; 1076 1077 default: 1078 RESERVED(); 1079 } 1080 dc->next_pc = dc->pc + len; 1081 1082 switch (OP0) { 1083 case 0: /*QRST*/ 1084 switch (OP1) { 1085 case 0: /*RST0*/ 1086 switch (OP2) { 1087 case 0: /*ST0*/ 1088 if ((RRR_R & 0xc) == 0x8) { 1089 HAS_OPTION(XTENSA_OPTION_BOOLEAN); 1090 } 1091 1092 switch (RRR_R) { 1093 case 0: /*SNM0*/ 1094 switch (CALLX_M) { 1095 case 0: /*ILL*/ 1096 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); 1097 break; 1098 1099 case 1: /*reserved*/ 1100 RESERVED(); 1101 break; 1102 1103 case 2: /*JR*/ 1104 switch (CALLX_N) { 1105 case 0: /*RET*/ 1106 case 2: /*JX*/ 1107 if (gen_window_check1(dc, CALLX_S)) { 1108 gen_jump(dc, cpu_R[CALLX_S]); 1109 } 1110 break; 1111 1112 case 1: /*RETWw*/ 1113 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); 1114 { 1115 TCGv_i32 tmp = tcg_const_i32(dc->pc); 1116 gen_helper_retw(tmp, cpu_env, tmp); 1117 gen_jump(dc, tmp); 1118 tcg_temp_free(tmp); 1119 } 1120 break; 1121 1122 case 3: /*reserved*/ 1123 RESERVED(); 1124 break; 1125 } 1126 break; 1127 1128 case 3: /*CALLX*/ 1129 if (!gen_window_check2(dc, CALLX_S, CALLX_N << 2)) { 1130 break; 1131 } 1132 switch (CALLX_N) { 1133 case 0: /*CALLX0*/ 1134 { 1135 TCGv_i32 tmp = tcg_temp_new_i32(); 1136 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]); 1137 tcg_gen_movi_i32(cpu_R[0], dc->next_pc); 1138 gen_jump(dc, tmp); 1139 tcg_temp_free(tmp); 1140 } 1141 break; 1142 1143 case 1: /*CALLX4w*/ 1144 case 2: /*CALLX8w*/ 1145 case 3: /*CALLX12w*/ 1146 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); 1147 { 1148 TCGv_i32 tmp = tcg_temp_new_i32(); 1149 1150 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]); 1151 gen_callw(dc, CALLX_N, tmp); 1152 tcg_temp_free(tmp); 1153 } 1154 break; 1155 } 1156 break; 1157 } 1158 break; 1159 1160 case 1: /*MOVSPw*/ 1161 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); 1162 if (gen_window_check2(dc, RRR_T, RRR_S)) { 1163 TCGv_i32 pc = tcg_const_i32(dc->pc); 1164 gen_helper_movsp(cpu_env, pc); 1165 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_R[RRR_S]); 1166 tcg_temp_free(pc); 1167 } 1168 break; 1169 1170 case 2: /*SYNC*/ 1171 switch (RRR_T) { 1172 case 0: /*ISYNC*/ 1173 break; 1174 1175 case 1: /*RSYNC*/ 1176 break; 1177 1178 case 2: /*ESYNC*/ 1179 break; 1180 1181 case 3: /*DSYNC*/ 1182 break; 1183 1184 case 8: /*EXCW*/ 1185 HAS_OPTION(XTENSA_OPTION_EXCEPTION); 1186 break; 1187 1188 case 12: /*MEMW*/ 1189 break; 1190 1191 case 13: /*EXTW*/ 1192 break; 1193 1194 case 15: /*NOP*/ 1195 break; 1196 1197 default: /*reserved*/ 1198 RESERVED(); 1199 break; 1200 } 1201 break; 1202 1203 case 3: /*RFEIx*/ 1204 switch (RRR_T) { 1205 case 0: /*RFETx*/ 1206 HAS_OPTION(XTENSA_OPTION_EXCEPTION); 1207 switch (RRR_S) { 1208 case 0: /*RFEx*/ 1209 if (gen_check_privilege(dc)) { 1210 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); 1211 gen_check_interrupts(dc); 1212 gen_jump(dc, cpu_SR[EPC1]); 1213 } 1214 break; 1215 1216 case 1: /*RFUEx*/ 1217 RESERVED(); 1218 break; 1219 1220 case 2: /*RFDEx*/ 1221 if (gen_check_privilege(dc)) { 1222 gen_jump(dc, cpu_SR[ 1223 dc->config->ndepc ? DEPC : EPC1]); 1224 } 1225 break; 1226 1227 case 4: /*RFWOw*/ 1228 case 5: /*RFWUw*/ 1229 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); 1230 if (gen_check_privilege(dc)) { 1231 TCGv_i32 tmp = tcg_const_i32(1); 1232 1233 tcg_gen_andi_i32( 1234 cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); 1235 tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]); 1236 1237 if (RRR_S == 4) { 1238 tcg_gen_andc_i32(cpu_SR[WINDOW_START], 1239 cpu_SR[WINDOW_START], tmp); 1240 } else { 1241 tcg_gen_or_i32(cpu_SR[WINDOW_START], 1242 cpu_SR[WINDOW_START], tmp); 1243 } 1244 1245 gen_helper_restore_owb(cpu_env); 1246 gen_check_interrupts(dc); 1247 gen_jump(dc, cpu_SR[EPC1]); 1248 1249 tcg_temp_free(tmp); 1250 } 1251 break; 1252 1253 default: /*reserved*/ 1254 RESERVED(); 1255 break; 1256 } 1257 break; 1258 1259 case 1: /*RFIx*/ 1260 HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT); 1261 if (RRR_S >= 2 && RRR_S <= dc->config->nlevel) { 1262 if (gen_check_privilege(dc)) { 1263 tcg_gen_mov_i32(cpu_SR[PS], 1264 cpu_SR[EPS2 + RRR_S - 2]); 1265 gen_check_interrupts(dc); 1266 gen_jump(dc, cpu_SR[EPC1 + RRR_S - 1]); 1267 } 1268 } else { 1269 qemu_log_mask(LOG_GUEST_ERROR, "RFI %d is illegal\n", RRR_S); 1270 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); 1271 } 1272 break; 1273 1274 case 2: /*RFME*/ 1275 TBD(); 1276 break; 1277 1278 default: /*reserved*/ 1279 RESERVED(); 1280 break; 1281 1282 } 1283 break; 1284 1285 case 4: /*BREAKx*/ 1286 HAS_OPTION(XTENSA_OPTION_DEBUG); 1287 if (dc->debug) { 1288 gen_debug_exception(dc, DEBUGCAUSE_BI); 1289 } 1290 break; 1291 1292 case 5: /*SYSCALLx*/ 1293 HAS_OPTION(XTENSA_OPTION_EXCEPTION); 1294 switch (RRR_S) { 1295 case 0: /*SYSCALLx*/ 1296 gen_exception_cause(dc, SYSCALL_CAUSE); 1297 break; 1298 1299 case 1: /*SIMCALL*/ 1300 if (semihosting_enabled()) { 1301 if (gen_check_privilege(dc)) { 1302 gen_helper_simcall(cpu_env); 1303 } 1304 } else { 1305 qemu_log_mask(LOG_GUEST_ERROR, "SIMCALL but semihosting is disabled\n"); 1306 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); 1307 } 1308 break; 1309 1310 default: 1311 RESERVED(); 1312 break; 1313 } 1314 break; 1315 1316 case 6: /*RSILx*/ 1317 HAS_OPTION(XTENSA_OPTION_INTERRUPT); 1318 if (gen_check_privilege(dc) && 1319 gen_window_check1(dc, RRR_T)) { 1320 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_SR[PS]); 1321 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL); 1322 tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], RRR_S); 1323 gen_check_interrupts(dc); 1324 gen_jumpi_check_loop_end(dc, 0); 1325 } 1326 break; 1327 1328 case 7: /*WAITIx*/ 1329 HAS_OPTION(XTENSA_OPTION_INTERRUPT); 1330 if (gen_check_privilege(dc)) { 1331 gen_waiti(dc, RRR_S); 1332 } 1333 break; 1334 1335 case 8: /*ANY4p*/ 1336 case 9: /*ALL4p*/ 1337 case 10: /*ANY8p*/ 1338 case 11: /*ALL8p*/ 1339 HAS_OPTION(XTENSA_OPTION_BOOLEAN); 1340 { 1341 const unsigned shift = (RRR_R & 2) ? 8 : 4; 1342 TCGv_i32 mask = tcg_const_i32( 1343 ((1 << shift) - 1) << RRR_S); 1344 TCGv_i32 tmp = tcg_temp_new_i32(); 1345 1346 tcg_gen_and_i32(tmp, cpu_SR[BR], mask); 1347 if (RRR_R & 1) { /*ALL*/ 1348 tcg_gen_addi_i32(tmp, tmp, 1 << RRR_S); 1349 } else { /*ANY*/ 1350 tcg_gen_add_i32(tmp, tmp, mask); 1351 } 1352 tcg_gen_shri_i32(tmp, tmp, RRR_S + shift); 1353 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], 1354 tmp, RRR_T, 1); 1355 tcg_temp_free(mask); 1356 tcg_temp_free(tmp); 1357 } 1358 break; 1359 1360 default: /*reserved*/ 1361 RESERVED(); 1362 break; 1363 1364 } 1365 break; 1366 1367 case 1: /*AND*/ 1368 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { 1369 tcg_gen_and_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); 1370 } 1371 break; 1372 1373 case 2: /*OR*/ 1374 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { 1375 tcg_gen_or_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); 1376 } 1377 break; 1378 1379 case 3: /*XOR*/ 1380 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { 1381 tcg_gen_xor_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); 1382 } 1383 break; 1384 1385 case 4: /*ST1*/ 1386 switch (RRR_R) { 1387 case 0: /*SSR*/ 1388 if (gen_window_check1(dc, RRR_S)) { 1389 gen_right_shift_sar(dc, cpu_R[RRR_S]); 1390 } 1391 break; 1392 1393 case 1: /*SSL*/ 1394 if (gen_window_check1(dc, RRR_S)) { 1395 gen_left_shift_sar(dc, cpu_R[RRR_S]); 1396 } 1397 break; 1398 1399 case 2: /*SSA8L*/ 1400 if (gen_window_check1(dc, RRR_S)) { 1401 TCGv_i32 tmp = tcg_temp_new_i32(); 1402 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3); 1403 gen_right_shift_sar(dc, tmp); 1404 tcg_temp_free(tmp); 1405 } 1406 break; 1407 1408 case 3: /*SSA8B*/ 1409 if (gen_window_check1(dc, RRR_S)) { 1410 TCGv_i32 tmp = tcg_temp_new_i32(); 1411 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3); 1412 gen_left_shift_sar(dc, tmp); 1413 tcg_temp_free(tmp); 1414 } 1415 break; 1416 1417 case 4: /*SSAI*/ 1418 { 1419 TCGv_i32 tmp = tcg_const_i32( 1420 RRR_S | ((RRR_T & 1) << 4)); 1421 gen_right_shift_sar(dc, tmp); 1422 tcg_temp_free(tmp); 1423 } 1424 break; 1425 1426 case 6: /*RER*/ 1427 HAS_OPTION(XTENSA_OPTION_EXTERN_REGS); 1428 if (gen_check_privilege(dc) && 1429 gen_window_check2(dc, RRR_S, RRR_T)) { 1430 gen_helper_rer(cpu_R[RRR_T], cpu_env, cpu_R[RRR_S]); 1431 } 1432 break; 1433 1434 case 7: /*WER*/ 1435 HAS_OPTION(XTENSA_OPTION_EXTERN_REGS); 1436 if (gen_check_privilege(dc) && 1437 gen_window_check2(dc, RRR_S, RRR_T)) { 1438 gen_helper_wer(cpu_env, cpu_R[RRR_T], cpu_R[RRR_S]); 1439 } 1440 break; 1441 1442 case 8: /*ROTWw*/ 1443 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); 1444 if (gen_check_privilege(dc)) { 1445 TCGv_i32 tmp = tcg_const_i32( 1446 RRR_T | ((RRR_T & 8) ? 0xfffffff0 : 0)); 1447 gen_helper_rotw(cpu_env, tmp); 1448 tcg_temp_free(tmp); 1449 /* This can change tb->flags, so exit tb */ 1450 gen_jumpi_check_loop_end(dc, -1); 1451 } 1452 break; 1453 1454 case 14: /*NSAu*/ 1455 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA); 1456 if (gen_window_check2(dc, RRR_S, RRR_T)) { 1457 tcg_gen_clrsb_i32(cpu_R[RRR_T], cpu_R[RRR_S]); 1458 } 1459 break; 1460 1461 case 15: /*NSAUu*/ 1462 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA); 1463 if (gen_window_check2(dc, RRR_S, RRR_T)) { 1464 tcg_gen_clzi_i32(cpu_R[RRR_T], cpu_R[RRR_S], 32); 1465 } 1466 break; 1467 1468 default: /*reserved*/ 1469 RESERVED(); 1470 break; 1471 } 1472 break; 1473 1474 case 5: /*TLB*/ 1475 HAS_OPTION_BITS( 1476 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU) | 1477 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) | 1478 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION)); 1479 if (gen_check_privilege(dc) && 1480 gen_window_check2(dc, RRR_S, RRR_T)) { 1481 TCGv_i32 dtlb = tcg_const_i32((RRR_R & 8) != 0); 1482 1483 switch (RRR_R & 7) { 1484 case 3: /*RITLB0*/ /*RDTLB0*/ 1485 gen_helper_rtlb0(cpu_R[RRR_T], 1486 cpu_env, cpu_R[RRR_S], dtlb); 1487 break; 1488 1489 case 4: /*IITLB*/ /*IDTLB*/ 1490 gen_helper_itlb(cpu_env, cpu_R[RRR_S], dtlb); 1491 /* This could change memory mapping, so exit tb */ 1492 gen_jumpi_check_loop_end(dc, -1); 1493 break; 1494 1495 case 5: /*PITLB*/ /*PDTLB*/ 1496 tcg_gen_movi_i32(cpu_pc, dc->pc); 1497 gen_helper_ptlb(cpu_R[RRR_T], 1498 cpu_env, cpu_R[RRR_S], dtlb); 1499 break; 1500 1501 case 6: /*WITLB*/ /*WDTLB*/ 1502 gen_helper_wtlb( 1503 cpu_env, cpu_R[RRR_T], cpu_R[RRR_S], dtlb); 1504 /* This could change memory mapping, so exit tb */ 1505 gen_jumpi_check_loop_end(dc, -1); 1506 break; 1507 1508 case 7: /*RITLB1*/ /*RDTLB1*/ 1509 gen_helper_rtlb1(cpu_R[RRR_T], 1510 cpu_env, cpu_R[RRR_S], dtlb); 1511 break; 1512 1513 default: 1514 tcg_temp_free(dtlb); 1515 RESERVED(); 1516 break; 1517 } 1518 tcg_temp_free(dtlb); 1519 } 1520 break; 1521 1522 case 6: /*RT0*/ 1523 if (!gen_window_check2(dc, RRR_R, RRR_T)) { 1524 break; 1525 } 1526 switch (RRR_S) { 1527 case 0: /*NEG*/ 1528 tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]); 1529 break; 1530 1531 case 1: /*ABS*/ 1532 { 1533 TCGv_i32 zero = tcg_const_i32(0); 1534 TCGv_i32 neg = tcg_temp_new_i32(); 1535 1536 tcg_gen_neg_i32(neg, cpu_R[RRR_T]); 1537 tcg_gen_movcond_i32(TCG_COND_GE, cpu_R[RRR_R], 1538 cpu_R[RRR_T], zero, cpu_R[RRR_T], neg); 1539 tcg_temp_free(neg); 1540 tcg_temp_free(zero); 1541 } 1542 break; 1543 1544 default: /*reserved*/ 1545 RESERVED(); 1546 break; 1547 } 1548 break; 1549 1550 case 7: /*reserved*/ 1551 RESERVED(); 1552 break; 1553 1554 case 8: /*ADD*/ 1555 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { 1556 tcg_gen_add_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); 1557 } 1558 break; 1559 1560 case 9: /*ADD**/ 1561 case 10: 1562 case 11: 1563 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { 1564 TCGv_i32 tmp = tcg_temp_new_i32(); 1565 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 8); 1566 tcg_gen_add_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]); 1567 tcg_temp_free(tmp); 1568 } 1569 break; 1570 1571 case 12: /*SUB*/ 1572 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { 1573 tcg_gen_sub_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); 1574 } 1575 break; 1576 1577 case 13: /*SUB**/ 1578 case 14: 1579 case 15: 1580 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { 1581 TCGv_i32 tmp = tcg_temp_new_i32(); 1582 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 12); 1583 tcg_gen_sub_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]); 1584 tcg_temp_free(tmp); 1585 } 1586 break; 1587 } 1588 break; 1589 1590 case 1: /*RST1*/ 1591 switch (OP2) { 1592 case 0: /*SLLI*/ 1593 case 1: 1594 if (gen_window_check2(dc, RRR_R, RRR_S)) { 1595 tcg_gen_shli_i32(cpu_R[RRR_R], cpu_R[RRR_S], 1596 32 - (RRR_T | ((OP2 & 1) << 4))); 1597 } 1598 break; 1599 1600 case 2: /*SRAI*/ 1601 case 3: 1602 if (gen_window_check2(dc, RRR_R, RRR_T)) { 1603 tcg_gen_sari_i32(cpu_R[RRR_R], cpu_R[RRR_T], 1604 RRR_S | ((OP2 & 1) << 4)); 1605 } 1606 break; 1607 1608 case 4: /*SRLI*/ 1609 if (gen_window_check2(dc, RRR_R, RRR_T)) { 1610 tcg_gen_shri_i32(cpu_R[RRR_R], cpu_R[RRR_T], RRR_S); 1611 } 1612 break; 1613 1614 case 6: /*XSR*/ 1615 if (gen_check_sr(dc, RSR_SR, SR_X) && 1616 (RSR_SR < 64 || gen_check_privilege(dc)) && 1617 gen_window_check1(dc, RRR_T)) { 1618 TCGv_i32 tmp = tcg_temp_new_i32(); 1619 bool rsr_end, wsr_end; 1620 1621 tcg_gen_mov_i32(tmp, cpu_R[RRR_T]); 1622 rsr_end = gen_rsr(dc, cpu_R[RRR_T], RSR_SR); 1623 wsr_end = gen_wsr(dc, RSR_SR, tmp); 1624 tcg_temp_free(tmp); 1625 if (rsr_end && !wsr_end) { 1626 gen_jumpi_check_loop_end(dc, 0); 1627 } 1628 } 1629 break; 1630 1631 /* 1632 * Note: 64 bit ops are used here solely because SAR values 1633 * have range 0..63 1634 */ 1635 #define gen_shift_reg(cmd, reg) do { \ 1636 TCGv_i64 tmp = tcg_temp_new_i64(); \ 1637 tcg_gen_extu_i32_i64(tmp, reg); \ 1638 tcg_gen_##cmd##_i64(v, v, tmp); \ 1639 tcg_gen_extrl_i64_i32(cpu_R[RRR_R], v); \ 1640 tcg_temp_free_i64(v); \ 1641 tcg_temp_free_i64(tmp); \ 1642 } while (0) 1643 1644 #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR]) 1645 1646 case 8: /*SRC*/ 1647 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { 1648 TCGv_i64 v = tcg_temp_new_i64(); 1649 tcg_gen_concat_i32_i64(v, cpu_R[RRR_T], cpu_R[RRR_S]); 1650 gen_shift(shr); 1651 } 1652 break; 1653 1654 case 9: /*SRL*/ 1655 if (!gen_window_check2(dc, RRR_R, RRR_T)) { 1656 break; 1657 } 1658 if (dc->sar_5bit) { 1659 tcg_gen_shr_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]); 1660 } else { 1661 TCGv_i64 v = tcg_temp_new_i64(); 1662 tcg_gen_extu_i32_i64(v, cpu_R[RRR_T]); 1663 gen_shift(shr); 1664 } 1665 break; 1666 1667 case 10: /*SLL*/ 1668 if (!gen_window_check2(dc, RRR_R, RRR_S)) { 1669 break; 1670 } 1671 if (dc->sar_m32_5bit) { 1672 tcg_gen_shl_i32(cpu_R[RRR_R], cpu_R[RRR_S], dc->sar_m32); 1673 } else { 1674 TCGv_i64 v = tcg_temp_new_i64(); 1675 TCGv_i32 s = tcg_const_i32(32); 1676 tcg_gen_sub_i32(s, s, cpu_SR[SAR]); 1677 tcg_gen_andi_i32(s, s, 0x3f); 1678 tcg_gen_extu_i32_i64(v, cpu_R[RRR_S]); 1679 gen_shift_reg(shl, s); 1680 tcg_temp_free(s); 1681 } 1682 break; 1683 1684 case 11: /*SRA*/ 1685 if (!gen_window_check2(dc, RRR_R, RRR_T)) { 1686 break; 1687 } 1688 if (dc->sar_5bit) { 1689 tcg_gen_sar_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]); 1690 } else { 1691 TCGv_i64 v = tcg_temp_new_i64(); 1692 tcg_gen_ext_i32_i64(v, cpu_R[RRR_T]); 1693 gen_shift(sar); 1694 } 1695 break; 1696 #undef gen_shift 1697 #undef gen_shift_reg 1698 1699 case 12: /*MUL16U*/ 1700 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL); 1701 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { 1702 TCGv_i32 v1 = tcg_temp_new_i32(); 1703 TCGv_i32 v2 = tcg_temp_new_i32(); 1704 tcg_gen_ext16u_i32(v1, cpu_R[RRR_S]); 1705 tcg_gen_ext16u_i32(v2, cpu_R[RRR_T]); 1706 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2); 1707 tcg_temp_free(v2); 1708 tcg_temp_free(v1); 1709 } 1710 break; 1711 1712 case 13: /*MUL16S*/ 1713 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL); 1714 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { 1715 TCGv_i32 v1 = tcg_temp_new_i32(); 1716 TCGv_i32 v2 = tcg_temp_new_i32(); 1717 tcg_gen_ext16s_i32(v1, cpu_R[RRR_S]); 1718 tcg_gen_ext16s_i32(v2, cpu_R[RRR_T]); 1719 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2); 1720 tcg_temp_free(v2); 1721 tcg_temp_free(v1); 1722 } 1723 break; 1724 1725 default: /*reserved*/ 1726 RESERVED(); 1727 break; 1728 } 1729 break; 1730 1731 case 2: /*RST2*/ 1732 if (OP2 >= 8 && !gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { 1733 break; 1734 } 1735 1736 if (OP2 >= 12) { 1737 HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV); 1738 TCGLabel *label = gen_new_label(); 1739 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0, label); 1740 gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE); 1741 gen_set_label(label); 1742 } 1743 1744 switch (OP2) { 1745 #define BOOLEAN_LOGIC(fn, r, s, t) \ 1746 do { \ 1747 HAS_OPTION(XTENSA_OPTION_BOOLEAN); \ 1748 TCGv_i32 tmp1 = tcg_temp_new_i32(); \ 1749 TCGv_i32 tmp2 = tcg_temp_new_i32(); \ 1750 \ 1751 tcg_gen_shri_i32(tmp1, cpu_SR[BR], s); \ 1752 tcg_gen_shri_i32(tmp2, cpu_SR[BR], t); \ 1753 tcg_gen_##fn##_i32(tmp1, tmp1, tmp2); \ 1754 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, r, 1); \ 1755 tcg_temp_free(tmp1); \ 1756 tcg_temp_free(tmp2); \ 1757 } while (0) 1758 1759 case 0: /*ANDBp*/ 1760 BOOLEAN_LOGIC(and, RRR_R, RRR_S, RRR_T); 1761 break; 1762 1763 case 1: /*ANDBCp*/ 1764 BOOLEAN_LOGIC(andc, RRR_R, RRR_S, RRR_T); 1765 break; 1766 1767 case 2: /*ORBp*/ 1768 BOOLEAN_LOGIC(or, RRR_R, RRR_S, RRR_T); 1769 break; 1770 1771 case 3: /*ORBCp*/ 1772 BOOLEAN_LOGIC(orc, RRR_R, RRR_S, RRR_T); 1773 break; 1774 1775 case 4: /*XORBp*/ 1776 BOOLEAN_LOGIC(xor, RRR_R, RRR_S, RRR_T); 1777 break; 1778 1779 #undef BOOLEAN_LOGIC 1780 1781 case 8: /*MULLi*/ 1782 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL); 1783 tcg_gen_mul_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); 1784 break; 1785 1786 case 10: /*MULUHi*/ 1787 case 11: /*MULSHi*/ 1788 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL_HIGH); 1789 { 1790 TCGv lo = tcg_temp_new(); 1791 1792 if (OP2 == 10) { 1793 tcg_gen_mulu2_i32(lo, cpu_R[RRR_R], 1794 cpu_R[RRR_S], cpu_R[RRR_T]); 1795 } else { 1796 tcg_gen_muls2_i32(lo, cpu_R[RRR_R], 1797 cpu_R[RRR_S], cpu_R[RRR_T]); 1798 } 1799 tcg_temp_free(lo); 1800 } 1801 break; 1802 1803 case 12: /*QUOUi*/ 1804 tcg_gen_divu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); 1805 break; 1806 1807 case 13: /*QUOSi*/ 1808 case 15: /*REMSi*/ 1809 { 1810 TCGLabel *label1 = gen_new_label(); 1811 TCGLabel *label2 = gen_new_label(); 1812 1813 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_S], 0x80000000, 1814 label1); 1815 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0xffffffff, 1816 label1); 1817 tcg_gen_movi_i32(cpu_R[RRR_R], 1818 OP2 == 13 ? 0x80000000 : 0); 1819 tcg_gen_br(label2); 1820 gen_set_label(label1); 1821 if (OP2 == 13) { 1822 tcg_gen_div_i32(cpu_R[RRR_R], 1823 cpu_R[RRR_S], cpu_R[RRR_T]); 1824 } else { 1825 tcg_gen_rem_i32(cpu_R[RRR_R], 1826 cpu_R[RRR_S], cpu_R[RRR_T]); 1827 } 1828 gen_set_label(label2); 1829 } 1830 break; 1831 1832 case 14: /*REMUi*/ 1833 tcg_gen_remu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); 1834 break; 1835 1836 default: /*reserved*/ 1837 RESERVED(); 1838 break; 1839 } 1840 break; 1841 1842 case 3: /*RST3*/ 1843 switch (OP2) { 1844 case 0: /*RSR*/ 1845 if (gen_check_sr(dc, RSR_SR, SR_R) && 1846 (RSR_SR < 64 || gen_check_privilege(dc)) && 1847 gen_window_check1(dc, RRR_T)) { 1848 if (gen_rsr(dc, cpu_R[RRR_T], RSR_SR)) { 1849 gen_jumpi_check_loop_end(dc, 0); 1850 } 1851 } 1852 break; 1853 1854 case 1: /*WSR*/ 1855 if (gen_check_sr(dc, RSR_SR, SR_W) && 1856 (RSR_SR < 64 || gen_check_privilege(dc)) && 1857 gen_window_check1(dc, RRR_T)) { 1858 gen_wsr(dc, RSR_SR, cpu_R[RRR_T]); 1859 } 1860 break; 1861 1862 case 2: /*SEXTu*/ 1863 HAS_OPTION(XTENSA_OPTION_MISC_OP_SEXT); 1864 if (gen_window_check2(dc, RRR_R, RRR_S)) { 1865 int shift = 24 - RRR_T; 1866 1867 if (shift == 24) { 1868 tcg_gen_ext8s_i32(cpu_R[RRR_R], cpu_R[RRR_S]); 1869 } else if (shift == 16) { 1870 tcg_gen_ext16s_i32(cpu_R[RRR_R], cpu_R[RRR_S]); 1871 } else { 1872 TCGv_i32 tmp = tcg_temp_new_i32(); 1873 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], shift); 1874 tcg_gen_sari_i32(cpu_R[RRR_R], tmp, shift); 1875 tcg_temp_free(tmp); 1876 } 1877 } 1878 break; 1879 1880 case 3: /*CLAMPSu*/ 1881 HAS_OPTION(XTENSA_OPTION_MISC_OP_CLAMPS); 1882 if (gen_window_check2(dc, RRR_R, RRR_S)) { 1883 TCGv_i32 tmp1 = tcg_temp_new_i32(); 1884 TCGv_i32 tmp2 = tcg_temp_new_i32(); 1885 TCGv_i32 zero = tcg_const_i32(0); 1886 1887 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 24 - RRR_T); 1888 tcg_gen_xor_i32(tmp2, tmp1, cpu_R[RRR_S]); 1889 tcg_gen_andi_i32(tmp2, tmp2, 0xffffffff << (RRR_T + 7)); 1890 1891 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 31); 1892 tcg_gen_xori_i32(tmp1, tmp1, 0xffffffff >> (25 - RRR_T)); 1893 1894 tcg_gen_movcond_i32(TCG_COND_EQ, cpu_R[RRR_R], tmp2, zero, 1895 cpu_R[RRR_S], tmp1); 1896 tcg_temp_free(tmp1); 1897 tcg_temp_free(tmp2); 1898 tcg_temp_free(zero); 1899 } 1900 break; 1901 1902 case 4: /*MINu*/ 1903 case 5: /*MAXu*/ 1904 case 6: /*MINUu*/ 1905 case 7: /*MAXUu*/ 1906 HAS_OPTION(XTENSA_OPTION_MISC_OP_MINMAX); 1907 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { 1908 static const TCGCond cond[] = { 1909 TCG_COND_LE, 1910 TCG_COND_GE, 1911 TCG_COND_LEU, 1912 TCG_COND_GEU 1913 }; 1914 tcg_gen_movcond_i32(cond[OP2 - 4], cpu_R[RRR_R], 1915 cpu_R[RRR_S], cpu_R[RRR_T], 1916 cpu_R[RRR_S], cpu_R[RRR_T]); 1917 } 1918 break; 1919 1920 case 8: /*MOVEQZ*/ 1921 case 9: /*MOVNEZ*/ 1922 case 10: /*MOVLTZ*/ 1923 case 11: /*MOVGEZ*/ 1924 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { 1925 static const TCGCond cond[] = { 1926 TCG_COND_EQ, 1927 TCG_COND_NE, 1928 TCG_COND_LT, 1929 TCG_COND_GE, 1930 }; 1931 TCGv_i32 zero = tcg_const_i32(0); 1932 1933 tcg_gen_movcond_i32(cond[OP2 - 8], cpu_R[RRR_R], 1934 cpu_R[RRR_T], zero, cpu_R[RRR_S], cpu_R[RRR_R]); 1935 tcg_temp_free(zero); 1936 } 1937 break; 1938 1939 case 12: /*MOVFp*/ 1940 case 13: /*MOVTp*/ 1941 HAS_OPTION(XTENSA_OPTION_BOOLEAN); 1942 if (gen_window_check2(dc, RRR_R, RRR_S)) { 1943 TCGv_i32 zero = tcg_const_i32(0); 1944 TCGv_i32 tmp = tcg_temp_new_i32(); 1945 1946 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T); 1947 tcg_gen_movcond_i32(OP2 & 1 ? TCG_COND_NE : TCG_COND_EQ, 1948 cpu_R[RRR_R], tmp, zero, 1949 cpu_R[RRR_S], cpu_R[RRR_R]); 1950 1951 tcg_temp_free(tmp); 1952 tcg_temp_free(zero); 1953 } 1954 break; 1955 1956 case 14: /*RUR*/ 1957 if (gen_window_check1(dc, RRR_R)) { 1958 int st = (RRR_S << 4) + RRR_T; 1959 if (uregnames[st].name) { 1960 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_UR[st]); 1961 } else { 1962 qemu_log_mask(LOG_UNIMP, "RUR %d not implemented, ", st); 1963 TBD(); 1964 } 1965 } 1966 break; 1967 1968 case 15: /*WUR*/ 1969 if (gen_window_check1(dc, RRR_T)) { 1970 if (uregnames[RSR_SR].name) { 1971 gen_wur(RSR_SR, cpu_R[RRR_T]); 1972 } else { 1973 qemu_log_mask(LOG_UNIMP, "WUR %d not implemented, ", RSR_SR); 1974 TBD(); 1975 } 1976 } 1977 break; 1978 1979 } 1980 break; 1981 1982 case 4: /*EXTUI*/ 1983 case 5: 1984 if (gen_window_check2(dc, RRR_R, RRR_T)) { 1985 int shiftimm = RRR_S | ((OP1 & 1) << 4); 1986 int maskimm = (1 << (OP2 + 1)) - 1; 1987 1988 TCGv_i32 tmp = tcg_temp_new_i32(); 1989 tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm); 1990 tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm); 1991 tcg_temp_free(tmp); 1992 } 1993 break; 1994 1995 case 6: /*CUST0*/ 1996 RESERVED(); 1997 break; 1998 1999 case 7: /*CUST1*/ 2000 RESERVED(); 2001 break; 2002 2003 case 8: /*LSCXp*/ 2004 switch (OP2) { 2005 case 0: /*LSXf*/ 2006 case 1: /*LSXUf*/ 2007 case 4: /*SSXf*/ 2008 case 5: /*SSXUf*/ 2009 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); 2010 if (gen_window_check2(dc, RRR_S, RRR_T) && 2011 gen_check_cpenable(dc, 0)) { 2012 TCGv_i32 addr = tcg_temp_new_i32(); 2013 tcg_gen_add_i32(addr, cpu_R[RRR_S], cpu_R[RRR_T]); 2014 gen_load_store_alignment(dc, 2, addr, false); 2015 if (OP2 & 0x4) { 2016 tcg_gen_qemu_st32(cpu_FR[RRR_R], addr, dc->cring); 2017 } else { 2018 tcg_gen_qemu_ld32u(cpu_FR[RRR_R], addr, dc->cring); 2019 } 2020 if (OP2 & 0x1) { 2021 tcg_gen_mov_i32(cpu_R[RRR_S], addr); 2022 } 2023 tcg_temp_free(addr); 2024 } 2025 break; 2026 2027 default: /*reserved*/ 2028 RESERVED(); 2029 break; 2030 } 2031 break; 2032 2033 case 9: /*LSC4*/ 2034 if (!gen_window_check2(dc, RRR_S, RRR_T)) { 2035 break; 2036 } 2037 switch (OP2) { 2038 case 0: /*L32E*/ 2039 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); 2040 if (gen_check_privilege(dc) && 2041 gen_window_check2(dc, RRR_S, RRR_T)) { 2042 TCGv_i32 addr = tcg_temp_new_i32(); 2043 tcg_gen_addi_i32(addr, cpu_R[RRR_S], 2044 (0xffffffc0 | (RRR_R << 2))); 2045 tcg_gen_qemu_ld32u(cpu_R[RRR_T], addr, dc->ring); 2046 tcg_temp_free(addr); 2047 } 2048 break; 2049 2050 case 4: /*S32E*/ 2051 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); 2052 if (gen_check_privilege(dc) && 2053 gen_window_check2(dc, RRR_S, RRR_T)) { 2054 TCGv_i32 addr = tcg_temp_new_i32(); 2055 tcg_gen_addi_i32(addr, cpu_R[RRR_S], 2056 (0xffffffc0 | (RRR_R << 2))); 2057 tcg_gen_qemu_st32(cpu_R[RRR_T], addr, dc->ring); 2058 tcg_temp_free(addr); 2059 } 2060 break; 2061 2062 case 5: /*S32N*/ 2063 if (gen_window_check2(dc, RRI4_S, RRI4_T)) { 2064 TCGv_i32 addr = tcg_temp_new_i32(); 2065 2066 tcg_gen_addi_i32(addr, cpu_R[RRI4_S], RRI4_IMM4 << 2); 2067 gen_load_store_alignment(dc, 2, addr, false); 2068 tcg_gen_qemu_st32(cpu_R[RRI4_T], addr, dc->cring); 2069 tcg_temp_free(addr); 2070 } 2071 break; 2072 2073 default: 2074 RESERVED(); 2075 break; 2076 } 2077 break; 2078 2079 case 10: /*FP0*/ 2080 /*DEPBITS*/ 2081 if (option_enabled(dc, XTENSA_OPTION_DEPBITS)) { 2082 if (!gen_window_check2(dc, RRR_S, RRR_T)) { 2083 break; 2084 } 2085 tcg_gen_deposit_i32(cpu_R[RRR_T], cpu_R[RRR_T], cpu_R[RRR_S], 2086 OP2, RRR_R + 1); 2087 break; 2088 } 2089 2090 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); 2091 switch (OP2) { 2092 case 0: /*ADD.Sf*/ 2093 if (gen_check_cpenable(dc, 0)) { 2094 gen_helper_add_s(cpu_FR[RRR_R], cpu_env, 2095 cpu_FR[RRR_S], cpu_FR[RRR_T]); 2096 } 2097 break; 2098 2099 case 1: /*SUB.Sf*/ 2100 if (gen_check_cpenable(dc, 0)) { 2101 gen_helper_sub_s(cpu_FR[RRR_R], cpu_env, 2102 cpu_FR[RRR_S], cpu_FR[RRR_T]); 2103 } 2104 break; 2105 2106 case 2: /*MUL.Sf*/ 2107 if (gen_check_cpenable(dc, 0)) { 2108 gen_helper_mul_s(cpu_FR[RRR_R], cpu_env, 2109 cpu_FR[RRR_S], cpu_FR[RRR_T]); 2110 } 2111 break; 2112 2113 case 4: /*MADD.Sf*/ 2114 if (gen_check_cpenable(dc, 0)) { 2115 gen_helper_madd_s(cpu_FR[RRR_R], cpu_env, 2116 cpu_FR[RRR_R], cpu_FR[RRR_S], 2117 cpu_FR[RRR_T]); 2118 } 2119 break; 2120 2121 case 5: /*MSUB.Sf*/ 2122 if (gen_check_cpenable(dc, 0)) { 2123 gen_helper_msub_s(cpu_FR[RRR_R], cpu_env, 2124 cpu_FR[RRR_R], cpu_FR[RRR_S], 2125 cpu_FR[RRR_T]); 2126 } 2127 break; 2128 2129 case 8: /*ROUND.Sf*/ 2130 case 9: /*TRUNC.Sf*/ 2131 case 10: /*FLOOR.Sf*/ 2132 case 11: /*CEIL.Sf*/ 2133 case 14: /*UTRUNC.Sf*/ 2134 if (gen_window_check1(dc, RRR_R) && 2135 gen_check_cpenable(dc, 0)) { 2136 static const unsigned rounding_mode_const[] = { 2137 float_round_nearest_even, 2138 float_round_to_zero, 2139 float_round_down, 2140 float_round_up, 2141 [6] = float_round_to_zero, 2142 }; 2143 TCGv_i32 rounding_mode = tcg_const_i32( 2144 rounding_mode_const[OP2 & 7]); 2145 TCGv_i32 scale = tcg_const_i32(RRR_T); 2146 2147 if (OP2 == 14) { 2148 gen_helper_ftoui(cpu_R[RRR_R], cpu_FR[RRR_S], 2149 rounding_mode, scale); 2150 } else { 2151 gen_helper_ftoi(cpu_R[RRR_R], cpu_FR[RRR_S], 2152 rounding_mode, scale); 2153 } 2154 2155 tcg_temp_free(rounding_mode); 2156 tcg_temp_free(scale); 2157 } 2158 break; 2159 2160 case 12: /*FLOAT.Sf*/ 2161 case 13: /*UFLOAT.Sf*/ 2162 if (gen_window_check1(dc, RRR_S) && 2163 gen_check_cpenable(dc, 0)) { 2164 TCGv_i32 scale = tcg_const_i32(-RRR_T); 2165 2166 if (OP2 == 13) { 2167 gen_helper_uitof(cpu_FR[RRR_R], cpu_env, 2168 cpu_R[RRR_S], scale); 2169 } else { 2170 gen_helper_itof(cpu_FR[RRR_R], cpu_env, 2171 cpu_R[RRR_S], scale); 2172 } 2173 tcg_temp_free(scale); 2174 } 2175 break; 2176 2177 case 15: /*FP1OP*/ 2178 switch (RRR_T) { 2179 case 0: /*MOV.Sf*/ 2180 if (gen_check_cpenable(dc, 0)) { 2181 tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_FR[RRR_S]); 2182 } 2183 break; 2184 2185 case 1: /*ABS.Sf*/ 2186 if (gen_check_cpenable(dc, 0)) { 2187 gen_helper_abs_s(cpu_FR[RRR_R], cpu_FR[RRR_S]); 2188 } 2189 break; 2190 2191 case 4: /*RFRf*/ 2192 if (gen_window_check1(dc, RRR_R) && 2193 gen_check_cpenable(dc, 0)) { 2194 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_FR[RRR_S]); 2195 } 2196 break; 2197 2198 case 5: /*WFRf*/ 2199 if (gen_window_check1(dc, RRR_S) && 2200 gen_check_cpenable(dc, 0)) { 2201 tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_R[RRR_S]); 2202 } 2203 break; 2204 2205 case 6: /*NEG.Sf*/ 2206 if (gen_check_cpenable(dc, 0)) { 2207 gen_helper_neg_s(cpu_FR[RRR_R], cpu_FR[RRR_S]); 2208 } 2209 break; 2210 2211 default: /*reserved*/ 2212 RESERVED(); 2213 break; 2214 } 2215 break; 2216 2217 default: /*reserved*/ 2218 RESERVED(); 2219 break; 2220 } 2221 break; 2222 2223 case 11: /*FP1*/ 2224 /*DEPBITS*/ 2225 if (option_enabled(dc, XTENSA_OPTION_DEPBITS)) { 2226 if (!gen_window_check2(dc, RRR_S, RRR_T)) { 2227 break; 2228 } 2229 tcg_gen_deposit_i32(cpu_R[RRR_T], cpu_R[RRR_T], cpu_R[RRR_S], 2230 OP2 + 16, RRR_R + 1); 2231 break; 2232 } 2233 2234 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); 2235 2236 #define gen_compare(rel, br, a, b) \ 2237 do { \ 2238 if (gen_check_cpenable(dc, 0)) { \ 2239 TCGv_i32 bit = tcg_const_i32(1 << br); \ 2240 \ 2241 gen_helper_##rel(cpu_env, bit, cpu_FR[a], cpu_FR[b]); \ 2242 tcg_temp_free(bit); \ 2243 } \ 2244 } while (0) 2245 2246 switch (OP2) { 2247 case 1: /*UN.Sf*/ 2248 gen_compare(un_s, RRR_R, RRR_S, RRR_T); 2249 break; 2250 2251 case 2: /*OEQ.Sf*/ 2252 gen_compare(oeq_s, RRR_R, RRR_S, RRR_T); 2253 break; 2254 2255 case 3: /*UEQ.Sf*/ 2256 gen_compare(ueq_s, RRR_R, RRR_S, RRR_T); 2257 break; 2258 2259 case 4: /*OLT.Sf*/ 2260 gen_compare(olt_s, RRR_R, RRR_S, RRR_T); 2261 break; 2262 2263 case 5: /*ULT.Sf*/ 2264 gen_compare(ult_s, RRR_R, RRR_S, RRR_T); 2265 break; 2266 2267 case 6: /*OLE.Sf*/ 2268 gen_compare(ole_s, RRR_R, RRR_S, RRR_T); 2269 break; 2270 2271 case 7: /*ULE.Sf*/ 2272 gen_compare(ule_s, RRR_R, RRR_S, RRR_T); 2273 break; 2274 2275 #undef gen_compare 2276 2277 case 8: /*MOVEQZ.Sf*/ 2278 case 9: /*MOVNEZ.Sf*/ 2279 case 10: /*MOVLTZ.Sf*/ 2280 case 11: /*MOVGEZ.Sf*/ 2281 if (gen_window_check1(dc, RRR_T) && 2282 gen_check_cpenable(dc, 0)) { 2283 static const TCGCond cond[] = { 2284 TCG_COND_EQ, 2285 TCG_COND_NE, 2286 TCG_COND_LT, 2287 TCG_COND_GE, 2288 }; 2289 TCGv_i32 zero = tcg_const_i32(0); 2290 2291 tcg_gen_movcond_i32(cond[OP2 - 8], cpu_FR[RRR_R], 2292 cpu_R[RRR_T], zero, cpu_FR[RRR_S], cpu_FR[RRR_R]); 2293 tcg_temp_free(zero); 2294 } 2295 break; 2296 2297 case 12: /*MOVF.Sf*/ 2298 case 13: /*MOVT.Sf*/ 2299 HAS_OPTION(XTENSA_OPTION_BOOLEAN); 2300 if (gen_check_cpenable(dc, 0)) { 2301 TCGv_i32 zero = tcg_const_i32(0); 2302 TCGv_i32 tmp = tcg_temp_new_i32(); 2303 2304 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T); 2305 tcg_gen_movcond_i32(OP2 & 1 ? TCG_COND_NE : TCG_COND_EQ, 2306 cpu_FR[RRR_R], tmp, zero, 2307 cpu_FR[RRR_S], cpu_FR[RRR_R]); 2308 2309 tcg_temp_free(tmp); 2310 tcg_temp_free(zero); 2311 } 2312 break; 2313 2314 default: /*reserved*/ 2315 RESERVED(); 2316 break; 2317 } 2318 break; 2319 2320 default: /*reserved*/ 2321 RESERVED(); 2322 break; 2323 } 2324 break; 2325 2326 case 1: /*L32R*/ 2327 if (gen_window_check1(dc, RRR_T)) { 2328 TCGv_i32 tmp = tcg_const_i32( 2329 ((dc->tb->flags & XTENSA_TBFLAG_LITBASE) ? 2330 0 : ((dc->pc + 3) & ~3)) + 2331 (0xfffc0000 | (RI16_IMM16 << 2))); 2332 2333 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) { 2334 tcg_gen_add_i32(tmp, tmp, dc->litbase); 2335 } 2336 tcg_gen_qemu_ld32u(cpu_R[RRR_T], tmp, dc->cring); 2337 tcg_temp_free(tmp); 2338 } 2339 break; 2340 2341 case 2: /*LSAI*/ 2342 #define gen_load_store(type, shift) do { \ 2343 if (gen_window_check2(dc, RRI8_S, RRI8_T)) { \ 2344 TCGv_i32 addr = tcg_temp_new_i32(); \ 2345 \ 2346 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \ 2347 if (shift) { \ 2348 gen_load_store_alignment(dc, shift, addr, false); \ 2349 } \ 2350 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \ 2351 tcg_temp_free(addr); \ 2352 } \ 2353 } while (0) 2354 2355 switch (RRI8_R) { 2356 case 0: /*L8UI*/ 2357 gen_load_store(ld8u, 0); 2358 break; 2359 2360 case 1: /*L16UI*/ 2361 gen_load_store(ld16u, 1); 2362 break; 2363 2364 case 2: /*L32I*/ 2365 gen_load_store(ld32u, 2); 2366 break; 2367 2368 case 4: /*S8I*/ 2369 gen_load_store(st8, 0); 2370 break; 2371 2372 case 5: /*S16I*/ 2373 gen_load_store(st16, 1); 2374 break; 2375 2376 case 6: /*S32I*/ 2377 gen_load_store(st32, 2); 2378 break; 2379 2380 #define gen_dcache_hit_test(w, shift) do { \ 2381 if (gen_window_check1(dc, RRI##w##_S)) { \ 2382 TCGv_i32 addr = tcg_temp_new_i32(); \ 2383 TCGv_i32 res = tcg_temp_new_i32(); \ 2384 tcg_gen_addi_i32(addr, cpu_R[RRI##w##_S], \ 2385 RRI##w##_IMM##w << shift); \ 2386 tcg_gen_qemu_ld8u(res, addr, dc->cring); \ 2387 tcg_temp_free(addr); \ 2388 tcg_temp_free(res); \ 2389 } \ 2390 } while (0) 2391 2392 #define gen_dcache_hit_test4() gen_dcache_hit_test(4, 4) 2393 #define gen_dcache_hit_test8() gen_dcache_hit_test(8, 2) 2394 2395 case 7: /*CACHEc*/ 2396 if (RRI8_T < 8) { 2397 HAS_OPTION(XTENSA_OPTION_DCACHE); 2398 } 2399 2400 switch (RRI8_T) { 2401 case 0: /*DPFRc*/ 2402 gen_window_check1(dc, RRI8_S); 2403 break; 2404 2405 case 1: /*DPFWc*/ 2406 gen_window_check1(dc, RRI8_S); 2407 break; 2408 2409 case 2: /*DPFROc*/ 2410 gen_window_check1(dc, RRI8_S); 2411 break; 2412 2413 case 3: /*DPFWOc*/ 2414 gen_window_check1(dc, RRI8_S); 2415 break; 2416 2417 case 4: /*DHWBc*/ 2418 gen_dcache_hit_test8(); 2419 break; 2420 2421 case 5: /*DHWBIc*/ 2422 gen_dcache_hit_test8(); 2423 break; 2424 2425 case 6: /*DHIc*/ 2426 if (gen_check_privilege(dc)) { 2427 gen_dcache_hit_test8(); 2428 } 2429 break; 2430 2431 case 7: /*DIIc*/ 2432 if (gen_check_privilege(dc)) { 2433 gen_window_check1(dc, RRI8_S); 2434 } 2435 break; 2436 2437 case 8: /*DCEc*/ 2438 switch (OP1) { 2439 case 0: /*DPFLl*/ 2440 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK); 2441 if (gen_check_privilege(dc)) { 2442 gen_dcache_hit_test4(); 2443 } 2444 break; 2445 2446 case 2: /*DHUl*/ 2447 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK); 2448 if (gen_check_privilege(dc)) { 2449 gen_dcache_hit_test4(); 2450 } 2451 break; 2452 2453 case 3: /*DIUl*/ 2454 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK); 2455 if (gen_check_privilege(dc)) { 2456 gen_window_check1(dc, RRI4_S); 2457 } 2458 break; 2459 2460 case 4: /*DIWBc*/ 2461 HAS_OPTION(XTENSA_OPTION_DCACHE); 2462 if (gen_check_privilege(dc)) { 2463 gen_window_check1(dc, RRI4_S); 2464 } 2465 break; 2466 2467 case 5: /*DIWBIc*/ 2468 HAS_OPTION(XTENSA_OPTION_DCACHE); 2469 if (gen_check_privilege(dc)) { 2470 gen_window_check1(dc, RRI4_S); 2471 } 2472 break; 2473 2474 default: /*reserved*/ 2475 RESERVED(); 2476 break; 2477 2478 } 2479 break; 2480 2481 #undef gen_dcache_hit_test 2482 #undef gen_dcache_hit_test4 2483 #undef gen_dcache_hit_test8 2484 2485 #define gen_icache_hit_test(w, shift) do { \ 2486 if (gen_window_check1(dc, RRI##w##_S)) { \ 2487 TCGv_i32 addr = tcg_temp_new_i32(); \ 2488 tcg_gen_movi_i32(cpu_pc, dc->pc); \ 2489 tcg_gen_addi_i32(addr, cpu_R[RRI##w##_S], \ 2490 RRI##w##_IMM##w << shift); \ 2491 gen_helper_itlb_hit_test(cpu_env, addr); \ 2492 tcg_temp_free(addr); \ 2493 }\ 2494 } while (0) 2495 2496 #define gen_icache_hit_test4() gen_icache_hit_test(4, 4) 2497 #define gen_icache_hit_test8() gen_icache_hit_test(8, 2) 2498 2499 case 12: /*IPFc*/ 2500 HAS_OPTION(XTENSA_OPTION_ICACHE); 2501 gen_window_check1(dc, RRI8_S); 2502 break; 2503 2504 case 13: /*ICEc*/ 2505 switch (OP1) { 2506 case 0: /*IPFLl*/ 2507 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK); 2508 if (gen_check_privilege(dc)) { 2509 gen_icache_hit_test4(); 2510 } 2511 break; 2512 2513 case 2: /*IHUl*/ 2514 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK); 2515 if (gen_check_privilege(dc)) { 2516 gen_icache_hit_test4(); 2517 } 2518 break; 2519 2520 case 3: /*IIUl*/ 2521 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK); 2522 if (gen_check_privilege(dc)) { 2523 gen_window_check1(dc, RRI4_S); 2524 } 2525 break; 2526 2527 default: /*reserved*/ 2528 RESERVED(); 2529 break; 2530 } 2531 break; 2532 2533 case 14: /*IHIc*/ 2534 HAS_OPTION(XTENSA_OPTION_ICACHE); 2535 gen_icache_hit_test8(); 2536 break; 2537 2538 case 15: /*IIIc*/ 2539 HAS_OPTION(XTENSA_OPTION_ICACHE); 2540 if (gen_check_privilege(dc)) { 2541 gen_window_check1(dc, RRI8_S); 2542 } 2543 break; 2544 2545 default: /*reserved*/ 2546 RESERVED(); 2547 break; 2548 } 2549 break; 2550 2551 #undef gen_icache_hit_test 2552 #undef gen_icache_hit_test4 2553 #undef gen_icache_hit_test8 2554 2555 case 9: /*L16SI*/ 2556 gen_load_store(ld16s, 1); 2557 break; 2558 #undef gen_load_store 2559 2560 case 10: /*MOVI*/ 2561 if (gen_window_check1(dc, RRI8_T)) { 2562 tcg_gen_movi_i32(cpu_R[RRI8_T], 2563 RRI8_IMM8 | (RRI8_S << 8) | 2564 ((RRI8_S & 0x8) ? 0xfffff000 : 0)); 2565 } 2566 break; 2567 2568 #define gen_load_store_no_hw_align(type) do { \ 2569 if (gen_window_check2(dc, RRI8_S, RRI8_T)) { \ 2570 TCGv_i32 addr = tcg_temp_local_new_i32(); \ 2571 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); \ 2572 gen_load_store_alignment(dc, 2, addr, true); \ 2573 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \ 2574 tcg_temp_free(addr); \ 2575 } \ 2576 } while (0) 2577 2578 case 11: /*L32AIy*/ 2579 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO); 2580 gen_load_store_no_hw_align(ld32u); /*TODO acquire?*/ 2581 break; 2582 2583 case 12: /*ADDI*/ 2584 if (gen_window_check2(dc, RRI8_S, RRI8_T)) { 2585 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE); 2586 } 2587 break; 2588 2589 case 13: /*ADDMI*/ 2590 if (gen_window_check2(dc, RRI8_S, RRI8_T)) { 2591 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], 2592 RRI8_IMM8_SE << 8); 2593 } 2594 break; 2595 2596 case 14: /*S32C1Iy*/ 2597 HAS_OPTION(XTENSA_OPTION_CONDITIONAL_STORE); 2598 if (gen_window_check2(dc, RRI8_S, RRI8_T)) { 2599 TCGLabel *label = gen_new_label(); 2600 TCGv_i32 tmp = tcg_temp_local_new_i32(); 2601 TCGv_i32 addr = tcg_temp_local_new_i32(); 2602 TCGv_i32 tpc; 2603 2604 tcg_gen_mov_i32(tmp, cpu_R[RRI8_T]); 2605 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); 2606 gen_load_store_alignment(dc, 2, addr, true); 2607 2608 tpc = tcg_const_i32(dc->pc); 2609 gen_helper_check_atomctl(cpu_env, tpc, addr); 2610 tcg_gen_qemu_ld32u(cpu_R[RRI8_T], addr, dc->cring); 2611 tcg_gen_brcond_i32(TCG_COND_NE, cpu_R[RRI8_T], 2612 cpu_SR[SCOMPARE1], label); 2613 2614 tcg_gen_qemu_st32(tmp, addr, dc->cring); 2615 2616 gen_set_label(label); 2617 tcg_temp_free(tpc); 2618 tcg_temp_free(addr); 2619 tcg_temp_free(tmp); 2620 } 2621 break; 2622 2623 case 15: /*S32RIy*/ 2624 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO); 2625 gen_load_store_no_hw_align(st32); /*TODO release?*/ 2626 break; 2627 #undef gen_load_store_no_hw_align 2628 2629 default: /*reserved*/ 2630 RESERVED(); 2631 break; 2632 } 2633 break; 2634 2635 case 3: /*LSCIp*/ 2636 switch (RRI8_R) { 2637 case 0: /*LSIf*/ 2638 case 4: /*SSIf*/ 2639 case 8: /*LSIUf*/ 2640 case 12: /*SSIUf*/ 2641 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); 2642 if (gen_window_check1(dc, RRI8_S) && 2643 gen_check_cpenable(dc, 0)) { 2644 TCGv_i32 addr = tcg_temp_new_i32(); 2645 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); 2646 gen_load_store_alignment(dc, 2, addr, false); 2647 if (RRI8_R & 0x4) { 2648 tcg_gen_qemu_st32(cpu_FR[RRI8_T], addr, dc->cring); 2649 } else { 2650 tcg_gen_qemu_ld32u(cpu_FR[RRI8_T], addr, dc->cring); 2651 } 2652 if (RRI8_R & 0x8) { 2653 tcg_gen_mov_i32(cpu_R[RRI8_S], addr); 2654 } 2655 tcg_temp_free(addr); 2656 } 2657 break; 2658 2659 default: /*reserved*/ 2660 RESERVED(); 2661 break; 2662 } 2663 break; 2664 2665 case 4: /*MAC16d*/ 2666 HAS_OPTION(XTENSA_OPTION_MAC16); 2667 { 2668 enum { 2669 MAC16_UMUL = 0x0, 2670 MAC16_MUL = 0x4, 2671 MAC16_MULA = 0x8, 2672 MAC16_MULS = 0xc, 2673 MAC16_NONE = 0xf, 2674 } op = OP1 & 0xc; 2675 bool is_m1_sr = (OP2 & 0x3) == 2; 2676 bool is_m2_sr = (OP2 & 0xc) == 0; 2677 uint32_t ld_offset = 0; 2678 2679 if (OP2 > 9) { 2680 RESERVED(); 2681 } 2682 2683 switch (OP2 & 2) { 2684 case 0: /*MACI?/MACC?*/ 2685 is_m1_sr = true; 2686 ld_offset = (OP2 & 1) ? -4 : 4; 2687 2688 if (OP2 >= 8) { /*MACI/MACC*/ 2689 if (OP1 == 0) { /*LDINC/LDDEC*/ 2690 op = MAC16_NONE; 2691 } else { 2692 RESERVED(); 2693 } 2694 } else if (op != MAC16_MULA) { /*MULA.*.*.LDINC/LDDEC*/ 2695 RESERVED(); 2696 } 2697 break; 2698 2699 case 2: /*MACD?/MACA?*/ 2700 if (op == MAC16_UMUL && OP2 != 7) { /*UMUL only in MACAA*/ 2701 RESERVED(); 2702 } 2703 break; 2704 } 2705 2706 if (op != MAC16_NONE) { 2707 if (!is_m1_sr && !gen_window_check1(dc, RRR_S)) { 2708 break; 2709 } 2710 if (!is_m2_sr && !gen_window_check1(dc, RRR_T)) { 2711 break; 2712 } 2713 } 2714 2715 if (ld_offset && !gen_window_check1(dc, RRR_S)) { 2716 break; 2717 } 2718 2719 { 2720 TCGv_i32 vaddr = tcg_temp_new_i32(); 2721 TCGv_i32 mem32 = tcg_temp_new_i32(); 2722 2723 if (ld_offset) { 2724 tcg_gen_addi_i32(vaddr, cpu_R[RRR_S], ld_offset); 2725 gen_load_store_alignment(dc, 2, vaddr, false); 2726 tcg_gen_qemu_ld32u(mem32, vaddr, dc->cring); 2727 } 2728 if (op != MAC16_NONE) { 2729 TCGv_i32 m1 = gen_mac16_m( 2730 is_m1_sr ? cpu_SR[MR + RRR_X] : cpu_R[RRR_S], 2731 OP1 & 1, op == MAC16_UMUL); 2732 TCGv_i32 m2 = gen_mac16_m( 2733 is_m2_sr ? cpu_SR[MR + 2 + RRR_Y] : cpu_R[RRR_T], 2734 OP1 & 2, op == MAC16_UMUL); 2735 2736 if (op == MAC16_MUL || op == MAC16_UMUL) { 2737 tcg_gen_mul_i32(cpu_SR[ACCLO], m1, m2); 2738 if (op == MAC16_UMUL) { 2739 tcg_gen_movi_i32(cpu_SR[ACCHI], 0); 2740 } else { 2741 tcg_gen_sari_i32(cpu_SR[ACCHI], cpu_SR[ACCLO], 31); 2742 } 2743 } else { 2744 TCGv_i32 lo = tcg_temp_new_i32(); 2745 TCGv_i32 hi = tcg_temp_new_i32(); 2746 2747 tcg_gen_mul_i32(lo, m1, m2); 2748 tcg_gen_sari_i32(hi, lo, 31); 2749 if (op == MAC16_MULA) { 2750 tcg_gen_add2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI], 2751 cpu_SR[ACCLO], cpu_SR[ACCHI], 2752 lo, hi); 2753 } else { 2754 tcg_gen_sub2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI], 2755 cpu_SR[ACCLO], cpu_SR[ACCHI], 2756 lo, hi); 2757 } 2758 tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]); 2759 2760 tcg_temp_free_i32(lo); 2761 tcg_temp_free_i32(hi); 2762 } 2763 tcg_temp_free(m1); 2764 tcg_temp_free(m2); 2765 } 2766 if (ld_offset) { 2767 tcg_gen_mov_i32(cpu_R[RRR_S], vaddr); 2768 tcg_gen_mov_i32(cpu_SR[MR + RRR_W], mem32); 2769 } 2770 tcg_temp_free(vaddr); 2771 tcg_temp_free(mem32); 2772 } 2773 } 2774 break; 2775 2776 case 5: /*CALLN*/ 2777 switch (CALL_N) { 2778 case 0: /*CALL0*/ 2779 tcg_gen_movi_i32(cpu_R[0], dc->next_pc); 2780 gen_jumpi(dc, (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0); 2781 break; 2782 2783 case 1: /*CALL4w*/ 2784 case 2: /*CALL8w*/ 2785 case 3: /*CALL12w*/ 2786 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); 2787 if (gen_window_check1(dc, CALL_N << 2)) { 2788 gen_callwi(dc, CALL_N, 2789 (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0); 2790 } 2791 break; 2792 } 2793 break; 2794 2795 case 6: /*SI*/ 2796 switch (CALL_N) { 2797 case 0: /*J*/ 2798 gen_jumpi(dc, dc->pc + 4 + CALL_OFFSET_SE, 0); 2799 break; 2800 2801 case 1: /*BZ*/ 2802 if (gen_window_check1(dc, BRI12_S)) { 2803 static const TCGCond cond[] = { 2804 TCG_COND_EQ, /*BEQZ*/ 2805 TCG_COND_NE, /*BNEZ*/ 2806 TCG_COND_LT, /*BLTZ*/ 2807 TCG_COND_GE, /*BGEZ*/ 2808 }; 2809 2810 gen_brcondi(dc, cond[BRI12_M & 3], cpu_R[BRI12_S], 0, 2811 4 + BRI12_IMM12_SE); 2812 } 2813 break; 2814 2815 case 2: /*BI0*/ 2816 if (gen_window_check1(dc, BRI8_S)) { 2817 static const TCGCond cond[] = { 2818 TCG_COND_EQ, /*BEQI*/ 2819 TCG_COND_NE, /*BNEI*/ 2820 TCG_COND_LT, /*BLTI*/ 2821 TCG_COND_GE, /*BGEI*/ 2822 }; 2823 2824 gen_brcondi(dc, cond[BRI8_M & 3], 2825 cpu_R[BRI8_S], B4CONST[BRI8_R], 4 + BRI8_IMM8_SE); 2826 } 2827 break; 2828 2829 case 3: /*BI1*/ 2830 switch (BRI8_M) { 2831 case 0: /*ENTRYw*/ 2832 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); 2833 { 2834 TCGv_i32 pc = tcg_const_i32(dc->pc); 2835 TCGv_i32 s = tcg_const_i32(BRI12_S); 2836 TCGv_i32 imm = tcg_const_i32(BRI12_IMM12); 2837 gen_helper_entry(cpu_env, pc, s, imm); 2838 tcg_temp_free(imm); 2839 tcg_temp_free(s); 2840 tcg_temp_free(pc); 2841 /* This can change tb->flags, so exit tb */ 2842 gen_jumpi_check_loop_end(dc, -1); 2843 } 2844 break; 2845 2846 case 1: /*B1*/ 2847 switch (BRI8_R) { 2848 case 0: /*BFp*/ 2849 case 1: /*BTp*/ 2850 HAS_OPTION(XTENSA_OPTION_BOOLEAN); 2851 { 2852 TCGv_i32 tmp = tcg_temp_new_i32(); 2853 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRI8_S); 2854 gen_brcondi(dc, 2855 BRI8_R == 1 ? TCG_COND_NE : TCG_COND_EQ, 2856 tmp, 0, 4 + RRI8_IMM8_SE); 2857 tcg_temp_free(tmp); 2858 } 2859 break; 2860 2861 case 8: /*LOOP*/ 2862 case 9: /*LOOPNEZ*/ 2863 case 10: /*LOOPGTZ*/ 2864 HAS_OPTION(XTENSA_OPTION_LOOP); 2865 if (gen_window_check1(dc, RRI8_S)) { 2866 uint32_t lend = dc->pc + RRI8_IMM8 + 4; 2867 TCGv_i32 tmp = tcg_const_i32(lend); 2868 2869 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[RRI8_S], 1); 2870 tcg_gen_movi_i32(cpu_SR[LBEG], dc->next_pc); 2871 gen_helper_wsr_lend(cpu_env, tmp); 2872 tcg_temp_free(tmp); 2873 2874 if (BRI8_R > 8) { 2875 TCGLabel *label = gen_new_label(); 2876 tcg_gen_brcondi_i32( 2877 BRI8_R == 9 ? TCG_COND_NE : TCG_COND_GT, 2878 cpu_R[RRI8_S], 0, label); 2879 gen_jumpi(dc, lend, 1); 2880 gen_set_label(label); 2881 } 2882 2883 gen_jumpi(dc, dc->next_pc, 0); 2884 } 2885 break; 2886 2887 default: /*reserved*/ 2888 RESERVED(); 2889 break; 2890 2891 } 2892 break; 2893 2894 case 2: /*BLTUI*/ 2895 case 3: /*BGEUI*/ 2896 if (gen_window_check1(dc, BRI8_S)) { 2897 gen_brcondi(dc, BRI8_M == 2 ? TCG_COND_LTU : TCG_COND_GEU, 2898 cpu_R[BRI8_S], B4CONSTU[BRI8_R], 2899 4 + BRI8_IMM8_SE); 2900 } 2901 break; 2902 } 2903 break; 2904 2905 } 2906 break; 2907 2908 case 7: /*B*/ 2909 { 2910 TCGCond eq_ne = (RRI8_R & 8) ? TCG_COND_NE : TCG_COND_EQ; 2911 2912 switch (RRI8_R & 7) { 2913 case 0: /*BNONE*/ /*BANY*/ 2914 if (gen_window_check2(dc, RRI8_S, RRI8_T)) { 2915 TCGv_i32 tmp = tcg_temp_new_i32(); 2916 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]); 2917 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE); 2918 tcg_temp_free(tmp); 2919 } 2920 break; 2921 2922 case 1: /*BEQ*/ /*BNE*/ 2923 case 2: /*BLT*/ /*BGE*/ 2924 case 3: /*BLTU*/ /*BGEU*/ 2925 if (gen_window_check2(dc, RRI8_S, RRI8_T)) { 2926 static const TCGCond cond[] = { 2927 [1] = TCG_COND_EQ, 2928 [2] = TCG_COND_LT, 2929 [3] = TCG_COND_LTU, 2930 [9] = TCG_COND_NE, 2931 [10] = TCG_COND_GE, 2932 [11] = TCG_COND_GEU, 2933 }; 2934 gen_brcond(dc, cond[RRI8_R], cpu_R[RRI8_S], cpu_R[RRI8_T], 2935 4 + RRI8_IMM8_SE); 2936 } 2937 break; 2938 2939 case 4: /*BALL*/ /*BNALL*/ 2940 if (gen_window_check2(dc, RRI8_S, RRI8_T)) { 2941 TCGv_i32 tmp = tcg_temp_new_i32(); 2942 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]); 2943 gen_brcond(dc, eq_ne, tmp, cpu_R[RRI8_T], 2944 4 + RRI8_IMM8_SE); 2945 tcg_temp_free(tmp); 2946 } 2947 break; 2948 2949 case 5: /*BBC*/ /*BBS*/ 2950 if (gen_window_check2(dc, RRI8_S, RRI8_T)) { 2951 #ifdef TARGET_WORDS_BIGENDIAN 2952 TCGv_i32 bit = tcg_const_i32(0x80000000); 2953 #else 2954 TCGv_i32 bit = tcg_const_i32(0x00000001); 2955 #endif 2956 TCGv_i32 tmp = tcg_temp_new_i32(); 2957 tcg_gen_andi_i32(tmp, cpu_R[RRI8_T], 0x1f); 2958 #ifdef TARGET_WORDS_BIGENDIAN 2959 tcg_gen_shr_i32(bit, bit, tmp); 2960 #else 2961 tcg_gen_shl_i32(bit, bit, tmp); 2962 #endif 2963 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], bit); 2964 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE); 2965 tcg_temp_free(tmp); 2966 tcg_temp_free(bit); 2967 } 2968 break; 2969 2970 case 6: /*BBCI*/ /*BBSI*/ 2971 case 7: 2972 if (gen_window_check1(dc, RRI8_S)) { 2973 TCGv_i32 tmp = tcg_temp_new_i32(); 2974 tcg_gen_andi_i32(tmp, cpu_R[RRI8_S], 2975 #ifdef TARGET_WORDS_BIGENDIAN 2976 0x80000000 >> (((RRI8_R & 1) << 4) | RRI8_T)); 2977 #else 2978 0x00000001 << (((RRI8_R & 1) << 4) | RRI8_T)); 2979 #endif 2980 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE); 2981 tcg_temp_free(tmp); 2982 } 2983 break; 2984 2985 } 2986 } 2987 break; 2988 2989 #define gen_narrow_load_store(type) do { \ 2990 if (gen_window_check2(dc, RRRN_S, RRRN_T)) { \ 2991 TCGv_i32 addr = tcg_temp_new_i32(); \ 2992 tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \ 2993 gen_load_store_alignment(dc, 2, addr, false); \ 2994 tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, dc->cring); \ 2995 tcg_temp_free(addr); \ 2996 } \ 2997 } while (0) 2998 2999 case 8: /*L32I.Nn*/ 3000 gen_narrow_load_store(ld32u); 3001 break; 3002 3003 case 9: /*S32I.Nn*/ 3004 gen_narrow_load_store(st32); 3005 break; 3006 #undef gen_narrow_load_store 3007 3008 case 10: /*ADD.Nn*/ 3009 if (gen_window_check3(dc, RRRN_R, RRRN_S, RRRN_T)) { 3010 tcg_gen_add_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], cpu_R[RRRN_T]); 3011 } 3012 break; 3013 3014 case 11: /*ADDI.Nn*/ 3015 if (gen_window_check2(dc, RRRN_R, RRRN_S)) { 3016 tcg_gen_addi_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], 3017 RRRN_T ? RRRN_T : -1); 3018 } 3019 break; 3020 3021 case 12: /*ST2n*/ 3022 if (!gen_window_check1(dc, RRRN_S)) { 3023 break; 3024 } 3025 if (RRRN_T < 8) { /*MOVI.Nn*/ 3026 tcg_gen_movi_i32(cpu_R[RRRN_S], 3027 RRRN_R | (RRRN_T << 4) | 3028 ((RRRN_T & 6) == 6 ? 0xffffff80 : 0)); 3029 } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/ 3030 TCGCond eq_ne = (RRRN_T & 4) ? TCG_COND_NE : TCG_COND_EQ; 3031 3032 gen_brcondi(dc, eq_ne, cpu_R[RRRN_S], 0, 3033 4 + (RRRN_R | ((RRRN_T & 3) << 4))); 3034 } 3035 break; 3036 3037 case 13: /*ST3n*/ 3038 switch (RRRN_R) { 3039 case 0: /*MOV.Nn*/ 3040 if (gen_window_check2(dc, RRRN_S, RRRN_T)) { 3041 tcg_gen_mov_i32(cpu_R[RRRN_T], cpu_R[RRRN_S]); 3042 } 3043 break; 3044 3045 case 15: /*S3*/ 3046 switch (RRRN_T) { 3047 case 0: /*RET.Nn*/ 3048 gen_jump(dc, cpu_R[0]); 3049 break; 3050 3051 case 1: /*RETW.Nn*/ 3052 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); 3053 { 3054 TCGv_i32 tmp = tcg_const_i32(dc->pc); 3055 gen_helper_retw(tmp, cpu_env, tmp); 3056 gen_jump(dc, tmp); 3057 tcg_temp_free(tmp); 3058 } 3059 break; 3060 3061 case 2: /*BREAK.Nn*/ 3062 HAS_OPTION(XTENSA_OPTION_DEBUG); 3063 if (dc->debug) { 3064 gen_debug_exception(dc, DEBUGCAUSE_BN); 3065 } 3066 break; 3067 3068 case 3: /*NOP.Nn*/ 3069 break; 3070 3071 case 6: /*ILL.Nn*/ 3072 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); 3073 break; 3074 3075 default: /*reserved*/ 3076 RESERVED(); 3077 break; 3078 } 3079 break; 3080 3081 default: /*reserved*/ 3082 RESERVED(); 3083 break; 3084 } 3085 break; 3086 3087 default: /*reserved*/ 3088 RESERVED(); 3089 break; 3090 } 3091 3092 if (dc->is_jmp == DISAS_NEXT) { 3093 gen_check_loop_end(dc, 0); 3094 } 3095 dc->pc = dc->next_pc; 3096 3097 return; 3098 3099 invalid_opcode: 3100 qemu_log_mask(LOG_GUEST_ERROR, "INVALID(pc = %08x)\n", dc->pc); 3101 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); 3102 #undef HAS_OPTION 3103 } 3104 3105 static inline unsigned xtensa_insn_len(CPUXtensaState *env, DisasContext *dc) 3106 { 3107 uint8_t b0 = cpu_ldub_code(env, dc->pc); 3108 return xtensa_op0_insn_len(OP0); 3109 } 3110 3111 static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc) 3112 { 3113 unsigned i; 3114 3115 for (i = 0; i < dc->config->nibreak; ++i) { 3116 if ((env->sregs[IBREAKENABLE] & (1 << i)) && 3117 env->sregs[IBREAKA + i] == dc->pc) { 3118 gen_debug_exception(dc, DEBUGCAUSE_IB); 3119 break; 3120 } 3121 } 3122 } 3123 3124 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) 3125 { 3126 CPUXtensaState *env = cs->env_ptr; 3127 DisasContext dc; 3128 int insn_count = 0; 3129 int max_insns = tb->cflags & CF_COUNT_MASK; 3130 uint32_t pc_start = tb->pc; 3131 uint32_t next_page_start = 3132 (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; 3133 3134 if (max_insns == 0) { 3135 max_insns = CF_COUNT_MASK; 3136 } 3137 if (max_insns > TCG_MAX_INSNS) { 3138 max_insns = TCG_MAX_INSNS; 3139 } 3140 3141 dc.config = env->config; 3142 dc.singlestep_enabled = cs->singlestep_enabled; 3143 dc.tb = tb; 3144 dc.pc = pc_start; 3145 dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK; 3146 dc.cring = (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc.ring; 3147 dc.lbeg = env->sregs[LBEG]; 3148 dc.lend = env->sregs[LEND]; 3149 dc.is_jmp = DISAS_NEXT; 3150 dc.debug = tb->flags & XTENSA_TBFLAG_DEBUG; 3151 dc.icount = tb->flags & XTENSA_TBFLAG_ICOUNT; 3152 dc.cpenable = (tb->flags & XTENSA_TBFLAG_CPENABLE_MASK) >> 3153 XTENSA_TBFLAG_CPENABLE_SHIFT; 3154 dc.window = ((tb->flags & XTENSA_TBFLAG_WINDOW_MASK) >> 3155 XTENSA_TBFLAG_WINDOW_SHIFT); 3156 3157 init_litbase(&dc); 3158 init_sar_tracker(&dc); 3159 if (dc.icount) { 3160 dc.next_icount = tcg_temp_local_new_i32(); 3161 } 3162 3163 gen_tb_start(tb); 3164 3165 if ((tb->cflags & CF_USE_ICOUNT) && 3166 (tb->flags & XTENSA_TBFLAG_YIELD)) { 3167 tcg_gen_insn_start(dc.pc); 3168 ++insn_count; 3169 gen_exception(&dc, EXCP_YIELD); 3170 dc.is_jmp = DISAS_UPDATE; 3171 goto done; 3172 } 3173 if (tb->flags & XTENSA_TBFLAG_EXCEPTION) { 3174 tcg_gen_insn_start(dc.pc); 3175 ++insn_count; 3176 gen_exception(&dc, EXCP_DEBUG); 3177 dc.is_jmp = DISAS_UPDATE; 3178 goto done; 3179 } 3180 3181 do { 3182 tcg_gen_insn_start(dc.pc); 3183 ++insn_count; 3184 3185 if (unlikely(cpu_breakpoint_test(cs, dc.pc, BP_ANY))) { 3186 tcg_gen_movi_i32(cpu_pc, dc.pc); 3187 gen_exception(&dc, EXCP_DEBUG); 3188 dc.is_jmp = DISAS_UPDATE; 3189 /* The address covered by the breakpoint must be included in 3190 [tb->pc, tb->pc + tb->size) in order to for it to be 3191 properly cleared -- thus we increment the PC here so that 3192 the logic setting tb->size below does the right thing. */ 3193 dc.pc += 2; 3194 break; 3195 } 3196 3197 if (insn_count == max_insns && (tb->cflags & CF_LAST_IO)) { 3198 gen_io_start(); 3199 } 3200 3201 if (dc.icount) { 3202 TCGLabel *label = gen_new_label(); 3203 3204 tcg_gen_addi_i32(dc.next_icount, cpu_SR[ICOUNT], 1); 3205 tcg_gen_brcondi_i32(TCG_COND_NE, dc.next_icount, 0, label); 3206 tcg_gen_mov_i32(dc.next_icount, cpu_SR[ICOUNT]); 3207 if (dc.debug) { 3208 gen_debug_exception(&dc, DEBUGCAUSE_IC); 3209 } 3210 gen_set_label(label); 3211 } 3212 3213 if (dc.debug) { 3214 gen_ibreak_check(env, &dc); 3215 } 3216 3217 disas_xtensa_insn(env, &dc); 3218 if (dc.icount) { 3219 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount); 3220 } 3221 if (cs->singlestep_enabled) { 3222 tcg_gen_movi_i32(cpu_pc, dc.pc); 3223 gen_exception(&dc, EXCP_DEBUG); 3224 break; 3225 } 3226 } while (dc.is_jmp == DISAS_NEXT && 3227 insn_count < max_insns && 3228 dc.pc < next_page_start && 3229 dc.pc + xtensa_insn_len(env, &dc) <= next_page_start && 3230 !tcg_op_buf_full()); 3231 done: 3232 reset_litbase(&dc); 3233 reset_sar_tracker(&dc); 3234 if (dc.icount) { 3235 tcg_temp_free(dc.next_icount); 3236 } 3237 3238 if (tb->cflags & CF_LAST_IO) { 3239 gen_io_end(); 3240 } 3241 3242 if (dc.is_jmp == DISAS_NEXT) { 3243 gen_jumpi(&dc, dc.pc, 0); 3244 } 3245 gen_tb_end(tb, insn_count); 3246 3247 #ifdef DEBUG_DISAS 3248 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) 3249 && qemu_log_in_addr_range(pc_start)) { 3250 qemu_log_lock(); 3251 qemu_log("----------------\n"); 3252 qemu_log("IN: %s\n", lookup_symbol(pc_start)); 3253 log_target_disas(cs, pc_start, dc.pc - pc_start, 0); 3254 qemu_log("\n"); 3255 qemu_log_unlock(); 3256 } 3257 #endif 3258 tb->size = dc.pc - pc_start; 3259 tb->icount = insn_count; 3260 } 3261 3262 void xtensa_cpu_dump_state(CPUState *cs, FILE *f, 3263 fprintf_function cpu_fprintf, int flags) 3264 { 3265 XtensaCPU *cpu = XTENSA_CPU(cs); 3266 CPUXtensaState *env = &cpu->env; 3267 int i, j; 3268 3269 cpu_fprintf(f, "PC=%08x\n\n", env->pc); 3270 3271 for (i = j = 0; i < 256; ++i) { 3272 if (xtensa_option_bits_enabled(env->config, sregnames[i].opt_bits)) { 3273 cpu_fprintf(f, "%12s=%08x%c", sregnames[i].name, env->sregs[i], 3274 (j++ % 4) == 3 ? '\n' : ' '); 3275 } 3276 } 3277 3278 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n"); 3279 3280 for (i = j = 0; i < 256; ++i) { 3281 if (xtensa_option_bits_enabled(env->config, uregnames[i].opt_bits)) { 3282 cpu_fprintf(f, "%s=%08x%c", uregnames[i].name, env->uregs[i], 3283 (j++ % 4) == 3 ? '\n' : ' '); 3284 } 3285 } 3286 3287 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n"); 3288 3289 for (i = 0; i < 16; ++i) { 3290 cpu_fprintf(f, " A%02d=%08x%c", i, env->regs[i], 3291 (i % 4) == 3 ? '\n' : ' '); 3292 } 3293 3294 cpu_fprintf(f, "\n"); 3295 3296 for (i = 0; i < env->config->nareg; ++i) { 3297 cpu_fprintf(f, "AR%02d=%08x%c", i, env->phys_regs[i], 3298 (i % 4) == 3 ? '\n' : ' '); 3299 } 3300 3301 if (xtensa_option_enabled(env->config, XTENSA_OPTION_FP_COPROCESSOR)) { 3302 cpu_fprintf(f, "\n"); 3303 3304 for (i = 0; i < 16; ++i) { 3305 cpu_fprintf(f, "F%02d=%08x (%+10.8e)%c", i, 3306 float32_val(env->fregs[i].f32[FP_F32_LOW]), 3307 *(float *)(env->fregs[i].f32 + FP_F32_LOW), 3308 (i % 2) == 1 ? '\n' : ' '); 3309 } 3310 } 3311 } 3312 3313 void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb, 3314 target_ulong *data) 3315 { 3316 env->pc = data[0]; 3317 } 3318