1 /* 2 * Xtensa ISA: 3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm 4 * 5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * * Neither the name of the Open Source and Linux Lab nor the 16 * names of its contributors may be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include "qemu/osdep.h" 32 33 #include "cpu.h" 34 #include "exec/exec-all.h" 35 #include "disas/disas.h" 36 #include "tcg-op.h" 37 #include "qemu/log.h" 38 #include "sysemu/sysemu.h" 39 #include "exec/cpu_ldst.h" 40 #include "exec/semihost.h" 41 #include "exec/translator.h" 42 43 #include "exec/helper-proto.h" 44 #include "exec/helper-gen.h" 45 46 #include "trace-tcg.h" 47 #include "exec/log.h" 48 49 50 /* is_jmp field values */ 51 #define DISAS_UPDATE DISAS_TARGET_0 /* cpu state was modified dynamically */ 52 53 struct DisasContext { 54 const XtensaConfig *config; 55 TranslationBlock *tb; 56 uint32_t pc; 57 uint32_t next_pc; 58 int cring; 59 int ring; 60 uint32_t lbeg; 61 uint32_t lend; 62 int is_jmp; 63 int singlestep_enabled; 64 65 bool sar_5bit; 66 bool sar_m32_5bit; 67 bool sar_m32_allocated; 68 TCGv_i32 sar_m32; 69 70 unsigned window; 71 72 bool debug; 73 bool icount; 74 TCGv_i32 next_icount; 75 76 unsigned cpenable; 77 78 uint32_t *raw_arg; 79 xtensa_insnbuf insnbuf; 80 xtensa_insnbuf slotbuf; 81 }; 82 83 static TCGv_i32 cpu_pc; 84 static TCGv_i32 cpu_R[16]; 85 static TCGv_i32 cpu_FR[16]; 86 static TCGv_i32 cpu_SR[256]; 87 static TCGv_i32 cpu_UR[256]; 88 89 #include "exec/gen-icount.h" 90 91 typedef struct XtensaReg { 92 const char *name; 93 uint64_t opt_bits; 94 enum { 95 SR_R = 1, 96 SR_W = 2, 97 SR_X = 4, 98 SR_RW = 3, 99 SR_RWX = 7, 100 } access; 101 } XtensaReg; 102 103 #define XTENSA_REG_ACCESS(regname, opt, acc) { \ 104 .name = (regname), \ 105 .opt_bits = XTENSA_OPTION_BIT(opt), \ 106 .access = (acc), \ 107 } 108 109 #define XTENSA_REG(regname, opt) XTENSA_REG_ACCESS(regname, opt, SR_RWX) 110 111 #define XTENSA_REG_BITS_ACCESS(regname, opt, acc) { \ 112 .name = (regname), \ 113 .opt_bits = (opt), \ 114 .access = (acc), \ 115 } 116 117 #define XTENSA_REG_BITS(regname, opt) \ 118 XTENSA_REG_BITS_ACCESS(regname, opt, SR_RWX) 119 120 static const XtensaReg sregnames[256] = { 121 [LBEG] = XTENSA_REG("LBEG", XTENSA_OPTION_LOOP), 122 [LEND] = XTENSA_REG("LEND", XTENSA_OPTION_LOOP), 123 [LCOUNT] = XTENSA_REG("LCOUNT", XTENSA_OPTION_LOOP), 124 [SAR] = XTENSA_REG_BITS("SAR", XTENSA_OPTION_ALL), 125 [BR] = XTENSA_REG("BR", XTENSA_OPTION_BOOLEAN), 126 [LITBASE] = XTENSA_REG("LITBASE", XTENSA_OPTION_EXTENDED_L32R), 127 [SCOMPARE1] = XTENSA_REG("SCOMPARE1", XTENSA_OPTION_CONDITIONAL_STORE), 128 [ACCLO] = XTENSA_REG("ACCLO", XTENSA_OPTION_MAC16), 129 [ACCHI] = XTENSA_REG("ACCHI", XTENSA_OPTION_MAC16), 130 [MR] = XTENSA_REG("MR0", XTENSA_OPTION_MAC16), 131 [MR + 1] = XTENSA_REG("MR1", XTENSA_OPTION_MAC16), 132 [MR + 2] = XTENSA_REG("MR2", XTENSA_OPTION_MAC16), 133 [MR + 3] = XTENSA_REG("MR3", XTENSA_OPTION_MAC16), 134 [WINDOW_BASE] = XTENSA_REG("WINDOW_BASE", XTENSA_OPTION_WINDOWED_REGISTER), 135 [WINDOW_START] = XTENSA_REG("WINDOW_START", 136 XTENSA_OPTION_WINDOWED_REGISTER), 137 [PTEVADDR] = XTENSA_REG("PTEVADDR", XTENSA_OPTION_MMU), 138 [MMID] = XTENSA_REG_BITS("MMID", XTENSA_OPTION_ALL), 139 [RASID] = XTENSA_REG("RASID", XTENSA_OPTION_MMU), 140 [ITLBCFG] = XTENSA_REG("ITLBCFG", XTENSA_OPTION_MMU), 141 [DTLBCFG] = XTENSA_REG("DTLBCFG", XTENSA_OPTION_MMU), 142 [IBREAKENABLE] = XTENSA_REG("IBREAKENABLE", XTENSA_OPTION_DEBUG), 143 [MEMCTL] = XTENSA_REG_BITS("MEMCTL", XTENSA_OPTION_ALL), 144 [CACHEATTR] = XTENSA_REG("CACHEATTR", XTENSA_OPTION_CACHEATTR), 145 [ATOMCTL] = XTENSA_REG("ATOMCTL", XTENSA_OPTION_ATOMCTL), 146 [DDR] = XTENSA_REG("DDR", XTENSA_OPTION_DEBUG), 147 [IBREAKA] = XTENSA_REG("IBREAKA0", XTENSA_OPTION_DEBUG), 148 [IBREAKA + 1] = XTENSA_REG("IBREAKA1", XTENSA_OPTION_DEBUG), 149 [DBREAKA] = XTENSA_REG("DBREAKA0", XTENSA_OPTION_DEBUG), 150 [DBREAKA + 1] = XTENSA_REG("DBREAKA1", XTENSA_OPTION_DEBUG), 151 [DBREAKC] = XTENSA_REG("DBREAKC0", XTENSA_OPTION_DEBUG), 152 [DBREAKC + 1] = XTENSA_REG("DBREAKC1", XTENSA_OPTION_DEBUG), 153 [CONFIGID0] = XTENSA_REG_BITS_ACCESS("CONFIGID0", XTENSA_OPTION_ALL, SR_R), 154 [EPC1] = XTENSA_REG("EPC1", XTENSA_OPTION_EXCEPTION), 155 [EPC1 + 1] = XTENSA_REG("EPC2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 156 [EPC1 + 2] = XTENSA_REG("EPC3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 157 [EPC1 + 3] = XTENSA_REG("EPC4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 158 [EPC1 + 4] = XTENSA_REG("EPC5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 159 [EPC1 + 5] = XTENSA_REG("EPC6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 160 [EPC1 + 6] = XTENSA_REG("EPC7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 161 [DEPC] = XTENSA_REG("DEPC", XTENSA_OPTION_EXCEPTION), 162 [EPS2] = XTENSA_REG("EPS2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 163 [EPS2 + 1] = XTENSA_REG("EPS3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 164 [EPS2 + 2] = XTENSA_REG("EPS4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 165 [EPS2 + 3] = XTENSA_REG("EPS5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 166 [EPS2 + 4] = XTENSA_REG("EPS6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 167 [EPS2 + 5] = XTENSA_REG("EPS7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 168 [CONFIGID1] = XTENSA_REG_BITS_ACCESS("CONFIGID1", XTENSA_OPTION_ALL, SR_R), 169 [EXCSAVE1] = XTENSA_REG("EXCSAVE1", XTENSA_OPTION_EXCEPTION), 170 [EXCSAVE1 + 1] = XTENSA_REG("EXCSAVE2", 171 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 172 [EXCSAVE1 + 2] = XTENSA_REG("EXCSAVE3", 173 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 174 [EXCSAVE1 + 3] = XTENSA_REG("EXCSAVE4", 175 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 176 [EXCSAVE1 + 4] = XTENSA_REG("EXCSAVE5", 177 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 178 [EXCSAVE1 + 5] = XTENSA_REG("EXCSAVE6", 179 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 180 [EXCSAVE1 + 6] = XTENSA_REG("EXCSAVE7", 181 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 182 [CPENABLE] = XTENSA_REG("CPENABLE", XTENSA_OPTION_COPROCESSOR), 183 [INTSET] = XTENSA_REG_ACCESS("INTSET", XTENSA_OPTION_INTERRUPT, SR_RW), 184 [INTCLEAR] = XTENSA_REG_ACCESS("INTCLEAR", XTENSA_OPTION_INTERRUPT, SR_W), 185 [INTENABLE] = XTENSA_REG("INTENABLE", XTENSA_OPTION_INTERRUPT), 186 [PS] = XTENSA_REG_BITS("PS", XTENSA_OPTION_ALL), 187 [VECBASE] = XTENSA_REG("VECBASE", XTENSA_OPTION_RELOCATABLE_VECTOR), 188 [EXCCAUSE] = XTENSA_REG("EXCCAUSE", XTENSA_OPTION_EXCEPTION), 189 [DEBUGCAUSE] = XTENSA_REG_ACCESS("DEBUGCAUSE", XTENSA_OPTION_DEBUG, SR_R), 190 [CCOUNT] = XTENSA_REG("CCOUNT", XTENSA_OPTION_TIMER_INTERRUPT), 191 [PRID] = XTENSA_REG_ACCESS("PRID", XTENSA_OPTION_PROCESSOR_ID, SR_R), 192 [ICOUNT] = XTENSA_REG("ICOUNT", XTENSA_OPTION_DEBUG), 193 [ICOUNTLEVEL] = XTENSA_REG("ICOUNTLEVEL", XTENSA_OPTION_DEBUG), 194 [EXCVADDR] = XTENSA_REG("EXCVADDR", XTENSA_OPTION_EXCEPTION), 195 [CCOMPARE] = XTENSA_REG("CCOMPARE0", XTENSA_OPTION_TIMER_INTERRUPT), 196 [CCOMPARE + 1] = XTENSA_REG("CCOMPARE1", 197 XTENSA_OPTION_TIMER_INTERRUPT), 198 [CCOMPARE + 2] = XTENSA_REG("CCOMPARE2", 199 XTENSA_OPTION_TIMER_INTERRUPT), 200 [MISC] = XTENSA_REG("MISC0", XTENSA_OPTION_MISC_SR), 201 [MISC + 1] = XTENSA_REG("MISC1", XTENSA_OPTION_MISC_SR), 202 [MISC + 2] = XTENSA_REG("MISC2", XTENSA_OPTION_MISC_SR), 203 [MISC + 3] = XTENSA_REG("MISC3", XTENSA_OPTION_MISC_SR), 204 }; 205 206 static const XtensaReg uregnames[256] = { 207 [EXPSTATE] = XTENSA_REG_BITS("EXPSTATE", XTENSA_OPTION_ALL), 208 [THREADPTR] = XTENSA_REG("THREADPTR", XTENSA_OPTION_THREAD_POINTER), 209 [FCR] = XTENSA_REG("FCR", XTENSA_OPTION_FP_COPROCESSOR), 210 [FSR] = XTENSA_REG("FSR", XTENSA_OPTION_FP_COPROCESSOR), 211 }; 212 213 void xtensa_translate_init(void) 214 { 215 static const char * const regnames[] = { 216 "ar0", "ar1", "ar2", "ar3", 217 "ar4", "ar5", "ar6", "ar7", 218 "ar8", "ar9", "ar10", "ar11", 219 "ar12", "ar13", "ar14", "ar15", 220 }; 221 static const char * const fregnames[] = { 222 "f0", "f1", "f2", "f3", 223 "f4", "f5", "f6", "f7", 224 "f8", "f9", "f10", "f11", 225 "f12", "f13", "f14", "f15", 226 }; 227 int i; 228 229 cpu_pc = tcg_global_mem_new_i32(cpu_env, 230 offsetof(CPUXtensaState, pc), "pc"); 231 232 for (i = 0; i < 16; i++) { 233 cpu_R[i] = tcg_global_mem_new_i32(cpu_env, 234 offsetof(CPUXtensaState, regs[i]), 235 regnames[i]); 236 } 237 238 for (i = 0; i < 16; i++) { 239 cpu_FR[i] = tcg_global_mem_new_i32(cpu_env, 240 offsetof(CPUXtensaState, fregs[i].f32[FP_F32_LOW]), 241 fregnames[i]); 242 } 243 244 for (i = 0; i < 256; ++i) { 245 if (sregnames[i].name) { 246 cpu_SR[i] = tcg_global_mem_new_i32(cpu_env, 247 offsetof(CPUXtensaState, sregs[i]), 248 sregnames[i].name); 249 } 250 } 251 252 for (i = 0; i < 256; ++i) { 253 if (uregnames[i].name) { 254 cpu_UR[i] = tcg_global_mem_new_i32(cpu_env, 255 offsetof(CPUXtensaState, uregs[i]), 256 uregnames[i].name); 257 } 258 } 259 } 260 261 static inline bool option_enabled(DisasContext *dc, int opt) 262 { 263 return xtensa_option_enabled(dc->config, opt); 264 } 265 266 static void init_sar_tracker(DisasContext *dc) 267 { 268 dc->sar_5bit = false; 269 dc->sar_m32_5bit = false; 270 dc->sar_m32_allocated = false; 271 } 272 273 static void reset_sar_tracker(DisasContext *dc) 274 { 275 if (dc->sar_m32_allocated) { 276 tcg_temp_free(dc->sar_m32); 277 } 278 } 279 280 static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa) 281 { 282 tcg_gen_andi_i32(cpu_SR[SAR], sa, 0x1f); 283 if (dc->sar_m32_5bit) { 284 tcg_gen_discard_i32(dc->sar_m32); 285 } 286 dc->sar_5bit = true; 287 dc->sar_m32_5bit = false; 288 } 289 290 static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa) 291 { 292 TCGv_i32 tmp = tcg_const_i32(32); 293 if (!dc->sar_m32_allocated) { 294 dc->sar_m32 = tcg_temp_local_new_i32(); 295 dc->sar_m32_allocated = true; 296 } 297 tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f); 298 tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32); 299 dc->sar_5bit = false; 300 dc->sar_m32_5bit = true; 301 tcg_temp_free(tmp); 302 } 303 304 static void gen_exception(DisasContext *dc, int excp) 305 { 306 TCGv_i32 tmp = tcg_const_i32(excp); 307 gen_helper_exception(cpu_env, tmp); 308 tcg_temp_free(tmp); 309 } 310 311 static void gen_exception_cause(DisasContext *dc, uint32_t cause) 312 { 313 TCGv_i32 tpc = tcg_const_i32(dc->pc); 314 TCGv_i32 tcause = tcg_const_i32(cause); 315 gen_helper_exception_cause(cpu_env, tpc, tcause); 316 tcg_temp_free(tpc); 317 tcg_temp_free(tcause); 318 if (cause == ILLEGAL_INSTRUCTION_CAUSE || 319 cause == SYSCALL_CAUSE) { 320 dc->is_jmp = DISAS_UPDATE; 321 } 322 } 323 324 static void gen_exception_cause_vaddr(DisasContext *dc, uint32_t cause, 325 TCGv_i32 vaddr) 326 { 327 TCGv_i32 tpc = tcg_const_i32(dc->pc); 328 TCGv_i32 tcause = tcg_const_i32(cause); 329 gen_helper_exception_cause_vaddr(cpu_env, tpc, tcause, vaddr); 330 tcg_temp_free(tpc); 331 tcg_temp_free(tcause); 332 } 333 334 static void gen_debug_exception(DisasContext *dc, uint32_t cause) 335 { 336 TCGv_i32 tpc = tcg_const_i32(dc->pc); 337 TCGv_i32 tcause = tcg_const_i32(cause); 338 gen_helper_debug_exception(cpu_env, tpc, tcause); 339 tcg_temp_free(tpc); 340 tcg_temp_free(tcause); 341 if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) { 342 dc->is_jmp = DISAS_UPDATE; 343 } 344 } 345 346 static bool gen_check_privilege(DisasContext *dc) 347 { 348 #ifndef CONFIG_USER_ONLY 349 if (!dc->cring) { 350 return true; 351 } 352 #endif 353 gen_exception_cause(dc, PRIVILEGED_CAUSE); 354 dc->is_jmp = DISAS_UPDATE; 355 return false; 356 } 357 358 static bool gen_check_cpenable(DisasContext *dc, unsigned cp) 359 { 360 if (option_enabled(dc, XTENSA_OPTION_COPROCESSOR) && 361 !(dc->cpenable & (1 << cp))) { 362 gen_exception_cause(dc, COPROCESSOR0_DISABLED + cp); 363 dc->is_jmp = DISAS_UPDATE; 364 return false; 365 } 366 return true; 367 } 368 369 static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot) 370 { 371 tcg_gen_mov_i32(cpu_pc, dest); 372 if (dc->icount) { 373 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount); 374 } 375 if (dc->singlestep_enabled) { 376 gen_exception(dc, EXCP_DEBUG); 377 } else { 378 if (slot >= 0) { 379 tcg_gen_goto_tb(slot); 380 tcg_gen_exit_tb((uintptr_t)dc->tb + slot); 381 } else { 382 tcg_gen_exit_tb(0); 383 } 384 } 385 dc->is_jmp = DISAS_UPDATE; 386 } 387 388 static void gen_jump(DisasContext *dc, TCGv dest) 389 { 390 gen_jump_slot(dc, dest, -1); 391 } 392 393 static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot) 394 { 395 TCGv_i32 tmp = tcg_const_i32(dest); 396 #ifndef CONFIG_USER_ONLY 397 if (((dc->tb->pc ^ dest) & TARGET_PAGE_MASK) != 0) { 398 slot = -1; 399 } 400 #endif 401 gen_jump_slot(dc, tmp, slot); 402 tcg_temp_free(tmp); 403 } 404 405 static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest, 406 int slot) 407 { 408 TCGv_i32 tcallinc = tcg_const_i32(callinc); 409 410 tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS], 411 tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN); 412 tcg_temp_free(tcallinc); 413 tcg_gen_movi_i32(cpu_R[callinc << 2], 414 (callinc << 30) | (dc->next_pc & 0x3fffffff)); 415 gen_jump_slot(dc, dest, slot); 416 } 417 418 static void gen_callw(DisasContext *dc, int callinc, TCGv_i32 dest) 419 { 420 gen_callw_slot(dc, callinc, dest, -1); 421 } 422 423 static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot) 424 { 425 TCGv_i32 tmp = tcg_const_i32(dest); 426 #ifndef CONFIG_USER_ONLY 427 if (((dc->tb->pc ^ dest) & TARGET_PAGE_MASK) != 0) { 428 slot = -1; 429 } 430 #endif 431 gen_callw_slot(dc, callinc, tmp, slot); 432 tcg_temp_free(tmp); 433 } 434 435 static bool gen_check_loop_end(DisasContext *dc, int slot) 436 { 437 if (option_enabled(dc, XTENSA_OPTION_LOOP) && 438 !(dc->tb->flags & XTENSA_TBFLAG_EXCM) && 439 dc->next_pc == dc->lend) { 440 TCGLabel *label = gen_new_label(); 441 442 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label); 443 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1); 444 gen_jumpi(dc, dc->lbeg, slot); 445 gen_set_label(label); 446 gen_jumpi(dc, dc->next_pc, -1); 447 return true; 448 } 449 return false; 450 } 451 452 static void gen_jumpi_check_loop_end(DisasContext *dc, int slot) 453 { 454 if (!gen_check_loop_end(dc, slot)) { 455 gen_jumpi(dc, dc->next_pc, slot); 456 } 457 } 458 459 static void gen_brcond(DisasContext *dc, TCGCond cond, 460 TCGv_i32 t0, TCGv_i32 t1, uint32_t addr) 461 { 462 TCGLabel *label = gen_new_label(); 463 464 tcg_gen_brcond_i32(cond, t0, t1, label); 465 gen_jumpi_check_loop_end(dc, 0); 466 gen_set_label(label); 467 gen_jumpi(dc, addr, 1); 468 } 469 470 static void gen_brcondi(DisasContext *dc, TCGCond cond, 471 TCGv_i32 t0, uint32_t t1, uint32_t addr) 472 { 473 TCGv_i32 tmp = tcg_const_i32(t1); 474 gen_brcond(dc, cond, t0, tmp, addr); 475 tcg_temp_free(tmp); 476 } 477 478 static bool gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access) 479 { 480 if (!xtensa_option_bits_enabled(dc->config, sregnames[sr].opt_bits)) { 481 if (sregnames[sr].name) { 482 qemu_log_mask(LOG_GUEST_ERROR, "SR %s is not configured\n", sregnames[sr].name); 483 } else { 484 qemu_log_mask(LOG_UNIMP, "SR %d is not implemented\n", sr); 485 } 486 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); 487 return false; 488 } else if (!(sregnames[sr].access & access)) { 489 static const char * const access_text[] = { 490 [SR_R] = "rsr", 491 [SR_W] = "wsr", 492 [SR_X] = "xsr", 493 }; 494 assert(access < ARRAY_SIZE(access_text) && access_text[access]); 495 qemu_log_mask(LOG_GUEST_ERROR, "SR %s is not available for %s\n", sregnames[sr].name, 496 access_text[access]); 497 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); 498 return false; 499 } 500 return true; 501 } 502 503 #ifndef CONFIG_USER_ONLY 504 static bool gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr) 505 { 506 if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { 507 gen_io_start(); 508 } 509 gen_helper_update_ccount(cpu_env); 510 tcg_gen_mov_i32(d, cpu_SR[sr]); 511 if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { 512 gen_io_end(); 513 return true; 514 } 515 return false; 516 } 517 518 static bool gen_rsr_ptevaddr(DisasContext *dc, TCGv_i32 d, uint32_t sr) 519 { 520 tcg_gen_shri_i32(d, cpu_SR[EXCVADDR], 10); 521 tcg_gen_or_i32(d, d, cpu_SR[sr]); 522 tcg_gen_andi_i32(d, d, 0xfffffffc); 523 return false; 524 } 525 #endif 526 527 static bool gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr) 528 { 529 static bool (* const rsr_handler[256])(DisasContext *dc, 530 TCGv_i32 d, uint32_t sr) = { 531 #ifndef CONFIG_USER_ONLY 532 [CCOUNT] = gen_rsr_ccount, 533 [INTSET] = gen_rsr_ccount, 534 [PTEVADDR] = gen_rsr_ptevaddr, 535 #endif 536 }; 537 538 if (rsr_handler[sr]) { 539 return rsr_handler[sr](dc, d, sr); 540 } else { 541 tcg_gen_mov_i32(d, cpu_SR[sr]); 542 return false; 543 } 544 } 545 546 static bool gen_wsr_lbeg(DisasContext *dc, uint32_t sr, TCGv_i32 s) 547 { 548 gen_helper_wsr_lbeg(cpu_env, s); 549 gen_jumpi_check_loop_end(dc, 0); 550 return false; 551 } 552 553 static bool gen_wsr_lend(DisasContext *dc, uint32_t sr, TCGv_i32 s) 554 { 555 gen_helper_wsr_lend(cpu_env, s); 556 gen_jumpi_check_loop_end(dc, 0); 557 return false; 558 } 559 560 static bool gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s) 561 { 562 tcg_gen_andi_i32(cpu_SR[sr], s, 0x3f); 563 if (dc->sar_m32_5bit) { 564 tcg_gen_discard_i32(dc->sar_m32); 565 } 566 dc->sar_5bit = false; 567 dc->sar_m32_5bit = false; 568 return false; 569 } 570 571 static bool gen_wsr_br(DisasContext *dc, uint32_t sr, TCGv_i32 s) 572 { 573 tcg_gen_andi_i32(cpu_SR[sr], s, 0xffff); 574 return false; 575 } 576 577 static bool gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s) 578 { 579 tcg_gen_andi_i32(cpu_SR[sr], s, 0xfffff001); 580 /* This can change tb->flags, so exit tb */ 581 gen_jumpi_check_loop_end(dc, -1); 582 return true; 583 } 584 585 static bool gen_wsr_acchi(DisasContext *dc, uint32_t sr, TCGv_i32 s) 586 { 587 tcg_gen_ext8s_i32(cpu_SR[sr], s); 588 return false; 589 } 590 591 #ifndef CONFIG_USER_ONLY 592 static bool gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v) 593 { 594 gen_helper_wsr_windowbase(cpu_env, v); 595 /* This can change tb->flags, so exit tb */ 596 gen_jumpi_check_loop_end(dc, -1); 597 return true; 598 } 599 600 static bool gen_wsr_windowstart(DisasContext *dc, uint32_t sr, TCGv_i32 v) 601 { 602 tcg_gen_andi_i32(cpu_SR[sr], v, (1 << dc->config->nareg / 4) - 1); 603 /* This can change tb->flags, so exit tb */ 604 gen_jumpi_check_loop_end(dc, -1); 605 return true; 606 } 607 608 static bool gen_wsr_ptevaddr(DisasContext *dc, uint32_t sr, TCGv_i32 v) 609 { 610 tcg_gen_andi_i32(cpu_SR[sr], v, 0xffc00000); 611 return false; 612 } 613 614 static bool gen_wsr_rasid(DisasContext *dc, uint32_t sr, TCGv_i32 v) 615 { 616 gen_helper_wsr_rasid(cpu_env, v); 617 /* This can change tb->flags, so exit tb */ 618 gen_jumpi_check_loop_end(dc, -1); 619 return true; 620 } 621 622 static bool gen_wsr_tlbcfg(DisasContext *dc, uint32_t sr, TCGv_i32 v) 623 { 624 tcg_gen_andi_i32(cpu_SR[sr], v, 0x01130000); 625 return false; 626 } 627 628 static bool gen_wsr_ibreakenable(DisasContext *dc, uint32_t sr, TCGv_i32 v) 629 { 630 gen_helper_wsr_ibreakenable(cpu_env, v); 631 gen_jumpi_check_loop_end(dc, 0); 632 return true; 633 } 634 635 static bool gen_wsr_memctl(DisasContext *dc, uint32_t sr, TCGv_i32 v) 636 { 637 gen_helper_wsr_memctl(cpu_env, v); 638 return false; 639 } 640 641 static bool gen_wsr_atomctl(DisasContext *dc, uint32_t sr, TCGv_i32 v) 642 { 643 tcg_gen_andi_i32(cpu_SR[sr], v, 0x3f); 644 return false; 645 } 646 647 static bool gen_wsr_ibreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v) 648 { 649 unsigned id = sr - IBREAKA; 650 651 if (id < dc->config->nibreak) { 652 TCGv_i32 tmp = tcg_const_i32(id); 653 gen_helper_wsr_ibreaka(cpu_env, tmp, v); 654 tcg_temp_free(tmp); 655 gen_jumpi_check_loop_end(dc, 0); 656 return true; 657 } 658 return false; 659 } 660 661 static bool gen_wsr_dbreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v) 662 { 663 unsigned id = sr - DBREAKA; 664 665 if (id < dc->config->ndbreak) { 666 TCGv_i32 tmp = tcg_const_i32(id); 667 gen_helper_wsr_dbreaka(cpu_env, tmp, v); 668 tcg_temp_free(tmp); 669 } 670 return false; 671 } 672 673 static bool gen_wsr_dbreakc(DisasContext *dc, uint32_t sr, TCGv_i32 v) 674 { 675 unsigned id = sr - DBREAKC; 676 677 if (id < dc->config->ndbreak) { 678 TCGv_i32 tmp = tcg_const_i32(id); 679 gen_helper_wsr_dbreakc(cpu_env, tmp, v); 680 tcg_temp_free(tmp); 681 } 682 return false; 683 } 684 685 static bool gen_wsr_cpenable(DisasContext *dc, uint32_t sr, TCGv_i32 v) 686 { 687 tcg_gen_andi_i32(cpu_SR[sr], v, 0xff); 688 /* This can change tb->flags, so exit tb */ 689 gen_jumpi_check_loop_end(dc, -1); 690 return true; 691 } 692 693 static void gen_check_interrupts(DisasContext *dc) 694 { 695 if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { 696 gen_io_start(); 697 } 698 gen_helper_check_interrupts(cpu_env); 699 if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { 700 gen_io_end(); 701 } 702 } 703 704 static bool gen_wsr_intset(DisasContext *dc, uint32_t sr, TCGv_i32 v) 705 { 706 tcg_gen_andi_i32(cpu_SR[sr], v, 707 dc->config->inttype_mask[INTTYPE_SOFTWARE]); 708 gen_check_interrupts(dc); 709 gen_jumpi_check_loop_end(dc, 0); 710 return true; 711 } 712 713 static bool gen_wsr_intclear(DisasContext *dc, uint32_t sr, TCGv_i32 v) 714 { 715 TCGv_i32 tmp = tcg_temp_new_i32(); 716 717 tcg_gen_andi_i32(tmp, v, 718 dc->config->inttype_mask[INTTYPE_EDGE] | 719 dc->config->inttype_mask[INTTYPE_NMI] | 720 dc->config->inttype_mask[INTTYPE_SOFTWARE]); 721 tcg_gen_andc_i32(cpu_SR[INTSET], cpu_SR[INTSET], tmp); 722 tcg_temp_free(tmp); 723 gen_check_interrupts(dc); 724 gen_jumpi_check_loop_end(dc, 0); 725 return true; 726 } 727 728 static bool gen_wsr_intenable(DisasContext *dc, uint32_t sr, TCGv_i32 v) 729 { 730 tcg_gen_mov_i32(cpu_SR[sr], v); 731 gen_check_interrupts(dc); 732 gen_jumpi_check_loop_end(dc, 0); 733 return true; 734 } 735 736 static bool gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v) 737 { 738 uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB | 739 PS_UM | PS_EXCM | PS_INTLEVEL; 740 741 if (option_enabled(dc, XTENSA_OPTION_MMU)) { 742 mask |= PS_RING; 743 } 744 tcg_gen_andi_i32(cpu_SR[sr], v, mask); 745 gen_check_interrupts(dc); 746 /* This can change mmu index and tb->flags, so exit tb */ 747 gen_jumpi_check_loop_end(dc, -1); 748 return true; 749 } 750 751 static bool gen_wsr_ccount(DisasContext *dc, uint32_t sr, TCGv_i32 v) 752 { 753 if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { 754 gen_io_start(); 755 } 756 gen_helper_wsr_ccount(cpu_env, v); 757 if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { 758 gen_io_end(); 759 gen_jumpi_check_loop_end(dc, 0); 760 return true; 761 } 762 return false; 763 } 764 765 static bool gen_wsr_icount(DisasContext *dc, uint32_t sr, TCGv_i32 v) 766 { 767 if (dc->icount) { 768 tcg_gen_mov_i32(dc->next_icount, v); 769 } else { 770 tcg_gen_mov_i32(cpu_SR[sr], v); 771 } 772 return false; 773 } 774 775 static bool gen_wsr_icountlevel(DisasContext *dc, uint32_t sr, TCGv_i32 v) 776 { 777 tcg_gen_andi_i32(cpu_SR[sr], v, 0xf); 778 /* This can change tb->flags, so exit tb */ 779 gen_jumpi_check_loop_end(dc, -1); 780 return true; 781 } 782 783 static bool gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v) 784 { 785 uint32_t id = sr - CCOMPARE; 786 bool ret = false; 787 788 if (id < dc->config->nccompare) { 789 uint32_t int_bit = 1 << dc->config->timerint[id]; 790 TCGv_i32 tmp = tcg_const_i32(id); 791 792 tcg_gen_mov_i32(cpu_SR[sr], v); 793 tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit); 794 if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { 795 gen_io_start(); 796 } 797 gen_helper_update_ccompare(cpu_env, tmp); 798 if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { 799 gen_io_end(); 800 gen_jumpi_check_loop_end(dc, 0); 801 ret = true; 802 } 803 tcg_temp_free(tmp); 804 } 805 return ret; 806 } 807 #else 808 static void gen_check_interrupts(DisasContext *dc) 809 { 810 } 811 #endif 812 813 static bool gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s) 814 { 815 static bool (* const wsr_handler[256])(DisasContext *dc, 816 uint32_t sr, TCGv_i32 v) = { 817 [LBEG] = gen_wsr_lbeg, 818 [LEND] = gen_wsr_lend, 819 [SAR] = gen_wsr_sar, 820 [BR] = gen_wsr_br, 821 [LITBASE] = gen_wsr_litbase, 822 [ACCHI] = gen_wsr_acchi, 823 #ifndef CONFIG_USER_ONLY 824 [WINDOW_BASE] = gen_wsr_windowbase, 825 [WINDOW_START] = gen_wsr_windowstart, 826 [PTEVADDR] = gen_wsr_ptevaddr, 827 [RASID] = gen_wsr_rasid, 828 [ITLBCFG] = gen_wsr_tlbcfg, 829 [DTLBCFG] = gen_wsr_tlbcfg, 830 [IBREAKENABLE] = gen_wsr_ibreakenable, 831 [MEMCTL] = gen_wsr_memctl, 832 [ATOMCTL] = gen_wsr_atomctl, 833 [IBREAKA] = gen_wsr_ibreaka, 834 [IBREAKA + 1] = gen_wsr_ibreaka, 835 [DBREAKA] = gen_wsr_dbreaka, 836 [DBREAKA + 1] = gen_wsr_dbreaka, 837 [DBREAKC] = gen_wsr_dbreakc, 838 [DBREAKC + 1] = gen_wsr_dbreakc, 839 [CPENABLE] = gen_wsr_cpenable, 840 [INTSET] = gen_wsr_intset, 841 [INTCLEAR] = gen_wsr_intclear, 842 [INTENABLE] = gen_wsr_intenable, 843 [PS] = gen_wsr_ps, 844 [CCOUNT] = gen_wsr_ccount, 845 [ICOUNT] = gen_wsr_icount, 846 [ICOUNTLEVEL] = gen_wsr_icountlevel, 847 [CCOMPARE] = gen_wsr_ccompare, 848 [CCOMPARE + 1] = gen_wsr_ccompare, 849 [CCOMPARE + 2] = gen_wsr_ccompare, 850 #endif 851 }; 852 853 if (wsr_handler[sr]) { 854 return wsr_handler[sr](dc, sr, s); 855 } else { 856 tcg_gen_mov_i32(cpu_SR[sr], s); 857 return false; 858 } 859 } 860 861 static void gen_wur(uint32_t ur, TCGv_i32 s) 862 { 863 switch (ur) { 864 case FCR: 865 gen_helper_wur_fcr(cpu_env, s); 866 break; 867 868 case FSR: 869 tcg_gen_andi_i32(cpu_UR[ur], s, 0xffffff80); 870 break; 871 872 default: 873 tcg_gen_mov_i32(cpu_UR[ur], s); 874 break; 875 } 876 } 877 878 static void gen_load_store_alignment(DisasContext *dc, int shift, 879 TCGv_i32 addr, bool no_hw_alignment) 880 { 881 if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) { 882 tcg_gen_andi_i32(addr, addr, ~0 << shift); 883 } else if (option_enabled(dc, XTENSA_OPTION_HW_ALIGNMENT) && 884 no_hw_alignment) { 885 TCGLabel *label = gen_new_label(); 886 TCGv_i32 tmp = tcg_temp_new_i32(); 887 tcg_gen_andi_i32(tmp, addr, ~(~0 << shift)); 888 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label); 889 gen_exception_cause_vaddr(dc, LOAD_STORE_ALIGNMENT_CAUSE, addr); 890 gen_set_label(label); 891 tcg_temp_free(tmp); 892 } 893 } 894 895 #ifndef CONFIG_USER_ONLY 896 static void gen_waiti(DisasContext *dc, uint32_t imm4) 897 { 898 TCGv_i32 pc = tcg_const_i32(dc->next_pc); 899 TCGv_i32 intlevel = tcg_const_i32(imm4); 900 901 if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { 902 gen_io_start(); 903 } 904 gen_helper_waiti(cpu_env, pc, intlevel); 905 if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { 906 gen_io_end(); 907 } 908 tcg_temp_free(pc); 909 tcg_temp_free(intlevel); 910 gen_jumpi_check_loop_end(dc, 0); 911 } 912 #endif 913 914 static bool gen_window_check1(DisasContext *dc, unsigned r1) 915 { 916 if (r1 / 4 > dc->window) { 917 TCGv_i32 pc = tcg_const_i32(dc->pc); 918 TCGv_i32 w = tcg_const_i32(r1 / 4); 919 920 gen_helper_window_check(cpu_env, pc, w); 921 dc->is_jmp = DISAS_UPDATE; 922 return false; 923 } 924 return true; 925 } 926 927 static bool gen_window_check2(DisasContext *dc, unsigned r1, unsigned r2) 928 { 929 return gen_window_check1(dc, r1 > r2 ? r1 : r2); 930 } 931 932 static bool gen_window_check3(DisasContext *dc, unsigned r1, unsigned r2, 933 unsigned r3) 934 { 935 return gen_window_check2(dc, r1, r2 > r3 ? r2 : r3); 936 } 937 938 static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned) 939 { 940 TCGv_i32 m = tcg_temp_new_i32(); 941 942 if (hi) { 943 (is_unsigned ? tcg_gen_shri_i32 : tcg_gen_sari_i32)(m, v, 16); 944 } else { 945 (is_unsigned ? tcg_gen_ext16u_i32 : tcg_gen_ext16s_i32)(m, v); 946 } 947 return m; 948 } 949 950 static inline unsigned xtensa_op0_insn_len(DisasContext *dc, uint8_t op0) 951 { 952 return xtensa_isa_length_from_chars(dc->config->isa, &op0); 953 } 954 955 static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) 956 { 957 xtensa_isa isa = dc->config->isa; 958 unsigned char b[MAX_INSN_LENGTH] = {cpu_ldub_code(env, dc->pc)}; 959 unsigned len = xtensa_op0_insn_len(dc, b[0]); 960 xtensa_format fmt; 961 int slot, slots; 962 unsigned i; 963 964 if (len == XTENSA_UNDEFINED) { 965 qemu_log_mask(LOG_GUEST_ERROR, 966 "unknown instruction length (pc = %08x)\n", 967 dc->pc); 968 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); 969 return; 970 } 971 972 dc->next_pc = dc->pc + len; 973 for (i = 1; i < len; ++i) { 974 b[i] = cpu_ldub_code(env, dc->pc + i); 975 } 976 xtensa_insnbuf_from_chars(isa, dc->insnbuf, b, len); 977 fmt = xtensa_format_decode(isa, dc->insnbuf); 978 if (fmt == XTENSA_UNDEFINED) { 979 qemu_log_mask(LOG_GUEST_ERROR, 980 "unrecognized instruction format (pc = %08x)\n", 981 dc->pc); 982 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); 983 return; 984 } 985 slots = xtensa_format_num_slots(isa, fmt); 986 for (slot = 0; slot < slots; ++slot) { 987 xtensa_opcode opc; 988 int opnd, vopnd, opnds; 989 uint32_t raw_arg[MAX_OPCODE_ARGS]; 990 uint32_t arg[MAX_OPCODE_ARGS]; 991 XtensaOpcodeOps *ops; 992 993 dc->raw_arg = raw_arg; 994 995 xtensa_format_get_slot(isa, fmt, slot, dc->insnbuf, dc->slotbuf); 996 opc = xtensa_opcode_decode(isa, fmt, slot, dc->slotbuf); 997 if (opc == XTENSA_UNDEFINED) { 998 qemu_log_mask(LOG_GUEST_ERROR, 999 "unrecognized opcode in slot %d (pc = %08x)\n", 1000 slot, dc->pc); 1001 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); 1002 return; 1003 } 1004 opnds = xtensa_opcode_num_operands(isa, opc); 1005 1006 for (opnd = vopnd = 0; opnd < opnds; ++opnd) { 1007 if (xtensa_operand_is_visible(isa, opc, opnd)) { 1008 uint32_t v; 1009 1010 xtensa_operand_get_field(isa, opc, opnd, fmt, slot, 1011 dc->slotbuf, &v); 1012 xtensa_operand_decode(isa, opc, opnd, &v); 1013 raw_arg[vopnd] = v; 1014 if (xtensa_operand_is_PCrelative(isa, opc, opnd)) { 1015 xtensa_operand_undo_reloc(isa, opc, opnd, &v, dc->pc); 1016 } 1017 arg[vopnd] = v; 1018 ++vopnd; 1019 } 1020 } 1021 ops = dc->config->opcode_ops[opc]; 1022 if (ops) { 1023 ops->translate(dc, arg, ops->par); 1024 } else { 1025 qemu_log_mask(LOG_GUEST_ERROR, 1026 "unimplemented opcode '%s' in slot %d (pc = %08x)\n", 1027 xtensa_opcode_name(isa, opc), slot, dc->pc); 1028 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); 1029 return; 1030 } 1031 } 1032 if (dc->is_jmp == DISAS_NEXT) { 1033 gen_check_loop_end(dc, 0); 1034 } 1035 dc->pc = dc->next_pc; 1036 } 1037 1038 static inline unsigned xtensa_insn_len(CPUXtensaState *env, DisasContext *dc) 1039 { 1040 uint8_t b0 = cpu_ldub_code(env, dc->pc); 1041 return xtensa_op0_insn_len(dc, b0); 1042 } 1043 1044 static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc) 1045 { 1046 unsigned i; 1047 1048 for (i = 0; i < dc->config->nibreak; ++i) { 1049 if ((env->sregs[IBREAKENABLE] & (1 << i)) && 1050 env->sregs[IBREAKA + i] == dc->pc) { 1051 gen_debug_exception(dc, DEBUGCAUSE_IB); 1052 break; 1053 } 1054 } 1055 } 1056 1057 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) 1058 { 1059 CPUXtensaState *env = cs->env_ptr; 1060 DisasContext dc; 1061 int insn_count = 0; 1062 int max_insns = tb_cflags(tb) & CF_COUNT_MASK; 1063 uint32_t pc_start = tb->pc; 1064 uint32_t page_start = pc_start & TARGET_PAGE_MASK; 1065 1066 if (max_insns == 0) { 1067 max_insns = CF_COUNT_MASK; 1068 } 1069 if (max_insns > TCG_MAX_INSNS) { 1070 max_insns = TCG_MAX_INSNS; 1071 } 1072 1073 dc.config = env->config; 1074 dc.singlestep_enabled = cs->singlestep_enabled; 1075 dc.tb = tb; 1076 dc.pc = pc_start; 1077 dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK; 1078 dc.cring = (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc.ring; 1079 dc.lbeg = env->sregs[LBEG]; 1080 dc.lend = env->sregs[LEND]; 1081 dc.is_jmp = DISAS_NEXT; 1082 dc.debug = tb->flags & XTENSA_TBFLAG_DEBUG; 1083 dc.icount = tb->flags & XTENSA_TBFLAG_ICOUNT; 1084 dc.cpenable = (tb->flags & XTENSA_TBFLAG_CPENABLE_MASK) >> 1085 XTENSA_TBFLAG_CPENABLE_SHIFT; 1086 dc.window = ((tb->flags & XTENSA_TBFLAG_WINDOW_MASK) >> 1087 XTENSA_TBFLAG_WINDOW_SHIFT); 1088 1089 if (dc.config->isa) { 1090 dc.insnbuf = xtensa_insnbuf_alloc(dc.config->isa); 1091 dc.slotbuf = xtensa_insnbuf_alloc(dc.config->isa); 1092 } 1093 1094 init_sar_tracker(&dc); 1095 if (dc.icount) { 1096 dc.next_icount = tcg_temp_local_new_i32(); 1097 } 1098 1099 gen_tb_start(tb); 1100 1101 if ((tb_cflags(tb) & CF_USE_ICOUNT) && 1102 (tb->flags & XTENSA_TBFLAG_YIELD)) { 1103 tcg_gen_insn_start(dc.pc); 1104 ++insn_count; 1105 gen_exception(&dc, EXCP_YIELD); 1106 dc.is_jmp = DISAS_UPDATE; 1107 goto done; 1108 } 1109 if (tb->flags & XTENSA_TBFLAG_EXCEPTION) { 1110 tcg_gen_insn_start(dc.pc); 1111 ++insn_count; 1112 gen_exception(&dc, EXCP_DEBUG); 1113 dc.is_jmp = DISAS_UPDATE; 1114 goto done; 1115 } 1116 1117 do { 1118 tcg_gen_insn_start(dc.pc); 1119 ++insn_count; 1120 1121 if (unlikely(cpu_breakpoint_test(cs, dc.pc, BP_ANY))) { 1122 tcg_gen_movi_i32(cpu_pc, dc.pc); 1123 gen_exception(&dc, EXCP_DEBUG); 1124 dc.is_jmp = DISAS_UPDATE; 1125 /* The address covered by the breakpoint must be included in 1126 [tb->pc, tb->pc + tb->size) in order to for it to be 1127 properly cleared -- thus we increment the PC here so that 1128 the logic setting tb->size below does the right thing. */ 1129 dc.pc += 2; 1130 break; 1131 } 1132 1133 if (insn_count == max_insns && (tb_cflags(tb) & CF_LAST_IO)) { 1134 gen_io_start(); 1135 } 1136 1137 if (dc.icount) { 1138 TCGLabel *label = gen_new_label(); 1139 1140 tcg_gen_addi_i32(dc.next_icount, cpu_SR[ICOUNT], 1); 1141 tcg_gen_brcondi_i32(TCG_COND_NE, dc.next_icount, 0, label); 1142 tcg_gen_mov_i32(dc.next_icount, cpu_SR[ICOUNT]); 1143 if (dc.debug) { 1144 gen_debug_exception(&dc, DEBUGCAUSE_IC); 1145 } 1146 gen_set_label(label); 1147 } 1148 1149 if (dc.debug) { 1150 gen_ibreak_check(env, &dc); 1151 } 1152 1153 disas_xtensa_insn(env, &dc); 1154 if (dc.icount) { 1155 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount); 1156 } 1157 if (cs->singlestep_enabled) { 1158 tcg_gen_movi_i32(cpu_pc, dc.pc); 1159 gen_exception(&dc, EXCP_DEBUG); 1160 break; 1161 } 1162 } while (dc.is_jmp == DISAS_NEXT && 1163 insn_count < max_insns && 1164 dc.pc - page_start < TARGET_PAGE_SIZE && 1165 dc.pc - page_start + xtensa_insn_len(env, &dc) <= TARGET_PAGE_SIZE 1166 && !tcg_op_buf_full()); 1167 done: 1168 reset_sar_tracker(&dc); 1169 if (dc.icount) { 1170 tcg_temp_free(dc.next_icount); 1171 } 1172 if (dc.config->isa) { 1173 xtensa_insnbuf_free(dc.config->isa, dc.insnbuf); 1174 xtensa_insnbuf_free(dc.config->isa, dc.slotbuf); 1175 } 1176 1177 if (tb_cflags(tb) & CF_LAST_IO) { 1178 gen_io_end(); 1179 } 1180 1181 if (dc.is_jmp == DISAS_NEXT) { 1182 gen_jumpi(&dc, dc.pc, 0); 1183 } 1184 gen_tb_end(tb, insn_count); 1185 1186 #ifdef DEBUG_DISAS 1187 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) 1188 && qemu_log_in_addr_range(pc_start)) { 1189 qemu_log_lock(); 1190 qemu_log("----------------\n"); 1191 qemu_log("IN: %s\n", lookup_symbol(pc_start)); 1192 log_target_disas(cs, pc_start, dc.pc - pc_start); 1193 qemu_log("\n"); 1194 qemu_log_unlock(); 1195 } 1196 #endif 1197 tb->size = dc.pc - pc_start; 1198 tb->icount = insn_count; 1199 } 1200 1201 void xtensa_cpu_dump_state(CPUState *cs, FILE *f, 1202 fprintf_function cpu_fprintf, int flags) 1203 { 1204 XtensaCPU *cpu = XTENSA_CPU(cs); 1205 CPUXtensaState *env = &cpu->env; 1206 int i, j; 1207 1208 cpu_fprintf(f, "PC=%08x\n\n", env->pc); 1209 1210 for (i = j = 0; i < 256; ++i) { 1211 if (xtensa_option_bits_enabled(env->config, sregnames[i].opt_bits)) { 1212 cpu_fprintf(f, "%12s=%08x%c", sregnames[i].name, env->sregs[i], 1213 (j++ % 4) == 3 ? '\n' : ' '); 1214 } 1215 } 1216 1217 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n"); 1218 1219 for (i = j = 0; i < 256; ++i) { 1220 if (xtensa_option_bits_enabled(env->config, uregnames[i].opt_bits)) { 1221 cpu_fprintf(f, "%s=%08x%c", uregnames[i].name, env->uregs[i], 1222 (j++ % 4) == 3 ? '\n' : ' '); 1223 } 1224 } 1225 1226 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n"); 1227 1228 for (i = 0; i < 16; ++i) { 1229 cpu_fprintf(f, " A%02d=%08x%c", i, env->regs[i], 1230 (i % 4) == 3 ? '\n' : ' '); 1231 } 1232 1233 xtensa_sync_phys_from_window(env); 1234 cpu_fprintf(f, "\n"); 1235 1236 for (i = 0; i < env->config->nareg; ++i) { 1237 cpu_fprintf(f, "AR%02d=%08x ", i, env->phys_regs[i]); 1238 if (i % 4 == 3) { 1239 bool ws = (env->sregs[WINDOW_START] & (1 << (i / 4))) != 0; 1240 bool cw = env->sregs[WINDOW_BASE] == i / 4; 1241 1242 cpu_fprintf(f, "%c%c\n", ws ? '<' : ' ', cw ? '=' : ' '); 1243 } 1244 } 1245 1246 if (xtensa_option_enabled(env->config, XTENSA_OPTION_FP_COPROCESSOR)) { 1247 cpu_fprintf(f, "\n"); 1248 1249 for (i = 0; i < 16; ++i) { 1250 cpu_fprintf(f, "F%02d=%08x (%+10.8e)%c", i, 1251 float32_val(env->fregs[i].f32[FP_F32_LOW]), 1252 *(float *)(env->fregs[i].f32 + FP_F32_LOW), 1253 (i % 2) == 1 ? '\n' : ' '); 1254 } 1255 } 1256 } 1257 1258 void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb, 1259 target_ulong *data) 1260 { 1261 env->pc = data[0]; 1262 } 1263 1264 static int compare_opcode_ops(const void *a, const void *b) 1265 { 1266 return strcmp((const char *)a, 1267 ((const XtensaOpcodeOps *)b)->name); 1268 } 1269 1270 XtensaOpcodeOps * 1271 xtensa_find_opcode_ops(const XtensaOpcodeTranslators *t, 1272 const char *name) 1273 { 1274 XtensaOpcodeOps *ops; 1275 1276 ops = bsearch(name, t->opcode, t->num_opcodes, 1277 sizeof(XtensaOpcodeOps), compare_opcode_ops); 1278 return ops; 1279 } 1280 1281 static void translate_abs(DisasContext *dc, const uint32_t arg[], 1282 const uint32_t par[]) 1283 { 1284 if (gen_window_check2(dc, arg[0], arg[1])) { 1285 TCGv_i32 zero = tcg_const_i32(0); 1286 TCGv_i32 neg = tcg_temp_new_i32(); 1287 1288 tcg_gen_neg_i32(neg, cpu_R[arg[1]]); 1289 tcg_gen_movcond_i32(TCG_COND_GE, cpu_R[arg[0]], 1290 cpu_R[arg[1]], zero, cpu_R[arg[1]], neg); 1291 tcg_temp_free(neg); 1292 tcg_temp_free(zero); 1293 } 1294 } 1295 1296 static void translate_add(DisasContext *dc, const uint32_t arg[], 1297 const uint32_t par[]) 1298 { 1299 if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { 1300 tcg_gen_add_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); 1301 } 1302 } 1303 1304 static void translate_addi(DisasContext *dc, const uint32_t arg[], 1305 const uint32_t par[]) 1306 { 1307 if (gen_window_check2(dc, arg[0], arg[1])) { 1308 tcg_gen_addi_i32(cpu_R[arg[0]], cpu_R[arg[1]], arg[2]); 1309 } 1310 } 1311 1312 static void translate_addx(DisasContext *dc, const uint32_t arg[], 1313 const uint32_t par[]) 1314 { 1315 if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { 1316 TCGv_i32 tmp = tcg_temp_new_i32(); 1317 tcg_gen_shli_i32(tmp, cpu_R[arg[1]], par[0]); 1318 tcg_gen_add_i32(cpu_R[arg[0]], tmp, cpu_R[arg[2]]); 1319 tcg_temp_free(tmp); 1320 } 1321 } 1322 1323 static void translate_all(DisasContext *dc, const uint32_t arg[], 1324 const uint32_t par[]) 1325 { 1326 uint32_t shift = par[1]; 1327 TCGv_i32 mask = tcg_const_i32(((1 << shift) - 1) << arg[1]); 1328 TCGv_i32 tmp = tcg_temp_new_i32(); 1329 1330 tcg_gen_and_i32(tmp, cpu_SR[BR], mask); 1331 if (par[0]) { 1332 tcg_gen_addi_i32(tmp, tmp, 1 << arg[1]); 1333 } else { 1334 tcg_gen_add_i32(tmp, tmp, mask); 1335 } 1336 tcg_gen_shri_i32(tmp, tmp, arg[1] + shift); 1337 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], 1338 tmp, arg[0], 1); 1339 tcg_temp_free(mask); 1340 tcg_temp_free(tmp); 1341 } 1342 1343 static void translate_and(DisasContext *dc, const uint32_t arg[], 1344 const uint32_t par[]) 1345 { 1346 if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { 1347 tcg_gen_and_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); 1348 } 1349 } 1350 1351 static void translate_ball(DisasContext *dc, const uint32_t arg[], 1352 const uint32_t par[]) 1353 { 1354 if (gen_window_check2(dc, arg[0], arg[1])) { 1355 TCGv_i32 tmp = tcg_temp_new_i32(); 1356 tcg_gen_and_i32(tmp, cpu_R[arg[0]], cpu_R[arg[1]]); 1357 gen_brcond(dc, par[0], tmp, cpu_R[arg[1]], arg[2]); 1358 tcg_temp_free(tmp); 1359 } 1360 } 1361 1362 static void translate_bany(DisasContext *dc, const uint32_t arg[], 1363 const uint32_t par[]) 1364 { 1365 if (gen_window_check2(dc, arg[0], arg[1])) { 1366 TCGv_i32 tmp = tcg_temp_new_i32(); 1367 tcg_gen_and_i32(tmp, cpu_R[arg[0]], cpu_R[arg[1]]); 1368 gen_brcondi(dc, par[0], tmp, 0, arg[2]); 1369 tcg_temp_free(tmp); 1370 } 1371 } 1372 1373 static void translate_b(DisasContext *dc, const uint32_t arg[], 1374 const uint32_t par[]) 1375 { 1376 if (gen_window_check2(dc, arg[0], arg[1])) { 1377 gen_brcond(dc, par[0], cpu_R[arg[0]], cpu_R[arg[1]], arg[2]); 1378 } 1379 } 1380 1381 static void translate_bb(DisasContext *dc, const uint32_t arg[], 1382 const uint32_t par[]) 1383 { 1384 if (gen_window_check2(dc, arg[0], arg[1])) { 1385 #ifdef TARGET_WORDS_BIGENDIAN 1386 TCGv_i32 bit = tcg_const_i32(0x80000000u); 1387 #else 1388 TCGv_i32 bit = tcg_const_i32(0x00000001u); 1389 #endif 1390 TCGv_i32 tmp = tcg_temp_new_i32(); 1391 tcg_gen_andi_i32(tmp, cpu_R[arg[1]], 0x1f); 1392 #ifdef TARGET_WORDS_BIGENDIAN 1393 tcg_gen_shr_i32(bit, bit, tmp); 1394 #else 1395 tcg_gen_shl_i32(bit, bit, tmp); 1396 #endif 1397 tcg_gen_and_i32(tmp, cpu_R[arg[0]], bit); 1398 gen_brcondi(dc, par[0], tmp, 0, arg[2]); 1399 tcg_temp_free(tmp); 1400 tcg_temp_free(bit); 1401 } 1402 } 1403 1404 static void translate_bbi(DisasContext *dc, const uint32_t arg[], 1405 const uint32_t par[]) 1406 { 1407 if (gen_window_check1(dc, arg[0])) { 1408 TCGv_i32 tmp = tcg_temp_new_i32(); 1409 #ifdef TARGET_WORDS_BIGENDIAN 1410 tcg_gen_andi_i32(tmp, cpu_R[arg[0]], 0x80000000u >> arg[1]); 1411 #else 1412 tcg_gen_andi_i32(tmp, cpu_R[arg[0]], 0x00000001u << arg[1]); 1413 #endif 1414 gen_brcondi(dc, par[0], tmp, 0, arg[2]); 1415 tcg_temp_free(tmp); 1416 } 1417 } 1418 1419 static void translate_bi(DisasContext *dc, const uint32_t arg[], 1420 const uint32_t par[]) 1421 { 1422 if (gen_window_check1(dc, arg[0])) { 1423 gen_brcondi(dc, par[0], cpu_R[arg[0]], arg[1], arg[2]); 1424 } 1425 } 1426 1427 static void translate_bz(DisasContext *dc, const uint32_t arg[], 1428 const uint32_t par[]) 1429 { 1430 if (gen_window_check1(dc, arg[0])) { 1431 gen_brcondi(dc, par[0], cpu_R[arg[0]], 0, arg[1]); 1432 } 1433 } 1434 1435 enum { 1436 BOOLEAN_AND, 1437 BOOLEAN_ANDC, 1438 BOOLEAN_OR, 1439 BOOLEAN_ORC, 1440 BOOLEAN_XOR, 1441 }; 1442 1443 static void translate_boolean(DisasContext *dc, const uint32_t arg[], 1444 const uint32_t par[]) 1445 { 1446 static void (* const op[])(TCGv_i32, TCGv_i32, TCGv_i32) = { 1447 [BOOLEAN_AND] = tcg_gen_and_i32, 1448 [BOOLEAN_ANDC] = tcg_gen_andc_i32, 1449 [BOOLEAN_OR] = tcg_gen_or_i32, 1450 [BOOLEAN_ORC] = tcg_gen_orc_i32, 1451 [BOOLEAN_XOR] = tcg_gen_xor_i32, 1452 }; 1453 1454 TCGv_i32 tmp1 = tcg_temp_new_i32(); 1455 TCGv_i32 tmp2 = tcg_temp_new_i32(); 1456 1457 tcg_gen_shri_i32(tmp1, cpu_SR[BR], arg[1]); 1458 tcg_gen_shri_i32(tmp2, cpu_SR[BR], arg[2]); 1459 op[par[0]](tmp1, tmp1, tmp2); 1460 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, arg[0], 1); 1461 tcg_temp_free(tmp1); 1462 tcg_temp_free(tmp2); 1463 } 1464 1465 static void translate_bp(DisasContext *dc, const uint32_t arg[], 1466 const uint32_t par[]) 1467 { 1468 TCGv_i32 tmp = tcg_temp_new_i32(); 1469 1470 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << arg[0]); 1471 gen_brcondi(dc, par[0], tmp, 0, arg[1]); 1472 tcg_temp_free(tmp); 1473 } 1474 1475 static void translate_break(DisasContext *dc, const uint32_t arg[], 1476 const uint32_t par[]) 1477 { 1478 if (dc->debug) { 1479 gen_debug_exception(dc, par[0]); 1480 } 1481 } 1482 1483 static void translate_call0(DisasContext *dc, const uint32_t arg[], 1484 const uint32_t par[]) 1485 { 1486 tcg_gen_movi_i32(cpu_R[0], dc->next_pc); 1487 gen_jumpi(dc, arg[0], 0); 1488 } 1489 1490 static void translate_callw(DisasContext *dc, const uint32_t arg[], 1491 const uint32_t par[]) 1492 { 1493 if (gen_window_check1(dc, par[0] << 2)) { 1494 gen_callwi(dc, par[0], arg[0], 0); 1495 } 1496 } 1497 1498 static void translate_callx0(DisasContext *dc, const uint32_t arg[], 1499 const uint32_t par[]) 1500 { 1501 if (gen_window_check1(dc, arg[0])) { 1502 TCGv_i32 tmp = tcg_temp_new_i32(); 1503 tcg_gen_mov_i32(tmp, cpu_R[arg[0]]); 1504 tcg_gen_movi_i32(cpu_R[0], dc->next_pc); 1505 gen_jump(dc, tmp); 1506 tcg_temp_free(tmp); 1507 } 1508 } 1509 1510 static void translate_callxw(DisasContext *dc, const uint32_t arg[], 1511 const uint32_t par[]) 1512 { 1513 if (gen_window_check2(dc, arg[0], par[0] << 2)) { 1514 TCGv_i32 tmp = tcg_temp_new_i32(); 1515 1516 tcg_gen_mov_i32(tmp, cpu_R[arg[0]]); 1517 gen_callw(dc, par[0], tmp); 1518 tcg_temp_free(tmp); 1519 } 1520 } 1521 1522 static void translate_clamps(DisasContext *dc, const uint32_t arg[], 1523 const uint32_t par[]) 1524 { 1525 if (gen_window_check2(dc, arg[0], arg[1])) { 1526 TCGv_i32 tmp1 = tcg_const_i32(-1u << arg[2]); 1527 TCGv_i32 tmp2 = tcg_const_i32((1 << arg[2]) - 1); 1528 1529 tcg_gen_smax_i32(tmp1, tmp1, cpu_R[arg[1]]); 1530 tcg_gen_smin_i32(cpu_R[arg[0]], tmp1, tmp2); 1531 tcg_temp_free(tmp1); 1532 tcg_temp_free(tmp2); 1533 } 1534 } 1535 1536 static void translate_clrb_expstate(DisasContext *dc, const uint32_t arg[], 1537 const uint32_t par[]) 1538 { 1539 /* TODO: GPIO32 may be a part of coprocessor */ 1540 tcg_gen_andi_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], ~(1u << arg[0])); 1541 } 1542 1543 static void translate_const16(DisasContext *dc, const uint32_t arg[], 1544 const uint32_t par[]) 1545 { 1546 if (gen_window_check1(dc, arg[0])) { 1547 TCGv_i32 c = tcg_const_i32(arg[1]); 1548 1549 tcg_gen_deposit_i32(cpu_R[arg[0]], c, cpu_R[arg[0]], 16, 16); 1550 tcg_temp_free(c); 1551 } 1552 } 1553 1554 /* par[0]: privileged, par[1]: check memory access */ 1555 static void translate_dcache(DisasContext *dc, const uint32_t arg[], 1556 const uint32_t par[]) 1557 { 1558 if ((!par[0] || gen_check_privilege(dc)) && 1559 gen_window_check1(dc, arg[0]) && par[1]) { 1560 TCGv_i32 addr = tcg_temp_new_i32(); 1561 TCGv_i32 res = tcg_temp_new_i32(); 1562 1563 tcg_gen_addi_i32(addr, cpu_R[arg[0]], arg[1]); 1564 tcg_gen_qemu_ld8u(res, addr, dc->cring); 1565 tcg_temp_free(addr); 1566 tcg_temp_free(res); 1567 } 1568 } 1569 1570 static void translate_depbits(DisasContext *dc, const uint32_t arg[], 1571 const uint32_t par[]) 1572 { 1573 if (gen_window_check2(dc, arg[0], arg[1])) { 1574 tcg_gen_deposit_i32(cpu_R[arg[1]], cpu_R[arg[1]], cpu_R[arg[0]], 1575 arg[2], arg[3]); 1576 } 1577 } 1578 1579 static void translate_entry(DisasContext *dc, const uint32_t arg[], 1580 const uint32_t par[]) 1581 { 1582 TCGv_i32 pc = tcg_const_i32(dc->pc); 1583 TCGv_i32 s = tcg_const_i32(arg[0]); 1584 TCGv_i32 imm = tcg_const_i32(arg[1]); 1585 gen_helper_entry(cpu_env, pc, s, imm); 1586 tcg_temp_free(imm); 1587 tcg_temp_free(s); 1588 tcg_temp_free(pc); 1589 /* This can change tb->flags, so exit tb */ 1590 gen_jumpi_check_loop_end(dc, -1); 1591 } 1592 1593 static void translate_extui(DisasContext *dc, const uint32_t arg[], 1594 const uint32_t par[]) 1595 { 1596 if (gen_window_check2(dc, arg[0], arg[1])) { 1597 int maskimm = (1 << arg[3]) - 1; 1598 1599 TCGv_i32 tmp = tcg_temp_new_i32(); 1600 tcg_gen_shri_i32(tmp, cpu_R[arg[1]], arg[2]); 1601 tcg_gen_andi_i32(cpu_R[arg[0]], tmp, maskimm); 1602 tcg_temp_free(tmp); 1603 } 1604 } 1605 1606 /* par[0]: privileged, par[1]: check memory access */ 1607 static void translate_icache(DisasContext *dc, const uint32_t arg[], 1608 const uint32_t par[]) 1609 { 1610 if ((!par[0] || gen_check_privilege(dc)) && 1611 gen_window_check1(dc, arg[0]) && par[1]) { 1612 #ifndef CONFIG_USER_ONLY 1613 TCGv_i32 addr = tcg_temp_new_i32(); 1614 1615 tcg_gen_movi_i32(cpu_pc, dc->pc); 1616 tcg_gen_addi_i32(addr, cpu_R[arg[0]], arg[1]); 1617 gen_helper_itlb_hit_test(cpu_env, addr); 1618 tcg_temp_free(addr); 1619 #endif 1620 } 1621 } 1622 1623 static void translate_itlb(DisasContext *dc, const uint32_t arg[], 1624 const uint32_t par[]) 1625 { 1626 if (gen_check_privilege(dc) && 1627 gen_window_check1(dc, arg[0])) { 1628 #ifndef CONFIG_USER_ONLY 1629 TCGv_i32 dtlb = tcg_const_i32(par[0]); 1630 1631 gen_helper_itlb(cpu_env, cpu_R[arg[0]], dtlb); 1632 /* This could change memory mapping, so exit tb */ 1633 gen_jumpi_check_loop_end(dc, -1); 1634 tcg_temp_free(dtlb); 1635 #endif 1636 } 1637 } 1638 1639 static void translate_ill(DisasContext *dc, const uint32_t arg[], 1640 const uint32_t par[]) 1641 { 1642 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); 1643 } 1644 1645 static void translate_j(DisasContext *dc, const uint32_t arg[], 1646 const uint32_t par[]) 1647 { 1648 gen_jumpi(dc, arg[0], 0); 1649 } 1650 1651 static void translate_jx(DisasContext *dc, const uint32_t arg[], 1652 const uint32_t par[]) 1653 { 1654 if (gen_window_check1(dc, arg[0])) { 1655 gen_jump(dc, cpu_R[arg[0]]); 1656 } 1657 } 1658 1659 static void translate_l32e(DisasContext *dc, const uint32_t arg[], 1660 const uint32_t par[]) 1661 { 1662 if (gen_check_privilege(dc) && 1663 gen_window_check2(dc, arg[0], arg[1])) { 1664 TCGv_i32 addr = tcg_temp_new_i32(); 1665 1666 tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]); 1667 gen_load_store_alignment(dc, 2, addr, false); 1668 tcg_gen_qemu_ld_tl(cpu_R[arg[0]], addr, dc->ring, MO_TEUL); 1669 tcg_temp_free(addr); 1670 } 1671 } 1672 1673 static void translate_ldst(DisasContext *dc, const uint32_t arg[], 1674 const uint32_t par[]) 1675 { 1676 if (gen_window_check2(dc, arg[0], arg[1])) { 1677 TCGv_i32 addr = tcg_temp_new_i32(); 1678 1679 tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]); 1680 if (par[0] & MO_SIZE) { 1681 gen_load_store_alignment(dc, par[0] & MO_SIZE, addr, par[1]); 1682 } 1683 if (par[2]) { 1684 if (par[1]) { 1685 tcg_gen_mb(TCG_BAR_STRL | TCG_MO_ALL); 1686 } 1687 tcg_gen_qemu_st_tl(cpu_R[arg[0]], addr, dc->cring, par[0]); 1688 } else { 1689 tcg_gen_qemu_ld_tl(cpu_R[arg[0]], addr, dc->cring, par[0]); 1690 if (par[1]) { 1691 tcg_gen_mb(TCG_BAR_LDAQ | TCG_MO_ALL); 1692 } 1693 } 1694 tcg_temp_free(addr); 1695 } 1696 } 1697 1698 static void translate_l32r(DisasContext *dc, const uint32_t arg[], 1699 const uint32_t par[]) 1700 { 1701 if (gen_window_check1(dc, arg[0])) { 1702 TCGv_i32 tmp; 1703 1704 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) { 1705 tmp = tcg_const_i32(dc->raw_arg[1] - 1); 1706 tcg_gen_add_i32(tmp, cpu_SR[LITBASE], tmp); 1707 } else { 1708 tmp = tcg_const_i32(arg[1]); 1709 } 1710 tcg_gen_qemu_ld32u(cpu_R[arg[0]], tmp, dc->cring); 1711 tcg_temp_free(tmp); 1712 } 1713 } 1714 1715 static void translate_loop(DisasContext *dc, const uint32_t arg[], 1716 const uint32_t par[]) 1717 { 1718 if (gen_window_check1(dc, arg[0])) { 1719 uint32_t lend = arg[1]; 1720 TCGv_i32 tmp = tcg_const_i32(lend); 1721 1722 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[arg[0]], 1); 1723 tcg_gen_movi_i32(cpu_SR[LBEG], dc->next_pc); 1724 gen_helper_wsr_lend(cpu_env, tmp); 1725 tcg_temp_free(tmp); 1726 1727 if (par[0] != TCG_COND_NEVER) { 1728 TCGLabel *label = gen_new_label(); 1729 tcg_gen_brcondi_i32(par[0], cpu_R[arg[0]], 0, label); 1730 gen_jumpi(dc, lend, 1); 1731 gen_set_label(label); 1732 } 1733 1734 gen_jumpi(dc, dc->next_pc, 0); 1735 } 1736 } 1737 1738 enum { 1739 MAC16_UMUL, 1740 MAC16_MUL, 1741 MAC16_MULA, 1742 MAC16_MULS, 1743 MAC16_NONE, 1744 }; 1745 1746 enum { 1747 MAC16_LL, 1748 MAC16_HL, 1749 MAC16_LH, 1750 MAC16_HH, 1751 1752 MAC16_HX = 0x1, 1753 MAC16_XH = 0x2, 1754 }; 1755 1756 enum { 1757 MAC16_AA, 1758 MAC16_AD, 1759 MAC16_DA, 1760 MAC16_DD, 1761 1762 MAC16_XD = 0x1, 1763 MAC16_DX = 0x2, 1764 }; 1765 1766 static void translate_mac16(DisasContext *dc, const uint32_t arg[], 1767 const uint32_t par[]) 1768 { 1769 int op = par[0]; 1770 bool is_m1_sr = par[1] & MAC16_DX; 1771 bool is_m2_sr = par[1] & MAC16_XD; 1772 unsigned half = par[2]; 1773 uint32_t ld_offset = par[3]; 1774 unsigned off = ld_offset ? 2 : 0; 1775 uint32_t ar[3] = {0}; 1776 unsigned n_ar = 0; 1777 1778 if (op != MAC16_NONE) { 1779 if (!is_m1_sr) { 1780 ar[n_ar++] = arg[off]; 1781 } 1782 if (!is_m2_sr) { 1783 ar[n_ar++] = arg[off + 1]; 1784 } 1785 } 1786 1787 if (ld_offset) { 1788 ar[n_ar++] = arg[1]; 1789 } 1790 1791 if (gen_window_check3(dc, ar[0], ar[1], ar[2])) { 1792 TCGv_i32 vaddr = tcg_temp_new_i32(); 1793 TCGv_i32 mem32 = tcg_temp_new_i32(); 1794 1795 if (ld_offset) { 1796 tcg_gen_addi_i32(vaddr, cpu_R[arg[1]], ld_offset); 1797 gen_load_store_alignment(dc, 2, vaddr, false); 1798 tcg_gen_qemu_ld32u(mem32, vaddr, dc->cring); 1799 } 1800 if (op != MAC16_NONE) { 1801 TCGv_i32 m1 = gen_mac16_m(is_m1_sr ? 1802 cpu_SR[MR + arg[off]] : 1803 cpu_R[arg[off]], 1804 half & MAC16_HX, op == MAC16_UMUL); 1805 TCGv_i32 m2 = gen_mac16_m(is_m2_sr ? 1806 cpu_SR[MR + arg[off + 1]] : 1807 cpu_R[arg[off + 1]], 1808 half & MAC16_XH, op == MAC16_UMUL); 1809 1810 if (op == MAC16_MUL || op == MAC16_UMUL) { 1811 tcg_gen_mul_i32(cpu_SR[ACCLO], m1, m2); 1812 if (op == MAC16_UMUL) { 1813 tcg_gen_movi_i32(cpu_SR[ACCHI], 0); 1814 } else { 1815 tcg_gen_sari_i32(cpu_SR[ACCHI], cpu_SR[ACCLO], 31); 1816 } 1817 } else { 1818 TCGv_i32 lo = tcg_temp_new_i32(); 1819 TCGv_i32 hi = tcg_temp_new_i32(); 1820 1821 tcg_gen_mul_i32(lo, m1, m2); 1822 tcg_gen_sari_i32(hi, lo, 31); 1823 if (op == MAC16_MULA) { 1824 tcg_gen_add2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI], 1825 cpu_SR[ACCLO], cpu_SR[ACCHI], 1826 lo, hi); 1827 } else { 1828 tcg_gen_sub2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI], 1829 cpu_SR[ACCLO], cpu_SR[ACCHI], 1830 lo, hi); 1831 } 1832 tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]); 1833 1834 tcg_temp_free_i32(lo); 1835 tcg_temp_free_i32(hi); 1836 } 1837 tcg_temp_free(m1); 1838 tcg_temp_free(m2); 1839 } 1840 if (ld_offset) { 1841 tcg_gen_mov_i32(cpu_R[arg[1]], vaddr); 1842 tcg_gen_mov_i32(cpu_SR[MR + arg[0]], mem32); 1843 } 1844 tcg_temp_free(vaddr); 1845 tcg_temp_free(mem32); 1846 } 1847 } 1848 1849 static void translate_memw(DisasContext *dc, const uint32_t arg[], 1850 const uint32_t par[]) 1851 { 1852 tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); 1853 } 1854 1855 static void translate_smin(DisasContext *dc, const uint32_t arg[], 1856 const uint32_t par[]) 1857 { 1858 if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { 1859 tcg_gen_smin_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); 1860 } 1861 } 1862 1863 static void translate_umin(DisasContext *dc, const uint32_t arg[], 1864 const uint32_t par[]) 1865 { 1866 if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { 1867 tcg_gen_umin_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); 1868 } 1869 } 1870 1871 static void translate_smax(DisasContext *dc, const uint32_t arg[], 1872 const uint32_t par[]) 1873 { 1874 if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { 1875 tcg_gen_smax_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); 1876 } 1877 } 1878 1879 static void translate_umax(DisasContext *dc, const uint32_t arg[], 1880 const uint32_t par[]) 1881 { 1882 if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { 1883 tcg_gen_umax_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); 1884 } 1885 } 1886 1887 static void translate_mov(DisasContext *dc, const uint32_t arg[], 1888 const uint32_t par[]) 1889 { 1890 if (gen_window_check2(dc, arg[0], arg[1])) { 1891 tcg_gen_mov_i32(cpu_R[arg[0]], cpu_R[arg[1]]); 1892 } 1893 } 1894 1895 static void translate_movcond(DisasContext *dc, const uint32_t arg[], 1896 const uint32_t par[]) 1897 { 1898 if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { 1899 TCGv_i32 zero = tcg_const_i32(0); 1900 1901 tcg_gen_movcond_i32(par[0], cpu_R[arg[0]], 1902 cpu_R[arg[2]], zero, cpu_R[arg[1]], cpu_R[arg[0]]); 1903 tcg_temp_free(zero); 1904 } 1905 } 1906 1907 static void translate_movi(DisasContext *dc, const uint32_t arg[], 1908 const uint32_t par[]) 1909 { 1910 if (gen_window_check1(dc, arg[0])) { 1911 tcg_gen_movi_i32(cpu_R[arg[0]], arg[1]); 1912 } 1913 } 1914 1915 static void translate_movp(DisasContext *dc, const uint32_t arg[], 1916 const uint32_t par[]) 1917 { 1918 if (gen_window_check2(dc, arg[0], arg[1])) { 1919 TCGv_i32 zero = tcg_const_i32(0); 1920 TCGv_i32 tmp = tcg_temp_new_i32(); 1921 1922 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << arg[2]); 1923 tcg_gen_movcond_i32(par[0], 1924 cpu_R[arg[0]], tmp, zero, 1925 cpu_R[arg[1]], cpu_R[arg[0]]); 1926 tcg_temp_free(tmp); 1927 tcg_temp_free(zero); 1928 } 1929 } 1930 1931 static void translate_movsp(DisasContext *dc, const uint32_t arg[], 1932 const uint32_t par[]) 1933 { 1934 if (gen_window_check2(dc, arg[0], arg[1])) { 1935 TCGv_i32 pc = tcg_const_i32(dc->pc); 1936 gen_helper_movsp(cpu_env, pc); 1937 tcg_gen_mov_i32(cpu_R[arg[0]], cpu_R[arg[1]]); 1938 tcg_temp_free(pc); 1939 } 1940 } 1941 1942 static void translate_mul16(DisasContext *dc, const uint32_t arg[], 1943 const uint32_t par[]) 1944 { 1945 if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { 1946 TCGv_i32 v1 = tcg_temp_new_i32(); 1947 TCGv_i32 v2 = tcg_temp_new_i32(); 1948 1949 if (par[0]) { 1950 tcg_gen_ext16s_i32(v1, cpu_R[arg[1]]); 1951 tcg_gen_ext16s_i32(v2, cpu_R[arg[2]]); 1952 } else { 1953 tcg_gen_ext16u_i32(v1, cpu_R[arg[1]]); 1954 tcg_gen_ext16u_i32(v2, cpu_R[arg[2]]); 1955 } 1956 tcg_gen_mul_i32(cpu_R[arg[0]], v1, v2); 1957 tcg_temp_free(v2); 1958 tcg_temp_free(v1); 1959 } 1960 } 1961 1962 static void translate_mull(DisasContext *dc, const uint32_t arg[], 1963 const uint32_t par[]) 1964 { 1965 if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { 1966 tcg_gen_mul_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); 1967 } 1968 } 1969 1970 static void translate_mulh(DisasContext *dc, const uint32_t arg[], 1971 const uint32_t par[]) 1972 { 1973 if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { 1974 TCGv_i32 lo = tcg_temp_new(); 1975 1976 if (par[0]) { 1977 tcg_gen_muls2_i32(lo, cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); 1978 } else { 1979 tcg_gen_mulu2_i32(lo, cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); 1980 } 1981 tcg_temp_free(lo); 1982 } 1983 } 1984 1985 static void translate_neg(DisasContext *dc, const uint32_t arg[], 1986 const uint32_t par[]) 1987 { 1988 if (gen_window_check2(dc, arg[0], arg[1])) { 1989 tcg_gen_neg_i32(cpu_R[arg[0]], cpu_R[arg[1]]); 1990 } 1991 } 1992 1993 static void translate_nop(DisasContext *dc, const uint32_t arg[], 1994 const uint32_t par[]) 1995 { 1996 } 1997 1998 static void translate_nsa(DisasContext *dc, const uint32_t arg[], 1999 const uint32_t par[]) 2000 { 2001 if (gen_window_check2(dc, arg[0], arg[1])) { 2002 tcg_gen_clrsb_i32(cpu_R[arg[0]], cpu_R[arg[1]]); 2003 } 2004 } 2005 2006 static void translate_nsau(DisasContext *dc, const uint32_t arg[], 2007 const uint32_t par[]) 2008 { 2009 if (gen_window_check2(dc, arg[0], arg[1])) { 2010 tcg_gen_clzi_i32(cpu_R[arg[0]], cpu_R[arg[1]], 32); 2011 } 2012 } 2013 2014 static void translate_or(DisasContext *dc, const uint32_t arg[], 2015 const uint32_t par[]) 2016 { 2017 if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { 2018 tcg_gen_or_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); 2019 } 2020 } 2021 2022 static void translate_ptlb(DisasContext *dc, const uint32_t arg[], 2023 const uint32_t par[]) 2024 { 2025 if (gen_check_privilege(dc) && 2026 gen_window_check2(dc, arg[0], arg[1])) { 2027 #ifndef CONFIG_USER_ONLY 2028 TCGv_i32 dtlb = tcg_const_i32(par[0]); 2029 2030 tcg_gen_movi_i32(cpu_pc, dc->pc); 2031 gen_helper_ptlb(cpu_R[arg[0]], cpu_env, cpu_R[arg[1]], dtlb); 2032 tcg_temp_free(dtlb); 2033 #endif 2034 } 2035 } 2036 2037 static void gen_zero_check(DisasContext *dc, const uint32_t arg[]) 2038 { 2039 TCGLabel *label = gen_new_label(); 2040 2041 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[arg[2]], 0, label); 2042 gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE); 2043 gen_set_label(label); 2044 } 2045 2046 static void translate_quos(DisasContext *dc, const uint32_t arg[], 2047 const uint32_t par[]) 2048 { 2049 if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { 2050 TCGLabel *label1 = gen_new_label(); 2051 TCGLabel *label2 = gen_new_label(); 2052 2053 gen_zero_check(dc, arg); 2054 2055 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[arg[1]], 0x80000000, 2056 label1); 2057 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[arg[2]], 0xffffffff, 2058 label1); 2059 tcg_gen_movi_i32(cpu_R[arg[0]], 2060 par[0] ? 0x80000000 : 0); 2061 tcg_gen_br(label2); 2062 gen_set_label(label1); 2063 if (par[0]) { 2064 tcg_gen_div_i32(cpu_R[arg[0]], 2065 cpu_R[arg[1]], cpu_R[arg[2]]); 2066 } else { 2067 tcg_gen_rem_i32(cpu_R[arg[0]], 2068 cpu_R[arg[1]], cpu_R[arg[2]]); 2069 } 2070 gen_set_label(label2); 2071 } 2072 } 2073 2074 static void translate_quou(DisasContext *dc, const uint32_t arg[], 2075 const uint32_t par[]) 2076 { 2077 if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { 2078 gen_zero_check(dc, arg); 2079 if (par[0]) { 2080 tcg_gen_divu_i32(cpu_R[arg[0]], 2081 cpu_R[arg[1]], cpu_R[arg[2]]); 2082 } else { 2083 tcg_gen_remu_i32(cpu_R[arg[0]], 2084 cpu_R[arg[1]], cpu_R[arg[2]]); 2085 } 2086 } 2087 } 2088 2089 static void translate_read_impwire(DisasContext *dc, const uint32_t arg[], 2090 const uint32_t par[]) 2091 { 2092 if (gen_window_check1(dc, arg[0])) { 2093 /* TODO: GPIO32 may be a part of coprocessor */ 2094 tcg_gen_movi_i32(cpu_R[arg[0]], 0); 2095 } 2096 } 2097 2098 static void translate_rer(DisasContext *dc, const uint32_t arg[], 2099 const uint32_t par[]) 2100 { 2101 if (gen_check_privilege(dc) && 2102 gen_window_check2(dc, arg[0], arg[1])) { 2103 gen_helper_rer(cpu_R[arg[0]], cpu_env, cpu_R[arg[1]]); 2104 } 2105 } 2106 2107 static void translate_ret(DisasContext *dc, const uint32_t arg[], 2108 const uint32_t par[]) 2109 { 2110 gen_jump(dc, cpu_R[0]); 2111 } 2112 2113 static void translate_retw(DisasContext *dc, const uint32_t arg[], 2114 const uint32_t par[]) 2115 { 2116 TCGv_i32 tmp = tcg_const_i32(dc->pc); 2117 gen_helper_retw(tmp, cpu_env, tmp); 2118 gen_jump(dc, tmp); 2119 tcg_temp_free(tmp); 2120 } 2121 2122 static void translate_rfde(DisasContext *dc, const uint32_t arg[], 2123 const uint32_t par[]) 2124 { 2125 if (gen_check_privilege(dc)) { 2126 gen_jump(dc, cpu_SR[dc->config->ndepc ? DEPC : EPC1]); 2127 } 2128 } 2129 2130 static void translate_rfe(DisasContext *dc, const uint32_t arg[], 2131 const uint32_t par[]) 2132 { 2133 if (gen_check_privilege(dc)) { 2134 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); 2135 gen_check_interrupts(dc); 2136 gen_jump(dc, cpu_SR[EPC1]); 2137 } 2138 } 2139 2140 static void translate_rfi(DisasContext *dc, const uint32_t arg[], 2141 const uint32_t par[]) 2142 { 2143 if (gen_check_privilege(dc)) { 2144 tcg_gen_mov_i32(cpu_SR[PS], cpu_SR[EPS2 + arg[0] - 2]); 2145 gen_check_interrupts(dc); 2146 gen_jump(dc, cpu_SR[EPC1 + arg[0] - 1]); 2147 } 2148 } 2149 2150 static void translate_rfw(DisasContext *dc, const uint32_t arg[], 2151 const uint32_t par[]) 2152 { 2153 if (gen_check_privilege(dc)) { 2154 TCGv_i32 tmp = tcg_const_i32(1); 2155 2156 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); 2157 tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]); 2158 2159 if (par[0]) { 2160 tcg_gen_andc_i32(cpu_SR[WINDOW_START], 2161 cpu_SR[WINDOW_START], tmp); 2162 } else { 2163 tcg_gen_or_i32(cpu_SR[WINDOW_START], 2164 cpu_SR[WINDOW_START], tmp); 2165 } 2166 2167 gen_helper_restore_owb(cpu_env); 2168 gen_check_interrupts(dc); 2169 gen_jump(dc, cpu_SR[EPC1]); 2170 2171 tcg_temp_free(tmp); 2172 } 2173 } 2174 2175 static void translate_rotw(DisasContext *dc, const uint32_t arg[], 2176 const uint32_t par[]) 2177 { 2178 if (gen_check_privilege(dc)) { 2179 TCGv_i32 tmp = tcg_const_i32(arg[0]); 2180 gen_helper_rotw(cpu_env, tmp); 2181 tcg_temp_free(tmp); 2182 /* This can change tb->flags, so exit tb */ 2183 gen_jumpi_check_loop_end(dc, -1); 2184 } 2185 } 2186 2187 static void translate_rsil(DisasContext *dc, const uint32_t arg[], 2188 const uint32_t par[]) 2189 { 2190 if (gen_check_privilege(dc) && 2191 gen_window_check1(dc, arg[0])) { 2192 tcg_gen_mov_i32(cpu_R[arg[0]], cpu_SR[PS]); 2193 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL); 2194 tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], arg[1]); 2195 gen_check_interrupts(dc); 2196 gen_jumpi_check_loop_end(dc, 0); 2197 } 2198 } 2199 2200 static void translate_rsr(DisasContext *dc, const uint32_t arg[], 2201 const uint32_t par[]) 2202 { 2203 if (gen_check_sr(dc, par[0], SR_R) && 2204 (par[0] < 64 || gen_check_privilege(dc)) && 2205 gen_window_check1(dc, arg[0])) { 2206 if (gen_rsr(dc, cpu_R[arg[0]], par[0])) { 2207 gen_jumpi_check_loop_end(dc, 0); 2208 } 2209 } 2210 } 2211 2212 static void translate_rtlb(DisasContext *dc, const uint32_t arg[], 2213 const uint32_t par[]) 2214 { 2215 static void (* const helper[])(TCGv_i32 r, TCGv_env env, TCGv_i32 a1, 2216 TCGv_i32 a2) = { 2217 #ifndef CONFIG_USER_ONLY 2218 gen_helper_rtlb0, 2219 gen_helper_rtlb1, 2220 #endif 2221 }; 2222 2223 if (gen_check_privilege(dc) && 2224 gen_window_check2(dc, arg[0], arg[1])) { 2225 TCGv_i32 dtlb = tcg_const_i32(par[0]); 2226 2227 helper[par[1]](cpu_R[arg[0]], cpu_env, cpu_R[arg[1]], dtlb); 2228 tcg_temp_free(dtlb); 2229 } 2230 } 2231 2232 static void translate_rur(DisasContext *dc, const uint32_t arg[], 2233 const uint32_t par[]) 2234 { 2235 if (gen_window_check1(dc, arg[0])) { 2236 if (uregnames[par[0]].name) { 2237 tcg_gen_mov_i32(cpu_R[arg[0]], cpu_UR[par[0]]); 2238 } else { 2239 qemu_log_mask(LOG_UNIMP, "RUR %d not implemented, ", par[0]); 2240 } 2241 } 2242 } 2243 2244 static void translate_setb_expstate(DisasContext *dc, const uint32_t arg[], 2245 const uint32_t par[]) 2246 { 2247 /* TODO: GPIO32 may be a part of coprocessor */ 2248 tcg_gen_ori_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], 1u << arg[0]); 2249 } 2250 2251 #ifdef CONFIG_USER_ONLY 2252 static void gen_check_atomctl(DisasContext *dc, TCGv_i32 addr) 2253 { 2254 } 2255 #else 2256 static void gen_check_atomctl(DisasContext *dc, TCGv_i32 addr) 2257 { 2258 TCGv_i32 tpc = tcg_const_i32(dc->pc); 2259 2260 gen_helper_check_atomctl(cpu_env, tpc, addr); 2261 tcg_temp_free(tpc); 2262 } 2263 #endif 2264 2265 static void translate_s32c1i(DisasContext *dc, const uint32_t arg[], 2266 const uint32_t par[]) 2267 { 2268 if (gen_window_check2(dc, arg[0], arg[1])) { 2269 TCGv_i32 tmp = tcg_temp_local_new_i32(); 2270 TCGv_i32 addr = tcg_temp_local_new_i32(); 2271 2272 tcg_gen_mov_i32(tmp, cpu_R[arg[0]]); 2273 tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]); 2274 gen_load_store_alignment(dc, 2, addr, true); 2275 gen_check_atomctl(dc, addr); 2276 tcg_gen_atomic_cmpxchg_i32(cpu_R[arg[0]], addr, cpu_SR[SCOMPARE1], 2277 tmp, dc->cring, MO_32); 2278 tcg_temp_free(addr); 2279 tcg_temp_free(tmp); 2280 } 2281 } 2282 2283 static void translate_s32e(DisasContext *dc, const uint32_t arg[], 2284 const uint32_t par[]) 2285 { 2286 if (gen_check_privilege(dc) && 2287 gen_window_check2(dc, arg[0], arg[1])) { 2288 TCGv_i32 addr = tcg_temp_new_i32(); 2289 2290 tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]); 2291 gen_load_store_alignment(dc, 2, addr, false); 2292 tcg_gen_qemu_st_tl(cpu_R[arg[0]], addr, dc->ring, MO_TEUL); 2293 tcg_temp_free(addr); 2294 } 2295 } 2296 2297 static void translate_salt(DisasContext *dc, const uint32_t arg[], 2298 const uint32_t par[]) 2299 { 2300 if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { 2301 tcg_gen_setcond_i32(par[0], 2302 cpu_R[arg[0]], 2303 cpu_R[arg[1]], cpu_R[arg[2]]); 2304 } 2305 } 2306 2307 static void translate_sext(DisasContext *dc, const uint32_t arg[], 2308 const uint32_t par[]) 2309 { 2310 if (gen_window_check2(dc, arg[0], arg[1])) { 2311 int shift = 31 - arg[2]; 2312 2313 if (shift == 24) { 2314 tcg_gen_ext8s_i32(cpu_R[arg[0]], cpu_R[arg[1]]); 2315 } else if (shift == 16) { 2316 tcg_gen_ext16s_i32(cpu_R[arg[0]], cpu_R[arg[1]]); 2317 } else { 2318 TCGv_i32 tmp = tcg_temp_new_i32(); 2319 tcg_gen_shli_i32(tmp, cpu_R[arg[1]], shift); 2320 tcg_gen_sari_i32(cpu_R[arg[0]], tmp, shift); 2321 tcg_temp_free(tmp); 2322 } 2323 } 2324 } 2325 2326 static void translate_simcall(DisasContext *dc, const uint32_t arg[], 2327 const uint32_t par[]) 2328 { 2329 #ifndef CONFIG_USER_ONLY 2330 if (semihosting_enabled()) { 2331 if (gen_check_privilege(dc)) { 2332 gen_helper_simcall(cpu_env); 2333 } 2334 } else 2335 #endif 2336 { 2337 qemu_log_mask(LOG_GUEST_ERROR, "SIMCALL but semihosting is disabled\n"); 2338 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); 2339 } 2340 } 2341 2342 /* 2343 * Note: 64 bit ops are used here solely because SAR values 2344 * have range 0..63 2345 */ 2346 #define gen_shift_reg(cmd, reg) do { \ 2347 TCGv_i64 tmp = tcg_temp_new_i64(); \ 2348 tcg_gen_extu_i32_i64(tmp, reg); \ 2349 tcg_gen_##cmd##_i64(v, v, tmp); \ 2350 tcg_gen_extrl_i64_i32(cpu_R[arg[0]], v); \ 2351 tcg_temp_free_i64(v); \ 2352 tcg_temp_free_i64(tmp); \ 2353 } while (0) 2354 2355 #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR]) 2356 2357 static void translate_sll(DisasContext *dc, const uint32_t arg[], 2358 const uint32_t par[]) 2359 { 2360 if (gen_window_check2(dc, arg[0], arg[1])) { 2361 if (dc->sar_m32_5bit) { 2362 tcg_gen_shl_i32(cpu_R[arg[0]], cpu_R[arg[1]], dc->sar_m32); 2363 } else { 2364 TCGv_i64 v = tcg_temp_new_i64(); 2365 TCGv_i32 s = tcg_const_i32(32); 2366 tcg_gen_sub_i32(s, s, cpu_SR[SAR]); 2367 tcg_gen_andi_i32(s, s, 0x3f); 2368 tcg_gen_extu_i32_i64(v, cpu_R[arg[1]]); 2369 gen_shift_reg(shl, s); 2370 tcg_temp_free(s); 2371 } 2372 } 2373 } 2374 2375 static void translate_slli(DisasContext *dc, const uint32_t arg[], 2376 const uint32_t par[]) 2377 { 2378 if (gen_window_check2(dc, arg[0], arg[1])) { 2379 if (arg[2] == 32) { 2380 qemu_log_mask(LOG_GUEST_ERROR, "slli a%d, a%d, 32 is undefined", 2381 arg[0], arg[1]); 2382 } 2383 tcg_gen_shli_i32(cpu_R[arg[0]], cpu_R[arg[1]], arg[2] & 0x1f); 2384 } 2385 } 2386 2387 static void translate_sra(DisasContext *dc, const uint32_t arg[], 2388 const uint32_t par[]) 2389 { 2390 if (gen_window_check2(dc, arg[0], arg[1])) { 2391 if (dc->sar_m32_5bit) { 2392 tcg_gen_sar_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_SR[SAR]); 2393 } else { 2394 TCGv_i64 v = tcg_temp_new_i64(); 2395 tcg_gen_ext_i32_i64(v, cpu_R[arg[1]]); 2396 gen_shift(sar); 2397 } 2398 } 2399 } 2400 2401 static void translate_srai(DisasContext *dc, const uint32_t arg[], 2402 const uint32_t par[]) 2403 { 2404 if (gen_window_check2(dc, arg[0], arg[1])) { 2405 tcg_gen_sari_i32(cpu_R[arg[0]], cpu_R[arg[1]], arg[2]); 2406 } 2407 } 2408 2409 static void translate_src(DisasContext *dc, const uint32_t arg[], 2410 const uint32_t par[]) 2411 { 2412 if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { 2413 TCGv_i64 v = tcg_temp_new_i64(); 2414 tcg_gen_concat_i32_i64(v, cpu_R[arg[2]], cpu_R[arg[1]]); 2415 gen_shift(shr); 2416 } 2417 } 2418 2419 static void translate_srl(DisasContext *dc, const uint32_t arg[], 2420 const uint32_t par[]) 2421 { 2422 if (gen_window_check2(dc, arg[0], arg[1])) { 2423 if (dc->sar_m32_5bit) { 2424 tcg_gen_shr_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_SR[SAR]); 2425 } else { 2426 TCGv_i64 v = tcg_temp_new_i64(); 2427 tcg_gen_extu_i32_i64(v, cpu_R[arg[1]]); 2428 gen_shift(shr); 2429 } 2430 } 2431 } 2432 2433 #undef gen_shift 2434 #undef gen_shift_reg 2435 2436 static void translate_srli(DisasContext *dc, const uint32_t arg[], 2437 const uint32_t par[]) 2438 { 2439 if (gen_window_check2(dc, arg[0], arg[1])) { 2440 tcg_gen_shri_i32(cpu_R[arg[0]], cpu_R[arg[1]], arg[2]); 2441 } 2442 } 2443 2444 static void translate_ssa8b(DisasContext *dc, const uint32_t arg[], 2445 const uint32_t par[]) 2446 { 2447 if (gen_window_check1(dc, arg[0])) { 2448 TCGv_i32 tmp = tcg_temp_new_i32(); 2449 tcg_gen_shli_i32(tmp, cpu_R[arg[0]], 3); 2450 gen_left_shift_sar(dc, tmp); 2451 tcg_temp_free(tmp); 2452 } 2453 } 2454 2455 static void translate_ssa8l(DisasContext *dc, const uint32_t arg[], 2456 const uint32_t par[]) 2457 { 2458 if (gen_window_check1(dc, arg[0])) { 2459 TCGv_i32 tmp = tcg_temp_new_i32(); 2460 tcg_gen_shli_i32(tmp, cpu_R[arg[0]], 3); 2461 gen_right_shift_sar(dc, tmp); 2462 tcg_temp_free(tmp); 2463 } 2464 } 2465 2466 static void translate_ssai(DisasContext *dc, const uint32_t arg[], 2467 const uint32_t par[]) 2468 { 2469 TCGv_i32 tmp = tcg_const_i32(arg[0]); 2470 gen_right_shift_sar(dc, tmp); 2471 tcg_temp_free(tmp); 2472 } 2473 2474 static void translate_ssl(DisasContext *dc, const uint32_t arg[], 2475 const uint32_t par[]) 2476 { 2477 if (gen_window_check1(dc, arg[0])) { 2478 gen_left_shift_sar(dc, cpu_R[arg[0]]); 2479 } 2480 } 2481 2482 static void translate_ssr(DisasContext *dc, const uint32_t arg[], 2483 const uint32_t par[]) 2484 { 2485 if (gen_window_check1(dc, arg[0])) { 2486 gen_right_shift_sar(dc, cpu_R[arg[0]]); 2487 } 2488 } 2489 2490 static void translate_sub(DisasContext *dc, const uint32_t arg[], 2491 const uint32_t par[]) 2492 { 2493 if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { 2494 tcg_gen_sub_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); 2495 } 2496 } 2497 2498 static void translate_subx(DisasContext *dc, const uint32_t arg[], 2499 const uint32_t par[]) 2500 { 2501 if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { 2502 TCGv_i32 tmp = tcg_temp_new_i32(); 2503 tcg_gen_shli_i32(tmp, cpu_R[arg[1]], par[0]); 2504 tcg_gen_sub_i32(cpu_R[arg[0]], tmp, cpu_R[arg[2]]); 2505 tcg_temp_free(tmp); 2506 } 2507 } 2508 2509 static void translate_syscall(DisasContext *dc, const uint32_t arg[], 2510 const uint32_t par[]) 2511 { 2512 gen_exception_cause(dc, SYSCALL_CAUSE); 2513 } 2514 2515 static void translate_waiti(DisasContext *dc, const uint32_t arg[], 2516 const uint32_t par[]) 2517 { 2518 if (gen_check_privilege(dc)) { 2519 #ifndef CONFIG_USER_ONLY 2520 gen_waiti(dc, arg[0]); 2521 #endif 2522 } 2523 } 2524 2525 static void translate_wtlb(DisasContext *dc, const uint32_t arg[], 2526 const uint32_t par[]) 2527 { 2528 if (gen_check_privilege(dc) && 2529 gen_window_check2(dc, arg[0], arg[1])) { 2530 #ifndef CONFIG_USER_ONLY 2531 TCGv_i32 dtlb = tcg_const_i32(par[0]); 2532 2533 gen_helper_wtlb(cpu_env, cpu_R[arg[0]], cpu_R[arg[1]], dtlb); 2534 /* This could change memory mapping, so exit tb */ 2535 gen_jumpi_check_loop_end(dc, -1); 2536 tcg_temp_free(dtlb); 2537 #endif 2538 } 2539 } 2540 2541 static void translate_wer(DisasContext *dc, const uint32_t arg[], 2542 const uint32_t par[]) 2543 { 2544 if (gen_check_privilege(dc) && 2545 gen_window_check2(dc, arg[0], arg[1])) { 2546 gen_helper_wer(cpu_env, cpu_R[arg[0]], cpu_R[arg[1]]); 2547 } 2548 } 2549 2550 static void translate_wrmsk_expstate(DisasContext *dc, const uint32_t arg[], 2551 const uint32_t par[]) 2552 { 2553 if (gen_window_check2(dc, arg[0], arg[1])) { 2554 /* TODO: GPIO32 may be a part of coprocessor */ 2555 tcg_gen_and_i32(cpu_UR[EXPSTATE], cpu_R[arg[0]], cpu_R[arg[1]]); 2556 } 2557 } 2558 2559 static void translate_wsr(DisasContext *dc, const uint32_t arg[], 2560 const uint32_t par[]) 2561 { 2562 if (gen_check_sr(dc, par[0], SR_W) && 2563 (par[0] < 64 || gen_check_privilege(dc)) && 2564 gen_window_check1(dc, arg[0])) { 2565 gen_wsr(dc, par[0], cpu_R[arg[0]]); 2566 } 2567 } 2568 2569 static void translate_wur(DisasContext *dc, const uint32_t arg[], 2570 const uint32_t par[]) 2571 { 2572 if (gen_window_check1(dc, arg[0])) { 2573 if (uregnames[par[0]].name) { 2574 gen_wur(par[0], cpu_R[arg[0]]); 2575 } else { 2576 qemu_log_mask(LOG_UNIMP, "WUR %d not implemented, ", par[0]); 2577 } 2578 } 2579 } 2580 2581 static void translate_xor(DisasContext *dc, const uint32_t arg[], 2582 const uint32_t par[]) 2583 { 2584 if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { 2585 tcg_gen_xor_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); 2586 } 2587 } 2588 2589 static void translate_xsr(DisasContext *dc, const uint32_t arg[], 2590 const uint32_t par[]) 2591 { 2592 if (gen_check_sr(dc, par[0], SR_X) && 2593 (par[0] < 64 || gen_check_privilege(dc)) && 2594 gen_window_check1(dc, arg[0])) { 2595 TCGv_i32 tmp = tcg_temp_new_i32(); 2596 bool rsr_end, wsr_end; 2597 2598 tcg_gen_mov_i32(tmp, cpu_R[arg[0]]); 2599 rsr_end = gen_rsr(dc, cpu_R[arg[0]], par[0]); 2600 wsr_end = gen_wsr(dc, par[0], tmp); 2601 tcg_temp_free(tmp); 2602 if (rsr_end && !wsr_end) { 2603 gen_jumpi_check_loop_end(dc, 0); 2604 } 2605 } 2606 } 2607 2608 static const XtensaOpcodeOps core_ops[] = { 2609 { 2610 .name = "abs", 2611 .translate = translate_abs, 2612 }, { 2613 .name = "add", 2614 .translate = translate_add, 2615 }, { 2616 .name = "add.n", 2617 .translate = translate_add, 2618 }, { 2619 .name = "addi", 2620 .translate = translate_addi, 2621 }, { 2622 .name = "addi.n", 2623 .translate = translate_addi, 2624 }, { 2625 .name = "addmi", 2626 .translate = translate_addi, 2627 }, { 2628 .name = "addx2", 2629 .translate = translate_addx, 2630 .par = (const uint32_t[]){1}, 2631 }, { 2632 .name = "addx4", 2633 .translate = translate_addx, 2634 .par = (const uint32_t[]){2}, 2635 }, { 2636 .name = "addx8", 2637 .translate = translate_addx, 2638 .par = (const uint32_t[]){3}, 2639 }, { 2640 .name = "all4", 2641 .translate = translate_all, 2642 .par = (const uint32_t[]){true, 4}, 2643 }, { 2644 .name = "all8", 2645 .translate = translate_all, 2646 .par = (const uint32_t[]){true, 8}, 2647 }, { 2648 .name = "and", 2649 .translate = translate_and, 2650 }, { 2651 .name = "andb", 2652 .translate = translate_boolean, 2653 .par = (const uint32_t[]){BOOLEAN_AND}, 2654 }, { 2655 .name = "andbc", 2656 .translate = translate_boolean, 2657 .par = (const uint32_t[]){BOOLEAN_ANDC}, 2658 }, { 2659 .name = "any4", 2660 .translate = translate_all, 2661 .par = (const uint32_t[]){false, 4}, 2662 }, { 2663 .name = "any8", 2664 .translate = translate_all, 2665 .par = (const uint32_t[]){false, 8}, 2666 }, { 2667 .name = "ball", 2668 .translate = translate_ball, 2669 .par = (const uint32_t[]){TCG_COND_EQ}, 2670 }, { 2671 .name = "bany", 2672 .translate = translate_bany, 2673 .par = (const uint32_t[]){TCG_COND_NE}, 2674 }, { 2675 .name = "bbc", 2676 .translate = translate_bb, 2677 .par = (const uint32_t[]){TCG_COND_EQ}, 2678 }, { 2679 .name = "bbci", 2680 .translate = translate_bbi, 2681 .par = (const uint32_t[]){TCG_COND_EQ}, 2682 }, { 2683 .name = "bbs", 2684 .translate = translate_bb, 2685 .par = (const uint32_t[]){TCG_COND_NE}, 2686 }, { 2687 .name = "bbsi", 2688 .translate = translate_bbi, 2689 .par = (const uint32_t[]){TCG_COND_NE}, 2690 }, { 2691 .name = "beq", 2692 .translate = translate_b, 2693 .par = (const uint32_t[]){TCG_COND_EQ}, 2694 }, { 2695 .name = "beqi", 2696 .translate = translate_bi, 2697 .par = (const uint32_t[]){TCG_COND_EQ}, 2698 }, { 2699 .name = "beqz", 2700 .translate = translate_bz, 2701 .par = (const uint32_t[]){TCG_COND_EQ}, 2702 }, { 2703 .name = "beqz.n", 2704 .translate = translate_bz, 2705 .par = (const uint32_t[]){TCG_COND_EQ}, 2706 }, { 2707 .name = "bf", 2708 .translate = translate_bp, 2709 .par = (const uint32_t[]){TCG_COND_EQ}, 2710 }, { 2711 .name = "bge", 2712 .translate = translate_b, 2713 .par = (const uint32_t[]){TCG_COND_GE}, 2714 }, { 2715 .name = "bgei", 2716 .translate = translate_bi, 2717 .par = (const uint32_t[]){TCG_COND_GE}, 2718 }, { 2719 .name = "bgeu", 2720 .translate = translate_b, 2721 .par = (const uint32_t[]){TCG_COND_GEU}, 2722 }, { 2723 .name = "bgeui", 2724 .translate = translate_bi, 2725 .par = (const uint32_t[]){TCG_COND_GEU}, 2726 }, { 2727 .name = "bgez", 2728 .translate = translate_bz, 2729 .par = (const uint32_t[]){TCG_COND_GE}, 2730 }, { 2731 .name = "blt", 2732 .translate = translate_b, 2733 .par = (const uint32_t[]){TCG_COND_LT}, 2734 }, { 2735 .name = "blti", 2736 .translate = translate_bi, 2737 .par = (const uint32_t[]){TCG_COND_LT}, 2738 }, { 2739 .name = "bltu", 2740 .translate = translate_b, 2741 .par = (const uint32_t[]){TCG_COND_LTU}, 2742 }, { 2743 .name = "bltui", 2744 .translate = translate_bi, 2745 .par = (const uint32_t[]){TCG_COND_LTU}, 2746 }, { 2747 .name = "bltz", 2748 .translate = translate_bz, 2749 .par = (const uint32_t[]){TCG_COND_LT}, 2750 }, { 2751 .name = "bnall", 2752 .translate = translate_ball, 2753 .par = (const uint32_t[]){TCG_COND_NE}, 2754 }, { 2755 .name = "bne", 2756 .translate = translate_b, 2757 .par = (const uint32_t[]){TCG_COND_NE}, 2758 }, { 2759 .name = "bnei", 2760 .translate = translate_bi, 2761 .par = (const uint32_t[]){TCG_COND_NE}, 2762 }, { 2763 .name = "bnez", 2764 .translate = translate_bz, 2765 .par = (const uint32_t[]){TCG_COND_NE}, 2766 }, { 2767 .name = "bnez.n", 2768 .translate = translate_bz, 2769 .par = (const uint32_t[]){TCG_COND_NE}, 2770 }, { 2771 .name = "bnone", 2772 .translate = translate_bany, 2773 .par = (const uint32_t[]){TCG_COND_EQ}, 2774 }, { 2775 .name = "break", 2776 .translate = translate_break, 2777 .par = (const uint32_t[]){DEBUGCAUSE_BI}, 2778 }, { 2779 .name = "break.n", 2780 .translate = translate_break, 2781 .par = (const uint32_t[]){DEBUGCAUSE_BN}, 2782 }, { 2783 .name = "bt", 2784 .translate = translate_bp, 2785 .par = (const uint32_t[]){TCG_COND_NE}, 2786 }, { 2787 .name = "call0", 2788 .translate = translate_call0, 2789 }, { 2790 .name = "call12", 2791 .translate = translate_callw, 2792 .par = (const uint32_t[]){3}, 2793 }, { 2794 .name = "call4", 2795 .translate = translate_callw, 2796 .par = (const uint32_t[]){1}, 2797 }, { 2798 .name = "call8", 2799 .translate = translate_callw, 2800 .par = (const uint32_t[]){2}, 2801 }, { 2802 .name = "callx0", 2803 .translate = translate_callx0, 2804 }, { 2805 .name = "callx12", 2806 .translate = translate_callxw, 2807 .par = (const uint32_t[]){3}, 2808 }, { 2809 .name = "callx4", 2810 .translate = translate_callxw, 2811 .par = (const uint32_t[]){1}, 2812 }, { 2813 .name = "callx8", 2814 .translate = translate_callxw, 2815 .par = (const uint32_t[]){2}, 2816 }, { 2817 .name = "clamps", 2818 .translate = translate_clamps, 2819 }, { 2820 .name = "clrb_expstate", 2821 .translate = translate_clrb_expstate, 2822 }, { 2823 .name = "const16", 2824 .translate = translate_const16, 2825 }, { 2826 .name = "depbits", 2827 .translate = translate_depbits, 2828 }, { 2829 .name = "dhi", 2830 .translate = translate_dcache, 2831 .par = (const uint32_t[]){true, true}, 2832 }, { 2833 .name = "dhu", 2834 .translate = translate_dcache, 2835 .par = (const uint32_t[]){true, true}, 2836 }, { 2837 .name = "dhwb", 2838 .translate = translate_dcache, 2839 .par = (const uint32_t[]){false, true}, 2840 }, { 2841 .name = "dhwbi", 2842 .translate = translate_dcache, 2843 .par = (const uint32_t[]){false, true}, 2844 }, { 2845 .name = "dii", 2846 .translate = translate_dcache, 2847 .par = (const uint32_t[]){true, false}, 2848 }, { 2849 .name = "diu", 2850 .translate = translate_dcache, 2851 .par = (const uint32_t[]){true, false}, 2852 }, { 2853 .name = "diwb", 2854 .translate = translate_dcache, 2855 .par = (const uint32_t[]){true, false}, 2856 }, { 2857 .name = "diwbi", 2858 .translate = translate_dcache, 2859 .par = (const uint32_t[]){true, false}, 2860 }, { 2861 .name = "dpfl", 2862 .translate = translate_dcache, 2863 .par = (const uint32_t[]){true, true}, 2864 }, { 2865 .name = "dpfr", 2866 .translate = translate_dcache, 2867 .par = (const uint32_t[]){false, false}, 2868 }, { 2869 .name = "dpfro", 2870 .translate = translate_dcache, 2871 .par = (const uint32_t[]){false, false}, 2872 }, { 2873 .name = "dpfw", 2874 .translate = translate_dcache, 2875 .par = (const uint32_t[]){false, false}, 2876 }, { 2877 .name = "dpfwo", 2878 .translate = translate_dcache, 2879 .par = (const uint32_t[]){false, false}, 2880 }, { 2881 .name = "dsync", 2882 .translate = translate_nop, 2883 }, { 2884 .name = "entry", 2885 .translate = translate_entry, 2886 }, { 2887 .name = "esync", 2888 .translate = translate_nop, 2889 }, { 2890 .name = "excw", 2891 .translate = translate_nop, 2892 }, { 2893 .name = "extui", 2894 .translate = translate_extui, 2895 }, { 2896 .name = "extw", 2897 .translate = translate_memw, 2898 }, { 2899 .name = "hwwdtlba", 2900 .translate = translate_ill, 2901 }, { 2902 .name = "hwwitlba", 2903 .translate = translate_ill, 2904 }, { 2905 .name = "idtlb", 2906 .translate = translate_itlb, 2907 .par = (const uint32_t[]){true}, 2908 }, { 2909 .name = "ihi", 2910 .translate = translate_icache, 2911 .par = (const uint32_t[]){false, true}, 2912 }, { 2913 .name = "ihu", 2914 .translate = translate_icache, 2915 .par = (const uint32_t[]){true, true}, 2916 }, { 2917 .name = "iii", 2918 .translate = translate_icache, 2919 .par = (const uint32_t[]){true, false}, 2920 }, { 2921 .name = "iitlb", 2922 .translate = translate_itlb, 2923 .par = (const uint32_t[]){false}, 2924 }, { 2925 .name = "iiu", 2926 .translate = translate_icache, 2927 .par = (const uint32_t[]){true, false}, 2928 }, { 2929 .name = "ill", 2930 .translate = translate_ill, 2931 }, { 2932 .name = "ill.n", 2933 .translate = translate_ill, 2934 }, { 2935 .name = "ipf", 2936 .translate = translate_icache, 2937 .par = (const uint32_t[]){false, false}, 2938 }, { 2939 .name = "ipfl", 2940 .translate = translate_icache, 2941 .par = (const uint32_t[]){true, true}, 2942 }, { 2943 .name = "isync", 2944 .translate = translate_nop, 2945 }, { 2946 .name = "j", 2947 .translate = translate_j, 2948 }, { 2949 .name = "jx", 2950 .translate = translate_jx, 2951 }, { 2952 .name = "l16si", 2953 .translate = translate_ldst, 2954 .par = (const uint32_t[]){MO_TESW, false, false}, 2955 }, { 2956 .name = "l16ui", 2957 .translate = translate_ldst, 2958 .par = (const uint32_t[]){MO_TEUW, false, false}, 2959 }, { 2960 .name = "l32ai", 2961 .translate = translate_ldst, 2962 .par = (const uint32_t[]){MO_TEUL, true, false}, 2963 }, { 2964 .name = "l32e", 2965 .translate = translate_l32e, 2966 }, { 2967 .name = "l32i", 2968 .translate = translate_ldst, 2969 .par = (const uint32_t[]){MO_TEUL, false, false}, 2970 }, { 2971 .name = "l32i.n", 2972 .translate = translate_ldst, 2973 .par = (const uint32_t[]){MO_TEUL, false, false}, 2974 }, { 2975 .name = "l32r", 2976 .translate = translate_l32r, 2977 }, { 2978 .name = "l8ui", 2979 .translate = translate_ldst, 2980 .par = (const uint32_t[]){MO_UB, false, false}, 2981 }, { 2982 .name = "lddec", 2983 .translate = translate_mac16, 2984 .par = (const uint32_t[]){MAC16_NONE, 0, 0, -4}, 2985 }, { 2986 .name = "ldinc", 2987 .translate = translate_mac16, 2988 .par = (const uint32_t[]){MAC16_NONE, 0, 0, 4}, 2989 }, { 2990 .name = "ldpte", 2991 .translate = translate_ill, 2992 }, { 2993 .name = "loop", 2994 .translate = translate_loop, 2995 .par = (const uint32_t[]){TCG_COND_NEVER}, 2996 }, { 2997 .name = "loopgtz", 2998 .translate = translate_loop, 2999 .par = (const uint32_t[]){TCG_COND_GT}, 3000 }, { 3001 .name = "loopnez", 3002 .translate = translate_loop, 3003 .par = (const uint32_t[]){TCG_COND_NE}, 3004 }, { 3005 .name = "max", 3006 .translate = translate_smax, 3007 }, { 3008 .name = "maxu", 3009 .translate = translate_umax, 3010 }, { 3011 .name = "memw", 3012 .translate = translate_memw, 3013 }, { 3014 .name = "min", 3015 .translate = translate_smin, 3016 }, { 3017 .name = "minu", 3018 .translate = translate_umin, 3019 }, { 3020 .name = "mov", 3021 .translate = translate_mov, 3022 }, { 3023 .name = "mov.n", 3024 .translate = translate_mov, 3025 }, { 3026 .name = "moveqz", 3027 .translate = translate_movcond, 3028 .par = (const uint32_t[]){TCG_COND_EQ}, 3029 }, { 3030 .name = "movf", 3031 .translate = translate_movp, 3032 .par = (const uint32_t[]){TCG_COND_EQ}, 3033 }, { 3034 .name = "movgez", 3035 .translate = translate_movcond, 3036 .par = (const uint32_t[]){TCG_COND_GE}, 3037 }, { 3038 .name = "movi", 3039 .translate = translate_movi, 3040 }, { 3041 .name = "movi.n", 3042 .translate = translate_movi, 3043 }, { 3044 .name = "movltz", 3045 .translate = translate_movcond, 3046 .par = (const uint32_t[]){TCG_COND_LT}, 3047 }, { 3048 .name = "movnez", 3049 .translate = translate_movcond, 3050 .par = (const uint32_t[]){TCG_COND_NE}, 3051 }, { 3052 .name = "movsp", 3053 .translate = translate_movsp, 3054 }, { 3055 .name = "movt", 3056 .translate = translate_movp, 3057 .par = (const uint32_t[]){TCG_COND_NE}, 3058 }, { 3059 .name = "mul.aa.hh", 3060 .translate = translate_mac16, 3061 .par = (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_HH, 0}, 3062 }, { 3063 .name = "mul.aa.hl", 3064 .translate = translate_mac16, 3065 .par = (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_HL, 0}, 3066 }, { 3067 .name = "mul.aa.lh", 3068 .translate = translate_mac16, 3069 .par = (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_LH, 0}, 3070 }, { 3071 .name = "mul.aa.ll", 3072 .translate = translate_mac16, 3073 .par = (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_LL, 0}, 3074 }, { 3075 .name = "mul.ad.hh", 3076 .translate = translate_mac16, 3077 .par = (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_HH, 0}, 3078 }, { 3079 .name = "mul.ad.hl", 3080 .translate = translate_mac16, 3081 .par = (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_HL, 0}, 3082 }, { 3083 .name = "mul.ad.lh", 3084 .translate = translate_mac16, 3085 .par = (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_LH, 0}, 3086 }, { 3087 .name = "mul.ad.ll", 3088 .translate = translate_mac16, 3089 .par = (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_LL, 0}, 3090 }, { 3091 .name = "mul.da.hh", 3092 .translate = translate_mac16, 3093 .par = (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_HH, 0}, 3094 }, { 3095 .name = "mul.da.hl", 3096 .translate = translate_mac16, 3097 .par = (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_HL, 0}, 3098 }, { 3099 .name = "mul.da.lh", 3100 .translate = translate_mac16, 3101 .par = (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_LH, 0}, 3102 }, { 3103 .name = "mul.da.ll", 3104 .translate = translate_mac16, 3105 .par = (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_LL, 0}, 3106 }, { 3107 .name = "mul.dd.hh", 3108 .translate = translate_mac16, 3109 .par = (const uint32_t[]){MAC16_MUL, MAC16_DD, MAC16_HH, 0}, 3110 }, { 3111 .name = "mul.dd.hl", 3112 .translate = translate_mac16, 3113 .par = (const uint32_t[]){MAC16_MUL, MAC16_DD, MAC16_HL, 0}, 3114 }, { 3115 .name = "mul.dd.lh", 3116 .translate = translate_mac16, 3117 .par = (const uint32_t[]){MAC16_MUL, MAC16_DD, MAC16_LH, 0}, 3118 }, { 3119 .name = "mul.dd.ll", 3120 .translate = translate_mac16, 3121 .par = (const uint32_t[]){MAC16_MUL, MAC16_DD, MAC16_LL, 0}, 3122 }, { 3123 .name = "mul16s", 3124 .translate = translate_mul16, 3125 .par = (const uint32_t[]){true}, 3126 }, { 3127 .name = "mul16u", 3128 .translate = translate_mul16, 3129 .par = (const uint32_t[]){false}, 3130 }, { 3131 .name = "mula.aa.hh", 3132 .translate = translate_mac16, 3133 .par = (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_HH, 0}, 3134 }, { 3135 .name = "mula.aa.hl", 3136 .translate = translate_mac16, 3137 .par = (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_HL, 0}, 3138 }, { 3139 .name = "mula.aa.lh", 3140 .translate = translate_mac16, 3141 .par = (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_LH, 0}, 3142 }, { 3143 .name = "mula.aa.ll", 3144 .translate = translate_mac16, 3145 .par = (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_LL, 0}, 3146 }, { 3147 .name = "mula.ad.hh", 3148 .translate = translate_mac16, 3149 .par = (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_HH, 0}, 3150 }, { 3151 .name = "mula.ad.hl", 3152 .translate = translate_mac16, 3153 .par = (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_HL, 0}, 3154 }, { 3155 .name = "mula.ad.lh", 3156 .translate = translate_mac16, 3157 .par = (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_LH, 0}, 3158 }, { 3159 .name = "mula.ad.ll", 3160 .translate = translate_mac16, 3161 .par = (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_LL, 0}, 3162 }, { 3163 .name = "mula.da.hh", 3164 .translate = translate_mac16, 3165 .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HH, 0}, 3166 }, { 3167 .name = "mula.da.hh.lddec", 3168 .translate = translate_mac16, 3169 .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HH, -4}, 3170 }, { 3171 .name = "mula.da.hh.ldinc", 3172 .translate = translate_mac16, 3173 .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HH, 4}, 3174 }, { 3175 .name = "mula.da.hl", 3176 .translate = translate_mac16, 3177 .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HL, 0}, 3178 }, { 3179 .name = "mula.da.hl.lddec", 3180 .translate = translate_mac16, 3181 .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HL, -4}, 3182 }, { 3183 .name = "mula.da.hl.ldinc", 3184 .translate = translate_mac16, 3185 .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HL, 4}, 3186 }, { 3187 .name = "mula.da.lh", 3188 .translate = translate_mac16, 3189 .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LH, 0}, 3190 }, { 3191 .name = "mula.da.lh.lddec", 3192 .translate = translate_mac16, 3193 .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LH, -4}, 3194 }, { 3195 .name = "mula.da.lh.ldinc", 3196 .translate = translate_mac16, 3197 .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LH, 4}, 3198 }, { 3199 .name = "mula.da.ll", 3200 .translate = translate_mac16, 3201 .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LL, 0}, 3202 }, { 3203 .name = "mula.da.ll.lddec", 3204 .translate = translate_mac16, 3205 .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LL, -4}, 3206 }, { 3207 .name = "mula.da.ll.ldinc", 3208 .translate = translate_mac16, 3209 .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LL, 4}, 3210 }, { 3211 .name = "mula.dd.hh", 3212 .translate = translate_mac16, 3213 .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HH, 0}, 3214 }, { 3215 .name = "mula.dd.hh.lddec", 3216 .translate = translate_mac16, 3217 .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HH, -4}, 3218 }, { 3219 .name = "mula.dd.hh.ldinc", 3220 .translate = translate_mac16, 3221 .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HH, 4}, 3222 }, { 3223 .name = "mula.dd.hl", 3224 .translate = translate_mac16, 3225 .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HL, 0}, 3226 }, { 3227 .name = "mula.dd.hl.lddec", 3228 .translate = translate_mac16, 3229 .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HL, -4}, 3230 }, { 3231 .name = "mula.dd.hl.ldinc", 3232 .translate = translate_mac16, 3233 .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HL, 4}, 3234 }, { 3235 .name = "mula.dd.lh", 3236 .translate = translate_mac16, 3237 .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LH, 0}, 3238 }, { 3239 .name = "mula.dd.lh.lddec", 3240 .translate = translate_mac16, 3241 .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LH, -4}, 3242 }, { 3243 .name = "mula.dd.lh.ldinc", 3244 .translate = translate_mac16, 3245 .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LH, 4}, 3246 }, { 3247 .name = "mula.dd.ll", 3248 .translate = translate_mac16, 3249 .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LL, 0}, 3250 }, { 3251 .name = "mula.dd.ll.lddec", 3252 .translate = translate_mac16, 3253 .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LL, -4}, 3254 }, { 3255 .name = "mula.dd.ll.ldinc", 3256 .translate = translate_mac16, 3257 .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LL, 4}, 3258 }, { 3259 .name = "mull", 3260 .translate = translate_mull, 3261 }, { 3262 .name = "muls.aa.hh", 3263 .translate = translate_mac16, 3264 .par = (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_HH, 0}, 3265 }, { 3266 .name = "muls.aa.hl", 3267 .translate = translate_mac16, 3268 .par = (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_HL, 0}, 3269 }, { 3270 .name = "muls.aa.lh", 3271 .translate = translate_mac16, 3272 .par = (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_LH, 0}, 3273 }, { 3274 .name = "muls.aa.ll", 3275 .translate = translate_mac16, 3276 .par = (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_LL, 0}, 3277 }, { 3278 .name = "muls.ad.hh", 3279 .translate = translate_mac16, 3280 .par = (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_HH, 0}, 3281 }, { 3282 .name = "muls.ad.hl", 3283 .translate = translate_mac16, 3284 .par = (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_HL, 0}, 3285 }, { 3286 .name = "muls.ad.lh", 3287 .translate = translate_mac16, 3288 .par = (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_LH, 0}, 3289 }, { 3290 .name = "muls.ad.ll", 3291 .translate = translate_mac16, 3292 .par = (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_LL, 0}, 3293 }, { 3294 .name = "muls.da.hh", 3295 .translate = translate_mac16, 3296 .par = (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_HH, 0}, 3297 }, { 3298 .name = "muls.da.hl", 3299 .translate = translate_mac16, 3300 .par = (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_HL, 0}, 3301 }, { 3302 .name = "muls.da.lh", 3303 .translate = translate_mac16, 3304 .par = (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_LH, 0}, 3305 }, { 3306 .name = "muls.da.ll", 3307 .translate = translate_mac16, 3308 .par = (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_LL, 0}, 3309 }, { 3310 .name = "muls.dd.hh", 3311 .translate = translate_mac16, 3312 .par = (const uint32_t[]){MAC16_MULS, MAC16_DD, MAC16_HH, 0}, 3313 }, { 3314 .name = "muls.dd.hl", 3315 .translate = translate_mac16, 3316 .par = (const uint32_t[]){MAC16_MULS, MAC16_DD, MAC16_HL, 0}, 3317 }, { 3318 .name = "muls.dd.lh", 3319 .translate = translate_mac16, 3320 .par = (const uint32_t[]){MAC16_MULS, MAC16_DD, MAC16_LH, 0}, 3321 }, { 3322 .name = "muls.dd.ll", 3323 .translate = translate_mac16, 3324 .par = (const uint32_t[]){MAC16_MULS, MAC16_DD, MAC16_LL, 0}, 3325 }, { 3326 .name = "mulsh", 3327 .translate = translate_mulh, 3328 .par = (const uint32_t[]){true}, 3329 }, { 3330 .name = "muluh", 3331 .translate = translate_mulh, 3332 .par = (const uint32_t[]){false}, 3333 }, { 3334 .name = "neg", 3335 .translate = translate_neg, 3336 }, { 3337 .name = "nop", 3338 .translate = translate_nop, 3339 }, { 3340 .name = "nop.n", 3341 .translate = translate_nop, 3342 }, { 3343 .name = "nsa", 3344 .translate = translate_nsa, 3345 }, { 3346 .name = "nsau", 3347 .translate = translate_nsau, 3348 }, { 3349 .name = "or", 3350 .translate = translate_or, 3351 }, { 3352 .name = "orb", 3353 .translate = translate_boolean, 3354 .par = (const uint32_t[]){BOOLEAN_OR}, 3355 }, { 3356 .name = "orbc", 3357 .translate = translate_boolean, 3358 .par = (const uint32_t[]){BOOLEAN_ORC}, 3359 }, { 3360 .name = "pdtlb", 3361 .translate = translate_ptlb, 3362 .par = (const uint32_t[]){true}, 3363 }, { 3364 .name = "pitlb", 3365 .translate = translate_ptlb, 3366 .par = (const uint32_t[]){false}, 3367 }, { 3368 .name = "quos", 3369 .translate = translate_quos, 3370 .par = (const uint32_t[]){true}, 3371 }, { 3372 .name = "quou", 3373 .translate = translate_quou, 3374 .par = (const uint32_t[]){true}, 3375 }, { 3376 .name = "rdtlb0", 3377 .translate = translate_rtlb, 3378 .par = (const uint32_t[]){true, 0}, 3379 }, { 3380 .name = "rdtlb1", 3381 .translate = translate_rtlb, 3382 .par = (const uint32_t[]){true, 1}, 3383 }, { 3384 .name = "read_impwire", 3385 .translate = translate_read_impwire, 3386 }, { 3387 .name = "rems", 3388 .translate = translate_quos, 3389 .par = (const uint32_t[]){false}, 3390 }, { 3391 .name = "remu", 3392 .translate = translate_quou, 3393 .par = (const uint32_t[]){false}, 3394 }, { 3395 .name = "rer", 3396 .translate = translate_rer, 3397 }, { 3398 .name = "ret", 3399 .translate = translate_ret, 3400 }, { 3401 .name = "ret.n", 3402 .translate = translate_ret, 3403 }, { 3404 .name = "retw", 3405 .translate = translate_retw, 3406 }, { 3407 .name = "retw.n", 3408 .translate = translate_retw, 3409 }, { 3410 .name = "rfdd", 3411 .translate = translate_ill, 3412 }, { 3413 .name = "rfde", 3414 .translate = translate_rfde, 3415 }, { 3416 .name = "rfdo", 3417 .translate = translate_ill, 3418 }, { 3419 .name = "rfe", 3420 .translate = translate_rfe, 3421 }, { 3422 .name = "rfi", 3423 .translate = translate_rfi, 3424 }, { 3425 .name = "rfwo", 3426 .translate = translate_rfw, 3427 .par = (const uint32_t[]){true}, 3428 }, { 3429 .name = "rfwu", 3430 .translate = translate_rfw, 3431 .par = (const uint32_t[]){false}, 3432 }, { 3433 .name = "ritlb0", 3434 .translate = translate_rtlb, 3435 .par = (const uint32_t[]){false, 0}, 3436 }, { 3437 .name = "ritlb1", 3438 .translate = translate_rtlb, 3439 .par = (const uint32_t[]){false, 1}, 3440 }, { 3441 .name = "rotw", 3442 .translate = translate_rotw, 3443 }, { 3444 .name = "rsil", 3445 .translate = translate_rsil, 3446 }, { 3447 .name = "rsr.176", 3448 .translate = translate_rsr, 3449 .par = (const uint32_t[]){176}, 3450 }, { 3451 .name = "rsr.208", 3452 .translate = translate_rsr, 3453 .par = (const uint32_t[]){208}, 3454 }, { 3455 .name = "rsr.acchi", 3456 .translate = translate_rsr, 3457 .par = (const uint32_t[]){ACCHI}, 3458 }, { 3459 .name = "rsr.acclo", 3460 .translate = translate_rsr, 3461 .par = (const uint32_t[]){ACCLO}, 3462 }, { 3463 .name = "rsr.atomctl", 3464 .translate = translate_rsr, 3465 .par = (const uint32_t[]){ATOMCTL}, 3466 }, { 3467 .name = "rsr.br", 3468 .translate = translate_rsr, 3469 .par = (const uint32_t[]){BR}, 3470 }, { 3471 .name = "rsr.cacheattr", 3472 .translate = translate_rsr, 3473 .par = (const uint32_t[]){CACHEATTR}, 3474 }, { 3475 .name = "rsr.ccompare0", 3476 .translate = translate_rsr, 3477 .par = (const uint32_t[]){CCOMPARE}, 3478 }, { 3479 .name = "rsr.ccompare1", 3480 .translate = translate_rsr, 3481 .par = (const uint32_t[]){CCOMPARE + 1}, 3482 }, { 3483 .name = "rsr.ccompare2", 3484 .translate = translate_rsr, 3485 .par = (const uint32_t[]){CCOMPARE + 2}, 3486 }, { 3487 .name = "rsr.ccount", 3488 .translate = translate_rsr, 3489 .par = (const uint32_t[]){CCOUNT}, 3490 }, { 3491 .name = "rsr.configid0", 3492 .translate = translate_rsr, 3493 .par = (const uint32_t[]){CONFIGID0}, 3494 }, { 3495 .name = "rsr.configid1", 3496 .translate = translate_rsr, 3497 .par = (const uint32_t[]){CONFIGID1}, 3498 }, { 3499 .name = "rsr.cpenable", 3500 .translate = translate_rsr, 3501 .par = (const uint32_t[]){CPENABLE}, 3502 }, { 3503 .name = "rsr.dbreaka0", 3504 .translate = translate_rsr, 3505 .par = (const uint32_t[]){DBREAKA}, 3506 }, { 3507 .name = "rsr.dbreaka1", 3508 .translate = translate_rsr, 3509 .par = (const uint32_t[]){DBREAKA + 1}, 3510 }, { 3511 .name = "rsr.dbreakc0", 3512 .translate = translate_rsr, 3513 .par = (const uint32_t[]){DBREAKC}, 3514 }, { 3515 .name = "rsr.dbreakc1", 3516 .translate = translate_rsr, 3517 .par = (const uint32_t[]){DBREAKC + 1}, 3518 }, { 3519 .name = "rsr.ddr", 3520 .translate = translate_rsr, 3521 .par = (const uint32_t[]){DDR}, 3522 }, { 3523 .name = "rsr.debugcause", 3524 .translate = translate_rsr, 3525 .par = (const uint32_t[]){DEBUGCAUSE}, 3526 }, { 3527 .name = "rsr.depc", 3528 .translate = translate_rsr, 3529 .par = (const uint32_t[]){DEPC}, 3530 }, { 3531 .name = "rsr.dtlbcfg", 3532 .translate = translate_rsr, 3533 .par = (const uint32_t[]){DTLBCFG}, 3534 }, { 3535 .name = "rsr.epc1", 3536 .translate = translate_rsr, 3537 .par = (const uint32_t[]){EPC1}, 3538 }, { 3539 .name = "rsr.epc2", 3540 .translate = translate_rsr, 3541 .par = (const uint32_t[]){EPC1 + 1}, 3542 }, { 3543 .name = "rsr.epc3", 3544 .translate = translate_rsr, 3545 .par = (const uint32_t[]){EPC1 + 2}, 3546 }, { 3547 .name = "rsr.epc4", 3548 .translate = translate_rsr, 3549 .par = (const uint32_t[]){EPC1 + 3}, 3550 }, { 3551 .name = "rsr.epc5", 3552 .translate = translate_rsr, 3553 .par = (const uint32_t[]){EPC1 + 4}, 3554 }, { 3555 .name = "rsr.epc6", 3556 .translate = translate_rsr, 3557 .par = (const uint32_t[]){EPC1 + 5}, 3558 }, { 3559 .name = "rsr.epc7", 3560 .translate = translate_rsr, 3561 .par = (const uint32_t[]){EPC1 + 6}, 3562 }, { 3563 .name = "rsr.eps2", 3564 .translate = translate_rsr, 3565 .par = (const uint32_t[]){EPS2}, 3566 }, { 3567 .name = "rsr.eps3", 3568 .translate = translate_rsr, 3569 .par = (const uint32_t[]){EPS2 + 1}, 3570 }, { 3571 .name = "rsr.eps4", 3572 .translate = translate_rsr, 3573 .par = (const uint32_t[]){EPS2 + 2}, 3574 }, { 3575 .name = "rsr.eps5", 3576 .translate = translate_rsr, 3577 .par = (const uint32_t[]){EPS2 + 3}, 3578 }, { 3579 .name = "rsr.eps6", 3580 .translate = translate_rsr, 3581 .par = (const uint32_t[]){EPS2 + 4}, 3582 }, { 3583 .name = "rsr.eps7", 3584 .translate = translate_rsr, 3585 .par = (const uint32_t[]){EPS2 + 5}, 3586 }, { 3587 .name = "rsr.exccause", 3588 .translate = translate_rsr, 3589 .par = (const uint32_t[]){EXCCAUSE}, 3590 }, { 3591 .name = "rsr.excsave1", 3592 .translate = translate_rsr, 3593 .par = (const uint32_t[]){EXCSAVE1}, 3594 }, { 3595 .name = "rsr.excsave2", 3596 .translate = translate_rsr, 3597 .par = (const uint32_t[]){EXCSAVE1 + 1}, 3598 }, { 3599 .name = "rsr.excsave3", 3600 .translate = translate_rsr, 3601 .par = (const uint32_t[]){EXCSAVE1 + 2}, 3602 }, { 3603 .name = "rsr.excsave4", 3604 .translate = translate_rsr, 3605 .par = (const uint32_t[]){EXCSAVE1 + 3}, 3606 }, { 3607 .name = "rsr.excsave5", 3608 .translate = translate_rsr, 3609 .par = (const uint32_t[]){EXCSAVE1 + 4}, 3610 }, { 3611 .name = "rsr.excsave6", 3612 .translate = translate_rsr, 3613 .par = (const uint32_t[]){EXCSAVE1 + 5}, 3614 }, { 3615 .name = "rsr.excsave7", 3616 .translate = translate_rsr, 3617 .par = (const uint32_t[]){EXCSAVE1 + 6}, 3618 }, { 3619 .name = "rsr.excvaddr", 3620 .translate = translate_rsr, 3621 .par = (const uint32_t[]){EXCVADDR}, 3622 }, { 3623 .name = "rsr.ibreaka0", 3624 .translate = translate_rsr, 3625 .par = (const uint32_t[]){IBREAKA}, 3626 }, { 3627 .name = "rsr.ibreaka1", 3628 .translate = translate_rsr, 3629 .par = (const uint32_t[]){IBREAKA + 1}, 3630 }, { 3631 .name = "rsr.ibreakenable", 3632 .translate = translate_rsr, 3633 .par = (const uint32_t[]){IBREAKENABLE}, 3634 }, { 3635 .name = "rsr.icount", 3636 .translate = translate_rsr, 3637 .par = (const uint32_t[]){ICOUNT}, 3638 }, { 3639 .name = "rsr.icountlevel", 3640 .translate = translate_rsr, 3641 .par = (const uint32_t[]){ICOUNTLEVEL}, 3642 }, { 3643 .name = "rsr.intclear", 3644 .translate = translate_rsr, 3645 .par = (const uint32_t[]){INTCLEAR}, 3646 }, { 3647 .name = "rsr.intenable", 3648 .translate = translate_rsr, 3649 .par = (const uint32_t[]){INTENABLE}, 3650 }, { 3651 .name = "rsr.interrupt", 3652 .translate = translate_rsr, 3653 .par = (const uint32_t[]){INTSET}, 3654 }, { 3655 .name = "rsr.intset", 3656 .translate = translate_rsr, 3657 .par = (const uint32_t[]){INTSET}, 3658 }, { 3659 .name = "rsr.itlbcfg", 3660 .translate = translate_rsr, 3661 .par = (const uint32_t[]){ITLBCFG}, 3662 }, { 3663 .name = "rsr.lbeg", 3664 .translate = translate_rsr, 3665 .par = (const uint32_t[]){LBEG}, 3666 }, { 3667 .name = "rsr.lcount", 3668 .translate = translate_rsr, 3669 .par = (const uint32_t[]){LCOUNT}, 3670 }, { 3671 .name = "rsr.lend", 3672 .translate = translate_rsr, 3673 .par = (const uint32_t[]){LEND}, 3674 }, { 3675 .name = "rsr.litbase", 3676 .translate = translate_rsr, 3677 .par = (const uint32_t[]){LITBASE}, 3678 }, { 3679 .name = "rsr.m0", 3680 .translate = translate_rsr, 3681 .par = (const uint32_t[]){MR}, 3682 }, { 3683 .name = "rsr.m1", 3684 .translate = translate_rsr, 3685 .par = (const uint32_t[]){MR + 1}, 3686 }, { 3687 .name = "rsr.m2", 3688 .translate = translate_rsr, 3689 .par = (const uint32_t[]){MR + 2}, 3690 }, { 3691 .name = "rsr.m3", 3692 .translate = translate_rsr, 3693 .par = (const uint32_t[]){MR + 3}, 3694 }, { 3695 .name = "rsr.memctl", 3696 .translate = translate_rsr, 3697 .par = (const uint32_t[]){MEMCTL}, 3698 }, { 3699 .name = "rsr.misc0", 3700 .translate = translate_rsr, 3701 .par = (const uint32_t[]){MISC}, 3702 }, { 3703 .name = "rsr.misc1", 3704 .translate = translate_rsr, 3705 .par = (const uint32_t[]){MISC + 1}, 3706 }, { 3707 .name = "rsr.misc2", 3708 .translate = translate_rsr, 3709 .par = (const uint32_t[]){MISC + 2}, 3710 }, { 3711 .name = "rsr.misc3", 3712 .translate = translate_rsr, 3713 .par = (const uint32_t[]){MISC + 3}, 3714 }, { 3715 .name = "rsr.prid", 3716 .translate = translate_rsr, 3717 .par = (const uint32_t[]){PRID}, 3718 }, { 3719 .name = "rsr.ps", 3720 .translate = translate_rsr, 3721 .par = (const uint32_t[]){PS}, 3722 }, { 3723 .name = "rsr.ptevaddr", 3724 .translate = translate_rsr, 3725 .par = (const uint32_t[]){PTEVADDR}, 3726 }, { 3727 .name = "rsr.rasid", 3728 .translate = translate_rsr, 3729 .par = (const uint32_t[]){RASID}, 3730 }, { 3731 .name = "rsr.sar", 3732 .translate = translate_rsr, 3733 .par = (const uint32_t[]){SAR}, 3734 }, { 3735 .name = "rsr.scompare1", 3736 .translate = translate_rsr, 3737 .par = (const uint32_t[]){SCOMPARE1}, 3738 }, { 3739 .name = "rsr.vecbase", 3740 .translate = translate_rsr, 3741 .par = (const uint32_t[]){VECBASE}, 3742 }, { 3743 .name = "rsr.windowbase", 3744 .translate = translate_rsr, 3745 .par = (const uint32_t[]){WINDOW_BASE}, 3746 }, { 3747 .name = "rsr.windowstart", 3748 .translate = translate_rsr, 3749 .par = (const uint32_t[]){WINDOW_START}, 3750 }, { 3751 .name = "rsync", 3752 .translate = translate_nop, 3753 }, { 3754 .name = "rur.expstate", 3755 .translate = translate_rur, 3756 .par = (const uint32_t[]){EXPSTATE}, 3757 }, { 3758 .name = "rur.fcr", 3759 .translate = translate_rur, 3760 .par = (const uint32_t[]){FCR}, 3761 }, { 3762 .name = "rur.fsr", 3763 .translate = translate_rur, 3764 .par = (const uint32_t[]){FSR}, 3765 }, { 3766 .name = "rur.threadptr", 3767 .translate = translate_rur, 3768 .par = (const uint32_t[]){THREADPTR}, 3769 }, { 3770 .name = "s16i", 3771 .translate = translate_ldst, 3772 .par = (const uint32_t[]){MO_TEUW, false, true}, 3773 }, { 3774 .name = "s32c1i", 3775 .translate = translate_s32c1i, 3776 }, { 3777 .name = "s32e", 3778 .translate = translate_s32e, 3779 }, { 3780 .name = "s32i", 3781 .translate = translate_ldst, 3782 .par = (const uint32_t[]){MO_TEUL, false, true}, 3783 }, { 3784 .name = "s32i.n", 3785 .translate = translate_ldst, 3786 .par = (const uint32_t[]){MO_TEUL, false, true}, 3787 }, { 3788 .name = "s32nb", 3789 .translate = translate_ldst, 3790 .par = (const uint32_t[]){MO_TEUL, false, true}, 3791 }, { 3792 .name = "s32ri", 3793 .translate = translate_ldst, 3794 .par = (const uint32_t[]){MO_TEUL, true, true}, 3795 }, { 3796 .name = "s8i", 3797 .translate = translate_ldst, 3798 .par = (const uint32_t[]){MO_UB, false, true}, 3799 }, { 3800 .name = "salt", 3801 .translate = translate_salt, 3802 .par = (const uint32_t[]){TCG_COND_LT}, 3803 }, { 3804 .name = "saltu", 3805 .translate = translate_salt, 3806 .par = (const uint32_t[]){TCG_COND_LTU}, 3807 }, { 3808 .name = "setb_expstate", 3809 .translate = translate_setb_expstate, 3810 }, { 3811 .name = "sext", 3812 .translate = translate_sext, 3813 }, { 3814 .name = "simcall", 3815 .translate = translate_simcall, 3816 }, { 3817 .name = "sll", 3818 .translate = translate_sll, 3819 }, { 3820 .name = "slli", 3821 .translate = translate_slli, 3822 }, { 3823 .name = "sra", 3824 .translate = translate_sra, 3825 }, { 3826 .name = "srai", 3827 .translate = translate_srai, 3828 }, { 3829 .name = "src", 3830 .translate = translate_src, 3831 }, { 3832 .name = "srl", 3833 .translate = translate_srl, 3834 }, { 3835 .name = "srli", 3836 .translate = translate_srli, 3837 }, { 3838 .name = "ssa8b", 3839 .translate = translate_ssa8b, 3840 }, { 3841 .name = "ssa8l", 3842 .translate = translate_ssa8l, 3843 }, { 3844 .name = "ssai", 3845 .translate = translate_ssai, 3846 }, { 3847 .name = "ssl", 3848 .translate = translate_ssl, 3849 }, { 3850 .name = "ssr", 3851 .translate = translate_ssr, 3852 }, { 3853 .name = "sub", 3854 .translate = translate_sub, 3855 }, { 3856 .name = "subx2", 3857 .translate = translate_subx, 3858 .par = (const uint32_t[]){1}, 3859 }, { 3860 .name = "subx4", 3861 .translate = translate_subx, 3862 .par = (const uint32_t[]){2}, 3863 }, { 3864 .name = "subx8", 3865 .translate = translate_subx, 3866 .par = (const uint32_t[]){3}, 3867 }, { 3868 .name = "syscall", 3869 .translate = translate_syscall, 3870 }, { 3871 .name = "umul.aa.hh", 3872 .translate = translate_mac16, 3873 .par = (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_HH, 0}, 3874 }, { 3875 .name = "umul.aa.hl", 3876 .translate = translate_mac16, 3877 .par = (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_HL, 0}, 3878 }, { 3879 .name = "umul.aa.lh", 3880 .translate = translate_mac16, 3881 .par = (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_LH, 0}, 3882 }, { 3883 .name = "umul.aa.ll", 3884 .translate = translate_mac16, 3885 .par = (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_LL, 0}, 3886 }, { 3887 .name = "waiti", 3888 .translate = translate_waiti, 3889 }, { 3890 .name = "wdtlb", 3891 .translate = translate_wtlb, 3892 .par = (const uint32_t[]){true}, 3893 }, { 3894 .name = "wer", 3895 .translate = translate_wer, 3896 }, { 3897 .name = "witlb", 3898 .translate = translate_wtlb, 3899 .par = (const uint32_t[]){false}, 3900 }, { 3901 .name = "wrmsk_expstate", 3902 .translate = translate_wrmsk_expstate, 3903 }, { 3904 .name = "wsr.176", 3905 .translate = translate_wsr, 3906 .par = (const uint32_t[]){176}, 3907 }, { 3908 .name = "wsr.208", 3909 .translate = translate_wsr, 3910 .par = (const uint32_t[]){208}, 3911 }, { 3912 .name = "wsr.acchi", 3913 .translate = translate_wsr, 3914 .par = (const uint32_t[]){ACCHI}, 3915 }, { 3916 .name = "wsr.acclo", 3917 .translate = translate_wsr, 3918 .par = (const uint32_t[]){ACCLO}, 3919 }, { 3920 .name = "wsr.atomctl", 3921 .translate = translate_wsr, 3922 .par = (const uint32_t[]){ATOMCTL}, 3923 }, { 3924 .name = "wsr.br", 3925 .translate = translate_wsr, 3926 .par = (const uint32_t[]){BR}, 3927 }, { 3928 .name = "wsr.cacheattr", 3929 .translate = translate_wsr, 3930 .par = (const uint32_t[]){CACHEATTR}, 3931 }, { 3932 .name = "wsr.ccompare0", 3933 .translate = translate_wsr, 3934 .par = (const uint32_t[]){CCOMPARE}, 3935 }, { 3936 .name = "wsr.ccompare1", 3937 .translate = translate_wsr, 3938 .par = (const uint32_t[]){CCOMPARE + 1}, 3939 }, { 3940 .name = "wsr.ccompare2", 3941 .translate = translate_wsr, 3942 .par = (const uint32_t[]){CCOMPARE + 2}, 3943 }, { 3944 .name = "wsr.ccount", 3945 .translate = translate_wsr, 3946 .par = (const uint32_t[]){CCOUNT}, 3947 }, { 3948 .name = "wsr.configid0", 3949 .translate = translate_wsr, 3950 .par = (const uint32_t[]){CONFIGID0}, 3951 }, { 3952 .name = "wsr.configid1", 3953 .translate = translate_wsr, 3954 .par = (const uint32_t[]){CONFIGID1}, 3955 }, { 3956 .name = "wsr.cpenable", 3957 .translate = translate_wsr, 3958 .par = (const uint32_t[]){CPENABLE}, 3959 }, { 3960 .name = "wsr.dbreaka0", 3961 .translate = translate_wsr, 3962 .par = (const uint32_t[]){DBREAKA}, 3963 }, { 3964 .name = "wsr.dbreaka1", 3965 .translate = translate_wsr, 3966 .par = (const uint32_t[]){DBREAKA + 1}, 3967 }, { 3968 .name = "wsr.dbreakc0", 3969 .translate = translate_wsr, 3970 .par = (const uint32_t[]){DBREAKC}, 3971 }, { 3972 .name = "wsr.dbreakc1", 3973 .translate = translate_wsr, 3974 .par = (const uint32_t[]){DBREAKC + 1}, 3975 }, { 3976 .name = "wsr.ddr", 3977 .translate = translate_wsr, 3978 .par = (const uint32_t[]){DDR}, 3979 }, { 3980 .name = "wsr.debugcause", 3981 .translate = translate_wsr, 3982 .par = (const uint32_t[]){DEBUGCAUSE}, 3983 }, { 3984 .name = "wsr.depc", 3985 .translate = translate_wsr, 3986 .par = (const uint32_t[]){DEPC}, 3987 }, { 3988 .name = "wsr.dtlbcfg", 3989 .translate = translate_wsr, 3990 .par = (const uint32_t[]){DTLBCFG}, 3991 }, { 3992 .name = "wsr.epc1", 3993 .translate = translate_wsr, 3994 .par = (const uint32_t[]){EPC1}, 3995 }, { 3996 .name = "wsr.epc2", 3997 .translate = translate_wsr, 3998 .par = (const uint32_t[]){EPC1 + 1}, 3999 }, { 4000 .name = "wsr.epc3", 4001 .translate = translate_wsr, 4002 .par = (const uint32_t[]){EPC1 + 2}, 4003 }, { 4004 .name = "wsr.epc4", 4005 .translate = translate_wsr, 4006 .par = (const uint32_t[]){EPC1 + 3}, 4007 }, { 4008 .name = "wsr.epc5", 4009 .translate = translate_wsr, 4010 .par = (const uint32_t[]){EPC1 + 4}, 4011 }, { 4012 .name = "wsr.epc6", 4013 .translate = translate_wsr, 4014 .par = (const uint32_t[]){EPC1 + 5}, 4015 }, { 4016 .name = "wsr.epc7", 4017 .translate = translate_wsr, 4018 .par = (const uint32_t[]){EPC1 + 6}, 4019 }, { 4020 .name = "wsr.eps2", 4021 .translate = translate_wsr, 4022 .par = (const uint32_t[]){EPS2}, 4023 }, { 4024 .name = "wsr.eps3", 4025 .translate = translate_wsr, 4026 .par = (const uint32_t[]){EPS2 + 1}, 4027 }, { 4028 .name = "wsr.eps4", 4029 .translate = translate_wsr, 4030 .par = (const uint32_t[]){EPS2 + 2}, 4031 }, { 4032 .name = "wsr.eps5", 4033 .translate = translate_wsr, 4034 .par = (const uint32_t[]){EPS2 + 3}, 4035 }, { 4036 .name = "wsr.eps6", 4037 .translate = translate_wsr, 4038 .par = (const uint32_t[]){EPS2 + 4}, 4039 }, { 4040 .name = "wsr.eps7", 4041 .translate = translate_wsr, 4042 .par = (const uint32_t[]){EPS2 + 5}, 4043 }, { 4044 .name = "wsr.exccause", 4045 .translate = translate_wsr, 4046 .par = (const uint32_t[]){EXCCAUSE}, 4047 }, { 4048 .name = "wsr.excsave1", 4049 .translate = translate_wsr, 4050 .par = (const uint32_t[]){EXCSAVE1}, 4051 }, { 4052 .name = "wsr.excsave2", 4053 .translate = translate_wsr, 4054 .par = (const uint32_t[]){EXCSAVE1 + 1}, 4055 }, { 4056 .name = "wsr.excsave3", 4057 .translate = translate_wsr, 4058 .par = (const uint32_t[]){EXCSAVE1 + 2}, 4059 }, { 4060 .name = "wsr.excsave4", 4061 .translate = translate_wsr, 4062 .par = (const uint32_t[]){EXCSAVE1 + 3}, 4063 }, { 4064 .name = "wsr.excsave5", 4065 .translate = translate_wsr, 4066 .par = (const uint32_t[]){EXCSAVE1 + 4}, 4067 }, { 4068 .name = "wsr.excsave6", 4069 .translate = translate_wsr, 4070 .par = (const uint32_t[]){EXCSAVE1 + 5}, 4071 }, { 4072 .name = "wsr.excsave7", 4073 .translate = translate_wsr, 4074 .par = (const uint32_t[]){EXCSAVE1 + 6}, 4075 }, { 4076 .name = "wsr.excvaddr", 4077 .translate = translate_wsr, 4078 .par = (const uint32_t[]){EXCVADDR}, 4079 }, { 4080 .name = "wsr.ibreaka0", 4081 .translate = translate_wsr, 4082 .par = (const uint32_t[]){IBREAKA}, 4083 }, { 4084 .name = "wsr.ibreaka1", 4085 .translate = translate_wsr, 4086 .par = (const uint32_t[]){IBREAKA + 1}, 4087 }, { 4088 .name = "wsr.ibreakenable", 4089 .translate = translate_wsr, 4090 .par = (const uint32_t[]){IBREAKENABLE}, 4091 }, { 4092 .name = "wsr.icount", 4093 .translate = translate_wsr, 4094 .par = (const uint32_t[]){ICOUNT}, 4095 }, { 4096 .name = "wsr.icountlevel", 4097 .translate = translate_wsr, 4098 .par = (const uint32_t[]){ICOUNTLEVEL}, 4099 }, { 4100 .name = "wsr.intclear", 4101 .translate = translate_wsr, 4102 .par = (const uint32_t[]){INTCLEAR}, 4103 }, { 4104 .name = "wsr.intenable", 4105 .translate = translate_wsr, 4106 .par = (const uint32_t[]){INTENABLE}, 4107 }, { 4108 .name = "wsr.interrupt", 4109 .translate = translate_wsr, 4110 .par = (const uint32_t[]){INTSET}, 4111 }, { 4112 .name = "wsr.intset", 4113 .translate = translate_wsr, 4114 .par = (const uint32_t[]){INTSET}, 4115 }, { 4116 .name = "wsr.itlbcfg", 4117 .translate = translate_wsr, 4118 .par = (const uint32_t[]){ITLBCFG}, 4119 }, { 4120 .name = "wsr.lbeg", 4121 .translate = translate_wsr, 4122 .par = (const uint32_t[]){LBEG}, 4123 }, { 4124 .name = "wsr.lcount", 4125 .translate = translate_wsr, 4126 .par = (const uint32_t[]){LCOUNT}, 4127 }, { 4128 .name = "wsr.lend", 4129 .translate = translate_wsr, 4130 .par = (const uint32_t[]){LEND}, 4131 }, { 4132 .name = "wsr.litbase", 4133 .translate = translate_wsr, 4134 .par = (const uint32_t[]){LITBASE}, 4135 }, { 4136 .name = "wsr.m0", 4137 .translate = translate_wsr, 4138 .par = (const uint32_t[]){MR}, 4139 }, { 4140 .name = "wsr.m1", 4141 .translate = translate_wsr, 4142 .par = (const uint32_t[]){MR + 1}, 4143 }, { 4144 .name = "wsr.m2", 4145 .translate = translate_wsr, 4146 .par = (const uint32_t[]){MR + 2}, 4147 }, { 4148 .name = "wsr.m3", 4149 .translate = translate_wsr, 4150 .par = (const uint32_t[]){MR + 3}, 4151 }, { 4152 .name = "wsr.memctl", 4153 .translate = translate_wsr, 4154 .par = (const uint32_t[]){MEMCTL}, 4155 }, { 4156 .name = "wsr.misc0", 4157 .translate = translate_wsr, 4158 .par = (const uint32_t[]){MISC}, 4159 }, { 4160 .name = "wsr.misc1", 4161 .translate = translate_wsr, 4162 .par = (const uint32_t[]){MISC + 1}, 4163 }, { 4164 .name = "wsr.misc2", 4165 .translate = translate_wsr, 4166 .par = (const uint32_t[]){MISC + 2}, 4167 }, { 4168 .name = "wsr.misc3", 4169 .translate = translate_wsr, 4170 .par = (const uint32_t[]){MISC + 3}, 4171 }, { 4172 .name = "wsr.mmid", 4173 .translate = translate_wsr, 4174 .par = (const uint32_t[]){MMID}, 4175 }, { 4176 .name = "wsr.prid", 4177 .translate = translate_wsr, 4178 .par = (const uint32_t[]){PRID}, 4179 }, { 4180 .name = "wsr.ps", 4181 .translate = translate_wsr, 4182 .par = (const uint32_t[]){PS}, 4183 }, { 4184 .name = "wsr.ptevaddr", 4185 .translate = translate_wsr, 4186 .par = (const uint32_t[]){PTEVADDR}, 4187 }, { 4188 .name = "wsr.rasid", 4189 .translate = translate_wsr, 4190 .par = (const uint32_t[]){RASID}, 4191 }, { 4192 .name = "wsr.sar", 4193 .translate = translate_wsr, 4194 .par = (const uint32_t[]){SAR}, 4195 }, { 4196 .name = "wsr.scompare1", 4197 .translate = translate_wsr, 4198 .par = (const uint32_t[]){SCOMPARE1}, 4199 }, { 4200 .name = "wsr.vecbase", 4201 .translate = translate_wsr, 4202 .par = (const uint32_t[]){VECBASE}, 4203 }, { 4204 .name = "wsr.windowbase", 4205 .translate = translate_wsr, 4206 .par = (const uint32_t[]){WINDOW_BASE}, 4207 }, { 4208 .name = "wsr.windowstart", 4209 .translate = translate_wsr, 4210 .par = (const uint32_t[]){WINDOW_START}, 4211 }, { 4212 .name = "wur.expstate", 4213 .translate = translate_wur, 4214 .par = (const uint32_t[]){EXPSTATE}, 4215 }, { 4216 .name = "wur.fcr", 4217 .translate = translate_wur, 4218 .par = (const uint32_t[]){FCR}, 4219 }, { 4220 .name = "wur.fsr", 4221 .translate = translate_wur, 4222 .par = (const uint32_t[]){FSR}, 4223 }, { 4224 .name = "wur.threadptr", 4225 .translate = translate_wur, 4226 .par = (const uint32_t[]){THREADPTR}, 4227 }, { 4228 .name = "xor", 4229 .translate = translate_xor, 4230 }, { 4231 .name = "xorb", 4232 .translate = translate_boolean, 4233 .par = (const uint32_t[]){BOOLEAN_XOR}, 4234 }, { 4235 .name = "xsr.176", 4236 .translate = translate_xsr, 4237 .par = (const uint32_t[]){176}, 4238 }, { 4239 .name = "xsr.208", 4240 .translate = translate_xsr, 4241 .par = (const uint32_t[]){208}, 4242 }, { 4243 .name = "xsr.acchi", 4244 .translate = translate_xsr, 4245 .par = (const uint32_t[]){ACCHI}, 4246 }, { 4247 .name = "xsr.acclo", 4248 .translate = translate_xsr, 4249 .par = (const uint32_t[]){ACCLO}, 4250 }, { 4251 .name = "xsr.atomctl", 4252 .translate = translate_xsr, 4253 .par = (const uint32_t[]){ATOMCTL}, 4254 }, { 4255 .name = "xsr.br", 4256 .translate = translate_xsr, 4257 .par = (const uint32_t[]){BR}, 4258 }, { 4259 .name = "xsr.cacheattr", 4260 .translate = translate_xsr, 4261 .par = (const uint32_t[]){CACHEATTR}, 4262 }, { 4263 .name = "xsr.ccompare0", 4264 .translate = translate_xsr, 4265 .par = (const uint32_t[]){CCOMPARE}, 4266 }, { 4267 .name = "xsr.ccompare1", 4268 .translate = translate_xsr, 4269 .par = (const uint32_t[]){CCOMPARE + 1}, 4270 }, { 4271 .name = "xsr.ccompare2", 4272 .translate = translate_xsr, 4273 .par = (const uint32_t[]){CCOMPARE + 2}, 4274 }, { 4275 .name = "xsr.ccount", 4276 .translate = translate_xsr, 4277 .par = (const uint32_t[]){CCOUNT}, 4278 }, { 4279 .name = "xsr.configid0", 4280 .translate = translate_xsr, 4281 .par = (const uint32_t[]){CONFIGID0}, 4282 }, { 4283 .name = "xsr.configid1", 4284 .translate = translate_xsr, 4285 .par = (const uint32_t[]){CONFIGID1}, 4286 }, { 4287 .name = "xsr.cpenable", 4288 .translate = translate_xsr, 4289 .par = (const uint32_t[]){CPENABLE}, 4290 }, { 4291 .name = "xsr.dbreaka0", 4292 .translate = translate_xsr, 4293 .par = (const uint32_t[]){DBREAKA}, 4294 }, { 4295 .name = "xsr.dbreaka1", 4296 .translate = translate_xsr, 4297 .par = (const uint32_t[]){DBREAKA + 1}, 4298 }, { 4299 .name = "xsr.dbreakc0", 4300 .translate = translate_xsr, 4301 .par = (const uint32_t[]){DBREAKC}, 4302 }, { 4303 .name = "xsr.dbreakc1", 4304 .translate = translate_xsr, 4305 .par = (const uint32_t[]){DBREAKC + 1}, 4306 }, { 4307 .name = "xsr.ddr", 4308 .translate = translate_xsr, 4309 .par = (const uint32_t[]){DDR}, 4310 }, { 4311 .name = "xsr.debugcause", 4312 .translate = translate_xsr, 4313 .par = (const uint32_t[]){DEBUGCAUSE}, 4314 }, { 4315 .name = "xsr.depc", 4316 .translate = translate_xsr, 4317 .par = (const uint32_t[]){DEPC}, 4318 }, { 4319 .name = "xsr.dtlbcfg", 4320 .translate = translate_xsr, 4321 .par = (const uint32_t[]){DTLBCFG}, 4322 }, { 4323 .name = "xsr.epc1", 4324 .translate = translate_xsr, 4325 .par = (const uint32_t[]){EPC1}, 4326 }, { 4327 .name = "xsr.epc2", 4328 .translate = translate_xsr, 4329 .par = (const uint32_t[]){EPC1 + 1}, 4330 }, { 4331 .name = "xsr.epc3", 4332 .translate = translate_xsr, 4333 .par = (const uint32_t[]){EPC1 + 2}, 4334 }, { 4335 .name = "xsr.epc4", 4336 .translate = translate_xsr, 4337 .par = (const uint32_t[]){EPC1 + 3}, 4338 }, { 4339 .name = "xsr.epc5", 4340 .translate = translate_xsr, 4341 .par = (const uint32_t[]){EPC1 + 4}, 4342 }, { 4343 .name = "xsr.epc6", 4344 .translate = translate_xsr, 4345 .par = (const uint32_t[]){EPC1 + 5}, 4346 }, { 4347 .name = "xsr.epc7", 4348 .translate = translate_xsr, 4349 .par = (const uint32_t[]){EPC1 + 6}, 4350 }, { 4351 .name = "xsr.eps2", 4352 .translate = translate_xsr, 4353 .par = (const uint32_t[]){EPS2}, 4354 }, { 4355 .name = "xsr.eps3", 4356 .translate = translate_xsr, 4357 .par = (const uint32_t[]){EPS2 + 1}, 4358 }, { 4359 .name = "xsr.eps4", 4360 .translate = translate_xsr, 4361 .par = (const uint32_t[]){EPS2 + 2}, 4362 }, { 4363 .name = "xsr.eps5", 4364 .translate = translate_xsr, 4365 .par = (const uint32_t[]){EPS2 + 3}, 4366 }, { 4367 .name = "xsr.eps6", 4368 .translate = translate_xsr, 4369 .par = (const uint32_t[]){EPS2 + 4}, 4370 }, { 4371 .name = "xsr.eps7", 4372 .translate = translate_xsr, 4373 .par = (const uint32_t[]){EPS2 + 5}, 4374 }, { 4375 .name = "xsr.exccause", 4376 .translate = translate_xsr, 4377 .par = (const uint32_t[]){EXCCAUSE}, 4378 }, { 4379 .name = "xsr.excsave1", 4380 .translate = translate_xsr, 4381 .par = (const uint32_t[]){EXCSAVE1}, 4382 }, { 4383 .name = "xsr.excsave2", 4384 .translate = translate_xsr, 4385 .par = (const uint32_t[]){EXCSAVE1 + 1}, 4386 }, { 4387 .name = "xsr.excsave3", 4388 .translate = translate_xsr, 4389 .par = (const uint32_t[]){EXCSAVE1 + 2}, 4390 }, { 4391 .name = "xsr.excsave4", 4392 .translate = translate_xsr, 4393 .par = (const uint32_t[]){EXCSAVE1 + 3}, 4394 }, { 4395 .name = "xsr.excsave5", 4396 .translate = translate_xsr, 4397 .par = (const uint32_t[]){EXCSAVE1 + 4}, 4398 }, { 4399 .name = "xsr.excsave6", 4400 .translate = translate_xsr, 4401 .par = (const uint32_t[]){EXCSAVE1 + 5}, 4402 }, { 4403 .name = "xsr.excsave7", 4404 .translate = translate_xsr, 4405 .par = (const uint32_t[]){EXCSAVE1 + 6}, 4406 }, { 4407 .name = "xsr.excvaddr", 4408 .translate = translate_xsr, 4409 .par = (const uint32_t[]){EXCVADDR}, 4410 }, { 4411 .name = "xsr.ibreaka0", 4412 .translate = translate_xsr, 4413 .par = (const uint32_t[]){IBREAKA}, 4414 }, { 4415 .name = "xsr.ibreaka1", 4416 .translate = translate_xsr, 4417 .par = (const uint32_t[]){IBREAKA + 1}, 4418 }, { 4419 .name = "xsr.ibreakenable", 4420 .translate = translate_xsr, 4421 .par = (const uint32_t[]){IBREAKENABLE}, 4422 }, { 4423 .name = "xsr.icount", 4424 .translate = translate_xsr, 4425 .par = (const uint32_t[]){ICOUNT}, 4426 }, { 4427 .name = "xsr.icountlevel", 4428 .translate = translate_xsr, 4429 .par = (const uint32_t[]){ICOUNTLEVEL}, 4430 }, { 4431 .name = "xsr.intclear", 4432 .translate = translate_xsr, 4433 .par = (const uint32_t[]){INTCLEAR}, 4434 }, { 4435 .name = "xsr.intenable", 4436 .translate = translate_xsr, 4437 .par = (const uint32_t[]){INTENABLE}, 4438 }, { 4439 .name = "xsr.interrupt", 4440 .translate = translate_xsr, 4441 .par = (const uint32_t[]){INTSET}, 4442 }, { 4443 .name = "xsr.intset", 4444 .translate = translate_xsr, 4445 .par = (const uint32_t[]){INTSET}, 4446 }, { 4447 .name = "xsr.itlbcfg", 4448 .translate = translate_xsr, 4449 .par = (const uint32_t[]){ITLBCFG}, 4450 }, { 4451 .name = "xsr.lbeg", 4452 .translate = translate_xsr, 4453 .par = (const uint32_t[]){LBEG}, 4454 }, { 4455 .name = "xsr.lcount", 4456 .translate = translate_xsr, 4457 .par = (const uint32_t[]){LCOUNT}, 4458 }, { 4459 .name = "xsr.lend", 4460 .translate = translate_xsr, 4461 .par = (const uint32_t[]){LEND}, 4462 }, { 4463 .name = "xsr.litbase", 4464 .translate = translate_xsr, 4465 .par = (const uint32_t[]){LITBASE}, 4466 }, { 4467 .name = "xsr.m0", 4468 .translate = translate_xsr, 4469 .par = (const uint32_t[]){MR}, 4470 }, { 4471 .name = "xsr.m1", 4472 .translate = translate_xsr, 4473 .par = (const uint32_t[]){MR + 1}, 4474 }, { 4475 .name = "xsr.m2", 4476 .translate = translate_xsr, 4477 .par = (const uint32_t[]){MR + 2}, 4478 }, { 4479 .name = "xsr.m3", 4480 .translate = translate_xsr, 4481 .par = (const uint32_t[]){MR + 3}, 4482 }, { 4483 .name = "xsr.memctl", 4484 .translate = translate_xsr, 4485 .par = (const uint32_t[]){MEMCTL}, 4486 }, { 4487 .name = "xsr.misc0", 4488 .translate = translate_xsr, 4489 .par = (const uint32_t[]){MISC}, 4490 }, { 4491 .name = "xsr.misc1", 4492 .translate = translate_xsr, 4493 .par = (const uint32_t[]){MISC + 1}, 4494 }, { 4495 .name = "xsr.misc2", 4496 .translate = translate_xsr, 4497 .par = (const uint32_t[]){MISC + 2}, 4498 }, { 4499 .name = "xsr.misc3", 4500 .translate = translate_xsr, 4501 .par = (const uint32_t[]){MISC + 3}, 4502 }, { 4503 .name = "xsr.prid", 4504 .translate = translate_xsr, 4505 .par = (const uint32_t[]){PRID}, 4506 }, { 4507 .name = "xsr.ps", 4508 .translate = translate_xsr, 4509 .par = (const uint32_t[]){PS}, 4510 }, { 4511 .name = "xsr.ptevaddr", 4512 .translate = translate_xsr, 4513 .par = (const uint32_t[]){PTEVADDR}, 4514 }, { 4515 .name = "xsr.rasid", 4516 .translate = translate_xsr, 4517 .par = (const uint32_t[]){RASID}, 4518 }, { 4519 .name = "xsr.sar", 4520 .translate = translate_xsr, 4521 .par = (const uint32_t[]){SAR}, 4522 }, { 4523 .name = "xsr.scompare1", 4524 .translate = translate_xsr, 4525 .par = (const uint32_t[]){SCOMPARE1}, 4526 }, { 4527 .name = "xsr.vecbase", 4528 .translate = translate_xsr, 4529 .par = (const uint32_t[]){VECBASE}, 4530 }, { 4531 .name = "xsr.windowbase", 4532 .translate = translate_xsr, 4533 .par = (const uint32_t[]){WINDOW_BASE}, 4534 }, { 4535 .name = "xsr.windowstart", 4536 .translate = translate_xsr, 4537 .par = (const uint32_t[]){WINDOW_START}, 4538 }, 4539 }; 4540 4541 const XtensaOpcodeTranslators xtensa_core_opcodes = { 4542 .num_opcodes = ARRAY_SIZE(core_ops), 4543 .opcode = core_ops, 4544 }; 4545 4546 4547 static void translate_abs_s(DisasContext *dc, const uint32_t arg[], 4548 const uint32_t par[]) 4549 { 4550 if (gen_check_cpenable(dc, 0)) { 4551 gen_helper_abs_s(cpu_FR[arg[0]], cpu_FR[arg[1]]); 4552 } 4553 } 4554 4555 static void translate_add_s(DisasContext *dc, const uint32_t arg[], 4556 const uint32_t par[]) 4557 { 4558 if (gen_check_cpenable(dc, 0)) { 4559 gen_helper_add_s(cpu_FR[arg[0]], cpu_env, 4560 cpu_FR[arg[1]], cpu_FR[arg[2]]); 4561 } 4562 } 4563 4564 enum { 4565 COMPARE_UN, 4566 COMPARE_OEQ, 4567 COMPARE_UEQ, 4568 COMPARE_OLT, 4569 COMPARE_ULT, 4570 COMPARE_OLE, 4571 COMPARE_ULE, 4572 }; 4573 4574 static void translate_compare_s(DisasContext *dc, const uint32_t arg[], 4575 const uint32_t par[]) 4576 { 4577 static void (* const helper[])(TCGv_env env, TCGv_i32 bit, 4578 TCGv_i32 s, TCGv_i32 t) = { 4579 [COMPARE_UN] = gen_helper_un_s, 4580 [COMPARE_OEQ] = gen_helper_oeq_s, 4581 [COMPARE_UEQ] = gen_helper_ueq_s, 4582 [COMPARE_OLT] = gen_helper_olt_s, 4583 [COMPARE_ULT] = gen_helper_ult_s, 4584 [COMPARE_OLE] = gen_helper_ole_s, 4585 [COMPARE_ULE] = gen_helper_ule_s, 4586 }; 4587 4588 if (gen_check_cpenable(dc, 0)) { 4589 TCGv_i32 bit = tcg_const_i32(1 << arg[0]); 4590 4591 helper[par[0]](cpu_env, bit, cpu_FR[arg[1]], cpu_FR[arg[2]]); 4592 tcg_temp_free(bit); 4593 } 4594 } 4595 4596 static void translate_float_s(DisasContext *dc, const uint32_t arg[], 4597 const uint32_t par[]) 4598 { 4599 if (gen_window_check1(dc, arg[1]) && gen_check_cpenable(dc, 0)) { 4600 TCGv_i32 scale = tcg_const_i32(-arg[2]); 4601 4602 if (par[0]) { 4603 gen_helper_uitof(cpu_FR[arg[0]], cpu_env, cpu_R[arg[1]], scale); 4604 } else { 4605 gen_helper_itof(cpu_FR[arg[0]], cpu_env, cpu_R[arg[1]], scale); 4606 } 4607 tcg_temp_free(scale); 4608 } 4609 } 4610 4611 static void translate_ftoi_s(DisasContext *dc, const uint32_t arg[], 4612 const uint32_t par[]) 4613 { 4614 if (gen_window_check1(dc, arg[0]) && gen_check_cpenable(dc, 0)) { 4615 TCGv_i32 rounding_mode = tcg_const_i32(par[0]); 4616 TCGv_i32 scale = tcg_const_i32(arg[2]); 4617 4618 if (par[1]) { 4619 gen_helper_ftoui(cpu_R[arg[0]], cpu_FR[arg[1]], 4620 rounding_mode, scale); 4621 } else { 4622 gen_helper_ftoi(cpu_R[arg[0]], cpu_FR[arg[1]], 4623 rounding_mode, scale); 4624 } 4625 tcg_temp_free(rounding_mode); 4626 tcg_temp_free(scale); 4627 } 4628 } 4629 4630 static void translate_ldsti(DisasContext *dc, const uint32_t arg[], 4631 const uint32_t par[]) 4632 { 4633 if (gen_window_check1(dc, arg[1]) && gen_check_cpenable(dc, 0)) { 4634 TCGv_i32 addr = tcg_temp_new_i32(); 4635 4636 tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]); 4637 gen_load_store_alignment(dc, 2, addr, false); 4638 if (par[0]) { 4639 tcg_gen_qemu_st32(cpu_FR[arg[0]], addr, dc->cring); 4640 } else { 4641 tcg_gen_qemu_ld32u(cpu_FR[arg[0]], addr, dc->cring); 4642 } 4643 if (par[1]) { 4644 tcg_gen_mov_i32(cpu_R[arg[1]], addr); 4645 } 4646 tcg_temp_free(addr); 4647 } 4648 } 4649 4650 static void translate_ldstx(DisasContext *dc, const uint32_t arg[], 4651 const uint32_t par[]) 4652 { 4653 if (gen_window_check2(dc, arg[1], arg[2]) && gen_check_cpenable(dc, 0)) { 4654 TCGv_i32 addr = tcg_temp_new_i32(); 4655 4656 tcg_gen_add_i32(addr, cpu_R[arg[1]], cpu_R[arg[2]]); 4657 gen_load_store_alignment(dc, 2, addr, false); 4658 if (par[0]) { 4659 tcg_gen_qemu_st32(cpu_FR[arg[0]], addr, dc->cring); 4660 } else { 4661 tcg_gen_qemu_ld32u(cpu_FR[arg[0]], addr, dc->cring); 4662 } 4663 if (par[1]) { 4664 tcg_gen_mov_i32(cpu_R[arg[1]], addr); 4665 } 4666 tcg_temp_free(addr); 4667 } 4668 } 4669 4670 static void translate_madd_s(DisasContext *dc, const uint32_t arg[], 4671 const uint32_t par[]) 4672 { 4673 if (gen_check_cpenable(dc, 0)) { 4674 gen_helper_madd_s(cpu_FR[arg[0]], cpu_env, 4675 cpu_FR[arg[0]], cpu_FR[arg[1]], cpu_FR[arg[2]]); 4676 } 4677 } 4678 4679 static void translate_mov_s(DisasContext *dc, const uint32_t arg[], 4680 const uint32_t par[]) 4681 { 4682 if (gen_check_cpenable(dc, 0)) { 4683 tcg_gen_mov_i32(cpu_FR[arg[0]], cpu_FR[arg[1]]); 4684 } 4685 } 4686 4687 static void translate_movcond_s(DisasContext *dc, const uint32_t arg[], 4688 const uint32_t par[]) 4689 { 4690 if (gen_window_check1(dc, arg[2]) && gen_check_cpenable(dc, 0)) { 4691 TCGv_i32 zero = tcg_const_i32(0); 4692 4693 tcg_gen_movcond_i32(par[0], cpu_FR[arg[0]], 4694 cpu_R[arg[2]], zero, 4695 cpu_FR[arg[1]], cpu_FR[arg[2]]); 4696 tcg_temp_free(zero); 4697 } 4698 } 4699 4700 static void translate_movp_s(DisasContext *dc, const uint32_t arg[], 4701 const uint32_t par[]) 4702 { 4703 if (gen_check_cpenable(dc, 0)) { 4704 TCGv_i32 zero = tcg_const_i32(0); 4705 TCGv_i32 tmp = tcg_temp_new_i32(); 4706 4707 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << arg[2]); 4708 tcg_gen_movcond_i32(par[0], 4709 cpu_FR[arg[0]], tmp, zero, 4710 cpu_FR[arg[1]], cpu_FR[arg[0]]); 4711 tcg_temp_free(tmp); 4712 tcg_temp_free(zero); 4713 } 4714 } 4715 4716 static void translate_mul_s(DisasContext *dc, const uint32_t arg[], 4717 const uint32_t par[]) 4718 { 4719 if (gen_check_cpenable(dc, 0)) { 4720 gen_helper_mul_s(cpu_FR[arg[0]], cpu_env, 4721 cpu_FR[arg[1]], cpu_FR[arg[2]]); 4722 } 4723 } 4724 4725 static void translate_msub_s(DisasContext *dc, const uint32_t arg[], 4726 const uint32_t par[]) 4727 { 4728 if (gen_check_cpenable(dc, 0)) { 4729 gen_helper_msub_s(cpu_FR[arg[0]], cpu_env, 4730 cpu_FR[arg[0]], cpu_FR[arg[1]], cpu_FR[arg[2]]); 4731 } 4732 } 4733 4734 static void translate_neg_s(DisasContext *dc, const uint32_t arg[], 4735 const uint32_t par[]) 4736 { 4737 if (gen_check_cpenable(dc, 0)) { 4738 gen_helper_neg_s(cpu_FR[arg[0]], cpu_FR[arg[1]]); 4739 } 4740 } 4741 4742 static void translate_rfr_s(DisasContext *dc, const uint32_t arg[], 4743 const uint32_t par[]) 4744 { 4745 if (gen_window_check1(dc, arg[0]) && 4746 gen_check_cpenable(dc, 0)) { 4747 tcg_gen_mov_i32(cpu_R[arg[0]], cpu_FR[arg[1]]); 4748 } 4749 } 4750 4751 static void translate_sub_s(DisasContext *dc, const uint32_t arg[], 4752 const uint32_t par[]) 4753 { 4754 if (gen_check_cpenable(dc, 0)) { 4755 gen_helper_sub_s(cpu_FR[arg[0]], cpu_env, 4756 cpu_FR[arg[1]], cpu_FR[arg[2]]); 4757 } 4758 } 4759 4760 static void translate_wfr_s(DisasContext *dc, const uint32_t arg[], 4761 const uint32_t par[]) 4762 { 4763 if (gen_window_check1(dc, arg[1]) && 4764 gen_check_cpenable(dc, 0)) { 4765 tcg_gen_mov_i32(cpu_FR[arg[0]], cpu_R[arg[1]]); 4766 } 4767 } 4768 4769 static const XtensaOpcodeOps fpu2000_ops[] = { 4770 { 4771 .name = "abs.s", 4772 .translate = translate_abs_s, 4773 }, { 4774 .name = "add.s", 4775 .translate = translate_add_s, 4776 }, { 4777 .name = "ceil.s", 4778 .translate = translate_ftoi_s, 4779 .par = (const uint32_t[]){float_round_up, false}, 4780 }, { 4781 .name = "float.s", 4782 .translate = translate_float_s, 4783 .par = (const uint32_t[]){false}, 4784 }, { 4785 .name = "floor.s", 4786 .translate = translate_ftoi_s, 4787 .par = (const uint32_t[]){float_round_down, false}, 4788 }, { 4789 .name = "lsi", 4790 .translate = translate_ldsti, 4791 .par = (const uint32_t[]){false, false}, 4792 }, { 4793 .name = "lsiu", 4794 .translate = translate_ldsti, 4795 .par = (const uint32_t[]){false, true}, 4796 }, { 4797 .name = "lsx", 4798 .translate = translate_ldstx, 4799 .par = (const uint32_t[]){false, false}, 4800 }, { 4801 .name = "lsxu", 4802 .translate = translate_ldstx, 4803 .par = (const uint32_t[]){false, true}, 4804 }, { 4805 .name = "madd.s", 4806 .translate = translate_madd_s, 4807 }, { 4808 .name = "mov.s", 4809 .translate = translate_mov_s, 4810 }, { 4811 .name = "moveqz.s", 4812 .translate = translate_movcond_s, 4813 .par = (const uint32_t[]){TCG_COND_EQ}, 4814 }, { 4815 .name = "movf.s", 4816 .translate = translate_movp_s, 4817 .par = (const uint32_t[]){TCG_COND_EQ}, 4818 }, { 4819 .name = "movgez.s", 4820 .translate = translate_movcond_s, 4821 .par = (const uint32_t[]){TCG_COND_GE}, 4822 }, { 4823 .name = "movltz.s", 4824 .translate = translate_movcond_s, 4825 .par = (const uint32_t[]){TCG_COND_LT}, 4826 }, { 4827 .name = "movnez.s", 4828 .translate = translate_movcond_s, 4829 .par = (const uint32_t[]){TCG_COND_NE}, 4830 }, { 4831 .name = "movt.s", 4832 .translate = translate_movp_s, 4833 .par = (const uint32_t[]){TCG_COND_NE}, 4834 }, { 4835 .name = "msub.s", 4836 .translate = translate_msub_s, 4837 }, { 4838 .name = "mul.s", 4839 .translate = translate_mul_s, 4840 }, { 4841 .name = "neg.s", 4842 .translate = translate_neg_s, 4843 }, { 4844 .name = "oeq.s", 4845 .translate = translate_compare_s, 4846 .par = (const uint32_t[]){COMPARE_OEQ}, 4847 }, { 4848 .name = "ole.s", 4849 .translate = translate_compare_s, 4850 .par = (const uint32_t[]){COMPARE_OLE}, 4851 }, { 4852 .name = "olt.s", 4853 .translate = translate_compare_s, 4854 .par = (const uint32_t[]){COMPARE_OLT}, 4855 }, { 4856 .name = "rfr.s", 4857 .translate = translate_rfr_s, 4858 }, { 4859 .name = "round.s", 4860 .translate = translate_ftoi_s, 4861 .par = (const uint32_t[]){float_round_nearest_even, false}, 4862 }, { 4863 .name = "ssi", 4864 .translate = translate_ldsti, 4865 .par = (const uint32_t[]){true, false}, 4866 }, { 4867 .name = "ssiu", 4868 .translate = translate_ldsti, 4869 .par = (const uint32_t[]){true, true}, 4870 }, { 4871 .name = "ssx", 4872 .translate = translate_ldstx, 4873 .par = (const uint32_t[]){true, false}, 4874 }, { 4875 .name = "ssxu", 4876 .translate = translate_ldstx, 4877 .par = (const uint32_t[]){true, true}, 4878 }, { 4879 .name = "sub.s", 4880 .translate = translate_sub_s, 4881 }, { 4882 .name = "trunc.s", 4883 .translate = translate_ftoi_s, 4884 .par = (const uint32_t[]){float_round_to_zero, false}, 4885 }, { 4886 .name = "ueq.s", 4887 .translate = translate_compare_s, 4888 .par = (const uint32_t[]){COMPARE_UEQ}, 4889 }, { 4890 .name = "ufloat.s", 4891 .translate = translate_float_s, 4892 .par = (const uint32_t[]){true}, 4893 }, { 4894 .name = "ule.s", 4895 .translate = translate_compare_s, 4896 .par = (const uint32_t[]){COMPARE_ULE}, 4897 }, { 4898 .name = "ult.s", 4899 .translate = translate_compare_s, 4900 .par = (const uint32_t[]){COMPARE_ULT}, 4901 }, { 4902 .name = "un.s", 4903 .translate = translate_compare_s, 4904 .par = (const uint32_t[]){COMPARE_UN}, 4905 }, { 4906 .name = "utrunc.s", 4907 .translate = translate_ftoi_s, 4908 .par = (const uint32_t[]){float_round_to_zero, true}, 4909 }, { 4910 .name = "wfr.s", 4911 .translate = translate_wfr_s, 4912 }, 4913 }; 4914 4915 const XtensaOpcodeTranslators xtensa_fpu2000_opcodes = { 4916 .num_opcodes = ARRAY_SIZE(fpu2000_ops), 4917 .opcode = fpu2000_ops, 4918 }; 4919