1 /* 2 * Xtensa ISA: 3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm 4 * 5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * * Neither the name of the Open Source and Linux Lab nor the 16 * names of its contributors may be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include "qemu/osdep.h" 32 33 #include "cpu.h" 34 #include "exec/exec-all.h" 35 #include "disas/disas.h" 36 #include "tcg-op.h" 37 #include "qemu/log.h" 38 #include "sysemu/sysemu.h" 39 #include "exec/cpu_ldst.h" 40 #include "exec/semihost.h" 41 #include "exec/translator.h" 42 43 #include "exec/helper-proto.h" 44 #include "exec/helper-gen.h" 45 46 #include "trace-tcg.h" 47 #include "exec/log.h" 48 49 50 struct DisasContext { 51 DisasContextBase base; 52 const XtensaConfig *config; 53 uint32_t pc; 54 int cring; 55 int ring; 56 uint32_t lbeg_off; 57 uint32_t lend; 58 59 bool sar_5bit; 60 bool sar_m32_5bit; 61 bool sar_m32_allocated; 62 TCGv_i32 sar_m32; 63 64 unsigned window; 65 unsigned callinc; 66 bool cwoe; 67 68 bool debug; 69 bool icount; 70 TCGv_i32 next_icount; 71 72 unsigned cpenable; 73 74 uint32_t *raw_arg; 75 xtensa_insnbuf insnbuf; 76 xtensa_insnbuf slotbuf; 77 }; 78 79 static TCGv_i32 cpu_pc; 80 static TCGv_i32 cpu_R[16]; 81 static TCGv_i32 cpu_FR[16]; 82 static TCGv_i32 cpu_SR[256]; 83 static TCGv_i32 cpu_UR[256]; 84 85 #include "exec/gen-icount.h" 86 87 typedef struct XtensaReg { 88 const char *name; 89 uint64_t opt_bits; 90 enum { 91 SR_R = 1, 92 SR_W = 2, 93 SR_X = 4, 94 SR_RW = 3, 95 SR_RWX = 7, 96 } access; 97 } XtensaReg; 98 99 #define XTENSA_REG_ACCESS(regname, opt, acc) { \ 100 .name = (regname), \ 101 .opt_bits = XTENSA_OPTION_BIT(opt), \ 102 .access = (acc), \ 103 } 104 105 #define XTENSA_REG(regname, opt) XTENSA_REG_ACCESS(regname, opt, SR_RWX) 106 107 #define XTENSA_REG_BITS_ACCESS(regname, opt, acc) { \ 108 .name = (regname), \ 109 .opt_bits = (opt), \ 110 .access = (acc), \ 111 } 112 113 #define XTENSA_REG_BITS(regname, opt) \ 114 XTENSA_REG_BITS_ACCESS(regname, opt, SR_RWX) 115 116 static const XtensaReg sregnames[256] = { 117 [LBEG] = XTENSA_REG("LBEG", XTENSA_OPTION_LOOP), 118 [LEND] = XTENSA_REG("LEND", XTENSA_OPTION_LOOP), 119 [LCOUNT] = XTENSA_REG("LCOUNT", XTENSA_OPTION_LOOP), 120 [SAR] = XTENSA_REG_BITS("SAR", XTENSA_OPTION_ALL), 121 [BR] = XTENSA_REG("BR", XTENSA_OPTION_BOOLEAN), 122 [LITBASE] = XTENSA_REG("LITBASE", XTENSA_OPTION_EXTENDED_L32R), 123 [SCOMPARE1] = XTENSA_REG("SCOMPARE1", XTENSA_OPTION_CONDITIONAL_STORE), 124 [ACCLO] = XTENSA_REG("ACCLO", XTENSA_OPTION_MAC16), 125 [ACCHI] = XTENSA_REG("ACCHI", XTENSA_OPTION_MAC16), 126 [MR] = XTENSA_REG("MR0", XTENSA_OPTION_MAC16), 127 [MR + 1] = XTENSA_REG("MR1", XTENSA_OPTION_MAC16), 128 [MR + 2] = XTENSA_REG("MR2", XTENSA_OPTION_MAC16), 129 [MR + 3] = XTENSA_REG("MR3", XTENSA_OPTION_MAC16), 130 [WINDOW_BASE] = XTENSA_REG("WINDOW_BASE", XTENSA_OPTION_WINDOWED_REGISTER), 131 [WINDOW_START] = XTENSA_REG("WINDOW_START", 132 XTENSA_OPTION_WINDOWED_REGISTER), 133 [PTEVADDR] = XTENSA_REG("PTEVADDR", XTENSA_OPTION_MMU), 134 [MMID] = XTENSA_REG_BITS("MMID", XTENSA_OPTION_ALL), 135 [RASID] = XTENSA_REG("RASID", XTENSA_OPTION_MMU), 136 [ITLBCFG] = XTENSA_REG("ITLBCFG", XTENSA_OPTION_MMU), 137 [DTLBCFG] = XTENSA_REG("DTLBCFG", XTENSA_OPTION_MMU), 138 [IBREAKENABLE] = XTENSA_REG("IBREAKENABLE", XTENSA_OPTION_DEBUG), 139 [MEMCTL] = XTENSA_REG_BITS("MEMCTL", XTENSA_OPTION_ALL), 140 [CACHEATTR] = XTENSA_REG("CACHEATTR", XTENSA_OPTION_CACHEATTR), 141 [ATOMCTL] = XTENSA_REG("ATOMCTL", XTENSA_OPTION_ATOMCTL), 142 [DDR] = XTENSA_REG("DDR", XTENSA_OPTION_DEBUG), 143 [IBREAKA] = XTENSA_REG("IBREAKA0", XTENSA_OPTION_DEBUG), 144 [IBREAKA + 1] = XTENSA_REG("IBREAKA1", XTENSA_OPTION_DEBUG), 145 [DBREAKA] = XTENSA_REG("DBREAKA0", XTENSA_OPTION_DEBUG), 146 [DBREAKA + 1] = XTENSA_REG("DBREAKA1", XTENSA_OPTION_DEBUG), 147 [DBREAKC] = XTENSA_REG("DBREAKC0", XTENSA_OPTION_DEBUG), 148 [DBREAKC + 1] = XTENSA_REG("DBREAKC1", XTENSA_OPTION_DEBUG), 149 [CONFIGID0] = XTENSA_REG_BITS_ACCESS("CONFIGID0", XTENSA_OPTION_ALL, SR_R), 150 [EPC1] = XTENSA_REG("EPC1", XTENSA_OPTION_EXCEPTION), 151 [EPC1 + 1] = XTENSA_REG("EPC2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 152 [EPC1 + 2] = XTENSA_REG("EPC3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 153 [EPC1 + 3] = XTENSA_REG("EPC4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 154 [EPC1 + 4] = XTENSA_REG("EPC5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 155 [EPC1 + 5] = XTENSA_REG("EPC6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 156 [EPC1 + 6] = XTENSA_REG("EPC7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 157 [DEPC] = XTENSA_REG("DEPC", XTENSA_OPTION_EXCEPTION), 158 [EPS2] = XTENSA_REG("EPS2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 159 [EPS2 + 1] = XTENSA_REG("EPS3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 160 [EPS2 + 2] = XTENSA_REG("EPS4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 161 [EPS2 + 3] = XTENSA_REG("EPS5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 162 [EPS2 + 4] = XTENSA_REG("EPS6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 163 [EPS2 + 5] = XTENSA_REG("EPS7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 164 [CONFIGID1] = XTENSA_REG_BITS_ACCESS("CONFIGID1", XTENSA_OPTION_ALL, SR_R), 165 [EXCSAVE1] = XTENSA_REG("EXCSAVE1", XTENSA_OPTION_EXCEPTION), 166 [EXCSAVE1 + 1] = XTENSA_REG("EXCSAVE2", 167 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 168 [EXCSAVE1 + 2] = XTENSA_REG("EXCSAVE3", 169 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 170 [EXCSAVE1 + 3] = XTENSA_REG("EXCSAVE4", 171 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 172 [EXCSAVE1 + 4] = XTENSA_REG("EXCSAVE5", 173 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 174 [EXCSAVE1 + 5] = XTENSA_REG("EXCSAVE6", 175 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 176 [EXCSAVE1 + 6] = XTENSA_REG("EXCSAVE7", 177 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 178 [CPENABLE] = XTENSA_REG("CPENABLE", XTENSA_OPTION_COPROCESSOR), 179 [INTSET] = XTENSA_REG_ACCESS("INTSET", XTENSA_OPTION_INTERRUPT, SR_RW), 180 [INTCLEAR] = XTENSA_REG_ACCESS("INTCLEAR", XTENSA_OPTION_INTERRUPT, SR_W), 181 [INTENABLE] = XTENSA_REG("INTENABLE", XTENSA_OPTION_INTERRUPT), 182 [PS] = XTENSA_REG_BITS("PS", XTENSA_OPTION_ALL), 183 [VECBASE] = XTENSA_REG("VECBASE", XTENSA_OPTION_RELOCATABLE_VECTOR), 184 [EXCCAUSE] = XTENSA_REG("EXCCAUSE", XTENSA_OPTION_EXCEPTION), 185 [DEBUGCAUSE] = XTENSA_REG_ACCESS("DEBUGCAUSE", XTENSA_OPTION_DEBUG, SR_R), 186 [CCOUNT] = XTENSA_REG("CCOUNT", XTENSA_OPTION_TIMER_INTERRUPT), 187 [PRID] = XTENSA_REG_ACCESS("PRID", XTENSA_OPTION_PROCESSOR_ID, SR_R), 188 [ICOUNT] = XTENSA_REG("ICOUNT", XTENSA_OPTION_DEBUG), 189 [ICOUNTLEVEL] = XTENSA_REG("ICOUNTLEVEL", XTENSA_OPTION_DEBUG), 190 [EXCVADDR] = XTENSA_REG("EXCVADDR", XTENSA_OPTION_EXCEPTION), 191 [CCOMPARE] = XTENSA_REG("CCOMPARE0", XTENSA_OPTION_TIMER_INTERRUPT), 192 [CCOMPARE + 1] = XTENSA_REG("CCOMPARE1", 193 XTENSA_OPTION_TIMER_INTERRUPT), 194 [CCOMPARE + 2] = XTENSA_REG("CCOMPARE2", 195 XTENSA_OPTION_TIMER_INTERRUPT), 196 [MISC] = XTENSA_REG("MISC0", XTENSA_OPTION_MISC_SR), 197 [MISC + 1] = XTENSA_REG("MISC1", XTENSA_OPTION_MISC_SR), 198 [MISC + 2] = XTENSA_REG("MISC2", XTENSA_OPTION_MISC_SR), 199 [MISC + 3] = XTENSA_REG("MISC3", XTENSA_OPTION_MISC_SR), 200 }; 201 202 static const XtensaReg uregnames[256] = { 203 [EXPSTATE] = XTENSA_REG_BITS("EXPSTATE", XTENSA_OPTION_ALL), 204 [THREADPTR] = XTENSA_REG("THREADPTR", XTENSA_OPTION_THREAD_POINTER), 205 [FCR] = XTENSA_REG("FCR", XTENSA_OPTION_FP_COPROCESSOR), 206 [FSR] = XTENSA_REG("FSR", XTENSA_OPTION_FP_COPROCESSOR), 207 }; 208 209 void xtensa_translate_init(void) 210 { 211 static const char * const regnames[] = { 212 "ar0", "ar1", "ar2", "ar3", 213 "ar4", "ar5", "ar6", "ar7", 214 "ar8", "ar9", "ar10", "ar11", 215 "ar12", "ar13", "ar14", "ar15", 216 }; 217 static const char * const fregnames[] = { 218 "f0", "f1", "f2", "f3", 219 "f4", "f5", "f6", "f7", 220 "f8", "f9", "f10", "f11", 221 "f12", "f13", "f14", "f15", 222 }; 223 int i; 224 225 cpu_pc = tcg_global_mem_new_i32(cpu_env, 226 offsetof(CPUXtensaState, pc), "pc"); 227 228 for (i = 0; i < 16; i++) { 229 cpu_R[i] = tcg_global_mem_new_i32(cpu_env, 230 offsetof(CPUXtensaState, regs[i]), 231 regnames[i]); 232 } 233 234 for (i = 0; i < 16; i++) { 235 cpu_FR[i] = tcg_global_mem_new_i32(cpu_env, 236 offsetof(CPUXtensaState, fregs[i].f32[FP_F32_LOW]), 237 fregnames[i]); 238 } 239 240 for (i = 0; i < 256; ++i) { 241 if (sregnames[i].name) { 242 cpu_SR[i] = tcg_global_mem_new_i32(cpu_env, 243 offsetof(CPUXtensaState, sregs[i]), 244 sregnames[i].name); 245 } 246 } 247 248 for (i = 0; i < 256; ++i) { 249 if (uregnames[i].name) { 250 cpu_UR[i] = tcg_global_mem_new_i32(cpu_env, 251 offsetof(CPUXtensaState, uregs[i]), 252 uregnames[i].name); 253 } 254 } 255 } 256 257 static inline bool option_enabled(DisasContext *dc, int opt) 258 { 259 return xtensa_option_enabled(dc->config, opt); 260 } 261 262 static void init_sar_tracker(DisasContext *dc) 263 { 264 dc->sar_5bit = false; 265 dc->sar_m32_5bit = false; 266 dc->sar_m32_allocated = false; 267 } 268 269 static void reset_sar_tracker(DisasContext *dc) 270 { 271 if (dc->sar_m32_allocated) { 272 tcg_temp_free(dc->sar_m32); 273 } 274 } 275 276 static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa) 277 { 278 tcg_gen_andi_i32(cpu_SR[SAR], sa, 0x1f); 279 if (dc->sar_m32_5bit) { 280 tcg_gen_discard_i32(dc->sar_m32); 281 } 282 dc->sar_5bit = true; 283 dc->sar_m32_5bit = false; 284 } 285 286 static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa) 287 { 288 TCGv_i32 tmp = tcg_const_i32(32); 289 if (!dc->sar_m32_allocated) { 290 dc->sar_m32 = tcg_temp_local_new_i32(); 291 dc->sar_m32_allocated = true; 292 } 293 tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f); 294 tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32); 295 dc->sar_5bit = false; 296 dc->sar_m32_5bit = true; 297 tcg_temp_free(tmp); 298 } 299 300 static void gen_exception(DisasContext *dc, int excp) 301 { 302 TCGv_i32 tmp = tcg_const_i32(excp); 303 gen_helper_exception(cpu_env, tmp); 304 tcg_temp_free(tmp); 305 } 306 307 static void gen_exception_cause(DisasContext *dc, uint32_t cause) 308 { 309 TCGv_i32 tpc = tcg_const_i32(dc->pc); 310 TCGv_i32 tcause = tcg_const_i32(cause); 311 gen_helper_exception_cause(cpu_env, tpc, tcause); 312 tcg_temp_free(tpc); 313 tcg_temp_free(tcause); 314 if (cause == ILLEGAL_INSTRUCTION_CAUSE || 315 cause == SYSCALL_CAUSE) { 316 dc->base.is_jmp = DISAS_NORETURN; 317 } 318 } 319 320 static void gen_exception_cause_vaddr(DisasContext *dc, uint32_t cause, 321 TCGv_i32 vaddr) 322 { 323 TCGv_i32 tpc = tcg_const_i32(dc->pc); 324 TCGv_i32 tcause = tcg_const_i32(cause); 325 gen_helper_exception_cause_vaddr(cpu_env, tpc, tcause, vaddr); 326 tcg_temp_free(tpc); 327 tcg_temp_free(tcause); 328 } 329 330 static void gen_debug_exception(DisasContext *dc, uint32_t cause) 331 { 332 TCGv_i32 tpc = tcg_const_i32(dc->pc); 333 TCGv_i32 tcause = tcg_const_i32(cause); 334 gen_helper_debug_exception(cpu_env, tpc, tcause); 335 tcg_temp_free(tpc); 336 tcg_temp_free(tcause); 337 if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) { 338 dc->base.is_jmp = DISAS_NORETURN; 339 } 340 } 341 342 static bool gen_check_privilege(DisasContext *dc) 343 { 344 #ifndef CONFIG_USER_ONLY 345 if (!dc->cring) { 346 return true; 347 } 348 #endif 349 gen_exception_cause(dc, PRIVILEGED_CAUSE); 350 dc->base.is_jmp = DISAS_NORETURN; 351 return false; 352 } 353 354 static bool gen_check_cpenable(DisasContext *dc, uint32_t cp_mask) 355 { 356 cp_mask &= ~dc->cpenable; 357 358 if (option_enabled(dc, XTENSA_OPTION_COPROCESSOR) && cp_mask) { 359 gen_exception_cause(dc, COPROCESSOR0_DISABLED + ctz32(cp_mask)); 360 dc->base.is_jmp = DISAS_NORETURN; 361 return false; 362 } 363 return true; 364 } 365 366 static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot) 367 { 368 tcg_gen_mov_i32(cpu_pc, dest); 369 if (dc->icount) { 370 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount); 371 } 372 if (dc->base.singlestep_enabled) { 373 gen_exception(dc, EXCP_DEBUG); 374 } else { 375 if (slot >= 0) { 376 tcg_gen_goto_tb(slot); 377 tcg_gen_exit_tb(dc->base.tb, slot); 378 } else { 379 tcg_gen_exit_tb(NULL, 0); 380 } 381 } 382 dc->base.is_jmp = DISAS_NORETURN; 383 } 384 385 static void gen_jump(DisasContext *dc, TCGv dest) 386 { 387 gen_jump_slot(dc, dest, -1); 388 } 389 390 static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot) 391 { 392 TCGv_i32 tmp = tcg_const_i32(dest); 393 if (((dc->base.pc_first ^ dest) & TARGET_PAGE_MASK) != 0) { 394 slot = -1; 395 } 396 gen_jump_slot(dc, tmp, slot); 397 tcg_temp_free(tmp); 398 } 399 400 static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest, 401 int slot) 402 { 403 TCGv_i32 tcallinc = tcg_const_i32(callinc); 404 405 tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS], 406 tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN); 407 tcg_temp_free(tcallinc); 408 tcg_gen_movi_i32(cpu_R[callinc << 2], 409 (callinc << 30) | (dc->base.pc_next & 0x3fffffff)); 410 gen_jump_slot(dc, dest, slot); 411 } 412 413 static void gen_callw(DisasContext *dc, int callinc, TCGv_i32 dest) 414 { 415 gen_callw_slot(dc, callinc, dest, -1); 416 } 417 418 static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot) 419 { 420 TCGv_i32 tmp = tcg_const_i32(dest); 421 if (((dc->base.pc_first ^ dest) & TARGET_PAGE_MASK) != 0) { 422 slot = -1; 423 } 424 gen_callw_slot(dc, callinc, tmp, slot); 425 tcg_temp_free(tmp); 426 } 427 428 static bool gen_check_loop_end(DisasContext *dc, int slot) 429 { 430 if (dc->base.pc_next == dc->lend) { 431 TCGLabel *label = gen_new_label(); 432 433 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label); 434 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1); 435 if (dc->lbeg_off) { 436 gen_jumpi(dc, dc->base.pc_next - dc->lbeg_off, slot); 437 } else { 438 gen_jump(dc, cpu_SR[LBEG]); 439 } 440 gen_set_label(label); 441 gen_jumpi(dc, dc->base.pc_next, -1); 442 return true; 443 } 444 return false; 445 } 446 447 static void gen_jumpi_check_loop_end(DisasContext *dc, int slot) 448 { 449 if (!gen_check_loop_end(dc, slot)) { 450 gen_jumpi(dc, dc->base.pc_next, slot); 451 } 452 } 453 454 static void gen_brcond(DisasContext *dc, TCGCond cond, 455 TCGv_i32 t0, TCGv_i32 t1, uint32_t addr) 456 { 457 TCGLabel *label = gen_new_label(); 458 459 tcg_gen_brcond_i32(cond, t0, t1, label); 460 gen_jumpi_check_loop_end(dc, 0); 461 gen_set_label(label); 462 gen_jumpi(dc, addr, 1); 463 } 464 465 static void gen_brcondi(DisasContext *dc, TCGCond cond, 466 TCGv_i32 t0, uint32_t t1, uint32_t addr) 467 { 468 TCGv_i32 tmp = tcg_const_i32(t1); 469 gen_brcond(dc, cond, t0, tmp, addr); 470 tcg_temp_free(tmp); 471 } 472 473 static bool check_sr(DisasContext *dc, uint32_t sr, unsigned access) 474 { 475 if (!xtensa_option_bits_enabled(dc->config, sregnames[sr].opt_bits)) { 476 if (sregnames[sr].name) { 477 qemu_log_mask(LOG_GUEST_ERROR, "SR %s is not configured\n", sregnames[sr].name); 478 } else { 479 qemu_log_mask(LOG_UNIMP, "SR %d is not implemented\n", sr); 480 } 481 return false; 482 } else if (!(sregnames[sr].access & access)) { 483 static const char * const access_text[] = { 484 [SR_R] = "rsr", 485 [SR_W] = "wsr", 486 [SR_X] = "xsr", 487 }; 488 assert(access < ARRAY_SIZE(access_text) && access_text[access]); 489 qemu_log_mask(LOG_GUEST_ERROR, "SR %s is not available for %s\n", sregnames[sr].name, 490 access_text[access]); 491 return false; 492 } 493 return true; 494 } 495 496 #ifndef CONFIG_USER_ONLY 497 static void gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr) 498 { 499 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { 500 gen_io_start(); 501 } 502 gen_helper_update_ccount(cpu_env); 503 tcg_gen_mov_i32(d, cpu_SR[sr]); 504 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { 505 gen_io_end(); 506 } 507 } 508 509 static void gen_rsr_ptevaddr(DisasContext *dc, TCGv_i32 d, uint32_t sr) 510 { 511 tcg_gen_shri_i32(d, cpu_SR[EXCVADDR], 10); 512 tcg_gen_or_i32(d, d, cpu_SR[sr]); 513 tcg_gen_andi_i32(d, d, 0xfffffffc); 514 } 515 #endif 516 517 static void gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr) 518 { 519 static void (* const rsr_handler[256])(DisasContext *dc, 520 TCGv_i32 d, uint32_t sr) = { 521 #ifndef CONFIG_USER_ONLY 522 [CCOUNT] = gen_rsr_ccount, 523 [INTSET] = gen_rsr_ccount, 524 [PTEVADDR] = gen_rsr_ptevaddr, 525 #endif 526 }; 527 528 if (rsr_handler[sr]) { 529 rsr_handler[sr](dc, d, sr); 530 } else { 531 tcg_gen_mov_i32(d, cpu_SR[sr]); 532 } 533 } 534 535 static void gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s) 536 { 537 tcg_gen_andi_i32(cpu_SR[sr], s, 0x3f); 538 if (dc->sar_m32_5bit) { 539 tcg_gen_discard_i32(dc->sar_m32); 540 } 541 dc->sar_5bit = false; 542 dc->sar_m32_5bit = false; 543 } 544 545 static void gen_wsr_br(DisasContext *dc, uint32_t sr, TCGv_i32 s) 546 { 547 tcg_gen_andi_i32(cpu_SR[sr], s, 0xffff); 548 } 549 550 static void gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s) 551 { 552 tcg_gen_andi_i32(cpu_SR[sr], s, 0xfffff001); 553 } 554 555 static void gen_wsr_acchi(DisasContext *dc, uint32_t sr, TCGv_i32 s) 556 { 557 tcg_gen_ext8s_i32(cpu_SR[sr], s); 558 } 559 560 #ifndef CONFIG_USER_ONLY 561 static void gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v) 562 { 563 gen_helper_wsr_windowbase(cpu_env, v); 564 } 565 566 static void gen_wsr_windowstart(DisasContext *dc, uint32_t sr, TCGv_i32 v) 567 { 568 tcg_gen_andi_i32(cpu_SR[sr], v, (1 << dc->config->nareg / 4) - 1); 569 } 570 571 static void gen_wsr_ptevaddr(DisasContext *dc, uint32_t sr, TCGv_i32 v) 572 { 573 tcg_gen_andi_i32(cpu_SR[sr], v, 0xffc00000); 574 } 575 576 static void gen_wsr_rasid(DisasContext *dc, uint32_t sr, TCGv_i32 v) 577 { 578 gen_helper_wsr_rasid(cpu_env, v); 579 } 580 581 static void gen_wsr_tlbcfg(DisasContext *dc, uint32_t sr, TCGv_i32 v) 582 { 583 tcg_gen_andi_i32(cpu_SR[sr], v, 0x01130000); 584 } 585 586 static void gen_wsr_ibreakenable(DisasContext *dc, uint32_t sr, TCGv_i32 v) 587 { 588 gen_helper_wsr_ibreakenable(cpu_env, v); 589 } 590 591 static void gen_wsr_memctl(DisasContext *dc, uint32_t sr, TCGv_i32 v) 592 { 593 gen_helper_wsr_memctl(cpu_env, v); 594 } 595 596 static void gen_wsr_atomctl(DisasContext *dc, uint32_t sr, TCGv_i32 v) 597 { 598 tcg_gen_andi_i32(cpu_SR[sr], v, 0x3f); 599 } 600 601 static void gen_wsr_ibreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v) 602 { 603 unsigned id = sr - IBREAKA; 604 TCGv_i32 tmp = tcg_const_i32(id); 605 606 assert(id < dc->config->nibreak); 607 gen_helper_wsr_ibreaka(cpu_env, tmp, v); 608 tcg_temp_free(tmp); 609 } 610 611 static void gen_wsr_dbreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v) 612 { 613 unsigned id = sr - DBREAKA; 614 TCGv_i32 tmp = tcg_const_i32(id); 615 616 assert(id < dc->config->ndbreak); 617 gen_helper_wsr_dbreaka(cpu_env, tmp, v); 618 tcg_temp_free(tmp); 619 } 620 621 static void gen_wsr_dbreakc(DisasContext *dc, uint32_t sr, TCGv_i32 v) 622 { 623 unsigned id = sr - DBREAKC; 624 TCGv_i32 tmp = tcg_const_i32(id); 625 626 assert(id < dc->config->ndbreak); 627 gen_helper_wsr_dbreakc(cpu_env, tmp, v); 628 tcg_temp_free(tmp); 629 } 630 631 static void gen_wsr_cpenable(DisasContext *dc, uint32_t sr, TCGv_i32 v) 632 { 633 tcg_gen_andi_i32(cpu_SR[sr], v, 0xff); 634 } 635 636 static void gen_check_interrupts(DisasContext *dc) 637 { 638 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { 639 gen_io_start(); 640 } 641 gen_helper_check_interrupts(cpu_env); 642 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { 643 gen_io_end(); 644 } 645 } 646 647 static void gen_wsr_intset(DisasContext *dc, uint32_t sr, TCGv_i32 v) 648 { 649 gen_helper_intset(cpu_env, v); 650 } 651 652 static void gen_wsr_intclear(DisasContext *dc, uint32_t sr, TCGv_i32 v) 653 { 654 gen_helper_intclear(cpu_env, v); 655 } 656 657 static void gen_wsr_intenable(DisasContext *dc, uint32_t sr, TCGv_i32 v) 658 { 659 tcg_gen_mov_i32(cpu_SR[sr], v); 660 } 661 662 static void gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v) 663 { 664 uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB | 665 PS_UM | PS_EXCM | PS_INTLEVEL; 666 667 if (option_enabled(dc, XTENSA_OPTION_MMU)) { 668 mask |= PS_RING; 669 } 670 tcg_gen_andi_i32(cpu_SR[sr], v, mask); 671 } 672 673 static void gen_wsr_ccount(DisasContext *dc, uint32_t sr, TCGv_i32 v) 674 { 675 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { 676 gen_io_start(); 677 } 678 gen_helper_wsr_ccount(cpu_env, v); 679 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { 680 gen_io_end(); 681 } 682 } 683 684 static void gen_wsr_icount(DisasContext *dc, uint32_t sr, TCGv_i32 v) 685 { 686 if (dc->icount) { 687 tcg_gen_mov_i32(dc->next_icount, v); 688 } else { 689 tcg_gen_mov_i32(cpu_SR[sr], v); 690 } 691 } 692 693 static void gen_wsr_icountlevel(DisasContext *dc, uint32_t sr, TCGv_i32 v) 694 { 695 tcg_gen_andi_i32(cpu_SR[sr], v, 0xf); 696 } 697 698 static void gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v) 699 { 700 uint32_t id = sr - CCOMPARE; 701 TCGv_i32 tmp = tcg_const_i32(id); 702 703 assert(id < dc->config->nccompare); 704 tcg_gen_mov_i32(cpu_SR[sr], v); 705 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { 706 gen_io_start(); 707 } 708 gen_helper_update_ccompare(cpu_env, tmp); 709 tcg_temp_free(tmp); 710 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { 711 gen_io_end(); 712 } 713 } 714 #else 715 static void gen_check_interrupts(DisasContext *dc) 716 { 717 } 718 #endif 719 720 static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s) 721 { 722 static void (* const wsr_handler[256])(DisasContext *dc, 723 uint32_t sr, TCGv_i32 v) = { 724 [SAR] = gen_wsr_sar, 725 [BR] = gen_wsr_br, 726 [LITBASE] = gen_wsr_litbase, 727 [ACCHI] = gen_wsr_acchi, 728 #ifndef CONFIG_USER_ONLY 729 [WINDOW_BASE] = gen_wsr_windowbase, 730 [WINDOW_START] = gen_wsr_windowstart, 731 [PTEVADDR] = gen_wsr_ptevaddr, 732 [RASID] = gen_wsr_rasid, 733 [ITLBCFG] = gen_wsr_tlbcfg, 734 [DTLBCFG] = gen_wsr_tlbcfg, 735 [IBREAKENABLE] = gen_wsr_ibreakenable, 736 [MEMCTL] = gen_wsr_memctl, 737 [ATOMCTL] = gen_wsr_atomctl, 738 [IBREAKA] = gen_wsr_ibreaka, 739 [IBREAKA + 1] = gen_wsr_ibreaka, 740 [DBREAKA] = gen_wsr_dbreaka, 741 [DBREAKA + 1] = gen_wsr_dbreaka, 742 [DBREAKC] = gen_wsr_dbreakc, 743 [DBREAKC + 1] = gen_wsr_dbreakc, 744 [CPENABLE] = gen_wsr_cpenable, 745 [INTSET] = gen_wsr_intset, 746 [INTCLEAR] = gen_wsr_intclear, 747 [INTENABLE] = gen_wsr_intenable, 748 [PS] = gen_wsr_ps, 749 [CCOUNT] = gen_wsr_ccount, 750 [ICOUNT] = gen_wsr_icount, 751 [ICOUNTLEVEL] = gen_wsr_icountlevel, 752 [CCOMPARE] = gen_wsr_ccompare, 753 [CCOMPARE + 1] = gen_wsr_ccompare, 754 [CCOMPARE + 2] = gen_wsr_ccompare, 755 #endif 756 }; 757 758 if (wsr_handler[sr]) { 759 wsr_handler[sr](dc, sr, s); 760 } else { 761 tcg_gen_mov_i32(cpu_SR[sr], s); 762 } 763 } 764 765 static void gen_wur(uint32_t ur, TCGv_i32 s) 766 { 767 switch (ur) { 768 case FCR: 769 gen_helper_wur_fcr(cpu_env, s); 770 break; 771 772 case FSR: 773 tcg_gen_andi_i32(cpu_UR[ur], s, 0xffffff80); 774 break; 775 776 default: 777 tcg_gen_mov_i32(cpu_UR[ur], s); 778 break; 779 } 780 } 781 782 static void gen_load_store_alignment(DisasContext *dc, int shift, 783 TCGv_i32 addr, bool no_hw_alignment) 784 { 785 if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) { 786 tcg_gen_andi_i32(addr, addr, ~0 << shift); 787 } else if (option_enabled(dc, XTENSA_OPTION_HW_ALIGNMENT) && 788 no_hw_alignment) { 789 TCGLabel *label = gen_new_label(); 790 TCGv_i32 tmp = tcg_temp_new_i32(); 791 tcg_gen_andi_i32(tmp, addr, ~(~0 << shift)); 792 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label); 793 gen_exception_cause_vaddr(dc, LOAD_STORE_ALIGNMENT_CAUSE, addr); 794 gen_set_label(label); 795 tcg_temp_free(tmp); 796 } 797 } 798 799 #ifndef CONFIG_USER_ONLY 800 static void gen_waiti(DisasContext *dc, uint32_t imm4) 801 { 802 TCGv_i32 pc = tcg_const_i32(dc->base.pc_next); 803 TCGv_i32 intlevel = tcg_const_i32(imm4); 804 805 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { 806 gen_io_start(); 807 } 808 gen_helper_waiti(cpu_env, pc, intlevel); 809 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { 810 gen_io_end(); 811 } 812 tcg_temp_free(pc); 813 tcg_temp_free(intlevel); 814 } 815 #endif 816 817 static bool gen_window_check(DisasContext *dc, uint32_t mask) 818 { 819 unsigned r = 31 - clz32(mask); 820 821 if (r / 4 > dc->window) { 822 TCGv_i32 pc = tcg_const_i32(dc->pc); 823 TCGv_i32 w = tcg_const_i32(r / 4); 824 825 gen_helper_window_check(cpu_env, pc, w); 826 dc->base.is_jmp = DISAS_NORETURN; 827 return false; 828 } 829 return true; 830 } 831 832 static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned) 833 { 834 TCGv_i32 m = tcg_temp_new_i32(); 835 836 if (hi) { 837 (is_unsigned ? tcg_gen_shri_i32 : tcg_gen_sari_i32)(m, v, 16); 838 } else { 839 (is_unsigned ? tcg_gen_ext16u_i32 : tcg_gen_ext16s_i32)(m, v); 840 } 841 return m; 842 } 843 844 static void gen_zero_check(DisasContext *dc, const uint32_t arg[]) 845 { 846 TCGLabel *label = gen_new_label(); 847 848 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[arg[2]], 0, label); 849 gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE); 850 gen_set_label(label); 851 } 852 853 static inline unsigned xtensa_op0_insn_len(DisasContext *dc, uint8_t op0) 854 { 855 return xtensa_isa_length_from_chars(dc->config->isa, &op0); 856 } 857 858 static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) 859 { 860 xtensa_isa isa = dc->config->isa; 861 unsigned char b[MAX_INSN_LENGTH] = {cpu_ldub_code(env, dc->pc)}; 862 unsigned len = xtensa_op0_insn_len(dc, b[0]); 863 xtensa_format fmt; 864 int slot, slots; 865 unsigned i; 866 uint32_t op_flags = 0; 867 struct { 868 XtensaOpcodeOps *ops; 869 uint32_t arg[MAX_OPCODE_ARGS]; 870 uint32_t raw_arg[MAX_OPCODE_ARGS]; 871 } slot_prop[MAX_INSN_SLOTS]; 872 uint32_t debug_cause = 0; 873 uint32_t windowed_register = 0; 874 uint32_t coprocessor = 0; 875 876 if (len == XTENSA_UNDEFINED) { 877 qemu_log_mask(LOG_GUEST_ERROR, 878 "unknown instruction length (pc = %08x)\n", 879 dc->pc); 880 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); 881 return; 882 } 883 884 dc->base.pc_next = dc->pc + len; 885 for (i = 1; i < len; ++i) { 886 b[i] = cpu_ldub_code(env, dc->pc + i); 887 } 888 xtensa_insnbuf_from_chars(isa, dc->insnbuf, b, len); 889 fmt = xtensa_format_decode(isa, dc->insnbuf); 890 if (fmt == XTENSA_UNDEFINED) { 891 qemu_log_mask(LOG_GUEST_ERROR, 892 "unrecognized instruction format (pc = %08x)\n", 893 dc->pc); 894 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); 895 return; 896 } 897 slots = xtensa_format_num_slots(isa, fmt); 898 for (slot = 0; slot < slots; ++slot) { 899 xtensa_opcode opc; 900 int opnd, vopnd, opnds; 901 uint32_t *raw_arg = slot_prop[slot].raw_arg; 902 uint32_t *arg = slot_prop[slot].arg; 903 XtensaOpcodeOps *ops; 904 905 dc->raw_arg = raw_arg; 906 907 xtensa_format_get_slot(isa, fmt, slot, dc->insnbuf, dc->slotbuf); 908 opc = xtensa_opcode_decode(isa, fmt, slot, dc->slotbuf); 909 if (opc == XTENSA_UNDEFINED) { 910 qemu_log_mask(LOG_GUEST_ERROR, 911 "unrecognized opcode in slot %d (pc = %08x)\n", 912 slot, dc->pc); 913 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); 914 return; 915 } 916 opnds = xtensa_opcode_num_operands(isa, opc); 917 918 for (opnd = vopnd = 0; opnd < opnds; ++opnd) { 919 if (xtensa_operand_is_visible(isa, opc, opnd)) { 920 uint32_t v; 921 922 xtensa_operand_get_field(isa, opc, opnd, fmt, slot, 923 dc->slotbuf, &v); 924 xtensa_operand_decode(isa, opc, opnd, &v); 925 raw_arg[vopnd] = v; 926 if (xtensa_operand_is_PCrelative(isa, opc, opnd)) { 927 xtensa_operand_undo_reloc(isa, opc, opnd, &v, dc->pc); 928 } 929 arg[vopnd] = v; 930 ++vopnd; 931 } 932 } 933 ops = dc->config->opcode_ops[opc]; 934 slot_prop[slot].ops = ops; 935 936 if (ops) { 937 op_flags |= ops->op_flags; 938 } else { 939 qemu_log_mask(LOG_UNIMP, 940 "unimplemented opcode '%s' in slot %d (pc = %08x)\n", 941 xtensa_opcode_name(isa, opc), slot, dc->pc); 942 op_flags |= XTENSA_OP_ILL; 943 } 944 if ((op_flags & XTENSA_OP_ILL) || 945 (ops && ops->test_ill && ops->test_ill(dc, arg, ops->par))) { 946 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); 947 return; 948 } 949 if (ops->op_flags & XTENSA_OP_DEBUG_BREAK) { 950 debug_cause |= ops->par[0]; 951 } 952 if (ops->test_overflow) { 953 windowed_register |= ops->test_overflow(dc, arg, ops->par); 954 } 955 if (ops->windowed_register_op) { 956 uint32_t reg_opnd = ops->windowed_register_op; 957 958 while (reg_opnd) { 959 unsigned i = ctz32(reg_opnd); 960 961 windowed_register |= 1 << arg[i]; 962 reg_opnd ^= 1 << i; 963 } 964 } 965 coprocessor |= ops->coprocessor; 966 } 967 968 if ((op_flags & XTENSA_OP_PRIVILEGED) && 969 !gen_check_privilege(dc)) { 970 return; 971 } 972 973 if (op_flags & XTENSA_OP_SYSCALL) { 974 gen_exception_cause(dc, SYSCALL_CAUSE); 975 return; 976 } 977 978 if ((op_flags & XTENSA_OP_DEBUG_BREAK) && dc->debug) { 979 gen_debug_exception(dc, debug_cause); 980 return; 981 } 982 983 if (windowed_register && !gen_window_check(dc, windowed_register)) { 984 return; 985 } 986 987 if (op_flags & XTENSA_OP_UNDERFLOW) { 988 TCGv_i32 tmp = tcg_const_i32(dc->pc); 989 990 gen_helper_test_underflow_retw(cpu_env, tmp); 991 tcg_temp_free(tmp); 992 } 993 994 if (op_flags & XTENSA_OP_ALLOCA) { 995 TCGv_i32 tmp = tcg_const_i32(dc->pc); 996 997 gen_helper_movsp(cpu_env, tmp); 998 tcg_temp_free(tmp); 999 } 1000 1001 if (coprocessor && !gen_check_cpenable(dc, coprocessor)) { 1002 return; 1003 } 1004 1005 if (op_flags & XTENSA_OP_DIVIDE_BY_ZERO) { 1006 for (slot = 0; slot < slots; ++slot) { 1007 if (slot_prop[slot].ops->op_flags & XTENSA_OP_DIVIDE_BY_ZERO) { 1008 gen_zero_check(dc, slot_prop[slot].arg); 1009 } 1010 } 1011 } 1012 1013 for (slot = 0; slot < slots; ++slot) { 1014 XtensaOpcodeOps *ops = slot_prop[slot].ops; 1015 1016 dc->raw_arg = slot_prop[slot].raw_arg; 1017 ops->translate(dc, slot_prop[slot].arg, ops->par); 1018 } 1019 1020 if (dc->base.is_jmp == DISAS_NEXT) { 1021 if (op_flags & XTENSA_OP_CHECK_INTERRUPTS) { 1022 gen_check_interrupts(dc); 1023 } 1024 1025 if (op_flags & XTENSA_OP_EXIT_TB_M1) { 1026 /* Change in mmu index, memory mapping or tb->flags; exit tb */ 1027 gen_jumpi_check_loop_end(dc, -1); 1028 } else if (op_flags & XTENSA_OP_EXIT_TB_0) { 1029 gen_jumpi_check_loop_end(dc, 0); 1030 } 1031 } 1032 1033 if (dc->base.is_jmp == DISAS_NEXT) { 1034 gen_check_loop_end(dc, 0); 1035 } 1036 dc->pc = dc->base.pc_next; 1037 } 1038 1039 static inline unsigned xtensa_insn_len(CPUXtensaState *env, DisasContext *dc) 1040 { 1041 uint8_t b0 = cpu_ldub_code(env, dc->pc); 1042 return xtensa_op0_insn_len(dc, b0); 1043 } 1044 1045 static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc) 1046 { 1047 unsigned i; 1048 1049 for (i = 0; i < dc->config->nibreak; ++i) { 1050 if ((env->sregs[IBREAKENABLE] & (1 << i)) && 1051 env->sregs[IBREAKA + i] == dc->pc) { 1052 gen_debug_exception(dc, DEBUGCAUSE_IB); 1053 break; 1054 } 1055 } 1056 } 1057 1058 static void xtensa_tr_init_disas_context(DisasContextBase *dcbase, 1059 CPUState *cpu) 1060 { 1061 DisasContext *dc = container_of(dcbase, DisasContext, base); 1062 CPUXtensaState *env = cpu->env_ptr; 1063 uint32_t tb_flags = dc->base.tb->flags; 1064 1065 dc->config = env->config; 1066 dc->pc = dc->base.pc_first; 1067 dc->ring = tb_flags & XTENSA_TBFLAG_RING_MASK; 1068 dc->cring = (tb_flags & XTENSA_TBFLAG_EXCM) ? 0 : dc->ring; 1069 dc->lbeg_off = (dc->base.tb->cs_base & XTENSA_CSBASE_LBEG_OFF_MASK) >> 1070 XTENSA_CSBASE_LBEG_OFF_SHIFT; 1071 dc->lend = (dc->base.tb->cs_base & XTENSA_CSBASE_LEND_MASK) + 1072 (dc->base.pc_first & TARGET_PAGE_MASK); 1073 dc->debug = tb_flags & XTENSA_TBFLAG_DEBUG; 1074 dc->icount = tb_flags & XTENSA_TBFLAG_ICOUNT; 1075 dc->cpenable = (tb_flags & XTENSA_TBFLAG_CPENABLE_MASK) >> 1076 XTENSA_TBFLAG_CPENABLE_SHIFT; 1077 dc->window = ((tb_flags & XTENSA_TBFLAG_WINDOW_MASK) >> 1078 XTENSA_TBFLAG_WINDOW_SHIFT); 1079 dc->cwoe = tb_flags & XTENSA_TBFLAG_CWOE; 1080 dc->callinc = ((tb_flags & XTENSA_TBFLAG_CALLINC_MASK) >> 1081 XTENSA_TBFLAG_CALLINC_SHIFT); 1082 1083 if (dc->config->isa) { 1084 dc->insnbuf = xtensa_insnbuf_alloc(dc->config->isa); 1085 dc->slotbuf = xtensa_insnbuf_alloc(dc->config->isa); 1086 } 1087 init_sar_tracker(dc); 1088 } 1089 1090 static void xtensa_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu) 1091 { 1092 DisasContext *dc = container_of(dcbase, DisasContext, base); 1093 1094 if (dc->icount) { 1095 dc->next_icount = tcg_temp_local_new_i32(); 1096 } 1097 } 1098 1099 static void xtensa_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 1100 { 1101 tcg_gen_insn_start(dcbase->pc_next); 1102 } 1103 1104 static bool xtensa_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, 1105 const CPUBreakpoint *bp) 1106 { 1107 DisasContext *dc = container_of(dcbase, DisasContext, base); 1108 1109 tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); 1110 gen_exception(dc, EXCP_DEBUG); 1111 dc->base.is_jmp = DISAS_NORETURN; 1112 /* The address covered by the breakpoint must be included in 1113 [tb->pc, tb->pc + tb->size) in order to for it to be 1114 properly cleared -- thus we increment the PC here so that 1115 the logic setting tb->size below does the right thing. */ 1116 dc->base.pc_next += 2; 1117 return true; 1118 } 1119 1120 static void xtensa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 1121 { 1122 DisasContext *dc = container_of(dcbase, DisasContext, base); 1123 CPUXtensaState *env = cpu->env_ptr; 1124 target_ulong page_start; 1125 1126 /* These two conditions only apply to the first insn in the TB, 1127 but this is the first TranslateOps hook that allows exiting. */ 1128 if ((tb_cflags(dc->base.tb) & CF_USE_ICOUNT) 1129 && (dc->base.tb->flags & XTENSA_TBFLAG_YIELD)) { 1130 gen_exception(dc, EXCP_YIELD); 1131 dc->base.is_jmp = DISAS_NORETURN; 1132 return; 1133 } 1134 if (dc->base.tb->flags & XTENSA_TBFLAG_EXCEPTION) { 1135 gen_exception(dc, EXCP_DEBUG); 1136 dc->base.is_jmp = DISAS_NORETURN; 1137 return; 1138 } 1139 1140 if (dc->icount) { 1141 TCGLabel *label = gen_new_label(); 1142 1143 tcg_gen_addi_i32(dc->next_icount, cpu_SR[ICOUNT], 1); 1144 tcg_gen_brcondi_i32(TCG_COND_NE, dc->next_icount, 0, label); 1145 tcg_gen_mov_i32(dc->next_icount, cpu_SR[ICOUNT]); 1146 if (dc->debug) { 1147 gen_debug_exception(dc, DEBUGCAUSE_IC); 1148 } 1149 gen_set_label(label); 1150 } 1151 1152 if (dc->debug) { 1153 gen_ibreak_check(env, dc); 1154 } 1155 1156 disas_xtensa_insn(env, dc); 1157 1158 if (dc->icount) { 1159 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount); 1160 } 1161 1162 /* End the TB if the next insn will cross into the next page. */ 1163 page_start = dc->base.pc_first & TARGET_PAGE_MASK; 1164 if (dc->base.is_jmp == DISAS_NEXT && 1165 (dc->pc - page_start >= TARGET_PAGE_SIZE || 1166 dc->pc - page_start + xtensa_insn_len(env, dc) > TARGET_PAGE_SIZE)) { 1167 dc->base.is_jmp = DISAS_TOO_MANY; 1168 } 1169 } 1170 1171 static void xtensa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 1172 { 1173 DisasContext *dc = container_of(dcbase, DisasContext, base); 1174 1175 reset_sar_tracker(dc); 1176 if (dc->config->isa) { 1177 xtensa_insnbuf_free(dc->config->isa, dc->insnbuf); 1178 xtensa_insnbuf_free(dc->config->isa, dc->slotbuf); 1179 } 1180 if (dc->icount) { 1181 tcg_temp_free(dc->next_icount); 1182 } 1183 1184 switch (dc->base.is_jmp) { 1185 case DISAS_NORETURN: 1186 break; 1187 case DISAS_TOO_MANY: 1188 if (dc->base.singlestep_enabled) { 1189 tcg_gen_movi_i32(cpu_pc, dc->pc); 1190 gen_exception(dc, EXCP_DEBUG); 1191 } else { 1192 gen_jumpi(dc, dc->pc, 0); 1193 } 1194 break; 1195 default: 1196 g_assert_not_reached(); 1197 } 1198 } 1199 1200 static void xtensa_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) 1201 { 1202 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 1203 log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); 1204 } 1205 1206 static const TranslatorOps xtensa_translator_ops = { 1207 .init_disas_context = xtensa_tr_init_disas_context, 1208 .tb_start = xtensa_tr_tb_start, 1209 .insn_start = xtensa_tr_insn_start, 1210 .breakpoint_check = xtensa_tr_breakpoint_check, 1211 .translate_insn = xtensa_tr_translate_insn, 1212 .tb_stop = xtensa_tr_tb_stop, 1213 .disas_log = xtensa_tr_disas_log, 1214 }; 1215 1216 void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) 1217 { 1218 DisasContext dc = {}; 1219 translator_loop(&xtensa_translator_ops, &dc.base, cpu, tb); 1220 } 1221 1222 void xtensa_cpu_dump_state(CPUState *cs, FILE *f, 1223 fprintf_function cpu_fprintf, int flags) 1224 { 1225 XtensaCPU *cpu = XTENSA_CPU(cs); 1226 CPUXtensaState *env = &cpu->env; 1227 int i, j; 1228 1229 cpu_fprintf(f, "PC=%08x\n\n", env->pc); 1230 1231 for (i = j = 0; i < 256; ++i) { 1232 if (xtensa_option_bits_enabled(env->config, sregnames[i].opt_bits)) { 1233 cpu_fprintf(f, "%12s=%08x%c", sregnames[i].name, env->sregs[i], 1234 (j++ % 4) == 3 ? '\n' : ' '); 1235 } 1236 } 1237 1238 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n"); 1239 1240 for (i = j = 0; i < 256; ++i) { 1241 if (xtensa_option_bits_enabled(env->config, uregnames[i].opt_bits)) { 1242 cpu_fprintf(f, "%s=%08x%c", uregnames[i].name, env->uregs[i], 1243 (j++ % 4) == 3 ? '\n' : ' '); 1244 } 1245 } 1246 1247 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n"); 1248 1249 for (i = 0; i < 16; ++i) { 1250 cpu_fprintf(f, " A%02d=%08x%c", i, env->regs[i], 1251 (i % 4) == 3 ? '\n' : ' '); 1252 } 1253 1254 xtensa_sync_phys_from_window(env); 1255 cpu_fprintf(f, "\n"); 1256 1257 for (i = 0; i < env->config->nareg; ++i) { 1258 cpu_fprintf(f, "AR%02d=%08x ", i, env->phys_regs[i]); 1259 if (i % 4 == 3) { 1260 bool ws = (env->sregs[WINDOW_START] & (1 << (i / 4))) != 0; 1261 bool cw = env->sregs[WINDOW_BASE] == i / 4; 1262 1263 cpu_fprintf(f, "%c%c\n", ws ? '<' : ' ', cw ? '=' : ' '); 1264 } 1265 } 1266 1267 if ((flags & CPU_DUMP_FPU) && 1268 xtensa_option_enabled(env->config, XTENSA_OPTION_FP_COPROCESSOR)) { 1269 cpu_fprintf(f, "\n"); 1270 1271 for (i = 0; i < 16; ++i) { 1272 cpu_fprintf(f, "F%02d=%08x (%+10.8e)%c", i, 1273 float32_val(env->fregs[i].f32[FP_F32_LOW]), 1274 *(float *)(env->fregs[i].f32 + FP_F32_LOW), 1275 (i % 2) == 1 ? '\n' : ' '); 1276 } 1277 } 1278 } 1279 1280 void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb, 1281 target_ulong *data) 1282 { 1283 env->pc = data[0]; 1284 } 1285 1286 static int compare_opcode_ops(const void *a, const void *b) 1287 { 1288 return strcmp((const char *)a, 1289 ((const XtensaOpcodeOps *)b)->name); 1290 } 1291 1292 XtensaOpcodeOps * 1293 xtensa_find_opcode_ops(const XtensaOpcodeTranslators *t, 1294 const char *name) 1295 { 1296 return bsearch(name, t->opcode, t->num_opcodes, 1297 sizeof(XtensaOpcodeOps), compare_opcode_ops); 1298 } 1299 1300 static void translate_abs(DisasContext *dc, const uint32_t arg[], 1301 const uint32_t par[]) 1302 { 1303 TCGv_i32 zero = tcg_const_i32(0); 1304 TCGv_i32 neg = tcg_temp_new_i32(); 1305 1306 tcg_gen_neg_i32(neg, cpu_R[arg[1]]); 1307 tcg_gen_movcond_i32(TCG_COND_GE, cpu_R[arg[0]], 1308 cpu_R[arg[1]], zero, cpu_R[arg[1]], neg); 1309 tcg_temp_free(neg); 1310 tcg_temp_free(zero); 1311 } 1312 1313 static void translate_add(DisasContext *dc, const uint32_t arg[], 1314 const uint32_t par[]) 1315 { 1316 tcg_gen_add_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); 1317 } 1318 1319 static void translate_addi(DisasContext *dc, const uint32_t arg[], 1320 const uint32_t par[]) 1321 { 1322 tcg_gen_addi_i32(cpu_R[arg[0]], cpu_R[arg[1]], arg[2]); 1323 } 1324 1325 static void translate_addx(DisasContext *dc, const uint32_t arg[], 1326 const uint32_t par[]) 1327 { 1328 TCGv_i32 tmp = tcg_temp_new_i32(); 1329 tcg_gen_shli_i32(tmp, cpu_R[arg[1]], par[0]); 1330 tcg_gen_add_i32(cpu_R[arg[0]], tmp, cpu_R[arg[2]]); 1331 tcg_temp_free(tmp); 1332 } 1333 1334 static void translate_all(DisasContext *dc, const uint32_t arg[], 1335 const uint32_t par[]) 1336 { 1337 uint32_t shift = par[1]; 1338 TCGv_i32 mask = tcg_const_i32(((1 << shift) - 1) << arg[1]); 1339 TCGv_i32 tmp = tcg_temp_new_i32(); 1340 1341 tcg_gen_and_i32(tmp, cpu_SR[BR], mask); 1342 if (par[0]) { 1343 tcg_gen_addi_i32(tmp, tmp, 1 << arg[1]); 1344 } else { 1345 tcg_gen_add_i32(tmp, tmp, mask); 1346 } 1347 tcg_gen_shri_i32(tmp, tmp, arg[1] + shift); 1348 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], 1349 tmp, arg[0], 1); 1350 tcg_temp_free(mask); 1351 tcg_temp_free(tmp); 1352 } 1353 1354 static void translate_and(DisasContext *dc, const uint32_t arg[], 1355 const uint32_t par[]) 1356 { 1357 tcg_gen_and_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); 1358 } 1359 1360 static void translate_ball(DisasContext *dc, const uint32_t arg[], 1361 const uint32_t par[]) 1362 { 1363 TCGv_i32 tmp = tcg_temp_new_i32(); 1364 tcg_gen_and_i32(tmp, cpu_R[arg[0]], cpu_R[arg[1]]); 1365 gen_brcond(dc, par[0], tmp, cpu_R[arg[1]], arg[2]); 1366 tcg_temp_free(tmp); 1367 } 1368 1369 static void translate_bany(DisasContext *dc, const uint32_t arg[], 1370 const uint32_t par[]) 1371 { 1372 TCGv_i32 tmp = tcg_temp_new_i32(); 1373 tcg_gen_and_i32(tmp, cpu_R[arg[0]], cpu_R[arg[1]]); 1374 gen_brcondi(dc, par[0], tmp, 0, arg[2]); 1375 tcg_temp_free(tmp); 1376 } 1377 1378 static void translate_b(DisasContext *dc, const uint32_t arg[], 1379 const uint32_t par[]) 1380 { 1381 gen_brcond(dc, par[0], cpu_R[arg[0]], cpu_R[arg[1]], arg[2]); 1382 } 1383 1384 static void translate_bb(DisasContext *dc, const uint32_t arg[], 1385 const uint32_t par[]) 1386 { 1387 #ifdef TARGET_WORDS_BIGENDIAN 1388 TCGv_i32 bit = tcg_const_i32(0x80000000u); 1389 #else 1390 TCGv_i32 bit = tcg_const_i32(0x00000001u); 1391 #endif 1392 TCGv_i32 tmp = tcg_temp_new_i32(); 1393 tcg_gen_andi_i32(tmp, cpu_R[arg[1]], 0x1f); 1394 #ifdef TARGET_WORDS_BIGENDIAN 1395 tcg_gen_shr_i32(bit, bit, tmp); 1396 #else 1397 tcg_gen_shl_i32(bit, bit, tmp); 1398 #endif 1399 tcg_gen_and_i32(tmp, cpu_R[arg[0]], bit); 1400 gen_brcondi(dc, par[0], tmp, 0, arg[2]); 1401 tcg_temp_free(tmp); 1402 tcg_temp_free(bit); 1403 } 1404 1405 static void translate_bbi(DisasContext *dc, const uint32_t arg[], 1406 const uint32_t par[]) 1407 { 1408 TCGv_i32 tmp = tcg_temp_new_i32(); 1409 #ifdef TARGET_WORDS_BIGENDIAN 1410 tcg_gen_andi_i32(tmp, cpu_R[arg[0]], 0x80000000u >> arg[1]); 1411 #else 1412 tcg_gen_andi_i32(tmp, cpu_R[arg[0]], 0x00000001u << arg[1]); 1413 #endif 1414 gen_brcondi(dc, par[0], tmp, 0, arg[2]); 1415 tcg_temp_free(tmp); 1416 } 1417 1418 static void translate_bi(DisasContext *dc, const uint32_t arg[], 1419 const uint32_t par[]) 1420 { 1421 gen_brcondi(dc, par[0], cpu_R[arg[0]], arg[1], arg[2]); 1422 } 1423 1424 static void translate_bz(DisasContext *dc, const uint32_t arg[], 1425 const uint32_t par[]) 1426 { 1427 gen_brcondi(dc, par[0], cpu_R[arg[0]], 0, arg[1]); 1428 } 1429 1430 enum { 1431 BOOLEAN_AND, 1432 BOOLEAN_ANDC, 1433 BOOLEAN_OR, 1434 BOOLEAN_ORC, 1435 BOOLEAN_XOR, 1436 }; 1437 1438 static void translate_boolean(DisasContext *dc, const uint32_t arg[], 1439 const uint32_t par[]) 1440 { 1441 static void (* const op[])(TCGv_i32, TCGv_i32, TCGv_i32) = { 1442 [BOOLEAN_AND] = tcg_gen_and_i32, 1443 [BOOLEAN_ANDC] = tcg_gen_andc_i32, 1444 [BOOLEAN_OR] = tcg_gen_or_i32, 1445 [BOOLEAN_ORC] = tcg_gen_orc_i32, 1446 [BOOLEAN_XOR] = tcg_gen_xor_i32, 1447 }; 1448 1449 TCGv_i32 tmp1 = tcg_temp_new_i32(); 1450 TCGv_i32 tmp2 = tcg_temp_new_i32(); 1451 1452 tcg_gen_shri_i32(tmp1, cpu_SR[BR], arg[1]); 1453 tcg_gen_shri_i32(tmp2, cpu_SR[BR], arg[2]); 1454 op[par[0]](tmp1, tmp1, tmp2); 1455 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, arg[0], 1); 1456 tcg_temp_free(tmp1); 1457 tcg_temp_free(tmp2); 1458 } 1459 1460 static void translate_bp(DisasContext *dc, const uint32_t arg[], 1461 const uint32_t par[]) 1462 { 1463 TCGv_i32 tmp = tcg_temp_new_i32(); 1464 1465 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << arg[0]); 1466 gen_brcondi(dc, par[0], tmp, 0, arg[1]); 1467 tcg_temp_free(tmp); 1468 } 1469 1470 static void translate_call0(DisasContext *dc, const uint32_t arg[], 1471 const uint32_t par[]) 1472 { 1473 tcg_gen_movi_i32(cpu_R[0], dc->base.pc_next); 1474 gen_jumpi(dc, arg[0], 0); 1475 } 1476 1477 static uint32_t test_overflow_callw(DisasContext *dc, const uint32_t arg[], 1478 const uint32_t par[]) 1479 { 1480 return 1 << (par[0] * 4); 1481 } 1482 1483 static void translate_callw(DisasContext *dc, const uint32_t arg[], 1484 const uint32_t par[]) 1485 { 1486 gen_callwi(dc, par[0], arg[0], 0); 1487 } 1488 1489 static void translate_callx0(DisasContext *dc, const uint32_t arg[], 1490 const uint32_t par[]) 1491 { 1492 TCGv_i32 tmp = tcg_temp_new_i32(); 1493 tcg_gen_mov_i32(tmp, cpu_R[arg[0]]); 1494 tcg_gen_movi_i32(cpu_R[0], dc->base.pc_next); 1495 gen_jump(dc, tmp); 1496 tcg_temp_free(tmp); 1497 } 1498 1499 static void translate_callxw(DisasContext *dc, const uint32_t arg[], 1500 const uint32_t par[]) 1501 { 1502 TCGv_i32 tmp = tcg_temp_new_i32(); 1503 1504 tcg_gen_mov_i32(tmp, cpu_R[arg[0]]); 1505 gen_callw(dc, par[0], tmp); 1506 tcg_temp_free(tmp); 1507 } 1508 1509 static void translate_clamps(DisasContext *dc, const uint32_t arg[], 1510 const uint32_t par[]) 1511 { 1512 TCGv_i32 tmp1 = tcg_const_i32(-1u << arg[2]); 1513 TCGv_i32 tmp2 = tcg_const_i32((1 << arg[2]) - 1); 1514 1515 tcg_gen_smax_i32(tmp1, tmp1, cpu_R[arg[1]]); 1516 tcg_gen_smin_i32(cpu_R[arg[0]], tmp1, tmp2); 1517 tcg_temp_free(tmp1); 1518 tcg_temp_free(tmp2); 1519 } 1520 1521 static void translate_clrb_expstate(DisasContext *dc, const uint32_t arg[], 1522 const uint32_t par[]) 1523 { 1524 /* TODO: GPIO32 may be a part of coprocessor */ 1525 tcg_gen_andi_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], ~(1u << arg[0])); 1526 } 1527 1528 static void translate_const16(DisasContext *dc, const uint32_t arg[], 1529 const uint32_t par[]) 1530 { 1531 TCGv_i32 c = tcg_const_i32(arg[1]); 1532 1533 tcg_gen_deposit_i32(cpu_R[arg[0]], c, cpu_R[arg[0]], 16, 16); 1534 tcg_temp_free(c); 1535 } 1536 1537 static void translate_dcache(DisasContext *dc, const uint32_t arg[], 1538 const uint32_t par[]) 1539 { 1540 TCGv_i32 addr = tcg_temp_new_i32(); 1541 TCGv_i32 res = tcg_temp_new_i32(); 1542 1543 tcg_gen_addi_i32(addr, cpu_R[arg[0]], arg[1]); 1544 tcg_gen_qemu_ld8u(res, addr, dc->cring); 1545 tcg_temp_free(addr); 1546 tcg_temp_free(res); 1547 } 1548 1549 static void translate_depbits(DisasContext *dc, const uint32_t arg[], 1550 const uint32_t par[]) 1551 { 1552 tcg_gen_deposit_i32(cpu_R[arg[1]], cpu_R[arg[1]], cpu_R[arg[0]], 1553 arg[2], arg[3]); 1554 } 1555 1556 static bool test_ill_entry(DisasContext *dc, const uint32_t arg[], 1557 const uint32_t par[]) 1558 { 1559 if (arg[0] > 3 || !dc->cwoe) { 1560 qemu_log_mask(LOG_GUEST_ERROR, 1561 "Illegal entry instruction(pc = %08x)\n", dc->pc); 1562 return true; 1563 } else { 1564 return false; 1565 } 1566 } 1567 1568 static uint32_t test_overflow_entry(DisasContext *dc, const uint32_t arg[], 1569 const uint32_t par[]) 1570 { 1571 return 1 << (dc->callinc * 4); 1572 } 1573 1574 static void translate_entry(DisasContext *dc, const uint32_t arg[], 1575 const uint32_t par[]) 1576 { 1577 TCGv_i32 pc = tcg_const_i32(dc->pc); 1578 TCGv_i32 s = tcg_const_i32(arg[0]); 1579 TCGv_i32 imm = tcg_const_i32(arg[1]); 1580 gen_helper_entry(cpu_env, pc, s, imm); 1581 tcg_temp_free(imm); 1582 tcg_temp_free(s); 1583 tcg_temp_free(pc); 1584 } 1585 1586 static void translate_extui(DisasContext *dc, const uint32_t arg[], 1587 const uint32_t par[]) 1588 { 1589 int maskimm = (1 << arg[3]) - 1; 1590 1591 TCGv_i32 tmp = tcg_temp_new_i32(); 1592 tcg_gen_shri_i32(tmp, cpu_R[arg[1]], arg[2]); 1593 tcg_gen_andi_i32(cpu_R[arg[0]], tmp, maskimm); 1594 tcg_temp_free(tmp); 1595 } 1596 1597 static void translate_icache(DisasContext *dc, const uint32_t arg[], 1598 const uint32_t par[]) 1599 { 1600 #ifndef CONFIG_USER_ONLY 1601 TCGv_i32 addr = tcg_temp_new_i32(); 1602 1603 tcg_gen_movi_i32(cpu_pc, dc->pc); 1604 tcg_gen_addi_i32(addr, cpu_R[arg[0]], arg[1]); 1605 gen_helper_itlb_hit_test(cpu_env, addr); 1606 tcg_temp_free(addr); 1607 #endif 1608 } 1609 1610 static void translate_itlb(DisasContext *dc, const uint32_t arg[], 1611 const uint32_t par[]) 1612 { 1613 #ifndef CONFIG_USER_ONLY 1614 TCGv_i32 dtlb = tcg_const_i32(par[0]); 1615 1616 gen_helper_itlb(cpu_env, cpu_R[arg[0]], dtlb); 1617 tcg_temp_free(dtlb); 1618 #endif 1619 } 1620 1621 static void translate_j(DisasContext *dc, const uint32_t arg[], 1622 const uint32_t par[]) 1623 { 1624 gen_jumpi(dc, arg[0], 0); 1625 } 1626 1627 static void translate_jx(DisasContext *dc, const uint32_t arg[], 1628 const uint32_t par[]) 1629 { 1630 gen_jump(dc, cpu_R[arg[0]]); 1631 } 1632 1633 static void translate_l32e(DisasContext *dc, const uint32_t arg[], 1634 const uint32_t par[]) 1635 { 1636 TCGv_i32 addr = tcg_temp_new_i32(); 1637 1638 tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]); 1639 gen_load_store_alignment(dc, 2, addr, false); 1640 tcg_gen_qemu_ld_tl(cpu_R[arg[0]], addr, dc->ring, MO_TEUL); 1641 tcg_temp_free(addr); 1642 } 1643 1644 static void translate_ldst(DisasContext *dc, const uint32_t arg[], 1645 const uint32_t par[]) 1646 { 1647 TCGv_i32 addr = tcg_temp_new_i32(); 1648 1649 tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]); 1650 if (par[0] & MO_SIZE) { 1651 gen_load_store_alignment(dc, par[0] & MO_SIZE, addr, par[1]); 1652 } 1653 if (par[2]) { 1654 if (par[1]) { 1655 tcg_gen_mb(TCG_BAR_STRL | TCG_MO_ALL); 1656 } 1657 tcg_gen_qemu_st_tl(cpu_R[arg[0]], addr, dc->cring, par[0]); 1658 } else { 1659 tcg_gen_qemu_ld_tl(cpu_R[arg[0]], addr, dc->cring, par[0]); 1660 if (par[1]) { 1661 tcg_gen_mb(TCG_BAR_LDAQ | TCG_MO_ALL); 1662 } 1663 } 1664 tcg_temp_free(addr); 1665 } 1666 1667 static void translate_l32r(DisasContext *dc, const uint32_t arg[], 1668 const uint32_t par[]) 1669 { 1670 TCGv_i32 tmp; 1671 1672 if (dc->base.tb->flags & XTENSA_TBFLAG_LITBASE) { 1673 tmp = tcg_const_i32(dc->raw_arg[1] - 1); 1674 tcg_gen_add_i32(tmp, cpu_SR[LITBASE], tmp); 1675 } else { 1676 tmp = tcg_const_i32(arg[1]); 1677 } 1678 tcg_gen_qemu_ld32u(cpu_R[arg[0]], tmp, dc->cring); 1679 tcg_temp_free(tmp); 1680 } 1681 1682 static void translate_loop(DisasContext *dc, const uint32_t arg[], 1683 const uint32_t par[]) 1684 { 1685 uint32_t lend = arg[1]; 1686 1687 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[arg[0]], 1); 1688 tcg_gen_movi_i32(cpu_SR[LBEG], dc->base.pc_next); 1689 tcg_gen_movi_i32(cpu_SR[LEND], lend); 1690 1691 if (par[0] != TCG_COND_NEVER) { 1692 TCGLabel *label = gen_new_label(); 1693 tcg_gen_brcondi_i32(par[0], cpu_R[arg[0]], 0, label); 1694 gen_jumpi(dc, lend, 1); 1695 gen_set_label(label); 1696 } 1697 1698 gen_jumpi(dc, dc->base.pc_next, 0); 1699 } 1700 1701 enum { 1702 MAC16_UMUL, 1703 MAC16_MUL, 1704 MAC16_MULA, 1705 MAC16_MULS, 1706 MAC16_NONE, 1707 }; 1708 1709 enum { 1710 MAC16_LL, 1711 MAC16_HL, 1712 MAC16_LH, 1713 MAC16_HH, 1714 1715 MAC16_HX = 0x1, 1716 MAC16_XH = 0x2, 1717 }; 1718 1719 enum { 1720 MAC16_AA, 1721 MAC16_AD, 1722 MAC16_DA, 1723 MAC16_DD, 1724 1725 MAC16_XD = 0x1, 1726 MAC16_DX = 0x2, 1727 }; 1728 1729 static void translate_mac16(DisasContext *dc, const uint32_t arg[], 1730 const uint32_t par[]) 1731 { 1732 int op = par[0]; 1733 bool is_m1_sr = par[1] & MAC16_DX; 1734 bool is_m2_sr = par[1] & MAC16_XD; 1735 unsigned half = par[2]; 1736 uint32_t ld_offset = par[3]; 1737 unsigned off = ld_offset ? 2 : 0; 1738 TCGv_i32 vaddr = tcg_temp_new_i32(); 1739 TCGv_i32 mem32 = tcg_temp_new_i32(); 1740 1741 if (ld_offset) { 1742 tcg_gen_addi_i32(vaddr, cpu_R[arg[1]], ld_offset); 1743 gen_load_store_alignment(dc, 2, vaddr, false); 1744 tcg_gen_qemu_ld32u(mem32, vaddr, dc->cring); 1745 } 1746 if (op != MAC16_NONE) { 1747 TCGv_i32 m1 = gen_mac16_m(is_m1_sr ? 1748 cpu_SR[MR + arg[off]] : 1749 cpu_R[arg[off]], 1750 half & MAC16_HX, op == MAC16_UMUL); 1751 TCGv_i32 m2 = gen_mac16_m(is_m2_sr ? 1752 cpu_SR[MR + arg[off + 1]] : 1753 cpu_R[arg[off + 1]], 1754 half & MAC16_XH, op == MAC16_UMUL); 1755 1756 if (op == MAC16_MUL || op == MAC16_UMUL) { 1757 tcg_gen_mul_i32(cpu_SR[ACCLO], m1, m2); 1758 if (op == MAC16_UMUL) { 1759 tcg_gen_movi_i32(cpu_SR[ACCHI], 0); 1760 } else { 1761 tcg_gen_sari_i32(cpu_SR[ACCHI], cpu_SR[ACCLO], 31); 1762 } 1763 } else { 1764 TCGv_i32 lo = tcg_temp_new_i32(); 1765 TCGv_i32 hi = tcg_temp_new_i32(); 1766 1767 tcg_gen_mul_i32(lo, m1, m2); 1768 tcg_gen_sari_i32(hi, lo, 31); 1769 if (op == MAC16_MULA) { 1770 tcg_gen_add2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI], 1771 cpu_SR[ACCLO], cpu_SR[ACCHI], 1772 lo, hi); 1773 } else { 1774 tcg_gen_sub2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI], 1775 cpu_SR[ACCLO], cpu_SR[ACCHI], 1776 lo, hi); 1777 } 1778 tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]); 1779 1780 tcg_temp_free_i32(lo); 1781 tcg_temp_free_i32(hi); 1782 } 1783 tcg_temp_free(m1); 1784 tcg_temp_free(m2); 1785 } 1786 if (ld_offset) { 1787 tcg_gen_mov_i32(cpu_R[arg[1]], vaddr); 1788 tcg_gen_mov_i32(cpu_SR[MR + arg[0]], mem32); 1789 } 1790 tcg_temp_free(vaddr); 1791 tcg_temp_free(mem32); 1792 } 1793 1794 static void translate_memw(DisasContext *dc, const uint32_t arg[], 1795 const uint32_t par[]) 1796 { 1797 tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); 1798 } 1799 1800 static void translate_smin(DisasContext *dc, const uint32_t arg[], 1801 const uint32_t par[]) 1802 { 1803 tcg_gen_smin_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); 1804 } 1805 1806 static void translate_umin(DisasContext *dc, const uint32_t arg[], 1807 const uint32_t par[]) 1808 { 1809 tcg_gen_umin_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); 1810 } 1811 1812 static void translate_smax(DisasContext *dc, const uint32_t arg[], 1813 const uint32_t par[]) 1814 { 1815 tcg_gen_smax_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); 1816 } 1817 1818 static void translate_umax(DisasContext *dc, const uint32_t arg[], 1819 const uint32_t par[]) 1820 { 1821 tcg_gen_umax_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); 1822 } 1823 1824 static void translate_mov(DisasContext *dc, const uint32_t arg[], 1825 const uint32_t par[]) 1826 { 1827 tcg_gen_mov_i32(cpu_R[arg[0]], cpu_R[arg[1]]); 1828 } 1829 1830 static void translate_movcond(DisasContext *dc, const uint32_t arg[], 1831 const uint32_t par[]) 1832 { 1833 TCGv_i32 zero = tcg_const_i32(0); 1834 1835 tcg_gen_movcond_i32(par[0], cpu_R[arg[0]], 1836 cpu_R[arg[2]], zero, cpu_R[arg[1]], cpu_R[arg[0]]); 1837 tcg_temp_free(zero); 1838 } 1839 1840 static void translate_movi(DisasContext *dc, const uint32_t arg[], 1841 const uint32_t par[]) 1842 { 1843 tcg_gen_movi_i32(cpu_R[arg[0]], arg[1]); 1844 } 1845 1846 static void translate_movp(DisasContext *dc, const uint32_t arg[], 1847 const uint32_t par[]) 1848 { 1849 TCGv_i32 zero = tcg_const_i32(0); 1850 TCGv_i32 tmp = tcg_temp_new_i32(); 1851 1852 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << arg[2]); 1853 tcg_gen_movcond_i32(par[0], 1854 cpu_R[arg[0]], tmp, zero, 1855 cpu_R[arg[1]], cpu_R[arg[0]]); 1856 tcg_temp_free(tmp); 1857 tcg_temp_free(zero); 1858 } 1859 1860 static void translate_movsp(DisasContext *dc, const uint32_t arg[], 1861 const uint32_t par[]) 1862 { 1863 tcg_gen_mov_i32(cpu_R[arg[0]], cpu_R[arg[1]]); 1864 } 1865 1866 static void translate_mul16(DisasContext *dc, const uint32_t arg[], 1867 const uint32_t par[]) 1868 { 1869 TCGv_i32 v1 = tcg_temp_new_i32(); 1870 TCGv_i32 v2 = tcg_temp_new_i32(); 1871 1872 if (par[0]) { 1873 tcg_gen_ext16s_i32(v1, cpu_R[arg[1]]); 1874 tcg_gen_ext16s_i32(v2, cpu_R[arg[2]]); 1875 } else { 1876 tcg_gen_ext16u_i32(v1, cpu_R[arg[1]]); 1877 tcg_gen_ext16u_i32(v2, cpu_R[arg[2]]); 1878 } 1879 tcg_gen_mul_i32(cpu_R[arg[0]], v1, v2); 1880 tcg_temp_free(v2); 1881 tcg_temp_free(v1); 1882 } 1883 1884 static void translate_mull(DisasContext *dc, const uint32_t arg[], 1885 const uint32_t par[]) 1886 { 1887 tcg_gen_mul_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); 1888 } 1889 1890 static void translate_mulh(DisasContext *dc, const uint32_t arg[], 1891 const uint32_t par[]) 1892 { 1893 TCGv_i32 lo = tcg_temp_new(); 1894 1895 if (par[0]) { 1896 tcg_gen_muls2_i32(lo, cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); 1897 } else { 1898 tcg_gen_mulu2_i32(lo, cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); 1899 } 1900 tcg_temp_free(lo); 1901 } 1902 1903 static void translate_neg(DisasContext *dc, const uint32_t arg[], 1904 const uint32_t par[]) 1905 { 1906 tcg_gen_neg_i32(cpu_R[arg[0]], cpu_R[arg[1]]); 1907 } 1908 1909 static void translate_nop(DisasContext *dc, const uint32_t arg[], 1910 const uint32_t par[]) 1911 { 1912 } 1913 1914 static void translate_nsa(DisasContext *dc, const uint32_t arg[], 1915 const uint32_t par[]) 1916 { 1917 tcg_gen_clrsb_i32(cpu_R[arg[0]], cpu_R[arg[1]]); 1918 } 1919 1920 static void translate_nsau(DisasContext *dc, const uint32_t arg[], 1921 const uint32_t par[]) 1922 { 1923 tcg_gen_clzi_i32(cpu_R[arg[0]], cpu_R[arg[1]], 32); 1924 } 1925 1926 static void translate_or(DisasContext *dc, const uint32_t arg[], 1927 const uint32_t par[]) 1928 { 1929 tcg_gen_or_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); 1930 } 1931 1932 static void translate_ptlb(DisasContext *dc, const uint32_t arg[], 1933 const uint32_t par[]) 1934 { 1935 #ifndef CONFIG_USER_ONLY 1936 TCGv_i32 dtlb = tcg_const_i32(par[0]); 1937 1938 tcg_gen_movi_i32(cpu_pc, dc->pc); 1939 gen_helper_ptlb(cpu_R[arg[0]], cpu_env, cpu_R[arg[1]], dtlb); 1940 tcg_temp_free(dtlb); 1941 #endif 1942 } 1943 1944 static void translate_quos(DisasContext *dc, const uint32_t arg[], 1945 const uint32_t par[]) 1946 { 1947 TCGLabel *label1 = gen_new_label(); 1948 TCGLabel *label2 = gen_new_label(); 1949 1950 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[arg[1]], 0x80000000, 1951 label1); 1952 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[arg[2]], 0xffffffff, 1953 label1); 1954 tcg_gen_movi_i32(cpu_R[arg[0]], 1955 par[0] ? 0x80000000 : 0); 1956 tcg_gen_br(label2); 1957 gen_set_label(label1); 1958 if (par[0]) { 1959 tcg_gen_div_i32(cpu_R[arg[0]], 1960 cpu_R[arg[1]], cpu_R[arg[2]]); 1961 } else { 1962 tcg_gen_rem_i32(cpu_R[arg[0]], 1963 cpu_R[arg[1]], cpu_R[arg[2]]); 1964 } 1965 gen_set_label(label2); 1966 } 1967 1968 static void translate_quou(DisasContext *dc, const uint32_t arg[], 1969 const uint32_t par[]) 1970 { 1971 tcg_gen_divu_i32(cpu_R[arg[0]], 1972 cpu_R[arg[1]], cpu_R[arg[2]]); 1973 } 1974 1975 static void translate_read_impwire(DisasContext *dc, const uint32_t arg[], 1976 const uint32_t par[]) 1977 { 1978 /* TODO: GPIO32 may be a part of coprocessor */ 1979 tcg_gen_movi_i32(cpu_R[arg[0]], 0); 1980 } 1981 1982 static void translate_remu(DisasContext *dc, const uint32_t arg[], 1983 const uint32_t par[]) 1984 { 1985 tcg_gen_remu_i32(cpu_R[arg[0]], 1986 cpu_R[arg[1]], cpu_R[arg[2]]); 1987 } 1988 1989 static void translate_rer(DisasContext *dc, const uint32_t arg[], 1990 const uint32_t par[]) 1991 { 1992 gen_helper_rer(cpu_R[arg[0]], cpu_env, cpu_R[arg[1]]); 1993 } 1994 1995 static void translate_ret(DisasContext *dc, const uint32_t arg[], 1996 const uint32_t par[]) 1997 { 1998 gen_jump(dc, cpu_R[0]); 1999 } 2000 2001 static bool test_ill_retw(DisasContext *dc, const uint32_t arg[], 2002 const uint32_t par[]) 2003 { 2004 if (!dc->cwoe) { 2005 qemu_log_mask(LOG_GUEST_ERROR, 2006 "Illegal retw instruction(pc = %08x)\n", dc->pc); 2007 return true; 2008 } else { 2009 TCGv_i32 tmp = tcg_const_i32(dc->pc); 2010 2011 gen_helper_test_ill_retw(cpu_env, tmp); 2012 tcg_temp_free(tmp); 2013 return false; 2014 } 2015 } 2016 2017 static void translate_retw(DisasContext *dc, const uint32_t arg[], 2018 const uint32_t par[]) 2019 { 2020 TCGv_i32 tmp = tcg_const_i32(dc->pc); 2021 gen_helper_retw(tmp, cpu_env, tmp); 2022 gen_jump(dc, tmp); 2023 tcg_temp_free(tmp); 2024 } 2025 2026 static void translate_rfde(DisasContext *dc, const uint32_t arg[], 2027 const uint32_t par[]) 2028 { 2029 gen_jump(dc, cpu_SR[dc->config->ndepc ? DEPC : EPC1]); 2030 } 2031 2032 static void translate_rfe(DisasContext *dc, const uint32_t arg[], 2033 const uint32_t par[]) 2034 { 2035 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); 2036 gen_jump(dc, cpu_SR[EPC1]); 2037 } 2038 2039 static void translate_rfi(DisasContext *dc, const uint32_t arg[], 2040 const uint32_t par[]) 2041 { 2042 tcg_gen_mov_i32(cpu_SR[PS], cpu_SR[EPS2 + arg[0] - 2]); 2043 gen_jump(dc, cpu_SR[EPC1 + arg[0] - 1]); 2044 } 2045 2046 static void translate_rfw(DisasContext *dc, const uint32_t arg[], 2047 const uint32_t par[]) 2048 { 2049 TCGv_i32 tmp = tcg_const_i32(1); 2050 2051 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); 2052 tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]); 2053 2054 if (par[0]) { 2055 tcg_gen_andc_i32(cpu_SR[WINDOW_START], 2056 cpu_SR[WINDOW_START], tmp); 2057 } else { 2058 tcg_gen_or_i32(cpu_SR[WINDOW_START], 2059 cpu_SR[WINDOW_START], tmp); 2060 } 2061 2062 tcg_temp_free(tmp); 2063 gen_helper_restore_owb(cpu_env); 2064 gen_jump(dc, cpu_SR[EPC1]); 2065 } 2066 2067 static void translate_rotw(DisasContext *dc, const uint32_t arg[], 2068 const uint32_t par[]) 2069 { 2070 TCGv_i32 tmp = tcg_const_i32(arg[0]); 2071 gen_helper_rotw(cpu_env, tmp); 2072 tcg_temp_free(tmp); 2073 } 2074 2075 static void translate_rsil(DisasContext *dc, const uint32_t arg[], 2076 const uint32_t par[]) 2077 { 2078 tcg_gen_mov_i32(cpu_R[arg[0]], cpu_SR[PS]); 2079 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL); 2080 tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], arg[1]); 2081 } 2082 2083 static bool test_ill_rsr(DisasContext *dc, const uint32_t arg[], 2084 const uint32_t par[]) 2085 { 2086 return !check_sr(dc, par[0], SR_R); 2087 } 2088 2089 static void translate_rsr(DisasContext *dc, const uint32_t arg[], 2090 const uint32_t par[]) 2091 { 2092 gen_rsr(dc, cpu_R[arg[0]], par[0]); 2093 } 2094 2095 static void translate_rtlb(DisasContext *dc, const uint32_t arg[], 2096 const uint32_t par[]) 2097 { 2098 #ifndef CONFIG_USER_ONLY 2099 static void (* const helper[])(TCGv_i32 r, TCGv_env env, TCGv_i32 a1, 2100 TCGv_i32 a2) = { 2101 gen_helper_rtlb0, 2102 gen_helper_rtlb1, 2103 }; 2104 TCGv_i32 dtlb = tcg_const_i32(par[0]); 2105 2106 helper[par[1]](cpu_R[arg[0]], cpu_env, cpu_R[arg[1]], dtlb); 2107 tcg_temp_free(dtlb); 2108 #endif 2109 } 2110 2111 static void translate_rur(DisasContext *dc, const uint32_t arg[], 2112 const uint32_t par[]) 2113 { 2114 if (uregnames[par[0]].name) { 2115 tcg_gen_mov_i32(cpu_R[arg[0]], cpu_UR[par[0]]); 2116 } else { 2117 qemu_log_mask(LOG_UNIMP, "RUR %d not implemented\n", par[0]); 2118 } 2119 } 2120 2121 static void translate_setb_expstate(DisasContext *dc, const uint32_t arg[], 2122 const uint32_t par[]) 2123 { 2124 /* TODO: GPIO32 may be a part of coprocessor */ 2125 tcg_gen_ori_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], 1u << arg[0]); 2126 } 2127 2128 #ifdef CONFIG_USER_ONLY 2129 static void gen_check_atomctl(DisasContext *dc, TCGv_i32 addr) 2130 { 2131 } 2132 #else 2133 static void gen_check_atomctl(DisasContext *dc, TCGv_i32 addr) 2134 { 2135 TCGv_i32 tpc = tcg_const_i32(dc->pc); 2136 2137 gen_helper_check_atomctl(cpu_env, tpc, addr); 2138 tcg_temp_free(tpc); 2139 } 2140 #endif 2141 2142 static void translate_s32c1i(DisasContext *dc, const uint32_t arg[], 2143 const uint32_t par[]) 2144 { 2145 TCGv_i32 tmp = tcg_temp_local_new_i32(); 2146 TCGv_i32 addr = tcg_temp_local_new_i32(); 2147 2148 tcg_gen_mov_i32(tmp, cpu_R[arg[0]]); 2149 tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]); 2150 gen_load_store_alignment(dc, 2, addr, true); 2151 gen_check_atomctl(dc, addr); 2152 tcg_gen_atomic_cmpxchg_i32(cpu_R[arg[0]], addr, cpu_SR[SCOMPARE1], 2153 tmp, dc->cring, MO_TEUL); 2154 tcg_temp_free(addr); 2155 tcg_temp_free(tmp); 2156 } 2157 2158 static void translate_s32e(DisasContext *dc, const uint32_t arg[], 2159 const uint32_t par[]) 2160 { 2161 TCGv_i32 addr = tcg_temp_new_i32(); 2162 2163 tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]); 2164 gen_load_store_alignment(dc, 2, addr, false); 2165 tcg_gen_qemu_st_tl(cpu_R[arg[0]], addr, dc->ring, MO_TEUL); 2166 tcg_temp_free(addr); 2167 } 2168 2169 static void translate_salt(DisasContext *dc, const uint32_t arg[], 2170 const uint32_t par[]) 2171 { 2172 tcg_gen_setcond_i32(par[0], 2173 cpu_R[arg[0]], 2174 cpu_R[arg[1]], cpu_R[arg[2]]); 2175 } 2176 2177 static void translate_sext(DisasContext *dc, const uint32_t arg[], 2178 const uint32_t par[]) 2179 { 2180 int shift = 31 - arg[2]; 2181 2182 if (shift == 24) { 2183 tcg_gen_ext8s_i32(cpu_R[arg[0]], cpu_R[arg[1]]); 2184 } else if (shift == 16) { 2185 tcg_gen_ext16s_i32(cpu_R[arg[0]], cpu_R[arg[1]]); 2186 } else { 2187 TCGv_i32 tmp = tcg_temp_new_i32(); 2188 tcg_gen_shli_i32(tmp, cpu_R[arg[1]], shift); 2189 tcg_gen_sari_i32(cpu_R[arg[0]], tmp, shift); 2190 tcg_temp_free(tmp); 2191 } 2192 } 2193 2194 static bool test_ill_simcall(DisasContext *dc, const uint32_t arg[], 2195 const uint32_t par[]) 2196 { 2197 #ifdef CONFIG_USER_ONLY 2198 bool ill = true; 2199 #else 2200 bool ill = !semihosting_enabled(); 2201 #endif 2202 if (ill) { 2203 qemu_log_mask(LOG_GUEST_ERROR, "SIMCALL but semihosting is disabled\n"); 2204 } 2205 return ill; 2206 } 2207 2208 static void translate_simcall(DisasContext *dc, const uint32_t arg[], 2209 const uint32_t par[]) 2210 { 2211 #ifndef CONFIG_USER_ONLY 2212 gen_helper_simcall(cpu_env); 2213 #endif 2214 } 2215 2216 /* 2217 * Note: 64 bit ops are used here solely because SAR values 2218 * have range 0..63 2219 */ 2220 #define gen_shift_reg(cmd, reg) do { \ 2221 TCGv_i64 tmp = tcg_temp_new_i64(); \ 2222 tcg_gen_extu_i32_i64(tmp, reg); \ 2223 tcg_gen_##cmd##_i64(v, v, tmp); \ 2224 tcg_gen_extrl_i64_i32(cpu_R[arg[0]], v); \ 2225 tcg_temp_free_i64(v); \ 2226 tcg_temp_free_i64(tmp); \ 2227 } while (0) 2228 2229 #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR]) 2230 2231 static void translate_sll(DisasContext *dc, const uint32_t arg[], 2232 const uint32_t par[]) 2233 { 2234 if (dc->sar_m32_5bit) { 2235 tcg_gen_shl_i32(cpu_R[arg[0]], cpu_R[arg[1]], dc->sar_m32); 2236 } else { 2237 TCGv_i64 v = tcg_temp_new_i64(); 2238 TCGv_i32 s = tcg_const_i32(32); 2239 tcg_gen_sub_i32(s, s, cpu_SR[SAR]); 2240 tcg_gen_andi_i32(s, s, 0x3f); 2241 tcg_gen_extu_i32_i64(v, cpu_R[arg[1]]); 2242 gen_shift_reg(shl, s); 2243 tcg_temp_free(s); 2244 } 2245 } 2246 2247 static void translate_slli(DisasContext *dc, const uint32_t arg[], 2248 const uint32_t par[]) 2249 { 2250 if (arg[2] == 32) { 2251 qemu_log_mask(LOG_GUEST_ERROR, "slli a%d, a%d, 32 is undefined\n", 2252 arg[0], arg[1]); 2253 } 2254 tcg_gen_shli_i32(cpu_R[arg[0]], cpu_R[arg[1]], arg[2] & 0x1f); 2255 } 2256 2257 static void translate_sra(DisasContext *dc, const uint32_t arg[], 2258 const uint32_t par[]) 2259 { 2260 if (dc->sar_m32_5bit) { 2261 tcg_gen_sar_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_SR[SAR]); 2262 } else { 2263 TCGv_i64 v = tcg_temp_new_i64(); 2264 tcg_gen_ext_i32_i64(v, cpu_R[arg[1]]); 2265 gen_shift(sar); 2266 } 2267 } 2268 2269 static void translate_srai(DisasContext *dc, const uint32_t arg[], 2270 const uint32_t par[]) 2271 { 2272 tcg_gen_sari_i32(cpu_R[arg[0]], cpu_R[arg[1]], arg[2]); 2273 } 2274 2275 static void translate_src(DisasContext *dc, const uint32_t arg[], 2276 const uint32_t par[]) 2277 { 2278 TCGv_i64 v = tcg_temp_new_i64(); 2279 tcg_gen_concat_i32_i64(v, cpu_R[arg[2]], cpu_R[arg[1]]); 2280 gen_shift(shr); 2281 } 2282 2283 static void translate_srl(DisasContext *dc, const uint32_t arg[], 2284 const uint32_t par[]) 2285 { 2286 if (dc->sar_m32_5bit) { 2287 tcg_gen_shr_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_SR[SAR]); 2288 } else { 2289 TCGv_i64 v = tcg_temp_new_i64(); 2290 tcg_gen_extu_i32_i64(v, cpu_R[arg[1]]); 2291 gen_shift(shr); 2292 } 2293 } 2294 2295 #undef gen_shift 2296 #undef gen_shift_reg 2297 2298 static void translate_srli(DisasContext *dc, const uint32_t arg[], 2299 const uint32_t par[]) 2300 { 2301 tcg_gen_shri_i32(cpu_R[arg[0]], cpu_R[arg[1]], arg[2]); 2302 } 2303 2304 static void translate_ssa8b(DisasContext *dc, const uint32_t arg[], 2305 const uint32_t par[]) 2306 { 2307 TCGv_i32 tmp = tcg_temp_new_i32(); 2308 tcg_gen_shli_i32(tmp, cpu_R[arg[0]], 3); 2309 gen_left_shift_sar(dc, tmp); 2310 tcg_temp_free(tmp); 2311 } 2312 2313 static void translate_ssa8l(DisasContext *dc, const uint32_t arg[], 2314 const uint32_t par[]) 2315 { 2316 TCGv_i32 tmp = tcg_temp_new_i32(); 2317 tcg_gen_shli_i32(tmp, cpu_R[arg[0]], 3); 2318 gen_right_shift_sar(dc, tmp); 2319 tcg_temp_free(tmp); 2320 } 2321 2322 static void translate_ssai(DisasContext *dc, const uint32_t arg[], 2323 const uint32_t par[]) 2324 { 2325 TCGv_i32 tmp = tcg_const_i32(arg[0]); 2326 gen_right_shift_sar(dc, tmp); 2327 tcg_temp_free(tmp); 2328 } 2329 2330 static void translate_ssl(DisasContext *dc, const uint32_t arg[], 2331 const uint32_t par[]) 2332 { 2333 gen_left_shift_sar(dc, cpu_R[arg[0]]); 2334 } 2335 2336 static void translate_ssr(DisasContext *dc, const uint32_t arg[], 2337 const uint32_t par[]) 2338 { 2339 gen_right_shift_sar(dc, cpu_R[arg[0]]); 2340 } 2341 2342 static void translate_sub(DisasContext *dc, const uint32_t arg[], 2343 const uint32_t par[]) 2344 { 2345 tcg_gen_sub_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); 2346 } 2347 2348 static void translate_subx(DisasContext *dc, const uint32_t arg[], 2349 const uint32_t par[]) 2350 { 2351 TCGv_i32 tmp = tcg_temp_new_i32(); 2352 tcg_gen_shli_i32(tmp, cpu_R[arg[1]], par[0]); 2353 tcg_gen_sub_i32(cpu_R[arg[0]], tmp, cpu_R[arg[2]]); 2354 tcg_temp_free(tmp); 2355 } 2356 2357 static void translate_waiti(DisasContext *dc, const uint32_t arg[], 2358 const uint32_t par[]) 2359 { 2360 #ifndef CONFIG_USER_ONLY 2361 gen_waiti(dc, arg[0]); 2362 #endif 2363 } 2364 2365 static void translate_wtlb(DisasContext *dc, const uint32_t arg[], 2366 const uint32_t par[]) 2367 { 2368 #ifndef CONFIG_USER_ONLY 2369 TCGv_i32 dtlb = tcg_const_i32(par[0]); 2370 2371 gen_helper_wtlb(cpu_env, cpu_R[arg[0]], cpu_R[arg[1]], dtlb); 2372 tcg_temp_free(dtlb); 2373 #endif 2374 } 2375 2376 static void translate_wer(DisasContext *dc, const uint32_t arg[], 2377 const uint32_t par[]) 2378 { 2379 gen_helper_wer(cpu_env, cpu_R[arg[0]], cpu_R[arg[1]]); 2380 } 2381 2382 static void translate_wrmsk_expstate(DisasContext *dc, const uint32_t arg[], 2383 const uint32_t par[]) 2384 { 2385 /* TODO: GPIO32 may be a part of coprocessor */ 2386 tcg_gen_and_i32(cpu_UR[EXPSTATE], cpu_R[arg[0]], cpu_R[arg[1]]); 2387 } 2388 2389 static bool test_ill_wsr(DisasContext *dc, const uint32_t arg[], 2390 const uint32_t par[]) 2391 { 2392 return !check_sr(dc, par[0], SR_W); 2393 } 2394 2395 static void translate_wsr(DisasContext *dc, const uint32_t arg[], 2396 const uint32_t par[]) 2397 { 2398 gen_wsr(dc, par[0], cpu_R[arg[0]]); 2399 } 2400 2401 static void translate_wur(DisasContext *dc, const uint32_t arg[], 2402 const uint32_t par[]) 2403 { 2404 if (uregnames[par[0]].name) { 2405 gen_wur(par[0], cpu_R[arg[0]]); 2406 } else { 2407 qemu_log_mask(LOG_UNIMP, "WUR %d not implemented\n", par[0]); 2408 } 2409 } 2410 2411 static void translate_xor(DisasContext *dc, const uint32_t arg[], 2412 const uint32_t par[]) 2413 { 2414 tcg_gen_xor_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); 2415 } 2416 2417 static bool test_ill_xsr(DisasContext *dc, const uint32_t arg[], 2418 const uint32_t par[]) 2419 { 2420 return !check_sr(dc, par[0], SR_X); 2421 } 2422 2423 static void translate_xsr(DisasContext *dc, const uint32_t arg[], 2424 const uint32_t par[]) 2425 { 2426 TCGv_i32 tmp = tcg_temp_new_i32(); 2427 2428 tcg_gen_mov_i32(tmp, cpu_R[arg[0]]); 2429 gen_rsr(dc, cpu_R[arg[0]], par[0]); 2430 gen_wsr(dc, par[0], tmp); 2431 tcg_temp_free(tmp); 2432 } 2433 2434 static const XtensaOpcodeOps core_ops[] = { 2435 { 2436 .name = "abs", 2437 .translate = translate_abs, 2438 .windowed_register_op = 0x3, 2439 }, { 2440 .name = "add", 2441 .translate = translate_add, 2442 .windowed_register_op = 0x7, 2443 }, { 2444 .name = "add.n", 2445 .translate = translate_add, 2446 .windowed_register_op = 0x7, 2447 }, { 2448 .name = "addi", 2449 .translate = translate_addi, 2450 .windowed_register_op = 0x3, 2451 }, { 2452 .name = "addi.n", 2453 .translate = translate_addi, 2454 .windowed_register_op = 0x3, 2455 }, { 2456 .name = "addmi", 2457 .translate = translate_addi, 2458 .windowed_register_op = 0x3, 2459 }, { 2460 .name = "addx2", 2461 .translate = translate_addx, 2462 .par = (const uint32_t[]){1}, 2463 .windowed_register_op = 0x7, 2464 }, { 2465 .name = "addx4", 2466 .translate = translate_addx, 2467 .par = (const uint32_t[]){2}, 2468 .windowed_register_op = 0x7, 2469 }, { 2470 .name = "addx8", 2471 .translate = translate_addx, 2472 .par = (const uint32_t[]){3}, 2473 .windowed_register_op = 0x7, 2474 }, { 2475 .name = "all4", 2476 .translate = translate_all, 2477 .par = (const uint32_t[]){true, 4}, 2478 }, { 2479 .name = "all8", 2480 .translate = translate_all, 2481 .par = (const uint32_t[]){true, 8}, 2482 }, { 2483 .name = "and", 2484 .translate = translate_and, 2485 .windowed_register_op = 0x7, 2486 }, { 2487 .name = "andb", 2488 .translate = translate_boolean, 2489 .par = (const uint32_t[]){BOOLEAN_AND}, 2490 }, { 2491 .name = "andbc", 2492 .translate = translate_boolean, 2493 .par = (const uint32_t[]){BOOLEAN_ANDC}, 2494 }, { 2495 .name = "any4", 2496 .translate = translate_all, 2497 .par = (const uint32_t[]){false, 4}, 2498 }, { 2499 .name = "any8", 2500 .translate = translate_all, 2501 .par = (const uint32_t[]){false, 8}, 2502 }, { 2503 .name = "ball", 2504 .translate = translate_ball, 2505 .par = (const uint32_t[]){TCG_COND_EQ}, 2506 .windowed_register_op = 0x3, 2507 }, { 2508 .name = "bany", 2509 .translate = translate_bany, 2510 .par = (const uint32_t[]){TCG_COND_NE}, 2511 .windowed_register_op = 0x3, 2512 }, { 2513 .name = "bbc", 2514 .translate = translate_bb, 2515 .par = (const uint32_t[]){TCG_COND_EQ}, 2516 .windowed_register_op = 0x3, 2517 }, { 2518 .name = "bbci", 2519 .translate = translate_bbi, 2520 .par = (const uint32_t[]){TCG_COND_EQ}, 2521 .windowed_register_op = 0x1, 2522 }, { 2523 .name = "bbs", 2524 .translate = translate_bb, 2525 .par = (const uint32_t[]){TCG_COND_NE}, 2526 .windowed_register_op = 0x3, 2527 }, { 2528 .name = "bbsi", 2529 .translate = translate_bbi, 2530 .par = (const uint32_t[]){TCG_COND_NE}, 2531 .windowed_register_op = 0x1, 2532 }, { 2533 .name = "beq", 2534 .translate = translate_b, 2535 .par = (const uint32_t[]){TCG_COND_EQ}, 2536 .windowed_register_op = 0x3, 2537 }, { 2538 .name = "beqi", 2539 .translate = translate_bi, 2540 .par = (const uint32_t[]){TCG_COND_EQ}, 2541 .windowed_register_op = 0x1, 2542 }, { 2543 .name = "beqz", 2544 .translate = translate_bz, 2545 .par = (const uint32_t[]){TCG_COND_EQ}, 2546 .windowed_register_op = 0x1, 2547 }, { 2548 .name = "beqz.n", 2549 .translate = translate_bz, 2550 .par = (const uint32_t[]){TCG_COND_EQ}, 2551 .windowed_register_op = 0x1, 2552 }, { 2553 .name = "bf", 2554 .translate = translate_bp, 2555 .par = (const uint32_t[]){TCG_COND_EQ}, 2556 }, { 2557 .name = "bge", 2558 .translate = translate_b, 2559 .par = (const uint32_t[]){TCG_COND_GE}, 2560 .windowed_register_op = 0x3, 2561 }, { 2562 .name = "bgei", 2563 .translate = translate_bi, 2564 .par = (const uint32_t[]){TCG_COND_GE}, 2565 .windowed_register_op = 0x1, 2566 }, { 2567 .name = "bgeu", 2568 .translate = translate_b, 2569 .par = (const uint32_t[]){TCG_COND_GEU}, 2570 .windowed_register_op = 0x3, 2571 }, { 2572 .name = "bgeui", 2573 .translate = translate_bi, 2574 .par = (const uint32_t[]){TCG_COND_GEU}, 2575 .windowed_register_op = 0x1, 2576 }, { 2577 .name = "bgez", 2578 .translate = translate_bz, 2579 .par = (const uint32_t[]){TCG_COND_GE}, 2580 .windowed_register_op = 0x1, 2581 }, { 2582 .name = "blt", 2583 .translate = translate_b, 2584 .par = (const uint32_t[]){TCG_COND_LT}, 2585 .windowed_register_op = 0x3, 2586 }, { 2587 .name = "blti", 2588 .translate = translate_bi, 2589 .par = (const uint32_t[]){TCG_COND_LT}, 2590 .windowed_register_op = 0x1, 2591 }, { 2592 .name = "bltu", 2593 .translate = translate_b, 2594 .par = (const uint32_t[]){TCG_COND_LTU}, 2595 .windowed_register_op = 0x3, 2596 }, { 2597 .name = "bltui", 2598 .translate = translate_bi, 2599 .par = (const uint32_t[]){TCG_COND_LTU}, 2600 .windowed_register_op = 0x1, 2601 }, { 2602 .name = "bltz", 2603 .translate = translate_bz, 2604 .par = (const uint32_t[]){TCG_COND_LT}, 2605 .windowed_register_op = 0x1, 2606 }, { 2607 .name = "bnall", 2608 .translate = translate_ball, 2609 .par = (const uint32_t[]){TCG_COND_NE}, 2610 .windowed_register_op = 0x3, 2611 }, { 2612 .name = "bne", 2613 .translate = translate_b, 2614 .par = (const uint32_t[]){TCG_COND_NE}, 2615 .windowed_register_op = 0x3, 2616 }, { 2617 .name = "bnei", 2618 .translate = translate_bi, 2619 .par = (const uint32_t[]){TCG_COND_NE}, 2620 .windowed_register_op = 0x1, 2621 }, { 2622 .name = "bnez", 2623 .translate = translate_bz, 2624 .par = (const uint32_t[]){TCG_COND_NE}, 2625 .windowed_register_op = 0x1, 2626 }, { 2627 .name = "bnez.n", 2628 .translate = translate_bz, 2629 .par = (const uint32_t[]){TCG_COND_NE}, 2630 .windowed_register_op = 0x1, 2631 }, { 2632 .name = "bnone", 2633 .translate = translate_bany, 2634 .par = (const uint32_t[]){TCG_COND_EQ}, 2635 .windowed_register_op = 0x3, 2636 }, { 2637 .name = "break", 2638 .translate = translate_nop, 2639 .par = (const uint32_t[]){DEBUGCAUSE_BI}, 2640 .op_flags = XTENSA_OP_DEBUG_BREAK, 2641 }, { 2642 .name = "break.n", 2643 .translate = translate_nop, 2644 .par = (const uint32_t[]){DEBUGCAUSE_BN}, 2645 .op_flags = XTENSA_OP_DEBUG_BREAK, 2646 }, { 2647 .name = "bt", 2648 .translate = translate_bp, 2649 .par = (const uint32_t[]){TCG_COND_NE}, 2650 }, { 2651 .name = "call0", 2652 .translate = translate_call0, 2653 }, { 2654 .name = "call12", 2655 .translate = translate_callw, 2656 .test_overflow = test_overflow_callw, 2657 .par = (const uint32_t[]){3}, 2658 }, { 2659 .name = "call4", 2660 .translate = translate_callw, 2661 .test_overflow = test_overflow_callw, 2662 .par = (const uint32_t[]){1}, 2663 }, { 2664 .name = "call8", 2665 .translate = translate_callw, 2666 .test_overflow = test_overflow_callw, 2667 .par = (const uint32_t[]){2}, 2668 }, { 2669 .name = "callx0", 2670 .translate = translate_callx0, 2671 .windowed_register_op = 0x1, 2672 }, { 2673 .name = "callx12", 2674 .translate = translate_callxw, 2675 .test_overflow = test_overflow_callw, 2676 .par = (const uint32_t[]){3}, 2677 .windowed_register_op = 0x1, 2678 }, { 2679 .name = "callx4", 2680 .translate = translate_callxw, 2681 .test_overflow = test_overflow_callw, 2682 .par = (const uint32_t[]){1}, 2683 .windowed_register_op = 0x1, 2684 }, { 2685 .name = "callx8", 2686 .translate = translate_callxw, 2687 .test_overflow = test_overflow_callw, 2688 .par = (const uint32_t[]){2}, 2689 .windowed_register_op = 0x1, 2690 }, { 2691 .name = "clamps", 2692 .translate = translate_clamps, 2693 .windowed_register_op = 0x3, 2694 }, { 2695 .name = "clrb_expstate", 2696 .translate = translate_clrb_expstate, 2697 }, { 2698 .name = "const16", 2699 .translate = translate_const16, 2700 .windowed_register_op = 0x1, 2701 }, { 2702 .name = "depbits", 2703 .translate = translate_depbits, 2704 .windowed_register_op = 0x3, 2705 }, { 2706 .name = "dhi", 2707 .translate = translate_dcache, 2708 .op_flags = XTENSA_OP_PRIVILEGED, 2709 .windowed_register_op = 0x1, 2710 }, { 2711 .name = "dhu", 2712 .translate = translate_dcache, 2713 .op_flags = XTENSA_OP_PRIVILEGED, 2714 .windowed_register_op = 0x1, 2715 }, { 2716 .name = "dhwb", 2717 .translate = translate_dcache, 2718 .windowed_register_op = 0x1, 2719 }, { 2720 .name = "dhwbi", 2721 .translate = translate_dcache, 2722 .windowed_register_op = 0x1, 2723 }, { 2724 .name = "dii", 2725 .translate = translate_nop, 2726 .op_flags = XTENSA_OP_PRIVILEGED, 2727 .windowed_register_op = 0x1, 2728 }, { 2729 .name = "diu", 2730 .translate = translate_nop, 2731 .op_flags = XTENSA_OP_PRIVILEGED, 2732 .windowed_register_op = 0x1, 2733 }, { 2734 .name = "diwb", 2735 .translate = translate_nop, 2736 .op_flags = XTENSA_OP_PRIVILEGED, 2737 .windowed_register_op = 0x1, 2738 }, { 2739 .name = "diwbi", 2740 .translate = translate_nop, 2741 .op_flags = XTENSA_OP_PRIVILEGED, 2742 .windowed_register_op = 0x1, 2743 }, { 2744 .name = "dpfl", 2745 .translate = translate_dcache, 2746 .op_flags = XTENSA_OP_PRIVILEGED, 2747 .windowed_register_op = 0x1, 2748 }, { 2749 .name = "dpfr", 2750 .translate = translate_nop, 2751 .windowed_register_op = 0x1, 2752 }, { 2753 .name = "dpfro", 2754 .translate = translate_nop, 2755 .windowed_register_op = 0x1, 2756 }, { 2757 .name = "dpfw", 2758 .translate = translate_nop, 2759 .windowed_register_op = 0x1, 2760 }, { 2761 .name = "dpfwo", 2762 .translate = translate_nop, 2763 .windowed_register_op = 0x1, 2764 }, { 2765 .name = "dsync", 2766 .translate = translate_nop, 2767 }, { 2768 .name = "entry", 2769 .translate = translate_entry, 2770 .test_ill = test_ill_entry, 2771 .test_overflow = test_overflow_entry, 2772 .op_flags = XTENSA_OP_EXIT_TB_M1, 2773 }, { 2774 .name = "esync", 2775 .translate = translate_nop, 2776 }, { 2777 .name = "excw", 2778 .translate = translate_nop, 2779 }, { 2780 .name = "extui", 2781 .translate = translate_extui, 2782 .windowed_register_op = 0x3, 2783 }, { 2784 .name = "extw", 2785 .translate = translate_memw, 2786 }, { 2787 .name = "hwwdtlba", 2788 .op_flags = XTENSA_OP_ILL, 2789 }, { 2790 .name = "hwwitlba", 2791 .op_flags = XTENSA_OP_ILL, 2792 }, { 2793 .name = "idtlb", 2794 .translate = translate_itlb, 2795 .par = (const uint32_t[]){true}, 2796 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, 2797 .windowed_register_op = 0x1, 2798 }, { 2799 .name = "ihi", 2800 .translate = translate_icache, 2801 .windowed_register_op = 0x1, 2802 }, { 2803 .name = "ihu", 2804 .translate = translate_icache, 2805 .op_flags = XTENSA_OP_PRIVILEGED, 2806 .windowed_register_op = 0x1, 2807 }, { 2808 .name = "iii", 2809 .translate = translate_nop, 2810 .op_flags = XTENSA_OP_PRIVILEGED, 2811 .windowed_register_op = 0x1, 2812 }, { 2813 .name = "iitlb", 2814 .translate = translate_itlb, 2815 .par = (const uint32_t[]){false}, 2816 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, 2817 .windowed_register_op = 0x1, 2818 }, { 2819 .name = "iiu", 2820 .translate = translate_nop, 2821 .op_flags = XTENSA_OP_PRIVILEGED, 2822 .windowed_register_op = 0x1, 2823 }, { 2824 .name = "ill", 2825 .op_flags = XTENSA_OP_ILL, 2826 }, { 2827 .name = "ill.n", 2828 .op_flags = XTENSA_OP_ILL, 2829 }, { 2830 .name = "ipf", 2831 .translate = translate_nop, 2832 .windowed_register_op = 0x1, 2833 }, { 2834 .name = "ipfl", 2835 .translate = translate_icache, 2836 .op_flags = XTENSA_OP_PRIVILEGED, 2837 .windowed_register_op = 0x1, 2838 }, { 2839 .name = "isync", 2840 .translate = translate_nop, 2841 }, { 2842 .name = "j", 2843 .translate = translate_j, 2844 }, { 2845 .name = "jx", 2846 .translate = translate_jx, 2847 .windowed_register_op = 0x1, 2848 }, { 2849 .name = "l16si", 2850 .translate = translate_ldst, 2851 .par = (const uint32_t[]){MO_TESW, false, false}, 2852 .windowed_register_op = 0x3, 2853 }, { 2854 .name = "l16ui", 2855 .translate = translate_ldst, 2856 .par = (const uint32_t[]){MO_TEUW, false, false}, 2857 .windowed_register_op = 0x3, 2858 }, { 2859 .name = "l32ai", 2860 .translate = translate_ldst, 2861 .par = (const uint32_t[]){MO_TEUL, true, false}, 2862 .windowed_register_op = 0x3, 2863 }, { 2864 .name = "l32e", 2865 .translate = translate_l32e, 2866 .op_flags = XTENSA_OP_PRIVILEGED, 2867 .windowed_register_op = 0x3, 2868 }, { 2869 .name = "l32i", 2870 .translate = translate_ldst, 2871 .par = (const uint32_t[]){MO_TEUL, false, false}, 2872 .windowed_register_op = 0x3, 2873 }, { 2874 .name = "l32i.n", 2875 .translate = translate_ldst, 2876 .par = (const uint32_t[]){MO_TEUL, false, false}, 2877 .windowed_register_op = 0x3, 2878 }, { 2879 .name = "l32r", 2880 .translate = translate_l32r, 2881 .windowed_register_op = 0x1, 2882 }, { 2883 .name = "l8ui", 2884 .translate = translate_ldst, 2885 .par = (const uint32_t[]){MO_UB, false, false}, 2886 .windowed_register_op = 0x3, 2887 }, { 2888 .name = "lddec", 2889 .translate = translate_mac16, 2890 .par = (const uint32_t[]){MAC16_NONE, 0, 0, -4}, 2891 .windowed_register_op = 0x2, 2892 }, { 2893 .name = "ldinc", 2894 .translate = translate_mac16, 2895 .par = (const uint32_t[]){MAC16_NONE, 0, 0, 4}, 2896 .windowed_register_op = 0x2, 2897 }, { 2898 .name = "ldpte", 2899 .op_flags = XTENSA_OP_ILL, 2900 }, { 2901 .name = "loop", 2902 .translate = translate_loop, 2903 .par = (const uint32_t[]){TCG_COND_NEVER}, 2904 .windowed_register_op = 0x1, 2905 }, { 2906 .name = "loopgtz", 2907 .translate = translate_loop, 2908 .par = (const uint32_t[]){TCG_COND_GT}, 2909 .windowed_register_op = 0x1, 2910 }, { 2911 .name = "loopnez", 2912 .translate = translate_loop, 2913 .par = (const uint32_t[]){TCG_COND_NE}, 2914 .windowed_register_op = 0x1, 2915 }, { 2916 .name = "max", 2917 .translate = translate_smax, 2918 .windowed_register_op = 0x7, 2919 }, { 2920 .name = "maxu", 2921 .translate = translate_umax, 2922 .windowed_register_op = 0x7, 2923 }, { 2924 .name = "memw", 2925 .translate = translate_memw, 2926 }, { 2927 .name = "min", 2928 .translate = translate_smin, 2929 .windowed_register_op = 0x7, 2930 }, { 2931 .name = "minu", 2932 .translate = translate_umin, 2933 .windowed_register_op = 0x7, 2934 }, { 2935 .name = "mov", 2936 .translate = translate_mov, 2937 .windowed_register_op = 0x3, 2938 }, { 2939 .name = "mov.n", 2940 .translate = translate_mov, 2941 .windowed_register_op = 0x3, 2942 }, { 2943 .name = "moveqz", 2944 .translate = translate_movcond, 2945 .par = (const uint32_t[]){TCG_COND_EQ}, 2946 .windowed_register_op = 0x7, 2947 }, { 2948 .name = "movf", 2949 .translate = translate_movp, 2950 .par = (const uint32_t[]){TCG_COND_EQ}, 2951 .windowed_register_op = 0x3, 2952 }, { 2953 .name = "movgez", 2954 .translate = translate_movcond, 2955 .par = (const uint32_t[]){TCG_COND_GE}, 2956 .windowed_register_op = 0x7, 2957 }, { 2958 .name = "movi", 2959 .translate = translate_movi, 2960 .windowed_register_op = 0x1, 2961 }, { 2962 .name = "movi.n", 2963 .translate = translate_movi, 2964 .windowed_register_op = 0x1, 2965 }, { 2966 .name = "movltz", 2967 .translate = translate_movcond, 2968 .par = (const uint32_t[]){TCG_COND_LT}, 2969 .windowed_register_op = 0x7, 2970 }, { 2971 .name = "movnez", 2972 .translate = translate_movcond, 2973 .par = (const uint32_t[]){TCG_COND_NE}, 2974 .windowed_register_op = 0x7, 2975 }, { 2976 .name = "movsp", 2977 .translate = translate_movsp, 2978 .windowed_register_op = 0x3, 2979 .op_flags = XTENSA_OP_ALLOCA, 2980 }, { 2981 .name = "movt", 2982 .translate = translate_movp, 2983 .par = (const uint32_t[]){TCG_COND_NE}, 2984 .windowed_register_op = 0x3, 2985 }, { 2986 .name = "mul.aa.hh", 2987 .translate = translate_mac16, 2988 .par = (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_HH, 0}, 2989 .windowed_register_op = 0x3, 2990 }, { 2991 .name = "mul.aa.hl", 2992 .translate = translate_mac16, 2993 .par = (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_HL, 0}, 2994 .windowed_register_op = 0x3, 2995 }, { 2996 .name = "mul.aa.lh", 2997 .translate = translate_mac16, 2998 .par = (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_LH, 0}, 2999 .windowed_register_op = 0x3, 3000 }, { 3001 .name = "mul.aa.ll", 3002 .translate = translate_mac16, 3003 .par = (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_LL, 0}, 3004 .windowed_register_op = 0x3, 3005 }, { 3006 .name = "mul.ad.hh", 3007 .translate = translate_mac16, 3008 .par = (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_HH, 0}, 3009 .windowed_register_op = 0x1, 3010 }, { 3011 .name = "mul.ad.hl", 3012 .translate = translate_mac16, 3013 .par = (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_HL, 0}, 3014 .windowed_register_op = 0x1, 3015 }, { 3016 .name = "mul.ad.lh", 3017 .translate = translate_mac16, 3018 .par = (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_LH, 0}, 3019 .windowed_register_op = 0x1, 3020 }, { 3021 .name = "mul.ad.ll", 3022 .translate = translate_mac16, 3023 .par = (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_LL, 0}, 3024 .windowed_register_op = 0x1, 3025 }, { 3026 .name = "mul.da.hh", 3027 .translate = translate_mac16, 3028 .par = (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_HH, 0}, 3029 .windowed_register_op = 0x2, 3030 }, { 3031 .name = "mul.da.hl", 3032 .translate = translate_mac16, 3033 .par = (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_HL, 0}, 3034 .windowed_register_op = 0x2, 3035 }, { 3036 .name = "mul.da.lh", 3037 .translate = translate_mac16, 3038 .par = (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_LH, 0}, 3039 .windowed_register_op = 0x2, 3040 }, { 3041 .name = "mul.da.ll", 3042 .translate = translate_mac16, 3043 .par = (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_LL, 0}, 3044 .windowed_register_op = 0x2, 3045 }, { 3046 .name = "mul.dd.hh", 3047 .translate = translate_mac16, 3048 .par = (const uint32_t[]){MAC16_MUL, MAC16_DD, MAC16_HH, 0}, 3049 }, { 3050 .name = "mul.dd.hl", 3051 .translate = translate_mac16, 3052 .par = (const uint32_t[]){MAC16_MUL, MAC16_DD, MAC16_HL, 0}, 3053 }, { 3054 .name = "mul.dd.lh", 3055 .translate = translate_mac16, 3056 .par = (const uint32_t[]){MAC16_MUL, MAC16_DD, MAC16_LH, 0}, 3057 }, { 3058 .name = "mul.dd.ll", 3059 .translate = translate_mac16, 3060 .par = (const uint32_t[]){MAC16_MUL, MAC16_DD, MAC16_LL, 0}, 3061 }, { 3062 .name = "mul16s", 3063 .translate = translate_mul16, 3064 .par = (const uint32_t[]){true}, 3065 .windowed_register_op = 0x7, 3066 }, { 3067 .name = "mul16u", 3068 .translate = translate_mul16, 3069 .par = (const uint32_t[]){false}, 3070 .windowed_register_op = 0x7, 3071 }, { 3072 .name = "mula.aa.hh", 3073 .translate = translate_mac16, 3074 .par = (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_HH, 0}, 3075 .windowed_register_op = 0x3, 3076 }, { 3077 .name = "mula.aa.hl", 3078 .translate = translate_mac16, 3079 .par = (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_HL, 0}, 3080 .windowed_register_op = 0x3, 3081 }, { 3082 .name = "mula.aa.lh", 3083 .translate = translate_mac16, 3084 .par = (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_LH, 0}, 3085 .windowed_register_op = 0x3, 3086 }, { 3087 .name = "mula.aa.ll", 3088 .translate = translate_mac16, 3089 .par = (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_LL, 0}, 3090 .windowed_register_op = 0x3, 3091 }, { 3092 .name = "mula.ad.hh", 3093 .translate = translate_mac16, 3094 .par = (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_HH, 0}, 3095 .windowed_register_op = 0x1, 3096 }, { 3097 .name = "mula.ad.hl", 3098 .translate = translate_mac16, 3099 .par = (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_HL, 0}, 3100 .windowed_register_op = 0x1, 3101 }, { 3102 .name = "mula.ad.lh", 3103 .translate = translate_mac16, 3104 .par = (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_LH, 0}, 3105 .windowed_register_op = 0x1, 3106 }, { 3107 .name = "mula.ad.ll", 3108 .translate = translate_mac16, 3109 .par = (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_LL, 0}, 3110 .windowed_register_op = 0x1, 3111 }, { 3112 .name = "mula.da.hh", 3113 .translate = translate_mac16, 3114 .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HH, 0}, 3115 .windowed_register_op = 0x2, 3116 }, { 3117 .name = "mula.da.hh.lddec", 3118 .translate = translate_mac16, 3119 .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HH, -4}, 3120 .windowed_register_op = 0xa, 3121 }, { 3122 .name = "mula.da.hh.ldinc", 3123 .translate = translate_mac16, 3124 .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HH, 4}, 3125 .windowed_register_op = 0xa, 3126 }, { 3127 .name = "mula.da.hl", 3128 .translate = translate_mac16, 3129 .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HL, 0}, 3130 .windowed_register_op = 0x2, 3131 }, { 3132 .name = "mula.da.hl.lddec", 3133 .translate = translate_mac16, 3134 .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HL, -4}, 3135 .windowed_register_op = 0xa, 3136 }, { 3137 .name = "mula.da.hl.ldinc", 3138 .translate = translate_mac16, 3139 .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HL, 4}, 3140 .windowed_register_op = 0xa, 3141 }, { 3142 .name = "mula.da.lh", 3143 .translate = translate_mac16, 3144 .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LH, 0}, 3145 .windowed_register_op = 0x2, 3146 }, { 3147 .name = "mula.da.lh.lddec", 3148 .translate = translate_mac16, 3149 .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LH, -4}, 3150 .windowed_register_op = 0xa, 3151 }, { 3152 .name = "mula.da.lh.ldinc", 3153 .translate = translate_mac16, 3154 .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LH, 4}, 3155 .windowed_register_op = 0xa, 3156 }, { 3157 .name = "mula.da.ll", 3158 .translate = translate_mac16, 3159 .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LL, 0}, 3160 .windowed_register_op = 0x2, 3161 }, { 3162 .name = "mula.da.ll.lddec", 3163 .translate = translate_mac16, 3164 .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LL, -4}, 3165 .windowed_register_op = 0xa, 3166 }, { 3167 .name = "mula.da.ll.ldinc", 3168 .translate = translate_mac16, 3169 .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LL, 4}, 3170 .windowed_register_op = 0xa, 3171 }, { 3172 .name = "mula.dd.hh", 3173 .translate = translate_mac16, 3174 .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HH, 0}, 3175 }, { 3176 .name = "mula.dd.hh.lddec", 3177 .translate = translate_mac16, 3178 .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HH, -4}, 3179 .windowed_register_op = 0x2, 3180 }, { 3181 .name = "mula.dd.hh.ldinc", 3182 .translate = translate_mac16, 3183 .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HH, 4}, 3184 .windowed_register_op = 0x2, 3185 }, { 3186 .name = "mula.dd.hl", 3187 .translate = translate_mac16, 3188 .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HL, 0}, 3189 }, { 3190 .name = "mula.dd.hl.lddec", 3191 .translate = translate_mac16, 3192 .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HL, -4}, 3193 .windowed_register_op = 0x2, 3194 }, { 3195 .name = "mula.dd.hl.ldinc", 3196 .translate = translate_mac16, 3197 .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HL, 4}, 3198 .windowed_register_op = 0x2, 3199 }, { 3200 .name = "mula.dd.lh", 3201 .translate = translate_mac16, 3202 .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LH, 0}, 3203 }, { 3204 .name = "mula.dd.lh.lddec", 3205 .translate = translate_mac16, 3206 .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LH, -4}, 3207 .windowed_register_op = 0x2, 3208 }, { 3209 .name = "mula.dd.lh.ldinc", 3210 .translate = translate_mac16, 3211 .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LH, 4}, 3212 .windowed_register_op = 0x2, 3213 }, { 3214 .name = "mula.dd.ll", 3215 .translate = translate_mac16, 3216 .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LL, 0}, 3217 }, { 3218 .name = "mula.dd.ll.lddec", 3219 .translate = translate_mac16, 3220 .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LL, -4}, 3221 .windowed_register_op = 0x2, 3222 }, { 3223 .name = "mula.dd.ll.ldinc", 3224 .translate = translate_mac16, 3225 .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LL, 4}, 3226 .windowed_register_op = 0x2, 3227 }, { 3228 .name = "mull", 3229 .translate = translate_mull, 3230 .windowed_register_op = 0x7, 3231 }, { 3232 .name = "muls.aa.hh", 3233 .translate = translate_mac16, 3234 .par = (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_HH, 0}, 3235 .windowed_register_op = 0x3, 3236 }, { 3237 .name = "muls.aa.hl", 3238 .translate = translate_mac16, 3239 .par = (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_HL, 0}, 3240 .windowed_register_op = 0x3, 3241 }, { 3242 .name = "muls.aa.lh", 3243 .translate = translate_mac16, 3244 .par = (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_LH, 0}, 3245 .windowed_register_op = 0x3, 3246 }, { 3247 .name = "muls.aa.ll", 3248 .translate = translate_mac16, 3249 .par = (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_LL, 0}, 3250 .windowed_register_op = 0x3, 3251 }, { 3252 .name = "muls.ad.hh", 3253 .translate = translate_mac16, 3254 .par = (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_HH, 0}, 3255 .windowed_register_op = 0x1, 3256 }, { 3257 .name = "muls.ad.hl", 3258 .translate = translate_mac16, 3259 .par = (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_HL, 0}, 3260 .windowed_register_op = 0x1, 3261 }, { 3262 .name = "muls.ad.lh", 3263 .translate = translate_mac16, 3264 .par = (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_LH, 0}, 3265 .windowed_register_op = 0x1, 3266 }, { 3267 .name = "muls.ad.ll", 3268 .translate = translate_mac16, 3269 .par = (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_LL, 0}, 3270 .windowed_register_op = 0x1, 3271 }, { 3272 .name = "muls.da.hh", 3273 .translate = translate_mac16, 3274 .par = (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_HH, 0}, 3275 .windowed_register_op = 0x2, 3276 }, { 3277 .name = "muls.da.hl", 3278 .translate = translate_mac16, 3279 .par = (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_HL, 0}, 3280 .windowed_register_op = 0x2, 3281 }, { 3282 .name = "muls.da.lh", 3283 .translate = translate_mac16, 3284 .par = (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_LH, 0}, 3285 .windowed_register_op = 0x2, 3286 }, { 3287 .name = "muls.da.ll", 3288 .translate = translate_mac16, 3289 .par = (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_LL, 0}, 3290 .windowed_register_op = 0x2, 3291 }, { 3292 .name = "muls.dd.hh", 3293 .translate = translate_mac16, 3294 .par = (const uint32_t[]){MAC16_MULS, MAC16_DD, MAC16_HH, 0}, 3295 }, { 3296 .name = "muls.dd.hl", 3297 .translate = translate_mac16, 3298 .par = (const uint32_t[]){MAC16_MULS, MAC16_DD, MAC16_HL, 0}, 3299 }, { 3300 .name = "muls.dd.lh", 3301 .translate = translate_mac16, 3302 .par = (const uint32_t[]){MAC16_MULS, MAC16_DD, MAC16_LH, 0}, 3303 }, { 3304 .name = "muls.dd.ll", 3305 .translate = translate_mac16, 3306 .par = (const uint32_t[]){MAC16_MULS, MAC16_DD, MAC16_LL, 0}, 3307 }, { 3308 .name = "mulsh", 3309 .translate = translate_mulh, 3310 .par = (const uint32_t[]){true}, 3311 .windowed_register_op = 0x7, 3312 }, { 3313 .name = "muluh", 3314 .translate = translate_mulh, 3315 .par = (const uint32_t[]){false}, 3316 .windowed_register_op = 0x7, 3317 }, { 3318 .name = "neg", 3319 .translate = translate_neg, 3320 .windowed_register_op = 0x3, 3321 }, { 3322 .name = "nop", 3323 .translate = translate_nop, 3324 }, { 3325 .name = "nop.n", 3326 .translate = translate_nop, 3327 }, { 3328 .name = "nsa", 3329 .translate = translate_nsa, 3330 .windowed_register_op = 0x3, 3331 }, { 3332 .name = "nsau", 3333 .translate = translate_nsau, 3334 .windowed_register_op = 0x3, 3335 }, { 3336 .name = "or", 3337 .translate = translate_or, 3338 .windowed_register_op = 0x7, 3339 }, { 3340 .name = "orb", 3341 .translate = translate_boolean, 3342 .par = (const uint32_t[]){BOOLEAN_OR}, 3343 }, { 3344 .name = "orbc", 3345 .translate = translate_boolean, 3346 .par = (const uint32_t[]){BOOLEAN_ORC}, 3347 }, { 3348 .name = "pdtlb", 3349 .translate = translate_ptlb, 3350 .par = (const uint32_t[]){true}, 3351 .op_flags = XTENSA_OP_PRIVILEGED, 3352 .windowed_register_op = 0x3, 3353 }, { 3354 .name = "pitlb", 3355 .translate = translate_ptlb, 3356 .par = (const uint32_t[]){false}, 3357 .op_flags = XTENSA_OP_PRIVILEGED, 3358 .windowed_register_op = 0x3, 3359 }, { 3360 .name = "quos", 3361 .translate = translate_quos, 3362 .par = (const uint32_t[]){true}, 3363 .op_flags = XTENSA_OP_DIVIDE_BY_ZERO, 3364 .windowed_register_op = 0x7, 3365 }, { 3366 .name = "quou", 3367 .translate = translate_quou, 3368 .op_flags = XTENSA_OP_DIVIDE_BY_ZERO, 3369 .windowed_register_op = 0x7, 3370 }, { 3371 .name = "rdtlb0", 3372 .translate = translate_rtlb, 3373 .par = (const uint32_t[]){true, 0}, 3374 .op_flags = XTENSA_OP_PRIVILEGED, 3375 .windowed_register_op = 0x3, 3376 }, { 3377 .name = "rdtlb1", 3378 .translate = translate_rtlb, 3379 .par = (const uint32_t[]){true, 1}, 3380 .op_flags = XTENSA_OP_PRIVILEGED, 3381 .windowed_register_op = 0x3, 3382 }, { 3383 .name = "read_impwire", 3384 .translate = translate_read_impwire, 3385 .windowed_register_op = 0x1, 3386 }, { 3387 .name = "rems", 3388 .translate = translate_quos, 3389 .par = (const uint32_t[]){false}, 3390 .op_flags = XTENSA_OP_DIVIDE_BY_ZERO, 3391 .windowed_register_op = 0x7, 3392 }, { 3393 .name = "remu", 3394 .translate = translate_remu, 3395 .op_flags = XTENSA_OP_DIVIDE_BY_ZERO, 3396 .windowed_register_op = 0x7, 3397 }, { 3398 .name = "rer", 3399 .translate = translate_rer, 3400 .op_flags = XTENSA_OP_PRIVILEGED, 3401 .windowed_register_op = 0x3, 3402 }, { 3403 .name = "ret", 3404 .translate = translate_ret, 3405 }, { 3406 .name = "ret.n", 3407 .translate = translate_ret, 3408 }, { 3409 .name = "retw", 3410 .translate = translate_retw, 3411 .test_ill = test_ill_retw, 3412 .op_flags = XTENSA_OP_UNDERFLOW, 3413 }, { 3414 .name = "retw.n", 3415 .translate = translate_retw, 3416 .test_ill = test_ill_retw, 3417 .op_flags = XTENSA_OP_UNDERFLOW, 3418 }, { 3419 .name = "rfdd", 3420 .op_flags = XTENSA_OP_ILL, 3421 }, { 3422 .name = "rfde", 3423 .translate = translate_rfde, 3424 .op_flags = XTENSA_OP_PRIVILEGED, 3425 }, { 3426 .name = "rfdo", 3427 .op_flags = XTENSA_OP_ILL, 3428 }, { 3429 .name = "rfe", 3430 .translate = translate_rfe, 3431 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_CHECK_INTERRUPTS, 3432 }, { 3433 .name = "rfi", 3434 .translate = translate_rfi, 3435 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_CHECK_INTERRUPTS, 3436 }, { 3437 .name = "rfwo", 3438 .translate = translate_rfw, 3439 .par = (const uint32_t[]){true}, 3440 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_CHECK_INTERRUPTS, 3441 }, { 3442 .name = "rfwu", 3443 .translate = translate_rfw, 3444 .par = (const uint32_t[]){false}, 3445 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_CHECK_INTERRUPTS, 3446 }, { 3447 .name = "ritlb0", 3448 .translate = translate_rtlb, 3449 .par = (const uint32_t[]){false, 0}, 3450 .op_flags = XTENSA_OP_PRIVILEGED, 3451 .windowed_register_op = 0x3, 3452 }, { 3453 .name = "ritlb1", 3454 .translate = translate_rtlb, 3455 .par = (const uint32_t[]){false, 1}, 3456 .op_flags = XTENSA_OP_PRIVILEGED, 3457 .windowed_register_op = 0x3, 3458 }, { 3459 .name = "rotw", 3460 .translate = translate_rotw, 3461 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, 3462 }, { 3463 .name = "rsil", 3464 .translate = translate_rsil, 3465 .op_flags = 3466 XTENSA_OP_PRIVILEGED | 3467 XTENSA_OP_EXIT_TB_0 | 3468 XTENSA_OP_CHECK_INTERRUPTS, 3469 .windowed_register_op = 0x1, 3470 }, { 3471 .name = "rsr.176", 3472 .translate = translate_rsr, 3473 .test_ill = test_ill_rsr, 3474 .par = (const uint32_t[]){176}, 3475 .op_flags = XTENSA_OP_PRIVILEGED, 3476 .windowed_register_op = 0x1, 3477 }, { 3478 .name = "rsr.208", 3479 .translate = translate_rsr, 3480 .test_ill = test_ill_rsr, 3481 .par = (const uint32_t[]){208}, 3482 .op_flags = XTENSA_OP_PRIVILEGED, 3483 .windowed_register_op = 0x1, 3484 }, { 3485 .name = "rsr.acchi", 3486 .translate = translate_rsr, 3487 .test_ill = test_ill_rsr, 3488 .par = (const uint32_t[]){ACCHI}, 3489 .windowed_register_op = 0x1, 3490 }, { 3491 .name = "rsr.acclo", 3492 .translate = translate_rsr, 3493 .test_ill = test_ill_rsr, 3494 .par = (const uint32_t[]){ACCLO}, 3495 .windowed_register_op = 0x1, 3496 }, { 3497 .name = "rsr.atomctl", 3498 .translate = translate_rsr, 3499 .test_ill = test_ill_rsr, 3500 .par = (const uint32_t[]){ATOMCTL}, 3501 .op_flags = XTENSA_OP_PRIVILEGED, 3502 .windowed_register_op = 0x1, 3503 }, { 3504 .name = "rsr.br", 3505 .translate = translate_rsr, 3506 .test_ill = test_ill_rsr, 3507 .par = (const uint32_t[]){BR}, 3508 .windowed_register_op = 0x1, 3509 }, { 3510 .name = "rsr.cacheattr", 3511 .translate = translate_rsr, 3512 .test_ill = test_ill_rsr, 3513 .par = (const uint32_t[]){CACHEATTR}, 3514 .op_flags = XTENSA_OP_PRIVILEGED, 3515 .windowed_register_op = 0x1, 3516 }, { 3517 .name = "rsr.ccompare0", 3518 .translate = translate_rsr, 3519 .test_ill = test_ill_rsr, 3520 .par = (const uint32_t[]){CCOMPARE}, 3521 .op_flags = XTENSA_OP_PRIVILEGED, 3522 .windowed_register_op = 0x1, 3523 }, { 3524 .name = "rsr.ccompare1", 3525 .translate = translate_rsr, 3526 .test_ill = test_ill_rsr, 3527 .par = (const uint32_t[]){CCOMPARE + 1}, 3528 .op_flags = XTENSA_OP_PRIVILEGED, 3529 .windowed_register_op = 0x1, 3530 }, { 3531 .name = "rsr.ccompare2", 3532 .translate = translate_rsr, 3533 .test_ill = test_ill_rsr, 3534 .par = (const uint32_t[]){CCOMPARE + 2}, 3535 .op_flags = XTENSA_OP_PRIVILEGED, 3536 .windowed_register_op = 0x1, 3537 }, { 3538 .name = "rsr.ccount", 3539 .translate = translate_rsr, 3540 .test_ill = test_ill_rsr, 3541 .par = (const uint32_t[]){CCOUNT}, 3542 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, 3543 .windowed_register_op = 0x1, 3544 }, { 3545 .name = "rsr.configid0", 3546 .translate = translate_rsr, 3547 .test_ill = test_ill_rsr, 3548 .par = (const uint32_t[]){CONFIGID0}, 3549 .op_flags = XTENSA_OP_PRIVILEGED, 3550 .windowed_register_op = 0x1, 3551 }, { 3552 .name = "rsr.configid1", 3553 .translate = translate_rsr, 3554 .test_ill = test_ill_rsr, 3555 .par = (const uint32_t[]){CONFIGID1}, 3556 .op_flags = XTENSA_OP_PRIVILEGED, 3557 .windowed_register_op = 0x1, 3558 }, { 3559 .name = "rsr.cpenable", 3560 .translate = translate_rsr, 3561 .test_ill = test_ill_rsr, 3562 .par = (const uint32_t[]){CPENABLE}, 3563 .op_flags = XTENSA_OP_PRIVILEGED, 3564 .windowed_register_op = 0x1, 3565 }, { 3566 .name = "rsr.dbreaka0", 3567 .translate = translate_rsr, 3568 .test_ill = test_ill_rsr, 3569 .par = (const uint32_t[]){DBREAKA}, 3570 .op_flags = XTENSA_OP_PRIVILEGED, 3571 .windowed_register_op = 0x1, 3572 }, { 3573 .name = "rsr.dbreaka1", 3574 .translate = translate_rsr, 3575 .test_ill = test_ill_rsr, 3576 .par = (const uint32_t[]){DBREAKA + 1}, 3577 .op_flags = XTENSA_OP_PRIVILEGED, 3578 .windowed_register_op = 0x1, 3579 }, { 3580 .name = "rsr.dbreakc0", 3581 .translate = translate_rsr, 3582 .test_ill = test_ill_rsr, 3583 .par = (const uint32_t[]){DBREAKC}, 3584 .op_flags = XTENSA_OP_PRIVILEGED, 3585 .windowed_register_op = 0x1, 3586 }, { 3587 .name = "rsr.dbreakc1", 3588 .translate = translate_rsr, 3589 .test_ill = test_ill_rsr, 3590 .par = (const uint32_t[]){DBREAKC + 1}, 3591 .op_flags = XTENSA_OP_PRIVILEGED, 3592 .windowed_register_op = 0x1, 3593 }, { 3594 .name = "rsr.ddr", 3595 .translate = translate_rsr, 3596 .test_ill = test_ill_rsr, 3597 .par = (const uint32_t[]){DDR}, 3598 .op_flags = XTENSA_OP_PRIVILEGED, 3599 .windowed_register_op = 0x1, 3600 }, { 3601 .name = "rsr.debugcause", 3602 .translate = translate_rsr, 3603 .test_ill = test_ill_rsr, 3604 .par = (const uint32_t[]){DEBUGCAUSE}, 3605 .op_flags = XTENSA_OP_PRIVILEGED, 3606 .windowed_register_op = 0x1, 3607 }, { 3608 .name = "rsr.depc", 3609 .translate = translate_rsr, 3610 .test_ill = test_ill_rsr, 3611 .par = (const uint32_t[]){DEPC}, 3612 .op_flags = XTENSA_OP_PRIVILEGED, 3613 .windowed_register_op = 0x1, 3614 }, { 3615 .name = "rsr.dtlbcfg", 3616 .translate = translate_rsr, 3617 .test_ill = test_ill_rsr, 3618 .par = (const uint32_t[]){DTLBCFG}, 3619 .op_flags = XTENSA_OP_PRIVILEGED, 3620 .windowed_register_op = 0x1, 3621 }, { 3622 .name = "rsr.epc1", 3623 .translate = translate_rsr, 3624 .test_ill = test_ill_rsr, 3625 .par = (const uint32_t[]){EPC1}, 3626 .op_flags = XTENSA_OP_PRIVILEGED, 3627 .windowed_register_op = 0x1, 3628 }, { 3629 .name = "rsr.epc2", 3630 .translate = translate_rsr, 3631 .test_ill = test_ill_rsr, 3632 .par = (const uint32_t[]){EPC1 + 1}, 3633 .op_flags = XTENSA_OP_PRIVILEGED, 3634 .windowed_register_op = 0x1, 3635 }, { 3636 .name = "rsr.epc3", 3637 .translate = translate_rsr, 3638 .test_ill = test_ill_rsr, 3639 .par = (const uint32_t[]){EPC1 + 2}, 3640 .op_flags = XTENSA_OP_PRIVILEGED, 3641 .windowed_register_op = 0x1, 3642 }, { 3643 .name = "rsr.epc4", 3644 .translate = translate_rsr, 3645 .test_ill = test_ill_rsr, 3646 .par = (const uint32_t[]){EPC1 + 3}, 3647 .op_flags = XTENSA_OP_PRIVILEGED, 3648 .windowed_register_op = 0x1, 3649 }, { 3650 .name = "rsr.epc5", 3651 .translate = translate_rsr, 3652 .test_ill = test_ill_rsr, 3653 .par = (const uint32_t[]){EPC1 + 4}, 3654 .op_flags = XTENSA_OP_PRIVILEGED, 3655 .windowed_register_op = 0x1, 3656 }, { 3657 .name = "rsr.epc6", 3658 .translate = translate_rsr, 3659 .test_ill = test_ill_rsr, 3660 .par = (const uint32_t[]){EPC1 + 5}, 3661 .op_flags = XTENSA_OP_PRIVILEGED, 3662 .windowed_register_op = 0x1, 3663 }, { 3664 .name = "rsr.epc7", 3665 .translate = translate_rsr, 3666 .test_ill = test_ill_rsr, 3667 .par = (const uint32_t[]){EPC1 + 6}, 3668 .op_flags = XTENSA_OP_PRIVILEGED, 3669 .windowed_register_op = 0x1, 3670 }, { 3671 .name = "rsr.eps2", 3672 .translate = translate_rsr, 3673 .test_ill = test_ill_rsr, 3674 .par = (const uint32_t[]){EPS2}, 3675 .op_flags = XTENSA_OP_PRIVILEGED, 3676 .windowed_register_op = 0x1, 3677 }, { 3678 .name = "rsr.eps3", 3679 .translate = translate_rsr, 3680 .test_ill = test_ill_rsr, 3681 .par = (const uint32_t[]){EPS2 + 1}, 3682 .op_flags = XTENSA_OP_PRIVILEGED, 3683 .windowed_register_op = 0x1, 3684 }, { 3685 .name = "rsr.eps4", 3686 .translate = translate_rsr, 3687 .test_ill = test_ill_rsr, 3688 .par = (const uint32_t[]){EPS2 + 2}, 3689 .op_flags = XTENSA_OP_PRIVILEGED, 3690 .windowed_register_op = 0x1, 3691 }, { 3692 .name = "rsr.eps5", 3693 .translate = translate_rsr, 3694 .test_ill = test_ill_rsr, 3695 .par = (const uint32_t[]){EPS2 + 3}, 3696 .op_flags = XTENSA_OP_PRIVILEGED, 3697 .windowed_register_op = 0x1, 3698 }, { 3699 .name = "rsr.eps6", 3700 .translate = translate_rsr, 3701 .test_ill = test_ill_rsr, 3702 .par = (const uint32_t[]){EPS2 + 4}, 3703 .op_flags = XTENSA_OP_PRIVILEGED, 3704 .windowed_register_op = 0x1, 3705 }, { 3706 .name = "rsr.eps7", 3707 .translate = translate_rsr, 3708 .test_ill = test_ill_rsr, 3709 .par = (const uint32_t[]){EPS2 + 5}, 3710 .op_flags = XTENSA_OP_PRIVILEGED, 3711 .windowed_register_op = 0x1, 3712 }, { 3713 .name = "rsr.exccause", 3714 .translate = translate_rsr, 3715 .test_ill = test_ill_rsr, 3716 .par = (const uint32_t[]){EXCCAUSE}, 3717 .op_flags = XTENSA_OP_PRIVILEGED, 3718 .windowed_register_op = 0x1, 3719 }, { 3720 .name = "rsr.excsave1", 3721 .translate = translate_rsr, 3722 .test_ill = test_ill_rsr, 3723 .par = (const uint32_t[]){EXCSAVE1}, 3724 .op_flags = XTENSA_OP_PRIVILEGED, 3725 .windowed_register_op = 0x1, 3726 }, { 3727 .name = "rsr.excsave2", 3728 .translate = translate_rsr, 3729 .test_ill = test_ill_rsr, 3730 .par = (const uint32_t[]){EXCSAVE1 + 1}, 3731 .op_flags = XTENSA_OP_PRIVILEGED, 3732 .windowed_register_op = 0x1, 3733 }, { 3734 .name = "rsr.excsave3", 3735 .translate = translate_rsr, 3736 .test_ill = test_ill_rsr, 3737 .par = (const uint32_t[]){EXCSAVE1 + 2}, 3738 .op_flags = XTENSA_OP_PRIVILEGED, 3739 .windowed_register_op = 0x1, 3740 }, { 3741 .name = "rsr.excsave4", 3742 .translate = translate_rsr, 3743 .test_ill = test_ill_rsr, 3744 .par = (const uint32_t[]){EXCSAVE1 + 3}, 3745 .op_flags = XTENSA_OP_PRIVILEGED, 3746 .windowed_register_op = 0x1, 3747 }, { 3748 .name = "rsr.excsave5", 3749 .translate = translate_rsr, 3750 .test_ill = test_ill_rsr, 3751 .par = (const uint32_t[]){EXCSAVE1 + 4}, 3752 .op_flags = XTENSA_OP_PRIVILEGED, 3753 .windowed_register_op = 0x1, 3754 }, { 3755 .name = "rsr.excsave6", 3756 .translate = translate_rsr, 3757 .test_ill = test_ill_rsr, 3758 .par = (const uint32_t[]){EXCSAVE1 + 5}, 3759 .op_flags = XTENSA_OP_PRIVILEGED, 3760 .windowed_register_op = 0x1, 3761 }, { 3762 .name = "rsr.excsave7", 3763 .translate = translate_rsr, 3764 .test_ill = test_ill_rsr, 3765 .par = (const uint32_t[]){EXCSAVE1 + 6}, 3766 .op_flags = XTENSA_OP_PRIVILEGED, 3767 .windowed_register_op = 0x1, 3768 }, { 3769 .name = "rsr.excvaddr", 3770 .translate = translate_rsr, 3771 .test_ill = test_ill_rsr, 3772 .par = (const uint32_t[]){EXCVADDR}, 3773 .op_flags = XTENSA_OP_PRIVILEGED, 3774 .windowed_register_op = 0x1, 3775 }, { 3776 .name = "rsr.ibreaka0", 3777 .translate = translate_rsr, 3778 .test_ill = test_ill_rsr, 3779 .par = (const uint32_t[]){IBREAKA}, 3780 .op_flags = XTENSA_OP_PRIVILEGED, 3781 .windowed_register_op = 0x1, 3782 }, { 3783 .name = "rsr.ibreaka1", 3784 .translate = translate_rsr, 3785 .test_ill = test_ill_rsr, 3786 .par = (const uint32_t[]){IBREAKA + 1}, 3787 .op_flags = XTENSA_OP_PRIVILEGED, 3788 .windowed_register_op = 0x1, 3789 }, { 3790 .name = "rsr.ibreakenable", 3791 .translate = translate_rsr, 3792 .test_ill = test_ill_rsr, 3793 .par = (const uint32_t[]){IBREAKENABLE}, 3794 .op_flags = XTENSA_OP_PRIVILEGED, 3795 .windowed_register_op = 0x1, 3796 }, { 3797 .name = "rsr.icount", 3798 .translate = translate_rsr, 3799 .test_ill = test_ill_rsr, 3800 .par = (const uint32_t[]){ICOUNT}, 3801 .op_flags = XTENSA_OP_PRIVILEGED, 3802 .windowed_register_op = 0x1, 3803 }, { 3804 .name = "rsr.icountlevel", 3805 .translate = translate_rsr, 3806 .test_ill = test_ill_rsr, 3807 .par = (const uint32_t[]){ICOUNTLEVEL}, 3808 .op_flags = XTENSA_OP_PRIVILEGED, 3809 .windowed_register_op = 0x1, 3810 }, { 3811 .name = "rsr.intclear", 3812 .translate = translate_rsr, 3813 .test_ill = test_ill_rsr, 3814 .par = (const uint32_t[]){INTCLEAR}, 3815 .op_flags = XTENSA_OP_PRIVILEGED, 3816 .windowed_register_op = 0x1, 3817 }, { 3818 .name = "rsr.intenable", 3819 .translate = translate_rsr, 3820 .test_ill = test_ill_rsr, 3821 .par = (const uint32_t[]){INTENABLE}, 3822 .op_flags = XTENSA_OP_PRIVILEGED, 3823 .windowed_register_op = 0x1, 3824 }, { 3825 .name = "rsr.interrupt", 3826 .translate = translate_rsr, 3827 .test_ill = test_ill_rsr, 3828 .par = (const uint32_t[]){INTSET}, 3829 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, 3830 .windowed_register_op = 0x1, 3831 }, { 3832 .name = "rsr.intset", 3833 .translate = translate_rsr, 3834 .test_ill = test_ill_rsr, 3835 .par = (const uint32_t[]){INTSET}, 3836 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, 3837 .windowed_register_op = 0x1, 3838 }, { 3839 .name = "rsr.itlbcfg", 3840 .translate = translate_rsr, 3841 .test_ill = test_ill_rsr, 3842 .par = (const uint32_t[]){ITLBCFG}, 3843 .op_flags = XTENSA_OP_PRIVILEGED, 3844 .windowed_register_op = 0x1, 3845 }, { 3846 .name = "rsr.lbeg", 3847 .translate = translate_rsr, 3848 .test_ill = test_ill_rsr, 3849 .par = (const uint32_t[]){LBEG}, 3850 .windowed_register_op = 0x1, 3851 }, { 3852 .name = "rsr.lcount", 3853 .translate = translate_rsr, 3854 .test_ill = test_ill_rsr, 3855 .par = (const uint32_t[]){LCOUNT}, 3856 .windowed_register_op = 0x1, 3857 }, { 3858 .name = "rsr.lend", 3859 .translate = translate_rsr, 3860 .test_ill = test_ill_rsr, 3861 .par = (const uint32_t[]){LEND}, 3862 .windowed_register_op = 0x1, 3863 }, { 3864 .name = "rsr.litbase", 3865 .translate = translate_rsr, 3866 .test_ill = test_ill_rsr, 3867 .par = (const uint32_t[]){LITBASE}, 3868 .windowed_register_op = 0x1, 3869 }, { 3870 .name = "rsr.m0", 3871 .translate = translate_rsr, 3872 .test_ill = test_ill_rsr, 3873 .par = (const uint32_t[]){MR}, 3874 .windowed_register_op = 0x1, 3875 }, { 3876 .name = "rsr.m1", 3877 .translate = translate_rsr, 3878 .test_ill = test_ill_rsr, 3879 .par = (const uint32_t[]){MR + 1}, 3880 .windowed_register_op = 0x1, 3881 }, { 3882 .name = "rsr.m2", 3883 .translate = translate_rsr, 3884 .test_ill = test_ill_rsr, 3885 .par = (const uint32_t[]){MR + 2}, 3886 .windowed_register_op = 0x1, 3887 }, { 3888 .name = "rsr.m3", 3889 .translate = translate_rsr, 3890 .test_ill = test_ill_rsr, 3891 .par = (const uint32_t[]){MR + 3}, 3892 .windowed_register_op = 0x1, 3893 }, { 3894 .name = "rsr.memctl", 3895 .translate = translate_rsr, 3896 .test_ill = test_ill_rsr, 3897 .par = (const uint32_t[]){MEMCTL}, 3898 .op_flags = XTENSA_OP_PRIVILEGED, 3899 .windowed_register_op = 0x1, 3900 }, { 3901 .name = "rsr.misc0", 3902 .translate = translate_rsr, 3903 .test_ill = test_ill_rsr, 3904 .par = (const uint32_t[]){MISC}, 3905 .op_flags = XTENSA_OP_PRIVILEGED, 3906 .windowed_register_op = 0x1, 3907 }, { 3908 .name = "rsr.misc1", 3909 .translate = translate_rsr, 3910 .test_ill = test_ill_rsr, 3911 .par = (const uint32_t[]){MISC + 1}, 3912 .op_flags = XTENSA_OP_PRIVILEGED, 3913 .windowed_register_op = 0x1, 3914 }, { 3915 .name = "rsr.misc2", 3916 .translate = translate_rsr, 3917 .test_ill = test_ill_rsr, 3918 .par = (const uint32_t[]){MISC + 2}, 3919 .op_flags = XTENSA_OP_PRIVILEGED, 3920 .windowed_register_op = 0x1, 3921 }, { 3922 .name = "rsr.misc3", 3923 .translate = translate_rsr, 3924 .test_ill = test_ill_rsr, 3925 .par = (const uint32_t[]){MISC + 3}, 3926 .op_flags = XTENSA_OP_PRIVILEGED, 3927 .windowed_register_op = 0x1, 3928 }, { 3929 .name = "rsr.prid", 3930 .translate = translate_rsr, 3931 .test_ill = test_ill_rsr, 3932 .par = (const uint32_t[]){PRID}, 3933 .op_flags = XTENSA_OP_PRIVILEGED, 3934 .windowed_register_op = 0x1, 3935 }, { 3936 .name = "rsr.ps", 3937 .translate = translate_rsr, 3938 .test_ill = test_ill_rsr, 3939 .par = (const uint32_t[]){PS}, 3940 .op_flags = XTENSA_OP_PRIVILEGED, 3941 .windowed_register_op = 0x1, 3942 }, { 3943 .name = "rsr.ptevaddr", 3944 .translate = translate_rsr, 3945 .test_ill = test_ill_rsr, 3946 .par = (const uint32_t[]){PTEVADDR}, 3947 .op_flags = XTENSA_OP_PRIVILEGED, 3948 .windowed_register_op = 0x1, 3949 }, { 3950 .name = "rsr.rasid", 3951 .translate = translate_rsr, 3952 .test_ill = test_ill_rsr, 3953 .par = (const uint32_t[]){RASID}, 3954 .op_flags = XTENSA_OP_PRIVILEGED, 3955 .windowed_register_op = 0x1, 3956 }, { 3957 .name = "rsr.sar", 3958 .translate = translate_rsr, 3959 .test_ill = test_ill_rsr, 3960 .par = (const uint32_t[]){SAR}, 3961 .windowed_register_op = 0x1, 3962 }, { 3963 .name = "rsr.scompare1", 3964 .translate = translate_rsr, 3965 .test_ill = test_ill_rsr, 3966 .par = (const uint32_t[]){SCOMPARE1}, 3967 .windowed_register_op = 0x1, 3968 }, { 3969 .name = "rsr.vecbase", 3970 .translate = translate_rsr, 3971 .test_ill = test_ill_rsr, 3972 .par = (const uint32_t[]){VECBASE}, 3973 .op_flags = XTENSA_OP_PRIVILEGED, 3974 .windowed_register_op = 0x1, 3975 }, { 3976 .name = "rsr.windowbase", 3977 .translate = translate_rsr, 3978 .test_ill = test_ill_rsr, 3979 .par = (const uint32_t[]){WINDOW_BASE}, 3980 .op_flags = XTENSA_OP_PRIVILEGED, 3981 .windowed_register_op = 0x1, 3982 }, { 3983 .name = "rsr.windowstart", 3984 .translate = translate_rsr, 3985 .test_ill = test_ill_rsr, 3986 .par = (const uint32_t[]){WINDOW_START}, 3987 .op_flags = XTENSA_OP_PRIVILEGED, 3988 .windowed_register_op = 0x1, 3989 }, { 3990 .name = "rsync", 3991 .translate = translate_nop, 3992 }, { 3993 .name = "rur.expstate", 3994 .translate = translate_rur, 3995 .par = (const uint32_t[]){EXPSTATE}, 3996 .windowed_register_op = 0x1, 3997 }, { 3998 .name = "rur.fcr", 3999 .translate = translate_rur, 4000 .par = (const uint32_t[]){FCR}, 4001 .windowed_register_op = 0x1, 4002 .coprocessor = 0x1, 4003 }, { 4004 .name = "rur.fsr", 4005 .translate = translate_rur, 4006 .par = (const uint32_t[]){FSR}, 4007 .windowed_register_op = 0x1, 4008 .coprocessor = 0x1, 4009 }, { 4010 .name = "rur.threadptr", 4011 .translate = translate_rur, 4012 .par = (const uint32_t[]){THREADPTR}, 4013 .windowed_register_op = 0x1, 4014 }, { 4015 .name = "s16i", 4016 .translate = translate_ldst, 4017 .par = (const uint32_t[]){MO_TEUW, false, true}, 4018 .windowed_register_op = 0x3, 4019 }, { 4020 .name = "s32c1i", 4021 .translate = translate_s32c1i, 4022 .windowed_register_op = 0x3, 4023 }, { 4024 .name = "s32e", 4025 .translate = translate_s32e, 4026 .op_flags = XTENSA_OP_PRIVILEGED, 4027 .windowed_register_op = 0x3, 4028 }, { 4029 .name = "s32i", 4030 .translate = translate_ldst, 4031 .par = (const uint32_t[]){MO_TEUL, false, true}, 4032 .windowed_register_op = 0x3, 4033 }, { 4034 .name = "s32i.n", 4035 .translate = translate_ldst, 4036 .par = (const uint32_t[]){MO_TEUL, false, true}, 4037 .windowed_register_op = 0x3, 4038 }, { 4039 .name = "s32nb", 4040 .translate = translate_ldst, 4041 .par = (const uint32_t[]){MO_TEUL, false, true}, 4042 .windowed_register_op = 0x3, 4043 }, { 4044 .name = "s32ri", 4045 .translate = translate_ldst, 4046 .par = (const uint32_t[]){MO_TEUL, true, true}, 4047 .windowed_register_op = 0x3, 4048 }, { 4049 .name = "s8i", 4050 .translate = translate_ldst, 4051 .par = (const uint32_t[]){MO_UB, false, true}, 4052 .windowed_register_op = 0x3, 4053 }, { 4054 .name = "salt", 4055 .translate = translate_salt, 4056 .par = (const uint32_t[]){TCG_COND_LT}, 4057 .windowed_register_op = 0x7, 4058 }, { 4059 .name = "saltu", 4060 .translate = translate_salt, 4061 .par = (const uint32_t[]){TCG_COND_LTU}, 4062 .windowed_register_op = 0x7, 4063 }, { 4064 .name = "setb_expstate", 4065 .translate = translate_setb_expstate, 4066 }, { 4067 .name = "sext", 4068 .translate = translate_sext, 4069 .windowed_register_op = 0x3, 4070 }, { 4071 .name = "simcall", 4072 .translate = translate_simcall, 4073 .test_ill = test_ill_simcall, 4074 .op_flags = XTENSA_OP_PRIVILEGED, 4075 }, { 4076 .name = "sll", 4077 .translate = translate_sll, 4078 .windowed_register_op = 0x3, 4079 }, { 4080 .name = "slli", 4081 .translate = translate_slli, 4082 .windowed_register_op = 0x3, 4083 }, { 4084 .name = "sra", 4085 .translate = translate_sra, 4086 .windowed_register_op = 0x3, 4087 }, { 4088 .name = "srai", 4089 .translate = translate_srai, 4090 .windowed_register_op = 0x3, 4091 }, { 4092 .name = "src", 4093 .translate = translate_src, 4094 .windowed_register_op = 0x7, 4095 }, { 4096 .name = "srl", 4097 .translate = translate_srl, 4098 .windowed_register_op = 0x3, 4099 }, { 4100 .name = "srli", 4101 .translate = translate_srli, 4102 .windowed_register_op = 0x3, 4103 }, { 4104 .name = "ssa8b", 4105 .translate = translate_ssa8b, 4106 .windowed_register_op = 0x1, 4107 }, { 4108 .name = "ssa8l", 4109 .translate = translate_ssa8l, 4110 .windowed_register_op = 0x1, 4111 }, { 4112 .name = "ssai", 4113 .translate = translate_ssai, 4114 }, { 4115 .name = "ssl", 4116 .translate = translate_ssl, 4117 .windowed_register_op = 0x1, 4118 }, { 4119 .name = "ssr", 4120 .translate = translate_ssr, 4121 .windowed_register_op = 0x1, 4122 }, { 4123 .name = "sub", 4124 .translate = translate_sub, 4125 .windowed_register_op = 0x7, 4126 }, { 4127 .name = "subx2", 4128 .translate = translate_subx, 4129 .par = (const uint32_t[]){1}, 4130 .windowed_register_op = 0x7, 4131 }, { 4132 .name = "subx4", 4133 .translate = translate_subx, 4134 .par = (const uint32_t[]){2}, 4135 .windowed_register_op = 0x7, 4136 }, { 4137 .name = "subx8", 4138 .translate = translate_subx, 4139 .par = (const uint32_t[]){3}, 4140 .windowed_register_op = 0x7, 4141 }, { 4142 .name = "syscall", 4143 .op_flags = XTENSA_OP_SYSCALL, 4144 }, { 4145 .name = "umul.aa.hh", 4146 .translate = translate_mac16, 4147 .par = (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_HH, 0}, 4148 .windowed_register_op = 0x3, 4149 }, { 4150 .name = "umul.aa.hl", 4151 .translate = translate_mac16, 4152 .par = (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_HL, 0}, 4153 .windowed_register_op = 0x3, 4154 }, { 4155 .name = "umul.aa.lh", 4156 .translate = translate_mac16, 4157 .par = (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_LH, 0}, 4158 .windowed_register_op = 0x3, 4159 }, { 4160 .name = "umul.aa.ll", 4161 .translate = translate_mac16, 4162 .par = (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_LL, 0}, 4163 .windowed_register_op = 0x3, 4164 }, { 4165 .name = "waiti", 4166 .translate = translate_waiti, 4167 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, 4168 }, { 4169 .name = "wdtlb", 4170 .translate = translate_wtlb, 4171 .par = (const uint32_t[]){true}, 4172 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, 4173 .windowed_register_op = 0x3, 4174 }, { 4175 .name = "wer", 4176 .translate = translate_wer, 4177 .op_flags = XTENSA_OP_PRIVILEGED, 4178 .windowed_register_op = 0x3, 4179 }, { 4180 .name = "witlb", 4181 .translate = translate_wtlb, 4182 .par = (const uint32_t[]){false}, 4183 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, 4184 .windowed_register_op = 0x3, 4185 }, { 4186 .name = "wrmsk_expstate", 4187 .translate = translate_wrmsk_expstate, 4188 .windowed_register_op = 0x3, 4189 }, { 4190 .name = "wsr.176", 4191 .translate = translate_wsr, 4192 .test_ill = test_ill_wsr, 4193 .par = (const uint32_t[]){176}, 4194 .op_flags = XTENSA_OP_PRIVILEGED, 4195 .windowed_register_op = 0x1, 4196 }, { 4197 .name = "wsr.208", 4198 .translate = translate_wsr, 4199 .test_ill = test_ill_wsr, 4200 .par = (const uint32_t[]){208}, 4201 .op_flags = XTENSA_OP_PRIVILEGED, 4202 .windowed_register_op = 0x1, 4203 }, { 4204 .name = "wsr.acchi", 4205 .translate = translate_wsr, 4206 .test_ill = test_ill_wsr, 4207 .par = (const uint32_t[]){ACCHI}, 4208 .windowed_register_op = 0x1, 4209 }, { 4210 .name = "wsr.acclo", 4211 .translate = translate_wsr, 4212 .test_ill = test_ill_wsr, 4213 .par = (const uint32_t[]){ACCLO}, 4214 .windowed_register_op = 0x1, 4215 }, { 4216 .name = "wsr.atomctl", 4217 .translate = translate_wsr, 4218 .test_ill = test_ill_wsr, 4219 .par = (const uint32_t[]){ATOMCTL}, 4220 .op_flags = XTENSA_OP_PRIVILEGED, 4221 .windowed_register_op = 0x1, 4222 }, { 4223 .name = "wsr.br", 4224 .translate = translate_wsr, 4225 .test_ill = test_ill_wsr, 4226 .par = (const uint32_t[]){BR}, 4227 .windowed_register_op = 0x1, 4228 }, { 4229 .name = "wsr.cacheattr", 4230 .translate = translate_wsr, 4231 .test_ill = test_ill_wsr, 4232 .par = (const uint32_t[]){CACHEATTR}, 4233 .op_flags = XTENSA_OP_PRIVILEGED, 4234 .windowed_register_op = 0x1, 4235 }, { 4236 .name = "wsr.ccompare0", 4237 .translate = translate_wsr, 4238 .test_ill = test_ill_wsr, 4239 .par = (const uint32_t[]){CCOMPARE}, 4240 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, 4241 .windowed_register_op = 0x1, 4242 }, { 4243 .name = "wsr.ccompare1", 4244 .translate = translate_wsr, 4245 .test_ill = test_ill_wsr, 4246 .par = (const uint32_t[]){CCOMPARE + 1}, 4247 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, 4248 .windowed_register_op = 0x1, 4249 }, { 4250 .name = "wsr.ccompare2", 4251 .translate = translate_wsr, 4252 .test_ill = test_ill_wsr, 4253 .par = (const uint32_t[]){CCOMPARE + 2}, 4254 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, 4255 .windowed_register_op = 0x1, 4256 }, { 4257 .name = "wsr.ccount", 4258 .translate = translate_wsr, 4259 .test_ill = test_ill_wsr, 4260 .par = (const uint32_t[]){CCOUNT}, 4261 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, 4262 .windowed_register_op = 0x1, 4263 }, { 4264 .name = "wsr.configid0", 4265 .translate = translate_wsr, 4266 .test_ill = test_ill_wsr, 4267 .par = (const uint32_t[]){CONFIGID0}, 4268 .op_flags = XTENSA_OP_PRIVILEGED, 4269 .windowed_register_op = 0x1, 4270 }, { 4271 .name = "wsr.configid1", 4272 .translate = translate_wsr, 4273 .test_ill = test_ill_wsr, 4274 .par = (const uint32_t[]){CONFIGID1}, 4275 .op_flags = XTENSA_OP_PRIVILEGED, 4276 .windowed_register_op = 0x1, 4277 }, { 4278 .name = "wsr.cpenable", 4279 .translate = translate_wsr, 4280 .test_ill = test_ill_wsr, 4281 .par = (const uint32_t[]){CPENABLE}, 4282 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, 4283 .windowed_register_op = 0x1, 4284 }, { 4285 .name = "wsr.dbreaka0", 4286 .translate = translate_wsr, 4287 .test_ill = test_ill_wsr, 4288 .par = (const uint32_t[]){DBREAKA}, 4289 .op_flags = XTENSA_OP_PRIVILEGED, 4290 .windowed_register_op = 0x1, 4291 }, { 4292 .name = "wsr.dbreaka1", 4293 .translate = translate_wsr, 4294 .test_ill = test_ill_wsr, 4295 .par = (const uint32_t[]){DBREAKA + 1}, 4296 .op_flags = XTENSA_OP_PRIVILEGED, 4297 .windowed_register_op = 0x1, 4298 }, { 4299 .name = "wsr.dbreakc0", 4300 .translate = translate_wsr, 4301 .test_ill = test_ill_wsr, 4302 .par = (const uint32_t[]){DBREAKC}, 4303 .op_flags = XTENSA_OP_PRIVILEGED, 4304 .windowed_register_op = 0x1, 4305 }, { 4306 .name = "wsr.dbreakc1", 4307 .translate = translate_wsr, 4308 .test_ill = test_ill_wsr, 4309 .par = (const uint32_t[]){DBREAKC + 1}, 4310 .op_flags = XTENSA_OP_PRIVILEGED, 4311 .windowed_register_op = 0x1, 4312 }, { 4313 .name = "wsr.ddr", 4314 .translate = translate_wsr, 4315 .test_ill = test_ill_wsr, 4316 .par = (const uint32_t[]){DDR}, 4317 .op_flags = XTENSA_OP_PRIVILEGED, 4318 .windowed_register_op = 0x1, 4319 }, { 4320 .name = "wsr.debugcause", 4321 .translate = translate_wsr, 4322 .test_ill = test_ill_wsr, 4323 .par = (const uint32_t[]){DEBUGCAUSE}, 4324 .op_flags = XTENSA_OP_PRIVILEGED, 4325 .windowed_register_op = 0x1, 4326 }, { 4327 .name = "wsr.depc", 4328 .translate = translate_wsr, 4329 .test_ill = test_ill_wsr, 4330 .par = (const uint32_t[]){DEPC}, 4331 .op_flags = XTENSA_OP_PRIVILEGED, 4332 .windowed_register_op = 0x1, 4333 }, { 4334 .name = "wsr.dtlbcfg", 4335 .translate = translate_wsr, 4336 .test_ill = test_ill_wsr, 4337 .par = (const uint32_t[]){DTLBCFG}, 4338 .op_flags = XTENSA_OP_PRIVILEGED, 4339 .windowed_register_op = 0x1, 4340 }, { 4341 .name = "wsr.epc1", 4342 .translate = translate_wsr, 4343 .test_ill = test_ill_wsr, 4344 .par = (const uint32_t[]){EPC1}, 4345 .op_flags = XTENSA_OP_PRIVILEGED, 4346 .windowed_register_op = 0x1, 4347 }, { 4348 .name = "wsr.epc2", 4349 .translate = translate_wsr, 4350 .test_ill = test_ill_wsr, 4351 .par = (const uint32_t[]){EPC1 + 1}, 4352 .op_flags = XTENSA_OP_PRIVILEGED, 4353 .windowed_register_op = 0x1, 4354 }, { 4355 .name = "wsr.epc3", 4356 .translate = translate_wsr, 4357 .test_ill = test_ill_wsr, 4358 .par = (const uint32_t[]){EPC1 + 2}, 4359 .op_flags = XTENSA_OP_PRIVILEGED, 4360 .windowed_register_op = 0x1, 4361 }, { 4362 .name = "wsr.epc4", 4363 .translate = translate_wsr, 4364 .test_ill = test_ill_wsr, 4365 .par = (const uint32_t[]){EPC1 + 3}, 4366 .op_flags = XTENSA_OP_PRIVILEGED, 4367 .windowed_register_op = 0x1, 4368 }, { 4369 .name = "wsr.epc5", 4370 .translate = translate_wsr, 4371 .test_ill = test_ill_wsr, 4372 .par = (const uint32_t[]){EPC1 + 4}, 4373 .op_flags = XTENSA_OP_PRIVILEGED, 4374 .windowed_register_op = 0x1, 4375 }, { 4376 .name = "wsr.epc6", 4377 .translate = translate_wsr, 4378 .test_ill = test_ill_wsr, 4379 .par = (const uint32_t[]){EPC1 + 5}, 4380 .op_flags = XTENSA_OP_PRIVILEGED, 4381 .windowed_register_op = 0x1, 4382 }, { 4383 .name = "wsr.epc7", 4384 .translate = translate_wsr, 4385 .test_ill = test_ill_wsr, 4386 .par = (const uint32_t[]){EPC1 + 6}, 4387 .op_flags = XTENSA_OP_PRIVILEGED, 4388 .windowed_register_op = 0x1, 4389 }, { 4390 .name = "wsr.eps2", 4391 .translate = translate_wsr, 4392 .test_ill = test_ill_wsr, 4393 .par = (const uint32_t[]){EPS2}, 4394 .op_flags = XTENSA_OP_PRIVILEGED, 4395 .windowed_register_op = 0x1, 4396 }, { 4397 .name = "wsr.eps3", 4398 .translate = translate_wsr, 4399 .test_ill = test_ill_wsr, 4400 .par = (const uint32_t[]){EPS2 + 1}, 4401 .op_flags = XTENSA_OP_PRIVILEGED, 4402 .windowed_register_op = 0x1, 4403 }, { 4404 .name = "wsr.eps4", 4405 .translate = translate_wsr, 4406 .test_ill = test_ill_wsr, 4407 .par = (const uint32_t[]){EPS2 + 2}, 4408 .op_flags = XTENSA_OP_PRIVILEGED, 4409 .windowed_register_op = 0x1, 4410 }, { 4411 .name = "wsr.eps5", 4412 .translate = translate_wsr, 4413 .test_ill = test_ill_wsr, 4414 .par = (const uint32_t[]){EPS2 + 3}, 4415 .op_flags = XTENSA_OP_PRIVILEGED, 4416 .windowed_register_op = 0x1, 4417 }, { 4418 .name = "wsr.eps6", 4419 .translate = translate_wsr, 4420 .test_ill = test_ill_wsr, 4421 .par = (const uint32_t[]){EPS2 + 4}, 4422 .op_flags = XTENSA_OP_PRIVILEGED, 4423 .windowed_register_op = 0x1, 4424 }, { 4425 .name = "wsr.eps7", 4426 .translate = translate_wsr, 4427 .test_ill = test_ill_wsr, 4428 .par = (const uint32_t[]){EPS2 + 5}, 4429 .op_flags = XTENSA_OP_PRIVILEGED, 4430 .windowed_register_op = 0x1, 4431 }, { 4432 .name = "wsr.exccause", 4433 .translate = translate_wsr, 4434 .test_ill = test_ill_wsr, 4435 .par = (const uint32_t[]){EXCCAUSE}, 4436 .op_flags = XTENSA_OP_PRIVILEGED, 4437 .windowed_register_op = 0x1, 4438 }, { 4439 .name = "wsr.excsave1", 4440 .translate = translate_wsr, 4441 .test_ill = test_ill_wsr, 4442 .par = (const uint32_t[]){EXCSAVE1}, 4443 .op_flags = XTENSA_OP_PRIVILEGED, 4444 .windowed_register_op = 0x1, 4445 }, { 4446 .name = "wsr.excsave2", 4447 .translate = translate_wsr, 4448 .test_ill = test_ill_wsr, 4449 .par = (const uint32_t[]){EXCSAVE1 + 1}, 4450 .op_flags = XTENSA_OP_PRIVILEGED, 4451 .windowed_register_op = 0x1, 4452 }, { 4453 .name = "wsr.excsave3", 4454 .translate = translate_wsr, 4455 .test_ill = test_ill_wsr, 4456 .par = (const uint32_t[]){EXCSAVE1 + 2}, 4457 .op_flags = XTENSA_OP_PRIVILEGED, 4458 .windowed_register_op = 0x1, 4459 }, { 4460 .name = "wsr.excsave4", 4461 .translate = translate_wsr, 4462 .test_ill = test_ill_wsr, 4463 .par = (const uint32_t[]){EXCSAVE1 + 3}, 4464 .op_flags = XTENSA_OP_PRIVILEGED, 4465 .windowed_register_op = 0x1, 4466 }, { 4467 .name = "wsr.excsave5", 4468 .translate = translate_wsr, 4469 .test_ill = test_ill_wsr, 4470 .par = (const uint32_t[]){EXCSAVE1 + 4}, 4471 .op_flags = XTENSA_OP_PRIVILEGED, 4472 .windowed_register_op = 0x1, 4473 }, { 4474 .name = "wsr.excsave6", 4475 .translate = translate_wsr, 4476 .test_ill = test_ill_wsr, 4477 .par = (const uint32_t[]){EXCSAVE1 + 5}, 4478 .op_flags = XTENSA_OP_PRIVILEGED, 4479 .windowed_register_op = 0x1, 4480 }, { 4481 .name = "wsr.excsave7", 4482 .translate = translate_wsr, 4483 .test_ill = test_ill_wsr, 4484 .par = (const uint32_t[]){EXCSAVE1 + 6}, 4485 .op_flags = XTENSA_OP_PRIVILEGED, 4486 .windowed_register_op = 0x1, 4487 }, { 4488 .name = "wsr.excvaddr", 4489 .translate = translate_wsr, 4490 .test_ill = test_ill_wsr, 4491 .par = (const uint32_t[]){EXCVADDR}, 4492 .op_flags = XTENSA_OP_PRIVILEGED, 4493 .windowed_register_op = 0x1, 4494 }, { 4495 .name = "wsr.ibreaka0", 4496 .translate = translate_wsr, 4497 .test_ill = test_ill_wsr, 4498 .par = (const uint32_t[]){IBREAKA}, 4499 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, 4500 .windowed_register_op = 0x1, 4501 }, { 4502 .name = "wsr.ibreaka1", 4503 .translate = translate_wsr, 4504 .test_ill = test_ill_wsr, 4505 .par = (const uint32_t[]){IBREAKA + 1}, 4506 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, 4507 .windowed_register_op = 0x1, 4508 }, { 4509 .name = "wsr.ibreakenable", 4510 .translate = translate_wsr, 4511 .test_ill = test_ill_wsr, 4512 .par = (const uint32_t[]){IBREAKENABLE}, 4513 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, 4514 .windowed_register_op = 0x1, 4515 }, { 4516 .name = "wsr.icount", 4517 .translate = translate_wsr, 4518 .test_ill = test_ill_wsr, 4519 .par = (const uint32_t[]){ICOUNT}, 4520 .op_flags = XTENSA_OP_PRIVILEGED, 4521 .windowed_register_op = 0x1, 4522 }, { 4523 .name = "wsr.icountlevel", 4524 .translate = translate_wsr, 4525 .test_ill = test_ill_wsr, 4526 .par = (const uint32_t[]){ICOUNTLEVEL}, 4527 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, 4528 .windowed_register_op = 0x1, 4529 }, { 4530 .name = "wsr.intclear", 4531 .translate = translate_wsr, 4532 .test_ill = test_ill_wsr, 4533 .par = (const uint32_t[]){INTCLEAR}, 4534 .op_flags = 4535 XTENSA_OP_PRIVILEGED | 4536 XTENSA_OP_EXIT_TB_0 | 4537 XTENSA_OP_CHECK_INTERRUPTS, 4538 .windowed_register_op = 0x1, 4539 }, { 4540 .name = "wsr.intenable", 4541 .translate = translate_wsr, 4542 .test_ill = test_ill_wsr, 4543 .par = (const uint32_t[]){INTENABLE}, 4544 .op_flags = 4545 XTENSA_OP_PRIVILEGED | 4546 XTENSA_OP_EXIT_TB_0 | 4547 XTENSA_OP_CHECK_INTERRUPTS, 4548 .windowed_register_op = 0x1, 4549 }, { 4550 .name = "wsr.interrupt", 4551 .translate = translate_wsr, 4552 .test_ill = test_ill_wsr, 4553 .par = (const uint32_t[]){INTSET}, 4554 .op_flags = 4555 XTENSA_OP_PRIVILEGED | 4556 XTENSA_OP_EXIT_TB_0 | 4557 XTENSA_OP_CHECK_INTERRUPTS, 4558 .windowed_register_op = 0x1, 4559 }, { 4560 .name = "wsr.intset", 4561 .translate = translate_wsr, 4562 .test_ill = test_ill_wsr, 4563 .par = (const uint32_t[]){INTSET}, 4564 .op_flags = 4565 XTENSA_OP_PRIVILEGED | 4566 XTENSA_OP_EXIT_TB_0 | 4567 XTENSA_OP_CHECK_INTERRUPTS, 4568 .windowed_register_op = 0x1, 4569 }, { 4570 .name = "wsr.itlbcfg", 4571 .translate = translate_wsr, 4572 .test_ill = test_ill_wsr, 4573 .par = (const uint32_t[]){ITLBCFG}, 4574 .op_flags = XTENSA_OP_PRIVILEGED, 4575 .windowed_register_op = 0x1, 4576 }, { 4577 .name = "wsr.lbeg", 4578 .translate = translate_wsr, 4579 .test_ill = test_ill_wsr, 4580 .par = (const uint32_t[]){LBEG}, 4581 .op_flags = XTENSA_OP_EXIT_TB_M1, 4582 .windowed_register_op = 0x1, 4583 }, { 4584 .name = "wsr.lcount", 4585 .translate = translate_wsr, 4586 .test_ill = test_ill_wsr, 4587 .par = (const uint32_t[]){LCOUNT}, 4588 .windowed_register_op = 0x1, 4589 }, { 4590 .name = "wsr.lend", 4591 .translate = translate_wsr, 4592 .test_ill = test_ill_wsr, 4593 .par = (const uint32_t[]){LEND}, 4594 .op_flags = XTENSA_OP_EXIT_TB_M1, 4595 .windowed_register_op = 0x1, 4596 }, { 4597 .name = "wsr.litbase", 4598 .translate = translate_wsr, 4599 .test_ill = test_ill_wsr, 4600 .par = (const uint32_t[]){LITBASE}, 4601 .op_flags = XTENSA_OP_EXIT_TB_M1, 4602 .windowed_register_op = 0x1, 4603 }, { 4604 .name = "wsr.m0", 4605 .translate = translate_wsr, 4606 .test_ill = test_ill_wsr, 4607 .par = (const uint32_t[]){MR}, 4608 .windowed_register_op = 0x1, 4609 }, { 4610 .name = "wsr.m1", 4611 .translate = translate_wsr, 4612 .test_ill = test_ill_wsr, 4613 .par = (const uint32_t[]){MR + 1}, 4614 .windowed_register_op = 0x1, 4615 }, { 4616 .name = "wsr.m2", 4617 .translate = translate_wsr, 4618 .test_ill = test_ill_wsr, 4619 .par = (const uint32_t[]){MR + 2}, 4620 .windowed_register_op = 0x1, 4621 }, { 4622 .name = "wsr.m3", 4623 .translate = translate_wsr, 4624 .test_ill = test_ill_wsr, 4625 .par = (const uint32_t[]){MR + 3}, 4626 .windowed_register_op = 0x1, 4627 }, { 4628 .name = "wsr.memctl", 4629 .translate = translate_wsr, 4630 .test_ill = test_ill_wsr, 4631 .par = (const uint32_t[]){MEMCTL}, 4632 .op_flags = XTENSA_OP_PRIVILEGED, 4633 .windowed_register_op = 0x1, 4634 }, { 4635 .name = "wsr.misc0", 4636 .translate = translate_wsr, 4637 .test_ill = test_ill_wsr, 4638 .par = (const uint32_t[]){MISC}, 4639 .op_flags = XTENSA_OP_PRIVILEGED, 4640 .windowed_register_op = 0x1, 4641 }, { 4642 .name = "wsr.misc1", 4643 .translate = translate_wsr, 4644 .test_ill = test_ill_wsr, 4645 .par = (const uint32_t[]){MISC + 1}, 4646 .op_flags = XTENSA_OP_PRIVILEGED, 4647 .windowed_register_op = 0x1, 4648 }, { 4649 .name = "wsr.misc2", 4650 .translate = translate_wsr, 4651 .test_ill = test_ill_wsr, 4652 .par = (const uint32_t[]){MISC + 2}, 4653 .op_flags = XTENSA_OP_PRIVILEGED, 4654 .windowed_register_op = 0x1, 4655 }, { 4656 .name = "wsr.misc3", 4657 .translate = translate_wsr, 4658 .test_ill = test_ill_wsr, 4659 .par = (const uint32_t[]){MISC + 3}, 4660 .op_flags = XTENSA_OP_PRIVILEGED, 4661 .windowed_register_op = 0x1, 4662 }, { 4663 .name = "wsr.mmid", 4664 .translate = translate_wsr, 4665 .test_ill = test_ill_wsr, 4666 .par = (const uint32_t[]){MMID}, 4667 .op_flags = XTENSA_OP_PRIVILEGED, 4668 .windowed_register_op = 0x1, 4669 }, { 4670 .name = "wsr.prid", 4671 .translate = translate_wsr, 4672 .test_ill = test_ill_wsr, 4673 .par = (const uint32_t[]){PRID}, 4674 .op_flags = XTENSA_OP_PRIVILEGED, 4675 .windowed_register_op = 0x1, 4676 }, { 4677 .name = "wsr.ps", 4678 .translate = translate_wsr, 4679 .test_ill = test_ill_wsr, 4680 .par = (const uint32_t[]){PS}, 4681 .op_flags = 4682 XTENSA_OP_PRIVILEGED | 4683 XTENSA_OP_EXIT_TB_M1 | 4684 XTENSA_OP_CHECK_INTERRUPTS, 4685 .windowed_register_op = 0x1, 4686 }, { 4687 .name = "wsr.ptevaddr", 4688 .translate = translate_wsr, 4689 .test_ill = test_ill_wsr, 4690 .par = (const uint32_t[]){PTEVADDR}, 4691 .op_flags = XTENSA_OP_PRIVILEGED, 4692 .windowed_register_op = 0x1, 4693 }, { 4694 .name = "wsr.rasid", 4695 .translate = translate_wsr, 4696 .test_ill = test_ill_wsr, 4697 .par = (const uint32_t[]){RASID}, 4698 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, 4699 .windowed_register_op = 0x1, 4700 }, { 4701 .name = "wsr.sar", 4702 .translate = translate_wsr, 4703 .test_ill = test_ill_wsr, 4704 .par = (const uint32_t[]){SAR}, 4705 .windowed_register_op = 0x1, 4706 }, { 4707 .name = "wsr.scompare1", 4708 .translate = translate_wsr, 4709 .test_ill = test_ill_wsr, 4710 .par = (const uint32_t[]){SCOMPARE1}, 4711 .windowed_register_op = 0x1, 4712 }, { 4713 .name = "wsr.vecbase", 4714 .translate = translate_wsr, 4715 .test_ill = test_ill_wsr, 4716 .par = (const uint32_t[]){VECBASE}, 4717 .op_flags = XTENSA_OP_PRIVILEGED, 4718 .windowed_register_op = 0x1, 4719 }, { 4720 .name = "wsr.windowbase", 4721 .translate = translate_wsr, 4722 .test_ill = test_ill_wsr, 4723 .par = (const uint32_t[]){WINDOW_BASE}, 4724 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, 4725 .windowed_register_op = 0x1, 4726 }, { 4727 .name = "wsr.windowstart", 4728 .translate = translate_wsr, 4729 .test_ill = test_ill_wsr, 4730 .par = (const uint32_t[]){WINDOW_START}, 4731 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, 4732 .windowed_register_op = 0x1, 4733 }, { 4734 .name = "wur.expstate", 4735 .translate = translate_wur, 4736 .par = (const uint32_t[]){EXPSTATE}, 4737 .windowed_register_op = 0x1, 4738 }, { 4739 .name = "wur.fcr", 4740 .translate = translate_wur, 4741 .par = (const uint32_t[]){FCR}, 4742 .windowed_register_op = 0x1, 4743 .coprocessor = 0x1, 4744 }, { 4745 .name = "wur.fsr", 4746 .translate = translate_wur, 4747 .par = (const uint32_t[]){FSR}, 4748 .windowed_register_op = 0x1, 4749 .coprocessor = 0x1, 4750 }, { 4751 .name = "wur.threadptr", 4752 .translate = translate_wur, 4753 .par = (const uint32_t[]){THREADPTR}, 4754 .windowed_register_op = 0x1, 4755 }, { 4756 .name = "xor", 4757 .translate = translate_xor, 4758 .windowed_register_op = 0x7, 4759 }, { 4760 .name = "xorb", 4761 .translate = translate_boolean, 4762 .par = (const uint32_t[]){BOOLEAN_XOR}, 4763 }, { 4764 .name = "xsr.176", 4765 .translate = translate_xsr, 4766 .test_ill = test_ill_xsr, 4767 .par = (const uint32_t[]){176}, 4768 .op_flags = XTENSA_OP_PRIVILEGED, 4769 .windowed_register_op = 0x1, 4770 }, { 4771 .name = "xsr.208", 4772 .translate = translate_xsr, 4773 .test_ill = test_ill_xsr, 4774 .par = (const uint32_t[]){208}, 4775 .op_flags = XTENSA_OP_PRIVILEGED, 4776 .windowed_register_op = 0x1, 4777 }, { 4778 .name = "xsr.acchi", 4779 .translate = translate_xsr, 4780 .test_ill = test_ill_xsr, 4781 .par = (const uint32_t[]){ACCHI}, 4782 .windowed_register_op = 0x1, 4783 }, { 4784 .name = "xsr.acclo", 4785 .translate = translate_xsr, 4786 .test_ill = test_ill_xsr, 4787 .par = (const uint32_t[]){ACCLO}, 4788 .windowed_register_op = 0x1, 4789 }, { 4790 .name = "xsr.atomctl", 4791 .translate = translate_xsr, 4792 .test_ill = test_ill_xsr, 4793 .par = (const uint32_t[]){ATOMCTL}, 4794 .op_flags = XTENSA_OP_PRIVILEGED, 4795 .windowed_register_op = 0x1, 4796 }, { 4797 .name = "xsr.br", 4798 .translate = translate_xsr, 4799 .test_ill = test_ill_xsr, 4800 .par = (const uint32_t[]){BR}, 4801 .windowed_register_op = 0x1, 4802 }, { 4803 .name = "xsr.cacheattr", 4804 .translate = translate_xsr, 4805 .test_ill = test_ill_xsr, 4806 .par = (const uint32_t[]){CACHEATTR}, 4807 .op_flags = XTENSA_OP_PRIVILEGED, 4808 .windowed_register_op = 0x1, 4809 }, { 4810 .name = "xsr.ccompare0", 4811 .translate = translate_xsr, 4812 .test_ill = test_ill_xsr, 4813 .par = (const uint32_t[]){CCOMPARE}, 4814 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, 4815 .windowed_register_op = 0x1, 4816 }, { 4817 .name = "xsr.ccompare1", 4818 .translate = translate_xsr, 4819 .test_ill = test_ill_xsr, 4820 .par = (const uint32_t[]){CCOMPARE + 1}, 4821 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, 4822 .windowed_register_op = 0x1, 4823 }, { 4824 .name = "xsr.ccompare2", 4825 .translate = translate_xsr, 4826 .test_ill = test_ill_xsr, 4827 .par = (const uint32_t[]){CCOMPARE + 2}, 4828 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, 4829 .windowed_register_op = 0x1, 4830 }, { 4831 .name = "xsr.ccount", 4832 .translate = translate_xsr, 4833 .test_ill = test_ill_xsr, 4834 .par = (const uint32_t[]){CCOUNT}, 4835 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, 4836 .windowed_register_op = 0x1, 4837 }, { 4838 .name = "xsr.configid0", 4839 .translate = translate_xsr, 4840 .test_ill = test_ill_xsr, 4841 .par = (const uint32_t[]){CONFIGID0}, 4842 .op_flags = XTENSA_OP_PRIVILEGED, 4843 .windowed_register_op = 0x1, 4844 }, { 4845 .name = "xsr.configid1", 4846 .translate = translate_xsr, 4847 .test_ill = test_ill_xsr, 4848 .par = (const uint32_t[]){CONFIGID1}, 4849 .op_flags = XTENSA_OP_PRIVILEGED, 4850 .windowed_register_op = 0x1, 4851 }, { 4852 .name = "xsr.cpenable", 4853 .translate = translate_xsr, 4854 .test_ill = test_ill_xsr, 4855 .par = (const uint32_t[]){CPENABLE}, 4856 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, 4857 .windowed_register_op = 0x1, 4858 }, { 4859 .name = "xsr.dbreaka0", 4860 .translate = translate_xsr, 4861 .test_ill = test_ill_xsr, 4862 .par = (const uint32_t[]){DBREAKA}, 4863 .op_flags = XTENSA_OP_PRIVILEGED, 4864 .windowed_register_op = 0x1, 4865 }, { 4866 .name = "xsr.dbreaka1", 4867 .translate = translate_xsr, 4868 .test_ill = test_ill_xsr, 4869 .par = (const uint32_t[]){DBREAKA + 1}, 4870 .op_flags = XTENSA_OP_PRIVILEGED, 4871 .windowed_register_op = 0x1, 4872 }, { 4873 .name = "xsr.dbreakc0", 4874 .translate = translate_xsr, 4875 .test_ill = test_ill_xsr, 4876 .par = (const uint32_t[]){DBREAKC}, 4877 .op_flags = XTENSA_OP_PRIVILEGED, 4878 .windowed_register_op = 0x1, 4879 }, { 4880 .name = "xsr.dbreakc1", 4881 .translate = translate_xsr, 4882 .test_ill = test_ill_xsr, 4883 .par = (const uint32_t[]){DBREAKC + 1}, 4884 .op_flags = XTENSA_OP_PRIVILEGED, 4885 .windowed_register_op = 0x1, 4886 }, { 4887 .name = "xsr.ddr", 4888 .translate = translate_xsr, 4889 .test_ill = test_ill_xsr, 4890 .par = (const uint32_t[]){DDR}, 4891 .op_flags = XTENSA_OP_PRIVILEGED, 4892 .windowed_register_op = 0x1, 4893 }, { 4894 .name = "xsr.debugcause", 4895 .translate = translate_xsr, 4896 .test_ill = test_ill_xsr, 4897 .par = (const uint32_t[]){DEBUGCAUSE}, 4898 .op_flags = XTENSA_OP_PRIVILEGED, 4899 .windowed_register_op = 0x1, 4900 }, { 4901 .name = "xsr.depc", 4902 .translate = translate_xsr, 4903 .test_ill = test_ill_xsr, 4904 .par = (const uint32_t[]){DEPC}, 4905 .op_flags = XTENSA_OP_PRIVILEGED, 4906 .windowed_register_op = 0x1, 4907 }, { 4908 .name = "xsr.dtlbcfg", 4909 .translate = translate_xsr, 4910 .test_ill = test_ill_xsr, 4911 .par = (const uint32_t[]){DTLBCFG}, 4912 .op_flags = XTENSA_OP_PRIVILEGED, 4913 .windowed_register_op = 0x1, 4914 }, { 4915 .name = "xsr.epc1", 4916 .translate = translate_xsr, 4917 .test_ill = test_ill_xsr, 4918 .par = (const uint32_t[]){EPC1}, 4919 .op_flags = XTENSA_OP_PRIVILEGED, 4920 .windowed_register_op = 0x1, 4921 }, { 4922 .name = "xsr.epc2", 4923 .translate = translate_xsr, 4924 .test_ill = test_ill_xsr, 4925 .par = (const uint32_t[]){EPC1 + 1}, 4926 .op_flags = XTENSA_OP_PRIVILEGED, 4927 .windowed_register_op = 0x1, 4928 }, { 4929 .name = "xsr.epc3", 4930 .translate = translate_xsr, 4931 .test_ill = test_ill_xsr, 4932 .par = (const uint32_t[]){EPC1 + 2}, 4933 .op_flags = XTENSA_OP_PRIVILEGED, 4934 .windowed_register_op = 0x1, 4935 }, { 4936 .name = "xsr.epc4", 4937 .translate = translate_xsr, 4938 .test_ill = test_ill_xsr, 4939 .par = (const uint32_t[]){EPC1 + 3}, 4940 .op_flags = XTENSA_OP_PRIVILEGED, 4941 .windowed_register_op = 0x1, 4942 }, { 4943 .name = "xsr.epc5", 4944 .translate = translate_xsr, 4945 .test_ill = test_ill_xsr, 4946 .par = (const uint32_t[]){EPC1 + 4}, 4947 .op_flags = XTENSA_OP_PRIVILEGED, 4948 .windowed_register_op = 0x1, 4949 }, { 4950 .name = "xsr.epc6", 4951 .translate = translate_xsr, 4952 .test_ill = test_ill_xsr, 4953 .par = (const uint32_t[]){EPC1 + 5}, 4954 .op_flags = XTENSA_OP_PRIVILEGED, 4955 .windowed_register_op = 0x1, 4956 }, { 4957 .name = "xsr.epc7", 4958 .translate = translate_xsr, 4959 .test_ill = test_ill_xsr, 4960 .par = (const uint32_t[]){EPC1 + 6}, 4961 .op_flags = XTENSA_OP_PRIVILEGED, 4962 .windowed_register_op = 0x1, 4963 }, { 4964 .name = "xsr.eps2", 4965 .translate = translate_xsr, 4966 .test_ill = test_ill_xsr, 4967 .par = (const uint32_t[]){EPS2}, 4968 .op_flags = XTENSA_OP_PRIVILEGED, 4969 .windowed_register_op = 0x1, 4970 }, { 4971 .name = "xsr.eps3", 4972 .translate = translate_xsr, 4973 .test_ill = test_ill_xsr, 4974 .par = (const uint32_t[]){EPS2 + 1}, 4975 .op_flags = XTENSA_OP_PRIVILEGED, 4976 .windowed_register_op = 0x1, 4977 }, { 4978 .name = "xsr.eps4", 4979 .translate = translate_xsr, 4980 .test_ill = test_ill_xsr, 4981 .par = (const uint32_t[]){EPS2 + 2}, 4982 .op_flags = XTENSA_OP_PRIVILEGED, 4983 .windowed_register_op = 0x1, 4984 }, { 4985 .name = "xsr.eps5", 4986 .translate = translate_xsr, 4987 .test_ill = test_ill_xsr, 4988 .par = (const uint32_t[]){EPS2 + 3}, 4989 .op_flags = XTENSA_OP_PRIVILEGED, 4990 .windowed_register_op = 0x1, 4991 }, { 4992 .name = "xsr.eps6", 4993 .translate = translate_xsr, 4994 .test_ill = test_ill_xsr, 4995 .par = (const uint32_t[]){EPS2 + 4}, 4996 .op_flags = XTENSA_OP_PRIVILEGED, 4997 .windowed_register_op = 0x1, 4998 }, { 4999 .name = "xsr.eps7", 5000 .translate = translate_xsr, 5001 .test_ill = test_ill_xsr, 5002 .par = (const uint32_t[]){EPS2 + 5}, 5003 .op_flags = XTENSA_OP_PRIVILEGED, 5004 .windowed_register_op = 0x1, 5005 }, { 5006 .name = "xsr.exccause", 5007 .translate = translate_xsr, 5008 .test_ill = test_ill_xsr, 5009 .par = (const uint32_t[]){EXCCAUSE}, 5010 .op_flags = XTENSA_OP_PRIVILEGED, 5011 .windowed_register_op = 0x1, 5012 }, { 5013 .name = "xsr.excsave1", 5014 .translate = translate_xsr, 5015 .test_ill = test_ill_xsr, 5016 .par = (const uint32_t[]){EXCSAVE1}, 5017 .op_flags = XTENSA_OP_PRIVILEGED, 5018 .windowed_register_op = 0x1, 5019 }, { 5020 .name = "xsr.excsave2", 5021 .translate = translate_xsr, 5022 .test_ill = test_ill_xsr, 5023 .par = (const uint32_t[]){EXCSAVE1 + 1}, 5024 .op_flags = XTENSA_OP_PRIVILEGED, 5025 .windowed_register_op = 0x1, 5026 }, { 5027 .name = "xsr.excsave3", 5028 .translate = translate_xsr, 5029 .test_ill = test_ill_xsr, 5030 .par = (const uint32_t[]){EXCSAVE1 + 2}, 5031 .op_flags = XTENSA_OP_PRIVILEGED, 5032 .windowed_register_op = 0x1, 5033 }, { 5034 .name = "xsr.excsave4", 5035 .translate = translate_xsr, 5036 .test_ill = test_ill_xsr, 5037 .par = (const uint32_t[]){EXCSAVE1 + 3}, 5038 .op_flags = XTENSA_OP_PRIVILEGED, 5039 .windowed_register_op = 0x1, 5040 }, { 5041 .name = "xsr.excsave5", 5042 .translate = translate_xsr, 5043 .test_ill = test_ill_xsr, 5044 .par = (const uint32_t[]){EXCSAVE1 + 4}, 5045 .op_flags = XTENSA_OP_PRIVILEGED, 5046 .windowed_register_op = 0x1, 5047 }, { 5048 .name = "xsr.excsave6", 5049 .translate = translate_xsr, 5050 .test_ill = test_ill_xsr, 5051 .par = (const uint32_t[]){EXCSAVE1 + 5}, 5052 .op_flags = XTENSA_OP_PRIVILEGED, 5053 .windowed_register_op = 0x1, 5054 }, { 5055 .name = "xsr.excsave7", 5056 .translate = translate_xsr, 5057 .test_ill = test_ill_xsr, 5058 .par = (const uint32_t[]){EXCSAVE1 + 6}, 5059 .op_flags = XTENSA_OP_PRIVILEGED, 5060 .windowed_register_op = 0x1, 5061 }, { 5062 .name = "xsr.excvaddr", 5063 .translate = translate_xsr, 5064 .test_ill = test_ill_xsr, 5065 .par = (const uint32_t[]){EXCVADDR}, 5066 .op_flags = XTENSA_OP_PRIVILEGED, 5067 .windowed_register_op = 0x1, 5068 }, { 5069 .name = "xsr.ibreaka0", 5070 .translate = translate_xsr, 5071 .test_ill = test_ill_xsr, 5072 .par = (const uint32_t[]){IBREAKA}, 5073 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, 5074 .windowed_register_op = 0x1, 5075 }, { 5076 .name = "xsr.ibreaka1", 5077 .translate = translate_xsr, 5078 .test_ill = test_ill_xsr, 5079 .par = (const uint32_t[]){IBREAKA + 1}, 5080 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, 5081 .windowed_register_op = 0x1, 5082 }, { 5083 .name = "xsr.ibreakenable", 5084 .translate = translate_xsr, 5085 .test_ill = test_ill_xsr, 5086 .par = (const uint32_t[]){IBREAKENABLE}, 5087 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, 5088 .windowed_register_op = 0x1, 5089 }, { 5090 .name = "xsr.icount", 5091 .translate = translate_xsr, 5092 .test_ill = test_ill_xsr, 5093 .par = (const uint32_t[]){ICOUNT}, 5094 .op_flags = XTENSA_OP_PRIVILEGED, 5095 .windowed_register_op = 0x1, 5096 }, { 5097 .name = "xsr.icountlevel", 5098 .translate = translate_xsr, 5099 .test_ill = test_ill_xsr, 5100 .par = (const uint32_t[]){ICOUNTLEVEL}, 5101 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, 5102 .windowed_register_op = 0x1, 5103 }, { 5104 .name = "xsr.intclear", 5105 .translate = translate_xsr, 5106 .test_ill = test_ill_xsr, 5107 .par = (const uint32_t[]){INTCLEAR}, 5108 .op_flags = 5109 XTENSA_OP_PRIVILEGED | 5110 XTENSA_OP_EXIT_TB_0 | 5111 XTENSA_OP_CHECK_INTERRUPTS, 5112 .windowed_register_op = 0x1, 5113 }, { 5114 .name = "xsr.intenable", 5115 .translate = translate_xsr, 5116 .test_ill = test_ill_xsr, 5117 .par = (const uint32_t[]){INTENABLE}, 5118 .op_flags = 5119 XTENSA_OP_PRIVILEGED | 5120 XTENSA_OP_EXIT_TB_0 | 5121 XTENSA_OP_CHECK_INTERRUPTS, 5122 .windowed_register_op = 0x1, 5123 }, { 5124 .name = "xsr.interrupt", 5125 .translate = translate_xsr, 5126 .test_ill = test_ill_xsr, 5127 .par = (const uint32_t[]){INTSET}, 5128 .op_flags = 5129 XTENSA_OP_PRIVILEGED | 5130 XTENSA_OP_EXIT_TB_0 | 5131 XTENSA_OP_CHECK_INTERRUPTS, 5132 .windowed_register_op = 0x1, 5133 }, { 5134 .name = "xsr.intset", 5135 .translate = translate_xsr, 5136 .test_ill = test_ill_xsr, 5137 .par = (const uint32_t[]){INTSET}, 5138 .op_flags = 5139 XTENSA_OP_PRIVILEGED | 5140 XTENSA_OP_EXIT_TB_0 | 5141 XTENSA_OP_CHECK_INTERRUPTS, 5142 .windowed_register_op = 0x1, 5143 }, { 5144 .name = "xsr.itlbcfg", 5145 .translate = translate_xsr, 5146 .test_ill = test_ill_xsr, 5147 .par = (const uint32_t[]){ITLBCFG}, 5148 .op_flags = XTENSA_OP_PRIVILEGED, 5149 .windowed_register_op = 0x1, 5150 }, { 5151 .name = "xsr.lbeg", 5152 .translate = translate_xsr, 5153 .test_ill = test_ill_xsr, 5154 .par = (const uint32_t[]){LBEG}, 5155 .op_flags = XTENSA_OP_EXIT_TB_M1, 5156 .windowed_register_op = 0x1, 5157 }, { 5158 .name = "xsr.lcount", 5159 .translate = translate_xsr, 5160 .test_ill = test_ill_xsr, 5161 .par = (const uint32_t[]){LCOUNT}, 5162 .windowed_register_op = 0x1, 5163 }, { 5164 .name = "xsr.lend", 5165 .translate = translate_xsr, 5166 .test_ill = test_ill_xsr, 5167 .par = (const uint32_t[]){LEND}, 5168 .op_flags = XTENSA_OP_EXIT_TB_M1, 5169 .windowed_register_op = 0x1, 5170 }, { 5171 .name = "xsr.litbase", 5172 .translate = translate_xsr, 5173 .test_ill = test_ill_xsr, 5174 .par = (const uint32_t[]){LITBASE}, 5175 .op_flags = XTENSA_OP_EXIT_TB_M1, 5176 .windowed_register_op = 0x1, 5177 }, { 5178 .name = "xsr.m0", 5179 .translate = translate_xsr, 5180 .test_ill = test_ill_xsr, 5181 .par = (const uint32_t[]){MR}, 5182 .windowed_register_op = 0x1, 5183 }, { 5184 .name = "xsr.m1", 5185 .translate = translate_xsr, 5186 .test_ill = test_ill_xsr, 5187 .par = (const uint32_t[]){MR + 1}, 5188 .windowed_register_op = 0x1, 5189 }, { 5190 .name = "xsr.m2", 5191 .translate = translate_xsr, 5192 .test_ill = test_ill_xsr, 5193 .par = (const uint32_t[]){MR + 2}, 5194 .windowed_register_op = 0x1, 5195 }, { 5196 .name = "xsr.m3", 5197 .translate = translate_xsr, 5198 .test_ill = test_ill_xsr, 5199 .par = (const uint32_t[]){MR + 3}, 5200 .windowed_register_op = 0x1, 5201 }, { 5202 .name = "xsr.memctl", 5203 .translate = translate_xsr, 5204 .test_ill = test_ill_xsr, 5205 .par = (const uint32_t[]){MEMCTL}, 5206 .op_flags = XTENSA_OP_PRIVILEGED, 5207 .windowed_register_op = 0x1, 5208 }, { 5209 .name = "xsr.misc0", 5210 .translate = translate_xsr, 5211 .test_ill = test_ill_xsr, 5212 .par = (const uint32_t[]){MISC}, 5213 .op_flags = XTENSA_OP_PRIVILEGED, 5214 .windowed_register_op = 0x1, 5215 }, { 5216 .name = "xsr.misc1", 5217 .translate = translate_xsr, 5218 .test_ill = test_ill_xsr, 5219 .par = (const uint32_t[]){MISC + 1}, 5220 .op_flags = XTENSA_OP_PRIVILEGED, 5221 .windowed_register_op = 0x1, 5222 }, { 5223 .name = "xsr.misc2", 5224 .translate = translate_xsr, 5225 .test_ill = test_ill_xsr, 5226 .par = (const uint32_t[]){MISC + 2}, 5227 .op_flags = XTENSA_OP_PRIVILEGED, 5228 .windowed_register_op = 0x1, 5229 }, { 5230 .name = "xsr.misc3", 5231 .translate = translate_xsr, 5232 .test_ill = test_ill_xsr, 5233 .par = (const uint32_t[]){MISC + 3}, 5234 .op_flags = XTENSA_OP_PRIVILEGED, 5235 .windowed_register_op = 0x1, 5236 }, { 5237 .name = "xsr.prid", 5238 .translate = translate_xsr, 5239 .test_ill = test_ill_xsr, 5240 .par = (const uint32_t[]){PRID}, 5241 .op_flags = XTENSA_OP_PRIVILEGED, 5242 .windowed_register_op = 0x1, 5243 }, { 5244 .name = "xsr.ps", 5245 .translate = translate_xsr, 5246 .test_ill = test_ill_xsr, 5247 .par = (const uint32_t[]){PS}, 5248 .op_flags = 5249 XTENSA_OP_PRIVILEGED | 5250 XTENSA_OP_EXIT_TB_M1 | 5251 XTENSA_OP_CHECK_INTERRUPTS, 5252 .windowed_register_op = 0x1, 5253 }, { 5254 .name = "xsr.ptevaddr", 5255 .translate = translate_xsr, 5256 .test_ill = test_ill_xsr, 5257 .par = (const uint32_t[]){PTEVADDR}, 5258 .op_flags = XTENSA_OP_PRIVILEGED, 5259 .windowed_register_op = 0x1, 5260 }, { 5261 .name = "xsr.rasid", 5262 .translate = translate_xsr, 5263 .test_ill = test_ill_xsr, 5264 .par = (const uint32_t[]){RASID}, 5265 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, 5266 .windowed_register_op = 0x1, 5267 }, { 5268 .name = "xsr.sar", 5269 .translate = translate_xsr, 5270 .test_ill = test_ill_xsr, 5271 .par = (const uint32_t[]){SAR}, 5272 .windowed_register_op = 0x1, 5273 }, { 5274 .name = "xsr.scompare1", 5275 .translate = translate_xsr, 5276 .test_ill = test_ill_xsr, 5277 .par = (const uint32_t[]){SCOMPARE1}, 5278 .windowed_register_op = 0x1, 5279 }, { 5280 .name = "xsr.vecbase", 5281 .translate = translate_xsr, 5282 .test_ill = test_ill_xsr, 5283 .par = (const uint32_t[]){VECBASE}, 5284 .op_flags = XTENSA_OP_PRIVILEGED, 5285 .windowed_register_op = 0x1, 5286 }, { 5287 .name = "xsr.windowbase", 5288 .translate = translate_xsr, 5289 .test_ill = test_ill_xsr, 5290 .par = (const uint32_t[]){WINDOW_BASE}, 5291 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, 5292 .windowed_register_op = 0x1, 5293 }, { 5294 .name = "xsr.windowstart", 5295 .translate = translate_xsr, 5296 .test_ill = test_ill_xsr, 5297 .par = (const uint32_t[]){WINDOW_START}, 5298 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, 5299 .windowed_register_op = 0x1, 5300 }, 5301 }; 5302 5303 const XtensaOpcodeTranslators xtensa_core_opcodes = { 5304 .num_opcodes = ARRAY_SIZE(core_ops), 5305 .opcode = core_ops, 5306 }; 5307 5308 5309 static void translate_abs_s(DisasContext *dc, const uint32_t arg[], 5310 const uint32_t par[]) 5311 { 5312 gen_helper_abs_s(cpu_FR[arg[0]], cpu_FR[arg[1]]); 5313 } 5314 5315 static void translate_add_s(DisasContext *dc, const uint32_t arg[], 5316 const uint32_t par[]) 5317 { 5318 gen_helper_add_s(cpu_FR[arg[0]], cpu_env, 5319 cpu_FR[arg[1]], cpu_FR[arg[2]]); 5320 } 5321 5322 enum { 5323 COMPARE_UN, 5324 COMPARE_OEQ, 5325 COMPARE_UEQ, 5326 COMPARE_OLT, 5327 COMPARE_ULT, 5328 COMPARE_OLE, 5329 COMPARE_ULE, 5330 }; 5331 5332 static void translate_compare_s(DisasContext *dc, const uint32_t arg[], 5333 const uint32_t par[]) 5334 { 5335 static void (* const helper[])(TCGv_env env, TCGv_i32 bit, 5336 TCGv_i32 s, TCGv_i32 t) = { 5337 [COMPARE_UN] = gen_helper_un_s, 5338 [COMPARE_OEQ] = gen_helper_oeq_s, 5339 [COMPARE_UEQ] = gen_helper_ueq_s, 5340 [COMPARE_OLT] = gen_helper_olt_s, 5341 [COMPARE_ULT] = gen_helper_ult_s, 5342 [COMPARE_OLE] = gen_helper_ole_s, 5343 [COMPARE_ULE] = gen_helper_ule_s, 5344 }; 5345 TCGv_i32 bit = tcg_const_i32(1 << arg[0]); 5346 5347 helper[par[0]](cpu_env, bit, cpu_FR[arg[1]], cpu_FR[arg[2]]); 5348 tcg_temp_free(bit); 5349 } 5350 5351 static void translate_float_s(DisasContext *dc, const uint32_t arg[], 5352 const uint32_t par[]) 5353 { 5354 TCGv_i32 scale = tcg_const_i32(-arg[2]); 5355 5356 if (par[0]) { 5357 gen_helper_uitof(cpu_FR[arg[0]], cpu_env, cpu_R[arg[1]], scale); 5358 } else { 5359 gen_helper_itof(cpu_FR[arg[0]], cpu_env, cpu_R[arg[1]], scale); 5360 } 5361 tcg_temp_free(scale); 5362 } 5363 5364 static void translate_ftoi_s(DisasContext *dc, const uint32_t arg[], 5365 const uint32_t par[]) 5366 { 5367 TCGv_i32 rounding_mode = tcg_const_i32(par[0]); 5368 TCGv_i32 scale = tcg_const_i32(arg[2]); 5369 5370 if (par[1]) { 5371 gen_helper_ftoui(cpu_R[arg[0]], cpu_FR[arg[1]], 5372 rounding_mode, scale); 5373 } else { 5374 gen_helper_ftoi(cpu_R[arg[0]], cpu_FR[arg[1]], 5375 rounding_mode, scale); 5376 } 5377 tcg_temp_free(rounding_mode); 5378 tcg_temp_free(scale); 5379 } 5380 5381 static void translate_ldsti(DisasContext *dc, const uint32_t arg[], 5382 const uint32_t par[]) 5383 { 5384 TCGv_i32 addr = tcg_temp_new_i32(); 5385 5386 tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]); 5387 gen_load_store_alignment(dc, 2, addr, false); 5388 if (par[0]) { 5389 tcg_gen_qemu_st32(cpu_FR[arg[0]], addr, dc->cring); 5390 } else { 5391 tcg_gen_qemu_ld32u(cpu_FR[arg[0]], addr, dc->cring); 5392 } 5393 if (par[1]) { 5394 tcg_gen_mov_i32(cpu_R[arg[1]], addr); 5395 } 5396 tcg_temp_free(addr); 5397 } 5398 5399 static void translate_ldstx(DisasContext *dc, const uint32_t arg[], 5400 const uint32_t par[]) 5401 { 5402 TCGv_i32 addr = tcg_temp_new_i32(); 5403 5404 tcg_gen_add_i32(addr, cpu_R[arg[1]], cpu_R[arg[2]]); 5405 gen_load_store_alignment(dc, 2, addr, false); 5406 if (par[0]) { 5407 tcg_gen_qemu_st32(cpu_FR[arg[0]], addr, dc->cring); 5408 } else { 5409 tcg_gen_qemu_ld32u(cpu_FR[arg[0]], addr, dc->cring); 5410 } 5411 if (par[1]) { 5412 tcg_gen_mov_i32(cpu_R[arg[1]], addr); 5413 } 5414 tcg_temp_free(addr); 5415 } 5416 5417 static void translate_madd_s(DisasContext *dc, const uint32_t arg[], 5418 const uint32_t par[]) 5419 { 5420 gen_helper_madd_s(cpu_FR[arg[0]], cpu_env, 5421 cpu_FR[arg[0]], cpu_FR[arg[1]], cpu_FR[arg[2]]); 5422 } 5423 5424 static void translate_mov_s(DisasContext *dc, const uint32_t arg[], 5425 const uint32_t par[]) 5426 { 5427 tcg_gen_mov_i32(cpu_FR[arg[0]], cpu_FR[arg[1]]); 5428 } 5429 5430 static void translate_movcond_s(DisasContext *dc, const uint32_t arg[], 5431 const uint32_t par[]) 5432 { 5433 TCGv_i32 zero = tcg_const_i32(0); 5434 5435 tcg_gen_movcond_i32(par[0], cpu_FR[arg[0]], 5436 cpu_R[arg[2]], zero, 5437 cpu_FR[arg[1]], cpu_FR[arg[0]]); 5438 tcg_temp_free(zero); 5439 } 5440 5441 static void translate_movp_s(DisasContext *dc, const uint32_t arg[], 5442 const uint32_t par[]) 5443 { 5444 TCGv_i32 zero = tcg_const_i32(0); 5445 TCGv_i32 tmp = tcg_temp_new_i32(); 5446 5447 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << arg[2]); 5448 tcg_gen_movcond_i32(par[0], 5449 cpu_FR[arg[0]], tmp, zero, 5450 cpu_FR[arg[1]], cpu_FR[arg[0]]); 5451 tcg_temp_free(tmp); 5452 tcg_temp_free(zero); 5453 } 5454 5455 static void translate_mul_s(DisasContext *dc, const uint32_t arg[], 5456 const uint32_t par[]) 5457 { 5458 gen_helper_mul_s(cpu_FR[arg[0]], cpu_env, 5459 cpu_FR[arg[1]], cpu_FR[arg[2]]); 5460 } 5461 5462 static void translate_msub_s(DisasContext *dc, const uint32_t arg[], 5463 const uint32_t par[]) 5464 { 5465 gen_helper_msub_s(cpu_FR[arg[0]], cpu_env, 5466 cpu_FR[arg[0]], cpu_FR[arg[1]], cpu_FR[arg[2]]); 5467 } 5468 5469 static void translate_neg_s(DisasContext *dc, const uint32_t arg[], 5470 const uint32_t par[]) 5471 { 5472 gen_helper_neg_s(cpu_FR[arg[0]], cpu_FR[arg[1]]); 5473 } 5474 5475 static void translate_rfr_s(DisasContext *dc, const uint32_t arg[], 5476 const uint32_t par[]) 5477 { 5478 tcg_gen_mov_i32(cpu_R[arg[0]], cpu_FR[arg[1]]); 5479 } 5480 5481 static void translate_sub_s(DisasContext *dc, const uint32_t arg[], 5482 const uint32_t par[]) 5483 { 5484 gen_helper_sub_s(cpu_FR[arg[0]], cpu_env, 5485 cpu_FR[arg[1]], cpu_FR[arg[2]]); 5486 } 5487 5488 static void translate_wfr_s(DisasContext *dc, const uint32_t arg[], 5489 const uint32_t par[]) 5490 { 5491 tcg_gen_mov_i32(cpu_FR[arg[0]], cpu_R[arg[1]]); 5492 } 5493 5494 static const XtensaOpcodeOps fpu2000_ops[] = { 5495 { 5496 .name = "abs.s", 5497 .translate = translate_abs_s, 5498 .coprocessor = 0x1, 5499 }, { 5500 .name = "add.s", 5501 .translate = translate_add_s, 5502 .coprocessor = 0x1, 5503 }, { 5504 .name = "ceil.s", 5505 .translate = translate_ftoi_s, 5506 .par = (const uint32_t[]){float_round_up, false}, 5507 .windowed_register_op = 0x1, 5508 .coprocessor = 0x1, 5509 }, { 5510 .name = "float.s", 5511 .translate = translate_float_s, 5512 .par = (const uint32_t[]){false}, 5513 .windowed_register_op = 0x2, 5514 .coprocessor = 0x1, 5515 }, { 5516 .name = "floor.s", 5517 .translate = translate_ftoi_s, 5518 .par = (const uint32_t[]){float_round_down, false}, 5519 .windowed_register_op = 0x1, 5520 .coprocessor = 0x1, 5521 }, { 5522 .name = "lsi", 5523 .translate = translate_ldsti, 5524 .par = (const uint32_t[]){false, false}, 5525 .windowed_register_op = 0x2, 5526 .coprocessor = 0x1, 5527 }, { 5528 .name = "lsiu", 5529 .translate = translate_ldsti, 5530 .par = (const uint32_t[]){false, true}, 5531 .windowed_register_op = 0x2, 5532 .coprocessor = 0x1, 5533 }, { 5534 .name = "lsx", 5535 .translate = translate_ldstx, 5536 .par = (const uint32_t[]){false, false}, 5537 .windowed_register_op = 0x6, 5538 .coprocessor = 0x1, 5539 }, { 5540 .name = "lsxu", 5541 .translate = translate_ldstx, 5542 .par = (const uint32_t[]){false, true}, 5543 .windowed_register_op = 0x6, 5544 .coprocessor = 0x1, 5545 }, { 5546 .name = "madd.s", 5547 .translate = translate_madd_s, 5548 .coprocessor = 0x1, 5549 }, { 5550 .name = "mov.s", 5551 .translate = translate_mov_s, 5552 .coprocessor = 0x1, 5553 }, { 5554 .name = "moveqz.s", 5555 .translate = translate_movcond_s, 5556 .par = (const uint32_t[]){TCG_COND_EQ}, 5557 .windowed_register_op = 0x4, 5558 .coprocessor = 0x1, 5559 }, { 5560 .name = "movf.s", 5561 .translate = translate_movp_s, 5562 .par = (const uint32_t[]){TCG_COND_EQ}, 5563 .coprocessor = 0x1, 5564 }, { 5565 .name = "movgez.s", 5566 .translate = translate_movcond_s, 5567 .par = (const uint32_t[]){TCG_COND_GE}, 5568 .windowed_register_op = 0x4, 5569 .coprocessor = 0x1, 5570 }, { 5571 .name = "movltz.s", 5572 .translate = translate_movcond_s, 5573 .par = (const uint32_t[]){TCG_COND_LT}, 5574 .windowed_register_op = 0x4, 5575 .coprocessor = 0x1, 5576 }, { 5577 .name = "movnez.s", 5578 .translate = translate_movcond_s, 5579 .par = (const uint32_t[]){TCG_COND_NE}, 5580 .windowed_register_op = 0x4, 5581 .coprocessor = 0x1, 5582 }, { 5583 .name = "movt.s", 5584 .translate = translate_movp_s, 5585 .par = (const uint32_t[]){TCG_COND_NE}, 5586 .coprocessor = 0x1, 5587 }, { 5588 .name = "msub.s", 5589 .translate = translate_msub_s, 5590 .coprocessor = 0x1, 5591 }, { 5592 .name = "mul.s", 5593 .translate = translate_mul_s, 5594 .coprocessor = 0x1, 5595 }, { 5596 .name = "neg.s", 5597 .translate = translate_neg_s, 5598 .coprocessor = 0x1, 5599 }, { 5600 .name = "oeq.s", 5601 .translate = translate_compare_s, 5602 .par = (const uint32_t[]){COMPARE_OEQ}, 5603 .coprocessor = 0x1, 5604 }, { 5605 .name = "ole.s", 5606 .translate = translate_compare_s, 5607 .par = (const uint32_t[]){COMPARE_OLE}, 5608 .coprocessor = 0x1, 5609 }, { 5610 .name = "olt.s", 5611 .translate = translate_compare_s, 5612 .par = (const uint32_t[]){COMPARE_OLT}, 5613 .coprocessor = 0x1, 5614 }, { 5615 .name = "rfr", 5616 .translate = translate_rfr_s, 5617 .windowed_register_op = 0x1, 5618 .coprocessor = 0x1, 5619 }, { 5620 .name = "round.s", 5621 .translate = translate_ftoi_s, 5622 .par = (const uint32_t[]){float_round_nearest_even, false}, 5623 .windowed_register_op = 0x1, 5624 .coprocessor = 0x1, 5625 }, { 5626 .name = "ssi", 5627 .translate = translate_ldsti, 5628 .par = (const uint32_t[]){true, false}, 5629 .windowed_register_op = 0x2, 5630 .coprocessor = 0x1, 5631 }, { 5632 .name = "ssiu", 5633 .translate = translate_ldsti, 5634 .par = (const uint32_t[]){true, true}, 5635 .windowed_register_op = 0x2, 5636 .coprocessor = 0x1, 5637 }, { 5638 .name = "ssx", 5639 .translate = translate_ldstx, 5640 .par = (const uint32_t[]){true, false}, 5641 .windowed_register_op = 0x6, 5642 .coprocessor = 0x1, 5643 }, { 5644 .name = "ssxu", 5645 .translate = translate_ldstx, 5646 .par = (const uint32_t[]){true, true}, 5647 .windowed_register_op = 0x6, 5648 .coprocessor = 0x1, 5649 }, { 5650 .name = "sub.s", 5651 .translate = translate_sub_s, 5652 .coprocessor = 0x1, 5653 }, { 5654 .name = "trunc.s", 5655 .translate = translate_ftoi_s, 5656 .par = (const uint32_t[]){float_round_to_zero, false}, 5657 .windowed_register_op = 0x1, 5658 .coprocessor = 0x1, 5659 }, { 5660 .name = "ueq.s", 5661 .translate = translate_compare_s, 5662 .par = (const uint32_t[]){COMPARE_UEQ}, 5663 .coprocessor = 0x1, 5664 }, { 5665 .name = "ufloat.s", 5666 .translate = translate_float_s, 5667 .par = (const uint32_t[]){true}, 5668 .windowed_register_op = 0x2, 5669 .coprocessor = 0x1, 5670 }, { 5671 .name = "ule.s", 5672 .translate = translate_compare_s, 5673 .par = (const uint32_t[]){COMPARE_ULE}, 5674 .coprocessor = 0x1, 5675 }, { 5676 .name = "ult.s", 5677 .translate = translate_compare_s, 5678 .par = (const uint32_t[]){COMPARE_ULT}, 5679 .coprocessor = 0x1, 5680 }, { 5681 .name = "un.s", 5682 .translate = translate_compare_s, 5683 .par = (const uint32_t[]){COMPARE_UN}, 5684 .coprocessor = 0x1, 5685 }, { 5686 .name = "utrunc.s", 5687 .translate = translate_ftoi_s, 5688 .par = (const uint32_t[]){float_round_to_zero, true}, 5689 .windowed_register_op = 0x1, 5690 .coprocessor = 0x1, 5691 }, { 5692 .name = "wfr", 5693 .translate = translate_wfr_s, 5694 .windowed_register_op = 0x2, 5695 .coprocessor = 0x1, 5696 }, 5697 }; 5698 5699 const XtensaOpcodeTranslators xtensa_fpu2000_opcodes = { 5700 .num_opcodes = ARRAY_SIZE(fpu2000_ops), 5701 .opcode = fpu2000_ops, 5702 }; 5703