1 /* 2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * * Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * * Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * * Neither the name of the Open Source and Linux Lab nor the 13 * names of its contributors may be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include "qemu/osdep.h" 29 #include "cpu.h" 30 #include "exec/helper-proto.h" 31 #include "qemu/host-utils.h" 32 #include "exec/exec-all.h" 33 #include "exec/cpu_ldst.h" 34 #include "exec/address-spaces.h" 35 #include "qemu/timer.h" 36 37 void xtensa_cpu_do_unaligned_access(CPUState *cs, 38 vaddr addr, MMUAccessType access_type, 39 int mmu_idx, uintptr_t retaddr) 40 { 41 XtensaCPU *cpu = XTENSA_CPU(cs); 42 CPUXtensaState *env = &cpu->env; 43 44 if (xtensa_option_enabled(env->config, XTENSA_OPTION_UNALIGNED_EXCEPTION) && 45 !xtensa_option_enabled(env->config, XTENSA_OPTION_HW_ALIGNMENT)) { 46 cpu_restore_state(CPU(cpu), retaddr); 47 HELPER(exception_cause_vaddr)(env, 48 env->pc, LOAD_STORE_ALIGNMENT_CAUSE, addr); 49 } 50 } 51 52 void tlb_fill(CPUState *cs, target_ulong vaddr, MMUAccessType access_type, 53 int mmu_idx, uintptr_t retaddr) 54 { 55 XtensaCPU *cpu = XTENSA_CPU(cs); 56 CPUXtensaState *env = &cpu->env; 57 uint32_t paddr; 58 uint32_t page_size; 59 unsigned access; 60 int ret = xtensa_get_physical_addr(env, true, vaddr, access_type, mmu_idx, 61 &paddr, &page_size, &access); 62 63 qemu_log_mask(CPU_LOG_MMU, "%s(%08x, %d, %d) -> %08x, ret = %d\n", 64 __func__, vaddr, access_type, mmu_idx, paddr, ret); 65 66 if (ret == 0) { 67 tlb_set_page(cs, 68 vaddr & TARGET_PAGE_MASK, 69 paddr & TARGET_PAGE_MASK, 70 access, mmu_idx, page_size); 71 } else { 72 cpu_restore_state(cs, retaddr); 73 HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr); 74 } 75 } 76 77 void xtensa_cpu_do_unassigned_access(CPUState *cs, hwaddr addr, 78 bool is_write, bool is_exec, int opaque, 79 unsigned size) 80 { 81 XtensaCPU *cpu = XTENSA_CPU(cs); 82 CPUXtensaState *env = &cpu->env; 83 84 HELPER(exception_cause_vaddr)(env, env->pc, 85 is_exec ? 86 INSTR_PIF_ADDR_ERROR_CAUSE : 87 LOAD_STORE_PIF_ADDR_ERROR_CAUSE, 88 is_exec ? addr : cs->mem_io_vaddr); 89 } 90 91 static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr) 92 { 93 uint32_t paddr; 94 uint32_t page_size; 95 unsigned access; 96 int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0, 97 &paddr, &page_size, &access); 98 if (ret == 0) { 99 tb_invalidate_phys_addr(&address_space_memory, paddr); 100 } 101 } 102 103 void HELPER(exception)(CPUXtensaState *env, uint32_t excp) 104 { 105 CPUState *cs = CPU(xtensa_env_get_cpu(env)); 106 107 cs->exception_index = excp; 108 if (excp == EXCP_DEBUG) { 109 env->exception_taken = 0; 110 } 111 cpu_loop_exit(cs); 112 } 113 114 void HELPER(exception_cause)(CPUXtensaState *env, uint32_t pc, uint32_t cause) 115 { 116 uint32_t vector; 117 118 env->pc = pc; 119 if (env->sregs[PS] & PS_EXCM) { 120 if (env->config->ndepc) { 121 env->sregs[DEPC] = pc; 122 } else { 123 env->sregs[EPC1] = pc; 124 } 125 vector = EXC_DOUBLE; 126 } else { 127 env->sregs[EPC1] = pc; 128 vector = (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL; 129 } 130 131 env->sregs[EXCCAUSE] = cause; 132 env->sregs[PS] |= PS_EXCM; 133 134 HELPER(exception)(env, vector); 135 } 136 137 void HELPER(exception_cause_vaddr)(CPUXtensaState *env, 138 uint32_t pc, uint32_t cause, uint32_t vaddr) 139 { 140 env->sregs[EXCVADDR] = vaddr; 141 HELPER(exception_cause)(env, pc, cause); 142 } 143 144 void debug_exception_env(CPUXtensaState *env, uint32_t cause) 145 { 146 if (xtensa_get_cintlevel(env) < env->config->debug_level) { 147 HELPER(debug_exception)(env, env->pc, cause); 148 } 149 } 150 151 void HELPER(debug_exception)(CPUXtensaState *env, uint32_t pc, uint32_t cause) 152 { 153 unsigned level = env->config->debug_level; 154 155 env->pc = pc; 156 env->sregs[DEBUGCAUSE] = cause; 157 env->sregs[EPC1 + level - 1] = pc; 158 env->sregs[EPS2 + level - 2] = env->sregs[PS]; 159 env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) | PS_EXCM | 160 (level << PS_INTLEVEL_SHIFT); 161 HELPER(exception)(env, EXC_DEBUG); 162 } 163 164 static void copy_window_from_phys(CPUXtensaState *env, 165 uint32_t window, uint32_t phys, uint32_t n) 166 { 167 assert(phys < env->config->nareg); 168 if (phys + n <= env->config->nareg) { 169 memcpy(env->regs + window, env->phys_regs + phys, 170 n * sizeof(uint32_t)); 171 } else { 172 uint32_t n1 = env->config->nareg - phys; 173 memcpy(env->regs + window, env->phys_regs + phys, 174 n1 * sizeof(uint32_t)); 175 memcpy(env->regs + window + n1, env->phys_regs, 176 (n - n1) * sizeof(uint32_t)); 177 } 178 } 179 180 static void copy_phys_from_window(CPUXtensaState *env, 181 uint32_t phys, uint32_t window, uint32_t n) 182 { 183 assert(phys < env->config->nareg); 184 if (phys + n <= env->config->nareg) { 185 memcpy(env->phys_regs + phys, env->regs + window, 186 n * sizeof(uint32_t)); 187 } else { 188 uint32_t n1 = env->config->nareg - phys; 189 memcpy(env->phys_regs + phys, env->regs + window, 190 n1 * sizeof(uint32_t)); 191 memcpy(env->phys_regs, env->regs + window + n1, 192 (n - n1) * sizeof(uint32_t)); 193 } 194 } 195 196 197 static inline unsigned windowbase_bound(unsigned a, const CPUXtensaState *env) 198 { 199 return a & (env->config->nareg / 4 - 1); 200 } 201 202 static inline unsigned windowstart_bit(unsigned a, const CPUXtensaState *env) 203 { 204 return 1 << windowbase_bound(a, env); 205 } 206 207 void xtensa_sync_window_from_phys(CPUXtensaState *env) 208 { 209 copy_window_from_phys(env, 0, env->sregs[WINDOW_BASE] * 4, 16); 210 } 211 212 void xtensa_sync_phys_from_window(CPUXtensaState *env) 213 { 214 copy_phys_from_window(env, env->sregs[WINDOW_BASE] * 4, 0, 16); 215 } 216 217 static void rotate_window_abs(CPUXtensaState *env, uint32_t position) 218 { 219 xtensa_sync_phys_from_window(env); 220 env->sregs[WINDOW_BASE] = windowbase_bound(position, env); 221 xtensa_sync_window_from_phys(env); 222 } 223 224 static void rotate_window(CPUXtensaState *env, uint32_t delta) 225 { 226 rotate_window_abs(env, env->sregs[WINDOW_BASE] + delta); 227 } 228 229 void HELPER(wsr_windowbase)(CPUXtensaState *env, uint32_t v) 230 { 231 rotate_window_abs(env, v); 232 } 233 234 void HELPER(entry)(CPUXtensaState *env, uint32_t pc, uint32_t s, uint32_t imm) 235 { 236 int callinc = (env->sregs[PS] & PS_CALLINC) >> PS_CALLINC_SHIFT; 237 if (s > 3 || ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) { 238 qemu_log_mask(LOG_GUEST_ERROR, "Illegal entry instruction(pc = %08x), PS = %08x\n", 239 pc, env->sregs[PS]); 240 HELPER(exception_cause)(env, pc, ILLEGAL_INSTRUCTION_CAUSE); 241 } else { 242 uint32_t windowstart = xtensa_replicate_windowstart(env) >> 243 (env->sregs[WINDOW_BASE] + 1); 244 245 if (windowstart & ((1 << callinc) - 1)) { 246 HELPER(window_check)(env, pc, callinc); 247 } 248 env->regs[(callinc << 2) | (s & 3)] = env->regs[s] - (imm << 3); 249 rotate_window(env, callinc); 250 env->sregs[WINDOW_START] |= 251 windowstart_bit(env->sregs[WINDOW_BASE], env); 252 } 253 } 254 255 void HELPER(window_check)(CPUXtensaState *env, uint32_t pc, uint32_t w) 256 { 257 uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env); 258 uint32_t windowstart = xtensa_replicate_windowstart(env) >> 259 (env->sregs[WINDOW_BASE] + 1); 260 uint32_t n = ctz32(windowstart) + 1; 261 262 assert(n <= w); 263 264 rotate_window(env, n); 265 env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) | 266 (windowbase << PS_OWB_SHIFT) | PS_EXCM; 267 env->sregs[EPC1] = env->pc = pc; 268 269 switch (ctz32(windowstart >> n)) { 270 case 0: 271 HELPER(exception)(env, EXC_WINDOW_OVERFLOW4); 272 break; 273 case 1: 274 HELPER(exception)(env, EXC_WINDOW_OVERFLOW8); 275 break; 276 default: 277 HELPER(exception)(env, EXC_WINDOW_OVERFLOW12); 278 break; 279 } 280 } 281 282 uint32_t HELPER(retw)(CPUXtensaState *env, uint32_t pc) 283 { 284 int n = (env->regs[0] >> 30) & 0x3; 285 int m = 0; 286 uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env); 287 uint32_t windowstart = env->sregs[WINDOW_START]; 288 uint32_t ret_pc = 0; 289 290 if (windowstart & windowstart_bit(windowbase - 1, env)) { 291 m = 1; 292 } else if (windowstart & windowstart_bit(windowbase - 2, env)) { 293 m = 2; 294 } else if (windowstart & windowstart_bit(windowbase - 3, env)) { 295 m = 3; 296 } 297 298 if (n == 0 || (m != 0 && m != n) || 299 ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) { 300 qemu_log_mask(LOG_GUEST_ERROR, "Illegal retw instruction(pc = %08x), " 301 "PS = %08x, m = %d, n = %d\n", 302 pc, env->sregs[PS], m, n); 303 HELPER(exception_cause)(env, pc, ILLEGAL_INSTRUCTION_CAUSE); 304 } else { 305 int owb = windowbase; 306 307 ret_pc = (pc & 0xc0000000) | (env->regs[0] & 0x3fffffff); 308 309 rotate_window(env, -n); 310 if (windowstart & windowstart_bit(env->sregs[WINDOW_BASE], env)) { 311 env->sregs[WINDOW_START] &= ~windowstart_bit(owb, env); 312 } else { 313 /* window underflow */ 314 env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) | 315 (windowbase << PS_OWB_SHIFT) | PS_EXCM; 316 env->sregs[EPC1] = env->pc = pc; 317 318 if (n == 1) { 319 HELPER(exception)(env, EXC_WINDOW_UNDERFLOW4); 320 } else if (n == 2) { 321 HELPER(exception)(env, EXC_WINDOW_UNDERFLOW8); 322 } else if (n == 3) { 323 HELPER(exception)(env, EXC_WINDOW_UNDERFLOW12); 324 } 325 } 326 } 327 return ret_pc; 328 } 329 330 void HELPER(rotw)(CPUXtensaState *env, uint32_t imm4) 331 { 332 rotate_window(env, imm4); 333 } 334 335 void HELPER(restore_owb)(CPUXtensaState *env) 336 { 337 rotate_window_abs(env, (env->sregs[PS] & PS_OWB) >> PS_OWB_SHIFT); 338 } 339 340 void HELPER(movsp)(CPUXtensaState *env, uint32_t pc) 341 { 342 if ((env->sregs[WINDOW_START] & 343 (windowstart_bit(env->sregs[WINDOW_BASE] - 3, env) | 344 windowstart_bit(env->sregs[WINDOW_BASE] - 2, env) | 345 windowstart_bit(env->sregs[WINDOW_BASE] - 1, env))) == 0) { 346 HELPER(exception_cause)(env, pc, ALLOCA_CAUSE); 347 } 348 } 349 350 void HELPER(wsr_lbeg)(CPUXtensaState *env, uint32_t v) 351 { 352 if (env->sregs[LBEG] != v) { 353 tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1); 354 env->sregs[LBEG] = v; 355 } 356 } 357 358 void HELPER(wsr_lend)(CPUXtensaState *env, uint32_t v) 359 { 360 if (env->sregs[LEND] != v) { 361 tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1); 362 env->sregs[LEND] = v; 363 tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1); 364 } 365 } 366 367 void HELPER(dump_state)(CPUXtensaState *env) 368 { 369 XtensaCPU *cpu = xtensa_env_get_cpu(env); 370 371 cpu_dump_state(CPU(cpu), stderr, fprintf, 0); 372 } 373 374 void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, uint32_t intlevel) 375 { 376 CPUState *cpu; 377 378 env->pc = pc; 379 env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) | 380 (intlevel << PS_INTLEVEL_SHIFT); 381 check_interrupts(env); 382 if (env->pending_irq_level) { 383 cpu_loop_exit(CPU(xtensa_env_get_cpu(env))); 384 return; 385 } 386 387 cpu = CPU(xtensa_env_get_cpu(env)); 388 env->halt_clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 389 cpu->halted = 1; 390 if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT)) { 391 xtensa_rearm_ccompare_timer(env); 392 } 393 HELPER(exception)(env, EXCP_HLT); 394 } 395 396 void HELPER(timer_irq)(CPUXtensaState *env, uint32_t id, uint32_t active) 397 { 398 xtensa_timer_irq(env, id, active); 399 } 400 401 void HELPER(advance_ccount)(CPUXtensaState *env, uint32_t d) 402 { 403 xtensa_advance_ccount(env, d); 404 } 405 406 void HELPER(check_interrupts)(CPUXtensaState *env) 407 { 408 check_interrupts(env); 409 } 410 411 void HELPER(itlb_hit_test)(CPUXtensaState *env, uint32_t vaddr) 412 { 413 get_page_addr_code(env, vaddr); 414 } 415 416 /*! 417 * Check vaddr accessibility/cache attributes and raise an exception if 418 * specified by the ATOMCTL SR. 419 * 420 * Note: local memory exclusion is not implemented 421 */ 422 void HELPER(check_atomctl)(CPUXtensaState *env, uint32_t pc, uint32_t vaddr) 423 { 424 uint32_t paddr, page_size, access; 425 uint32_t atomctl = env->sregs[ATOMCTL]; 426 int rc = xtensa_get_physical_addr(env, true, vaddr, 1, 427 xtensa_get_cring(env), &paddr, &page_size, &access); 428 429 /* 430 * s32c1i never causes LOAD_PROHIBITED_CAUSE exceptions, 431 * see opcode description in the ISA 432 */ 433 if (rc == 0 && 434 (access & (PAGE_READ | PAGE_WRITE)) != (PAGE_READ | PAGE_WRITE)) { 435 rc = STORE_PROHIBITED_CAUSE; 436 } 437 438 if (rc) { 439 HELPER(exception_cause_vaddr)(env, pc, rc, vaddr); 440 } 441 442 /* 443 * When data cache is not configured use ATOMCTL bypass field. 444 * See ISA, 4.3.12.4 The Atomic Operation Control Register (ATOMCTL) 445 * under the Conditional Store Option. 446 */ 447 if (!xtensa_option_enabled(env->config, XTENSA_OPTION_DCACHE)) { 448 access = PAGE_CACHE_BYPASS; 449 } 450 451 switch (access & PAGE_CACHE_MASK) { 452 case PAGE_CACHE_WB: 453 atomctl >>= 2; 454 /* fall through */ 455 case PAGE_CACHE_WT: 456 atomctl >>= 2; 457 /* fall through */ 458 case PAGE_CACHE_BYPASS: 459 if ((atomctl & 0x3) == 0) { 460 HELPER(exception_cause_vaddr)(env, pc, 461 LOAD_STORE_ERROR_CAUSE, vaddr); 462 } 463 break; 464 465 case PAGE_CACHE_ISOLATE: 466 HELPER(exception_cause_vaddr)(env, pc, 467 LOAD_STORE_ERROR_CAUSE, vaddr); 468 break; 469 470 default: 471 break; 472 } 473 } 474 475 void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v) 476 { 477 XtensaCPU *cpu = xtensa_env_get_cpu(env); 478 479 v = (v & 0xffffff00) | 0x1; 480 if (v != env->sregs[RASID]) { 481 env->sregs[RASID] = v; 482 tlb_flush(CPU(cpu)); 483 } 484 } 485 486 static uint32_t get_page_size(const CPUXtensaState *env, bool dtlb, uint32_t way) 487 { 488 uint32_t tlbcfg = env->sregs[dtlb ? DTLBCFG : ITLBCFG]; 489 490 switch (way) { 491 case 4: 492 return (tlbcfg >> 16) & 0x3; 493 494 case 5: 495 return (tlbcfg >> 20) & 0x1; 496 497 case 6: 498 return (tlbcfg >> 24) & 0x1; 499 500 default: 501 return 0; 502 } 503 } 504 505 /*! 506 * Get bit mask for the virtual address bits translated by the TLB way 507 */ 508 uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way) 509 { 510 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 511 bool varway56 = dtlb ? 512 env->config->dtlb.varway56 : 513 env->config->itlb.varway56; 514 515 switch (way) { 516 case 4: 517 return 0xfff00000 << get_page_size(env, dtlb, way) * 2; 518 519 case 5: 520 if (varway56) { 521 return 0xf8000000 << get_page_size(env, dtlb, way); 522 } else { 523 return 0xf8000000; 524 } 525 526 case 6: 527 if (varway56) { 528 return 0xf0000000 << (1 - get_page_size(env, dtlb, way)); 529 } else { 530 return 0xf0000000; 531 } 532 533 default: 534 return 0xfffff000; 535 } 536 } else { 537 return REGION_PAGE_MASK; 538 } 539 } 540 541 /*! 542 * Get bit mask for the 'VPN without index' field. 543 * See ISA, 4.6.5.6, data format for RxTLB0 544 */ 545 static uint32_t get_vpn_mask(const CPUXtensaState *env, bool dtlb, uint32_t way) 546 { 547 if (way < 4) { 548 bool is32 = (dtlb ? 549 env->config->dtlb.nrefillentries : 550 env->config->itlb.nrefillentries) == 32; 551 return is32 ? 0xffff8000 : 0xffffc000; 552 } else if (way == 4) { 553 return xtensa_tlb_get_addr_mask(env, dtlb, way) << 2; 554 } else if (way <= 6) { 555 uint32_t mask = xtensa_tlb_get_addr_mask(env, dtlb, way); 556 bool varway56 = dtlb ? 557 env->config->dtlb.varway56 : 558 env->config->itlb.varway56; 559 560 if (varway56) { 561 return mask << (way == 5 ? 2 : 3); 562 } else { 563 return mask << 1; 564 } 565 } else { 566 return 0xfffff000; 567 } 568 } 569 570 /*! 571 * Split virtual address into VPN (with index) and entry index 572 * for the given TLB way 573 */ 574 void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb, 575 uint32_t *vpn, uint32_t wi, uint32_t *ei) 576 { 577 bool varway56 = dtlb ? 578 env->config->dtlb.varway56 : 579 env->config->itlb.varway56; 580 581 if (!dtlb) { 582 wi &= 7; 583 } 584 585 if (wi < 4) { 586 bool is32 = (dtlb ? 587 env->config->dtlb.nrefillentries : 588 env->config->itlb.nrefillentries) == 32; 589 *ei = (v >> 12) & (is32 ? 0x7 : 0x3); 590 } else { 591 switch (wi) { 592 case 4: 593 { 594 uint32_t eibase = 20 + get_page_size(env, dtlb, wi) * 2; 595 *ei = (v >> eibase) & 0x3; 596 } 597 break; 598 599 case 5: 600 if (varway56) { 601 uint32_t eibase = 27 + get_page_size(env, dtlb, wi); 602 *ei = (v >> eibase) & 0x3; 603 } else { 604 *ei = (v >> 27) & 0x1; 605 } 606 break; 607 608 case 6: 609 if (varway56) { 610 uint32_t eibase = 29 - get_page_size(env, dtlb, wi); 611 *ei = (v >> eibase) & 0x7; 612 } else { 613 *ei = (v >> 28) & 0x1; 614 } 615 break; 616 617 default: 618 *ei = 0; 619 break; 620 } 621 } 622 *vpn = v & xtensa_tlb_get_addr_mask(env, dtlb, wi); 623 } 624 625 /*! 626 * Split TLB address into TLB way, entry index and VPN (with index). 627 * See ISA, 4.6.5.5 - 4.6.5.8 for the TLB addressing format 628 */ 629 static void split_tlb_entry_spec(CPUXtensaState *env, uint32_t v, bool dtlb, 630 uint32_t *vpn, uint32_t *wi, uint32_t *ei) 631 { 632 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 633 *wi = v & (dtlb ? 0xf : 0x7); 634 split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei); 635 } else { 636 *vpn = v & REGION_PAGE_MASK; 637 *wi = 0; 638 *ei = (v >> 29) & 0x7; 639 } 640 } 641 642 static xtensa_tlb_entry *get_tlb_entry(CPUXtensaState *env, 643 uint32_t v, bool dtlb, uint32_t *pwi) 644 { 645 uint32_t vpn; 646 uint32_t wi; 647 uint32_t ei; 648 649 split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei); 650 if (pwi) { 651 *pwi = wi; 652 } 653 return xtensa_tlb_get_entry(env, dtlb, wi, ei); 654 } 655 656 uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) 657 { 658 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 659 uint32_t wi; 660 const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi); 661 return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->asid; 662 } else { 663 return v & REGION_PAGE_MASK; 664 } 665 } 666 667 uint32_t HELPER(rtlb1)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) 668 { 669 const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, NULL); 670 return entry->paddr | entry->attr; 671 } 672 673 void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) 674 { 675 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 676 uint32_t wi; 677 xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi); 678 if (entry->variable && entry->asid) { 679 tlb_flush_page(CPU(xtensa_env_get_cpu(env)), entry->vaddr); 680 entry->asid = 0; 681 } 682 } 683 } 684 685 uint32_t HELPER(ptlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) 686 { 687 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 688 uint32_t wi; 689 uint32_t ei; 690 uint8_t ring; 691 int res = xtensa_tlb_lookup(env, v, dtlb, &wi, &ei, &ring); 692 693 switch (res) { 694 case 0: 695 if (ring >= xtensa_get_ring(env)) { 696 return (v & 0xfffff000) | wi | (dtlb ? 0x10 : 0x8); 697 } 698 break; 699 700 case INST_TLB_MULTI_HIT_CAUSE: 701 case LOAD_STORE_TLB_MULTI_HIT_CAUSE: 702 HELPER(exception_cause_vaddr)(env, env->pc, res, v); 703 break; 704 } 705 return 0; 706 } else { 707 return (v & REGION_PAGE_MASK) | 0x1; 708 } 709 } 710 711 void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env, 712 xtensa_tlb_entry *entry, bool dtlb, 713 unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte) 714 { 715 entry->vaddr = vpn; 716 entry->paddr = pte & xtensa_tlb_get_addr_mask(env, dtlb, wi); 717 entry->asid = (env->sregs[RASID] >> ((pte >> 1) & 0x18)) & 0xff; 718 entry->attr = pte & 0xf; 719 } 720 721 void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb, 722 unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte) 723 { 724 XtensaCPU *cpu = xtensa_env_get_cpu(env); 725 CPUState *cs = CPU(cpu); 726 xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei); 727 728 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 729 if (entry->variable) { 730 if (entry->asid) { 731 tlb_flush_page(cs, entry->vaddr); 732 } 733 xtensa_tlb_set_entry_mmu(env, entry, dtlb, wi, ei, vpn, pte); 734 tlb_flush_page(cs, entry->vaddr); 735 } else { 736 qemu_log_mask(LOG_GUEST_ERROR, "%s %d, %d, %d trying to set immutable entry\n", 737 __func__, dtlb, wi, ei); 738 } 739 } else { 740 tlb_flush_page(cs, entry->vaddr); 741 if (xtensa_option_enabled(env->config, 742 XTENSA_OPTION_REGION_TRANSLATION)) { 743 entry->paddr = pte & REGION_PAGE_MASK; 744 } 745 entry->attr = pte & 0xf; 746 } 747 } 748 749 void HELPER(wtlb)(CPUXtensaState *env, uint32_t p, uint32_t v, uint32_t dtlb) 750 { 751 uint32_t vpn; 752 uint32_t wi; 753 uint32_t ei; 754 split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei); 755 xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, p); 756 } 757 758 759 void HELPER(wsr_ibreakenable)(CPUXtensaState *env, uint32_t v) 760 { 761 uint32_t change = v ^ env->sregs[IBREAKENABLE]; 762 unsigned i; 763 764 for (i = 0; i < env->config->nibreak; ++i) { 765 if (change & (1 << i)) { 766 tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]); 767 } 768 } 769 env->sregs[IBREAKENABLE] = v & ((1 << env->config->nibreak) - 1); 770 } 771 772 void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t i, uint32_t v) 773 { 774 if (env->sregs[IBREAKENABLE] & (1 << i) && env->sregs[IBREAKA + i] != v) { 775 tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]); 776 tb_invalidate_virtual_addr(env, v); 777 } 778 env->sregs[IBREAKA + i] = v; 779 } 780 781 static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka, 782 uint32_t dbreakc) 783 { 784 CPUState *cs = CPU(xtensa_env_get_cpu(env)); 785 int flags = BP_CPU | BP_STOP_BEFORE_ACCESS; 786 uint32_t mask = dbreakc | ~DBREAKC_MASK; 787 788 if (env->cpu_watchpoint[i]) { 789 cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]); 790 } 791 if (dbreakc & DBREAKC_SB) { 792 flags |= BP_MEM_WRITE; 793 } 794 if (dbreakc & DBREAKC_LB) { 795 flags |= BP_MEM_READ; 796 } 797 /* contiguous mask after inversion is one less than some power of 2 */ 798 if ((~mask + 1) & ~mask) { 799 qemu_log_mask(LOG_GUEST_ERROR, "DBREAKC mask is not contiguous: 0x%08x\n", dbreakc); 800 /* cut mask after the first zero bit */ 801 mask = 0xffffffff << (32 - clo32(mask)); 802 } 803 if (cpu_watchpoint_insert(cs, dbreaka & mask, ~mask + 1, 804 flags, &env->cpu_watchpoint[i])) { 805 env->cpu_watchpoint[i] = NULL; 806 qemu_log_mask(LOG_GUEST_ERROR, "Failed to set data breakpoint at 0x%08x/%d\n", 807 dbreaka & mask, ~mask + 1); 808 } 809 } 810 811 void HELPER(wsr_dbreaka)(CPUXtensaState *env, uint32_t i, uint32_t v) 812 { 813 uint32_t dbreakc = env->sregs[DBREAKC + i]; 814 815 if ((dbreakc & DBREAKC_SB_LB) && 816 env->sregs[DBREAKA + i] != v) { 817 set_dbreak(env, i, v, dbreakc); 818 } 819 env->sregs[DBREAKA + i] = v; 820 } 821 822 void HELPER(wsr_dbreakc)(CPUXtensaState *env, uint32_t i, uint32_t v) 823 { 824 if ((env->sregs[DBREAKC + i] ^ v) & (DBREAKC_SB_LB | DBREAKC_MASK)) { 825 if (v & DBREAKC_SB_LB) { 826 set_dbreak(env, i, env->sregs[DBREAKA + i], v); 827 } else { 828 if (env->cpu_watchpoint[i]) { 829 CPUState *cs = CPU(xtensa_env_get_cpu(env)); 830 831 cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]); 832 env->cpu_watchpoint[i] = NULL; 833 } 834 } 835 } 836 env->sregs[DBREAKC + i] = v; 837 } 838 839 void HELPER(wur_fcr)(CPUXtensaState *env, uint32_t v) 840 { 841 static const int rounding_mode[] = { 842 float_round_nearest_even, 843 float_round_to_zero, 844 float_round_up, 845 float_round_down, 846 }; 847 848 env->uregs[FCR] = v & 0xfffff07f; 849 set_float_rounding_mode(rounding_mode[v & 3], &env->fp_status); 850 } 851 852 float32 HELPER(abs_s)(float32 v) 853 { 854 return float32_abs(v); 855 } 856 857 float32 HELPER(neg_s)(float32 v) 858 { 859 return float32_chs(v); 860 } 861 862 float32 HELPER(add_s)(CPUXtensaState *env, float32 a, float32 b) 863 { 864 return float32_add(a, b, &env->fp_status); 865 } 866 867 float32 HELPER(sub_s)(CPUXtensaState *env, float32 a, float32 b) 868 { 869 return float32_sub(a, b, &env->fp_status); 870 } 871 872 float32 HELPER(mul_s)(CPUXtensaState *env, float32 a, float32 b) 873 { 874 return float32_mul(a, b, &env->fp_status); 875 } 876 877 float32 HELPER(madd_s)(CPUXtensaState *env, float32 a, float32 b, float32 c) 878 { 879 return float32_muladd(b, c, a, 0, 880 &env->fp_status); 881 } 882 883 float32 HELPER(msub_s)(CPUXtensaState *env, float32 a, float32 b, float32 c) 884 { 885 return float32_muladd(b, c, a, float_muladd_negate_product, 886 &env->fp_status); 887 } 888 889 uint32_t HELPER(ftoi)(float32 v, uint32_t rounding_mode, uint32_t scale) 890 { 891 float_status fp_status = {0}; 892 893 set_float_rounding_mode(rounding_mode, &fp_status); 894 return float32_to_int32( 895 float32_scalbn(v, scale, &fp_status), &fp_status); 896 } 897 898 uint32_t HELPER(ftoui)(float32 v, uint32_t rounding_mode, uint32_t scale) 899 { 900 float_status fp_status = {0}; 901 float32 res; 902 903 set_float_rounding_mode(rounding_mode, &fp_status); 904 905 res = float32_scalbn(v, scale, &fp_status); 906 907 if (float32_is_neg(v) && !float32_is_any_nan(v)) { 908 return float32_to_int32(res, &fp_status); 909 } else { 910 return float32_to_uint32(res, &fp_status); 911 } 912 } 913 914 float32 HELPER(itof)(CPUXtensaState *env, uint32_t v, uint32_t scale) 915 { 916 return float32_scalbn(int32_to_float32(v, &env->fp_status), 917 (int32_t)scale, &env->fp_status); 918 } 919 920 float32 HELPER(uitof)(CPUXtensaState *env, uint32_t v, uint32_t scale) 921 { 922 return float32_scalbn(uint32_to_float32(v, &env->fp_status), 923 (int32_t)scale, &env->fp_status); 924 } 925 926 static inline void set_br(CPUXtensaState *env, bool v, uint32_t br) 927 { 928 if (v) { 929 env->sregs[BR] |= br; 930 } else { 931 env->sregs[BR] &= ~br; 932 } 933 } 934 935 void HELPER(un_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) 936 { 937 set_br(env, float32_unordered_quiet(a, b, &env->fp_status), br); 938 } 939 940 void HELPER(oeq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) 941 { 942 set_br(env, float32_eq_quiet(a, b, &env->fp_status), br); 943 } 944 945 void HELPER(ueq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) 946 { 947 int v = float32_compare_quiet(a, b, &env->fp_status); 948 set_br(env, v == float_relation_equal || v == float_relation_unordered, br); 949 } 950 951 void HELPER(olt_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) 952 { 953 set_br(env, float32_lt_quiet(a, b, &env->fp_status), br); 954 } 955 956 void HELPER(ult_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) 957 { 958 int v = float32_compare_quiet(a, b, &env->fp_status); 959 set_br(env, v == float_relation_less || v == float_relation_unordered, br); 960 } 961 962 void HELPER(ole_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) 963 { 964 set_br(env, float32_le_quiet(a, b, &env->fp_status), br); 965 } 966 967 void HELPER(ule_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) 968 { 969 int v = float32_compare_quiet(a, b, &env->fp_status); 970 set_br(env, v != float_relation_greater, br); 971 } 972