1*fcf5ef2aSThomas Huth /* 2*fcf5ef2aSThomas Huth * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. 3*fcf5ef2aSThomas Huth * All rights reserved. 4*fcf5ef2aSThomas Huth * 5*fcf5ef2aSThomas Huth * Redistribution and use in source and binary forms, with or without 6*fcf5ef2aSThomas Huth * modification, are permitted provided that the following conditions are met: 7*fcf5ef2aSThomas Huth * * Redistributions of source code must retain the above copyright 8*fcf5ef2aSThomas Huth * notice, this list of conditions and the following disclaimer. 9*fcf5ef2aSThomas Huth * * Redistributions in binary form must reproduce the above copyright 10*fcf5ef2aSThomas Huth * notice, this list of conditions and the following disclaimer in the 11*fcf5ef2aSThomas Huth * documentation and/or other materials provided with the distribution. 12*fcf5ef2aSThomas Huth * * Neither the name of the Open Source and Linux Lab nor the 13*fcf5ef2aSThomas Huth * names of its contributors may be used to endorse or promote products 14*fcf5ef2aSThomas Huth * derived from this software without specific prior written permission. 15*fcf5ef2aSThomas Huth * 16*fcf5ef2aSThomas Huth * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17*fcf5ef2aSThomas Huth * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18*fcf5ef2aSThomas Huth * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19*fcf5ef2aSThomas Huth * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 20*fcf5ef2aSThomas Huth * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21*fcf5ef2aSThomas Huth * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22*fcf5ef2aSThomas Huth * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 23*fcf5ef2aSThomas Huth * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24*fcf5ef2aSThomas Huth * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 25*fcf5ef2aSThomas Huth * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26*fcf5ef2aSThomas Huth */ 27*fcf5ef2aSThomas Huth 28*fcf5ef2aSThomas Huth #include "qemu/osdep.h" 29*fcf5ef2aSThomas Huth #include "cpu.h" 30*fcf5ef2aSThomas Huth #include "exec/helper-proto.h" 31*fcf5ef2aSThomas Huth #include "qemu/host-utils.h" 32*fcf5ef2aSThomas Huth #include "exec/exec-all.h" 33*fcf5ef2aSThomas Huth #include "exec/cpu_ldst.h" 34*fcf5ef2aSThomas Huth #include "exec/address-spaces.h" 35*fcf5ef2aSThomas Huth #include "qemu/timer.h" 36*fcf5ef2aSThomas Huth 37*fcf5ef2aSThomas Huth void xtensa_cpu_do_unaligned_access(CPUState *cs, 38*fcf5ef2aSThomas Huth vaddr addr, MMUAccessType access_type, 39*fcf5ef2aSThomas Huth int mmu_idx, uintptr_t retaddr) 40*fcf5ef2aSThomas Huth { 41*fcf5ef2aSThomas Huth XtensaCPU *cpu = XTENSA_CPU(cs); 42*fcf5ef2aSThomas Huth CPUXtensaState *env = &cpu->env; 43*fcf5ef2aSThomas Huth 44*fcf5ef2aSThomas Huth if (xtensa_option_enabled(env->config, XTENSA_OPTION_UNALIGNED_EXCEPTION) && 45*fcf5ef2aSThomas Huth !xtensa_option_enabled(env->config, XTENSA_OPTION_HW_ALIGNMENT)) { 46*fcf5ef2aSThomas Huth cpu_restore_state(CPU(cpu), retaddr); 47*fcf5ef2aSThomas Huth HELPER(exception_cause_vaddr)(env, 48*fcf5ef2aSThomas Huth env->pc, LOAD_STORE_ALIGNMENT_CAUSE, addr); 49*fcf5ef2aSThomas Huth } 50*fcf5ef2aSThomas Huth } 51*fcf5ef2aSThomas Huth 52*fcf5ef2aSThomas Huth void tlb_fill(CPUState *cs, target_ulong vaddr, MMUAccessType access_type, 53*fcf5ef2aSThomas Huth int mmu_idx, uintptr_t retaddr) 54*fcf5ef2aSThomas Huth { 55*fcf5ef2aSThomas Huth XtensaCPU *cpu = XTENSA_CPU(cs); 56*fcf5ef2aSThomas Huth CPUXtensaState *env = &cpu->env; 57*fcf5ef2aSThomas Huth uint32_t paddr; 58*fcf5ef2aSThomas Huth uint32_t page_size; 59*fcf5ef2aSThomas Huth unsigned access; 60*fcf5ef2aSThomas Huth int ret = xtensa_get_physical_addr(env, true, vaddr, access_type, mmu_idx, 61*fcf5ef2aSThomas Huth &paddr, &page_size, &access); 62*fcf5ef2aSThomas Huth 63*fcf5ef2aSThomas Huth qemu_log_mask(CPU_LOG_MMU, "%s(%08x, %d, %d) -> %08x, ret = %d\n", 64*fcf5ef2aSThomas Huth __func__, vaddr, access_type, mmu_idx, paddr, ret); 65*fcf5ef2aSThomas Huth 66*fcf5ef2aSThomas Huth if (ret == 0) { 67*fcf5ef2aSThomas Huth tlb_set_page(cs, 68*fcf5ef2aSThomas Huth vaddr & TARGET_PAGE_MASK, 69*fcf5ef2aSThomas Huth paddr & TARGET_PAGE_MASK, 70*fcf5ef2aSThomas Huth access, mmu_idx, page_size); 71*fcf5ef2aSThomas Huth } else { 72*fcf5ef2aSThomas Huth cpu_restore_state(cs, retaddr); 73*fcf5ef2aSThomas Huth HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr); 74*fcf5ef2aSThomas Huth } 75*fcf5ef2aSThomas Huth } 76*fcf5ef2aSThomas Huth 77*fcf5ef2aSThomas Huth void xtensa_cpu_do_unassigned_access(CPUState *cs, hwaddr addr, 78*fcf5ef2aSThomas Huth bool is_write, bool is_exec, int opaque, 79*fcf5ef2aSThomas Huth unsigned size) 80*fcf5ef2aSThomas Huth { 81*fcf5ef2aSThomas Huth XtensaCPU *cpu = XTENSA_CPU(cs); 82*fcf5ef2aSThomas Huth CPUXtensaState *env = &cpu->env; 83*fcf5ef2aSThomas Huth 84*fcf5ef2aSThomas Huth HELPER(exception_cause_vaddr)(env, env->pc, 85*fcf5ef2aSThomas Huth is_exec ? 86*fcf5ef2aSThomas Huth INSTR_PIF_ADDR_ERROR_CAUSE : 87*fcf5ef2aSThomas Huth LOAD_STORE_PIF_ADDR_ERROR_CAUSE, 88*fcf5ef2aSThomas Huth is_exec ? addr : cs->mem_io_vaddr); 89*fcf5ef2aSThomas Huth } 90*fcf5ef2aSThomas Huth 91*fcf5ef2aSThomas Huth static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr) 92*fcf5ef2aSThomas Huth { 93*fcf5ef2aSThomas Huth uint32_t paddr; 94*fcf5ef2aSThomas Huth uint32_t page_size; 95*fcf5ef2aSThomas Huth unsigned access; 96*fcf5ef2aSThomas Huth int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0, 97*fcf5ef2aSThomas Huth &paddr, &page_size, &access); 98*fcf5ef2aSThomas Huth if (ret == 0) { 99*fcf5ef2aSThomas Huth tb_invalidate_phys_addr(&address_space_memory, paddr); 100*fcf5ef2aSThomas Huth } 101*fcf5ef2aSThomas Huth } 102*fcf5ef2aSThomas Huth 103*fcf5ef2aSThomas Huth void HELPER(exception)(CPUXtensaState *env, uint32_t excp) 104*fcf5ef2aSThomas Huth { 105*fcf5ef2aSThomas Huth CPUState *cs = CPU(xtensa_env_get_cpu(env)); 106*fcf5ef2aSThomas Huth 107*fcf5ef2aSThomas Huth cs->exception_index = excp; 108*fcf5ef2aSThomas Huth if (excp == EXCP_DEBUG) { 109*fcf5ef2aSThomas Huth env->exception_taken = 0; 110*fcf5ef2aSThomas Huth } 111*fcf5ef2aSThomas Huth cpu_loop_exit(cs); 112*fcf5ef2aSThomas Huth } 113*fcf5ef2aSThomas Huth 114*fcf5ef2aSThomas Huth void HELPER(exception_cause)(CPUXtensaState *env, uint32_t pc, uint32_t cause) 115*fcf5ef2aSThomas Huth { 116*fcf5ef2aSThomas Huth uint32_t vector; 117*fcf5ef2aSThomas Huth 118*fcf5ef2aSThomas Huth env->pc = pc; 119*fcf5ef2aSThomas Huth if (env->sregs[PS] & PS_EXCM) { 120*fcf5ef2aSThomas Huth if (env->config->ndepc) { 121*fcf5ef2aSThomas Huth env->sregs[DEPC] = pc; 122*fcf5ef2aSThomas Huth } else { 123*fcf5ef2aSThomas Huth env->sregs[EPC1] = pc; 124*fcf5ef2aSThomas Huth } 125*fcf5ef2aSThomas Huth vector = EXC_DOUBLE; 126*fcf5ef2aSThomas Huth } else { 127*fcf5ef2aSThomas Huth env->sregs[EPC1] = pc; 128*fcf5ef2aSThomas Huth vector = (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL; 129*fcf5ef2aSThomas Huth } 130*fcf5ef2aSThomas Huth 131*fcf5ef2aSThomas Huth env->sregs[EXCCAUSE] = cause; 132*fcf5ef2aSThomas Huth env->sregs[PS] |= PS_EXCM; 133*fcf5ef2aSThomas Huth 134*fcf5ef2aSThomas Huth HELPER(exception)(env, vector); 135*fcf5ef2aSThomas Huth } 136*fcf5ef2aSThomas Huth 137*fcf5ef2aSThomas Huth void HELPER(exception_cause_vaddr)(CPUXtensaState *env, 138*fcf5ef2aSThomas Huth uint32_t pc, uint32_t cause, uint32_t vaddr) 139*fcf5ef2aSThomas Huth { 140*fcf5ef2aSThomas Huth env->sregs[EXCVADDR] = vaddr; 141*fcf5ef2aSThomas Huth HELPER(exception_cause)(env, pc, cause); 142*fcf5ef2aSThomas Huth } 143*fcf5ef2aSThomas Huth 144*fcf5ef2aSThomas Huth void debug_exception_env(CPUXtensaState *env, uint32_t cause) 145*fcf5ef2aSThomas Huth { 146*fcf5ef2aSThomas Huth if (xtensa_get_cintlevel(env) < env->config->debug_level) { 147*fcf5ef2aSThomas Huth HELPER(debug_exception)(env, env->pc, cause); 148*fcf5ef2aSThomas Huth } 149*fcf5ef2aSThomas Huth } 150*fcf5ef2aSThomas Huth 151*fcf5ef2aSThomas Huth void HELPER(debug_exception)(CPUXtensaState *env, uint32_t pc, uint32_t cause) 152*fcf5ef2aSThomas Huth { 153*fcf5ef2aSThomas Huth unsigned level = env->config->debug_level; 154*fcf5ef2aSThomas Huth 155*fcf5ef2aSThomas Huth env->pc = pc; 156*fcf5ef2aSThomas Huth env->sregs[DEBUGCAUSE] = cause; 157*fcf5ef2aSThomas Huth env->sregs[EPC1 + level - 1] = pc; 158*fcf5ef2aSThomas Huth env->sregs[EPS2 + level - 2] = env->sregs[PS]; 159*fcf5ef2aSThomas Huth env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) | PS_EXCM | 160*fcf5ef2aSThomas Huth (level << PS_INTLEVEL_SHIFT); 161*fcf5ef2aSThomas Huth HELPER(exception)(env, EXC_DEBUG); 162*fcf5ef2aSThomas Huth } 163*fcf5ef2aSThomas Huth 164*fcf5ef2aSThomas Huth uint32_t HELPER(nsa)(uint32_t v) 165*fcf5ef2aSThomas Huth { 166*fcf5ef2aSThomas Huth if (v & 0x80000000) { 167*fcf5ef2aSThomas Huth v = ~v; 168*fcf5ef2aSThomas Huth } 169*fcf5ef2aSThomas Huth return v ? clz32(v) - 1 : 31; 170*fcf5ef2aSThomas Huth } 171*fcf5ef2aSThomas Huth 172*fcf5ef2aSThomas Huth uint32_t HELPER(nsau)(uint32_t v) 173*fcf5ef2aSThomas Huth { 174*fcf5ef2aSThomas Huth return v ? clz32(v) : 32; 175*fcf5ef2aSThomas Huth } 176*fcf5ef2aSThomas Huth 177*fcf5ef2aSThomas Huth static void copy_window_from_phys(CPUXtensaState *env, 178*fcf5ef2aSThomas Huth uint32_t window, uint32_t phys, uint32_t n) 179*fcf5ef2aSThomas Huth { 180*fcf5ef2aSThomas Huth assert(phys < env->config->nareg); 181*fcf5ef2aSThomas Huth if (phys + n <= env->config->nareg) { 182*fcf5ef2aSThomas Huth memcpy(env->regs + window, env->phys_regs + phys, 183*fcf5ef2aSThomas Huth n * sizeof(uint32_t)); 184*fcf5ef2aSThomas Huth } else { 185*fcf5ef2aSThomas Huth uint32_t n1 = env->config->nareg - phys; 186*fcf5ef2aSThomas Huth memcpy(env->regs + window, env->phys_regs + phys, 187*fcf5ef2aSThomas Huth n1 * sizeof(uint32_t)); 188*fcf5ef2aSThomas Huth memcpy(env->regs + window + n1, env->phys_regs, 189*fcf5ef2aSThomas Huth (n - n1) * sizeof(uint32_t)); 190*fcf5ef2aSThomas Huth } 191*fcf5ef2aSThomas Huth } 192*fcf5ef2aSThomas Huth 193*fcf5ef2aSThomas Huth static void copy_phys_from_window(CPUXtensaState *env, 194*fcf5ef2aSThomas Huth uint32_t phys, uint32_t window, uint32_t n) 195*fcf5ef2aSThomas Huth { 196*fcf5ef2aSThomas Huth assert(phys < env->config->nareg); 197*fcf5ef2aSThomas Huth if (phys + n <= env->config->nareg) { 198*fcf5ef2aSThomas Huth memcpy(env->phys_regs + phys, env->regs + window, 199*fcf5ef2aSThomas Huth n * sizeof(uint32_t)); 200*fcf5ef2aSThomas Huth } else { 201*fcf5ef2aSThomas Huth uint32_t n1 = env->config->nareg - phys; 202*fcf5ef2aSThomas Huth memcpy(env->phys_regs + phys, env->regs + window, 203*fcf5ef2aSThomas Huth n1 * sizeof(uint32_t)); 204*fcf5ef2aSThomas Huth memcpy(env->phys_regs, env->regs + window + n1, 205*fcf5ef2aSThomas Huth (n - n1) * sizeof(uint32_t)); 206*fcf5ef2aSThomas Huth } 207*fcf5ef2aSThomas Huth } 208*fcf5ef2aSThomas Huth 209*fcf5ef2aSThomas Huth 210*fcf5ef2aSThomas Huth static inline unsigned windowbase_bound(unsigned a, const CPUXtensaState *env) 211*fcf5ef2aSThomas Huth { 212*fcf5ef2aSThomas Huth return a & (env->config->nareg / 4 - 1); 213*fcf5ef2aSThomas Huth } 214*fcf5ef2aSThomas Huth 215*fcf5ef2aSThomas Huth static inline unsigned windowstart_bit(unsigned a, const CPUXtensaState *env) 216*fcf5ef2aSThomas Huth { 217*fcf5ef2aSThomas Huth return 1 << windowbase_bound(a, env); 218*fcf5ef2aSThomas Huth } 219*fcf5ef2aSThomas Huth 220*fcf5ef2aSThomas Huth void xtensa_sync_window_from_phys(CPUXtensaState *env) 221*fcf5ef2aSThomas Huth { 222*fcf5ef2aSThomas Huth copy_window_from_phys(env, 0, env->sregs[WINDOW_BASE] * 4, 16); 223*fcf5ef2aSThomas Huth } 224*fcf5ef2aSThomas Huth 225*fcf5ef2aSThomas Huth void xtensa_sync_phys_from_window(CPUXtensaState *env) 226*fcf5ef2aSThomas Huth { 227*fcf5ef2aSThomas Huth copy_phys_from_window(env, env->sregs[WINDOW_BASE] * 4, 0, 16); 228*fcf5ef2aSThomas Huth } 229*fcf5ef2aSThomas Huth 230*fcf5ef2aSThomas Huth static void rotate_window_abs(CPUXtensaState *env, uint32_t position) 231*fcf5ef2aSThomas Huth { 232*fcf5ef2aSThomas Huth xtensa_sync_phys_from_window(env); 233*fcf5ef2aSThomas Huth env->sregs[WINDOW_BASE] = windowbase_bound(position, env); 234*fcf5ef2aSThomas Huth xtensa_sync_window_from_phys(env); 235*fcf5ef2aSThomas Huth } 236*fcf5ef2aSThomas Huth 237*fcf5ef2aSThomas Huth static void rotate_window(CPUXtensaState *env, uint32_t delta) 238*fcf5ef2aSThomas Huth { 239*fcf5ef2aSThomas Huth rotate_window_abs(env, env->sregs[WINDOW_BASE] + delta); 240*fcf5ef2aSThomas Huth } 241*fcf5ef2aSThomas Huth 242*fcf5ef2aSThomas Huth void HELPER(wsr_windowbase)(CPUXtensaState *env, uint32_t v) 243*fcf5ef2aSThomas Huth { 244*fcf5ef2aSThomas Huth rotate_window_abs(env, v); 245*fcf5ef2aSThomas Huth } 246*fcf5ef2aSThomas Huth 247*fcf5ef2aSThomas Huth void HELPER(entry)(CPUXtensaState *env, uint32_t pc, uint32_t s, uint32_t imm) 248*fcf5ef2aSThomas Huth { 249*fcf5ef2aSThomas Huth int callinc = (env->sregs[PS] & PS_CALLINC) >> PS_CALLINC_SHIFT; 250*fcf5ef2aSThomas Huth if (s > 3 || ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) { 251*fcf5ef2aSThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Illegal entry instruction(pc = %08x), PS = %08x\n", 252*fcf5ef2aSThomas Huth pc, env->sregs[PS]); 253*fcf5ef2aSThomas Huth HELPER(exception_cause)(env, pc, ILLEGAL_INSTRUCTION_CAUSE); 254*fcf5ef2aSThomas Huth } else { 255*fcf5ef2aSThomas Huth uint32_t windowstart = xtensa_replicate_windowstart(env) >> 256*fcf5ef2aSThomas Huth (env->sregs[WINDOW_BASE] + 1); 257*fcf5ef2aSThomas Huth 258*fcf5ef2aSThomas Huth if (windowstart & ((1 << callinc) - 1)) { 259*fcf5ef2aSThomas Huth HELPER(window_check)(env, pc, callinc); 260*fcf5ef2aSThomas Huth } 261*fcf5ef2aSThomas Huth env->regs[(callinc << 2) | (s & 3)] = env->regs[s] - (imm << 3); 262*fcf5ef2aSThomas Huth rotate_window(env, callinc); 263*fcf5ef2aSThomas Huth env->sregs[WINDOW_START] |= 264*fcf5ef2aSThomas Huth windowstart_bit(env->sregs[WINDOW_BASE], env); 265*fcf5ef2aSThomas Huth } 266*fcf5ef2aSThomas Huth } 267*fcf5ef2aSThomas Huth 268*fcf5ef2aSThomas Huth void HELPER(window_check)(CPUXtensaState *env, uint32_t pc, uint32_t w) 269*fcf5ef2aSThomas Huth { 270*fcf5ef2aSThomas Huth uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env); 271*fcf5ef2aSThomas Huth uint32_t windowstart = xtensa_replicate_windowstart(env) >> 272*fcf5ef2aSThomas Huth (env->sregs[WINDOW_BASE] + 1); 273*fcf5ef2aSThomas Huth uint32_t n = ctz32(windowstart) + 1; 274*fcf5ef2aSThomas Huth 275*fcf5ef2aSThomas Huth assert(n <= w); 276*fcf5ef2aSThomas Huth 277*fcf5ef2aSThomas Huth rotate_window(env, n); 278*fcf5ef2aSThomas Huth env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) | 279*fcf5ef2aSThomas Huth (windowbase << PS_OWB_SHIFT) | PS_EXCM; 280*fcf5ef2aSThomas Huth env->sregs[EPC1] = env->pc = pc; 281*fcf5ef2aSThomas Huth 282*fcf5ef2aSThomas Huth switch (ctz32(windowstart >> n)) { 283*fcf5ef2aSThomas Huth case 0: 284*fcf5ef2aSThomas Huth HELPER(exception)(env, EXC_WINDOW_OVERFLOW4); 285*fcf5ef2aSThomas Huth break; 286*fcf5ef2aSThomas Huth case 1: 287*fcf5ef2aSThomas Huth HELPER(exception)(env, EXC_WINDOW_OVERFLOW8); 288*fcf5ef2aSThomas Huth break; 289*fcf5ef2aSThomas Huth default: 290*fcf5ef2aSThomas Huth HELPER(exception)(env, EXC_WINDOW_OVERFLOW12); 291*fcf5ef2aSThomas Huth break; 292*fcf5ef2aSThomas Huth } 293*fcf5ef2aSThomas Huth } 294*fcf5ef2aSThomas Huth 295*fcf5ef2aSThomas Huth uint32_t HELPER(retw)(CPUXtensaState *env, uint32_t pc) 296*fcf5ef2aSThomas Huth { 297*fcf5ef2aSThomas Huth int n = (env->regs[0] >> 30) & 0x3; 298*fcf5ef2aSThomas Huth int m = 0; 299*fcf5ef2aSThomas Huth uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env); 300*fcf5ef2aSThomas Huth uint32_t windowstart = env->sregs[WINDOW_START]; 301*fcf5ef2aSThomas Huth uint32_t ret_pc = 0; 302*fcf5ef2aSThomas Huth 303*fcf5ef2aSThomas Huth if (windowstart & windowstart_bit(windowbase - 1, env)) { 304*fcf5ef2aSThomas Huth m = 1; 305*fcf5ef2aSThomas Huth } else if (windowstart & windowstart_bit(windowbase - 2, env)) { 306*fcf5ef2aSThomas Huth m = 2; 307*fcf5ef2aSThomas Huth } else if (windowstart & windowstart_bit(windowbase - 3, env)) { 308*fcf5ef2aSThomas Huth m = 3; 309*fcf5ef2aSThomas Huth } 310*fcf5ef2aSThomas Huth 311*fcf5ef2aSThomas Huth if (n == 0 || (m != 0 && m != n) || 312*fcf5ef2aSThomas Huth ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) { 313*fcf5ef2aSThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Illegal retw instruction(pc = %08x), " 314*fcf5ef2aSThomas Huth "PS = %08x, m = %d, n = %d\n", 315*fcf5ef2aSThomas Huth pc, env->sregs[PS], m, n); 316*fcf5ef2aSThomas Huth HELPER(exception_cause)(env, pc, ILLEGAL_INSTRUCTION_CAUSE); 317*fcf5ef2aSThomas Huth } else { 318*fcf5ef2aSThomas Huth int owb = windowbase; 319*fcf5ef2aSThomas Huth 320*fcf5ef2aSThomas Huth ret_pc = (pc & 0xc0000000) | (env->regs[0] & 0x3fffffff); 321*fcf5ef2aSThomas Huth 322*fcf5ef2aSThomas Huth rotate_window(env, -n); 323*fcf5ef2aSThomas Huth if (windowstart & windowstart_bit(env->sregs[WINDOW_BASE], env)) { 324*fcf5ef2aSThomas Huth env->sregs[WINDOW_START] &= ~windowstart_bit(owb, env); 325*fcf5ef2aSThomas Huth } else { 326*fcf5ef2aSThomas Huth /* window underflow */ 327*fcf5ef2aSThomas Huth env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) | 328*fcf5ef2aSThomas Huth (windowbase << PS_OWB_SHIFT) | PS_EXCM; 329*fcf5ef2aSThomas Huth env->sregs[EPC1] = env->pc = pc; 330*fcf5ef2aSThomas Huth 331*fcf5ef2aSThomas Huth if (n == 1) { 332*fcf5ef2aSThomas Huth HELPER(exception)(env, EXC_WINDOW_UNDERFLOW4); 333*fcf5ef2aSThomas Huth } else if (n == 2) { 334*fcf5ef2aSThomas Huth HELPER(exception)(env, EXC_WINDOW_UNDERFLOW8); 335*fcf5ef2aSThomas Huth } else if (n == 3) { 336*fcf5ef2aSThomas Huth HELPER(exception)(env, EXC_WINDOW_UNDERFLOW12); 337*fcf5ef2aSThomas Huth } 338*fcf5ef2aSThomas Huth } 339*fcf5ef2aSThomas Huth } 340*fcf5ef2aSThomas Huth return ret_pc; 341*fcf5ef2aSThomas Huth } 342*fcf5ef2aSThomas Huth 343*fcf5ef2aSThomas Huth void HELPER(rotw)(CPUXtensaState *env, uint32_t imm4) 344*fcf5ef2aSThomas Huth { 345*fcf5ef2aSThomas Huth rotate_window(env, imm4); 346*fcf5ef2aSThomas Huth } 347*fcf5ef2aSThomas Huth 348*fcf5ef2aSThomas Huth void HELPER(restore_owb)(CPUXtensaState *env) 349*fcf5ef2aSThomas Huth { 350*fcf5ef2aSThomas Huth rotate_window_abs(env, (env->sregs[PS] & PS_OWB) >> PS_OWB_SHIFT); 351*fcf5ef2aSThomas Huth } 352*fcf5ef2aSThomas Huth 353*fcf5ef2aSThomas Huth void HELPER(movsp)(CPUXtensaState *env, uint32_t pc) 354*fcf5ef2aSThomas Huth { 355*fcf5ef2aSThomas Huth if ((env->sregs[WINDOW_START] & 356*fcf5ef2aSThomas Huth (windowstart_bit(env->sregs[WINDOW_BASE] - 3, env) | 357*fcf5ef2aSThomas Huth windowstart_bit(env->sregs[WINDOW_BASE] - 2, env) | 358*fcf5ef2aSThomas Huth windowstart_bit(env->sregs[WINDOW_BASE] - 1, env))) == 0) { 359*fcf5ef2aSThomas Huth HELPER(exception_cause)(env, pc, ALLOCA_CAUSE); 360*fcf5ef2aSThomas Huth } 361*fcf5ef2aSThomas Huth } 362*fcf5ef2aSThomas Huth 363*fcf5ef2aSThomas Huth void HELPER(wsr_lbeg)(CPUXtensaState *env, uint32_t v) 364*fcf5ef2aSThomas Huth { 365*fcf5ef2aSThomas Huth if (env->sregs[LBEG] != v) { 366*fcf5ef2aSThomas Huth tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1); 367*fcf5ef2aSThomas Huth env->sregs[LBEG] = v; 368*fcf5ef2aSThomas Huth } 369*fcf5ef2aSThomas Huth } 370*fcf5ef2aSThomas Huth 371*fcf5ef2aSThomas Huth void HELPER(wsr_lend)(CPUXtensaState *env, uint32_t v) 372*fcf5ef2aSThomas Huth { 373*fcf5ef2aSThomas Huth if (env->sregs[LEND] != v) { 374*fcf5ef2aSThomas Huth tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1); 375*fcf5ef2aSThomas Huth env->sregs[LEND] = v; 376*fcf5ef2aSThomas Huth tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1); 377*fcf5ef2aSThomas Huth } 378*fcf5ef2aSThomas Huth } 379*fcf5ef2aSThomas Huth 380*fcf5ef2aSThomas Huth void HELPER(dump_state)(CPUXtensaState *env) 381*fcf5ef2aSThomas Huth { 382*fcf5ef2aSThomas Huth XtensaCPU *cpu = xtensa_env_get_cpu(env); 383*fcf5ef2aSThomas Huth 384*fcf5ef2aSThomas Huth cpu_dump_state(CPU(cpu), stderr, fprintf, 0); 385*fcf5ef2aSThomas Huth } 386*fcf5ef2aSThomas Huth 387*fcf5ef2aSThomas Huth void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, uint32_t intlevel) 388*fcf5ef2aSThomas Huth { 389*fcf5ef2aSThomas Huth CPUState *cpu; 390*fcf5ef2aSThomas Huth 391*fcf5ef2aSThomas Huth env->pc = pc; 392*fcf5ef2aSThomas Huth env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) | 393*fcf5ef2aSThomas Huth (intlevel << PS_INTLEVEL_SHIFT); 394*fcf5ef2aSThomas Huth check_interrupts(env); 395*fcf5ef2aSThomas Huth if (env->pending_irq_level) { 396*fcf5ef2aSThomas Huth cpu_loop_exit(CPU(xtensa_env_get_cpu(env))); 397*fcf5ef2aSThomas Huth return; 398*fcf5ef2aSThomas Huth } 399*fcf5ef2aSThomas Huth 400*fcf5ef2aSThomas Huth cpu = CPU(xtensa_env_get_cpu(env)); 401*fcf5ef2aSThomas Huth env->halt_clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 402*fcf5ef2aSThomas Huth cpu->halted = 1; 403*fcf5ef2aSThomas Huth if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT)) { 404*fcf5ef2aSThomas Huth xtensa_rearm_ccompare_timer(env); 405*fcf5ef2aSThomas Huth } 406*fcf5ef2aSThomas Huth HELPER(exception)(env, EXCP_HLT); 407*fcf5ef2aSThomas Huth } 408*fcf5ef2aSThomas Huth 409*fcf5ef2aSThomas Huth void HELPER(timer_irq)(CPUXtensaState *env, uint32_t id, uint32_t active) 410*fcf5ef2aSThomas Huth { 411*fcf5ef2aSThomas Huth xtensa_timer_irq(env, id, active); 412*fcf5ef2aSThomas Huth } 413*fcf5ef2aSThomas Huth 414*fcf5ef2aSThomas Huth void HELPER(advance_ccount)(CPUXtensaState *env, uint32_t d) 415*fcf5ef2aSThomas Huth { 416*fcf5ef2aSThomas Huth xtensa_advance_ccount(env, d); 417*fcf5ef2aSThomas Huth } 418*fcf5ef2aSThomas Huth 419*fcf5ef2aSThomas Huth void HELPER(check_interrupts)(CPUXtensaState *env) 420*fcf5ef2aSThomas Huth { 421*fcf5ef2aSThomas Huth check_interrupts(env); 422*fcf5ef2aSThomas Huth } 423*fcf5ef2aSThomas Huth 424*fcf5ef2aSThomas Huth void HELPER(itlb_hit_test)(CPUXtensaState *env, uint32_t vaddr) 425*fcf5ef2aSThomas Huth { 426*fcf5ef2aSThomas Huth get_page_addr_code(env, vaddr); 427*fcf5ef2aSThomas Huth } 428*fcf5ef2aSThomas Huth 429*fcf5ef2aSThomas Huth /*! 430*fcf5ef2aSThomas Huth * Check vaddr accessibility/cache attributes and raise an exception if 431*fcf5ef2aSThomas Huth * specified by the ATOMCTL SR. 432*fcf5ef2aSThomas Huth * 433*fcf5ef2aSThomas Huth * Note: local memory exclusion is not implemented 434*fcf5ef2aSThomas Huth */ 435*fcf5ef2aSThomas Huth void HELPER(check_atomctl)(CPUXtensaState *env, uint32_t pc, uint32_t vaddr) 436*fcf5ef2aSThomas Huth { 437*fcf5ef2aSThomas Huth uint32_t paddr, page_size, access; 438*fcf5ef2aSThomas Huth uint32_t atomctl = env->sregs[ATOMCTL]; 439*fcf5ef2aSThomas Huth int rc = xtensa_get_physical_addr(env, true, vaddr, 1, 440*fcf5ef2aSThomas Huth xtensa_get_cring(env), &paddr, &page_size, &access); 441*fcf5ef2aSThomas Huth 442*fcf5ef2aSThomas Huth /* 443*fcf5ef2aSThomas Huth * s32c1i never causes LOAD_PROHIBITED_CAUSE exceptions, 444*fcf5ef2aSThomas Huth * see opcode description in the ISA 445*fcf5ef2aSThomas Huth */ 446*fcf5ef2aSThomas Huth if (rc == 0 && 447*fcf5ef2aSThomas Huth (access & (PAGE_READ | PAGE_WRITE)) != (PAGE_READ | PAGE_WRITE)) { 448*fcf5ef2aSThomas Huth rc = STORE_PROHIBITED_CAUSE; 449*fcf5ef2aSThomas Huth } 450*fcf5ef2aSThomas Huth 451*fcf5ef2aSThomas Huth if (rc) { 452*fcf5ef2aSThomas Huth HELPER(exception_cause_vaddr)(env, pc, rc, vaddr); 453*fcf5ef2aSThomas Huth } 454*fcf5ef2aSThomas Huth 455*fcf5ef2aSThomas Huth /* 456*fcf5ef2aSThomas Huth * When data cache is not configured use ATOMCTL bypass field. 457*fcf5ef2aSThomas Huth * See ISA, 4.3.12.4 The Atomic Operation Control Register (ATOMCTL) 458*fcf5ef2aSThomas Huth * under the Conditional Store Option. 459*fcf5ef2aSThomas Huth */ 460*fcf5ef2aSThomas Huth if (!xtensa_option_enabled(env->config, XTENSA_OPTION_DCACHE)) { 461*fcf5ef2aSThomas Huth access = PAGE_CACHE_BYPASS; 462*fcf5ef2aSThomas Huth } 463*fcf5ef2aSThomas Huth 464*fcf5ef2aSThomas Huth switch (access & PAGE_CACHE_MASK) { 465*fcf5ef2aSThomas Huth case PAGE_CACHE_WB: 466*fcf5ef2aSThomas Huth atomctl >>= 2; 467*fcf5ef2aSThomas Huth /* fall through */ 468*fcf5ef2aSThomas Huth case PAGE_CACHE_WT: 469*fcf5ef2aSThomas Huth atomctl >>= 2; 470*fcf5ef2aSThomas Huth /* fall through */ 471*fcf5ef2aSThomas Huth case PAGE_CACHE_BYPASS: 472*fcf5ef2aSThomas Huth if ((atomctl & 0x3) == 0) { 473*fcf5ef2aSThomas Huth HELPER(exception_cause_vaddr)(env, pc, 474*fcf5ef2aSThomas Huth LOAD_STORE_ERROR_CAUSE, vaddr); 475*fcf5ef2aSThomas Huth } 476*fcf5ef2aSThomas Huth break; 477*fcf5ef2aSThomas Huth 478*fcf5ef2aSThomas Huth case PAGE_CACHE_ISOLATE: 479*fcf5ef2aSThomas Huth HELPER(exception_cause_vaddr)(env, pc, 480*fcf5ef2aSThomas Huth LOAD_STORE_ERROR_CAUSE, vaddr); 481*fcf5ef2aSThomas Huth break; 482*fcf5ef2aSThomas Huth 483*fcf5ef2aSThomas Huth default: 484*fcf5ef2aSThomas Huth break; 485*fcf5ef2aSThomas Huth } 486*fcf5ef2aSThomas Huth } 487*fcf5ef2aSThomas Huth 488*fcf5ef2aSThomas Huth void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v) 489*fcf5ef2aSThomas Huth { 490*fcf5ef2aSThomas Huth XtensaCPU *cpu = xtensa_env_get_cpu(env); 491*fcf5ef2aSThomas Huth 492*fcf5ef2aSThomas Huth v = (v & 0xffffff00) | 0x1; 493*fcf5ef2aSThomas Huth if (v != env->sregs[RASID]) { 494*fcf5ef2aSThomas Huth env->sregs[RASID] = v; 495*fcf5ef2aSThomas Huth tlb_flush(CPU(cpu), 1); 496*fcf5ef2aSThomas Huth } 497*fcf5ef2aSThomas Huth } 498*fcf5ef2aSThomas Huth 499*fcf5ef2aSThomas Huth static uint32_t get_page_size(const CPUXtensaState *env, bool dtlb, uint32_t way) 500*fcf5ef2aSThomas Huth { 501*fcf5ef2aSThomas Huth uint32_t tlbcfg = env->sregs[dtlb ? DTLBCFG : ITLBCFG]; 502*fcf5ef2aSThomas Huth 503*fcf5ef2aSThomas Huth switch (way) { 504*fcf5ef2aSThomas Huth case 4: 505*fcf5ef2aSThomas Huth return (tlbcfg >> 16) & 0x3; 506*fcf5ef2aSThomas Huth 507*fcf5ef2aSThomas Huth case 5: 508*fcf5ef2aSThomas Huth return (tlbcfg >> 20) & 0x1; 509*fcf5ef2aSThomas Huth 510*fcf5ef2aSThomas Huth case 6: 511*fcf5ef2aSThomas Huth return (tlbcfg >> 24) & 0x1; 512*fcf5ef2aSThomas Huth 513*fcf5ef2aSThomas Huth default: 514*fcf5ef2aSThomas Huth return 0; 515*fcf5ef2aSThomas Huth } 516*fcf5ef2aSThomas Huth } 517*fcf5ef2aSThomas Huth 518*fcf5ef2aSThomas Huth /*! 519*fcf5ef2aSThomas Huth * Get bit mask for the virtual address bits translated by the TLB way 520*fcf5ef2aSThomas Huth */ 521*fcf5ef2aSThomas Huth uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way) 522*fcf5ef2aSThomas Huth { 523*fcf5ef2aSThomas Huth if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 524*fcf5ef2aSThomas Huth bool varway56 = dtlb ? 525*fcf5ef2aSThomas Huth env->config->dtlb.varway56 : 526*fcf5ef2aSThomas Huth env->config->itlb.varway56; 527*fcf5ef2aSThomas Huth 528*fcf5ef2aSThomas Huth switch (way) { 529*fcf5ef2aSThomas Huth case 4: 530*fcf5ef2aSThomas Huth return 0xfff00000 << get_page_size(env, dtlb, way) * 2; 531*fcf5ef2aSThomas Huth 532*fcf5ef2aSThomas Huth case 5: 533*fcf5ef2aSThomas Huth if (varway56) { 534*fcf5ef2aSThomas Huth return 0xf8000000 << get_page_size(env, dtlb, way); 535*fcf5ef2aSThomas Huth } else { 536*fcf5ef2aSThomas Huth return 0xf8000000; 537*fcf5ef2aSThomas Huth } 538*fcf5ef2aSThomas Huth 539*fcf5ef2aSThomas Huth case 6: 540*fcf5ef2aSThomas Huth if (varway56) { 541*fcf5ef2aSThomas Huth return 0xf0000000 << (1 - get_page_size(env, dtlb, way)); 542*fcf5ef2aSThomas Huth } else { 543*fcf5ef2aSThomas Huth return 0xf0000000; 544*fcf5ef2aSThomas Huth } 545*fcf5ef2aSThomas Huth 546*fcf5ef2aSThomas Huth default: 547*fcf5ef2aSThomas Huth return 0xfffff000; 548*fcf5ef2aSThomas Huth } 549*fcf5ef2aSThomas Huth } else { 550*fcf5ef2aSThomas Huth return REGION_PAGE_MASK; 551*fcf5ef2aSThomas Huth } 552*fcf5ef2aSThomas Huth } 553*fcf5ef2aSThomas Huth 554*fcf5ef2aSThomas Huth /*! 555*fcf5ef2aSThomas Huth * Get bit mask for the 'VPN without index' field. 556*fcf5ef2aSThomas Huth * See ISA, 4.6.5.6, data format for RxTLB0 557*fcf5ef2aSThomas Huth */ 558*fcf5ef2aSThomas Huth static uint32_t get_vpn_mask(const CPUXtensaState *env, bool dtlb, uint32_t way) 559*fcf5ef2aSThomas Huth { 560*fcf5ef2aSThomas Huth if (way < 4) { 561*fcf5ef2aSThomas Huth bool is32 = (dtlb ? 562*fcf5ef2aSThomas Huth env->config->dtlb.nrefillentries : 563*fcf5ef2aSThomas Huth env->config->itlb.nrefillentries) == 32; 564*fcf5ef2aSThomas Huth return is32 ? 0xffff8000 : 0xffffc000; 565*fcf5ef2aSThomas Huth } else if (way == 4) { 566*fcf5ef2aSThomas Huth return xtensa_tlb_get_addr_mask(env, dtlb, way) << 2; 567*fcf5ef2aSThomas Huth } else if (way <= 6) { 568*fcf5ef2aSThomas Huth uint32_t mask = xtensa_tlb_get_addr_mask(env, dtlb, way); 569*fcf5ef2aSThomas Huth bool varway56 = dtlb ? 570*fcf5ef2aSThomas Huth env->config->dtlb.varway56 : 571*fcf5ef2aSThomas Huth env->config->itlb.varway56; 572*fcf5ef2aSThomas Huth 573*fcf5ef2aSThomas Huth if (varway56) { 574*fcf5ef2aSThomas Huth return mask << (way == 5 ? 2 : 3); 575*fcf5ef2aSThomas Huth } else { 576*fcf5ef2aSThomas Huth return mask << 1; 577*fcf5ef2aSThomas Huth } 578*fcf5ef2aSThomas Huth } else { 579*fcf5ef2aSThomas Huth return 0xfffff000; 580*fcf5ef2aSThomas Huth } 581*fcf5ef2aSThomas Huth } 582*fcf5ef2aSThomas Huth 583*fcf5ef2aSThomas Huth /*! 584*fcf5ef2aSThomas Huth * Split virtual address into VPN (with index) and entry index 585*fcf5ef2aSThomas Huth * for the given TLB way 586*fcf5ef2aSThomas Huth */ 587*fcf5ef2aSThomas Huth void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb, 588*fcf5ef2aSThomas Huth uint32_t *vpn, uint32_t wi, uint32_t *ei) 589*fcf5ef2aSThomas Huth { 590*fcf5ef2aSThomas Huth bool varway56 = dtlb ? 591*fcf5ef2aSThomas Huth env->config->dtlb.varway56 : 592*fcf5ef2aSThomas Huth env->config->itlb.varway56; 593*fcf5ef2aSThomas Huth 594*fcf5ef2aSThomas Huth if (!dtlb) { 595*fcf5ef2aSThomas Huth wi &= 7; 596*fcf5ef2aSThomas Huth } 597*fcf5ef2aSThomas Huth 598*fcf5ef2aSThomas Huth if (wi < 4) { 599*fcf5ef2aSThomas Huth bool is32 = (dtlb ? 600*fcf5ef2aSThomas Huth env->config->dtlb.nrefillentries : 601*fcf5ef2aSThomas Huth env->config->itlb.nrefillentries) == 32; 602*fcf5ef2aSThomas Huth *ei = (v >> 12) & (is32 ? 0x7 : 0x3); 603*fcf5ef2aSThomas Huth } else { 604*fcf5ef2aSThomas Huth switch (wi) { 605*fcf5ef2aSThomas Huth case 4: 606*fcf5ef2aSThomas Huth { 607*fcf5ef2aSThomas Huth uint32_t eibase = 20 + get_page_size(env, dtlb, wi) * 2; 608*fcf5ef2aSThomas Huth *ei = (v >> eibase) & 0x3; 609*fcf5ef2aSThomas Huth } 610*fcf5ef2aSThomas Huth break; 611*fcf5ef2aSThomas Huth 612*fcf5ef2aSThomas Huth case 5: 613*fcf5ef2aSThomas Huth if (varway56) { 614*fcf5ef2aSThomas Huth uint32_t eibase = 27 + get_page_size(env, dtlb, wi); 615*fcf5ef2aSThomas Huth *ei = (v >> eibase) & 0x3; 616*fcf5ef2aSThomas Huth } else { 617*fcf5ef2aSThomas Huth *ei = (v >> 27) & 0x1; 618*fcf5ef2aSThomas Huth } 619*fcf5ef2aSThomas Huth break; 620*fcf5ef2aSThomas Huth 621*fcf5ef2aSThomas Huth case 6: 622*fcf5ef2aSThomas Huth if (varway56) { 623*fcf5ef2aSThomas Huth uint32_t eibase = 29 - get_page_size(env, dtlb, wi); 624*fcf5ef2aSThomas Huth *ei = (v >> eibase) & 0x7; 625*fcf5ef2aSThomas Huth } else { 626*fcf5ef2aSThomas Huth *ei = (v >> 28) & 0x1; 627*fcf5ef2aSThomas Huth } 628*fcf5ef2aSThomas Huth break; 629*fcf5ef2aSThomas Huth 630*fcf5ef2aSThomas Huth default: 631*fcf5ef2aSThomas Huth *ei = 0; 632*fcf5ef2aSThomas Huth break; 633*fcf5ef2aSThomas Huth } 634*fcf5ef2aSThomas Huth } 635*fcf5ef2aSThomas Huth *vpn = v & xtensa_tlb_get_addr_mask(env, dtlb, wi); 636*fcf5ef2aSThomas Huth } 637*fcf5ef2aSThomas Huth 638*fcf5ef2aSThomas Huth /*! 639*fcf5ef2aSThomas Huth * Split TLB address into TLB way, entry index and VPN (with index). 640*fcf5ef2aSThomas Huth * See ISA, 4.6.5.5 - 4.6.5.8 for the TLB addressing format 641*fcf5ef2aSThomas Huth */ 642*fcf5ef2aSThomas Huth static void split_tlb_entry_spec(CPUXtensaState *env, uint32_t v, bool dtlb, 643*fcf5ef2aSThomas Huth uint32_t *vpn, uint32_t *wi, uint32_t *ei) 644*fcf5ef2aSThomas Huth { 645*fcf5ef2aSThomas Huth if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 646*fcf5ef2aSThomas Huth *wi = v & (dtlb ? 0xf : 0x7); 647*fcf5ef2aSThomas Huth split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei); 648*fcf5ef2aSThomas Huth } else { 649*fcf5ef2aSThomas Huth *vpn = v & REGION_PAGE_MASK; 650*fcf5ef2aSThomas Huth *wi = 0; 651*fcf5ef2aSThomas Huth *ei = (v >> 29) & 0x7; 652*fcf5ef2aSThomas Huth } 653*fcf5ef2aSThomas Huth } 654*fcf5ef2aSThomas Huth 655*fcf5ef2aSThomas Huth static xtensa_tlb_entry *get_tlb_entry(CPUXtensaState *env, 656*fcf5ef2aSThomas Huth uint32_t v, bool dtlb, uint32_t *pwi) 657*fcf5ef2aSThomas Huth { 658*fcf5ef2aSThomas Huth uint32_t vpn; 659*fcf5ef2aSThomas Huth uint32_t wi; 660*fcf5ef2aSThomas Huth uint32_t ei; 661*fcf5ef2aSThomas Huth 662*fcf5ef2aSThomas Huth split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei); 663*fcf5ef2aSThomas Huth if (pwi) { 664*fcf5ef2aSThomas Huth *pwi = wi; 665*fcf5ef2aSThomas Huth } 666*fcf5ef2aSThomas Huth return xtensa_tlb_get_entry(env, dtlb, wi, ei); 667*fcf5ef2aSThomas Huth } 668*fcf5ef2aSThomas Huth 669*fcf5ef2aSThomas Huth uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) 670*fcf5ef2aSThomas Huth { 671*fcf5ef2aSThomas Huth if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 672*fcf5ef2aSThomas Huth uint32_t wi; 673*fcf5ef2aSThomas Huth const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi); 674*fcf5ef2aSThomas Huth return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->asid; 675*fcf5ef2aSThomas Huth } else { 676*fcf5ef2aSThomas Huth return v & REGION_PAGE_MASK; 677*fcf5ef2aSThomas Huth } 678*fcf5ef2aSThomas Huth } 679*fcf5ef2aSThomas Huth 680*fcf5ef2aSThomas Huth uint32_t HELPER(rtlb1)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) 681*fcf5ef2aSThomas Huth { 682*fcf5ef2aSThomas Huth const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, NULL); 683*fcf5ef2aSThomas Huth return entry->paddr | entry->attr; 684*fcf5ef2aSThomas Huth } 685*fcf5ef2aSThomas Huth 686*fcf5ef2aSThomas Huth void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) 687*fcf5ef2aSThomas Huth { 688*fcf5ef2aSThomas Huth if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 689*fcf5ef2aSThomas Huth uint32_t wi; 690*fcf5ef2aSThomas Huth xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi); 691*fcf5ef2aSThomas Huth if (entry->variable && entry->asid) { 692*fcf5ef2aSThomas Huth tlb_flush_page(CPU(xtensa_env_get_cpu(env)), entry->vaddr); 693*fcf5ef2aSThomas Huth entry->asid = 0; 694*fcf5ef2aSThomas Huth } 695*fcf5ef2aSThomas Huth } 696*fcf5ef2aSThomas Huth } 697*fcf5ef2aSThomas Huth 698*fcf5ef2aSThomas Huth uint32_t HELPER(ptlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) 699*fcf5ef2aSThomas Huth { 700*fcf5ef2aSThomas Huth if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 701*fcf5ef2aSThomas Huth uint32_t wi; 702*fcf5ef2aSThomas Huth uint32_t ei; 703*fcf5ef2aSThomas Huth uint8_t ring; 704*fcf5ef2aSThomas Huth int res = xtensa_tlb_lookup(env, v, dtlb, &wi, &ei, &ring); 705*fcf5ef2aSThomas Huth 706*fcf5ef2aSThomas Huth switch (res) { 707*fcf5ef2aSThomas Huth case 0: 708*fcf5ef2aSThomas Huth if (ring >= xtensa_get_ring(env)) { 709*fcf5ef2aSThomas Huth return (v & 0xfffff000) | wi | (dtlb ? 0x10 : 0x8); 710*fcf5ef2aSThomas Huth } 711*fcf5ef2aSThomas Huth break; 712*fcf5ef2aSThomas Huth 713*fcf5ef2aSThomas Huth case INST_TLB_MULTI_HIT_CAUSE: 714*fcf5ef2aSThomas Huth case LOAD_STORE_TLB_MULTI_HIT_CAUSE: 715*fcf5ef2aSThomas Huth HELPER(exception_cause_vaddr)(env, env->pc, res, v); 716*fcf5ef2aSThomas Huth break; 717*fcf5ef2aSThomas Huth } 718*fcf5ef2aSThomas Huth return 0; 719*fcf5ef2aSThomas Huth } else { 720*fcf5ef2aSThomas Huth return (v & REGION_PAGE_MASK) | 0x1; 721*fcf5ef2aSThomas Huth } 722*fcf5ef2aSThomas Huth } 723*fcf5ef2aSThomas Huth 724*fcf5ef2aSThomas Huth void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env, 725*fcf5ef2aSThomas Huth xtensa_tlb_entry *entry, bool dtlb, 726*fcf5ef2aSThomas Huth unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte) 727*fcf5ef2aSThomas Huth { 728*fcf5ef2aSThomas Huth entry->vaddr = vpn; 729*fcf5ef2aSThomas Huth entry->paddr = pte & xtensa_tlb_get_addr_mask(env, dtlb, wi); 730*fcf5ef2aSThomas Huth entry->asid = (env->sregs[RASID] >> ((pte >> 1) & 0x18)) & 0xff; 731*fcf5ef2aSThomas Huth entry->attr = pte & 0xf; 732*fcf5ef2aSThomas Huth } 733*fcf5ef2aSThomas Huth 734*fcf5ef2aSThomas Huth void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb, 735*fcf5ef2aSThomas Huth unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte) 736*fcf5ef2aSThomas Huth { 737*fcf5ef2aSThomas Huth XtensaCPU *cpu = xtensa_env_get_cpu(env); 738*fcf5ef2aSThomas Huth CPUState *cs = CPU(cpu); 739*fcf5ef2aSThomas Huth xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei); 740*fcf5ef2aSThomas Huth 741*fcf5ef2aSThomas Huth if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 742*fcf5ef2aSThomas Huth if (entry->variable) { 743*fcf5ef2aSThomas Huth if (entry->asid) { 744*fcf5ef2aSThomas Huth tlb_flush_page(cs, entry->vaddr); 745*fcf5ef2aSThomas Huth } 746*fcf5ef2aSThomas Huth xtensa_tlb_set_entry_mmu(env, entry, dtlb, wi, ei, vpn, pte); 747*fcf5ef2aSThomas Huth tlb_flush_page(cs, entry->vaddr); 748*fcf5ef2aSThomas Huth } else { 749*fcf5ef2aSThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "%s %d, %d, %d trying to set immutable entry\n", 750*fcf5ef2aSThomas Huth __func__, dtlb, wi, ei); 751*fcf5ef2aSThomas Huth } 752*fcf5ef2aSThomas Huth } else { 753*fcf5ef2aSThomas Huth tlb_flush_page(cs, entry->vaddr); 754*fcf5ef2aSThomas Huth if (xtensa_option_enabled(env->config, 755*fcf5ef2aSThomas Huth XTENSA_OPTION_REGION_TRANSLATION)) { 756*fcf5ef2aSThomas Huth entry->paddr = pte & REGION_PAGE_MASK; 757*fcf5ef2aSThomas Huth } 758*fcf5ef2aSThomas Huth entry->attr = pte & 0xf; 759*fcf5ef2aSThomas Huth } 760*fcf5ef2aSThomas Huth } 761*fcf5ef2aSThomas Huth 762*fcf5ef2aSThomas Huth void HELPER(wtlb)(CPUXtensaState *env, uint32_t p, uint32_t v, uint32_t dtlb) 763*fcf5ef2aSThomas Huth { 764*fcf5ef2aSThomas Huth uint32_t vpn; 765*fcf5ef2aSThomas Huth uint32_t wi; 766*fcf5ef2aSThomas Huth uint32_t ei; 767*fcf5ef2aSThomas Huth split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei); 768*fcf5ef2aSThomas Huth xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, p); 769*fcf5ef2aSThomas Huth } 770*fcf5ef2aSThomas Huth 771*fcf5ef2aSThomas Huth 772*fcf5ef2aSThomas Huth void HELPER(wsr_ibreakenable)(CPUXtensaState *env, uint32_t v) 773*fcf5ef2aSThomas Huth { 774*fcf5ef2aSThomas Huth uint32_t change = v ^ env->sregs[IBREAKENABLE]; 775*fcf5ef2aSThomas Huth unsigned i; 776*fcf5ef2aSThomas Huth 777*fcf5ef2aSThomas Huth for (i = 0; i < env->config->nibreak; ++i) { 778*fcf5ef2aSThomas Huth if (change & (1 << i)) { 779*fcf5ef2aSThomas Huth tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]); 780*fcf5ef2aSThomas Huth } 781*fcf5ef2aSThomas Huth } 782*fcf5ef2aSThomas Huth env->sregs[IBREAKENABLE] = v & ((1 << env->config->nibreak) - 1); 783*fcf5ef2aSThomas Huth } 784*fcf5ef2aSThomas Huth 785*fcf5ef2aSThomas Huth void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t i, uint32_t v) 786*fcf5ef2aSThomas Huth { 787*fcf5ef2aSThomas Huth if (env->sregs[IBREAKENABLE] & (1 << i) && env->sregs[IBREAKA + i] != v) { 788*fcf5ef2aSThomas Huth tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]); 789*fcf5ef2aSThomas Huth tb_invalidate_virtual_addr(env, v); 790*fcf5ef2aSThomas Huth } 791*fcf5ef2aSThomas Huth env->sregs[IBREAKA + i] = v; 792*fcf5ef2aSThomas Huth } 793*fcf5ef2aSThomas Huth 794*fcf5ef2aSThomas Huth static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka, 795*fcf5ef2aSThomas Huth uint32_t dbreakc) 796*fcf5ef2aSThomas Huth { 797*fcf5ef2aSThomas Huth CPUState *cs = CPU(xtensa_env_get_cpu(env)); 798*fcf5ef2aSThomas Huth int flags = BP_CPU | BP_STOP_BEFORE_ACCESS; 799*fcf5ef2aSThomas Huth uint32_t mask = dbreakc | ~DBREAKC_MASK; 800*fcf5ef2aSThomas Huth 801*fcf5ef2aSThomas Huth if (env->cpu_watchpoint[i]) { 802*fcf5ef2aSThomas Huth cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]); 803*fcf5ef2aSThomas Huth } 804*fcf5ef2aSThomas Huth if (dbreakc & DBREAKC_SB) { 805*fcf5ef2aSThomas Huth flags |= BP_MEM_WRITE; 806*fcf5ef2aSThomas Huth } 807*fcf5ef2aSThomas Huth if (dbreakc & DBREAKC_LB) { 808*fcf5ef2aSThomas Huth flags |= BP_MEM_READ; 809*fcf5ef2aSThomas Huth } 810*fcf5ef2aSThomas Huth /* contiguous mask after inversion is one less than some power of 2 */ 811*fcf5ef2aSThomas Huth if ((~mask + 1) & ~mask) { 812*fcf5ef2aSThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "DBREAKC mask is not contiguous: 0x%08x\n", dbreakc); 813*fcf5ef2aSThomas Huth /* cut mask after the first zero bit */ 814*fcf5ef2aSThomas Huth mask = 0xffffffff << (32 - clo32(mask)); 815*fcf5ef2aSThomas Huth } 816*fcf5ef2aSThomas Huth if (cpu_watchpoint_insert(cs, dbreaka & mask, ~mask + 1, 817*fcf5ef2aSThomas Huth flags, &env->cpu_watchpoint[i])) { 818*fcf5ef2aSThomas Huth env->cpu_watchpoint[i] = NULL; 819*fcf5ef2aSThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Failed to set data breakpoint at 0x%08x/%d\n", 820*fcf5ef2aSThomas Huth dbreaka & mask, ~mask + 1); 821*fcf5ef2aSThomas Huth } 822*fcf5ef2aSThomas Huth } 823*fcf5ef2aSThomas Huth 824*fcf5ef2aSThomas Huth void HELPER(wsr_dbreaka)(CPUXtensaState *env, uint32_t i, uint32_t v) 825*fcf5ef2aSThomas Huth { 826*fcf5ef2aSThomas Huth uint32_t dbreakc = env->sregs[DBREAKC + i]; 827*fcf5ef2aSThomas Huth 828*fcf5ef2aSThomas Huth if ((dbreakc & DBREAKC_SB_LB) && 829*fcf5ef2aSThomas Huth env->sregs[DBREAKA + i] != v) { 830*fcf5ef2aSThomas Huth set_dbreak(env, i, v, dbreakc); 831*fcf5ef2aSThomas Huth } 832*fcf5ef2aSThomas Huth env->sregs[DBREAKA + i] = v; 833*fcf5ef2aSThomas Huth } 834*fcf5ef2aSThomas Huth 835*fcf5ef2aSThomas Huth void HELPER(wsr_dbreakc)(CPUXtensaState *env, uint32_t i, uint32_t v) 836*fcf5ef2aSThomas Huth { 837*fcf5ef2aSThomas Huth if ((env->sregs[DBREAKC + i] ^ v) & (DBREAKC_SB_LB | DBREAKC_MASK)) { 838*fcf5ef2aSThomas Huth if (v & DBREAKC_SB_LB) { 839*fcf5ef2aSThomas Huth set_dbreak(env, i, env->sregs[DBREAKA + i], v); 840*fcf5ef2aSThomas Huth } else { 841*fcf5ef2aSThomas Huth if (env->cpu_watchpoint[i]) { 842*fcf5ef2aSThomas Huth CPUState *cs = CPU(xtensa_env_get_cpu(env)); 843*fcf5ef2aSThomas Huth 844*fcf5ef2aSThomas Huth cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]); 845*fcf5ef2aSThomas Huth env->cpu_watchpoint[i] = NULL; 846*fcf5ef2aSThomas Huth } 847*fcf5ef2aSThomas Huth } 848*fcf5ef2aSThomas Huth } 849*fcf5ef2aSThomas Huth env->sregs[DBREAKC + i] = v; 850*fcf5ef2aSThomas Huth } 851*fcf5ef2aSThomas Huth 852*fcf5ef2aSThomas Huth void HELPER(wur_fcr)(CPUXtensaState *env, uint32_t v) 853*fcf5ef2aSThomas Huth { 854*fcf5ef2aSThomas Huth static const int rounding_mode[] = { 855*fcf5ef2aSThomas Huth float_round_nearest_even, 856*fcf5ef2aSThomas Huth float_round_to_zero, 857*fcf5ef2aSThomas Huth float_round_up, 858*fcf5ef2aSThomas Huth float_round_down, 859*fcf5ef2aSThomas Huth }; 860*fcf5ef2aSThomas Huth 861*fcf5ef2aSThomas Huth env->uregs[FCR] = v & 0xfffff07f; 862*fcf5ef2aSThomas Huth set_float_rounding_mode(rounding_mode[v & 3], &env->fp_status); 863*fcf5ef2aSThomas Huth } 864*fcf5ef2aSThomas Huth 865*fcf5ef2aSThomas Huth float32 HELPER(abs_s)(float32 v) 866*fcf5ef2aSThomas Huth { 867*fcf5ef2aSThomas Huth return float32_abs(v); 868*fcf5ef2aSThomas Huth } 869*fcf5ef2aSThomas Huth 870*fcf5ef2aSThomas Huth float32 HELPER(neg_s)(float32 v) 871*fcf5ef2aSThomas Huth { 872*fcf5ef2aSThomas Huth return float32_chs(v); 873*fcf5ef2aSThomas Huth } 874*fcf5ef2aSThomas Huth 875*fcf5ef2aSThomas Huth float32 HELPER(add_s)(CPUXtensaState *env, float32 a, float32 b) 876*fcf5ef2aSThomas Huth { 877*fcf5ef2aSThomas Huth return float32_add(a, b, &env->fp_status); 878*fcf5ef2aSThomas Huth } 879*fcf5ef2aSThomas Huth 880*fcf5ef2aSThomas Huth float32 HELPER(sub_s)(CPUXtensaState *env, float32 a, float32 b) 881*fcf5ef2aSThomas Huth { 882*fcf5ef2aSThomas Huth return float32_sub(a, b, &env->fp_status); 883*fcf5ef2aSThomas Huth } 884*fcf5ef2aSThomas Huth 885*fcf5ef2aSThomas Huth float32 HELPER(mul_s)(CPUXtensaState *env, float32 a, float32 b) 886*fcf5ef2aSThomas Huth { 887*fcf5ef2aSThomas Huth return float32_mul(a, b, &env->fp_status); 888*fcf5ef2aSThomas Huth } 889*fcf5ef2aSThomas Huth 890*fcf5ef2aSThomas Huth float32 HELPER(madd_s)(CPUXtensaState *env, float32 a, float32 b, float32 c) 891*fcf5ef2aSThomas Huth { 892*fcf5ef2aSThomas Huth return float32_muladd(b, c, a, 0, 893*fcf5ef2aSThomas Huth &env->fp_status); 894*fcf5ef2aSThomas Huth } 895*fcf5ef2aSThomas Huth 896*fcf5ef2aSThomas Huth float32 HELPER(msub_s)(CPUXtensaState *env, float32 a, float32 b, float32 c) 897*fcf5ef2aSThomas Huth { 898*fcf5ef2aSThomas Huth return float32_muladd(b, c, a, float_muladd_negate_product, 899*fcf5ef2aSThomas Huth &env->fp_status); 900*fcf5ef2aSThomas Huth } 901*fcf5ef2aSThomas Huth 902*fcf5ef2aSThomas Huth uint32_t HELPER(ftoi)(float32 v, uint32_t rounding_mode, uint32_t scale) 903*fcf5ef2aSThomas Huth { 904*fcf5ef2aSThomas Huth float_status fp_status = {0}; 905*fcf5ef2aSThomas Huth 906*fcf5ef2aSThomas Huth set_float_rounding_mode(rounding_mode, &fp_status); 907*fcf5ef2aSThomas Huth return float32_to_int32( 908*fcf5ef2aSThomas Huth float32_scalbn(v, scale, &fp_status), &fp_status); 909*fcf5ef2aSThomas Huth } 910*fcf5ef2aSThomas Huth 911*fcf5ef2aSThomas Huth uint32_t HELPER(ftoui)(float32 v, uint32_t rounding_mode, uint32_t scale) 912*fcf5ef2aSThomas Huth { 913*fcf5ef2aSThomas Huth float_status fp_status = {0}; 914*fcf5ef2aSThomas Huth float32 res; 915*fcf5ef2aSThomas Huth 916*fcf5ef2aSThomas Huth set_float_rounding_mode(rounding_mode, &fp_status); 917*fcf5ef2aSThomas Huth 918*fcf5ef2aSThomas Huth res = float32_scalbn(v, scale, &fp_status); 919*fcf5ef2aSThomas Huth 920*fcf5ef2aSThomas Huth if (float32_is_neg(v) && !float32_is_any_nan(v)) { 921*fcf5ef2aSThomas Huth return float32_to_int32(res, &fp_status); 922*fcf5ef2aSThomas Huth } else { 923*fcf5ef2aSThomas Huth return float32_to_uint32(res, &fp_status); 924*fcf5ef2aSThomas Huth } 925*fcf5ef2aSThomas Huth } 926*fcf5ef2aSThomas Huth 927*fcf5ef2aSThomas Huth float32 HELPER(itof)(CPUXtensaState *env, uint32_t v, uint32_t scale) 928*fcf5ef2aSThomas Huth { 929*fcf5ef2aSThomas Huth return float32_scalbn(int32_to_float32(v, &env->fp_status), 930*fcf5ef2aSThomas Huth (int32_t)scale, &env->fp_status); 931*fcf5ef2aSThomas Huth } 932*fcf5ef2aSThomas Huth 933*fcf5ef2aSThomas Huth float32 HELPER(uitof)(CPUXtensaState *env, uint32_t v, uint32_t scale) 934*fcf5ef2aSThomas Huth { 935*fcf5ef2aSThomas Huth return float32_scalbn(uint32_to_float32(v, &env->fp_status), 936*fcf5ef2aSThomas Huth (int32_t)scale, &env->fp_status); 937*fcf5ef2aSThomas Huth } 938*fcf5ef2aSThomas Huth 939*fcf5ef2aSThomas Huth static inline void set_br(CPUXtensaState *env, bool v, uint32_t br) 940*fcf5ef2aSThomas Huth { 941*fcf5ef2aSThomas Huth if (v) { 942*fcf5ef2aSThomas Huth env->sregs[BR] |= br; 943*fcf5ef2aSThomas Huth } else { 944*fcf5ef2aSThomas Huth env->sregs[BR] &= ~br; 945*fcf5ef2aSThomas Huth } 946*fcf5ef2aSThomas Huth } 947*fcf5ef2aSThomas Huth 948*fcf5ef2aSThomas Huth void HELPER(un_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) 949*fcf5ef2aSThomas Huth { 950*fcf5ef2aSThomas Huth set_br(env, float32_unordered_quiet(a, b, &env->fp_status), br); 951*fcf5ef2aSThomas Huth } 952*fcf5ef2aSThomas Huth 953*fcf5ef2aSThomas Huth void HELPER(oeq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) 954*fcf5ef2aSThomas Huth { 955*fcf5ef2aSThomas Huth set_br(env, float32_eq_quiet(a, b, &env->fp_status), br); 956*fcf5ef2aSThomas Huth } 957*fcf5ef2aSThomas Huth 958*fcf5ef2aSThomas Huth void HELPER(ueq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) 959*fcf5ef2aSThomas Huth { 960*fcf5ef2aSThomas Huth int v = float32_compare_quiet(a, b, &env->fp_status); 961*fcf5ef2aSThomas Huth set_br(env, v == float_relation_equal || v == float_relation_unordered, br); 962*fcf5ef2aSThomas Huth } 963*fcf5ef2aSThomas Huth 964*fcf5ef2aSThomas Huth void HELPER(olt_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) 965*fcf5ef2aSThomas Huth { 966*fcf5ef2aSThomas Huth set_br(env, float32_lt_quiet(a, b, &env->fp_status), br); 967*fcf5ef2aSThomas Huth } 968*fcf5ef2aSThomas Huth 969*fcf5ef2aSThomas Huth void HELPER(ult_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) 970*fcf5ef2aSThomas Huth { 971*fcf5ef2aSThomas Huth int v = float32_compare_quiet(a, b, &env->fp_status); 972*fcf5ef2aSThomas Huth set_br(env, v == float_relation_less || v == float_relation_unordered, br); 973*fcf5ef2aSThomas Huth } 974*fcf5ef2aSThomas Huth 975*fcf5ef2aSThomas Huth void HELPER(ole_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) 976*fcf5ef2aSThomas Huth { 977*fcf5ef2aSThomas Huth set_br(env, float32_le_quiet(a, b, &env->fp_status), br); 978*fcf5ef2aSThomas Huth } 979*fcf5ef2aSThomas Huth 980*fcf5ef2aSThomas Huth void HELPER(ule_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) 981*fcf5ef2aSThomas Huth { 982*fcf5ef2aSThomas Huth int v = float32_compare_quiet(a, b, &env->fp_status); 983*fcf5ef2aSThomas Huth set_br(env, v != float_relation_greater, br); 984*fcf5ef2aSThomas Huth } 985