1 /* 2 * Copyright (c) 2011 - 2019, Max Filippov, Open Source and Linux Lab. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * * Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * * Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * * Neither the name of the Open Source and Linux Lab nor the 13 * names of its contributors may be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include "qemu/osdep.h" 29 #include "qemu/log.h" 30 #include "qemu/qemu-print.h" 31 #include "qemu/units.h" 32 #include "cpu.h" 33 #include "exec/helper-proto.h" 34 #include "qemu/host-utils.h" 35 #include "exec/cputlb.h" 36 #include "accel/tcg/cpu-mmu-index.h" 37 #include "accel/tcg/probe.h" 38 #include "exec/exec-all.h" 39 #include "exec/page-protection.h" 40 #include "exec/target_page.h" 41 #include "system/memory.h" 42 43 #define XTENSA_MPU_SEGMENT_MASK 0x0000001f 44 #define XTENSA_MPU_ACC_RIGHTS_MASK 0x00000f00 45 #define XTENSA_MPU_ACC_RIGHTS_SHIFT 8 46 #define XTENSA_MPU_MEM_TYPE_MASK 0x001ff000 47 #define XTENSA_MPU_MEM_TYPE_SHIFT 12 48 #define XTENSA_MPU_ATTR_MASK 0x001fff00 49 50 #define XTENSA_MPU_PROBE_B 0x40000000 51 #define XTENSA_MPU_PROBE_V 0x80000000 52 53 #define XTENSA_MPU_SYSTEM_TYPE_DEVICE 0x0001 54 #define XTENSA_MPU_SYSTEM_TYPE_NC 0x0002 55 #define XTENSA_MPU_SYSTEM_TYPE_C 0x0003 56 #define XTENSA_MPU_SYSTEM_TYPE_MASK 0x0003 57 58 #define XTENSA_MPU_TYPE_SYS_C 0x0010 59 #define XTENSA_MPU_TYPE_SYS_W 0x0020 60 #define XTENSA_MPU_TYPE_SYS_R 0x0040 61 #define XTENSA_MPU_TYPE_CPU_C 0x0100 62 #define XTENSA_MPU_TYPE_CPU_W 0x0200 63 #define XTENSA_MPU_TYPE_CPU_R 0x0400 64 #define XTENSA_MPU_TYPE_CPU_CACHE 0x0800 65 #define XTENSA_MPU_TYPE_B 0x1000 66 #define XTENSA_MPU_TYPE_INT 0x2000 67 68 void HELPER(itlb_hit_test)(CPUXtensaState *env, uint32_t vaddr) 69 { 70 /* 71 * Probe the memory; we don't care about the result but 72 * only the side-effects (ie any MMU or other exception) 73 */ 74 probe_access(env, vaddr, 1, MMU_INST_FETCH, 75 cpu_mmu_index(env_cpu(env), true), GETPC()); 76 } 77 78 void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v) 79 { 80 v = (v & 0xffffff00) | 0x1; 81 if (v != env->sregs[RASID]) { 82 env->sregs[RASID] = v; 83 tlb_flush(env_cpu(env)); 84 } 85 } 86 87 static uint32_t get_page_size(const CPUXtensaState *env, 88 bool dtlb, uint32_t way) 89 { 90 uint32_t tlbcfg = env->sregs[dtlb ? DTLBCFG : ITLBCFG]; 91 92 switch (way) { 93 case 4: 94 return (tlbcfg >> 16) & 0x3; 95 96 case 5: 97 return (tlbcfg >> 20) & 0x1; 98 99 case 6: 100 return (tlbcfg >> 24) & 0x1; 101 102 default: 103 return 0; 104 } 105 } 106 107 /*! 108 * Get bit mask for the virtual address bits translated by the TLB way 109 */ 110 static uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, 111 bool dtlb, uint32_t way) 112 { 113 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 114 bool varway56 = dtlb ? 115 env->config->dtlb.varway56 : 116 env->config->itlb.varway56; 117 118 switch (way) { 119 case 4: 120 return 0xfff00000 << get_page_size(env, dtlb, way) * 2; 121 122 case 5: 123 if (varway56) { 124 return 0xf8000000 << get_page_size(env, dtlb, way); 125 } else { 126 return 0xf8000000; 127 } 128 129 case 6: 130 if (varway56) { 131 return 0xf0000000 << (1 - get_page_size(env, dtlb, way)); 132 } else { 133 return 0xf0000000; 134 } 135 136 default: 137 return 0xfffff000; 138 } 139 } else { 140 return REGION_PAGE_MASK; 141 } 142 } 143 144 /*! 145 * Get bit mask for the 'VPN without index' field. 146 * See ISA, 4.6.5.6, data format for RxTLB0 147 */ 148 static uint32_t get_vpn_mask(const CPUXtensaState *env, bool dtlb, uint32_t way) 149 { 150 if (way < 4) { 151 bool is32 = (dtlb ? 152 env->config->dtlb.nrefillentries : 153 env->config->itlb.nrefillentries) == 32; 154 return is32 ? 0xffff8000 : 0xffffc000; 155 } else if (way == 4) { 156 return xtensa_tlb_get_addr_mask(env, dtlb, way) << 2; 157 } else if (way <= 6) { 158 uint32_t mask = xtensa_tlb_get_addr_mask(env, dtlb, way); 159 bool varway56 = dtlb ? 160 env->config->dtlb.varway56 : 161 env->config->itlb.varway56; 162 163 if (varway56) { 164 return mask << (way == 5 ? 2 : 3); 165 } else { 166 return mask << 1; 167 } 168 } else { 169 return 0xfffff000; 170 } 171 } 172 173 /*! 174 * Split virtual address into VPN (with index) and entry index 175 * for the given TLB way 176 */ 177 static void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, 178 bool dtlb, uint32_t *vpn, 179 uint32_t wi, uint32_t *ei) 180 { 181 bool varway56 = dtlb ? 182 env->config->dtlb.varway56 : 183 env->config->itlb.varway56; 184 185 if (!dtlb) { 186 wi &= 7; 187 } 188 189 if (wi < 4) { 190 bool is32 = (dtlb ? 191 env->config->dtlb.nrefillentries : 192 env->config->itlb.nrefillentries) == 32; 193 *ei = (v >> 12) & (is32 ? 0x7 : 0x3); 194 } else { 195 switch (wi) { 196 case 4: 197 { 198 uint32_t eibase = 20 + get_page_size(env, dtlb, wi) * 2; 199 *ei = (v >> eibase) & 0x3; 200 } 201 break; 202 203 case 5: 204 if (varway56) { 205 uint32_t eibase = 27 + get_page_size(env, dtlb, wi); 206 *ei = (v >> eibase) & 0x3; 207 } else { 208 *ei = (v >> 27) & 0x1; 209 } 210 break; 211 212 case 6: 213 if (varway56) { 214 uint32_t eibase = 29 - get_page_size(env, dtlb, wi); 215 *ei = (v >> eibase) & 0x7; 216 } else { 217 *ei = (v >> 28) & 0x1; 218 } 219 break; 220 221 default: 222 *ei = 0; 223 break; 224 } 225 } 226 *vpn = v & xtensa_tlb_get_addr_mask(env, dtlb, wi); 227 } 228 229 /*! 230 * Split TLB address into TLB way, entry index and VPN (with index). 231 * See ISA, 4.6.5.5 - 4.6.5.8 for the TLB addressing format 232 */ 233 static bool split_tlb_entry_spec(CPUXtensaState *env, uint32_t v, bool dtlb, 234 uint32_t *vpn, uint32_t *wi, uint32_t *ei) 235 { 236 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 237 *wi = v & (dtlb ? 0xf : 0x7); 238 if (*wi < (dtlb ? env->config->dtlb.nways : env->config->itlb.nways)) { 239 split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei); 240 return true; 241 } else { 242 return false; 243 } 244 } else { 245 *vpn = v & REGION_PAGE_MASK; 246 *wi = 0; 247 *ei = (v >> 29) & 0x7; 248 return true; 249 } 250 } 251 252 static xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env, bool dtlb, 253 unsigned wi, unsigned ei) 254 { 255 const xtensa_tlb *tlb = dtlb ? &env->config->dtlb : &env->config->itlb; 256 257 assert(wi < tlb->nways && ei < tlb->way_size[wi]); 258 return dtlb ? 259 env->dtlb[wi] + ei : 260 env->itlb[wi] + ei; 261 } 262 263 static xtensa_tlb_entry *get_tlb_entry(CPUXtensaState *env, 264 uint32_t v, bool dtlb, uint32_t *pwi) 265 { 266 uint32_t vpn; 267 uint32_t wi; 268 uint32_t ei; 269 270 if (split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei)) { 271 if (pwi) { 272 *pwi = wi; 273 } 274 return xtensa_tlb_get_entry(env, dtlb, wi, ei); 275 } else { 276 return NULL; 277 } 278 } 279 280 static void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env, 281 xtensa_tlb_entry *entry, bool dtlb, 282 unsigned wi, unsigned ei, uint32_t vpn, 283 uint32_t pte) 284 { 285 entry->vaddr = vpn; 286 entry->paddr = pte & xtensa_tlb_get_addr_mask(env, dtlb, wi); 287 entry->asid = (env->sregs[RASID] >> ((pte >> 1) & 0x18)) & 0xff; 288 entry->attr = pte & 0xf; 289 } 290 291 static void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb, 292 unsigned wi, unsigned ei, 293 uint32_t vpn, uint32_t pte) 294 { 295 CPUState *cs = env_cpu(env); 296 xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei); 297 298 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 299 if (entry->variable) { 300 if (entry->asid) { 301 tlb_flush_page(cs, entry->vaddr); 302 } 303 xtensa_tlb_set_entry_mmu(env, entry, dtlb, wi, ei, vpn, pte); 304 tlb_flush_page(cs, entry->vaddr); 305 } else { 306 qemu_log_mask(LOG_GUEST_ERROR, 307 "%s %d, %d, %d trying to set immutable entry\n", 308 __func__, dtlb, wi, ei); 309 } 310 } else { 311 tlb_flush_page(cs, entry->vaddr); 312 if (xtensa_option_enabled(env->config, 313 XTENSA_OPTION_REGION_TRANSLATION)) { 314 entry->paddr = pte & REGION_PAGE_MASK; 315 } 316 entry->attr = pte & 0xf; 317 } 318 } 319 320 hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) 321 { 322 XtensaCPU *cpu = XTENSA_CPU(cs); 323 uint32_t paddr; 324 uint32_t page_size; 325 unsigned access; 326 327 if (xtensa_get_physical_addr(&cpu->env, false, addr, 0, 0, 328 &paddr, &page_size, &access) == 0) { 329 return paddr; 330 } 331 if (xtensa_get_physical_addr(&cpu->env, false, addr, 2, 0, 332 &paddr, &page_size, &access) == 0) { 333 return paddr; 334 } 335 return ~0; 336 } 337 338 static void reset_tlb_mmu_all_ways(CPUXtensaState *env, 339 const xtensa_tlb *tlb, 340 xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE]) 341 { 342 unsigned wi, ei; 343 344 for (wi = 0; wi < tlb->nways; ++wi) { 345 for (ei = 0; ei < tlb->way_size[wi]; ++ei) { 346 entry[wi][ei].asid = 0; 347 entry[wi][ei].variable = true; 348 } 349 } 350 } 351 352 static void reset_tlb_mmu_ways56(CPUXtensaState *env, 353 const xtensa_tlb *tlb, 354 xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE]) 355 { 356 if (!tlb->varway56) { 357 static const xtensa_tlb_entry way5[] = { 358 { 359 .vaddr = 0xd0000000, 360 .paddr = 0, 361 .asid = 1, 362 .attr = 7, 363 .variable = false, 364 }, { 365 .vaddr = 0xd8000000, 366 .paddr = 0, 367 .asid = 1, 368 .attr = 3, 369 .variable = false, 370 } 371 }; 372 static const xtensa_tlb_entry way6[] = { 373 { 374 .vaddr = 0xe0000000, 375 .paddr = 0xf0000000, 376 .asid = 1, 377 .attr = 7, 378 .variable = false, 379 }, { 380 .vaddr = 0xf0000000, 381 .paddr = 0xf0000000, 382 .asid = 1, 383 .attr = 3, 384 .variable = false, 385 } 386 }; 387 memcpy(entry[5], way5, sizeof(way5)); 388 memcpy(entry[6], way6, sizeof(way6)); 389 } else { 390 uint32_t ei; 391 for (ei = 0; ei < 8; ++ei) { 392 entry[6][ei].vaddr = ei << 29; 393 entry[6][ei].paddr = ei << 29; 394 entry[6][ei].asid = 1; 395 entry[6][ei].attr = 3; 396 } 397 } 398 } 399 400 static void reset_tlb_region_way0(CPUXtensaState *env, 401 xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE]) 402 { 403 unsigned ei; 404 405 for (ei = 0; ei < 8; ++ei) { 406 entry[0][ei].vaddr = ei << 29; 407 entry[0][ei].paddr = ei << 29; 408 entry[0][ei].asid = 1; 409 entry[0][ei].attr = 2; 410 entry[0][ei].variable = true; 411 } 412 } 413 414 void reset_mmu(CPUXtensaState *env) 415 { 416 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 417 env->sregs[RASID] = 0x04030201; 418 env->sregs[ITLBCFG] = 0; 419 env->sregs[DTLBCFG] = 0; 420 env->autorefill_idx = 0; 421 reset_tlb_mmu_all_ways(env, &env->config->itlb, env->itlb); 422 reset_tlb_mmu_all_ways(env, &env->config->dtlb, env->dtlb); 423 reset_tlb_mmu_ways56(env, &env->config->itlb, env->itlb); 424 reset_tlb_mmu_ways56(env, &env->config->dtlb, env->dtlb); 425 } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_MPU)) { 426 unsigned i; 427 428 env->sregs[MPUENB] = 0; 429 env->sregs[MPUCFG] = env->config->n_mpu_fg_segments; 430 env->sregs[CACHEADRDIS] = 0; 431 assert(env->config->n_mpu_bg_segments > 0 && 432 env->config->mpu_bg[0].vaddr == 0); 433 for (i = 1; i < env->config->n_mpu_bg_segments; ++i) { 434 assert(env->config->mpu_bg[i].vaddr >= 435 env->config->mpu_bg[i - 1].vaddr); 436 } 437 } else { 438 env->sregs[CACHEATTR] = 0x22222222; 439 reset_tlb_region_way0(env, env->itlb); 440 reset_tlb_region_way0(env, env->dtlb); 441 } 442 } 443 444 static unsigned get_ring(const CPUXtensaState *env, uint8_t asid) 445 { 446 unsigned i; 447 for (i = 0; i < 4; ++i) { 448 if (((env->sregs[RASID] >> i * 8) & 0xff) == asid) { 449 return i; 450 } 451 } 452 return 0xff; 453 } 454 455 /*! 456 * Lookup xtensa TLB for the given virtual address. 457 * See ISA, 4.6.2.2 458 * 459 * \param pwi: [out] way index 460 * \param pei: [out] entry index 461 * \param pring: [out] access ring 462 * \return 0 if ok, exception cause code otherwise 463 */ 464 static int xtensa_tlb_lookup(const CPUXtensaState *env, 465 uint32_t addr, bool dtlb, 466 uint32_t *pwi, uint32_t *pei, uint8_t *pring) 467 { 468 const xtensa_tlb *tlb = dtlb ? 469 &env->config->dtlb : &env->config->itlb; 470 const xtensa_tlb_entry (*entry)[MAX_TLB_WAY_SIZE] = dtlb ? 471 env->dtlb : env->itlb; 472 473 int nhits = 0; 474 unsigned wi; 475 476 for (wi = 0; wi < tlb->nways; ++wi) { 477 uint32_t vpn; 478 uint32_t ei; 479 split_tlb_entry_spec_way(env, addr, dtlb, &vpn, wi, &ei); 480 if (entry[wi][ei].vaddr == vpn && entry[wi][ei].asid) { 481 unsigned ring = get_ring(env, entry[wi][ei].asid); 482 if (ring < 4) { 483 if (++nhits > 1) { 484 return dtlb ? 485 LOAD_STORE_TLB_MULTI_HIT_CAUSE : 486 INST_TLB_MULTI_HIT_CAUSE; 487 } 488 *pwi = wi; 489 *pei = ei; 490 *pring = ring; 491 } 492 } 493 } 494 return nhits ? 0 : 495 (dtlb ? LOAD_STORE_TLB_MISS_CAUSE : INST_TLB_MISS_CAUSE); 496 } 497 498 uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) 499 { 500 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 501 uint32_t wi; 502 const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi); 503 504 if (entry) { 505 return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->asid; 506 } else { 507 return 0; 508 } 509 } else { 510 return v & REGION_PAGE_MASK; 511 } 512 } 513 514 uint32_t HELPER(rtlb1)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) 515 { 516 const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, NULL); 517 518 if (entry) { 519 return entry->paddr | entry->attr; 520 } else { 521 return 0; 522 } 523 } 524 525 void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) 526 { 527 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 528 uint32_t wi; 529 xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi); 530 if (entry && entry->variable && entry->asid) { 531 tlb_flush_page(env_cpu(env), entry->vaddr); 532 entry->asid = 0; 533 } 534 } 535 } 536 537 uint32_t HELPER(ptlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) 538 { 539 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 540 uint32_t wi; 541 uint32_t ei; 542 uint8_t ring; 543 int res = xtensa_tlb_lookup(env, v, dtlb, &wi, &ei, &ring); 544 545 switch (res) { 546 case 0: 547 if (ring >= xtensa_get_ring(env)) { 548 return (v & 0xfffff000) | wi | (dtlb ? 0x10 : 0x8); 549 } 550 break; 551 552 case INST_TLB_MULTI_HIT_CAUSE: 553 case LOAD_STORE_TLB_MULTI_HIT_CAUSE: 554 HELPER(exception_cause_vaddr)(env, env->pc, res, v); 555 break; 556 } 557 return 0; 558 } else { 559 return (v & REGION_PAGE_MASK) | 0x1; 560 } 561 } 562 563 void HELPER(wtlb)(CPUXtensaState *env, uint32_t p, uint32_t v, uint32_t dtlb) 564 { 565 uint32_t vpn; 566 uint32_t wi; 567 uint32_t ei; 568 if (split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei)) { 569 xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, p); 570 } 571 } 572 573 /*! 574 * Convert MMU ATTR to PAGE_{READ,WRITE,EXEC} mask. 575 * See ISA, 4.6.5.10 576 */ 577 static unsigned mmu_attr_to_access(uint32_t attr) 578 { 579 unsigned access = 0; 580 581 if (attr < 12) { 582 access |= PAGE_READ; 583 if (attr & 0x1) { 584 access |= PAGE_EXEC; 585 } 586 if (attr & 0x2) { 587 access |= PAGE_WRITE; 588 } 589 590 switch (attr & 0xc) { 591 case 0: 592 access |= PAGE_CACHE_BYPASS; 593 break; 594 595 case 4: 596 access |= PAGE_CACHE_WB; 597 break; 598 599 case 8: 600 access |= PAGE_CACHE_WT; 601 break; 602 } 603 } else if (attr == 13) { 604 access |= PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE; 605 } 606 return access; 607 } 608 609 /*! 610 * Convert region protection ATTR to PAGE_{READ,WRITE,EXEC} mask. 611 * See ISA, 4.6.3.3 612 */ 613 static unsigned region_attr_to_access(uint32_t attr) 614 { 615 static const unsigned access[16] = { 616 [0] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_WT, 617 [1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT, 618 [2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS, 619 [3] = PAGE_EXEC | PAGE_CACHE_WB, 620 [4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB, 621 [5] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB, 622 [14] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE, 623 }; 624 625 return access[attr & 0xf]; 626 } 627 628 /*! 629 * Convert cacheattr to PAGE_{READ,WRITE,EXEC} mask. 630 * See ISA, A.2.14 The Cache Attribute Register 631 */ 632 static unsigned cacheattr_attr_to_access(uint32_t attr) 633 { 634 static const unsigned access[16] = { 635 [0] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_WT, 636 [1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT, 637 [2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS, 638 [3] = PAGE_EXEC | PAGE_CACHE_WB, 639 [4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB, 640 [14] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE, 641 }; 642 643 return access[attr & 0xf]; 644 } 645 646 struct attr_pattern { 647 uint32_t mask; 648 uint32_t value; 649 }; 650 651 static int attr_pattern_match(uint32_t attr, 652 const struct attr_pattern *pattern, 653 size_t n) 654 { 655 size_t i; 656 657 for (i = 0; i < n; ++i) { 658 if ((attr & pattern[i].mask) == pattern[i].value) { 659 return 1; 660 } 661 } 662 return 0; 663 } 664 665 static unsigned mpu_attr_to_cpu_cache(uint32_t attr) 666 { 667 static const struct attr_pattern cpu_c[] = { 668 { .mask = 0x18f, .value = 0x089 }, 669 { .mask = 0x188, .value = 0x080 }, 670 { .mask = 0x180, .value = 0x180 }, 671 }; 672 673 unsigned type = 0; 674 675 if (attr_pattern_match(attr, cpu_c, ARRAY_SIZE(cpu_c))) { 676 type |= XTENSA_MPU_TYPE_CPU_CACHE; 677 if (attr & 0x10) { 678 type |= XTENSA_MPU_TYPE_CPU_C; 679 } 680 if (attr & 0x20) { 681 type |= XTENSA_MPU_TYPE_CPU_W; 682 } 683 if (attr & 0x40) { 684 type |= XTENSA_MPU_TYPE_CPU_R; 685 } 686 } 687 return type; 688 } 689 690 static unsigned mpu_attr_to_type(uint32_t attr) 691 { 692 static const struct attr_pattern device_type[] = { 693 { .mask = 0x1f6, .value = 0x000 }, 694 { .mask = 0x1f6, .value = 0x006 }, 695 }; 696 static const struct attr_pattern sys_nc_type[] = { 697 { .mask = 0x1fe, .value = 0x018 }, 698 { .mask = 0x1fe, .value = 0x01e }, 699 { .mask = 0x18f, .value = 0x089 }, 700 }; 701 static const struct attr_pattern sys_c_type[] = { 702 { .mask = 0x1f8, .value = 0x010 }, 703 { .mask = 0x188, .value = 0x080 }, 704 { .mask = 0x1f0, .value = 0x030 }, 705 { .mask = 0x180, .value = 0x180 }, 706 }; 707 static const struct attr_pattern b[] = { 708 { .mask = 0x1f7, .value = 0x001 }, 709 { .mask = 0x1f7, .value = 0x007 }, 710 { .mask = 0x1ff, .value = 0x019 }, 711 { .mask = 0x1ff, .value = 0x01f }, 712 }; 713 714 unsigned type = 0; 715 716 attr = (attr & XTENSA_MPU_MEM_TYPE_MASK) >> XTENSA_MPU_MEM_TYPE_SHIFT; 717 if (attr_pattern_match(attr, device_type, ARRAY_SIZE(device_type))) { 718 type |= XTENSA_MPU_SYSTEM_TYPE_DEVICE; 719 if (attr & 0x80) { 720 type |= XTENSA_MPU_TYPE_INT; 721 } 722 } 723 if (attr_pattern_match(attr, sys_nc_type, ARRAY_SIZE(sys_nc_type))) { 724 type |= XTENSA_MPU_SYSTEM_TYPE_NC; 725 } 726 if (attr_pattern_match(attr, sys_c_type, ARRAY_SIZE(sys_c_type))) { 727 type |= XTENSA_MPU_SYSTEM_TYPE_C; 728 if (attr & 0x1) { 729 type |= XTENSA_MPU_TYPE_SYS_C; 730 } 731 if (attr & 0x2) { 732 type |= XTENSA_MPU_TYPE_SYS_W; 733 } 734 if (attr & 0x4) { 735 type |= XTENSA_MPU_TYPE_SYS_R; 736 } 737 } 738 if (attr_pattern_match(attr, b, ARRAY_SIZE(b))) { 739 type |= XTENSA_MPU_TYPE_B; 740 } 741 type |= mpu_attr_to_cpu_cache(attr); 742 743 return type; 744 } 745 746 static unsigned mpu_attr_to_access(uint32_t attr, unsigned ring) 747 { 748 static const unsigned access[2][16] = { 749 [0] = { 750 [4] = PAGE_READ, 751 [5] = PAGE_READ | PAGE_EXEC, 752 [6] = PAGE_READ | PAGE_WRITE, 753 [7] = PAGE_READ | PAGE_WRITE | PAGE_EXEC, 754 [8] = PAGE_WRITE, 755 [9] = PAGE_READ | PAGE_WRITE, 756 [10] = PAGE_READ | PAGE_WRITE, 757 [11] = PAGE_READ | PAGE_WRITE | PAGE_EXEC, 758 [12] = PAGE_READ, 759 [13] = PAGE_READ | PAGE_EXEC, 760 [14] = PAGE_READ | PAGE_WRITE, 761 [15] = PAGE_READ | PAGE_WRITE | PAGE_EXEC, 762 }, 763 [1] = { 764 [8] = PAGE_WRITE, 765 [9] = PAGE_READ | PAGE_WRITE | PAGE_EXEC, 766 [10] = PAGE_READ, 767 [11] = PAGE_READ | PAGE_EXEC, 768 [12] = PAGE_READ, 769 [13] = PAGE_READ | PAGE_EXEC, 770 [14] = PAGE_READ | PAGE_WRITE, 771 [15] = PAGE_READ | PAGE_WRITE | PAGE_EXEC, 772 }, 773 }; 774 unsigned rv; 775 unsigned type; 776 777 type = mpu_attr_to_cpu_cache(attr); 778 rv = access[ring != 0][(attr & XTENSA_MPU_ACC_RIGHTS_MASK) >> 779 XTENSA_MPU_ACC_RIGHTS_SHIFT]; 780 781 if (type & XTENSA_MPU_TYPE_CPU_CACHE) { 782 rv |= (type & XTENSA_MPU_TYPE_CPU_C) ? PAGE_CACHE_WB : PAGE_CACHE_WT; 783 } else { 784 rv |= PAGE_CACHE_BYPASS; 785 } 786 return rv; 787 } 788 789 static bool is_access_granted(unsigned access, int is_write) 790 { 791 switch (is_write) { 792 case 0: 793 return access & PAGE_READ; 794 795 case 1: 796 return access & PAGE_WRITE; 797 798 case 2: 799 return access & PAGE_EXEC; 800 801 default: 802 return 0; 803 } 804 } 805 806 static bool get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte); 807 808 static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb, 809 uint32_t vaddr, int is_write, int mmu_idx, 810 uint32_t *paddr, uint32_t *page_size, 811 unsigned *access, bool may_lookup_pt) 812 { 813 bool dtlb = is_write != 2; 814 uint32_t wi; 815 uint32_t ei; 816 uint8_t ring; 817 uint32_t vpn; 818 uint32_t pte; 819 const xtensa_tlb_entry *entry = NULL; 820 xtensa_tlb_entry tmp_entry; 821 int ret = xtensa_tlb_lookup(env, vaddr, dtlb, &wi, &ei, &ring); 822 823 if ((ret == INST_TLB_MISS_CAUSE || ret == LOAD_STORE_TLB_MISS_CAUSE) && 824 may_lookup_pt && get_pte(env, vaddr, &pte)) { 825 ring = (pte >> 4) & 0x3; 826 wi = 0; 827 split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, wi, &ei); 828 829 if (update_tlb) { 830 wi = ++env->autorefill_idx & 0x3; 831 xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, pte); 832 env->sregs[EXCVADDR] = vaddr; 833 qemu_log_mask(CPU_LOG_MMU, "%s: autorefill(%08x): %08x -> %08x\n", 834 __func__, vaddr, vpn, pte); 835 } else { 836 xtensa_tlb_set_entry_mmu(env, &tmp_entry, dtlb, wi, ei, vpn, pte); 837 entry = &tmp_entry; 838 } 839 ret = 0; 840 } 841 if (ret != 0) { 842 return ret; 843 } 844 845 if (entry == NULL) { 846 entry = xtensa_tlb_get_entry(env, dtlb, wi, ei); 847 } 848 849 if (ring < mmu_idx) { 850 return dtlb ? 851 LOAD_STORE_PRIVILEGE_CAUSE : 852 INST_FETCH_PRIVILEGE_CAUSE; 853 } 854 855 *access = mmu_attr_to_access(entry->attr) & 856 ~(dtlb ? PAGE_EXEC : PAGE_READ | PAGE_WRITE); 857 if (!is_access_granted(*access, is_write)) { 858 return dtlb ? 859 (is_write ? 860 STORE_PROHIBITED_CAUSE : 861 LOAD_PROHIBITED_CAUSE) : 862 INST_FETCH_PROHIBITED_CAUSE; 863 } 864 865 *paddr = entry->paddr | (vaddr & ~xtensa_tlb_get_addr_mask(env, dtlb, wi)); 866 *page_size = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1; 867 868 return 0; 869 } 870 871 static bool get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte) 872 { 873 CPUState *cs = env_cpu(env); 874 uint32_t paddr; 875 uint32_t page_size; 876 unsigned access; 877 uint32_t pt_vaddr = 878 (env->sregs[PTEVADDR] | (vaddr >> 10)) & 0xfffffffc; 879 int ret = get_physical_addr_mmu(env, false, pt_vaddr, 0, 0, 880 &paddr, &page_size, &access, false); 881 882 if (ret == 0) { 883 qemu_log_mask(CPU_LOG_MMU, 884 "%s: autorefill(%08x): PTE va = %08x, pa = %08x\n", 885 __func__, vaddr, pt_vaddr, paddr); 886 } else { 887 qemu_log_mask(CPU_LOG_MMU, 888 "%s: autorefill(%08x): PTE va = %08x, failed (%d)\n", 889 __func__, vaddr, pt_vaddr, ret); 890 } 891 892 if (ret == 0) { 893 MemTxResult result; 894 895 *pte = address_space_ldl(cs->as, paddr, MEMTXATTRS_UNSPECIFIED, 896 &result); 897 if (result != MEMTX_OK) { 898 qemu_log_mask(CPU_LOG_MMU, 899 "%s: couldn't load PTE: transaction failed (%u)\n", 900 __func__, (unsigned)result); 901 ret = 1; 902 } 903 } 904 return ret == 0; 905 } 906 907 static int get_physical_addr_region(CPUXtensaState *env, 908 uint32_t vaddr, int is_write, int mmu_idx, 909 uint32_t *paddr, uint32_t *page_size, 910 unsigned *access) 911 { 912 bool dtlb = is_write != 2; 913 uint32_t wi = 0; 914 uint32_t ei = (vaddr >> 29) & 0x7; 915 const xtensa_tlb_entry *entry = 916 xtensa_tlb_get_entry(env, dtlb, wi, ei); 917 918 *access = region_attr_to_access(entry->attr); 919 if (!is_access_granted(*access, is_write)) { 920 return dtlb ? 921 (is_write ? 922 STORE_PROHIBITED_CAUSE : 923 LOAD_PROHIBITED_CAUSE) : 924 INST_FETCH_PROHIBITED_CAUSE; 925 } 926 927 *paddr = entry->paddr | (vaddr & ~REGION_PAGE_MASK); 928 *page_size = ~REGION_PAGE_MASK + 1; 929 930 return 0; 931 } 932 933 static int xtensa_mpu_lookup(const xtensa_mpu_entry *entry, unsigned n, 934 uint32_t vaddr, unsigned *segment) 935 { 936 unsigned nhits = 0; 937 unsigned i; 938 939 for (i = 0; i < n; ++i) { 940 if (vaddr >= entry[i].vaddr && 941 (i == n - 1 || vaddr < entry[i + 1].vaddr)) { 942 if (nhits++) { 943 break; 944 } 945 *segment = i; 946 } 947 } 948 return nhits; 949 } 950 951 void HELPER(wsr_mpuenb)(CPUXtensaState *env, uint32_t v) 952 { 953 v &= (2u << (env->config->n_mpu_fg_segments - 1)) - 1; 954 955 if (v != env->sregs[MPUENB]) { 956 env->sregs[MPUENB] = v; 957 tlb_flush(env_cpu(env)); 958 } 959 } 960 961 void HELPER(wptlb)(CPUXtensaState *env, uint32_t p, uint32_t v) 962 { 963 unsigned segment = p & XTENSA_MPU_SEGMENT_MASK; 964 965 if (segment < env->config->n_mpu_fg_segments) { 966 env->mpu_fg[segment].vaddr = v & -env->config->mpu_align; 967 env->mpu_fg[segment].attr = p & XTENSA_MPU_ATTR_MASK; 968 env->sregs[MPUENB] = deposit32(env->sregs[MPUENB], segment, 1, v); 969 tlb_flush(env_cpu(env)); 970 } 971 } 972 973 uint32_t HELPER(rptlb0)(CPUXtensaState *env, uint32_t s) 974 { 975 unsigned segment = s & XTENSA_MPU_SEGMENT_MASK; 976 977 if (segment < env->config->n_mpu_fg_segments) { 978 return env->mpu_fg[segment].vaddr | 979 extract32(env->sregs[MPUENB], segment, 1); 980 } else { 981 return 0; 982 } 983 } 984 985 uint32_t HELPER(rptlb1)(CPUXtensaState *env, uint32_t s) 986 { 987 unsigned segment = s & XTENSA_MPU_SEGMENT_MASK; 988 989 if (segment < env->config->n_mpu_fg_segments) { 990 return env->mpu_fg[segment].attr; 991 } else { 992 return 0; 993 } 994 } 995 996 uint32_t HELPER(pptlb)(CPUXtensaState *env, uint32_t v) 997 { 998 unsigned nhits; 999 unsigned segment; 1000 unsigned bg_segment; 1001 1002 nhits = xtensa_mpu_lookup(env->mpu_fg, env->config->n_mpu_fg_segments, 1003 v, &segment); 1004 if (nhits > 1) { 1005 HELPER(exception_cause_vaddr)(env, env->pc, 1006 LOAD_STORE_TLB_MULTI_HIT_CAUSE, v); 1007 } else if (nhits == 1 && (env->sregs[MPUENB] & (1u << segment))) { 1008 return env->mpu_fg[segment].attr | segment | XTENSA_MPU_PROBE_V; 1009 } else { 1010 xtensa_mpu_lookup(env->config->mpu_bg, 1011 env->config->n_mpu_bg_segments, 1012 v, &bg_segment); 1013 return env->config->mpu_bg[bg_segment].attr | XTENSA_MPU_PROBE_B; 1014 } 1015 } 1016 1017 static int get_physical_addr_mpu(CPUXtensaState *env, 1018 uint32_t vaddr, int is_write, int mmu_idx, 1019 uint32_t *paddr, uint32_t *page_size, 1020 unsigned *access) 1021 { 1022 unsigned nhits; 1023 unsigned segment; 1024 uint32_t attr; 1025 1026 nhits = xtensa_mpu_lookup(env->mpu_fg, env->config->n_mpu_fg_segments, 1027 vaddr, &segment); 1028 if (nhits > 1) { 1029 return is_write < 2 ? 1030 LOAD_STORE_TLB_MULTI_HIT_CAUSE : 1031 INST_TLB_MULTI_HIT_CAUSE; 1032 } else if (nhits == 1 && (env->sregs[MPUENB] & (1u << segment))) { 1033 attr = env->mpu_fg[segment].attr; 1034 } else { 1035 xtensa_mpu_lookup(env->config->mpu_bg, 1036 env->config->n_mpu_bg_segments, 1037 vaddr, &segment); 1038 attr = env->config->mpu_bg[segment].attr; 1039 } 1040 1041 *access = mpu_attr_to_access(attr, mmu_idx); 1042 if (!is_access_granted(*access, is_write)) { 1043 return is_write < 2 ? 1044 (is_write ? 1045 STORE_PROHIBITED_CAUSE : 1046 LOAD_PROHIBITED_CAUSE) : 1047 INST_FETCH_PROHIBITED_CAUSE; 1048 } 1049 *paddr = vaddr; 1050 *page_size = env->config->mpu_align; 1051 return 0; 1052 } 1053 1054 /*! 1055 * Convert virtual address to physical addr. 1056 * MMU may issue pagewalk and change xtensa autorefill TLB way entry. 1057 * 1058 * \return 0 if ok, exception cause code otherwise 1059 */ 1060 int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb, 1061 uint32_t vaddr, int is_write, int mmu_idx, 1062 uint32_t *paddr, uint32_t *page_size, 1063 unsigned *access) 1064 { 1065 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 1066 return get_physical_addr_mmu(env, update_tlb, 1067 vaddr, is_write, mmu_idx, paddr, 1068 page_size, access, true); 1069 } else if (xtensa_option_bits_enabled(env->config, 1070 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) | 1071 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION))) { 1072 return get_physical_addr_region(env, vaddr, is_write, mmu_idx, 1073 paddr, page_size, access); 1074 } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_MPU)) { 1075 return get_physical_addr_mpu(env, vaddr, is_write, mmu_idx, 1076 paddr, page_size, access); 1077 } else { 1078 *paddr = vaddr; 1079 *page_size = TARGET_PAGE_SIZE; 1080 *access = cacheattr_attr_to_access(env->sregs[CACHEATTR] >> 1081 ((vaddr & 0xe0000000) >> 27)); 1082 return 0; 1083 } 1084 } 1085 1086 static void dump_tlb(CPUXtensaState *env, bool dtlb) 1087 { 1088 unsigned wi, ei; 1089 const xtensa_tlb *conf = 1090 dtlb ? &env->config->dtlb : &env->config->itlb; 1091 unsigned (*attr_to_access)(uint32_t) = 1092 xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) ? 1093 mmu_attr_to_access : region_attr_to_access; 1094 1095 for (wi = 0; wi < conf->nways; ++wi) { 1096 uint32_t sz = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1; 1097 const char *sz_text; 1098 bool print_header = true; 1099 1100 if (sz >= 0x100000) { 1101 sz /= MiB; 1102 sz_text = "MB"; 1103 } else { 1104 sz /= KiB; 1105 sz_text = "KB"; 1106 } 1107 1108 for (ei = 0; ei < conf->way_size[wi]; ++ei) { 1109 const xtensa_tlb_entry *entry = 1110 xtensa_tlb_get_entry(env, dtlb, wi, ei); 1111 1112 if (entry->asid) { 1113 static const char * const cache_text[8] = { 1114 [PAGE_CACHE_BYPASS >> PAGE_CACHE_SHIFT] = "Bypass", 1115 [PAGE_CACHE_WT >> PAGE_CACHE_SHIFT] = "WT", 1116 [PAGE_CACHE_WB >> PAGE_CACHE_SHIFT] = "WB", 1117 [PAGE_CACHE_ISOLATE >> PAGE_CACHE_SHIFT] = "Isolate", 1118 }; 1119 unsigned access = attr_to_access(entry->attr); 1120 unsigned cache_idx = (access & PAGE_CACHE_MASK) >> 1121 PAGE_CACHE_SHIFT; 1122 1123 if (print_header) { 1124 print_header = false; 1125 qemu_printf("Way %u (%d %s)\n", wi, sz, sz_text); 1126 qemu_printf("\tVaddr Paddr ASID Attr RWX Cache\n" 1127 "\t---------- ---------- ---- ---- --- -------\n"); 1128 } 1129 qemu_printf("\t0x%08x 0x%08x 0x%02x 0x%02x %c%c%c %s\n", 1130 entry->vaddr, 1131 entry->paddr, 1132 entry->asid, 1133 entry->attr, 1134 (access & PAGE_READ) ? 'R' : '-', 1135 (access & PAGE_WRITE) ? 'W' : '-', 1136 (access & PAGE_EXEC) ? 'X' : '-', 1137 cache_text[cache_idx] ? 1138 cache_text[cache_idx] : "Invalid"); 1139 } 1140 } 1141 } 1142 } 1143 1144 static void dump_mpu(CPUXtensaState *env, 1145 const xtensa_mpu_entry *entry, unsigned n) 1146 { 1147 unsigned i; 1148 1149 qemu_printf("\t%s Vaddr Attr Ring0 Ring1 System Type CPU cache\n" 1150 "\t%s ---------- ---------- ----- ----- ------------- ---------\n", 1151 env ? "En" : " ", 1152 env ? "--" : " "); 1153 1154 for (i = 0; i < n; ++i) { 1155 uint32_t attr = entry[i].attr; 1156 unsigned access0 = mpu_attr_to_access(attr, 0); 1157 unsigned access1 = mpu_attr_to_access(attr, 1); 1158 unsigned type = mpu_attr_to_type(attr); 1159 char cpu_cache = (type & XTENSA_MPU_TYPE_CPU_CACHE) ? '-' : ' '; 1160 1161 qemu_printf("\t %c 0x%08x 0x%08x %c%c%c %c%c%c ", 1162 env ? 1163 ((env->sregs[MPUENB] & (1u << i)) ? '+' : '-') : ' ', 1164 entry[i].vaddr, attr, 1165 (access0 & PAGE_READ) ? 'R' : '-', 1166 (access0 & PAGE_WRITE) ? 'W' : '-', 1167 (access0 & PAGE_EXEC) ? 'X' : '-', 1168 (access1 & PAGE_READ) ? 'R' : '-', 1169 (access1 & PAGE_WRITE) ? 'W' : '-', 1170 (access1 & PAGE_EXEC) ? 'X' : '-'); 1171 1172 switch (type & XTENSA_MPU_SYSTEM_TYPE_MASK) { 1173 case XTENSA_MPU_SYSTEM_TYPE_DEVICE: 1174 qemu_printf("Device %cB %3s\n", 1175 (type & XTENSA_MPU_TYPE_B) ? ' ' : 'n', 1176 (type & XTENSA_MPU_TYPE_INT) ? "int" : ""); 1177 break; 1178 case XTENSA_MPU_SYSTEM_TYPE_NC: 1179 qemu_printf("Sys NC %cB %c%c%c\n", 1180 (type & XTENSA_MPU_TYPE_B) ? ' ' : 'n', 1181 (type & XTENSA_MPU_TYPE_CPU_R) ? 'r' : cpu_cache, 1182 (type & XTENSA_MPU_TYPE_CPU_W) ? 'w' : cpu_cache, 1183 (type & XTENSA_MPU_TYPE_CPU_C) ? 'c' : cpu_cache); 1184 break; 1185 case XTENSA_MPU_SYSTEM_TYPE_C: 1186 qemu_printf("Sys C %c%c%c %c%c%c\n", 1187 (type & XTENSA_MPU_TYPE_SYS_R) ? 'R' : '-', 1188 (type & XTENSA_MPU_TYPE_SYS_W) ? 'W' : '-', 1189 (type & XTENSA_MPU_TYPE_SYS_C) ? 'C' : '-', 1190 (type & XTENSA_MPU_TYPE_CPU_R) ? 'r' : cpu_cache, 1191 (type & XTENSA_MPU_TYPE_CPU_W) ? 'w' : cpu_cache, 1192 (type & XTENSA_MPU_TYPE_CPU_C) ? 'c' : cpu_cache); 1193 break; 1194 default: 1195 qemu_printf("Unknown\n"); 1196 break; 1197 } 1198 } 1199 } 1200 1201 void dump_mmu(CPUXtensaState *env) 1202 { 1203 if (xtensa_option_bits_enabled(env->config, 1204 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) | 1205 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION) | 1206 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU))) { 1207 1208 qemu_printf("ITLB:\n"); 1209 dump_tlb(env, false); 1210 qemu_printf("\nDTLB:\n"); 1211 dump_tlb(env, true); 1212 } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_MPU)) { 1213 qemu_printf("Foreground map:\n"); 1214 dump_mpu(env, env->mpu_fg, env->config->n_mpu_fg_segments); 1215 qemu_printf("\nBackground map:\n"); 1216 dump_mpu(NULL, env->config->mpu_bg, env->config->n_mpu_bg_segments); 1217 } else { 1218 qemu_printf("No TLB for this CPU core\n"); 1219 } 1220 } 1221