1 /* 2 * Copyright (c) 2011 - 2019, Max Filippov, Open Source and Linux Lab. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * * Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * * Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * * Neither the name of the Open Source and Linux Lab nor the 13 * names of its contributors may be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include "qemu/osdep.h" 29 #include "qemu/main-loop.h" 30 #include "qemu/qemu-print.h" 31 #include "qemu/units.h" 32 #include "cpu.h" 33 #include "exec/helper-proto.h" 34 #include "qemu/host-utils.h" 35 #include "exec/exec-all.h" 36 #include "exec/cpu_ldst.h" 37 38 #define XTENSA_MPU_SEGMENT_MASK 0x0000001f 39 #define XTENSA_MPU_ACC_RIGHTS_MASK 0x00000f00 40 #define XTENSA_MPU_ACC_RIGHTS_SHIFT 8 41 #define XTENSA_MPU_MEM_TYPE_MASK 0x001ff000 42 #define XTENSA_MPU_MEM_TYPE_SHIFT 12 43 #define XTENSA_MPU_ATTR_MASK 0x001fff00 44 45 #define XTENSA_MPU_PROBE_B 0x40000000 46 #define XTENSA_MPU_PROBE_V 0x80000000 47 48 #define XTENSA_MPU_SYSTEM_TYPE_DEVICE 0x0001 49 #define XTENSA_MPU_SYSTEM_TYPE_NC 0x0002 50 #define XTENSA_MPU_SYSTEM_TYPE_C 0x0003 51 #define XTENSA_MPU_SYSTEM_TYPE_MASK 0x0003 52 53 #define XTENSA_MPU_TYPE_SYS_C 0x0010 54 #define XTENSA_MPU_TYPE_SYS_W 0x0020 55 #define XTENSA_MPU_TYPE_SYS_R 0x0040 56 #define XTENSA_MPU_TYPE_CPU_C 0x0100 57 #define XTENSA_MPU_TYPE_CPU_W 0x0200 58 #define XTENSA_MPU_TYPE_CPU_R 0x0400 59 #define XTENSA_MPU_TYPE_CPU_CACHE 0x0800 60 #define XTENSA_MPU_TYPE_B 0x1000 61 #define XTENSA_MPU_TYPE_INT 0x2000 62 63 void HELPER(itlb_hit_test)(CPUXtensaState *env, uint32_t vaddr) 64 { 65 /* 66 * Attempt the memory load; we don't care about the result but 67 * only the side-effects (ie any MMU or other exception) 68 */ 69 cpu_ldub_code_ra(env, vaddr, GETPC()); 70 } 71 72 void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v) 73 { 74 XtensaCPU *cpu = xtensa_env_get_cpu(env); 75 76 v = (v & 0xffffff00) | 0x1; 77 if (v != env->sregs[RASID]) { 78 env->sregs[RASID] = v; 79 tlb_flush(CPU(cpu)); 80 } 81 } 82 83 static uint32_t get_page_size(const CPUXtensaState *env, 84 bool dtlb, uint32_t way) 85 { 86 uint32_t tlbcfg = env->sregs[dtlb ? DTLBCFG : ITLBCFG]; 87 88 switch (way) { 89 case 4: 90 return (tlbcfg >> 16) & 0x3; 91 92 case 5: 93 return (tlbcfg >> 20) & 0x1; 94 95 case 6: 96 return (tlbcfg >> 24) & 0x1; 97 98 default: 99 return 0; 100 } 101 } 102 103 /*! 104 * Get bit mask for the virtual address bits translated by the TLB way 105 */ 106 static uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, 107 bool dtlb, uint32_t way) 108 { 109 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 110 bool varway56 = dtlb ? 111 env->config->dtlb.varway56 : 112 env->config->itlb.varway56; 113 114 switch (way) { 115 case 4: 116 return 0xfff00000 << get_page_size(env, dtlb, way) * 2; 117 118 case 5: 119 if (varway56) { 120 return 0xf8000000 << get_page_size(env, dtlb, way); 121 } else { 122 return 0xf8000000; 123 } 124 125 case 6: 126 if (varway56) { 127 return 0xf0000000 << (1 - get_page_size(env, dtlb, way)); 128 } else { 129 return 0xf0000000; 130 } 131 132 default: 133 return 0xfffff000; 134 } 135 } else { 136 return REGION_PAGE_MASK; 137 } 138 } 139 140 /*! 141 * Get bit mask for the 'VPN without index' field. 142 * See ISA, 4.6.5.6, data format for RxTLB0 143 */ 144 static uint32_t get_vpn_mask(const CPUXtensaState *env, bool dtlb, uint32_t way) 145 { 146 if (way < 4) { 147 bool is32 = (dtlb ? 148 env->config->dtlb.nrefillentries : 149 env->config->itlb.nrefillentries) == 32; 150 return is32 ? 0xffff8000 : 0xffffc000; 151 } else if (way == 4) { 152 return xtensa_tlb_get_addr_mask(env, dtlb, way) << 2; 153 } else if (way <= 6) { 154 uint32_t mask = xtensa_tlb_get_addr_mask(env, dtlb, way); 155 bool varway56 = dtlb ? 156 env->config->dtlb.varway56 : 157 env->config->itlb.varway56; 158 159 if (varway56) { 160 return mask << (way == 5 ? 2 : 3); 161 } else { 162 return mask << 1; 163 } 164 } else { 165 return 0xfffff000; 166 } 167 } 168 169 /*! 170 * Split virtual address into VPN (with index) and entry index 171 * for the given TLB way 172 */ 173 static void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, 174 bool dtlb, uint32_t *vpn, 175 uint32_t wi, uint32_t *ei) 176 { 177 bool varway56 = dtlb ? 178 env->config->dtlb.varway56 : 179 env->config->itlb.varway56; 180 181 if (!dtlb) { 182 wi &= 7; 183 } 184 185 if (wi < 4) { 186 bool is32 = (dtlb ? 187 env->config->dtlb.nrefillentries : 188 env->config->itlb.nrefillentries) == 32; 189 *ei = (v >> 12) & (is32 ? 0x7 : 0x3); 190 } else { 191 switch (wi) { 192 case 4: 193 { 194 uint32_t eibase = 20 + get_page_size(env, dtlb, wi) * 2; 195 *ei = (v >> eibase) & 0x3; 196 } 197 break; 198 199 case 5: 200 if (varway56) { 201 uint32_t eibase = 27 + get_page_size(env, dtlb, wi); 202 *ei = (v >> eibase) & 0x3; 203 } else { 204 *ei = (v >> 27) & 0x1; 205 } 206 break; 207 208 case 6: 209 if (varway56) { 210 uint32_t eibase = 29 - get_page_size(env, dtlb, wi); 211 *ei = (v >> eibase) & 0x7; 212 } else { 213 *ei = (v >> 28) & 0x1; 214 } 215 break; 216 217 default: 218 *ei = 0; 219 break; 220 } 221 } 222 *vpn = v & xtensa_tlb_get_addr_mask(env, dtlb, wi); 223 } 224 225 /*! 226 * Split TLB address into TLB way, entry index and VPN (with index). 227 * See ISA, 4.6.5.5 - 4.6.5.8 for the TLB addressing format 228 */ 229 static void split_tlb_entry_spec(CPUXtensaState *env, uint32_t v, bool dtlb, 230 uint32_t *vpn, uint32_t *wi, uint32_t *ei) 231 { 232 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 233 *wi = v & (dtlb ? 0xf : 0x7); 234 split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei); 235 } else { 236 *vpn = v & REGION_PAGE_MASK; 237 *wi = 0; 238 *ei = (v >> 29) & 0x7; 239 } 240 } 241 242 static xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env, bool dtlb, 243 unsigned wi, unsigned ei) 244 { 245 return dtlb ? 246 env->dtlb[wi] + ei : 247 env->itlb[wi] + ei; 248 } 249 250 static xtensa_tlb_entry *get_tlb_entry(CPUXtensaState *env, 251 uint32_t v, bool dtlb, uint32_t *pwi) 252 { 253 uint32_t vpn; 254 uint32_t wi; 255 uint32_t ei; 256 257 split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei); 258 if (pwi) { 259 *pwi = wi; 260 } 261 return xtensa_tlb_get_entry(env, dtlb, wi, ei); 262 } 263 264 static void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env, 265 xtensa_tlb_entry *entry, bool dtlb, 266 unsigned wi, unsigned ei, uint32_t vpn, 267 uint32_t pte) 268 { 269 entry->vaddr = vpn; 270 entry->paddr = pte & xtensa_tlb_get_addr_mask(env, dtlb, wi); 271 entry->asid = (env->sregs[RASID] >> ((pte >> 1) & 0x18)) & 0xff; 272 entry->attr = pte & 0xf; 273 } 274 275 static void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb, 276 unsigned wi, unsigned ei, 277 uint32_t vpn, uint32_t pte) 278 { 279 XtensaCPU *cpu = xtensa_env_get_cpu(env); 280 CPUState *cs = CPU(cpu); 281 xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei); 282 283 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 284 if (entry->variable) { 285 if (entry->asid) { 286 tlb_flush_page(cs, entry->vaddr); 287 } 288 xtensa_tlb_set_entry_mmu(env, entry, dtlb, wi, ei, vpn, pte); 289 tlb_flush_page(cs, entry->vaddr); 290 } else { 291 qemu_log_mask(LOG_GUEST_ERROR, 292 "%s %d, %d, %d trying to set immutable entry\n", 293 __func__, dtlb, wi, ei); 294 } 295 } else { 296 tlb_flush_page(cs, entry->vaddr); 297 if (xtensa_option_enabled(env->config, 298 XTENSA_OPTION_REGION_TRANSLATION)) { 299 entry->paddr = pte & REGION_PAGE_MASK; 300 } 301 entry->attr = pte & 0xf; 302 } 303 } 304 305 hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) 306 { 307 XtensaCPU *cpu = XTENSA_CPU(cs); 308 uint32_t paddr; 309 uint32_t page_size; 310 unsigned access; 311 312 if (xtensa_get_physical_addr(&cpu->env, false, addr, 0, 0, 313 &paddr, &page_size, &access) == 0) { 314 return paddr; 315 } 316 if (xtensa_get_physical_addr(&cpu->env, false, addr, 2, 0, 317 &paddr, &page_size, &access) == 0) { 318 return paddr; 319 } 320 return ~0; 321 } 322 323 static void reset_tlb_mmu_all_ways(CPUXtensaState *env, 324 const xtensa_tlb *tlb, 325 xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE]) 326 { 327 unsigned wi, ei; 328 329 for (wi = 0; wi < tlb->nways; ++wi) { 330 for (ei = 0; ei < tlb->way_size[wi]; ++ei) { 331 entry[wi][ei].asid = 0; 332 entry[wi][ei].variable = true; 333 } 334 } 335 } 336 337 static void reset_tlb_mmu_ways56(CPUXtensaState *env, 338 const xtensa_tlb *tlb, 339 xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE]) 340 { 341 if (!tlb->varway56) { 342 static const xtensa_tlb_entry way5[] = { 343 { 344 .vaddr = 0xd0000000, 345 .paddr = 0, 346 .asid = 1, 347 .attr = 7, 348 .variable = false, 349 }, { 350 .vaddr = 0xd8000000, 351 .paddr = 0, 352 .asid = 1, 353 .attr = 3, 354 .variable = false, 355 } 356 }; 357 static const xtensa_tlb_entry way6[] = { 358 { 359 .vaddr = 0xe0000000, 360 .paddr = 0xf0000000, 361 .asid = 1, 362 .attr = 7, 363 .variable = false, 364 }, { 365 .vaddr = 0xf0000000, 366 .paddr = 0xf0000000, 367 .asid = 1, 368 .attr = 3, 369 .variable = false, 370 } 371 }; 372 memcpy(entry[5], way5, sizeof(way5)); 373 memcpy(entry[6], way6, sizeof(way6)); 374 } else { 375 uint32_t ei; 376 for (ei = 0; ei < 8; ++ei) { 377 entry[6][ei].vaddr = ei << 29; 378 entry[6][ei].paddr = ei << 29; 379 entry[6][ei].asid = 1; 380 entry[6][ei].attr = 3; 381 } 382 } 383 } 384 385 static void reset_tlb_region_way0(CPUXtensaState *env, 386 xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE]) 387 { 388 unsigned ei; 389 390 for (ei = 0; ei < 8; ++ei) { 391 entry[0][ei].vaddr = ei << 29; 392 entry[0][ei].paddr = ei << 29; 393 entry[0][ei].asid = 1; 394 entry[0][ei].attr = 2; 395 entry[0][ei].variable = true; 396 } 397 } 398 399 void reset_mmu(CPUXtensaState *env) 400 { 401 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 402 env->sregs[RASID] = 0x04030201; 403 env->sregs[ITLBCFG] = 0; 404 env->sregs[DTLBCFG] = 0; 405 env->autorefill_idx = 0; 406 reset_tlb_mmu_all_ways(env, &env->config->itlb, env->itlb); 407 reset_tlb_mmu_all_ways(env, &env->config->dtlb, env->dtlb); 408 reset_tlb_mmu_ways56(env, &env->config->itlb, env->itlb); 409 reset_tlb_mmu_ways56(env, &env->config->dtlb, env->dtlb); 410 } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_MPU)) { 411 unsigned i; 412 413 env->sregs[MPUENB] = 0; 414 env->sregs[MPUCFG] = env->config->n_mpu_fg_segments; 415 env->sregs[CACHEADRDIS] = 0; 416 assert(env->config->n_mpu_bg_segments > 0 && 417 env->config->mpu_bg[0].vaddr == 0); 418 for (i = 1; i < env->config->n_mpu_bg_segments; ++i) { 419 assert(env->config->mpu_bg[i].vaddr >= 420 env->config->mpu_bg[i - 1].vaddr); 421 } 422 } else { 423 env->sregs[CACHEATTR] = 0x22222222; 424 reset_tlb_region_way0(env, env->itlb); 425 reset_tlb_region_way0(env, env->dtlb); 426 } 427 } 428 429 static unsigned get_ring(const CPUXtensaState *env, uint8_t asid) 430 { 431 unsigned i; 432 for (i = 0; i < 4; ++i) { 433 if (((env->sregs[RASID] >> i * 8) & 0xff) == asid) { 434 return i; 435 } 436 } 437 return 0xff; 438 } 439 440 /*! 441 * Lookup xtensa TLB for the given virtual address. 442 * See ISA, 4.6.2.2 443 * 444 * \param pwi: [out] way index 445 * \param pei: [out] entry index 446 * \param pring: [out] access ring 447 * \return 0 if ok, exception cause code otherwise 448 */ 449 static int xtensa_tlb_lookup(const CPUXtensaState *env, 450 uint32_t addr, bool dtlb, 451 uint32_t *pwi, uint32_t *pei, uint8_t *pring) 452 { 453 const xtensa_tlb *tlb = dtlb ? 454 &env->config->dtlb : &env->config->itlb; 455 const xtensa_tlb_entry (*entry)[MAX_TLB_WAY_SIZE] = dtlb ? 456 env->dtlb : env->itlb; 457 458 int nhits = 0; 459 unsigned wi; 460 461 for (wi = 0; wi < tlb->nways; ++wi) { 462 uint32_t vpn; 463 uint32_t ei; 464 split_tlb_entry_spec_way(env, addr, dtlb, &vpn, wi, &ei); 465 if (entry[wi][ei].vaddr == vpn && entry[wi][ei].asid) { 466 unsigned ring = get_ring(env, entry[wi][ei].asid); 467 if (ring < 4) { 468 if (++nhits > 1) { 469 return dtlb ? 470 LOAD_STORE_TLB_MULTI_HIT_CAUSE : 471 INST_TLB_MULTI_HIT_CAUSE; 472 } 473 *pwi = wi; 474 *pei = ei; 475 *pring = ring; 476 } 477 } 478 } 479 return nhits ? 0 : 480 (dtlb ? LOAD_STORE_TLB_MISS_CAUSE : INST_TLB_MISS_CAUSE); 481 } 482 483 uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) 484 { 485 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 486 uint32_t wi; 487 const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi); 488 return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->asid; 489 } else { 490 return v & REGION_PAGE_MASK; 491 } 492 } 493 494 uint32_t HELPER(rtlb1)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) 495 { 496 const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, NULL); 497 return entry->paddr | entry->attr; 498 } 499 500 void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) 501 { 502 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 503 uint32_t wi; 504 xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi); 505 if (entry->variable && entry->asid) { 506 tlb_flush_page(CPU(xtensa_env_get_cpu(env)), entry->vaddr); 507 entry->asid = 0; 508 } 509 } 510 } 511 512 uint32_t HELPER(ptlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) 513 { 514 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 515 uint32_t wi; 516 uint32_t ei; 517 uint8_t ring; 518 int res = xtensa_tlb_lookup(env, v, dtlb, &wi, &ei, &ring); 519 520 switch (res) { 521 case 0: 522 if (ring >= xtensa_get_ring(env)) { 523 return (v & 0xfffff000) | wi | (dtlb ? 0x10 : 0x8); 524 } 525 break; 526 527 case INST_TLB_MULTI_HIT_CAUSE: 528 case LOAD_STORE_TLB_MULTI_HIT_CAUSE: 529 HELPER(exception_cause_vaddr)(env, env->pc, res, v); 530 break; 531 } 532 return 0; 533 } else { 534 return (v & REGION_PAGE_MASK) | 0x1; 535 } 536 } 537 538 void HELPER(wtlb)(CPUXtensaState *env, uint32_t p, uint32_t v, uint32_t dtlb) 539 { 540 uint32_t vpn; 541 uint32_t wi; 542 uint32_t ei; 543 split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei); 544 xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, p); 545 } 546 547 /*! 548 * Convert MMU ATTR to PAGE_{READ,WRITE,EXEC} mask. 549 * See ISA, 4.6.5.10 550 */ 551 static unsigned mmu_attr_to_access(uint32_t attr) 552 { 553 unsigned access = 0; 554 555 if (attr < 12) { 556 access |= PAGE_READ; 557 if (attr & 0x1) { 558 access |= PAGE_EXEC; 559 } 560 if (attr & 0x2) { 561 access |= PAGE_WRITE; 562 } 563 564 switch (attr & 0xc) { 565 case 0: 566 access |= PAGE_CACHE_BYPASS; 567 break; 568 569 case 4: 570 access |= PAGE_CACHE_WB; 571 break; 572 573 case 8: 574 access |= PAGE_CACHE_WT; 575 break; 576 } 577 } else if (attr == 13) { 578 access |= PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE; 579 } 580 return access; 581 } 582 583 /*! 584 * Convert region protection ATTR to PAGE_{READ,WRITE,EXEC} mask. 585 * See ISA, 4.6.3.3 586 */ 587 static unsigned region_attr_to_access(uint32_t attr) 588 { 589 static const unsigned access[16] = { 590 [0] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_WT, 591 [1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT, 592 [2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS, 593 [3] = PAGE_EXEC | PAGE_CACHE_WB, 594 [4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB, 595 [5] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB, 596 [14] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE, 597 }; 598 599 return access[attr & 0xf]; 600 } 601 602 /*! 603 * Convert cacheattr to PAGE_{READ,WRITE,EXEC} mask. 604 * See ISA, A.2.14 The Cache Attribute Register 605 */ 606 static unsigned cacheattr_attr_to_access(uint32_t attr) 607 { 608 static const unsigned access[16] = { 609 [0] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_WT, 610 [1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT, 611 [2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS, 612 [3] = PAGE_EXEC | PAGE_CACHE_WB, 613 [4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB, 614 [14] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE, 615 }; 616 617 return access[attr & 0xf]; 618 } 619 620 struct attr_pattern { 621 uint32_t mask; 622 uint32_t value; 623 }; 624 625 static int attr_pattern_match(uint32_t attr, 626 const struct attr_pattern *pattern, 627 size_t n) 628 { 629 size_t i; 630 631 for (i = 0; i < n; ++i) { 632 if ((attr & pattern[i].mask) == pattern[i].value) { 633 return 1; 634 } 635 } 636 return 0; 637 } 638 639 static unsigned mpu_attr_to_cpu_cache(uint32_t attr) 640 { 641 static const struct attr_pattern cpu_c[] = { 642 { .mask = 0x18f, .value = 0x089 }, 643 { .mask = 0x188, .value = 0x080 }, 644 { .mask = 0x180, .value = 0x180 }, 645 }; 646 647 unsigned type = 0; 648 649 if (attr_pattern_match(attr, cpu_c, ARRAY_SIZE(cpu_c))) { 650 type |= XTENSA_MPU_TYPE_CPU_CACHE; 651 if (attr & 0x10) { 652 type |= XTENSA_MPU_TYPE_CPU_C; 653 } 654 if (attr & 0x20) { 655 type |= XTENSA_MPU_TYPE_CPU_W; 656 } 657 if (attr & 0x40) { 658 type |= XTENSA_MPU_TYPE_CPU_R; 659 } 660 } 661 return type; 662 } 663 664 static unsigned mpu_attr_to_type(uint32_t attr) 665 { 666 static const struct attr_pattern device_type[] = { 667 { .mask = 0x1f6, .value = 0x000 }, 668 { .mask = 0x1f6, .value = 0x006 }, 669 }; 670 static const struct attr_pattern sys_nc_type[] = { 671 { .mask = 0x1fe, .value = 0x018 }, 672 { .mask = 0x1fe, .value = 0x01e }, 673 { .mask = 0x18f, .value = 0x089 }, 674 }; 675 static const struct attr_pattern sys_c_type[] = { 676 { .mask = 0x1f8, .value = 0x010 }, 677 { .mask = 0x188, .value = 0x080 }, 678 { .mask = 0x1f0, .value = 0x030 }, 679 { .mask = 0x180, .value = 0x180 }, 680 }; 681 static const struct attr_pattern b[] = { 682 { .mask = 0x1f7, .value = 0x001 }, 683 { .mask = 0x1f7, .value = 0x007 }, 684 { .mask = 0x1ff, .value = 0x019 }, 685 { .mask = 0x1ff, .value = 0x01f }, 686 }; 687 688 unsigned type = 0; 689 690 attr = (attr & XTENSA_MPU_MEM_TYPE_MASK) >> XTENSA_MPU_MEM_TYPE_SHIFT; 691 if (attr_pattern_match(attr, device_type, ARRAY_SIZE(device_type))) { 692 type |= XTENSA_MPU_SYSTEM_TYPE_DEVICE; 693 if (attr & 0x80) { 694 type |= XTENSA_MPU_TYPE_INT; 695 } 696 } 697 if (attr_pattern_match(attr, sys_nc_type, ARRAY_SIZE(sys_nc_type))) { 698 type |= XTENSA_MPU_SYSTEM_TYPE_NC; 699 } 700 if (attr_pattern_match(attr, sys_c_type, ARRAY_SIZE(sys_c_type))) { 701 type |= XTENSA_MPU_SYSTEM_TYPE_C; 702 if (attr & 0x1) { 703 type |= XTENSA_MPU_TYPE_SYS_C; 704 } 705 if (attr & 0x2) { 706 type |= XTENSA_MPU_TYPE_SYS_W; 707 } 708 if (attr & 0x4) { 709 type |= XTENSA_MPU_TYPE_SYS_R; 710 } 711 } 712 if (attr_pattern_match(attr, b, ARRAY_SIZE(b))) { 713 type |= XTENSA_MPU_TYPE_B; 714 } 715 type |= mpu_attr_to_cpu_cache(attr); 716 717 return type; 718 } 719 720 static unsigned mpu_attr_to_access(uint32_t attr, unsigned ring) 721 { 722 static const unsigned access[2][16] = { 723 [0] = { 724 [4] = PAGE_READ, 725 [5] = PAGE_READ | PAGE_EXEC, 726 [6] = PAGE_READ | PAGE_WRITE, 727 [7] = PAGE_READ | PAGE_WRITE | PAGE_EXEC, 728 [8] = PAGE_WRITE, 729 [9] = PAGE_READ | PAGE_WRITE, 730 [10] = PAGE_READ | PAGE_WRITE, 731 [11] = PAGE_READ | PAGE_WRITE | PAGE_EXEC, 732 [12] = PAGE_READ, 733 [13] = PAGE_READ | PAGE_EXEC, 734 [14] = PAGE_READ | PAGE_WRITE, 735 [15] = PAGE_READ | PAGE_WRITE | PAGE_EXEC, 736 }, 737 [1] = { 738 [8] = PAGE_WRITE, 739 [9] = PAGE_READ | PAGE_WRITE | PAGE_EXEC, 740 [10] = PAGE_READ, 741 [11] = PAGE_READ | PAGE_EXEC, 742 [12] = PAGE_READ, 743 [13] = PAGE_READ | PAGE_EXEC, 744 [14] = PAGE_READ | PAGE_WRITE, 745 [15] = PAGE_READ | PAGE_WRITE | PAGE_EXEC, 746 }, 747 }; 748 unsigned rv; 749 unsigned type; 750 751 type = mpu_attr_to_cpu_cache(attr); 752 rv = access[ring != 0][(attr & XTENSA_MPU_ACC_RIGHTS_MASK) >> 753 XTENSA_MPU_ACC_RIGHTS_SHIFT]; 754 755 if (type & XTENSA_MPU_TYPE_CPU_CACHE) { 756 rv |= (type & XTENSA_MPU_TYPE_CPU_C) ? PAGE_CACHE_WB : PAGE_CACHE_WT; 757 } else { 758 rv |= PAGE_CACHE_BYPASS; 759 } 760 return rv; 761 } 762 763 static bool is_access_granted(unsigned access, int is_write) 764 { 765 switch (is_write) { 766 case 0: 767 return access & PAGE_READ; 768 769 case 1: 770 return access & PAGE_WRITE; 771 772 case 2: 773 return access & PAGE_EXEC; 774 775 default: 776 return 0; 777 } 778 } 779 780 static bool get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte); 781 782 static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb, 783 uint32_t vaddr, int is_write, int mmu_idx, 784 uint32_t *paddr, uint32_t *page_size, 785 unsigned *access, bool may_lookup_pt) 786 { 787 bool dtlb = is_write != 2; 788 uint32_t wi; 789 uint32_t ei; 790 uint8_t ring; 791 uint32_t vpn; 792 uint32_t pte; 793 const xtensa_tlb_entry *entry = NULL; 794 xtensa_tlb_entry tmp_entry; 795 int ret = xtensa_tlb_lookup(env, vaddr, dtlb, &wi, &ei, &ring); 796 797 if ((ret == INST_TLB_MISS_CAUSE || ret == LOAD_STORE_TLB_MISS_CAUSE) && 798 may_lookup_pt && get_pte(env, vaddr, &pte)) { 799 ring = (pte >> 4) & 0x3; 800 wi = 0; 801 split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, wi, &ei); 802 803 if (update_tlb) { 804 wi = ++env->autorefill_idx & 0x3; 805 xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, pte); 806 env->sregs[EXCVADDR] = vaddr; 807 qemu_log_mask(CPU_LOG_MMU, "%s: autorefill(%08x): %08x -> %08x\n", 808 __func__, vaddr, vpn, pte); 809 } else { 810 xtensa_tlb_set_entry_mmu(env, &tmp_entry, dtlb, wi, ei, vpn, pte); 811 entry = &tmp_entry; 812 } 813 ret = 0; 814 } 815 if (ret != 0) { 816 return ret; 817 } 818 819 if (entry == NULL) { 820 entry = xtensa_tlb_get_entry(env, dtlb, wi, ei); 821 } 822 823 if (ring < mmu_idx) { 824 return dtlb ? 825 LOAD_STORE_PRIVILEGE_CAUSE : 826 INST_FETCH_PRIVILEGE_CAUSE; 827 } 828 829 *access = mmu_attr_to_access(entry->attr) & 830 ~(dtlb ? PAGE_EXEC : PAGE_READ | PAGE_WRITE); 831 if (!is_access_granted(*access, is_write)) { 832 return dtlb ? 833 (is_write ? 834 STORE_PROHIBITED_CAUSE : 835 LOAD_PROHIBITED_CAUSE) : 836 INST_FETCH_PROHIBITED_CAUSE; 837 } 838 839 *paddr = entry->paddr | (vaddr & ~xtensa_tlb_get_addr_mask(env, dtlb, wi)); 840 *page_size = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1; 841 842 return 0; 843 } 844 845 static bool get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte) 846 { 847 CPUState *cs = CPU(xtensa_env_get_cpu(env)); 848 uint32_t paddr; 849 uint32_t page_size; 850 unsigned access; 851 uint32_t pt_vaddr = 852 (env->sregs[PTEVADDR] | (vaddr >> 10)) & 0xfffffffc; 853 int ret = get_physical_addr_mmu(env, false, pt_vaddr, 0, 0, 854 &paddr, &page_size, &access, false); 855 856 if (ret == 0) { 857 qemu_log_mask(CPU_LOG_MMU, 858 "%s: autorefill(%08x): PTE va = %08x, pa = %08x\n", 859 __func__, vaddr, pt_vaddr, paddr); 860 } else { 861 qemu_log_mask(CPU_LOG_MMU, 862 "%s: autorefill(%08x): PTE va = %08x, failed (%d)\n", 863 __func__, vaddr, pt_vaddr, ret); 864 } 865 866 if (ret == 0) { 867 MemTxResult result; 868 869 *pte = address_space_ldl(cs->as, paddr, MEMTXATTRS_UNSPECIFIED, 870 &result); 871 if (result != MEMTX_OK) { 872 qemu_log_mask(CPU_LOG_MMU, 873 "%s: couldn't load PTE: transaction failed (%u)\n", 874 __func__, (unsigned)result); 875 ret = 1; 876 } 877 } 878 return ret == 0; 879 } 880 881 static int get_physical_addr_region(CPUXtensaState *env, 882 uint32_t vaddr, int is_write, int mmu_idx, 883 uint32_t *paddr, uint32_t *page_size, 884 unsigned *access) 885 { 886 bool dtlb = is_write != 2; 887 uint32_t wi = 0; 888 uint32_t ei = (vaddr >> 29) & 0x7; 889 const xtensa_tlb_entry *entry = 890 xtensa_tlb_get_entry(env, dtlb, wi, ei); 891 892 *access = region_attr_to_access(entry->attr); 893 if (!is_access_granted(*access, is_write)) { 894 return dtlb ? 895 (is_write ? 896 STORE_PROHIBITED_CAUSE : 897 LOAD_PROHIBITED_CAUSE) : 898 INST_FETCH_PROHIBITED_CAUSE; 899 } 900 901 *paddr = entry->paddr | (vaddr & ~REGION_PAGE_MASK); 902 *page_size = ~REGION_PAGE_MASK + 1; 903 904 return 0; 905 } 906 907 static int xtensa_mpu_lookup(const xtensa_mpu_entry *entry, unsigned n, 908 uint32_t vaddr, unsigned *segment) 909 { 910 unsigned nhits = 0; 911 unsigned i; 912 913 for (i = 0; i < n; ++i) { 914 if (vaddr >= entry[i].vaddr && 915 (i == n - 1 || vaddr < entry[i + 1].vaddr)) { 916 if (nhits++) { 917 break; 918 } 919 *segment = i; 920 } 921 } 922 return nhits; 923 } 924 925 void HELPER(wsr_mpuenb)(CPUXtensaState *env, uint32_t v) 926 { 927 XtensaCPU *cpu = xtensa_env_get_cpu(env); 928 929 v &= (2u << (env->config->n_mpu_fg_segments - 1)) - 1; 930 931 if (v != env->sregs[MPUENB]) { 932 env->sregs[MPUENB] = v; 933 tlb_flush(CPU(cpu)); 934 } 935 } 936 937 void HELPER(wptlb)(CPUXtensaState *env, uint32_t p, uint32_t v) 938 { 939 unsigned segment = p & XTENSA_MPU_SEGMENT_MASK; 940 941 if (segment < env->config->n_mpu_fg_segments) { 942 env->mpu_fg[segment].vaddr = v & -env->config->mpu_align; 943 env->mpu_fg[segment].attr = p & XTENSA_MPU_ATTR_MASK; 944 env->sregs[MPUENB] = deposit32(env->sregs[MPUENB], segment, 1, v); 945 tlb_flush(CPU(xtensa_env_get_cpu(env))); 946 } 947 } 948 949 uint32_t HELPER(rptlb0)(CPUXtensaState *env, uint32_t s) 950 { 951 unsigned segment = s & XTENSA_MPU_SEGMENT_MASK; 952 953 if (segment < env->config->n_mpu_fg_segments) { 954 return env->mpu_fg[segment].vaddr | 955 extract32(env->sregs[MPUENB], segment, 1); 956 } else { 957 return 0; 958 } 959 } 960 961 uint32_t HELPER(rptlb1)(CPUXtensaState *env, uint32_t s) 962 { 963 unsigned segment = s & XTENSA_MPU_SEGMENT_MASK; 964 965 if (segment < env->config->n_mpu_fg_segments) { 966 return env->mpu_fg[segment].attr; 967 } else { 968 return 0; 969 } 970 } 971 972 uint32_t HELPER(pptlb)(CPUXtensaState *env, uint32_t v) 973 { 974 unsigned nhits; 975 unsigned segment = XTENSA_MPU_PROBE_B; 976 unsigned bg_segment; 977 978 nhits = xtensa_mpu_lookup(env->mpu_fg, env->config->n_mpu_fg_segments, 979 v, &segment); 980 if (nhits > 1) { 981 HELPER(exception_cause_vaddr)(env, env->pc, 982 LOAD_STORE_TLB_MULTI_HIT_CAUSE, v); 983 } else if (nhits == 1 && (env->sregs[MPUENB] & (1u << segment))) { 984 return env->mpu_fg[segment].attr | segment | XTENSA_MPU_PROBE_V; 985 } else { 986 xtensa_mpu_lookup(env->config->mpu_bg, 987 env->config->n_mpu_bg_segments, 988 v, &bg_segment); 989 return env->config->mpu_bg[bg_segment].attr | segment; 990 } 991 } 992 993 static int get_physical_addr_mpu(CPUXtensaState *env, 994 uint32_t vaddr, int is_write, int mmu_idx, 995 uint32_t *paddr, uint32_t *page_size, 996 unsigned *access) 997 { 998 unsigned nhits; 999 unsigned segment; 1000 uint32_t attr; 1001 1002 nhits = xtensa_mpu_lookup(env->mpu_fg, env->config->n_mpu_fg_segments, 1003 vaddr, &segment); 1004 if (nhits > 1) { 1005 return is_write < 2 ? 1006 LOAD_STORE_TLB_MULTI_HIT_CAUSE : 1007 INST_TLB_MULTI_HIT_CAUSE; 1008 } else if (nhits == 1 && (env->sregs[MPUENB] & (1u << segment))) { 1009 attr = env->mpu_fg[segment].attr; 1010 } else { 1011 xtensa_mpu_lookup(env->config->mpu_bg, 1012 env->config->n_mpu_bg_segments, 1013 vaddr, &segment); 1014 attr = env->config->mpu_bg[segment].attr; 1015 } 1016 1017 *access = mpu_attr_to_access(attr, mmu_idx); 1018 if (!is_access_granted(*access, is_write)) { 1019 return is_write < 2 ? 1020 (is_write ? 1021 STORE_PROHIBITED_CAUSE : 1022 LOAD_PROHIBITED_CAUSE) : 1023 INST_FETCH_PROHIBITED_CAUSE; 1024 } 1025 *paddr = vaddr; 1026 *page_size = env->config->mpu_align; 1027 return 0; 1028 } 1029 1030 /*! 1031 * Convert virtual address to physical addr. 1032 * MMU may issue pagewalk and change xtensa autorefill TLB way entry. 1033 * 1034 * \return 0 if ok, exception cause code otherwise 1035 */ 1036 int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb, 1037 uint32_t vaddr, int is_write, int mmu_idx, 1038 uint32_t *paddr, uint32_t *page_size, 1039 unsigned *access) 1040 { 1041 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 1042 return get_physical_addr_mmu(env, update_tlb, 1043 vaddr, is_write, mmu_idx, paddr, 1044 page_size, access, true); 1045 } else if (xtensa_option_bits_enabled(env->config, 1046 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) | 1047 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION))) { 1048 return get_physical_addr_region(env, vaddr, is_write, mmu_idx, 1049 paddr, page_size, access); 1050 } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_MPU)) { 1051 return get_physical_addr_mpu(env, vaddr, is_write, mmu_idx, 1052 paddr, page_size, access); 1053 } else { 1054 *paddr = vaddr; 1055 *page_size = TARGET_PAGE_SIZE; 1056 *access = cacheattr_attr_to_access(env->sregs[CACHEATTR] >> 1057 ((vaddr & 0xe0000000) >> 27)); 1058 return 0; 1059 } 1060 } 1061 1062 static void dump_tlb(CPUXtensaState *env, bool dtlb) 1063 { 1064 unsigned wi, ei; 1065 const xtensa_tlb *conf = 1066 dtlb ? &env->config->dtlb : &env->config->itlb; 1067 unsigned (*attr_to_access)(uint32_t) = 1068 xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) ? 1069 mmu_attr_to_access : region_attr_to_access; 1070 1071 for (wi = 0; wi < conf->nways; ++wi) { 1072 uint32_t sz = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1; 1073 const char *sz_text; 1074 bool print_header = true; 1075 1076 if (sz >= 0x100000) { 1077 sz /= MiB; 1078 sz_text = "MB"; 1079 } else { 1080 sz /= KiB; 1081 sz_text = "KB"; 1082 } 1083 1084 for (ei = 0; ei < conf->way_size[wi]; ++ei) { 1085 const xtensa_tlb_entry *entry = 1086 xtensa_tlb_get_entry(env, dtlb, wi, ei); 1087 1088 if (entry->asid) { 1089 static const char * const cache_text[8] = { 1090 [PAGE_CACHE_BYPASS >> PAGE_CACHE_SHIFT] = "Bypass", 1091 [PAGE_CACHE_WT >> PAGE_CACHE_SHIFT] = "WT", 1092 [PAGE_CACHE_WB >> PAGE_CACHE_SHIFT] = "WB", 1093 [PAGE_CACHE_ISOLATE >> PAGE_CACHE_SHIFT] = "Isolate", 1094 }; 1095 unsigned access = attr_to_access(entry->attr); 1096 unsigned cache_idx = (access & PAGE_CACHE_MASK) >> 1097 PAGE_CACHE_SHIFT; 1098 1099 if (print_header) { 1100 print_header = false; 1101 qemu_printf("Way %u (%d %s)\n", wi, sz, sz_text); 1102 qemu_printf("\tVaddr Paddr ASID Attr RWX Cache\n" 1103 "\t---------- ---------- ---- ---- --- -------\n"); 1104 } 1105 qemu_printf("\t0x%08x 0x%08x 0x%02x 0x%02x %c%c%c %-7s\n", 1106 entry->vaddr, 1107 entry->paddr, 1108 entry->asid, 1109 entry->attr, 1110 (access & PAGE_READ) ? 'R' : '-', 1111 (access & PAGE_WRITE) ? 'W' : '-', 1112 (access & PAGE_EXEC) ? 'X' : '-', 1113 cache_text[cache_idx] ? 1114 cache_text[cache_idx] : "Invalid"); 1115 } 1116 } 1117 } 1118 } 1119 1120 static void dump_mpu(CPUXtensaState *env, 1121 const xtensa_mpu_entry *entry, unsigned n) 1122 { 1123 unsigned i; 1124 1125 qemu_printf("\t%s Vaddr Attr Ring0 Ring1 System Type CPU cache\n" 1126 "\t%s ---------- ---------- ----- ----- ------------- ---------\n", 1127 env ? "En" : " ", 1128 env ? "--" : " "); 1129 1130 for (i = 0; i < n; ++i) { 1131 uint32_t attr = entry[i].attr; 1132 unsigned access0 = mpu_attr_to_access(attr, 0); 1133 unsigned access1 = mpu_attr_to_access(attr, 1); 1134 unsigned type = mpu_attr_to_type(attr); 1135 char cpu_cache = (type & XTENSA_MPU_TYPE_CPU_CACHE) ? '-' : ' '; 1136 1137 qemu_printf("\t %c 0x%08x 0x%08x %c%c%c %c%c%c ", 1138 env ? 1139 ((env->sregs[MPUENB] & (1u << i)) ? '+' : '-') : ' ', 1140 entry[i].vaddr, attr, 1141 (access0 & PAGE_READ) ? 'R' : '-', 1142 (access0 & PAGE_WRITE) ? 'W' : '-', 1143 (access0 & PAGE_EXEC) ? 'X' : '-', 1144 (access1 & PAGE_READ) ? 'R' : '-', 1145 (access1 & PAGE_WRITE) ? 'W' : '-', 1146 (access1 & PAGE_EXEC) ? 'X' : '-'); 1147 1148 switch (type & XTENSA_MPU_SYSTEM_TYPE_MASK) { 1149 case XTENSA_MPU_SYSTEM_TYPE_DEVICE: 1150 qemu_printf("Device %cB %3s\n", 1151 (type & XTENSA_MPU_TYPE_B) ? ' ' : 'n', 1152 (type & XTENSA_MPU_TYPE_INT) ? "int" : ""); 1153 break; 1154 case XTENSA_MPU_SYSTEM_TYPE_NC: 1155 qemu_printf("Sys NC %cB %c%c%c\n", 1156 (type & XTENSA_MPU_TYPE_B) ? ' ' : 'n', 1157 (type & XTENSA_MPU_TYPE_CPU_R) ? 'r' : cpu_cache, 1158 (type & XTENSA_MPU_TYPE_CPU_W) ? 'w' : cpu_cache, 1159 (type & XTENSA_MPU_TYPE_CPU_C) ? 'c' : cpu_cache); 1160 break; 1161 case XTENSA_MPU_SYSTEM_TYPE_C: 1162 qemu_printf("Sys C %c%c%c %c%c%c\n", 1163 (type & XTENSA_MPU_TYPE_SYS_R) ? 'R' : '-', 1164 (type & XTENSA_MPU_TYPE_SYS_W) ? 'W' : '-', 1165 (type & XTENSA_MPU_TYPE_SYS_C) ? 'C' : '-', 1166 (type & XTENSA_MPU_TYPE_CPU_R) ? 'r' : cpu_cache, 1167 (type & XTENSA_MPU_TYPE_CPU_W) ? 'w' : cpu_cache, 1168 (type & XTENSA_MPU_TYPE_CPU_C) ? 'c' : cpu_cache); 1169 break; 1170 default: 1171 qemu_printf("Unknown\n"); 1172 break; 1173 } 1174 } 1175 } 1176 1177 void dump_mmu(CPUXtensaState *env) 1178 { 1179 if (xtensa_option_bits_enabled(env->config, 1180 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) | 1181 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION) | 1182 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU))) { 1183 1184 qemu_printf("ITLB:\n"); 1185 dump_tlb(env, false); 1186 qemu_printf("\nDTLB:\n"); 1187 dump_tlb(env, true); 1188 } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_MPU)) { 1189 qemu_printf("Foreground map:\n"); 1190 dump_mpu(env, env->mpu_fg, env->config->n_mpu_fg_segments); 1191 qemu_printf("\nBackground map:\n"); 1192 dump_mpu(NULL, env->config->mpu_bg, env->config->n_mpu_bg_segments); 1193 } else { 1194 qemu_printf("No TLB for this CPU core\n"); 1195 } 1196 } 1197