1 /* 2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * * Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * * Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * * Neither the name of the Open Source and Linux Lab nor the 13 * names of its contributors may be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #ifndef XTENSA_CPU_H 29 #define XTENSA_CPU_H 30 31 #include "cpu-qom.h" 32 #include "qemu/cpu-float.h" 33 #include "exec/cpu-defs.h" 34 #include "hw/clock.h" 35 #include "xtensa-isa.h" 36 37 /* Xtensa processors have a weak memory model */ 38 #define TCG_GUEST_DEFAULT_MO (0) 39 40 enum { 41 /* Additional instructions */ 42 XTENSA_OPTION_CODE_DENSITY, 43 XTENSA_OPTION_LOOP, 44 XTENSA_OPTION_EXTENDED_L32R, 45 XTENSA_OPTION_16_BIT_IMUL, 46 XTENSA_OPTION_32_BIT_IMUL, 47 XTENSA_OPTION_32_BIT_IMUL_HIGH, 48 XTENSA_OPTION_32_BIT_IDIV, 49 XTENSA_OPTION_MAC16, 50 XTENSA_OPTION_MISC_OP_NSA, 51 XTENSA_OPTION_MISC_OP_MINMAX, 52 XTENSA_OPTION_MISC_OP_SEXT, 53 XTENSA_OPTION_MISC_OP_CLAMPS, 54 XTENSA_OPTION_COPROCESSOR, 55 XTENSA_OPTION_BOOLEAN, 56 XTENSA_OPTION_FP_COPROCESSOR, 57 XTENSA_OPTION_DFP_COPROCESSOR, 58 XTENSA_OPTION_DFPU_SINGLE_ONLY, 59 XTENSA_OPTION_MP_SYNCHRO, 60 XTENSA_OPTION_CONDITIONAL_STORE, 61 XTENSA_OPTION_ATOMCTL, 62 XTENSA_OPTION_DEPBITS, 63 64 /* Interrupts and exceptions */ 65 XTENSA_OPTION_EXCEPTION, 66 XTENSA_OPTION_RELOCATABLE_VECTOR, 67 XTENSA_OPTION_UNALIGNED_EXCEPTION, 68 XTENSA_OPTION_INTERRUPT, 69 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 70 XTENSA_OPTION_TIMER_INTERRUPT, 71 72 /* Local memory */ 73 XTENSA_OPTION_ICACHE, 74 XTENSA_OPTION_ICACHE_TEST, 75 XTENSA_OPTION_ICACHE_INDEX_LOCK, 76 XTENSA_OPTION_DCACHE, 77 XTENSA_OPTION_DCACHE_TEST, 78 XTENSA_OPTION_DCACHE_INDEX_LOCK, 79 XTENSA_OPTION_IRAM, 80 XTENSA_OPTION_IROM, 81 XTENSA_OPTION_DRAM, 82 XTENSA_OPTION_DROM, 83 XTENSA_OPTION_XLMI, 84 XTENSA_OPTION_HW_ALIGNMENT, 85 XTENSA_OPTION_MEMORY_ECC_PARITY, 86 87 /* Memory protection and translation */ 88 XTENSA_OPTION_REGION_PROTECTION, 89 XTENSA_OPTION_REGION_TRANSLATION, 90 XTENSA_OPTION_MPU, 91 XTENSA_OPTION_MMU, 92 XTENSA_OPTION_CACHEATTR, 93 94 /* Other */ 95 XTENSA_OPTION_WINDOWED_REGISTER, 96 XTENSA_OPTION_PROCESSOR_INTERFACE, 97 XTENSA_OPTION_MISC_SR, 98 XTENSA_OPTION_THREAD_POINTER, 99 XTENSA_OPTION_PROCESSOR_ID, 100 XTENSA_OPTION_DEBUG, 101 XTENSA_OPTION_TRACE_PORT, 102 XTENSA_OPTION_EXTERN_REGS, 103 }; 104 105 enum { 106 EXPSTATE = 230, 107 THREADPTR = 231, 108 FCR = 232, 109 FSR = 233, 110 }; 111 112 enum { 113 LBEG = 0, 114 LEND = 1, 115 LCOUNT = 2, 116 SAR = 3, 117 BR = 4, 118 LITBASE = 5, 119 SCOMPARE1 = 12, 120 ACCLO = 16, 121 ACCHI = 17, 122 MR = 32, 123 PREFCTL = 40, 124 WINDOW_BASE = 72, 125 WINDOW_START = 73, 126 PTEVADDR = 83, 127 MMID = 89, 128 RASID = 90, 129 MPUENB = 90, 130 ITLBCFG = 91, 131 DTLBCFG = 92, 132 MPUCFG = 92, 133 ERACCESS = 95, 134 IBREAKENABLE = 96, 135 MEMCTL = 97, 136 CACHEATTR = 98, 137 CACHEADRDIS = 98, 138 ATOMCTL = 99, 139 DDR = 104, 140 MEPC = 106, 141 MEPS = 107, 142 MESAVE = 108, 143 MESR = 109, 144 MECR = 110, 145 MEVADDR = 111, 146 IBREAKA = 128, 147 DBREAKA = 144, 148 DBREAKC = 160, 149 CONFIGID0 = 176, 150 EPC1 = 177, 151 DEPC = 192, 152 EPS2 = 194, 153 CONFIGID1 = 208, 154 EXCSAVE1 = 209, 155 CPENABLE = 224, 156 INTSET = 226, 157 INTCLEAR = 227, 158 INTENABLE = 228, 159 PS = 230, 160 VECBASE = 231, 161 EXCCAUSE = 232, 162 DEBUGCAUSE = 233, 163 CCOUNT = 234, 164 PRID = 235, 165 ICOUNT = 236, 166 ICOUNTLEVEL = 237, 167 EXCVADDR = 238, 168 CCOMPARE = 240, 169 MISC = 244, 170 }; 171 172 #define PS_INTLEVEL 0xf 173 #define PS_INTLEVEL_SHIFT 0 174 175 #define PS_EXCM 0x10 176 #define PS_UM 0x20 177 178 #define PS_RING 0xc0 179 #define PS_RING_SHIFT 6 180 181 #define PS_OWB 0xf00 182 #define PS_OWB_SHIFT 8 183 #define PS_OWB_LEN 4 184 185 #define PS_CALLINC 0x30000 186 #define PS_CALLINC_SHIFT 16 187 #define PS_CALLINC_LEN 2 188 189 #define PS_WOE 0x40000 190 191 #define DEBUGCAUSE_IC 0x1 192 #define DEBUGCAUSE_IB 0x2 193 #define DEBUGCAUSE_DB 0x4 194 #define DEBUGCAUSE_BI 0x8 195 #define DEBUGCAUSE_BN 0x10 196 #define DEBUGCAUSE_DI 0x20 197 #define DEBUGCAUSE_DBNUM 0xf00 198 #define DEBUGCAUSE_DBNUM_SHIFT 8 199 200 #define DBREAKC_SB 0x80000000 201 #define DBREAKC_LB 0x40000000 202 #define DBREAKC_SB_LB (DBREAKC_SB | DBREAKC_LB) 203 #define DBREAKC_MASK 0x3f 204 205 #define MEMCTL_INIT 0x00800000 206 #define MEMCTL_IUSEWAYS_SHIFT 18 207 #define MEMCTL_IUSEWAYS_LEN 5 208 #define MEMCTL_IUSEWAYS_MASK 0x007c0000 209 #define MEMCTL_DALLOCWAYS_SHIFT 13 210 #define MEMCTL_DALLOCWAYS_LEN 5 211 #define MEMCTL_DALLOCWAYS_MASK 0x0003e000 212 #define MEMCTL_DUSEWAYS_SHIFT 8 213 #define MEMCTL_DUSEWAYS_LEN 5 214 #define MEMCTL_DUSEWAYS_MASK 0x00001f00 215 #define MEMCTL_ISNP 0x4 216 #define MEMCTL_DSNP 0x2 217 #define MEMCTL_IL0EN 0x1 218 219 #define MAX_INSN_LENGTH 64 220 #define MAX_INSNBUF_LENGTH \ 221 ((MAX_INSN_LENGTH + sizeof(xtensa_insnbuf_word) - 1) / \ 222 sizeof(xtensa_insnbuf_word)) 223 #define MAX_INSN_SLOTS 32 224 #define MAX_OPCODE_ARGS 16 225 #define MAX_NAREG 64 226 #define MAX_NINTERRUPT 32 227 #define MAX_NLEVEL 6 228 #define MAX_NNMI 1 229 #define MAX_NCCOMPARE 3 230 #define MAX_TLB_WAY_SIZE 8 231 #define MAX_NDBREAK 2 232 #define MAX_NIBREAK 2 233 #define MAX_NMEMORY 4 234 #define MAX_MPU_FOREGROUND_SEGMENTS 32 235 236 #define REGION_PAGE_MASK 0xe0000000 237 238 #define PAGE_CACHE_MASK 0x700 239 #define PAGE_CACHE_SHIFT 8 240 #define PAGE_CACHE_INVALID 0x000 241 #define PAGE_CACHE_BYPASS 0x100 242 #define PAGE_CACHE_WT 0x200 243 #define PAGE_CACHE_WB 0x400 244 #define PAGE_CACHE_ISOLATE 0x600 245 246 enum { 247 /* Static vectors */ 248 EXC_RESET0, 249 EXC_RESET1, 250 EXC_MEMORY_ERROR, 251 252 /* Dynamic vectors */ 253 EXC_WINDOW_OVERFLOW4, 254 EXC_WINDOW_UNDERFLOW4, 255 EXC_WINDOW_OVERFLOW8, 256 EXC_WINDOW_UNDERFLOW8, 257 EXC_WINDOW_OVERFLOW12, 258 EXC_WINDOW_UNDERFLOW12, 259 EXC_IRQ, 260 EXC_KERNEL, 261 EXC_USER, 262 EXC_DOUBLE, 263 EXC_DEBUG, 264 EXC_MAX 265 }; 266 267 enum { 268 ILLEGAL_INSTRUCTION_CAUSE = 0, 269 SYSCALL_CAUSE, 270 INSTRUCTION_FETCH_ERROR_CAUSE, 271 LOAD_STORE_ERROR_CAUSE, 272 LEVEL1_INTERRUPT_CAUSE, 273 ALLOCA_CAUSE, 274 INTEGER_DIVIDE_BY_ZERO_CAUSE, 275 PC_VALUE_ERROR_CAUSE, 276 PRIVILEGED_CAUSE, 277 LOAD_STORE_ALIGNMENT_CAUSE, 278 EXTERNAL_REG_PRIVILEGE_CAUSE, 279 EXCLUSIVE_ERROR_CAUSE, 280 INSTR_PIF_DATA_ERROR_CAUSE, 281 LOAD_STORE_PIF_DATA_ERROR_CAUSE, 282 INSTR_PIF_ADDR_ERROR_CAUSE, 283 LOAD_STORE_PIF_ADDR_ERROR_CAUSE, 284 INST_TLB_MISS_CAUSE, 285 INST_TLB_MULTI_HIT_CAUSE, 286 INST_FETCH_PRIVILEGE_CAUSE, 287 INST_FETCH_PROHIBITED_CAUSE = 20, 288 LOAD_STORE_TLB_MISS_CAUSE = 24, 289 LOAD_STORE_TLB_MULTI_HIT_CAUSE, 290 LOAD_STORE_PRIVILEGE_CAUSE, 291 LOAD_PROHIBITED_CAUSE = 28, 292 STORE_PROHIBITED_CAUSE, 293 294 COPROCESSOR0_DISABLED = 32, 295 }; 296 297 typedef enum { 298 INTTYPE_LEVEL, 299 INTTYPE_EDGE, 300 INTTYPE_NMI, 301 INTTYPE_SOFTWARE, 302 INTTYPE_TIMER, 303 INTTYPE_DEBUG, 304 INTTYPE_WRITE_ERR, 305 INTTYPE_PROFILING, 306 INTTYPE_IDMA_DONE, 307 INTTYPE_IDMA_ERR, 308 INTTYPE_GS_ERR, 309 INTTYPE_MAX 310 } interrupt_type; 311 312 typedef struct CPUArchState CPUXtensaState; 313 314 typedef struct xtensa_tlb_entry { 315 uint32_t vaddr; 316 uint32_t paddr; 317 uint8_t asid; 318 uint8_t attr; 319 bool variable; 320 } xtensa_tlb_entry; 321 322 typedef struct xtensa_tlb { 323 unsigned nways; 324 const unsigned way_size[10]; 325 bool varway56; 326 unsigned nrefillentries; 327 } xtensa_tlb; 328 329 typedef struct xtensa_mpu_entry { 330 uint32_t vaddr; 331 uint32_t attr; 332 } xtensa_mpu_entry; 333 334 typedef struct XtensaGdbReg { 335 int targno; 336 unsigned flags; 337 int type; 338 int group; 339 unsigned size; 340 } XtensaGdbReg; 341 342 typedef struct XtensaGdbRegmap { 343 int num_regs; 344 int num_core_regs; 345 /* PC + a + ar + sr + ur */ 346 XtensaGdbReg reg[1 + 16 + 64 + 256 + 256]; 347 } XtensaGdbRegmap; 348 349 typedef struct XtensaCcompareTimer { 350 CPUXtensaState *env; 351 QEMUTimer *timer; 352 } XtensaCcompareTimer; 353 354 typedef struct XtensaMemory { 355 unsigned num; 356 struct XtensaMemoryRegion { 357 uint32_t addr; 358 uint32_t size; 359 } location[MAX_NMEMORY]; 360 } XtensaMemory; 361 362 typedef struct opcode_arg { 363 uint32_t imm; 364 uint32_t raw_imm; 365 void *in; 366 void *out; 367 uint32_t num_bits; 368 } OpcodeArg; 369 370 typedef struct DisasContext DisasContext; 371 typedef void (*XtensaOpcodeOp)(DisasContext *dc, const OpcodeArg arg[], 372 const uint32_t par[]); 373 typedef uint32_t (*XtensaOpcodeUintTest)(DisasContext *dc, 374 const OpcodeArg arg[], 375 const uint32_t par[]); 376 377 enum { 378 XTENSA_OP_ILL = 0x1, 379 XTENSA_OP_PRIVILEGED = 0x2, 380 XTENSA_OP_SYSCALL = 0x4, 381 XTENSA_OP_DEBUG_BREAK = 0x8, 382 383 XTENSA_OP_OVERFLOW = 0x10, 384 XTENSA_OP_UNDERFLOW = 0x20, 385 XTENSA_OP_ALLOCA = 0x40, 386 XTENSA_OP_COPROCESSOR = 0x80, 387 388 XTENSA_OP_DIVIDE_BY_ZERO = 0x100, 389 390 /* Postprocessing flags */ 391 XTENSA_OP_CHECK_INTERRUPTS = 0x200, 392 XTENSA_OP_EXIT_TB_M1 = 0x400, 393 XTENSA_OP_EXIT_TB_0 = 0x800, 394 XTENSA_OP_SYNC_REGISTER_WINDOW = 0x1000, 395 396 XTENSA_OP_POSTPROCESS = 397 XTENSA_OP_CHECK_INTERRUPTS | 398 XTENSA_OP_EXIT_TB_M1 | 399 XTENSA_OP_EXIT_TB_0 | 400 XTENSA_OP_SYNC_REGISTER_WINDOW, 401 402 XTENSA_OP_NAME_ARRAY = 0x8000, 403 404 XTENSA_OP_CONTROL_FLOW = 0x10000, 405 XTENSA_OP_STORE = 0x20000, 406 XTENSA_OP_LOAD = 0x40000, 407 XTENSA_OP_LOAD_STORE = 408 XTENSA_OP_LOAD | XTENSA_OP_STORE, 409 }; 410 411 typedef struct XtensaOpcodeOps { 412 const void *name; 413 XtensaOpcodeOp translate; 414 XtensaOpcodeUintTest test_exceptions; 415 XtensaOpcodeUintTest test_overflow; 416 const uint32_t *par; 417 uint32_t op_flags; 418 uint32_t coprocessor; 419 } XtensaOpcodeOps; 420 421 typedef struct XtensaOpcodeTranslators { 422 unsigned num_opcodes; 423 const XtensaOpcodeOps *opcode; 424 } XtensaOpcodeTranslators; 425 426 extern const XtensaOpcodeTranslators xtensa_core_opcodes; 427 extern const XtensaOpcodeTranslators xtensa_fpu2000_opcodes; 428 extern const XtensaOpcodeTranslators xtensa_fpu_opcodes; 429 430 typedef struct XtensaConfig { 431 const char *name; 432 uint64_t options; 433 XtensaGdbRegmap gdb_regmap; 434 unsigned nareg; 435 int excm_level; 436 int ndepc; 437 unsigned inst_fetch_width; 438 unsigned max_insn_size; 439 uint32_t vecbase; 440 uint32_t exception_vector[EXC_MAX]; 441 unsigned ninterrupt; 442 unsigned nlevel; 443 unsigned nmi_level; 444 uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1]; 445 uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1]; 446 uint32_t inttype_mask[INTTYPE_MAX]; 447 struct { 448 uint32_t level; 449 interrupt_type inttype; 450 } interrupt[MAX_NINTERRUPT]; 451 unsigned nccompare; 452 uint32_t timerint[MAX_NCCOMPARE]; 453 unsigned nextint; 454 unsigned extint[MAX_NINTERRUPT]; 455 456 unsigned debug_level; 457 unsigned nibreak; 458 unsigned ndbreak; 459 460 unsigned icache_ways; 461 unsigned dcache_ways; 462 unsigned dcache_line_bytes; 463 uint32_t memctl_mask; 464 465 XtensaMemory instrom; 466 XtensaMemory instram; 467 XtensaMemory datarom; 468 XtensaMemory dataram; 469 XtensaMemory sysrom; 470 XtensaMemory sysram; 471 472 unsigned hw_version; 473 uint32_t configid[2]; 474 475 void *isa_internal; 476 xtensa_isa isa; 477 XtensaOpcodeOps **opcode_ops; 478 const XtensaOpcodeTranslators **opcode_translators; 479 xtensa_regfile a_regfile; 480 void ***regfile; 481 482 uint32_t clock_freq_khz; 483 484 xtensa_tlb itlb; 485 xtensa_tlb dtlb; 486 487 uint32_t mpu_align; 488 unsigned n_mpu_fg_segments; 489 unsigned n_mpu_bg_segments; 490 const xtensa_mpu_entry *mpu_bg; 491 492 bool use_first_nan; 493 } XtensaConfig; 494 495 typedef struct XtensaConfigList { 496 const XtensaConfig *config; 497 struct XtensaConfigList *next; 498 } XtensaConfigList; 499 500 #if HOST_BIG_ENDIAN 501 enum { 502 FP_F32_HIGH, 503 FP_F32_LOW, 504 }; 505 #else 506 enum { 507 FP_F32_LOW, 508 FP_F32_HIGH, 509 }; 510 #endif 511 512 struct CPUArchState { 513 const XtensaConfig *config; 514 uint32_t regs[16]; 515 uint32_t pc; 516 uint32_t sregs[256]; 517 uint32_t uregs[256]; 518 uint32_t phys_regs[MAX_NAREG]; 519 union { 520 float32 f32[2]; 521 float64 f64; 522 } fregs[16]; 523 float_status fp_status; 524 uint32_t windowbase_next; 525 uint32_t exclusive_addr; 526 uint32_t exclusive_val; 527 528 #ifndef CONFIG_USER_ONLY 529 xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE]; 530 xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE]; 531 xtensa_mpu_entry mpu_fg[MAX_MPU_FOREGROUND_SEGMENTS]; 532 unsigned autorefill_idx; 533 bool runstall; 534 AddressSpace *address_space_er; 535 MemoryRegion *system_er; 536 int pending_irq_level; /* level of last raised IRQ */ 537 qemu_irq *irq_inputs; 538 qemu_irq ext_irq_inputs[MAX_NINTERRUPT]; 539 qemu_irq runstall_irq; 540 XtensaCcompareTimer ccompare[MAX_NCCOMPARE]; 541 uint64_t time_base; 542 uint64_t ccount_time; 543 uint32_t ccount_base; 544 #endif 545 546 int yield_needed; 547 unsigned static_vectors; 548 549 /* Watchpoints for DBREAK registers */ 550 struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK]; 551 /* Breakpoints for IBREAK registers */ 552 struct CPUBreakpoint *cpu_breakpoint[MAX_NIBREAK]; 553 }; 554 555 /** 556 * XtensaCPU: 557 * @env: #CPUXtensaState 558 * 559 * An Xtensa CPU. 560 */ 561 struct ArchCPU { 562 CPUState parent_obj; 563 564 CPUXtensaState env; 565 Clock *clock; 566 }; 567 568 /** 569 * XtensaCPUClass: 570 * @parent_realize: The parent class' realize handler. 571 * @parent_phases: The parent class' reset phase handlers. 572 * @config: The CPU core configuration. 573 * 574 * An Xtensa CPU model. 575 */ 576 struct XtensaCPUClass { 577 CPUClass parent_class; 578 579 DeviceRealize parent_realize; 580 ResettablePhases parent_phases; 581 582 const XtensaConfig *config; 583 }; 584 585 #ifndef CONFIG_USER_ONLY 586 bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 587 MMUAccessType access_type, int mmu_idx, 588 bool probe, uintptr_t retaddr); 589 void xtensa_cpu_do_interrupt(CPUState *cpu); 590 bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request); 591 void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, 592 unsigned size, MMUAccessType access_type, 593 int mmu_idx, MemTxAttrs attrs, 594 MemTxResult response, uintptr_t retaddr); 595 hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 596 bool xtensa_debug_check_breakpoint(CPUState *cs); 597 #endif 598 void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, int flags); 599 void xtensa_count_regs(const XtensaConfig *config, 600 unsigned *n_regs, unsigned *n_core_regs); 601 int xtensa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 602 int xtensa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 603 G_NORETURN void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, 604 MMUAccessType access_type, int mmu_idx, 605 uintptr_t retaddr); 606 607 #define CPU_RESOLVING_TYPE TYPE_XTENSA_CPU 608 609 #if TARGET_BIG_ENDIAN 610 #define XTENSA_DEFAULT_CPU_MODEL "fsf" 611 #define XTENSA_DEFAULT_CPU_NOMMU_MODEL "fsf" 612 #else 613 #define XTENSA_DEFAULT_CPU_MODEL "dc232b" 614 #define XTENSA_DEFAULT_CPU_NOMMU_MODEL "de212" 615 #endif 616 #define XTENSA_DEFAULT_CPU_TYPE \ 617 XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_MODEL) 618 #define XTENSA_DEFAULT_CPU_NOMMU_TYPE \ 619 XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_NOMMU_MODEL) 620 621 void xtensa_collect_sr_names(const XtensaConfig *config); 622 void xtensa_translate_init(void); 623 void **xtensa_get_regfile_by_name(const char *name, int entries, int bits); 624 void xtensa_breakpoint_handler(CPUState *cs); 625 void xtensa_register_core(XtensaConfigList *node); 626 void xtensa_sim_open_console(Chardev *chr); 627 void check_interrupts(CPUXtensaState *s); 628 void xtensa_irq_init(CPUXtensaState *env); 629 qemu_irq *xtensa_get_extints(CPUXtensaState *env); 630 qemu_irq xtensa_get_runstall(CPUXtensaState *env); 631 void xtensa_sync_window_from_phys(CPUXtensaState *env); 632 void xtensa_sync_phys_from_window(CPUXtensaState *env); 633 void xtensa_rotate_window(CPUXtensaState *env, uint32_t delta); 634 void xtensa_restore_owb(CPUXtensaState *env); 635 void debug_exception_env(CPUXtensaState *new_env, uint32_t cause); 636 637 static inline void xtensa_select_static_vectors(CPUXtensaState *env, 638 unsigned n) 639 { 640 assert(n < 2); 641 env->static_vectors = n; 642 } 643 void xtensa_runstall(CPUXtensaState *env, bool runstall); 644 645 #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt)) 646 #define XTENSA_OPTION_ALL (~(uint64_t)0) 647 648 static inline bool xtensa_option_bits_enabled(const XtensaConfig *config, 649 uint64_t opt) 650 { 651 return (config->options & opt) != 0; 652 } 653 654 static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt) 655 { 656 return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt)); 657 } 658 659 static inline int xtensa_get_cintlevel(const CPUXtensaState *env) 660 { 661 int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT; 662 if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) { 663 level = env->config->excm_level; 664 } 665 return level; 666 } 667 668 static inline int xtensa_get_ring(const CPUXtensaState *env) 669 { 670 if (xtensa_option_bits_enabled(env->config, 671 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU) | 672 XTENSA_OPTION_BIT(XTENSA_OPTION_MPU))) { 673 return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT; 674 } else { 675 return 0; 676 } 677 } 678 679 static inline int xtensa_get_cring(const CPUXtensaState *env) 680 { 681 if (xtensa_option_bits_enabled(env->config, 682 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU) | 683 XTENSA_OPTION_BIT(XTENSA_OPTION_MPU)) && 684 (env->sregs[PS] & PS_EXCM) == 0) { 685 return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT; 686 } else { 687 return 0; 688 } 689 } 690 691 #ifndef CONFIG_USER_ONLY 692 int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb, 693 uint32_t vaddr, int is_write, int mmu_idx, 694 uint32_t *paddr, uint32_t *page_size, unsigned *access); 695 void reset_mmu(CPUXtensaState *env); 696 void dump_mmu(CPUXtensaState *env); 697 698 static inline MemoryRegion *xtensa_get_er_region(CPUXtensaState *env) 699 { 700 return env->system_er; 701 } 702 #else 703 void xtensa_set_abi_call0(void); 704 bool xtensa_abi_call0(void); 705 #endif 706 707 static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env) 708 { 709 return env->sregs[WINDOW_START] | 710 (env->sregs[WINDOW_START] << env->config->nareg / 4); 711 } 712 713 /* MMU modes definitions */ 714 #define MMU_USER_IDX 3 715 716 static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch) 717 { 718 return xtensa_get_cring(env); 719 } 720 721 #define XTENSA_TBFLAG_RING_MASK 0x3 722 #define XTENSA_TBFLAG_EXCM 0x4 723 #define XTENSA_TBFLAG_LITBASE 0x8 724 #define XTENSA_TBFLAG_DEBUG 0x10 725 #define XTENSA_TBFLAG_ICOUNT 0x20 726 #define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0 727 #define XTENSA_TBFLAG_CPENABLE_SHIFT 6 728 #define XTENSA_TBFLAG_WINDOW_MASK 0x18000 729 #define XTENSA_TBFLAG_WINDOW_SHIFT 15 730 #define XTENSA_TBFLAG_YIELD 0x20000 731 #define XTENSA_TBFLAG_CWOE 0x40000 732 #define XTENSA_TBFLAG_CALLINC_MASK 0x180000 733 #define XTENSA_TBFLAG_CALLINC_SHIFT 19 734 735 #define XTENSA_CSBASE_LEND_MASK 0x0000ffff 736 #define XTENSA_CSBASE_LEND_SHIFT 0 737 #define XTENSA_CSBASE_LBEG_OFF_MASK 0x00ff0000 738 #define XTENSA_CSBASE_LBEG_OFF_SHIFT 16 739 740 #include "exec/cpu-all.h" 741 742 static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr *pc, 743 uint64_t *cs_base, uint32_t *flags) 744 { 745 *pc = env->pc; 746 *cs_base = 0; 747 *flags = 0; 748 *flags |= xtensa_get_ring(env); 749 if (env->sregs[PS] & PS_EXCM) { 750 *flags |= XTENSA_TBFLAG_EXCM; 751 } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) { 752 target_ulong lend_dist = 753 env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS)); 754 755 /* 756 * 0 in the csbase_lend field means that there may not be a loopback 757 * for any instruction that starts inside this page. Any other value 758 * means that an instruction that ends at this offset from the page 759 * start may loop back and will need loopback code to be generated. 760 * 761 * lend_dist is 0 when LEND points to the start of the page, but 762 * no instruction that starts inside this page may end at offset 0, 763 * so it's still correct. 764 * 765 * When an instruction ends at a page boundary it may only start in 766 * the previous page. lend_dist will be encoded as TARGET_PAGE_SIZE 767 * for the TB that contains this instruction. 768 */ 769 if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_size) { 770 target_ulong lbeg_off = env->sregs[LEND] - env->sregs[LBEG]; 771 772 *cs_base = lend_dist; 773 if (lbeg_off < 256) { 774 *cs_base |= lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT; 775 } 776 } 777 } 778 if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) && 779 (env->sregs[LITBASE] & 1)) { 780 *flags |= XTENSA_TBFLAG_LITBASE; 781 } 782 if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) { 783 if (xtensa_get_cintlevel(env) < env->config->debug_level) { 784 *flags |= XTENSA_TBFLAG_DEBUG; 785 } 786 if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) { 787 *flags |= XTENSA_TBFLAG_ICOUNT; 788 } 789 } 790 if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) { 791 *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT; 792 } 793 if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) && 794 (env->sregs[PS] & (PS_WOE | PS_EXCM)) == PS_WOE) { 795 uint32_t windowstart = xtensa_replicate_windowstart(env) >> 796 (env->sregs[WINDOW_BASE] + 1); 797 uint32_t w = ctz32(windowstart | 0x8); 798 799 *flags |= (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE; 800 *flags |= extract32(env->sregs[PS], PS_CALLINC_SHIFT, 801 PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT; 802 } else { 803 *flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT; 804 } 805 if (env->yield_needed) { 806 *flags |= XTENSA_TBFLAG_YIELD; 807 } 808 } 809 810 XtensaCPU *xtensa_cpu_create_with_clock(const char *cpu_type, 811 Clock *cpu_refclk); 812 813 #endif 814