xref: /openbmc/qemu/target/xtensa/cpu.h (revision dc5bd18f) 
1 /*
2  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are met:
7  *     * Redistributions of source code must retain the above copyright
8  *       notice, this list of conditions and the following disclaimer.
9  *     * Redistributions in binary form must reproduce the above copyright
10  *       notice, this list of conditions and the following disclaimer in the
11  *       documentation and/or other materials provided with the distribution.
12  *     * Neither the name of the Open Source and Linux Lab nor the
13  *       names of its contributors may be used to endorse or promote products
14  *       derived from this software without specific prior written permission.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26  */
27 
28 #ifndef XTENSA_CPU_H
29 #define XTENSA_CPU_H
30 
31 #define ALIGNED_ONLY
32 #define TARGET_LONG_BITS 32
33 
34 #define CPUArchState struct CPUXtensaState
35 
36 #include "qemu-common.h"
37 #include "cpu-qom.h"
38 #include "exec/cpu-defs.h"
39 #include "xtensa-isa.h"
40 
41 #define NB_MMU_MODES 4
42 
43 #define TARGET_PHYS_ADDR_SPACE_BITS 32
44 #define TARGET_VIRT_ADDR_SPACE_BITS 32
45 #define TARGET_PAGE_BITS 12
46 
47 enum {
48     /* Additional instructions */
49     XTENSA_OPTION_CODE_DENSITY,
50     XTENSA_OPTION_LOOP,
51     XTENSA_OPTION_EXTENDED_L32R,
52     XTENSA_OPTION_16_BIT_IMUL,
53     XTENSA_OPTION_32_BIT_IMUL,
54     XTENSA_OPTION_32_BIT_IMUL_HIGH,
55     XTENSA_OPTION_32_BIT_IDIV,
56     XTENSA_OPTION_MAC16,
57     XTENSA_OPTION_MISC_OP_NSA,
58     XTENSA_OPTION_MISC_OP_MINMAX,
59     XTENSA_OPTION_MISC_OP_SEXT,
60     XTENSA_OPTION_MISC_OP_CLAMPS,
61     XTENSA_OPTION_COPROCESSOR,
62     XTENSA_OPTION_BOOLEAN,
63     XTENSA_OPTION_FP_COPROCESSOR,
64     XTENSA_OPTION_MP_SYNCHRO,
65     XTENSA_OPTION_CONDITIONAL_STORE,
66     XTENSA_OPTION_ATOMCTL,
67     XTENSA_OPTION_DEPBITS,
68 
69     /* Interrupts and exceptions */
70     XTENSA_OPTION_EXCEPTION,
71     XTENSA_OPTION_RELOCATABLE_VECTOR,
72     XTENSA_OPTION_UNALIGNED_EXCEPTION,
73     XTENSA_OPTION_INTERRUPT,
74     XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
75     XTENSA_OPTION_TIMER_INTERRUPT,
76 
77     /* Local memory */
78     XTENSA_OPTION_ICACHE,
79     XTENSA_OPTION_ICACHE_TEST,
80     XTENSA_OPTION_ICACHE_INDEX_LOCK,
81     XTENSA_OPTION_DCACHE,
82     XTENSA_OPTION_DCACHE_TEST,
83     XTENSA_OPTION_DCACHE_INDEX_LOCK,
84     XTENSA_OPTION_IRAM,
85     XTENSA_OPTION_IROM,
86     XTENSA_OPTION_DRAM,
87     XTENSA_OPTION_DROM,
88     XTENSA_OPTION_XLMI,
89     XTENSA_OPTION_HW_ALIGNMENT,
90     XTENSA_OPTION_MEMORY_ECC_PARITY,
91 
92     /* Memory protection and translation */
93     XTENSA_OPTION_REGION_PROTECTION,
94     XTENSA_OPTION_REGION_TRANSLATION,
95     XTENSA_OPTION_MMU,
96     XTENSA_OPTION_CACHEATTR,
97 
98     /* Other */
99     XTENSA_OPTION_WINDOWED_REGISTER,
100     XTENSA_OPTION_PROCESSOR_INTERFACE,
101     XTENSA_OPTION_MISC_SR,
102     XTENSA_OPTION_THREAD_POINTER,
103     XTENSA_OPTION_PROCESSOR_ID,
104     XTENSA_OPTION_DEBUG,
105     XTENSA_OPTION_TRACE_PORT,
106     XTENSA_OPTION_EXTERN_REGS,
107 };
108 
109 enum {
110     EXPSTATE = 230,
111     THREADPTR = 231,
112     FCR = 232,
113     FSR = 233,
114 };
115 
116 enum {
117     LBEG = 0,
118     LEND = 1,
119     LCOUNT = 2,
120     SAR = 3,
121     BR = 4,
122     LITBASE = 5,
123     SCOMPARE1 = 12,
124     ACCLO = 16,
125     ACCHI = 17,
126     MR = 32,
127     WINDOW_BASE = 72,
128     WINDOW_START = 73,
129     PTEVADDR = 83,
130     MMID = 89,
131     RASID = 90,
132     ITLBCFG = 91,
133     DTLBCFG = 92,
134     IBREAKENABLE = 96,
135     MEMCTL = 97,
136     CACHEATTR = 98,
137     ATOMCTL = 99,
138     DDR = 104,
139     IBREAKA = 128,
140     DBREAKA = 144,
141     DBREAKC = 160,
142     CONFIGID0 = 176,
143     EPC1 = 177,
144     DEPC = 192,
145     EPS2 = 194,
146     CONFIGID1 = 208,
147     EXCSAVE1 = 209,
148     CPENABLE = 224,
149     INTSET = 226,
150     INTCLEAR = 227,
151     INTENABLE = 228,
152     PS = 230,
153     VECBASE = 231,
154     EXCCAUSE = 232,
155     DEBUGCAUSE = 233,
156     CCOUNT = 234,
157     PRID = 235,
158     ICOUNT = 236,
159     ICOUNTLEVEL = 237,
160     EXCVADDR = 238,
161     CCOMPARE = 240,
162     MISC = 244,
163 };
164 
165 #define PS_INTLEVEL 0xf
166 #define PS_INTLEVEL_SHIFT 0
167 
168 #define PS_EXCM 0x10
169 #define PS_UM 0x20
170 
171 #define PS_RING 0xc0
172 #define PS_RING_SHIFT 6
173 
174 #define PS_OWB 0xf00
175 #define PS_OWB_SHIFT 8
176 
177 #define PS_CALLINC 0x30000
178 #define PS_CALLINC_SHIFT 16
179 #define PS_CALLINC_LEN 2
180 
181 #define PS_WOE 0x40000
182 
183 #define DEBUGCAUSE_IC 0x1
184 #define DEBUGCAUSE_IB 0x2
185 #define DEBUGCAUSE_DB 0x4
186 #define DEBUGCAUSE_BI 0x8
187 #define DEBUGCAUSE_BN 0x10
188 #define DEBUGCAUSE_DI 0x20
189 #define DEBUGCAUSE_DBNUM 0xf00
190 #define DEBUGCAUSE_DBNUM_SHIFT 8
191 
192 #define DBREAKC_SB 0x80000000
193 #define DBREAKC_LB 0x40000000
194 #define DBREAKC_SB_LB (DBREAKC_SB | DBREAKC_LB)
195 #define DBREAKC_MASK 0x3f
196 
197 #define MEMCTL_INIT 0x00800000
198 #define MEMCTL_IUSEWAYS_SHIFT 18
199 #define MEMCTL_IUSEWAYS_LEN 5
200 #define MEMCTL_IUSEWAYS_MASK 0x007c0000
201 #define MEMCTL_DALLOCWAYS_SHIFT 13
202 #define MEMCTL_DALLOCWAYS_LEN 5
203 #define MEMCTL_DALLOCWAYS_MASK 0x0003e000
204 #define MEMCTL_DUSEWAYS_SHIFT 8
205 #define MEMCTL_DUSEWAYS_LEN 5
206 #define MEMCTL_DUSEWAYS_MASK 0x00001f00
207 #define MEMCTL_ISNP 0x4
208 #define MEMCTL_DSNP 0x2
209 #define MEMCTL_IL0EN 0x1
210 
211 #define MAX_INSN_LENGTH 64
212 #define MAX_OPCODE_ARGS 16
213 #define MAX_NAREG 64
214 #define MAX_NINTERRUPT 32
215 #define MAX_NLEVEL 6
216 #define MAX_NNMI 1
217 #define MAX_NCCOMPARE 3
218 #define MAX_TLB_WAY_SIZE 8
219 #define MAX_NDBREAK 2
220 #define MAX_NMEMORY 4
221 
222 #define REGION_PAGE_MASK 0xe0000000
223 
224 #define PAGE_CACHE_MASK    0x700
225 #define PAGE_CACHE_SHIFT   8
226 #define PAGE_CACHE_INVALID 0x000
227 #define PAGE_CACHE_BYPASS  0x100
228 #define PAGE_CACHE_WT      0x200
229 #define PAGE_CACHE_WB      0x400
230 #define PAGE_CACHE_ISOLATE 0x600
231 
232 enum {
233     /* Static vectors */
234     EXC_RESET0,
235     EXC_RESET1,
236     EXC_MEMORY_ERROR,
237 
238     /* Dynamic vectors */
239     EXC_WINDOW_OVERFLOW4,
240     EXC_WINDOW_UNDERFLOW4,
241     EXC_WINDOW_OVERFLOW8,
242     EXC_WINDOW_UNDERFLOW8,
243     EXC_WINDOW_OVERFLOW12,
244     EXC_WINDOW_UNDERFLOW12,
245     EXC_IRQ,
246     EXC_KERNEL,
247     EXC_USER,
248     EXC_DOUBLE,
249     EXC_DEBUG,
250     EXC_MAX
251 };
252 
253 enum {
254     ILLEGAL_INSTRUCTION_CAUSE = 0,
255     SYSCALL_CAUSE,
256     INSTRUCTION_FETCH_ERROR_CAUSE,
257     LOAD_STORE_ERROR_CAUSE,
258     LEVEL1_INTERRUPT_CAUSE,
259     ALLOCA_CAUSE,
260     INTEGER_DIVIDE_BY_ZERO_CAUSE,
261     PRIVILEGED_CAUSE = 8,
262     LOAD_STORE_ALIGNMENT_CAUSE,
263 
264     INSTR_PIF_DATA_ERROR_CAUSE = 12,
265     LOAD_STORE_PIF_DATA_ERROR_CAUSE,
266     INSTR_PIF_ADDR_ERROR_CAUSE,
267     LOAD_STORE_PIF_ADDR_ERROR_CAUSE,
268 
269     INST_TLB_MISS_CAUSE,
270     INST_TLB_MULTI_HIT_CAUSE,
271     INST_FETCH_PRIVILEGE_CAUSE,
272     INST_FETCH_PROHIBITED_CAUSE = 20,
273     LOAD_STORE_TLB_MISS_CAUSE = 24,
274     LOAD_STORE_TLB_MULTI_HIT_CAUSE,
275     LOAD_STORE_PRIVILEGE_CAUSE,
276     LOAD_PROHIBITED_CAUSE = 28,
277     STORE_PROHIBITED_CAUSE,
278 
279     COPROCESSOR0_DISABLED = 32,
280 };
281 
282 typedef enum {
283     INTTYPE_LEVEL,
284     INTTYPE_EDGE,
285     INTTYPE_NMI,
286     INTTYPE_SOFTWARE,
287     INTTYPE_TIMER,
288     INTTYPE_DEBUG,
289     INTTYPE_WRITE_ERR,
290     INTTYPE_PROFILING,
291     INTTYPE_MAX
292 } interrupt_type;
293 
294 struct CPUXtensaState;
295 
296 typedef struct xtensa_tlb_entry {
297     uint32_t vaddr;
298     uint32_t paddr;
299     uint8_t asid;
300     uint8_t attr;
301     bool variable;
302 } xtensa_tlb_entry;
303 
304 typedef struct xtensa_tlb {
305     unsigned nways;
306     const unsigned way_size[10];
307     bool varway56;
308     unsigned nrefillentries;
309 } xtensa_tlb;
310 
311 typedef struct XtensaGdbReg {
312     int targno;
313     int type;
314     int group;
315     unsigned size;
316 } XtensaGdbReg;
317 
318 typedef struct XtensaGdbRegmap {
319     int num_regs;
320     int num_core_regs;
321     /* PC + a + ar + sr + ur */
322     XtensaGdbReg reg[1 + 16 + 64 + 256 + 256];
323 } XtensaGdbRegmap;
324 
325 typedef struct XtensaCcompareTimer {
326     struct CPUXtensaState *env;
327     QEMUTimer *timer;
328 } XtensaCcompareTimer;
329 
330 typedef struct XtensaMemory {
331     unsigned num;
332     struct XtensaMemoryRegion {
333         uint32_t addr;
334         uint32_t size;
335     } location[MAX_NMEMORY];
336 } XtensaMemory;
337 
338 typedef struct DisasContext DisasContext;
339 typedef void (*XtensaOpcodeOp)(DisasContext *dc, const uint32_t arg[],
340                                const uint32_t par[]);
341 
342 typedef struct XtensaOpcodeOps {
343     const char *name;
344     XtensaOpcodeOp translate;
345     const uint32_t *par;
346 } XtensaOpcodeOps;
347 
348 typedef struct XtensaOpcodeTranslators {
349     unsigned num_opcodes;
350     const XtensaOpcodeOps *opcode;
351 } XtensaOpcodeTranslators;
352 
353 extern const XtensaOpcodeTranslators xtensa_core_opcodes;
354 extern const XtensaOpcodeTranslators xtensa_fpu2000_opcodes;
355 
356 struct XtensaConfig {
357     const char *name;
358     uint64_t options;
359     XtensaGdbRegmap gdb_regmap;
360     unsigned nareg;
361     int excm_level;
362     int ndepc;
363     uint32_t vecbase;
364     uint32_t exception_vector[EXC_MAX];
365     unsigned ninterrupt;
366     unsigned nlevel;
367     uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1];
368     uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1];
369     uint32_t inttype_mask[INTTYPE_MAX];
370     struct {
371         uint32_t level;
372         interrupt_type inttype;
373     } interrupt[MAX_NINTERRUPT];
374     unsigned nccompare;
375     uint32_t timerint[MAX_NCCOMPARE];
376     unsigned nextint;
377     unsigned extint[MAX_NINTERRUPT];
378 
379     unsigned debug_level;
380     unsigned nibreak;
381     unsigned ndbreak;
382 
383     unsigned icache_ways;
384     unsigned dcache_ways;
385     uint32_t memctl_mask;
386 
387     XtensaMemory instrom;
388     XtensaMemory instram;
389     XtensaMemory datarom;
390     XtensaMemory dataram;
391     XtensaMemory sysrom;
392     XtensaMemory sysram;
393 
394     uint32_t configid[2];
395 
396     void *isa_internal;
397     xtensa_isa isa;
398     XtensaOpcodeOps **opcode_ops;
399     const XtensaOpcodeTranslators **opcode_translators;
400 
401     uint32_t clock_freq_khz;
402 
403     xtensa_tlb itlb;
404     xtensa_tlb dtlb;
405 };
406 
407 typedef struct XtensaConfigList {
408     const XtensaConfig *config;
409     struct XtensaConfigList *next;
410 } XtensaConfigList;
411 
412 #ifdef HOST_WORDS_BIGENDIAN
413 enum {
414     FP_F32_HIGH,
415     FP_F32_LOW,
416 };
417 #else
418 enum {
419     FP_F32_LOW,
420     FP_F32_HIGH,
421 };
422 #endif
423 
424 typedef struct CPUXtensaState {
425     const XtensaConfig *config;
426     uint32_t regs[16];
427     uint32_t pc;
428     uint32_t sregs[256];
429     uint32_t uregs[256];
430     uint32_t phys_regs[MAX_NAREG];
431     union {
432         float32 f32[2];
433         float64 f64;
434     } fregs[16];
435     float_status fp_status;
436 
437     xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE];
438     xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE];
439     unsigned autorefill_idx;
440     bool runstall;
441     AddressSpace *address_space_er;
442     MemoryRegion *system_er;
443     int pending_irq_level; /* level of last raised IRQ */
444     void **irq_inputs;
445     XtensaCcompareTimer ccompare[MAX_NCCOMPARE];
446     uint64_t time_base;
447     uint64_t ccount_time;
448     uint32_t ccount_base;
449 
450     int exception_taken;
451     int yield_needed;
452     unsigned static_vectors;
453 
454     /* Watchpoints for DBREAK registers */
455     struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];
456 
457     CPU_COMMON
458 } CPUXtensaState;
459 
460 /**
461  * XtensaCPU:
462  * @env: #CPUXtensaState
463  *
464  * An Xtensa CPU.
465  */
466 struct XtensaCPU {
467     /*< private >*/
468     CPUState parent_obj;
469     /*< public >*/
470 
471     CPUXtensaState env;
472 };
473 
474 static inline XtensaCPU *xtensa_env_get_cpu(const CPUXtensaState *env)
475 {
476     return container_of(env, XtensaCPU, env);
477 }
478 
479 #define ENV_GET_CPU(e) CPU(xtensa_env_get_cpu(e))
480 
481 #define ENV_OFFSET offsetof(XtensaCPU, env)
482 
483 void xtensa_cpu_do_interrupt(CPUState *cpu);
484 bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request);
485 void xtensa_cpu_do_unassigned_access(CPUState *cpu, hwaddr addr,
486                                      bool is_write, bool is_exec, int opaque,
487                                      unsigned size);
488 void xtensa_cpu_dump_state(CPUState *cpu, FILE *f,
489                            fprintf_function cpu_fprintf, int flags);
490 hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
491 int xtensa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
492 int xtensa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
493 void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
494                                     MMUAccessType access_type,
495                                     int mmu_idx, uintptr_t retaddr);
496 
497 #define cpu_signal_handler cpu_xtensa_signal_handler
498 #define cpu_list xtensa_cpu_list
499 
500 #define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU
501 #define XTENSA_CPU_TYPE_NAME(model) model XTENSA_CPU_TYPE_SUFFIX
502 
503 #ifdef TARGET_WORDS_BIGENDIAN
504 #define XTENSA_DEFAULT_CPU_MODEL "fsf"
505 #define XTENSA_DEFAULT_CPU_NOMMU_MODEL "fsf"
506 #else
507 #define XTENSA_DEFAULT_CPU_MODEL "dc232b"
508 #define XTENSA_DEFAULT_CPU_NOMMU_MODEL "de212"
509 #endif
510 #define XTENSA_DEFAULT_CPU_TYPE \
511     XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_MODEL)
512 #define XTENSA_DEFAULT_CPU_NOMMU_TYPE \
513     XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_NOMMU_MODEL)
514 
515 #define cpu_init(cpu_model) cpu_generic_init(TYPE_XTENSA_CPU, cpu_model)
516 
517 void xtensa_translate_init(void);
518 void xtensa_breakpoint_handler(CPUState *cs);
519 void xtensa_finalize_config(XtensaConfig *config);
520 void xtensa_register_core(XtensaConfigList *node);
521 void xtensa_sim_open_console(Chardev *chr);
522 void check_interrupts(CPUXtensaState *s);
523 void xtensa_irq_init(CPUXtensaState *env);
524 void *xtensa_get_extint(CPUXtensaState *env, unsigned extint);
525 void xtensa_timer_irq(CPUXtensaState *env, uint32_t id, uint32_t active);
526 int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc);
527 void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf);
528 void xtensa_sync_window_from_phys(CPUXtensaState *env);
529 void xtensa_sync_phys_from_window(CPUXtensaState *env);
530 uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way);
531 void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb,
532         uint32_t *vpn, uint32_t wi, uint32_t *ei);
533 int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
534         uint32_t *pwi, uint32_t *pei, uint8_t *pring);
535 void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
536         xtensa_tlb_entry *entry, bool dtlb,
537         unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
538 void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
539         unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
540 int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
541         uint32_t vaddr, int is_write, int mmu_idx,
542         uint32_t *paddr, uint32_t *page_size, unsigned *access);
543 void reset_mmu(CPUXtensaState *env);
544 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env);
545 void debug_exception_env(CPUXtensaState *new_env, uint32_t cause);
546 static inline MemoryRegion *xtensa_get_er_region(CPUXtensaState *env)
547 {
548     return env->system_er;
549 }
550 
551 static inline void xtensa_select_static_vectors(CPUXtensaState *env,
552                                                 unsigned n)
553 {
554     assert(n < 2);
555     env->static_vectors = n;
556 }
557 void xtensa_runstall(CPUXtensaState *env, bool runstall);
558 XtensaOpcodeOps *xtensa_find_opcode_ops(const XtensaOpcodeTranslators *t,
559                                         const char *opcode);
560 
561 #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
562 #define XTENSA_OPTION_ALL (~(uint64_t)0)
563 
564 static inline bool xtensa_option_bits_enabled(const XtensaConfig *config,
565         uint64_t opt)
566 {
567     return (config->options & opt) != 0;
568 }
569 
570 static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt)
571 {
572     return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt));
573 }
574 
575 static inline int xtensa_get_cintlevel(const CPUXtensaState *env)
576 {
577     int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT;
578     if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) {
579         level = env->config->excm_level;
580     }
581     return level;
582 }
583 
584 static inline int xtensa_get_ring(const CPUXtensaState *env)
585 {
586     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
587         return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
588     } else {
589         return 0;
590     }
591 }
592 
593 static inline int xtensa_get_cring(const CPUXtensaState *env)
594 {
595     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) &&
596             (env->sregs[PS] & PS_EXCM) == 0) {
597         return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
598     } else {
599         return 0;
600     }
601 }
602 
603 static inline xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env,
604         bool dtlb, unsigned wi, unsigned ei)
605 {
606     return dtlb ?
607         env->dtlb[wi] + ei :
608         env->itlb[wi] + ei;
609 }
610 
611 static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env)
612 {
613     return env->sregs[WINDOW_START] |
614         (env->sregs[WINDOW_START] << env->config->nareg / 4);
615 }
616 
617 /* MMU modes definitions */
618 #define MMU_MODE0_SUFFIX _ring0
619 #define MMU_MODE1_SUFFIX _ring1
620 #define MMU_MODE2_SUFFIX _ring2
621 #define MMU_MODE3_SUFFIX _ring3
622 
623 static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch)
624 {
625     return xtensa_get_cring(env);
626 }
627 
628 #define XTENSA_TBFLAG_RING_MASK 0x3
629 #define XTENSA_TBFLAG_EXCM 0x4
630 #define XTENSA_TBFLAG_LITBASE 0x8
631 #define XTENSA_TBFLAG_DEBUG 0x10
632 #define XTENSA_TBFLAG_ICOUNT 0x20
633 #define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0
634 #define XTENSA_TBFLAG_CPENABLE_SHIFT 6
635 #define XTENSA_TBFLAG_EXCEPTION 0x4000
636 #define XTENSA_TBFLAG_WINDOW_MASK 0x18000
637 #define XTENSA_TBFLAG_WINDOW_SHIFT 15
638 #define XTENSA_TBFLAG_YIELD 0x20000
639 
640 static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
641         target_ulong *cs_base, uint32_t *flags)
642 {
643     CPUState *cs = CPU(xtensa_env_get_cpu(env));
644 
645     *pc = env->pc;
646     *cs_base = 0;
647     *flags = 0;
648     *flags |= xtensa_get_ring(env);
649     if (env->sregs[PS] & PS_EXCM) {
650         *flags |= XTENSA_TBFLAG_EXCM;
651     }
652     if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
653             (env->sregs[LITBASE] & 1)) {
654         *flags |= XTENSA_TBFLAG_LITBASE;
655     }
656     if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) {
657         if (xtensa_get_cintlevel(env) < env->config->debug_level) {
658             *flags |= XTENSA_TBFLAG_DEBUG;
659         }
660         if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
661             *flags |= XTENSA_TBFLAG_ICOUNT;
662         }
663     }
664     if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) {
665         *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT;
666     }
667     if (cs->singlestep_enabled && env->exception_taken) {
668         *flags |= XTENSA_TBFLAG_EXCEPTION;
669     }
670     if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) &&
671         (env->sregs[PS] & (PS_WOE | PS_EXCM)) == PS_WOE) {
672         uint32_t windowstart = xtensa_replicate_windowstart(env) >>
673             (env->sregs[WINDOW_BASE] + 1);
674         uint32_t w = ctz32(windowstart | 0x8);
675 
676         *flags |= w << XTENSA_TBFLAG_WINDOW_SHIFT;
677     } else {
678         *flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT;
679     }
680     if (env->yield_needed) {
681         *flags |= XTENSA_TBFLAG_YIELD;
682     }
683 }
684 
685 #include "exec/cpu-all.h"
686 
687 #endif
688