1 /* 2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * * Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * * Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * * Neither the name of the Open Source and Linux Lab nor the 13 * names of its contributors may be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #ifndef XTENSA_CPU_H 29 #define XTENSA_CPU_H 30 31 #define ALIGNED_ONLY 32 #define TARGET_LONG_BITS 32 33 34 /* Xtensa processors have a weak memory model */ 35 #define TCG_GUEST_DEFAULT_MO (0) 36 37 #define CPUArchState struct CPUXtensaState 38 39 #include "qemu-common.h" 40 #include "cpu-qom.h" 41 #include "exec/cpu-defs.h" 42 #include "xtensa-isa.h" 43 44 #define NB_MMU_MODES 4 45 46 #define TARGET_PHYS_ADDR_SPACE_BITS 32 47 #ifdef CONFIG_USER_ONLY 48 #define TARGET_VIRT_ADDR_SPACE_BITS 30 49 #else 50 #define TARGET_VIRT_ADDR_SPACE_BITS 32 51 #endif 52 #define TARGET_PAGE_BITS 12 53 54 enum { 55 /* Additional instructions */ 56 XTENSA_OPTION_CODE_DENSITY, 57 XTENSA_OPTION_LOOP, 58 XTENSA_OPTION_EXTENDED_L32R, 59 XTENSA_OPTION_16_BIT_IMUL, 60 XTENSA_OPTION_32_BIT_IMUL, 61 XTENSA_OPTION_32_BIT_IMUL_HIGH, 62 XTENSA_OPTION_32_BIT_IDIV, 63 XTENSA_OPTION_MAC16, 64 XTENSA_OPTION_MISC_OP_NSA, 65 XTENSA_OPTION_MISC_OP_MINMAX, 66 XTENSA_OPTION_MISC_OP_SEXT, 67 XTENSA_OPTION_MISC_OP_CLAMPS, 68 XTENSA_OPTION_COPROCESSOR, 69 XTENSA_OPTION_BOOLEAN, 70 XTENSA_OPTION_FP_COPROCESSOR, 71 XTENSA_OPTION_MP_SYNCHRO, 72 XTENSA_OPTION_CONDITIONAL_STORE, 73 XTENSA_OPTION_ATOMCTL, 74 XTENSA_OPTION_DEPBITS, 75 76 /* Interrupts and exceptions */ 77 XTENSA_OPTION_EXCEPTION, 78 XTENSA_OPTION_RELOCATABLE_VECTOR, 79 XTENSA_OPTION_UNALIGNED_EXCEPTION, 80 XTENSA_OPTION_INTERRUPT, 81 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 82 XTENSA_OPTION_TIMER_INTERRUPT, 83 84 /* Local memory */ 85 XTENSA_OPTION_ICACHE, 86 XTENSA_OPTION_ICACHE_TEST, 87 XTENSA_OPTION_ICACHE_INDEX_LOCK, 88 XTENSA_OPTION_DCACHE, 89 XTENSA_OPTION_DCACHE_TEST, 90 XTENSA_OPTION_DCACHE_INDEX_LOCK, 91 XTENSA_OPTION_IRAM, 92 XTENSA_OPTION_IROM, 93 XTENSA_OPTION_DRAM, 94 XTENSA_OPTION_DROM, 95 XTENSA_OPTION_XLMI, 96 XTENSA_OPTION_HW_ALIGNMENT, 97 XTENSA_OPTION_MEMORY_ECC_PARITY, 98 99 /* Memory protection and translation */ 100 XTENSA_OPTION_REGION_PROTECTION, 101 XTENSA_OPTION_REGION_TRANSLATION, 102 XTENSA_OPTION_MPU, 103 XTENSA_OPTION_MMU, 104 XTENSA_OPTION_CACHEATTR, 105 106 /* Other */ 107 XTENSA_OPTION_WINDOWED_REGISTER, 108 XTENSA_OPTION_PROCESSOR_INTERFACE, 109 XTENSA_OPTION_MISC_SR, 110 XTENSA_OPTION_THREAD_POINTER, 111 XTENSA_OPTION_PROCESSOR_ID, 112 XTENSA_OPTION_DEBUG, 113 XTENSA_OPTION_TRACE_PORT, 114 XTENSA_OPTION_EXTERN_REGS, 115 }; 116 117 enum { 118 EXPSTATE = 230, 119 THREADPTR = 231, 120 FCR = 232, 121 FSR = 233, 122 }; 123 124 enum { 125 LBEG = 0, 126 LEND = 1, 127 LCOUNT = 2, 128 SAR = 3, 129 BR = 4, 130 LITBASE = 5, 131 SCOMPARE1 = 12, 132 ACCLO = 16, 133 ACCHI = 17, 134 MR = 32, 135 PREFCTL = 40, 136 WINDOW_BASE = 72, 137 WINDOW_START = 73, 138 PTEVADDR = 83, 139 MMID = 89, 140 RASID = 90, 141 MPUENB = 90, 142 ITLBCFG = 91, 143 DTLBCFG = 92, 144 MPUCFG = 92, 145 ERACCESS = 95, 146 IBREAKENABLE = 96, 147 MEMCTL = 97, 148 CACHEATTR = 98, 149 CACHEADRDIS = 98, 150 ATOMCTL = 99, 151 DDR = 104, 152 MEPC = 106, 153 MEPS = 107, 154 MESAVE = 108, 155 MESR = 109, 156 MECR = 110, 157 MEVADDR = 111, 158 IBREAKA = 128, 159 DBREAKA = 144, 160 DBREAKC = 160, 161 CONFIGID0 = 176, 162 EPC1 = 177, 163 DEPC = 192, 164 EPS2 = 194, 165 CONFIGID1 = 208, 166 EXCSAVE1 = 209, 167 CPENABLE = 224, 168 INTSET = 226, 169 INTCLEAR = 227, 170 INTENABLE = 228, 171 PS = 230, 172 VECBASE = 231, 173 EXCCAUSE = 232, 174 DEBUGCAUSE = 233, 175 CCOUNT = 234, 176 PRID = 235, 177 ICOUNT = 236, 178 ICOUNTLEVEL = 237, 179 EXCVADDR = 238, 180 CCOMPARE = 240, 181 MISC = 244, 182 }; 183 184 #define PS_INTLEVEL 0xf 185 #define PS_INTLEVEL_SHIFT 0 186 187 #define PS_EXCM 0x10 188 #define PS_UM 0x20 189 190 #define PS_RING 0xc0 191 #define PS_RING_SHIFT 6 192 193 #define PS_OWB 0xf00 194 #define PS_OWB_SHIFT 8 195 #define PS_OWB_LEN 4 196 197 #define PS_CALLINC 0x30000 198 #define PS_CALLINC_SHIFT 16 199 #define PS_CALLINC_LEN 2 200 201 #define PS_WOE 0x40000 202 203 #define DEBUGCAUSE_IC 0x1 204 #define DEBUGCAUSE_IB 0x2 205 #define DEBUGCAUSE_DB 0x4 206 #define DEBUGCAUSE_BI 0x8 207 #define DEBUGCAUSE_BN 0x10 208 #define DEBUGCAUSE_DI 0x20 209 #define DEBUGCAUSE_DBNUM 0xf00 210 #define DEBUGCAUSE_DBNUM_SHIFT 8 211 212 #define DBREAKC_SB 0x80000000 213 #define DBREAKC_LB 0x40000000 214 #define DBREAKC_SB_LB (DBREAKC_SB | DBREAKC_LB) 215 #define DBREAKC_MASK 0x3f 216 217 #define MEMCTL_INIT 0x00800000 218 #define MEMCTL_IUSEWAYS_SHIFT 18 219 #define MEMCTL_IUSEWAYS_LEN 5 220 #define MEMCTL_IUSEWAYS_MASK 0x007c0000 221 #define MEMCTL_DALLOCWAYS_SHIFT 13 222 #define MEMCTL_DALLOCWAYS_LEN 5 223 #define MEMCTL_DALLOCWAYS_MASK 0x0003e000 224 #define MEMCTL_DUSEWAYS_SHIFT 8 225 #define MEMCTL_DUSEWAYS_LEN 5 226 #define MEMCTL_DUSEWAYS_MASK 0x00001f00 227 #define MEMCTL_ISNP 0x4 228 #define MEMCTL_DSNP 0x2 229 #define MEMCTL_IL0EN 0x1 230 231 #define MAX_INSN_LENGTH 64 232 #define MAX_INSN_SLOTS 32 233 #define MAX_OPCODE_ARGS 16 234 #define MAX_NAREG 64 235 #define MAX_NINTERRUPT 32 236 #define MAX_NLEVEL 6 237 #define MAX_NNMI 1 238 #define MAX_NCCOMPARE 3 239 #define MAX_TLB_WAY_SIZE 8 240 #define MAX_NDBREAK 2 241 #define MAX_NMEMORY 4 242 #define MAX_MPU_FOREGROUND_SEGMENTS 32 243 244 #define REGION_PAGE_MASK 0xe0000000 245 246 #define PAGE_CACHE_MASK 0x700 247 #define PAGE_CACHE_SHIFT 8 248 #define PAGE_CACHE_INVALID 0x000 249 #define PAGE_CACHE_BYPASS 0x100 250 #define PAGE_CACHE_WT 0x200 251 #define PAGE_CACHE_WB 0x400 252 #define PAGE_CACHE_ISOLATE 0x600 253 254 enum { 255 /* Static vectors */ 256 EXC_RESET0, 257 EXC_RESET1, 258 EXC_MEMORY_ERROR, 259 260 /* Dynamic vectors */ 261 EXC_WINDOW_OVERFLOW4, 262 EXC_WINDOW_UNDERFLOW4, 263 EXC_WINDOW_OVERFLOW8, 264 EXC_WINDOW_UNDERFLOW8, 265 EXC_WINDOW_OVERFLOW12, 266 EXC_WINDOW_UNDERFLOW12, 267 EXC_IRQ, 268 EXC_KERNEL, 269 EXC_USER, 270 EXC_DOUBLE, 271 EXC_DEBUG, 272 EXC_MAX 273 }; 274 275 enum { 276 ILLEGAL_INSTRUCTION_CAUSE = 0, 277 SYSCALL_CAUSE, 278 INSTRUCTION_FETCH_ERROR_CAUSE, 279 LOAD_STORE_ERROR_CAUSE, 280 LEVEL1_INTERRUPT_CAUSE, 281 ALLOCA_CAUSE, 282 INTEGER_DIVIDE_BY_ZERO_CAUSE, 283 PC_VALUE_ERROR_CAUSE, 284 PRIVILEGED_CAUSE, 285 LOAD_STORE_ALIGNMENT_CAUSE, 286 EXTERNAL_REG_PRIVILEGE_CAUSE, 287 EXCLUSIVE_ERROR_CAUSE, 288 INSTR_PIF_DATA_ERROR_CAUSE, 289 LOAD_STORE_PIF_DATA_ERROR_CAUSE, 290 INSTR_PIF_ADDR_ERROR_CAUSE, 291 LOAD_STORE_PIF_ADDR_ERROR_CAUSE, 292 INST_TLB_MISS_CAUSE, 293 INST_TLB_MULTI_HIT_CAUSE, 294 INST_FETCH_PRIVILEGE_CAUSE, 295 INST_FETCH_PROHIBITED_CAUSE = 20, 296 LOAD_STORE_TLB_MISS_CAUSE = 24, 297 LOAD_STORE_TLB_MULTI_HIT_CAUSE, 298 LOAD_STORE_PRIVILEGE_CAUSE, 299 LOAD_PROHIBITED_CAUSE = 28, 300 STORE_PROHIBITED_CAUSE, 301 302 COPROCESSOR0_DISABLED = 32, 303 }; 304 305 typedef enum { 306 INTTYPE_LEVEL, 307 INTTYPE_EDGE, 308 INTTYPE_NMI, 309 INTTYPE_SOFTWARE, 310 INTTYPE_TIMER, 311 INTTYPE_DEBUG, 312 INTTYPE_WRITE_ERR, 313 INTTYPE_PROFILING, 314 INTTYPE_IDMA_DONE, 315 INTTYPE_IDMA_ERR, 316 INTTYPE_GS_ERR, 317 INTTYPE_MAX 318 } interrupt_type; 319 320 struct CPUXtensaState; 321 322 typedef struct xtensa_tlb_entry { 323 uint32_t vaddr; 324 uint32_t paddr; 325 uint8_t asid; 326 uint8_t attr; 327 bool variable; 328 } xtensa_tlb_entry; 329 330 typedef struct xtensa_tlb { 331 unsigned nways; 332 const unsigned way_size[10]; 333 bool varway56; 334 unsigned nrefillentries; 335 } xtensa_tlb; 336 337 typedef struct xtensa_mpu_entry { 338 uint32_t vaddr; 339 uint32_t attr; 340 } xtensa_mpu_entry; 341 342 typedef struct XtensaGdbReg { 343 int targno; 344 unsigned flags; 345 int type; 346 int group; 347 unsigned size; 348 } XtensaGdbReg; 349 350 typedef struct XtensaGdbRegmap { 351 int num_regs; 352 int num_core_regs; 353 /* PC + a + ar + sr + ur */ 354 XtensaGdbReg reg[1 + 16 + 64 + 256 + 256]; 355 } XtensaGdbRegmap; 356 357 typedef struct XtensaCcompareTimer { 358 struct CPUXtensaState *env; 359 QEMUTimer *timer; 360 } XtensaCcompareTimer; 361 362 typedef struct XtensaMemory { 363 unsigned num; 364 struct XtensaMemoryRegion { 365 uint32_t addr; 366 uint32_t size; 367 } location[MAX_NMEMORY]; 368 } XtensaMemory; 369 370 typedef struct opcode_arg { 371 uint32_t imm; 372 uint32_t raw_imm; 373 void *in; 374 void *out; 375 } OpcodeArg; 376 377 typedef struct DisasContext DisasContext; 378 typedef void (*XtensaOpcodeOp)(DisasContext *dc, const OpcodeArg arg[], 379 const uint32_t par[]); 380 typedef bool (*XtensaOpcodeBoolTest)(DisasContext *dc, 381 const OpcodeArg arg[], 382 const uint32_t par[]); 383 typedef uint32_t (*XtensaOpcodeUintTest)(DisasContext *dc, 384 const OpcodeArg arg[], 385 const uint32_t par[]); 386 387 enum { 388 XTENSA_OP_ILL = 0x1, 389 XTENSA_OP_PRIVILEGED = 0x2, 390 XTENSA_OP_SYSCALL = 0x4, 391 XTENSA_OP_DEBUG_BREAK = 0x8, 392 393 XTENSA_OP_OVERFLOW = 0x10, 394 XTENSA_OP_UNDERFLOW = 0x20, 395 XTENSA_OP_ALLOCA = 0x40, 396 XTENSA_OP_COPROCESSOR = 0x80, 397 398 XTENSA_OP_DIVIDE_BY_ZERO = 0x100, 399 400 /* Postprocessing flags */ 401 XTENSA_OP_CHECK_INTERRUPTS = 0x200, 402 XTENSA_OP_EXIT_TB_M1 = 0x400, 403 XTENSA_OP_EXIT_TB_0 = 0x800, 404 XTENSA_OP_SYNC_REGISTER_WINDOW = 0x1000, 405 406 XTENSA_OP_POSTPROCESS = 407 XTENSA_OP_CHECK_INTERRUPTS | 408 XTENSA_OP_EXIT_TB_M1 | 409 XTENSA_OP_EXIT_TB_0 | 410 XTENSA_OP_SYNC_REGISTER_WINDOW, 411 412 XTENSA_OP_NAME_ARRAY = 0x8000, 413 414 XTENSA_OP_CONTROL_FLOW = 0x10000, 415 XTENSA_OP_STORE = 0x20000, 416 XTENSA_OP_LOAD = 0x40000, 417 XTENSA_OP_LOAD_STORE = 418 XTENSA_OP_LOAD | XTENSA_OP_STORE, 419 }; 420 421 typedef struct XtensaOpcodeOps { 422 const void *name; 423 XtensaOpcodeOp translate; 424 XtensaOpcodeBoolTest test_ill; 425 XtensaOpcodeUintTest test_overflow; 426 const uint32_t *par; 427 uint32_t op_flags; 428 uint32_t coprocessor; 429 } XtensaOpcodeOps; 430 431 typedef struct XtensaOpcodeTranslators { 432 unsigned num_opcodes; 433 const XtensaOpcodeOps *opcode; 434 } XtensaOpcodeTranslators; 435 436 extern const XtensaOpcodeTranslators xtensa_core_opcodes; 437 extern const XtensaOpcodeTranslators xtensa_fpu2000_opcodes; 438 439 struct XtensaConfig { 440 const char *name; 441 uint64_t options; 442 XtensaGdbRegmap gdb_regmap; 443 unsigned nareg; 444 int excm_level; 445 int ndepc; 446 unsigned inst_fetch_width; 447 unsigned max_insn_size; 448 uint32_t vecbase; 449 uint32_t exception_vector[EXC_MAX]; 450 unsigned ninterrupt; 451 unsigned nlevel; 452 uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1]; 453 uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1]; 454 uint32_t inttype_mask[INTTYPE_MAX]; 455 struct { 456 uint32_t level; 457 interrupt_type inttype; 458 } interrupt[MAX_NINTERRUPT]; 459 unsigned nccompare; 460 uint32_t timerint[MAX_NCCOMPARE]; 461 unsigned nextint; 462 unsigned extint[MAX_NINTERRUPT]; 463 464 unsigned debug_level; 465 unsigned nibreak; 466 unsigned ndbreak; 467 468 unsigned icache_ways; 469 unsigned dcache_ways; 470 unsigned dcache_line_bytes; 471 uint32_t memctl_mask; 472 473 XtensaMemory instrom; 474 XtensaMemory instram; 475 XtensaMemory datarom; 476 XtensaMemory dataram; 477 XtensaMemory sysrom; 478 XtensaMemory sysram; 479 480 uint32_t configid[2]; 481 482 void *isa_internal; 483 xtensa_isa isa; 484 XtensaOpcodeOps **opcode_ops; 485 const XtensaOpcodeTranslators **opcode_translators; 486 xtensa_regfile a_regfile; 487 void ***regfile; 488 489 uint32_t clock_freq_khz; 490 491 xtensa_tlb itlb; 492 xtensa_tlb dtlb; 493 494 uint32_t mpu_align; 495 unsigned n_mpu_fg_segments; 496 unsigned n_mpu_bg_segments; 497 const xtensa_mpu_entry *mpu_bg; 498 }; 499 500 typedef struct XtensaConfigList { 501 const XtensaConfig *config; 502 struct XtensaConfigList *next; 503 } XtensaConfigList; 504 505 #ifdef HOST_WORDS_BIGENDIAN 506 enum { 507 FP_F32_HIGH, 508 FP_F32_LOW, 509 }; 510 #else 511 enum { 512 FP_F32_LOW, 513 FP_F32_HIGH, 514 }; 515 #endif 516 517 typedef struct CPUXtensaState { 518 const XtensaConfig *config; 519 uint32_t regs[16]; 520 uint32_t pc; 521 uint32_t sregs[256]; 522 uint32_t uregs[256]; 523 uint32_t phys_regs[MAX_NAREG]; 524 union { 525 float32 f32[2]; 526 float64 f64; 527 } fregs[16]; 528 float_status fp_status; 529 uint32_t windowbase_next; 530 uint32_t exclusive_addr; 531 uint32_t exclusive_val; 532 533 #ifndef CONFIG_USER_ONLY 534 xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE]; 535 xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE]; 536 xtensa_mpu_entry mpu_fg[MAX_MPU_FOREGROUND_SEGMENTS]; 537 unsigned autorefill_idx; 538 bool runstall; 539 AddressSpace *address_space_er; 540 MemoryRegion *system_er; 541 int pending_irq_level; /* level of last raised IRQ */ 542 qemu_irq *irq_inputs; 543 qemu_irq ext_irq_inputs[MAX_NINTERRUPT]; 544 qemu_irq runstall_irq; 545 XtensaCcompareTimer ccompare[MAX_NCCOMPARE]; 546 uint64_t time_base; 547 uint64_t ccount_time; 548 uint32_t ccount_base; 549 #endif 550 551 int exception_taken; 552 int yield_needed; 553 unsigned static_vectors; 554 555 /* Watchpoints for DBREAK registers */ 556 struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK]; 557 558 CPU_COMMON 559 } CPUXtensaState; 560 561 /** 562 * XtensaCPU: 563 * @env: #CPUXtensaState 564 * 565 * An Xtensa CPU. 566 */ 567 struct XtensaCPU { 568 /*< private >*/ 569 CPUState parent_obj; 570 /*< public >*/ 571 572 CPUXtensaState env; 573 }; 574 575 static inline XtensaCPU *xtensa_env_get_cpu(const CPUXtensaState *env) 576 { 577 return container_of(env, XtensaCPU, env); 578 } 579 580 #define ENV_GET_CPU(e) CPU(xtensa_env_get_cpu(e)) 581 582 #define ENV_OFFSET offsetof(XtensaCPU, env) 583 584 585 bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 586 MMUAccessType access_type, int mmu_idx, 587 bool probe, uintptr_t retaddr); 588 void xtensa_cpu_do_interrupt(CPUState *cpu); 589 bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request); 590 void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, 591 unsigned size, MMUAccessType access_type, 592 int mmu_idx, MemTxAttrs attrs, 593 MemTxResult response, uintptr_t retaddr); 594 void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, int flags); 595 hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 596 void xtensa_count_regs(const XtensaConfig *config, 597 unsigned *n_regs, unsigned *n_core_regs); 598 int xtensa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 599 int xtensa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 600 void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, 601 MMUAccessType access_type, 602 int mmu_idx, uintptr_t retaddr); 603 604 #define cpu_signal_handler cpu_xtensa_signal_handler 605 #define cpu_list xtensa_cpu_list 606 607 #define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU 608 #define XTENSA_CPU_TYPE_NAME(model) model XTENSA_CPU_TYPE_SUFFIX 609 #define CPU_RESOLVING_TYPE TYPE_XTENSA_CPU 610 611 #ifdef TARGET_WORDS_BIGENDIAN 612 #define XTENSA_DEFAULT_CPU_MODEL "fsf" 613 #define XTENSA_DEFAULT_CPU_NOMMU_MODEL "fsf" 614 #else 615 #define XTENSA_DEFAULT_CPU_MODEL "dc232b" 616 #define XTENSA_DEFAULT_CPU_NOMMU_MODEL "de212" 617 #endif 618 #define XTENSA_DEFAULT_CPU_TYPE \ 619 XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_MODEL) 620 #define XTENSA_DEFAULT_CPU_NOMMU_TYPE \ 621 XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_NOMMU_MODEL) 622 623 void xtensa_collect_sr_names(const XtensaConfig *config); 624 void xtensa_translate_init(void); 625 void **xtensa_get_regfile_by_name(const char *name); 626 void xtensa_breakpoint_handler(CPUState *cs); 627 void xtensa_register_core(XtensaConfigList *node); 628 void xtensa_sim_open_console(Chardev *chr); 629 void check_interrupts(CPUXtensaState *s); 630 void xtensa_irq_init(CPUXtensaState *env); 631 qemu_irq *xtensa_get_extints(CPUXtensaState *env); 632 qemu_irq xtensa_get_runstall(CPUXtensaState *env); 633 int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc); 634 void xtensa_cpu_list(void); 635 void xtensa_sync_window_from_phys(CPUXtensaState *env); 636 void xtensa_sync_phys_from_window(CPUXtensaState *env); 637 void xtensa_rotate_window(CPUXtensaState *env, uint32_t delta); 638 void xtensa_restore_owb(CPUXtensaState *env); 639 void debug_exception_env(CPUXtensaState *new_env, uint32_t cause); 640 641 static inline void xtensa_select_static_vectors(CPUXtensaState *env, 642 unsigned n) 643 { 644 assert(n < 2); 645 env->static_vectors = n; 646 } 647 void xtensa_runstall(CPUXtensaState *env, bool runstall); 648 649 #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt)) 650 #define XTENSA_OPTION_ALL (~(uint64_t)0) 651 652 static inline bool xtensa_option_bits_enabled(const XtensaConfig *config, 653 uint64_t opt) 654 { 655 return (config->options & opt) != 0; 656 } 657 658 static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt) 659 { 660 return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt)); 661 } 662 663 static inline int xtensa_get_cintlevel(const CPUXtensaState *env) 664 { 665 int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT; 666 if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) { 667 level = env->config->excm_level; 668 } 669 return level; 670 } 671 672 static inline int xtensa_get_ring(const CPUXtensaState *env) 673 { 674 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 675 return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT; 676 } else { 677 return 0; 678 } 679 } 680 681 static inline int xtensa_get_cring(const CPUXtensaState *env) 682 { 683 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) && 684 (env->sregs[PS] & PS_EXCM) == 0) { 685 return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT; 686 } else { 687 return 0; 688 } 689 } 690 691 #ifndef CONFIG_USER_ONLY 692 int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb, 693 uint32_t vaddr, int is_write, int mmu_idx, 694 uint32_t *paddr, uint32_t *page_size, unsigned *access); 695 void reset_mmu(CPUXtensaState *env); 696 void dump_mmu(CPUXtensaState *env); 697 698 static inline MemoryRegion *xtensa_get_er_region(CPUXtensaState *env) 699 { 700 return env->system_er; 701 } 702 #endif 703 704 static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env) 705 { 706 return env->sregs[WINDOW_START] | 707 (env->sregs[WINDOW_START] << env->config->nareg / 4); 708 } 709 710 /* MMU modes definitions */ 711 #define MMU_MODE0_SUFFIX _ring0 712 #define MMU_MODE1_SUFFIX _ring1 713 #define MMU_MODE2_SUFFIX _ring2 714 #define MMU_MODE3_SUFFIX _ring3 715 #define MMU_USER_IDX 3 716 717 static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch) 718 { 719 return xtensa_get_cring(env); 720 } 721 722 #define XTENSA_TBFLAG_RING_MASK 0x3 723 #define XTENSA_TBFLAG_EXCM 0x4 724 #define XTENSA_TBFLAG_LITBASE 0x8 725 #define XTENSA_TBFLAG_DEBUG 0x10 726 #define XTENSA_TBFLAG_ICOUNT 0x20 727 #define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0 728 #define XTENSA_TBFLAG_CPENABLE_SHIFT 6 729 #define XTENSA_TBFLAG_EXCEPTION 0x4000 730 #define XTENSA_TBFLAG_WINDOW_MASK 0x18000 731 #define XTENSA_TBFLAG_WINDOW_SHIFT 15 732 #define XTENSA_TBFLAG_YIELD 0x20000 733 #define XTENSA_TBFLAG_CWOE 0x40000 734 #define XTENSA_TBFLAG_CALLINC_MASK 0x180000 735 #define XTENSA_TBFLAG_CALLINC_SHIFT 19 736 737 #define XTENSA_CSBASE_LEND_MASK 0x0000ffff 738 #define XTENSA_CSBASE_LEND_SHIFT 0 739 #define XTENSA_CSBASE_LBEG_OFF_MASK 0x00ff0000 740 #define XTENSA_CSBASE_LBEG_OFF_SHIFT 16 741 742 static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc, 743 target_ulong *cs_base, uint32_t *flags) 744 { 745 CPUState *cs = CPU(xtensa_env_get_cpu(env)); 746 747 *pc = env->pc; 748 *cs_base = 0; 749 *flags = 0; 750 *flags |= xtensa_get_ring(env); 751 if (env->sregs[PS] & PS_EXCM) { 752 *flags |= XTENSA_TBFLAG_EXCM; 753 } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) { 754 target_ulong lend_dist = 755 env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS)); 756 757 /* 758 * 0 in the csbase_lend field means that there may not be a loopback 759 * for any instruction that starts inside this page. Any other value 760 * means that an instruction that ends at this offset from the page 761 * start may loop back and will need loopback code to be generated. 762 * 763 * lend_dist is 0 when LEND points to the start of the page, but 764 * no instruction that starts inside this page may end at offset 0, 765 * so it's still correct. 766 * 767 * When an instruction ends at a page boundary it may only start in 768 * the previous page. lend_dist will be encoded as TARGET_PAGE_SIZE 769 * for the TB that contains this instruction. 770 */ 771 if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_size) { 772 target_ulong lbeg_off = env->sregs[LEND] - env->sregs[LBEG]; 773 774 *cs_base = lend_dist; 775 if (lbeg_off < 256) { 776 *cs_base |= lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT; 777 } 778 } 779 } 780 if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) && 781 (env->sregs[LITBASE] & 1)) { 782 *flags |= XTENSA_TBFLAG_LITBASE; 783 } 784 if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) { 785 if (xtensa_get_cintlevel(env) < env->config->debug_level) { 786 *flags |= XTENSA_TBFLAG_DEBUG; 787 } 788 if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) { 789 *flags |= XTENSA_TBFLAG_ICOUNT; 790 } 791 } 792 if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) { 793 *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT; 794 } 795 if (cs->singlestep_enabled && env->exception_taken) { 796 *flags |= XTENSA_TBFLAG_EXCEPTION; 797 } 798 if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) && 799 (env->sregs[PS] & (PS_WOE | PS_EXCM)) == PS_WOE) { 800 uint32_t windowstart = xtensa_replicate_windowstart(env) >> 801 (env->sregs[WINDOW_BASE] + 1); 802 uint32_t w = ctz32(windowstart | 0x8); 803 804 *flags |= (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE; 805 *flags |= extract32(env->sregs[PS], PS_CALLINC_SHIFT, 806 PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT; 807 } else { 808 *flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT; 809 } 810 if (env->yield_needed) { 811 *flags |= XTENSA_TBFLAG_YIELD; 812 } 813 } 814 815 #include "exec/cpu-all.h" 816 817 #endif 818