1 /* 2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * * Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * * Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * * Neither the name of the Open Source and Linux Lab nor the 13 * names of its contributors may be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #ifndef XTENSA_CPU_H 29 #define XTENSA_CPU_H 30 31 #include "qemu-common.h" 32 #include "cpu-qom.h" 33 #include "exec/cpu-defs.h" 34 #include "xtensa-isa.h" 35 36 #define ALIGNED_ONLY 37 38 /* Xtensa processors have a weak memory model */ 39 #define TCG_GUEST_DEFAULT_MO (0) 40 41 #define CPUArchState struct CPUXtensaState 42 43 enum { 44 /* Additional instructions */ 45 XTENSA_OPTION_CODE_DENSITY, 46 XTENSA_OPTION_LOOP, 47 XTENSA_OPTION_EXTENDED_L32R, 48 XTENSA_OPTION_16_BIT_IMUL, 49 XTENSA_OPTION_32_BIT_IMUL, 50 XTENSA_OPTION_32_BIT_IMUL_HIGH, 51 XTENSA_OPTION_32_BIT_IDIV, 52 XTENSA_OPTION_MAC16, 53 XTENSA_OPTION_MISC_OP_NSA, 54 XTENSA_OPTION_MISC_OP_MINMAX, 55 XTENSA_OPTION_MISC_OP_SEXT, 56 XTENSA_OPTION_MISC_OP_CLAMPS, 57 XTENSA_OPTION_COPROCESSOR, 58 XTENSA_OPTION_BOOLEAN, 59 XTENSA_OPTION_FP_COPROCESSOR, 60 XTENSA_OPTION_MP_SYNCHRO, 61 XTENSA_OPTION_CONDITIONAL_STORE, 62 XTENSA_OPTION_ATOMCTL, 63 XTENSA_OPTION_DEPBITS, 64 65 /* Interrupts and exceptions */ 66 XTENSA_OPTION_EXCEPTION, 67 XTENSA_OPTION_RELOCATABLE_VECTOR, 68 XTENSA_OPTION_UNALIGNED_EXCEPTION, 69 XTENSA_OPTION_INTERRUPT, 70 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 71 XTENSA_OPTION_TIMER_INTERRUPT, 72 73 /* Local memory */ 74 XTENSA_OPTION_ICACHE, 75 XTENSA_OPTION_ICACHE_TEST, 76 XTENSA_OPTION_ICACHE_INDEX_LOCK, 77 XTENSA_OPTION_DCACHE, 78 XTENSA_OPTION_DCACHE_TEST, 79 XTENSA_OPTION_DCACHE_INDEX_LOCK, 80 XTENSA_OPTION_IRAM, 81 XTENSA_OPTION_IROM, 82 XTENSA_OPTION_DRAM, 83 XTENSA_OPTION_DROM, 84 XTENSA_OPTION_XLMI, 85 XTENSA_OPTION_HW_ALIGNMENT, 86 XTENSA_OPTION_MEMORY_ECC_PARITY, 87 88 /* Memory protection and translation */ 89 XTENSA_OPTION_REGION_PROTECTION, 90 XTENSA_OPTION_REGION_TRANSLATION, 91 XTENSA_OPTION_MPU, 92 XTENSA_OPTION_MMU, 93 XTENSA_OPTION_CACHEATTR, 94 95 /* Other */ 96 XTENSA_OPTION_WINDOWED_REGISTER, 97 XTENSA_OPTION_PROCESSOR_INTERFACE, 98 XTENSA_OPTION_MISC_SR, 99 XTENSA_OPTION_THREAD_POINTER, 100 XTENSA_OPTION_PROCESSOR_ID, 101 XTENSA_OPTION_DEBUG, 102 XTENSA_OPTION_TRACE_PORT, 103 XTENSA_OPTION_EXTERN_REGS, 104 }; 105 106 enum { 107 EXPSTATE = 230, 108 THREADPTR = 231, 109 FCR = 232, 110 FSR = 233, 111 }; 112 113 enum { 114 LBEG = 0, 115 LEND = 1, 116 LCOUNT = 2, 117 SAR = 3, 118 BR = 4, 119 LITBASE = 5, 120 SCOMPARE1 = 12, 121 ACCLO = 16, 122 ACCHI = 17, 123 MR = 32, 124 PREFCTL = 40, 125 WINDOW_BASE = 72, 126 WINDOW_START = 73, 127 PTEVADDR = 83, 128 MMID = 89, 129 RASID = 90, 130 MPUENB = 90, 131 ITLBCFG = 91, 132 DTLBCFG = 92, 133 MPUCFG = 92, 134 ERACCESS = 95, 135 IBREAKENABLE = 96, 136 MEMCTL = 97, 137 CACHEATTR = 98, 138 CACHEADRDIS = 98, 139 ATOMCTL = 99, 140 DDR = 104, 141 MEPC = 106, 142 MEPS = 107, 143 MESAVE = 108, 144 MESR = 109, 145 MECR = 110, 146 MEVADDR = 111, 147 IBREAKA = 128, 148 DBREAKA = 144, 149 DBREAKC = 160, 150 CONFIGID0 = 176, 151 EPC1 = 177, 152 DEPC = 192, 153 EPS2 = 194, 154 CONFIGID1 = 208, 155 EXCSAVE1 = 209, 156 CPENABLE = 224, 157 INTSET = 226, 158 INTCLEAR = 227, 159 INTENABLE = 228, 160 PS = 230, 161 VECBASE = 231, 162 EXCCAUSE = 232, 163 DEBUGCAUSE = 233, 164 CCOUNT = 234, 165 PRID = 235, 166 ICOUNT = 236, 167 ICOUNTLEVEL = 237, 168 EXCVADDR = 238, 169 CCOMPARE = 240, 170 MISC = 244, 171 }; 172 173 #define PS_INTLEVEL 0xf 174 #define PS_INTLEVEL_SHIFT 0 175 176 #define PS_EXCM 0x10 177 #define PS_UM 0x20 178 179 #define PS_RING 0xc0 180 #define PS_RING_SHIFT 6 181 182 #define PS_OWB 0xf00 183 #define PS_OWB_SHIFT 8 184 #define PS_OWB_LEN 4 185 186 #define PS_CALLINC 0x30000 187 #define PS_CALLINC_SHIFT 16 188 #define PS_CALLINC_LEN 2 189 190 #define PS_WOE 0x40000 191 192 #define DEBUGCAUSE_IC 0x1 193 #define DEBUGCAUSE_IB 0x2 194 #define DEBUGCAUSE_DB 0x4 195 #define DEBUGCAUSE_BI 0x8 196 #define DEBUGCAUSE_BN 0x10 197 #define DEBUGCAUSE_DI 0x20 198 #define DEBUGCAUSE_DBNUM 0xf00 199 #define DEBUGCAUSE_DBNUM_SHIFT 8 200 201 #define DBREAKC_SB 0x80000000 202 #define DBREAKC_LB 0x40000000 203 #define DBREAKC_SB_LB (DBREAKC_SB | DBREAKC_LB) 204 #define DBREAKC_MASK 0x3f 205 206 #define MEMCTL_INIT 0x00800000 207 #define MEMCTL_IUSEWAYS_SHIFT 18 208 #define MEMCTL_IUSEWAYS_LEN 5 209 #define MEMCTL_IUSEWAYS_MASK 0x007c0000 210 #define MEMCTL_DALLOCWAYS_SHIFT 13 211 #define MEMCTL_DALLOCWAYS_LEN 5 212 #define MEMCTL_DALLOCWAYS_MASK 0x0003e000 213 #define MEMCTL_DUSEWAYS_SHIFT 8 214 #define MEMCTL_DUSEWAYS_LEN 5 215 #define MEMCTL_DUSEWAYS_MASK 0x00001f00 216 #define MEMCTL_ISNP 0x4 217 #define MEMCTL_DSNP 0x2 218 #define MEMCTL_IL0EN 0x1 219 220 #define MAX_INSN_LENGTH 64 221 #define MAX_INSN_SLOTS 32 222 #define MAX_OPCODE_ARGS 16 223 #define MAX_NAREG 64 224 #define MAX_NINTERRUPT 32 225 #define MAX_NLEVEL 6 226 #define MAX_NNMI 1 227 #define MAX_NCCOMPARE 3 228 #define MAX_TLB_WAY_SIZE 8 229 #define MAX_NDBREAK 2 230 #define MAX_NMEMORY 4 231 #define MAX_MPU_FOREGROUND_SEGMENTS 32 232 233 #define REGION_PAGE_MASK 0xe0000000 234 235 #define PAGE_CACHE_MASK 0x700 236 #define PAGE_CACHE_SHIFT 8 237 #define PAGE_CACHE_INVALID 0x000 238 #define PAGE_CACHE_BYPASS 0x100 239 #define PAGE_CACHE_WT 0x200 240 #define PAGE_CACHE_WB 0x400 241 #define PAGE_CACHE_ISOLATE 0x600 242 243 enum { 244 /* Static vectors */ 245 EXC_RESET0, 246 EXC_RESET1, 247 EXC_MEMORY_ERROR, 248 249 /* Dynamic vectors */ 250 EXC_WINDOW_OVERFLOW4, 251 EXC_WINDOW_UNDERFLOW4, 252 EXC_WINDOW_OVERFLOW8, 253 EXC_WINDOW_UNDERFLOW8, 254 EXC_WINDOW_OVERFLOW12, 255 EXC_WINDOW_UNDERFLOW12, 256 EXC_IRQ, 257 EXC_KERNEL, 258 EXC_USER, 259 EXC_DOUBLE, 260 EXC_DEBUG, 261 EXC_MAX 262 }; 263 264 enum { 265 ILLEGAL_INSTRUCTION_CAUSE = 0, 266 SYSCALL_CAUSE, 267 INSTRUCTION_FETCH_ERROR_CAUSE, 268 LOAD_STORE_ERROR_CAUSE, 269 LEVEL1_INTERRUPT_CAUSE, 270 ALLOCA_CAUSE, 271 INTEGER_DIVIDE_BY_ZERO_CAUSE, 272 PC_VALUE_ERROR_CAUSE, 273 PRIVILEGED_CAUSE, 274 LOAD_STORE_ALIGNMENT_CAUSE, 275 EXTERNAL_REG_PRIVILEGE_CAUSE, 276 EXCLUSIVE_ERROR_CAUSE, 277 INSTR_PIF_DATA_ERROR_CAUSE, 278 LOAD_STORE_PIF_DATA_ERROR_CAUSE, 279 INSTR_PIF_ADDR_ERROR_CAUSE, 280 LOAD_STORE_PIF_ADDR_ERROR_CAUSE, 281 INST_TLB_MISS_CAUSE, 282 INST_TLB_MULTI_HIT_CAUSE, 283 INST_FETCH_PRIVILEGE_CAUSE, 284 INST_FETCH_PROHIBITED_CAUSE = 20, 285 LOAD_STORE_TLB_MISS_CAUSE = 24, 286 LOAD_STORE_TLB_MULTI_HIT_CAUSE, 287 LOAD_STORE_PRIVILEGE_CAUSE, 288 LOAD_PROHIBITED_CAUSE = 28, 289 STORE_PROHIBITED_CAUSE, 290 291 COPROCESSOR0_DISABLED = 32, 292 }; 293 294 typedef enum { 295 INTTYPE_LEVEL, 296 INTTYPE_EDGE, 297 INTTYPE_NMI, 298 INTTYPE_SOFTWARE, 299 INTTYPE_TIMER, 300 INTTYPE_DEBUG, 301 INTTYPE_WRITE_ERR, 302 INTTYPE_PROFILING, 303 INTTYPE_IDMA_DONE, 304 INTTYPE_IDMA_ERR, 305 INTTYPE_GS_ERR, 306 INTTYPE_MAX 307 } interrupt_type; 308 309 struct CPUXtensaState; 310 311 typedef struct xtensa_tlb_entry { 312 uint32_t vaddr; 313 uint32_t paddr; 314 uint8_t asid; 315 uint8_t attr; 316 bool variable; 317 } xtensa_tlb_entry; 318 319 typedef struct xtensa_tlb { 320 unsigned nways; 321 const unsigned way_size[10]; 322 bool varway56; 323 unsigned nrefillentries; 324 } xtensa_tlb; 325 326 typedef struct xtensa_mpu_entry { 327 uint32_t vaddr; 328 uint32_t attr; 329 } xtensa_mpu_entry; 330 331 typedef struct XtensaGdbReg { 332 int targno; 333 unsigned flags; 334 int type; 335 int group; 336 unsigned size; 337 } XtensaGdbReg; 338 339 typedef struct XtensaGdbRegmap { 340 int num_regs; 341 int num_core_regs; 342 /* PC + a + ar + sr + ur */ 343 XtensaGdbReg reg[1 + 16 + 64 + 256 + 256]; 344 } XtensaGdbRegmap; 345 346 typedef struct XtensaCcompareTimer { 347 struct CPUXtensaState *env; 348 QEMUTimer *timer; 349 } XtensaCcompareTimer; 350 351 typedef struct XtensaMemory { 352 unsigned num; 353 struct XtensaMemoryRegion { 354 uint32_t addr; 355 uint32_t size; 356 } location[MAX_NMEMORY]; 357 } XtensaMemory; 358 359 typedef struct opcode_arg { 360 uint32_t imm; 361 uint32_t raw_imm; 362 void *in; 363 void *out; 364 } OpcodeArg; 365 366 typedef struct DisasContext DisasContext; 367 typedef void (*XtensaOpcodeOp)(DisasContext *dc, const OpcodeArg arg[], 368 const uint32_t par[]); 369 typedef bool (*XtensaOpcodeBoolTest)(DisasContext *dc, 370 const OpcodeArg arg[], 371 const uint32_t par[]); 372 typedef uint32_t (*XtensaOpcodeUintTest)(DisasContext *dc, 373 const OpcodeArg arg[], 374 const uint32_t par[]); 375 376 enum { 377 XTENSA_OP_ILL = 0x1, 378 XTENSA_OP_PRIVILEGED = 0x2, 379 XTENSA_OP_SYSCALL = 0x4, 380 XTENSA_OP_DEBUG_BREAK = 0x8, 381 382 XTENSA_OP_OVERFLOW = 0x10, 383 XTENSA_OP_UNDERFLOW = 0x20, 384 XTENSA_OP_ALLOCA = 0x40, 385 XTENSA_OP_COPROCESSOR = 0x80, 386 387 XTENSA_OP_DIVIDE_BY_ZERO = 0x100, 388 389 /* Postprocessing flags */ 390 XTENSA_OP_CHECK_INTERRUPTS = 0x200, 391 XTENSA_OP_EXIT_TB_M1 = 0x400, 392 XTENSA_OP_EXIT_TB_0 = 0x800, 393 XTENSA_OP_SYNC_REGISTER_WINDOW = 0x1000, 394 395 XTENSA_OP_POSTPROCESS = 396 XTENSA_OP_CHECK_INTERRUPTS | 397 XTENSA_OP_EXIT_TB_M1 | 398 XTENSA_OP_EXIT_TB_0 | 399 XTENSA_OP_SYNC_REGISTER_WINDOW, 400 401 XTENSA_OP_NAME_ARRAY = 0x8000, 402 403 XTENSA_OP_CONTROL_FLOW = 0x10000, 404 XTENSA_OP_STORE = 0x20000, 405 XTENSA_OP_LOAD = 0x40000, 406 XTENSA_OP_LOAD_STORE = 407 XTENSA_OP_LOAD | XTENSA_OP_STORE, 408 }; 409 410 typedef struct XtensaOpcodeOps { 411 const void *name; 412 XtensaOpcodeOp translate; 413 XtensaOpcodeBoolTest test_ill; 414 XtensaOpcodeUintTest test_overflow; 415 const uint32_t *par; 416 uint32_t op_flags; 417 uint32_t coprocessor; 418 } XtensaOpcodeOps; 419 420 typedef struct XtensaOpcodeTranslators { 421 unsigned num_opcodes; 422 const XtensaOpcodeOps *opcode; 423 } XtensaOpcodeTranslators; 424 425 extern const XtensaOpcodeTranslators xtensa_core_opcodes; 426 extern const XtensaOpcodeTranslators xtensa_fpu2000_opcodes; 427 428 struct XtensaConfig { 429 const char *name; 430 uint64_t options; 431 XtensaGdbRegmap gdb_regmap; 432 unsigned nareg; 433 int excm_level; 434 int ndepc; 435 unsigned inst_fetch_width; 436 unsigned max_insn_size; 437 uint32_t vecbase; 438 uint32_t exception_vector[EXC_MAX]; 439 unsigned ninterrupt; 440 unsigned nlevel; 441 uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1]; 442 uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1]; 443 uint32_t inttype_mask[INTTYPE_MAX]; 444 struct { 445 uint32_t level; 446 interrupt_type inttype; 447 } interrupt[MAX_NINTERRUPT]; 448 unsigned nccompare; 449 uint32_t timerint[MAX_NCCOMPARE]; 450 unsigned nextint; 451 unsigned extint[MAX_NINTERRUPT]; 452 453 unsigned debug_level; 454 unsigned nibreak; 455 unsigned ndbreak; 456 457 unsigned icache_ways; 458 unsigned dcache_ways; 459 unsigned dcache_line_bytes; 460 uint32_t memctl_mask; 461 462 XtensaMemory instrom; 463 XtensaMemory instram; 464 XtensaMemory datarom; 465 XtensaMemory dataram; 466 XtensaMemory sysrom; 467 XtensaMemory sysram; 468 469 uint32_t configid[2]; 470 471 void *isa_internal; 472 xtensa_isa isa; 473 XtensaOpcodeOps **opcode_ops; 474 const XtensaOpcodeTranslators **opcode_translators; 475 xtensa_regfile a_regfile; 476 void ***regfile; 477 478 uint32_t clock_freq_khz; 479 480 xtensa_tlb itlb; 481 xtensa_tlb dtlb; 482 483 uint32_t mpu_align; 484 unsigned n_mpu_fg_segments; 485 unsigned n_mpu_bg_segments; 486 const xtensa_mpu_entry *mpu_bg; 487 }; 488 489 typedef struct XtensaConfigList { 490 const XtensaConfig *config; 491 struct XtensaConfigList *next; 492 } XtensaConfigList; 493 494 #ifdef HOST_WORDS_BIGENDIAN 495 enum { 496 FP_F32_HIGH, 497 FP_F32_LOW, 498 }; 499 #else 500 enum { 501 FP_F32_LOW, 502 FP_F32_HIGH, 503 }; 504 #endif 505 506 typedef struct CPUXtensaState { 507 const XtensaConfig *config; 508 uint32_t regs[16]; 509 uint32_t pc; 510 uint32_t sregs[256]; 511 uint32_t uregs[256]; 512 uint32_t phys_regs[MAX_NAREG]; 513 union { 514 float32 f32[2]; 515 float64 f64; 516 } fregs[16]; 517 float_status fp_status; 518 uint32_t windowbase_next; 519 uint32_t exclusive_addr; 520 uint32_t exclusive_val; 521 522 #ifndef CONFIG_USER_ONLY 523 xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE]; 524 xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE]; 525 xtensa_mpu_entry mpu_fg[MAX_MPU_FOREGROUND_SEGMENTS]; 526 unsigned autorefill_idx; 527 bool runstall; 528 AddressSpace *address_space_er; 529 MemoryRegion *system_er; 530 int pending_irq_level; /* level of last raised IRQ */ 531 qemu_irq *irq_inputs; 532 qemu_irq ext_irq_inputs[MAX_NINTERRUPT]; 533 qemu_irq runstall_irq; 534 XtensaCcompareTimer ccompare[MAX_NCCOMPARE]; 535 uint64_t time_base; 536 uint64_t ccount_time; 537 uint32_t ccount_base; 538 #endif 539 540 int exception_taken; 541 int yield_needed; 542 unsigned static_vectors; 543 544 /* Watchpoints for DBREAK registers */ 545 struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK]; 546 547 CPU_COMMON 548 } CPUXtensaState; 549 550 /** 551 * XtensaCPU: 552 * @env: #CPUXtensaState 553 * 554 * An Xtensa CPU. 555 */ 556 struct XtensaCPU { 557 /*< private >*/ 558 CPUState parent_obj; 559 /*< public >*/ 560 561 CPUXtensaState env; 562 }; 563 564 static inline XtensaCPU *xtensa_env_get_cpu(const CPUXtensaState *env) 565 { 566 return container_of(env, XtensaCPU, env); 567 } 568 569 #define ENV_GET_CPU(e) CPU(xtensa_env_get_cpu(e)) 570 571 #define ENV_OFFSET offsetof(XtensaCPU, env) 572 573 574 bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 575 MMUAccessType access_type, int mmu_idx, 576 bool probe, uintptr_t retaddr); 577 void xtensa_cpu_do_interrupt(CPUState *cpu); 578 bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request); 579 void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, 580 unsigned size, MMUAccessType access_type, 581 int mmu_idx, MemTxAttrs attrs, 582 MemTxResult response, uintptr_t retaddr); 583 void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, int flags); 584 hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 585 void xtensa_count_regs(const XtensaConfig *config, 586 unsigned *n_regs, unsigned *n_core_regs); 587 int xtensa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 588 int xtensa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 589 void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, 590 MMUAccessType access_type, 591 int mmu_idx, uintptr_t retaddr); 592 593 #define cpu_signal_handler cpu_xtensa_signal_handler 594 #define cpu_list xtensa_cpu_list 595 596 #define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU 597 #define XTENSA_CPU_TYPE_NAME(model) model XTENSA_CPU_TYPE_SUFFIX 598 #define CPU_RESOLVING_TYPE TYPE_XTENSA_CPU 599 600 #ifdef TARGET_WORDS_BIGENDIAN 601 #define XTENSA_DEFAULT_CPU_MODEL "fsf" 602 #define XTENSA_DEFAULT_CPU_NOMMU_MODEL "fsf" 603 #else 604 #define XTENSA_DEFAULT_CPU_MODEL "dc232b" 605 #define XTENSA_DEFAULT_CPU_NOMMU_MODEL "de212" 606 #endif 607 #define XTENSA_DEFAULT_CPU_TYPE \ 608 XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_MODEL) 609 #define XTENSA_DEFAULT_CPU_NOMMU_TYPE \ 610 XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_NOMMU_MODEL) 611 612 void xtensa_collect_sr_names(const XtensaConfig *config); 613 void xtensa_translate_init(void); 614 void **xtensa_get_regfile_by_name(const char *name); 615 void xtensa_breakpoint_handler(CPUState *cs); 616 void xtensa_register_core(XtensaConfigList *node); 617 void xtensa_sim_open_console(Chardev *chr); 618 void check_interrupts(CPUXtensaState *s); 619 void xtensa_irq_init(CPUXtensaState *env); 620 qemu_irq *xtensa_get_extints(CPUXtensaState *env); 621 qemu_irq xtensa_get_runstall(CPUXtensaState *env); 622 int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc); 623 void xtensa_cpu_list(void); 624 void xtensa_sync_window_from_phys(CPUXtensaState *env); 625 void xtensa_sync_phys_from_window(CPUXtensaState *env); 626 void xtensa_rotate_window(CPUXtensaState *env, uint32_t delta); 627 void xtensa_restore_owb(CPUXtensaState *env); 628 void debug_exception_env(CPUXtensaState *new_env, uint32_t cause); 629 630 static inline void xtensa_select_static_vectors(CPUXtensaState *env, 631 unsigned n) 632 { 633 assert(n < 2); 634 env->static_vectors = n; 635 } 636 void xtensa_runstall(CPUXtensaState *env, bool runstall); 637 638 #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt)) 639 #define XTENSA_OPTION_ALL (~(uint64_t)0) 640 641 static inline bool xtensa_option_bits_enabled(const XtensaConfig *config, 642 uint64_t opt) 643 { 644 return (config->options & opt) != 0; 645 } 646 647 static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt) 648 { 649 return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt)); 650 } 651 652 static inline int xtensa_get_cintlevel(const CPUXtensaState *env) 653 { 654 int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT; 655 if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) { 656 level = env->config->excm_level; 657 } 658 return level; 659 } 660 661 static inline int xtensa_get_ring(const CPUXtensaState *env) 662 { 663 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 664 return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT; 665 } else { 666 return 0; 667 } 668 } 669 670 static inline int xtensa_get_cring(const CPUXtensaState *env) 671 { 672 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) && 673 (env->sregs[PS] & PS_EXCM) == 0) { 674 return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT; 675 } else { 676 return 0; 677 } 678 } 679 680 #ifndef CONFIG_USER_ONLY 681 int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb, 682 uint32_t vaddr, int is_write, int mmu_idx, 683 uint32_t *paddr, uint32_t *page_size, unsigned *access); 684 void reset_mmu(CPUXtensaState *env); 685 void dump_mmu(CPUXtensaState *env); 686 687 static inline MemoryRegion *xtensa_get_er_region(CPUXtensaState *env) 688 { 689 return env->system_er; 690 } 691 #endif 692 693 static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env) 694 { 695 return env->sregs[WINDOW_START] | 696 (env->sregs[WINDOW_START] << env->config->nareg / 4); 697 } 698 699 /* MMU modes definitions */ 700 #define MMU_MODE0_SUFFIX _ring0 701 #define MMU_MODE1_SUFFIX _ring1 702 #define MMU_MODE2_SUFFIX _ring2 703 #define MMU_MODE3_SUFFIX _ring3 704 #define MMU_USER_IDX 3 705 706 static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch) 707 { 708 return xtensa_get_cring(env); 709 } 710 711 #define XTENSA_TBFLAG_RING_MASK 0x3 712 #define XTENSA_TBFLAG_EXCM 0x4 713 #define XTENSA_TBFLAG_LITBASE 0x8 714 #define XTENSA_TBFLAG_DEBUG 0x10 715 #define XTENSA_TBFLAG_ICOUNT 0x20 716 #define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0 717 #define XTENSA_TBFLAG_CPENABLE_SHIFT 6 718 #define XTENSA_TBFLAG_EXCEPTION 0x4000 719 #define XTENSA_TBFLAG_WINDOW_MASK 0x18000 720 #define XTENSA_TBFLAG_WINDOW_SHIFT 15 721 #define XTENSA_TBFLAG_YIELD 0x20000 722 #define XTENSA_TBFLAG_CWOE 0x40000 723 #define XTENSA_TBFLAG_CALLINC_MASK 0x180000 724 #define XTENSA_TBFLAG_CALLINC_SHIFT 19 725 726 #define XTENSA_CSBASE_LEND_MASK 0x0000ffff 727 #define XTENSA_CSBASE_LEND_SHIFT 0 728 #define XTENSA_CSBASE_LBEG_OFF_MASK 0x00ff0000 729 #define XTENSA_CSBASE_LBEG_OFF_SHIFT 16 730 731 static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc, 732 target_ulong *cs_base, uint32_t *flags) 733 { 734 CPUState *cs = CPU(xtensa_env_get_cpu(env)); 735 736 *pc = env->pc; 737 *cs_base = 0; 738 *flags = 0; 739 *flags |= xtensa_get_ring(env); 740 if (env->sregs[PS] & PS_EXCM) { 741 *flags |= XTENSA_TBFLAG_EXCM; 742 } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) { 743 target_ulong lend_dist = 744 env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS)); 745 746 /* 747 * 0 in the csbase_lend field means that there may not be a loopback 748 * for any instruction that starts inside this page. Any other value 749 * means that an instruction that ends at this offset from the page 750 * start may loop back and will need loopback code to be generated. 751 * 752 * lend_dist is 0 when LEND points to the start of the page, but 753 * no instruction that starts inside this page may end at offset 0, 754 * so it's still correct. 755 * 756 * When an instruction ends at a page boundary it may only start in 757 * the previous page. lend_dist will be encoded as TARGET_PAGE_SIZE 758 * for the TB that contains this instruction. 759 */ 760 if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_size) { 761 target_ulong lbeg_off = env->sregs[LEND] - env->sregs[LBEG]; 762 763 *cs_base = lend_dist; 764 if (lbeg_off < 256) { 765 *cs_base |= lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT; 766 } 767 } 768 } 769 if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) && 770 (env->sregs[LITBASE] & 1)) { 771 *flags |= XTENSA_TBFLAG_LITBASE; 772 } 773 if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) { 774 if (xtensa_get_cintlevel(env) < env->config->debug_level) { 775 *flags |= XTENSA_TBFLAG_DEBUG; 776 } 777 if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) { 778 *flags |= XTENSA_TBFLAG_ICOUNT; 779 } 780 } 781 if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) { 782 *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT; 783 } 784 if (cs->singlestep_enabled && env->exception_taken) { 785 *flags |= XTENSA_TBFLAG_EXCEPTION; 786 } 787 if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) && 788 (env->sregs[PS] & (PS_WOE | PS_EXCM)) == PS_WOE) { 789 uint32_t windowstart = xtensa_replicate_windowstart(env) >> 790 (env->sregs[WINDOW_BASE] + 1); 791 uint32_t w = ctz32(windowstart | 0x8); 792 793 *flags |= (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE; 794 *flags |= extract32(env->sregs[PS], PS_CALLINC_SHIFT, 795 PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT; 796 } else { 797 *flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT; 798 } 799 if (env->yield_needed) { 800 *flags |= XTENSA_TBFLAG_YIELD; 801 } 802 } 803 804 #include "exec/cpu-all.h" 805 806 #endif 807