1 /* 2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * * Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * * Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * * Neither the name of the Open Source and Linux Lab nor the 13 * names of its contributors may be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #ifndef XTENSA_CPU_H 29 #define XTENSA_CPU_H 30 31 #include "cpu-qom.h" 32 #include "qemu/cpu-float.h" 33 #include "exec/cpu-defs.h" 34 #include "xtensa-isa.h" 35 36 /* Xtensa processors have a weak memory model */ 37 #define TCG_GUEST_DEFAULT_MO (0) 38 39 enum { 40 /* Additional instructions */ 41 XTENSA_OPTION_CODE_DENSITY, 42 XTENSA_OPTION_LOOP, 43 XTENSA_OPTION_EXTENDED_L32R, 44 XTENSA_OPTION_16_BIT_IMUL, 45 XTENSA_OPTION_32_BIT_IMUL, 46 XTENSA_OPTION_32_BIT_IMUL_HIGH, 47 XTENSA_OPTION_32_BIT_IDIV, 48 XTENSA_OPTION_MAC16, 49 XTENSA_OPTION_MISC_OP_NSA, 50 XTENSA_OPTION_MISC_OP_MINMAX, 51 XTENSA_OPTION_MISC_OP_SEXT, 52 XTENSA_OPTION_MISC_OP_CLAMPS, 53 XTENSA_OPTION_COPROCESSOR, 54 XTENSA_OPTION_BOOLEAN, 55 XTENSA_OPTION_FP_COPROCESSOR, 56 XTENSA_OPTION_DFP_COPROCESSOR, 57 XTENSA_OPTION_DFPU_SINGLE_ONLY, 58 XTENSA_OPTION_MP_SYNCHRO, 59 XTENSA_OPTION_CONDITIONAL_STORE, 60 XTENSA_OPTION_ATOMCTL, 61 XTENSA_OPTION_DEPBITS, 62 63 /* Interrupts and exceptions */ 64 XTENSA_OPTION_EXCEPTION, 65 XTENSA_OPTION_RELOCATABLE_VECTOR, 66 XTENSA_OPTION_UNALIGNED_EXCEPTION, 67 XTENSA_OPTION_INTERRUPT, 68 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 69 XTENSA_OPTION_TIMER_INTERRUPT, 70 71 /* Local memory */ 72 XTENSA_OPTION_ICACHE, 73 XTENSA_OPTION_ICACHE_TEST, 74 XTENSA_OPTION_ICACHE_INDEX_LOCK, 75 XTENSA_OPTION_DCACHE, 76 XTENSA_OPTION_DCACHE_TEST, 77 XTENSA_OPTION_DCACHE_INDEX_LOCK, 78 XTENSA_OPTION_IRAM, 79 XTENSA_OPTION_IROM, 80 XTENSA_OPTION_DRAM, 81 XTENSA_OPTION_DROM, 82 XTENSA_OPTION_XLMI, 83 XTENSA_OPTION_HW_ALIGNMENT, 84 XTENSA_OPTION_MEMORY_ECC_PARITY, 85 86 /* Memory protection and translation */ 87 XTENSA_OPTION_REGION_PROTECTION, 88 XTENSA_OPTION_REGION_TRANSLATION, 89 XTENSA_OPTION_MPU, 90 XTENSA_OPTION_MMU, 91 XTENSA_OPTION_CACHEATTR, 92 93 /* Other */ 94 XTENSA_OPTION_WINDOWED_REGISTER, 95 XTENSA_OPTION_PROCESSOR_INTERFACE, 96 XTENSA_OPTION_MISC_SR, 97 XTENSA_OPTION_THREAD_POINTER, 98 XTENSA_OPTION_PROCESSOR_ID, 99 XTENSA_OPTION_DEBUG, 100 XTENSA_OPTION_TRACE_PORT, 101 XTENSA_OPTION_EXTERN_REGS, 102 }; 103 104 enum { 105 EXPSTATE = 230, 106 THREADPTR = 231, 107 FCR = 232, 108 FSR = 233, 109 }; 110 111 enum { 112 LBEG = 0, 113 LEND = 1, 114 LCOUNT = 2, 115 SAR = 3, 116 BR = 4, 117 LITBASE = 5, 118 SCOMPARE1 = 12, 119 ACCLO = 16, 120 ACCHI = 17, 121 MR = 32, 122 PREFCTL = 40, 123 WINDOW_BASE = 72, 124 WINDOW_START = 73, 125 PTEVADDR = 83, 126 MMID = 89, 127 RASID = 90, 128 MPUENB = 90, 129 ITLBCFG = 91, 130 DTLBCFG = 92, 131 MPUCFG = 92, 132 ERACCESS = 95, 133 IBREAKENABLE = 96, 134 MEMCTL = 97, 135 CACHEATTR = 98, 136 CACHEADRDIS = 98, 137 ATOMCTL = 99, 138 DDR = 104, 139 MEPC = 106, 140 MEPS = 107, 141 MESAVE = 108, 142 MESR = 109, 143 MECR = 110, 144 MEVADDR = 111, 145 IBREAKA = 128, 146 DBREAKA = 144, 147 DBREAKC = 160, 148 CONFIGID0 = 176, 149 EPC1 = 177, 150 DEPC = 192, 151 EPS2 = 194, 152 CONFIGID1 = 208, 153 EXCSAVE1 = 209, 154 CPENABLE = 224, 155 INTSET = 226, 156 INTCLEAR = 227, 157 INTENABLE = 228, 158 PS = 230, 159 VECBASE = 231, 160 EXCCAUSE = 232, 161 DEBUGCAUSE = 233, 162 CCOUNT = 234, 163 PRID = 235, 164 ICOUNT = 236, 165 ICOUNTLEVEL = 237, 166 EXCVADDR = 238, 167 CCOMPARE = 240, 168 MISC = 244, 169 }; 170 171 #define PS_INTLEVEL 0xf 172 #define PS_INTLEVEL_SHIFT 0 173 174 #define PS_EXCM 0x10 175 #define PS_UM 0x20 176 177 #define PS_RING 0xc0 178 #define PS_RING_SHIFT 6 179 180 #define PS_OWB 0xf00 181 #define PS_OWB_SHIFT 8 182 #define PS_OWB_LEN 4 183 184 #define PS_CALLINC 0x30000 185 #define PS_CALLINC_SHIFT 16 186 #define PS_CALLINC_LEN 2 187 188 #define PS_WOE 0x40000 189 190 #define DEBUGCAUSE_IC 0x1 191 #define DEBUGCAUSE_IB 0x2 192 #define DEBUGCAUSE_DB 0x4 193 #define DEBUGCAUSE_BI 0x8 194 #define DEBUGCAUSE_BN 0x10 195 #define DEBUGCAUSE_DI 0x20 196 #define DEBUGCAUSE_DBNUM 0xf00 197 #define DEBUGCAUSE_DBNUM_SHIFT 8 198 199 #define DBREAKC_SB 0x80000000 200 #define DBREAKC_LB 0x40000000 201 #define DBREAKC_SB_LB (DBREAKC_SB | DBREAKC_LB) 202 #define DBREAKC_MASK 0x3f 203 204 #define MEMCTL_INIT 0x00800000 205 #define MEMCTL_IUSEWAYS_SHIFT 18 206 #define MEMCTL_IUSEWAYS_LEN 5 207 #define MEMCTL_IUSEWAYS_MASK 0x007c0000 208 #define MEMCTL_DALLOCWAYS_SHIFT 13 209 #define MEMCTL_DALLOCWAYS_LEN 5 210 #define MEMCTL_DALLOCWAYS_MASK 0x0003e000 211 #define MEMCTL_DUSEWAYS_SHIFT 8 212 #define MEMCTL_DUSEWAYS_LEN 5 213 #define MEMCTL_DUSEWAYS_MASK 0x00001f00 214 #define MEMCTL_ISNP 0x4 215 #define MEMCTL_DSNP 0x2 216 #define MEMCTL_IL0EN 0x1 217 218 #define MAX_INSN_LENGTH 64 219 #define MAX_INSNBUF_LENGTH \ 220 ((MAX_INSN_LENGTH + sizeof(xtensa_insnbuf_word) - 1) / \ 221 sizeof(xtensa_insnbuf_word)) 222 #define MAX_INSN_SLOTS 32 223 #define MAX_OPCODE_ARGS 16 224 #define MAX_NAREG 64 225 #define MAX_NINTERRUPT 32 226 #define MAX_NLEVEL 6 227 #define MAX_NNMI 1 228 #define MAX_NCCOMPARE 3 229 #define MAX_TLB_WAY_SIZE 8 230 #define MAX_NDBREAK 2 231 #define MAX_NMEMORY 4 232 #define MAX_MPU_FOREGROUND_SEGMENTS 32 233 234 #define REGION_PAGE_MASK 0xe0000000 235 236 #define PAGE_CACHE_MASK 0x700 237 #define PAGE_CACHE_SHIFT 8 238 #define PAGE_CACHE_INVALID 0x000 239 #define PAGE_CACHE_BYPASS 0x100 240 #define PAGE_CACHE_WT 0x200 241 #define PAGE_CACHE_WB 0x400 242 #define PAGE_CACHE_ISOLATE 0x600 243 244 enum { 245 /* Static vectors */ 246 EXC_RESET0, 247 EXC_RESET1, 248 EXC_MEMORY_ERROR, 249 250 /* Dynamic vectors */ 251 EXC_WINDOW_OVERFLOW4, 252 EXC_WINDOW_UNDERFLOW4, 253 EXC_WINDOW_OVERFLOW8, 254 EXC_WINDOW_UNDERFLOW8, 255 EXC_WINDOW_OVERFLOW12, 256 EXC_WINDOW_UNDERFLOW12, 257 EXC_IRQ, 258 EXC_KERNEL, 259 EXC_USER, 260 EXC_DOUBLE, 261 EXC_DEBUG, 262 EXC_MAX 263 }; 264 265 enum { 266 ILLEGAL_INSTRUCTION_CAUSE = 0, 267 SYSCALL_CAUSE, 268 INSTRUCTION_FETCH_ERROR_CAUSE, 269 LOAD_STORE_ERROR_CAUSE, 270 LEVEL1_INTERRUPT_CAUSE, 271 ALLOCA_CAUSE, 272 INTEGER_DIVIDE_BY_ZERO_CAUSE, 273 PC_VALUE_ERROR_CAUSE, 274 PRIVILEGED_CAUSE, 275 LOAD_STORE_ALIGNMENT_CAUSE, 276 EXTERNAL_REG_PRIVILEGE_CAUSE, 277 EXCLUSIVE_ERROR_CAUSE, 278 INSTR_PIF_DATA_ERROR_CAUSE, 279 LOAD_STORE_PIF_DATA_ERROR_CAUSE, 280 INSTR_PIF_ADDR_ERROR_CAUSE, 281 LOAD_STORE_PIF_ADDR_ERROR_CAUSE, 282 INST_TLB_MISS_CAUSE, 283 INST_TLB_MULTI_HIT_CAUSE, 284 INST_FETCH_PRIVILEGE_CAUSE, 285 INST_FETCH_PROHIBITED_CAUSE = 20, 286 LOAD_STORE_TLB_MISS_CAUSE = 24, 287 LOAD_STORE_TLB_MULTI_HIT_CAUSE, 288 LOAD_STORE_PRIVILEGE_CAUSE, 289 LOAD_PROHIBITED_CAUSE = 28, 290 STORE_PROHIBITED_CAUSE, 291 292 COPROCESSOR0_DISABLED = 32, 293 }; 294 295 typedef enum { 296 INTTYPE_LEVEL, 297 INTTYPE_EDGE, 298 INTTYPE_NMI, 299 INTTYPE_SOFTWARE, 300 INTTYPE_TIMER, 301 INTTYPE_DEBUG, 302 INTTYPE_WRITE_ERR, 303 INTTYPE_PROFILING, 304 INTTYPE_IDMA_DONE, 305 INTTYPE_IDMA_ERR, 306 INTTYPE_GS_ERR, 307 INTTYPE_MAX 308 } interrupt_type; 309 310 typedef struct CPUArchState CPUXtensaState; 311 312 typedef struct xtensa_tlb_entry { 313 uint32_t vaddr; 314 uint32_t paddr; 315 uint8_t asid; 316 uint8_t attr; 317 bool variable; 318 } xtensa_tlb_entry; 319 320 typedef struct xtensa_tlb { 321 unsigned nways; 322 const unsigned way_size[10]; 323 bool varway56; 324 unsigned nrefillentries; 325 } xtensa_tlb; 326 327 typedef struct xtensa_mpu_entry { 328 uint32_t vaddr; 329 uint32_t attr; 330 } xtensa_mpu_entry; 331 332 typedef struct XtensaGdbReg { 333 int targno; 334 unsigned flags; 335 int type; 336 int group; 337 unsigned size; 338 } XtensaGdbReg; 339 340 typedef struct XtensaGdbRegmap { 341 int num_regs; 342 int num_core_regs; 343 /* PC + a + ar + sr + ur */ 344 XtensaGdbReg reg[1 + 16 + 64 + 256 + 256]; 345 } XtensaGdbRegmap; 346 347 typedef struct XtensaCcompareTimer { 348 CPUXtensaState *env; 349 QEMUTimer *timer; 350 } XtensaCcompareTimer; 351 352 typedef struct XtensaMemory { 353 unsigned num; 354 struct XtensaMemoryRegion { 355 uint32_t addr; 356 uint32_t size; 357 } location[MAX_NMEMORY]; 358 } XtensaMemory; 359 360 typedef struct opcode_arg { 361 uint32_t imm; 362 uint32_t raw_imm; 363 void *in; 364 void *out; 365 uint32_t num_bits; 366 } OpcodeArg; 367 368 typedef struct DisasContext DisasContext; 369 typedef void (*XtensaOpcodeOp)(DisasContext *dc, const OpcodeArg arg[], 370 const uint32_t par[]); 371 typedef uint32_t (*XtensaOpcodeUintTest)(DisasContext *dc, 372 const OpcodeArg arg[], 373 const uint32_t par[]); 374 375 enum { 376 XTENSA_OP_ILL = 0x1, 377 XTENSA_OP_PRIVILEGED = 0x2, 378 XTENSA_OP_SYSCALL = 0x4, 379 XTENSA_OP_DEBUG_BREAK = 0x8, 380 381 XTENSA_OP_OVERFLOW = 0x10, 382 XTENSA_OP_UNDERFLOW = 0x20, 383 XTENSA_OP_ALLOCA = 0x40, 384 XTENSA_OP_COPROCESSOR = 0x80, 385 386 XTENSA_OP_DIVIDE_BY_ZERO = 0x100, 387 388 /* Postprocessing flags */ 389 XTENSA_OP_CHECK_INTERRUPTS = 0x200, 390 XTENSA_OP_EXIT_TB_M1 = 0x400, 391 XTENSA_OP_EXIT_TB_0 = 0x800, 392 XTENSA_OP_SYNC_REGISTER_WINDOW = 0x1000, 393 394 XTENSA_OP_POSTPROCESS = 395 XTENSA_OP_CHECK_INTERRUPTS | 396 XTENSA_OP_EXIT_TB_M1 | 397 XTENSA_OP_EXIT_TB_0 | 398 XTENSA_OP_SYNC_REGISTER_WINDOW, 399 400 XTENSA_OP_NAME_ARRAY = 0x8000, 401 402 XTENSA_OP_CONTROL_FLOW = 0x10000, 403 XTENSA_OP_STORE = 0x20000, 404 XTENSA_OP_LOAD = 0x40000, 405 XTENSA_OP_LOAD_STORE = 406 XTENSA_OP_LOAD | XTENSA_OP_STORE, 407 }; 408 409 typedef struct XtensaOpcodeOps { 410 const void *name; 411 XtensaOpcodeOp translate; 412 XtensaOpcodeUintTest test_exceptions; 413 XtensaOpcodeUintTest test_overflow; 414 const uint32_t *par; 415 uint32_t op_flags; 416 uint32_t coprocessor; 417 } XtensaOpcodeOps; 418 419 typedef struct XtensaOpcodeTranslators { 420 unsigned num_opcodes; 421 const XtensaOpcodeOps *opcode; 422 } XtensaOpcodeTranslators; 423 424 extern const XtensaOpcodeTranslators xtensa_core_opcodes; 425 extern const XtensaOpcodeTranslators xtensa_fpu2000_opcodes; 426 extern const XtensaOpcodeTranslators xtensa_fpu_opcodes; 427 428 struct XtensaConfig { 429 const char *name; 430 uint64_t options; 431 XtensaGdbRegmap gdb_regmap; 432 unsigned nareg; 433 int excm_level; 434 int ndepc; 435 unsigned inst_fetch_width; 436 unsigned max_insn_size; 437 uint32_t vecbase; 438 uint32_t exception_vector[EXC_MAX]; 439 unsigned ninterrupt; 440 unsigned nlevel; 441 unsigned nmi_level; 442 uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1]; 443 uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1]; 444 uint32_t inttype_mask[INTTYPE_MAX]; 445 struct { 446 uint32_t level; 447 interrupt_type inttype; 448 } interrupt[MAX_NINTERRUPT]; 449 unsigned nccompare; 450 uint32_t timerint[MAX_NCCOMPARE]; 451 unsigned nextint; 452 unsigned extint[MAX_NINTERRUPT]; 453 454 unsigned debug_level; 455 unsigned nibreak; 456 unsigned ndbreak; 457 458 unsigned icache_ways; 459 unsigned dcache_ways; 460 unsigned dcache_line_bytes; 461 uint32_t memctl_mask; 462 463 XtensaMemory instrom; 464 XtensaMemory instram; 465 XtensaMemory datarom; 466 XtensaMemory dataram; 467 XtensaMemory sysrom; 468 XtensaMemory sysram; 469 470 unsigned hw_version; 471 uint32_t configid[2]; 472 473 void *isa_internal; 474 xtensa_isa isa; 475 XtensaOpcodeOps **opcode_ops; 476 const XtensaOpcodeTranslators **opcode_translators; 477 xtensa_regfile a_regfile; 478 void ***regfile; 479 480 uint32_t clock_freq_khz; 481 482 xtensa_tlb itlb; 483 xtensa_tlb dtlb; 484 485 uint32_t mpu_align; 486 unsigned n_mpu_fg_segments; 487 unsigned n_mpu_bg_segments; 488 const xtensa_mpu_entry *mpu_bg; 489 490 bool use_first_nan; 491 }; 492 493 typedef struct XtensaConfigList { 494 const XtensaConfig *config; 495 struct XtensaConfigList *next; 496 } XtensaConfigList; 497 498 #if HOST_BIG_ENDIAN 499 enum { 500 FP_F32_HIGH, 501 FP_F32_LOW, 502 }; 503 #else 504 enum { 505 FP_F32_LOW, 506 FP_F32_HIGH, 507 }; 508 #endif 509 510 struct CPUArchState { 511 const XtensaConfig *config; 512 uint32_t regs[16]; 513 uint32_t pc; 514 uint32_t sregs[256]; 515 uint32_t uregs[256]; 516 uint32_t phys_regs[MAX_NAREG]; 517 union { 518 float32 f32[2]; 519 float64 f64; 520 } fregs[16]; 521 float_status fp_status; 522 uint32_t windowbase_next; 523 uint32_t exclusive_addr; 524 uint32_t exclusive_val; 525 526 #ifndef CONFIG_USER_ONLY 527 xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE]; 528 xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE]; 529 xtensa_mpu_entry mpu_fg[MAX_MPU_FOREGROUND_SEGMENTS]; 530 unsigned autorefill_idx; 531 bool runstall; 532 AddressSpace *address_space_er; 533 MemoryRegion *system_er; 534 int pending_irq_level; /* level of last raised IRQ */ 535 qemu_irq *irq_inputs; 536 qemu_irq ext_irq_inputs[MAX_NINTERRUPT]; 537 qemu_irq runstall_irq; 538 XtensaCcompareTimer ccompare[MAX_NCCOMPARE]; 539 uint64_t time_base; 540 uint64_t ccount_time; 541 uint32_t ccount_base; 542 #endif 543 544 int yield_needed; 545 unsigned static_vectors; 546 547 /* Watchpoints for DBREAK registers */ 548 struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK]; 549 }; 550 551 /** 552 * XtensaCPU: 553 * @env: #CPUXtensaState 554 * 555 * An Xtensa CPU. 556 */ 557 struct ArchCPU { 558 /*< private >*/ 559 CPUState parent_obj; 560 /*< public >*/ 561 562 CPUNegativeOffsetState neg; 563 CPUXtensaState env; 564 }; 565 566 567 #ifndef CONFIG_USER_ONLY 568 bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 569 MMUAccessType access_type, int mmu_idx, 570 bool probe, uintptr_t retaddr); 571 void xtensa_cpu_do_interrupt(CPUState *cpu); 572 bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request); 573 void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, 574 unsigned size, MMUAccessType access_type, 575 int mmu_idx, MemTxAttrs attrs, 576 MemTxResult response, uintptr_t retaddr); 577 #endif 578 void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, int flags); 579 hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 580 void xtensa_count_regs(const XtensaConfig *config, 581 unsigned *n_regs, unsigned *n_core_regs); 582 int xtensa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 583 int xtensa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 584 void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, 585 MMUAccessType access_type, int mmu_idx, 586 uintptr_t retaddr) QEMU_NORETURN; 587 588 #define cpu_list xtensa_cpu_list 589 590 #define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU 591 #define XTENSA_CPU_TYPE_NAME(model) model XTENSA_CPU_TYPE_SUFFIX 592 #define CPU_RESOLVING_TYPE TYPE_XTENSA_CPU 593 594 #if TARGET_BIG_ENDIAN 595 #define XTENSA_DEFAULT_CPU_MODEL "fsf" 596 #define XTENSA_DEFAULT_CPU_NOMMU_MODEL "fsf" 597 #else 598 #define XTENSA_DEFAULT_CPU_MODEL "dc232b" 599 #define XTENSA_DEFAULT_CPU_NOMMU_MODEL "de212" 600 #endif 601 #define XTENSA_DEFAULT_CPU_TYPE \ 602 XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_MODEL) 603 #define XTENSA_DEFAULT_CPU_NOMMU_TYPE \ 604 XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_NOMMU_MODEL) 605 606 void xtensa_collect_sr_names(const XtensaConfig *config); 607 void xtensa_translate_init(void); 608 void **xtensa_get_regfile_by_name(const char *name, int entries, int bits); 609 void xtensa_breakpoint_handler(CPUState *cs); 610 void xtensa_register_core(XtensaConfigList *node); 611 void xtensa_sim_open_console(Chardev *chr); 612 void check_interrupts(CPUXtensaState *s); 613 void xtensa_irq_init(CPUXtensaState *env); 614 qemu_irq *xtensa_get_extints(CPUXtensaState *env); 615 qemu_irq xtensa_get_runstall(CPUXtensaState *env); 616 void xtensa_cpu_list(void); 617 void xtensa_sync_window_from_phys(CPUXtensaState *env); 618 void xtensa_sync_phys_from_window(CPUXtensaState *env); 619 void xtensa_rotate_window(CPUXtensaState *env, uint32_t delta); 620 void xtensa_restore_owb(CPUXtensaState *env); 621 void debug_exception_env(CPUXtensaState *new_env, uint32_t cause); 622 623 static inline void xtensa_select_static_vectors(CPUXtensaState *env, 624 unsigned n) 625 { 626 assert(n < 2); 627 env->static_vectors = n; 628 } 629 void xtensa_runstall(CPUXtensaState *env, bool runstall); 630 631 #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt)) 632 #define XTENSA_OPTION_ALL (~(uint64_t)0) 633 634 static inline bool xtensa_option_bits_enabled(const XtensaConfig *config, 635 uint64_t opt) 636 { 637 return (config->options & opt) != 0; 638 } 639 640 static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt) 641 { 642 return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt)); 643 } 644 645 static inline int xtensa_get_cintlevel(const CPUXtensaState *env) 646 { 647 int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT; 648 if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) { 649 level = env->config->excm_level; 650 } 651 return level; 652 } 653 654 static inline int xtensa_get_ring(const CPUXtensaState *env) 655 { 656 if (xtensa_option_bits_enabled(env->config, 657 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU) | 658 XTENSA_OPTION_BIT(XTENSA_OPTION_MPU))) { 659 return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT; 660 } else { 661 return 0; 662 } 663 } 664 665 static inline int xtensa_get_cring(const CPUXtensaState *env) 666 { 667 if (xtensa_option_bits_enabled(env->config, 668 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU) | 669 XTENSA_OPTION_BIT(XTENSA_OPTION_MPU)) && 670 (env->sregs[PS] & PS_EXCM) == 0) { 671 return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT; 672 } else { 673 return 0; 674 } 675 } 676 677 #ifndef CONFIG_USER_ONLY 678 int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb, 679 uint32_t vaddr, int is_write, int mmu_idx, 680 uint32_t *paddr, uint32_t *page_size, unsigned *access); 681 void reset_mmu(CPUXtensaState *env); 682 void dump_mmu(CPUXtensaState *env); 683 684 static inline MemoryRegion *xtensa_get_er_region(CPUXtensaState *env) 685 { 686 return env->system_er; 687 } 688 #else 689 void xtensa_set_abi_call0(void); 690 bool xtensa_abi_call0(void); 691 #endif 692 693 static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env) 694 { 695 return env->sregs[WINDOW_START] | 696 (env->sregs[WINDOW_START] << env->config->nareg / 4); 697 } 698 699 /* MMU modes definitions */ 700 #define MMU_USER_IDX 3 701 702 static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch) 703 { 704 return xtensa_get_cring(env); 705 } 706 707 #define XTENSA_TBFLAG_RING_MASK 0x3 708 #define XTENSA_TBFLAG_EXCM 0x4 709 #define XTENSA_TBFLAG_LITBASE 0x8 710 #define XTENSA_TBFLAG_DEBUG 0x10 711 #define XTENSA_TBFLAG_ICOUNT 0x20 712 #define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0 713 #define XTENSA_TBFLAG_CPENABLE_SHIFT 6 714 #define XTENSA_TBFLAG_WINDOW_MASK 0x18000 715 #define XTENSA_TBFLAG_WINDOW_SHIFT 15 716 #define XTENSA_TBFLAG_YIELD 0x20000 717 #define XTENSA_TBFLAG_CWOE 0x40000 718 #define XTENSA_TBFLAG_CALLINC_MASK 0x180000 719 #define XTENSA_TBFLAG_CALLINC_SHIFT 19 720 721 #define XTENSA_CSBASE_LEND_MASK 0x0000ffff 722 #define XTENSA_CSBASE_LEND_SHIFT 0 723 #define XTENSA_CSBASE_LBEG_OFF_MASK 0x00ff0000 724 #define XTENSA_CSBASE_LBEG_OFF_SHIFT 16 725 726 #include "exec/cpu-all.h" 727 728 static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc, 729 target_ulong *cs_base, uint32_t *flags) 730 { 731 *pc = env->pc; 732 *cs_base = 0; 733 *flags = 0; 734 *flags |= xtensa_get_ring(env); 735 if (env->sregs[PS] & PS_EXCM) { 736 *flags |= XTENSA_TBFLAG_EXCM; 737 } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) { 738 target_ulong lend_dist = 739 env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS)); 740 741 /* 742 * 0 in the csbase_lend field means that there may not be a loopback 743 * for any instruction that starts inside this page. Any other value 744 * means that an instruction that ends at this offset from the page 745 * start may loop back and will need loopback code to be generated. 746 * 747 * lend_dist is 0 when LEND points to the start of the page, but 748 * no instruction that starts inside this page may end at offset 0, 749 * so it's still correct. 750 * 751 * When an instruction ends at a page boundary it may only start in 752 * the previous page. lend_dist will be encoded as TARGET_PAGE_SIZE 753 * for the TB that contains this instruction. 754 */ 755 if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_size) { 756 target_ulong lbeg_off = env->sregs[LEND] - env->sregs[LBEG]; 757 758 *cs_base = lend_dist; 759 if (lbeg_off < 256) { 760 *cs_base |= lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT; 761 } 762 } 763 } 764 if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) && 765 (env->sregs[LITBASE] & 1)) { 766 *flags |= XTENSA_TBFLAG_LITBASE; 767 } 768 if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) { 769 if (xtensa_get_cintlevel(env) < env->config->debug_level) { 770 *flags |= XTENSA_TBFLAG_DEBUG; 771 } 772 if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) { 773 *flags |= XTENSA_TBFLAG_ICOUNT; 774 } 775 } 776 if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) { 777 *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT; 778 } 779 if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) && 780 (env->sregs[PS] & (PS_WOE | PS_EXCM)) == PS_WOE) { 781 uint32_t windowstart = xtensa_replicate_windowstart(env) >> 782 (env->sregs[WINDOW_BASE] + 1); 783 uint32_t w = ctz32(windowstart | 0x8); 784 785 *flags |= (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE; 786 *flags |= extract32(env->sregs[PS], PS_CALLINC_SHIFT, 787 PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT; 788 } else { 789 *flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT; 790 } 791 if (env->yield_needed) { 792 *flags |= XTENSA_TBFLAG_YIELD; 793 } 794 } 795 796 #endif 797