1 /* 2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * * Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * * Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * * Neither the name of the Open Source and Linux Lab nor the 13 * names of its contributors may be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #ifndef XTENSA_CPU_H 29 #define XTENSA_CPU_H 30 31 #define ALIGNED_ONLY 32 #define TARGET_LONG_BITS 32 33 34 /* Xtensa processors have a weak memory model */ 35 #define TCG_GUEST_DEFAULT_MO (0) 36 37 #define CPUArchState struct CPUXtensaState 38 39 #include "qemu-common.h" 40 #include "cpu-qom.h" 41 #include "exec/cpu-defs.h" 42 #include "xtensa-isa.h" 43 44 #define NB_MMU_MODES 4 45 46 #define TARGET_PHYS_ADDR_SPACE_BITS 32 47 #ifdef CONFIG_USER_ONLY 48 #define TARGET_VIRT_ADDR_SPACE_BITS 30 49 #else 50 #define TARGET_VIRT_ADDR_SPACE_BITS 32 51 #endif 52 #define TARGET_PAGE_BITS 12 53 54 enum { 55 /* Additional instructions */ 56 XTENSA_OPTION_CODE_DENSITY, 57 XTENSA_OPTION_LOOP, 58 XTENSA_OPTION_EXTENDED_L32R, 59 XTENSA_OPTION_16_BIT_IMUL, 60 XTENSA_OPTION_32_BIT_IMUL, 61 XTENSA_OPTION_32_BIT_IMUL_HIGH, 62 XTENSA_OPTION_32_BIT_IDIV, 63 XTENSA_OPTION_MAC16, 64 XTENSA_OPTION_MISC_OP_NSA, 65 XTENSA_OPTION_MISC_OP_MINMAX, 66 XTENSA_OPTION_MISC_OP_SEXT, 67 XTENSA_OPTION_MISC_OP_CLAMPS, 68 XTENSA_OPTION_COPROCESSOR, 69 XTENSA_OPTION_BOOLEAN, 70 XTENSA_OPTION_FP_COPROCESSOR, 71 XTENSA_OPTION_MP_SYNCHRO, 72 XTENSA_OPTION_CONDITIONAL_STORE, 73 XTENSA_OPTION_ATOMCTL, 74 XTENSA_OPTION_DEPBITS, 75 76 /* Interrupts and exceptions */ 77 XTENSA_OPTION_EXCEPTION, 78 XTENSA_OPTION_RELOCATABLE_VECTOR, 79 XTENSA_OPTION_UNALIGNED_EXCEPTION, 80 XTENSA_OPTION_INTERRUPT, 81 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 82 XTENSA_OPTION_TIMER_INTERRUPT, 83 84 /* Local memory */ 85 XTENSA_OPTION_ICACHE, 86 XTENSA_OPTION_ICACHE_TEST, 87 XTENSA_OPTION_ICACHE_INDEX_LOCK, 88 XTENSA_OPTION_DCACHE, 89 XTENSA_OPTION_DCACHE_TEST, 90 XTENSA_OPTION_DCACHE_INDEX_LOCK, 91 XTENSA_OPTION_IRAM, 92 XTENSA_OPTION_IROM, 93 XTENSA_OPTION_DRAM, 94 XTENSA_OPTION_DROM, 95 XTENSA_OPTION_XLMI, 96 XTENSA_OPTION_HW_ALIGNMENT, 97 XTENSA_OPTION_MEMORY_ECC_PARITY, 98 99 /* Memory protection and translation */ 100 XTENSA_OPTION_REGION_PROTECTION, 101 XTENSA_OPTION_REGION_TRANSLATION, 102 XTENSA_OPTION_MMU, 103 XTENSA_OPTION_CACHEATTR, 104 105 /* Other */ 106 XTENSA_OPTION_WINDOWED_REGISTER, 107 XTENSA_OPTION_PROCESSOR_INTERFACE, 108 XTENSA_OPTION_MISC_SR, 109 XTENSA_OPTION_THREAD_POINTER, 110 XTENSA_OPTION_PROCESSOR_ID, 111 XTENSA_OPTION_DEBUG, 112 XTENSA_OPTION_TRACE_PORT, 113 XTENSA_OPTION_EXTERN_REGS, 114 }; 115 116 enum { 117 EXPSTATE = 230, 118 THREADPTR = 231, 119 FCR = 232, 120 FSR = 233, 121 }; 122 123 enum { 124 LBEG = 0, 125 LEND = 1, 126 LCOUNT = 2, 127 SAR = 3, 128 BR = 4, 129 LITBASE = 5, 130 SCOMPARE1 = 12, 131 ACCLO = 16, 132 ACCHI = 17, 133 MR = 32, 134 PREFCTL = 40, 135 WINDOW_BASE = 72, 136 WINDOW_START = 73, 137 PTEVADDR = 83, 138 MMID = 89, 139 RASID = 90, 140 ITLBCFG = 91, 141 DTLBCFG = 92, 142 IBREAKENABLE = 96, 143 MEMCTL = 97, 144 CACHEATTR = 98, 145 ATOMCTL = 99, 146 DDR = 104, 147 IBREAKA = 128, 148 DBREAKA = 144, 149 DBREAKC = 160, 150 CONFIGID0 = 176, 151 EPC1 = 177, 152 DEPC = 192, 153 EPS2 = 194, 154 CONFIGID1 = 208, 155 EXCSAVE1 = 209, 156 CPENABLE = 224, 157 INTSET = 226, 158 INTCLEAR = 227, 159 INTENABLE = 228, 160 PS = 230, 161 VECBASE = 231, 162 EXCCAUSE = 232, 163 DEBUGCAUSE = 233, 164 CCOUNT = 234, 165 PRID = 235, 166 ICOUNT = 236, 167 ICOUNTLEVEL = 237, 168 EXCVADDR = 238, 169 CCOMPARE = 240, 170 MISC = 244, 171 }; 172 173 #define PS_INTLEVEL 0xf 174 #define PS_INTLEVEL_SHIFT 0 175 176 #define PS_EXCM 0x10 177 #define PS_UM 0x20 178 179 #define PS_RING 0xc0 180 #define PS_RING_SHIFT 6 181 182 #define PS_OWB 0xf00 183 #define PS_OWB_SHIFT 8 184 #define PS_OWB_LEN 4 185 186 #define PS_CALLINC 0x30000 187 #define PS_CALLINC_SHIFT 16 188 #define PS_CALLINC_LEN 2 189 190 #define PS_WOE 0x40000 191 192 #define DEBUGCAUSE_IC 0x1 193 #define DEBUGCAUSE_IB 0x2 194 #define DEBUGCAUSE_DB 0x4 195 #define DEBUGCAUSE_BI 0x8 196 #define DEBUGCAUSE_BN 0x10 197 #define DEBUGCAUSE_DI 0x20 198 #define DEBUGCAUSE_DBNUM 0xf00 199 #define DEBUGCAUSE_DBNUM_SHIFT 8 200 201 #define DBREAKC_SB 0x80000000 202 #define DBREAKC_LB 0x40000000 203 #define DBREAKC_SB_LB (DBREAKC_SB | DBREAKC_LB) 204 #define DBREAKC_MASK 0x3f 205 206 #define MEMCTL_INIT 0x00800000 207 #define MEMCTL_IUSEWAYS_SHIFT 18 208 #define MEMCTL_IUSEWAYS_LEN 5 209 #define MEMCTL_IUSEWAYS_MASK 0x007c0000 210 #define MEMCTL_DALLOCWAYS_SHIFT 13 211 #define MEMCTL_DALLOCWAYS_LEN 5 212 #define MEMCTL_DALLOCWAYS_MASK 0x0003e000 213 #define MEMCTL_DUSEWAYS_SHIFT 8 214 #define MEMCTL_DUSEWAYS_LEN 5 215 #define MEMCTL_DUSEWAYS_MASK 0x00001f00 216 #define MEMCTL_ISNP 0x4 217 #define MEMCTL_DSNP 0x2 218 #define MEMCTL_IL0EN 0x1 219 220 #define MAX_INSN_LENGTH 64 221 #define MAX_INSN_SLOTS 32 222 #define MAX_OPCODE_ARGS 16 223 #define MAX_NAREG 64 224 #define MAX_NINTERRUPT 32 225 #define MAX_NLEVEL 6 226 #define MAX_NNMI 1 227 #define MAX_NCCOMPARE 3 228 #define MAX_TLB_WAY_SIZE 8 229 #define MAX_NDBREAK 2 230 #define MAX_NMEMORY 4 231 232 #define REGION_PAGE_MASK 0xe0000000 233 234 #define PAGE_CACHE_MASK 0x700 235 #define PAGE_CACHE_SHIFT 8 236 #define PAGE_CACHE_INVALID 0x000 237 #define PAGE_CACHE_BYPASS 0x100 238 #define PAGE_CACHE_WT 0x200 239 #define PAGE_CACHE_WB 0x400 240 #define PAGE_CACHE_ISOLATE 0x600 241 242 enum { 243 /* Static vectors */ 244 EXC_RESET0, 245 EXC_RESET1, 246 EXC_MEMORY_ERROR, 247 248 /* Dynamic vectors */ 249 EXC_WINDOW_OVERFLOW4, 250 EXC_WINDOW_UNDERFLOW4, 251 EXC_WINDOW_OVERFLOW8, 252 EXC_WINDOW_UNDERFLOW8, 253 EXC_WINDOW_OVERFLOW12, 254 EXC_WINDOW_UNDERFLOW12, 255 EXC_IRQ, 256 EXC_KERNEL, 257 EXC_USER, 258 EXC_DOUBLE, 259 EXC_DEBUG, 260 EXC_MAX 261 }; 262 263 enum { 264 ILLEGAL_INSTRUCTION_CAUSE = 0, 265 SYSCALL_CAUSE, 266 INSTRUCTION_FETCH_ERROR_CAUSE, 267 LOAD_STORE_ERROR_CAUSE, 268 LEVEL1_INTERRUPT_CAUSE, 269 ALLOCA_CAUSE, 270 INTEGER_DIVIDE_BY_ZERO_CAUSE, 271 PRIVILEGED_CAUSE = 8, 272 LOAD_STORE_ALIGNMENT_CAUSE, 273 274 INSTR_PIF_DATA_ERROR_CAUSE = 12, 275 LOAD_STORE_PIF_DATA_ERROR_CAUSE, 276 INSTR_PIF_ADDR_ERROR_CAUSE, 277 LOAD_STORE_PIF_ADDR_ERROR_CAUSE, 278 279 INST_TLB_MISS_CAUSE, 280 INST_TLB_MULTI_HIT_CAUSE, 281 INST_FETCH_PRIVILEGE_CAUSE, 282 INST_FETCH_PROHIBITED_CAUSE = 20, 283 LOAD_STORE_TLB_MISS_CAUSE = 24, 284 LOAD_STORE_TLB_MULTI_HIT_CAUSE, 285 LOAD_STORE_PRIVILEGE_CAUSE, 286 LOAD_PROHIBITED_CAUSE = 28, 287 STORE_PROHIBITED_CAUSE, 288 289 COPROCESSOR0_DISABLED = 32, 290 }; 291 292 typedef enum { 293 INTTYPE_LEVEL, 294 INTTYPE_EDGE, 295 INTTYPE_NMI, 296 INTTYPE_SOFTWARE, 297 INTTYPE_TIMER, 298 INTTYPE_DEBUG, 299 INTTYPE_WRITE_ERR, 300 INTTYPE_PROFILING, 301 INTTYPE_MAX 302 } interrupt_type; 303 304 struct CPUXtensaState; 305 306 typedef struct xtensa_tlb_entry { 307 uint32_t vaddr; 308 uint32_t paddr; 309 uint8_t asid; 310 uint8_t attr; 311 bool variable; 312 } xtensa_tlb_entry; 313 314 typedef struct xtensa_tlb { 315 unsigned nways; 316 const unsigned way_size[10]; 317 bool varway56; 318 unsigned nrefillentries; 319 } xtensa_tlb; 320 321 typedef struct XtensaGdbReg { 322 int targno; 323 unsigned flags; 324 int type; 325 int group; 326 unsigned size; 327 } XtensaGdbReg; 328 329 typedef struct XtensaGdbRegmap { 330 int num_regs; 331 int num_core_regs; 332 /* PC + a + ar + sr + ur */ 333 XtensaGdbReg reg[1 + 16 + 64 + 256 + 256]; 334 } XtensaGdbRegmap; 335 336 typedef struct XtensaCcompareTimer { 337 struct CPUXtensaState *env; 338 QEMUTimer *timer; 339 } XtensaCcompareTimer; 340 341 typedef struct XtensaMemory { 342 unsigned num; 343 struct XtensaMemoryRegion { 344 uint32_t addr; 345 uint32_t size; 346 } location[MAX_NMEMORY]; 347 } XtensaMemory; 348 349 typedef struct opcode_arg { 350 uint32_t imm; 351 uint32_t raw_imm; 352 void *in; 353 void *out; 354 } OpcodeArg; 355 356 typedef struct DisasContext DisasContext; 357 typedef void (*XtensaOpcodeOp)(DisasContext *dc, const OpcodeArg arg[], 358 const uint32_t par[]); 359 typedef bool (*XtensaOpcodeBoolTest)(DisasContext *dc, 360 const OpcodeArg arg[], 361 const uint32_t par[]); 362 typedef uint32_t (*XtensaOpcodeUintTest)(DisasContext *dc, 363 const OpcodeArg arg[], 364 const uint32_t par[]); 365 366 enum { 367 XTENSA_OP_ILL = 0x1, 368 XTENSA_OP_PRIVILEGED = 0x2, 369 XTENSA_OP_SYSCALL = 0x4, 370 XTENSA_OP_DEBUG_BREAK = 0x8, 371 372 XTENSA_OP_OVERFLOW = 0x10, 373 XTENSA_OP_UNDERFLOW = 0x20, 374 XTENSA_OP_ALLOCA = 0x40, 375 XTENSA_OP_COPROCESSOR = 0x80, 376 377 XTENSA_OP_DIVIDE_BY_ZERO = 0x100, 378 379 /* Postprocessing flags */ 380 XTENSA_OP_CHECK_INTERRUPTS = 0x200, 381 XTENSA_OP_EXIT_TB_M1 = 0x400, 382 XTENSA_OP_EXIT_TB_0 = 0x800, 383 XTENSA_OP_SYNC_REGISTER_WINDOW = 0x1000, 384 385 XTENSA_OP_POSTPROCESS = 386 XTENSA_OP_CHECK_INTERRUPTS | 387 XTENSA_OP_EXIT_TB_M1 | 388 XTENSA_OP_EXIT_TB_0 | 389 XTENSA_OP_SYNC_REGISTER_WINDOW, 390 391 XTENSA_OP_NAME_ARRAY = 0x8000, 392 393 XTENSA_OP_CONTROL_FLOW = 0x10000, 394 XTENSA_OP_STORE = 0x20000, 395 XTENSA_OP_LOAD = 0x40000, 396 XTENSA_OP_LOAD_STORE = 397 XTENSA_OP_LOAD | XTENSA_OP_STORE, 398 }; 399 400 typedef struct XtensaOpcodeOps { 401 const void *name; 402 XtensaOpcodeOp translate; 403 XtensaOpcodeBoolTest test_ill; 404 XtensaOpcodeUintTest test_overflow; 405 const uint32_t *par; 406 uint32_t op_flags; 407 uint32_t coprocessor; 408 } XtensaOpcodeOps; 409 410 typedef struct XtensaOpcodeTranslators { 411 unsigned num_opcodes; 412 const XtensaOpcodeOps *opcode; 413 } XtensaOpcodeTranslators; 414 415 extern const XtensaOpcodeTranslators xtensa_core_opcodes; 416 extern const XtensaOpcodeTranslators xtensa_fpu2000_opcodes; 417 418 struct XtensaConfig { 419 const char *name; 420 uint64_t options; 421 XtensaGdbRegmap gdb_regmap; 422 unsigned nareg; 423 int excm_level; 424 int ndepc; 425 unsigned inst_fetch_width; 426 unsigned max_insn_size; 427 uint32_t vecbase; 428 uint32_t exception_vector[EXC_MAX]; 429 unsigned ninterrupt; 430 unsigned nlevel; 431 uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1]; 432 uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1]; 433 uint32_t inttype_mask[INTTYPE_MAX]; 434 struct { 435 uint32_t level; 436 interrupt_type inttype; 437 } interrupt[MAX_NINTERRUPT]; 438 unsigned nccompare; 439 uint32_t timerint[MAX_NCCOMPARE]; 440 unsigned nextint; 441 unsigned extint[MAX_NINTERRUPT]; 442 443 unsigned debug_level; 444 unsigned nibreak; 445 unsigned ndbreak; 446 447 unsigned icache_ways; 448 unsigned dcache_ways; 449 uint32_t memctl_mask; 450 451 XtensaMemory instrom; 452 XtensaMemory instram; 453 XtensaMemory datarom; 454 XtensaMemory dataram; 455 XtensaMemory sysrom; 456 XtensaMemory sysram; 457 458 uint32_t configid[2]; 459 460 void *isa_internal; 461 xtensa_isa isa; 462 XtensaOpcodeOps **opcode_ops; 463 const XtensaOpcodeTranslators **opcode_translators; 464 xtensa_regfile a_regfile; 465 void ***regfile; 466 467 uint32_t clock_freq_khz; 468 469 xtensa_tlb itlb; 470 xtensa_tlb dtlb; 471 }; 472 473 typedef struct XtensaConfigList { 474 const XtensaConfig *config; 475 struct XtensaConfigList *next; 476 } XtensaConfigList; 477 478 #ifdef HOST_WORDS_BIGENDIAN 479 enum { 480 FP_F32_HIGH, 481 FP_F32_LOW, 482 }; 483 #else 484 enum { 485 FP_F32_LOW, 486 FP_F32_HIGH, 487 }; 488 #endif 489 490 typedef struct CPUXtensaState { 491 const XtensaConfig *config; 492 uint32_t regs[16]; 493 uint32_t pc; 494 uint32_t sregs[256]; 495 uint32_t uregs[256]; 496 uint32_t phys_regs[MAX_NAREG]; 497 union { 498 float32 f32[2]; 499 float64 f64; 500 } fregs[16]; 501 float_status fp_status; 502 uint32_t windowbase_next; 503 504 #ifndef CONFIG_USER_ONLY 505 xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE]; 506 xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE]; 507 unsigned autorefill_idx; 508 bool runstall; 509 AddressSpace *address_space_er; 510 MemoryRegion *system_er; 511 int pending_irq_level; /* level of last raised IRQ */ 512 qemu_irq *irq_inputs; 513 qemu_irq ext_irq_inputs[MAX_NINTERRUPT]; 514 qemu_irq runstall_irq; 515 XtensaCcompareTimer ccompare[MAX_NCCOMPARE]; 516 uint64_t time_base; 517 uint64_t ccount_time; 518 uint32_t ccount_base; 519 #endif 520 521 int exception_taken; 522 int yield_needed; 523 unsigned static_vectors; 524 525 /* Watchpoints for DBREAK registers */ 526 struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK]; 527 528 CPU_COMMON 529 } CPUXtensaState; 530 531 /** 532 * XtensaCPU: 533 * @env: #CPUXtensaState 534 * 535 * An Xtensa CPU. 536 */ 537 struct XtensaCPU { 538 /*< private >*/ 539 CPUState parent_obj; 540 /*< public >*/ 541 542 CPUXtensaState env; 543 }; 544 545 static inline XtensaCPU *xtensa_env_get_cpu(const CPUXtensaState *env) 546 { 547 return container_of(env, XtensaCPU, env); 548 } 549 550 #define ENV_GET_CPU(e) CPU(xtensa_env_get_cpu(e)) 551 552 #define ENV_OFFSET offsetof(XtensaCPU, env) 553 554 555 int xtensa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int size, 556 int mmu_idx); 557 void xtensa_cpu_do_interrupt(CPUState *cpu); 558 bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request); 559 void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, 560 unsigned size, MMUAccessType access_type, 561 int mmu_idx, MemTxAttrs attrs, 562 MemTxResult response, uintptr_t retaddr); 563 void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, int flags); 564 hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 565 void xtensa_count_regs(const XtensaConfig *config, 566 unsigned *n_regs, unsigned *n_core_regs); 567 int xtensa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 568 int xtensa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 569 void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, 570 MMUAccessType access_type, 571 int mmu_idx, uintptr_t retaddr); 572 573 #define cpu_signal_handler cpu_xtensa_signal_handler 574 #define cpu_list xtensa_cpu_list 575 576 #define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU 577 #define XTENSA_CPU_TYPE_NAME(model) model XTENSA_CPU_TYPE_SUFFIX 578 #define CPU_RESOLVING_TYPE TYPE_XTENSA_CPU 579 580 #ifdef TARGET_WORDS_BIGENDIAN 581 #define XTENSA_DEFAULT_CPU_MODEL "fsf" 582 #define XTENSA_DEFAULT_CPU_NOMMU_MODEL "fsf" 583 #else 584 #define XTENSA_DEFAULT_CPU_MODEL "dc232b" 585 #define XTENSA_DEFAULT_CPU_NOMMU_MODEL "de212" 586 #endif 587 #define XTENSA_DEFAULT_CPU_TYPE \ 588 XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_MODEL) 589 #define XTENSA_DEFAULT_CPU_NOMMU_TYPE \ 590 XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_NOMMU_MODEL) 591 592 void xtensa_translate_init(void); 593 void **xtensa_get_regfile_by_name(const char *name); 594 void xtensa_breakpoint_handler(CPUState *cs); 595 void xtensa_register_core(XtensaConfigList *node); 596 void xtensa_sim_open_console(Chardev *chr); 597 void check_interrupts(CPUXtensaState *s); 598 void xtensa_irq_init(CPUXtensaState *env); 599 qemu_irq *xtensa_get_extints(CPUXtensaState *env); 600 qemu_irq xtensa_get_runstall(CPUXtensaState *env); 601 int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc); 602 void xtensa_cpu_list(void); 603 void xtensa_sync_window_from_phys(CPUXtensaState *env); 604 void xtensa_sync_phys_from_window(CPUXtensaState *env); 605 void xtensa_rotate_window(CPUXtensaState *env, uint32_t delta); 606 void xtensa_restore_owb(CPUXtensaState *env); 607 void debug_exception_env(CPUXtensaState *new_env, uint32_t cause); 608 609 static inline void xtensa_select_static_vectors(CPUXtensaState *env, 610 unsigned n) 611 { 612 assert(n < 2); 613 env->static_vectors = n; 614 } 615 void xtensa_runstall(CPUXtensaState *env, bool runstall); 616 617 #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt)) 618 #define XTENSA_OPTION_ALL (~(uint64_t)0) 619 620 static inline bool xtensa_option_bits_enabled(const XtensaConfig *config, 621 uint64_t opt) 622 { 623 return (config->options & opt) != 0; 624 } 625 626 static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt) 627 { 628 return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt)); 629 } 630 631 static inline int xtensa_get_cintlevel(const CPUXtensaState *env) 632 { 633 int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT; 634 if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) { 635 level = env->config->excm_level; 636 } 637 return level; 638 } 639 640 static inline int xtensa_get_ring(const CPUXtensaState *env) 641 { 642 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 643 return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT; 644 } else { 645 return 0; 646 } 647 } 648 649 static inline int xtensa_get_cring(const CPUXtensaState *env) 650 { 651 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) && 652 (env->sregs[PS] & PS_EXCM) == 0) { 653 return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT; 654 } else { 655 return 0; 656 } 657 } 658 659 #ifndef CONFIG_USER_ONLY 660 uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, 661 bool dtlb, uint32_t way); 662 void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb, 663 uint32_t *vpn, uint32_t wi, uint32_t *ei); 664 int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb, 665 uint32_t *pwi, uint32_t *pei, uint8_t *pring); 666 void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env, 667 xtensa_tlb_entry *entry, bool dtlb, 668 unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte); 669 void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb, 670 unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte); 671 int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb, 672 uint32_t vaddr, int is_write, int mmu_idx, 673 uint32_t *paddr, uint32_t *page_size, unsigned *access); 674 void reset_mmu(CPUXtensaState *env); 675 void dump_mmu(CPUXtensaState *env); 676 677 static inline MemoryRegion *xtensa_get_er_region(CPUXtensaState *env) 678 { 679 return env->system_er; 680 } 681 682 static inline xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env, 683 bool dtlb, unsigned wi, unsigned ei) 684 { 685 return dtlb ? 686 env->dtlb[wi] + ei : 687 env->itlb[wi] + ei; 688 } 689 #endif 690 691 static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env) 692 { 693 return env->sregs[WINDOW_START] | 694 (env->sregs[WINDOW_START] << env->config->nareg / 4); 695 } 696 697 /* MMU modes definitions */ 698 #define MMU_MODE0_SUFFIX _ring0 699 #define MMU_MODE1_SUFFIX _ring1 700 #define MMU_MODE2_SUFFIX _ring2 701 #define MMU_MODE3_SUFFIX _ring3 702 #define MMU_USER_IDX 3 703 704 static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch) 705 { 706 return xtensa_get_cring(env); 707 } 708 709 #define XTENSA_TBFLAG_RING_MASK 0x3 710 #define XTENSA_TBFLAG_EXCM 0x4 711 #define XTENSA_TBFLAG_LITBASE 0x8 712 #define XTENSA_TBFLAG_DEBUG 0x10 713 #define XTENSA_TBFLAG_ICOUNT 0x20 714 #define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0 715 #define XTENSA_TBFLAG_CPENABLE_SHIFT 6 716 #define XTENSA_TBFLAG_EXCEPTION 0x4000 717 #define XTENSA_TBFLAG_WINDOW_MASK 0x18000 718 #define XTENSA_TBFLAG_WINDOW_SHIFT 15 719 #define XTENSA_TBFLAG_YIELD 0x20000 720 #define XTENSA_TBFLAG_CWOE 0x40000 721 #define XTENSA_TBFLAG_CALLINC_MASK 0x180000 722 #define XTENSA_TBFLAG_CALLINC_SHIFT 19 723 724 #define XTENSA_CSBASE_LEND_MASK 0x0000ffff 725 #define XTENSA_CSBASE_LEND_SHIFT 0 726 #define XTENSA_CSBASE_LBEG_OFF_MASK 0x00ff0000 727 #define XTENSA_CSBASE_LBEG_OFF_SHIFT 16 728 729 static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc, 730 target_ulong *cs_base, uint32_t *flags) 731 { 732 CPUState *cs = CPU(xtensa_env_get_cpu(env)); 733 734 *pc = env->pc; 735 *cs_base = 0; 736 *flags = 0; 737 *flags |= xtensa_get_ring(env); 738 if (env->sregs[PS] & PS_EXCM) { 739 *flags |= XTENSA_TBFLAG_EXCM; 740 } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) { 741 target_ulong lend_dist = 742 env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS)); 743 744 /* 745 * 0 in the csbase_lend field means that there may not be a loopback 746 * for any instruction that starts inside this page. Any other value 747 * means that an instruction that ends at this offset from the page 748 * start may loop back and will need loopback code to be generated. 749 * 750 * lend_dist is 0 when LEND points to the start of the page, but 751 * no instruction that starts inside this page may end at offset 0, 752 * so it's still correct. 753 * 754 * When an instruction ends at a page boundary it may only start in 755 * the previous page. lend_dist will be encoded as TARGET_PAGE_SIZE 756 * for the TB that contains this instruction. 757 */ 758 if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_size) { 759 target_ulong lbeg_off = env->sregs[LEND] - env->sregs[LBEG]; 760 761 *cs_base = lend_dist; 762 if (lbeg_off < 256) { 763 *cs_base |= lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT; 764 } 765 } 766 } 767 if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) && 768 (env->sregs[LITBASE] & 1)) { 769 *flags |= XTENSA_TBFLAG_LITBASE; 770 } 771 if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) { 772 if (xtensa_get_cintlevel(env) < env->config->debug_level) { 773 *flags |= XTENSA_TBFLAG_DEBUG; 774 } 775 if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) { 776 *flags |= XTENSA_TBFLAG_ICOUNT; 777 } 778 } 779 if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) { 780 *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT; 781 } 782 if (cs->singlestep_enabled && env->exception_taken) { 783 *flags |= XTENSA_TBFLAG_EXCEPTION; 784 } 785 if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) && 786 (env->sregs[PS] & (PS_WOE | PS_EXCM)) == PS_WOE) { 787 uint32_t windowstart = xtensa_replicate_windowstart(env) >> 788 (env->sregs[WINDOW_BASE] + 1); 789 uint32_t w = ctz32(windowstart | 0x8); 790 791 *flags |= (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE; 792 *flags |= extract32(env->sregs[PS], PS_CALLINC_SHIFT, 793 PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT; 794 } else { 795 *flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT; 796 } 797 if (env->yield_needed) { 798 *flags |= XTENSA_TBFLAG_YIELD; 799 } 800 } 801 802 #include "exec/cpu-all.h" 803 804 #endif 805