1 /* 2 * QEMU Xtensa CPU 3 * 4 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. 5 * Copyright (c) 2012 SUSE LINUX Products GmbH 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * * Neither the name of the Open Source and Linux Lab nor the 16 * names of its contributors may be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qapi/error.h" 33 #include "cpu.h" 34 #include "fpu/softfloat.h" 35 #include "qemu/module.h" 36 #include "migration/vmstate.h" 37 #include "hw/qdev-clock.h" 38 #ifndef CONFIG_USER_ONLY 39 #include "exec/memory.h" 40 #endif 41 42 43 static void xtensa_cpu_set_pc(CPUState *cs, vaddr value) 44 { 45 XtensaCPU *cpu = XTENSA_CPU(cs); 46 47 cpu->env.pc = value; 48 } 49 50 static vaddr xtensa_cpu_get_pc(CPUState *cs) 51 { 52 XtensaCPU *cpu = XTENSA_CPU(cs); 53 54 return cpu->env.pc; 55 } 56 57 static void xtensa_restore_state_to_opc(CPUState *cs, 58 const TranslationBlock *tb, 59 const uint64_t *data) 60 { 61 XtensaCPU *cpu = XTENSA_CPU(cs); 62 63 cpu->env.pc = data[0]; 64 } 65 66 static bool xtensa_cpu_has_work(CPUState *cs) 67 { 68 #ifndef CONFIG_USER_ONLY 69 XtensaCPU *cpu = XTENSA_CPU(cs); 70 71 return !cpu->env.runstall && cpu->env.pending_irq_level; 72 #else 73 return true; 74 #endif 75 } 76 77 static int xtensa_cpu_mmu_index(CPUState *cs, bool ifetch) 78 { 79 return xtensa_get_cring(cpu_env(cs)); 80 } 81 82 #ifdef CONFIG_USER_ONLY 83 static bool abi_call0; 84 85 void xtensa_set_abi_call0(void) 86 { 87 abi_call0 = true; 88 } 89 90 bool xtensa_abi_call0(void) 91 { 92 return abi_call0; 93 } 94 #endif 95 96 static void xtensa_cpu_reset_hold(Object *obj) 97 { 98 CPUState *s = CPU(obj); 99 XtensaCPU *cpu = XTENSA_CPU(s); 100 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(cpu); 101 CPUXtensaState *env = &cpu->env; 102 bool dfpu = xtensa_option_enabled(env->config, 103 XTENSA_OPTION_DFP_COPROCESSOR); 104 105 if (xcc->parent_phases.hold) { 106 xcc->parent_phases.hold(obj); 107 } 108 109 env->pc = env->config->exception_vector[EXC_RESET0 + env->static_vectors]; 110 env->sregs[LITBASE] &= ~1; 111 #ifndef CONFIG_USER_ONLY 112 env->sregs[PS] = xtensa_option_enabled(env->config, 113 XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10; 114 env->pending_irq_level = 0; 115 #else 116 env->sregs[PS] = PS_UM | (3 << PS_RING_SHIFT); 117 if (xtensa_option_enabled(env->config, 118 XTENSA_OPTION_WINDOWED_REGISTER) && 119 !xtensa_abi_call0()) { 120 env->sregs[PS] |= PS_WOE; 121 } 122 env->sregs[CPENABLE] = 0xff; 123 #endif 124 env->sregs[VECBASE] = env->config->vecbase; 125 env->sregs[IBREAKENABLE] = 0; 126 env->sregs[MEMCTL] = MEMCTL_IL0EN & env->config->memctl_mask; 127 env->sregs[ATOMCTL] = xtensa_option_enabled(env->config, 128 XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15; 129 env->sregs[CONFIGID0] = env->config->configid[0]; 130 env->sregs[CONFIGID1] = env->config->configid[1]; 131 env->exclusive_addr = -1; 132 133 #ifndef CONFIG_USER_ONLY 134 reset_mmu(env); 135 s->halted = env->runstall; 136 #endif 137 set_no_signaling_nans(!dfpu, &env->fp_status); 138 set_use_first_nan(!dfpu, &env->fp_status); 139 } 140 141 static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model) 142 { 143 ObjectClass *oc; 144 char *typename; 145 146 typename = g_strdup_printf(XTENSA_CPU_TYPE_NAME("%s"), cpu_model); 147 oc = object_class_by_name(typename); 148 g_free(typename); 149 150 return oc; 151 } 152 153 static void xtensa_cpu_disas_set_info(CPUState *cs, disassemble_info *info) 154 { 155 XtensaCPU *cpu = XTENSA_CPU(cs); 156 157 info->private_data = cpu->env.config->isa; 158 info->print_insn = print_insn_xtensa; 159 } 160 161 static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp) 162 { 163 CPUState *cs = CPU(dev); 164 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev); 165 Error *local_err = NULL; 166 167 #ifndef CONFIG_USER_ONLY 168 xtensa_irq_init(&XTENSA_CPU(dev)->env); 169 #endif 170 171 cpu_exec_realizefn(cs, &local_err); 172 if (local_err != NULL) { 173 error_propagate(errp, local_err); 174 return; 175 } 176 177 cs->gdb_num_regs = xcc->config->gdb_regmap.num_regs; 178 179 qemu_init_vcpu(cs); 180 181 xcc->parent_realize(dev, errp); 182 } 183 184 static void xtensa_cpu_initfn(Object *obj) 185 { 186 XtensaCPU *cpu = XTENSA_CPU(obj); 187 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj); 188 CPUXtensaState *env = &cpu->env; 189 190 env->config = xcc->config; 191 192 #ifndef CONFIG_USER_ONLY 193 env->address_space_er = g_malloc(sizeof(*env->address_space_er)); 194 env->system_er = g_malloc(sizeof(*env->system_er)); 195 memory_region_init_io(env->system_er, obj, NULL, env, "er", 196 UINT64_C(0x100000000)); 197 address_space_init(env->address_space_er, env->system_er, "ER"); 198 199 cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu, 0); 200 clock_set_hz(cpu->clock, env->config->clock_freq_khz * 1000); 201 #endif 202 } 203 204 XtensaCPU *xtensa_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk) 205 { 206 DeviceState *cpu; 207 208 cpu = DEVICE(object_new(cpu_type)); 209 qdev_connect_clock_in(cpu, "clk-in", cpu_refclk); 210 qdev_realize(cpu, NULL, &error_abort); 211 212 return XTENSA_CPU(cpu); 213 } 214 215 #ifndef CONFIG_USER_ONLY 216 static const VMStateDescription vmstate_xtensa_cpu = { 217 .name = "cpu", 218 .unmigratable = 1, 219 }; 220 221 #include "hw/core/sysemu-cpu-ops.h" 222 223 static const struct SysemuCPUOps xtensa_sysemu_ops = { 224 .get_phys_page_debug = xtensa_cpu_get_phys_page_debug, 225 }; 226 #endif 227 228 #include "hw/core/tcg-cpu-ops.h" 229 230 static const TCGCPUOps xtensa_tcg_ops = { 231 .initialize = xtensa_translate_init, 232 .debug_excp_handler = xtensa_breakpoint_handler, 233 .restore_state_to_opc = xtensa_restore_state_to_opc, 234 235 #ifndef CONFIG_USER_ONLY 236 .tlb_fill = xtensa_cpu_tlb_fill, 237 .cpu_exec_interrupt = xtensa_cpu_exec_interrupt, 238 .do_interrupt = xtensa_cpu_do_interrupt, 239 .do_transaction_failed = xtensa_cpu_do_transaction_failed, 240 .do_unaligned_access = xtensa_cpu_do_unaligned_access, 241 .debug_check_breakpoint = xtensa_debug_check_breakpoint, 242 #endif /* !CONFIG_USER_ONLY */ 243 }; 244 245 static void xtensa_cpu_class_init(ObjectClass *oc, void *data) 246 { 247 DeviceClass *dc = DEVICE_CLASS(oc); 248 CPUClass *cc = CPU_CLASS(oc); 249 XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc); 250 ResettableClass *rc = RESETTABLE_CLASS(oc); 251 252 device_class_set_parent_realize(dc, xtensa_cpu_realizefn, 253 &xcc->parent_realize); 254 255 resettable_class_set_parent_phases(rc, NULL, xtensa_cpu_reset_hold, NULL, 256 &xcc->parent_phases); 257 258 cc->class_by_name = xtensa_cpu_class_by_name; 259 cc->has_work = xtensa_cpu_has_work; 260 cc->mmu_index = xtensa_cpu_mmu_index; 261 cc->dump_state = xtensa_cpu_dump_state; 262 cc->set_pc = xtensa_cpu_set_pc; 263 cc->get_pc = xtensa_cpu_get_pc; 264 cc->gdb_read_register = xtensa_cpu_gdb_read_register; 265 cc->gdb_write_register = xtensa_cpu_gdb_write_register; 266 cc->gdb_stop_before_watchpoint = true; 267 #ifndef CONFIG_USER_ONLY 268 cc->sysemu_ops = &xtensa_sysemu_ops; 269 dc->vmsd = &vmstate_xtensa_cpu; 270 #endif 271 cc->disas_set_info = xtensa_cpu_disas_set_info; 272 cc->tcg_ops = &xtensa_tcg_ops; 273 } 274 275 static const TypeInfo xtensa_cpu_type_info = { 276 .name = TYPE_XTENSA_CPU, 277 .parent = TYPE_CPU, 278 .instance_size = sizeof(XtensaCPU), 279 .instance_align = __alignof(XtensaCPU), 280 .instance_init = xtensa_cpu_initfn, 281 .abstract = true, 282 .class_size = sizeof(XtensaCPUClass), 283 .class_init = xtensa_cpu_class_init, 284 }; 285 286 static void xtensa_cpu_register_types(void) 287 { 288 type_register_static(&xtensa_cpu_type_info); 289 } 290 291 type_init(xtensa_cpu_register_types) 292