1 /* 2 * QEMU Xtensa CPU 3 * 4 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. 5 * Copyright (c) 2012 SUSE LINUX Products GmbH 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * * Neither the name of the Open Source and Linux Lab nor the 16 * names of its contributors may be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qapi/error.h" 33 #include "cpu.h" 34 #include "fpu/softfloat.h" 35 #include "qemu/module.h" 36 #include "migration/vmstate.h" 37 #include "hw/qdev-clock.h" 38 39 40 static void xtensa_cpu_set_pc(CPUState *cs, vaddr value) 41 { 42 XtensaCPU *cpu = XTENSA_CPU(cs); 43 44 cpu->env.pc = value; 45 } 46 47 static vaddr xtensa_cpu_get_pc(CPUState *cs) 48 { 49 XtensaCPU *cpu = XTENSA_CPU(cs); 50 51 return cpu->env.pc; 52 } 53 54 static void xtensa_restore_state_to_opc(CPUState *cs, 55 const TranslationBlock *tb, 56 const uint64_t *data) 57 { 58 XtensaCPU *cpu = XTENSA_CPU(cs); 59 60 cpu->env.pc = data[0]; 61 } 62 63 static bool xtensa_cpu_has_work(CPUState *cs) 64 { 65 #ifndef CONFIG_USER_ONLY 66 XtensaCPU *cpu = XTENSA_CPU(cs); 67 68 return !cpu->env.runstall && cpu->env.pending_irq_level; 69 #else 70 return true; 71 #endif 72 } 73 74 #ifdef CONFIG_USER_ONLY 75 static bool abi_call0; 76 77 void xtensa_set_abi_call0(void) 78 { 79 abi_call0 = true; 80 } 81 82 bool xtensa_abi_call0(void) 83 { 84 return abi_call0; 85 } 86 #endif 87 88 static void xtensa_cpu_reset(DeviceState *dev) 89 { 90 CPUState *s = CPU(dev); 91 XtensaCPU *cpu = XTENSA_CPU(s); 92 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(cpu); 93 CPUXtensaState *env = &cpu->env; 94 bool dfpu = xtensa_option_enabled(env->config, 95 XTENSA_OPTION_DFP_COPROCESSOR); 96 97 xcc->parent_reset(dev); 98 99 env->pc = env->config->exception_vector[EXC_RESET0 + env->static_vectors]; 100 env->sregs[LITBASE] &= ~1; 101 #ifndef CONFIG_USER_ONLY 102 env->sregs[PS] = xtensa_option_enabled(env->config, 103 XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10; 104 env->pending_irq_level = 0; 105 #else 106 env->sregs[PS] = PS_UM | (3 << PS_RING_SHIFT); 107 if (xtensa_option_enabled(env->config, 108 XTENSA_OPTION_WINDOWED_REGISTER) && 109 !xtensa_abi_call0()) { 110 env->sregs[PS] |= PS_WOE; 111 } 112 env->sregs[CPENABLE] = 0xff; 113 #endif 114 env->sregs[VECBASE] = env->config->vecbase; 115 env->sregs[IBREAKENABLE] = 0; 116 env->sregs[MEMCTL] = MEMCTL_IL0EN & env->config->memctl_mask; 117 env->sregs[ATOMCTL] = xtensa_option_enabled(env->config, 118 XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15; 119 env->sregs[CONFIGID0] = env->config->configid[0]; 120 env->sregs[CONFIGID1] = env->config->configid[1]; 121 env->exclusive_addr = -1; 122 123 #ifndef CONFIG_USER_ONLY 124 reset_mmu(env); 125 s->halted = env->runstall; 126 #endif 127 set_no_signaling_nans(!dfpu, &env->fp_status); 128 set_use_first_nan(!dfpu, &env->fp_status); 129 } 130 131 static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model) 132 { 133 ObjectClass *oc; 134 char *typename; 135 136 typename = g_strdup_printf(XTENSA_CPU_TYPE_NAME("%s"), cpu_model); 137 oc = object_class_by_name(typename); 138 g_free(typename); 139 if (oc == NULL || !object_class_dynamic_cast(oc, TYPE_XTENSA_CPU) || 140 object_class_is_abstract(oc)) { 141 return NULL; 142 } 143 return oc; 144 } 145 146 static void xtensa_cpu_disas_set_info(CPUState *cs, disassemble_info *info) 147 { 148 XtensaCPU *cpu = XTENSA_CPU(cs); 149 150 info->private_data = cpu->env.config->isa; 151 info->print_insn = print_insn_xtensa; 152 } 153 154 static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp) 155 { 156 CPUState *cs = CPU(dev); 157 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev); 158 Error *local_err = NULL; 159 160 #ifndef CONFIG_USER_ONLY 161 xtensa_irq_init(&XTENSA_CPU(dev)->env); 162 #endif 163 164 cpu_exec_realizefn(cs, &local_err); 165 if (local_err != NULL) { 166 error_propagate(errp, local_err); 167 return; 168 } 169 170 cs->gdb_num_regs = xcc->config->gdb_regmap.num_regs; 171 172 qemu_init_vcpu(cs); 173 174 xcc->parent_realize(dev, errp); 175 } 176 177 static void xtensa_cpu_initfn(Object *obj) 178 { 179 XtensaCPU *cpu = XTENSA_CPU(obj); 180 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj); 181 CPUXtensaState *env = &cpu->env; 182 183 cpu_set_cpustate_pointers(cpu); 184 env->config = xcc->config; 185 186 #ifndef CONFIG_USER_ONLY 187 env->address_space_er = g_malloc(sizeof(*env->address_space_er)); 188 env->system_er = g_malloc(sizeof(*env->system_er)); 189 memory_region_init_io(env->system_er, obj, NULL, env, "er", 190 UINT64_C(0x100000000)); 191 address_space_init(env->address_space_er, env->system_er, "ER"); 192 193 cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu, 0); 194 clock_set_hz(cpu->clock, env->config->clock_freq_khz * 1000); 195 #endif 196 } 197 198 XtensaCPU *xtensa_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk) 199 { 200 DeviceState *cpu; 201 202 cpu = DEVICE(object_new(cpu_type)); 203 qdev_connect_clock_in(cpu, "clk-in", cpu_refclk); 204 qdev_realize(cpu, NULL, &error_abort); 205 206 return XTENSA_CPU(cpu); 207 } 208 209 #ifndef CONFIG_USER_ONLY 210 static const VMStateDescription vmstate_xtensa_cpu = { 211 .name = "cpu", 212 .unmigratable = 1, 213 }; 214 215 #include "hw/core/sysemu-cpu-ops.h" 216 217 static const struct SysemuCPUOps xtensa_sysemu_ops = { 218 .get_phys_page_debug = xtensa_cpu_get_phys_page_debug, 219 }; 220 #endif 221 222 #include "hw/core/tcg-cpu-ops.h" 223 224 static const struct TCGCPUOps xtensa_tcg_ops = { 225 .initialize = xtensa_translate_init, 226 .debug_excp_handler = xtensa_breakpoint_handler, 227 .restore_state_to_opc = xtensa_restore_state_to_opc, 228 229 #ifndef CONFIG_USER_ONLY 230 .tlb_fill = xtensa_cpu_tlb_fill, 231 .cpu_exec_interrupt = xtensa_cpu_exec_interrupt, 232 .do_interrupt = xtensa_cpu_do_interrupt, 233 .do_transaction_failed = xtensa_cpu_do_transaction_failed, 234 .do_unaligned_access = xtensa_cpu_do_unaligned_access, 235 #endif /* !CONFIG_USER_ONLY */ 236 }; 237 238 static void xtensa_cpu_class_init(ObjectClass *oc, void *data) 239 { 240 DeviceClass *dc = DEVICE_CLASS(oc); 241 CPUClass *cc = CPU_CLASS(oc); 242 XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc); 243 244 device_class_set_parent_realize(dc, xtensa_cpu_realizefn, 245 &xcc->parent_realize); 246 247 device_class_set_parent_reset(dc, xtensa_cpu_reset, &xcc->parent_reset); 248 249 cc->class_by_name = xtensa_cpu_class_by_name; 250 cc->has_work = xtensa_cpu_has_work; 251 cc->dump_state = xtensa_cpu_dump_state; 252 cc->set_pc = xtensa_cpu_set_pc; 253 cc->get_pc = xtensa_cpu_get_pc; 254 cc->gdb_read_register = xtensa_cpu_gdb_read_register; 255 cc->gdb_write_register = xtensa_cpu_gdb_write_register; 256 cc->gdb_stop_before_watchpoint = true; 257 #ifndef CONFIG_USER_ONLY 258 cc->sysemu_ops = &xtensa_sysemu_ops; 259 dc->vmsd = &vmstate_xtensa_cpu; 260 #endif 261 cc->disas_set_info = xtensa_cpu_disas_set_info; 262 cc->tcg_ops = &xtensa_tcg_ops; 263 } 264 265 static const TypeInfo xtensa_cpu_type_info = { 266 .name = TYPE_XTENSA_CPU, 267 .parent = TYPE_CPU, 268 .instance_size = sizeof(XtensaCPU), 269 .instance_init = xtensa_cpu_initfn, 270 .abstract = true, 271 .class_size = sizeof(XtensaCPUClass), 272 .class_init = xtensa_cpu_class_init, 273 }; 274 275 static void xtensa_cpu_register_types(void) 276 { 277 type_register_static(&xtensa_cpu_type_info); 278 } 279 280 type_init(xtensa_cpu_register_types) 281