xref: /openbmc/qemu/target/xtensa/cpu.c (revision 29318db1)
1 /*
2  * QEMU Xtensa CPU
3  *
4  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
5  * Copyright (c) 2012 SUSE LINUX Products GmbH
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions are met:
10  *     * Redistributions of source code must retain the above copyright
11  *       notice, this list of conditions and the following disclaimer.
12  *     * Redistributions in binary form must reproduce the above copyright
13  *       notice, this list of conditions and the following disclaimer in the
14  *       documentation and/or other materials provided with the distribution.
15  *     * Neither the name of the Open Source and Linux Lab nor the
16  *       names of its contributors may be used to endorse or promote products
17  *       derived from this software without specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29  */
30 
31 #include "qemu/osdep.h"
32 #include "qapi/error.h"
33 #include "cpu.h"
34 #include "fpu/softfloat.h"
35 #include "qemu/module.h"
36 #include "migration/vmstate.h"
37 #include "hw/qdev-clock.h"
38 #ifndef CONFIG_USER_ONLY
39 #include "exec/memory.h"
40 #endif
41 
42 
43 static void xtensa_cpu_set_pc(CPUState *cs, vaddr value)
44 {
45     XtensaCPU *cpu = XTENSA_CPU(cs);
46 
47     cpu->env.pc = value;
48 }
49 
50 static vaddr xtensa_cpu_get_pc(CPUState *cs)
51 {
52     XtensaCPU *cpu = XTENSA_CPU(cs);
53 
54     return cpu->env.pc;
55 }
56 
57 static void xtensa_restore_state_to_opc(CPUState *cs,
58                                         const TranslationBlock *tb,
59                                         const uint64_t *data)
60 {
61     XtensaCPU *cpu = XTENSA_CPU(cs);
62 
63     cpu->env.pc = data[0];
64 }
65 
66 static bool xtensa_cpu_has_work(CPUState *cs)
67 {
68 #ifndef CONFIG_USER_ONLY
69     XtensaCPU *cpu = XTENSA_CPU(cs);
70 
71     return !cpu->env.runstall && cpu->env.pending_irq_level;
72 #else
73     return true;
74 #endif
75 }
76 
77 static int xtensa_cpu_mmu_index(CPUState *cs, bool ifetch)
78 {
79     return xtensa_get_cring(cpu_env(cs));
80 }
81 
82 #ifdef CONFIG_USER_ONLY
83 static bool abi_call0;
84 
85 void xtensa_set_abi_call0(void)
86 {
87     abi_call0 = true;
88 }
89 
90 bool xtensa_abi_call0(void)
91 {
92     return abi_call0;
93 }
94 #endif
95 
96 static void xtensa_cpu_reset_hold(Object *obj, ResetType type)
97 {
98     CPUState *cs = CPU(obj);
99     XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj);
100     CPUXtensaState *env = cpu_env(cs);
101     bool dfpu = xtensa_option_enabled(env->config,
102                                       XTENSA_OPTION_DFP_COPROCESSOR);
103 
104     if (xcc->parent_phases.hold) {
105         xcc->parent_phases.hold(obj, type);
106     }
107 
108     env->pc = env->config->exception_vector[EXC_RESET0 + env->static_vectors];
109     env->sregs[LITBASE] &= ~1;
110 #ifndef CONFIG_USER_ONLY
111     env->sregs[PS] = xtensa_option_enabled(env->config,
112             XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10;
113     env->pending_irq_level = 0;
114 #else
115     env->sregs[PS] = PS_UM | (3 << PS_RING_SHIFT);
116     if (xtensa_option_enabled(env->config,
117                               XTENSA_OPTION_WINDOWED_REGISTER) &&
118         !xtensa_abi_call0()) {
119         env->sregs[PS] |= PS_WOE;
120     }
121     env->sregs[CPENABLE] = 0xff;
122 #endif
123     env->sregs[VECBASE] = env->config->vecbase;
124     env->sregs[IBREAKENABLE] = 0;
125     env->sregs[MEMCTL] = MEMCTL_IL0EN & env->config->memctl_mask;
126     env->sregs[ATOMCTL] = xtensa_option_enabled(env->config,
127             XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15;
128     env->sregs[CONFIGID0] = env->config->configid[0];
129     env->sregs[CONFIGID1] = env->config->configid[1];
130     env->exclusive_addr = -1;
131 
132 #ifndef CONFIG_USER_ONLY
133     reset_mmu(env);
134     cs->halted = env->runstall;
135 #endif
136     set_no_signaling_nans(!dfpu, &env->fp_status);
137     set_use_first_nan(!dfpu, &env->fp_status);
138 }
139 
140 static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model)
141 {
142     ObjectClass *oc;
143     char *typename;
144 
145     typename = g_strdup_printf(XTENSA_CPU_TYPE_NAME("%s"), cpu_model);
146     oc = object_class_by_name(typename);
147     g_free(typename);
148 
149     return oc;
150 }
151 
152 static void xtensa_cpu_disas_set_info(CPUState *cs, disassemble_info *info)
153 {
154     XtensaCPU *cpu = XTENSA_CPU(cs);
155 
156     info->private_data = cpu->env.config->isa;
157     info->print_insn = print_insn_xtensa;
158 }
159 
160 static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp)
161 {
162     CPUState *cs = CPU(dev);
163     XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev);
164     Error *local_err = NULL;
165 
166 #ifndef CONFIG_USER_ONLY
167     xtensa_irq_init(&XTENSA_CPU(dev)->env);
168 #endif
169 
170     cpu_exec_realizefn(cs, &local_err);
171     if (local_err != NULL) {
172         error_propagate(errp, local_err);
173         return;
174     }
175 
176     cs->gdb_num_regs = xcc->config->gdb_regmap.num_regs;
177 
178     qemu_init_vcpu(cs);
179 
180     xcc->parent_realize(dev, errp);
181 }
182 
183 static void xtensa_cpu_initfn(Object *obj)
184 {
185     XtensaCPU *cpu = XTENSA_CPU(obj);
186     XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj);
187     CPUXtensaState *env = &cpu->env;
188 
189     env->config = xcc->config;
190 
191 #ifndef CONFIG_USER_ONLY
192     env->address_space_er = g_malloc(sizeof(*env->address_space_er));
193     env->system_er = g_malloc(sizeof(*env->system_er));
194     memory_region_init_io(env->system_er, obj, NULL, env, "er",
195                           UINT64_C(0x100000000));
196     address_space_init(env->address_space_er, env->system_er, "ER");
197 
198     cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu, 0);
199     clock_set_hz(cpu->clock, env->config->clock_freq_khz * 1000);
200 #endif
201 }
202 
203 XtensaCPU *xtensa_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk)
204 {
205     DeviceState *cpu;
206 
207     cpu = DEVICE(object_new(cpu_type));
208     qdev_connect_clock_in(cpu, "clk-in", cpu_refclk);
209     qdev_realize(cpu, NULL, &error_abort);
210 
211     return XTENSA_CPU(cpu);
212 }
213 
214 #ifndef CONFIG_USER_ONLY
215 static const VMStateDescription vmstate_xtensa_cpu = {
216     .name = "cpu",
217     .unmigratable = 1,
218 };
219 
220 #include "hw/core/sysemu-cpu-ops.h"
221 
222 static const struct SysemuCPUOps xtensa_sysemu_ops = {
223     .get_phys_page_debug = xtensa_cpu_get_phys_page_debug,
224 };
225 #endif
226 
227 #include "hw/core/tcg-cpu-ops.h"
228 
229 static const TCGCPUOps xtensa_tcg_ops = {
230     .initialize = xtensa_translate_init,
231     .debug_excp_handler = xtensa_breakpoint_handler,
232     .restore_state_to_opc = xtensa_restore_state_to_opc,
233 
234 #ifndef CONFIG_USER_ONLY
235     .tlb_fill = xtensa_cpu_tlb_fill,
236     .cpu_exec_interrupt = xtensa_cpu_exec_interrupt,
237     .cpu_exec_halt = xtensa_cpu_has_work,
238     .do_interrupt = xtensa_cpu_do_interrupt,
239     .do_transaction_failed = xtensa_cpu_do_transaction_failed,
240     .do_unaligned_access = xtensa_cpu_do_unaligned_access,
241     .debug_check_breakpoint = xtensa_debug_check_breakpoint,
242 #endif /* !CONFIG_USER_ONLY */
243 };
244 
245 static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
246 {
247     DeviceClass *dc = DEVICE_CLASS(oc);
248     CPUClass *cc = CPU_CLASS(oc);
249     XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc);
250     ResettableClass *rc = RESETTABLE_CLASS(oc);
251 
252     device_class_set_parent_realize(dc, xtensa_cpu_realizefn,
253                                     &xcc->parent_realize);
254 
255     resettable_class_set_parent_phases(rc, NULL, xtensa_cpu_reset_hold, NULL,
256                                        &xcc->parent_phases);
257 
258     cc->class_by_name = xtensa_cpu_class_by_name;
259     cc->has_work = xtensa_cpu_has_work;
260     cc->mmu_index = xtensa_cpu_mmu_index;
261     cc->dump_state = xtensa_cpu_dump_state;
262     cc->set_pc = xtensa_cpu_set_pc;
263     cc->get_pc = xtensa_cpu_get_pc;
264     cc->gdb_read_register = xtensa_cpu_gdb_read_register;
265     cc->gdb_write_register = xtensa_cpu_gdb_write_register;
266     cc->gdb_stop_before_watchpoint = true;
267 #ifndef CONFIG_USER_ONLY
268     cc->sysemu_ops = &xtensa_sysemu_ops;
269     dc->vmsd = &vmstate_xtensa_cpu;
270 #endif
271     cc->disas_set_info = xtensa_cpu_disas_set_info;
272     cc->tcg_ops = &xtensa_tcg_ops;
273 }
274 
275 static const TypeInfo xtensa_cpu_type_info = {
276     .name = TYPE_XTENSA_CPU,
277     .parent = TYPE_CPU,
278     .instance_size = sizeof(XtensaCPU),
279     .instance_align = __alignof(XtensaCPU),
280     .instance_init = xtensa_cpu_initfn,
281     .abstract = true,
282     .class_size = sizeof(XtensaCPUClass),
283     .class_init = xtensa_cpu_class_init,
284 };
285 
286 static void xtensa_cpu_register_types(void)
287 {
288     type_register_static(&xtensa_cpu_type_info);
289 }
290 
291 type_init(xtensa_cpu_register_types)
292