1 /* 2 * QEMU Xtensa CPU 3 * 4 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. 5 * Copyright (c) 2012 SUSE LINUX Products GmbH 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * * Neither the name of the Open Source and Linux Lab nor the 16 * names of its contributors may be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qapi/error.h" 33 #include "cpu.h" 34 #include "fpu/softfloat.h" 35 #include "qemu/module.h" 36 #include "migration/vmstate.h" 37 #include "hw/qdev-clock.h" 38 #ifndef CONFIG_USER_ONLY 39 #include "exec/memory.h" 40 #endif 41 42 43 static void xtensa_cpu_set_pc(CPUState *cs, vaddr value) 44 { 45 XtensaCPU *cpu = XTENSA_CPU(cs); 46 47 cpu->env.pc = value; 48 } 49 50 static vaddr xtensa_cpu_get_pc(CPUState *cs) 51 { 52 XtensaCPU *cpu = XTENSA_CPU(cs); 53 54 return cpu->env.pc; 55 } 56 57 static void xtensa_restore_state_to_opc(CPUState *cs, 58 const TranslationBlock *tb, 59 const uint64_t *data) 60 { 61 XtensaCPU *cpu = XTENSA_CPU(cs); 62 63 cpu->env.pc = data[0]; 64 } 65 66 static bool xtensa_cpu_has_work(CPUState *cs) 67 { 68 #ifndef CONFIG_USER_ONLY 69 XtensaCPU *cpu = XTENSA_CPU(cs); 70 71 return !cpu->env.runstall && cpu->env.pending_irq_level; 72 #else 73 return true; 74 #endif 75 } 76 77 #ifdef CONFIG_USER_ONLY 78 static bool abi_call0; 79 80 void xtensa_set_abi_call0(void) 81 { 82 abi_call0 = true; 83 } 84 85 bool xtensa_abi_call0(void) 86 { 87 return abi_call0; 88 } 89 #endif 90 91 static void xtensa_cpu_reset_hold(Object *obj) 92 { 93 CPUState *s = CPU(obj); 94 XtensaCPU *cpu = XTENSA_CPU(s); 95 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(cpu); 96 CPUXtensaState *env = &cpu->env; 97 bool dfpu = xtensa_option_enabled(env->config, 98 XTENSA_OPTION_DFP_COPROCESSOR); 99 100 if (xcc->parent_phases.hold) { 101 xcc->parent_phases.hold(obj); 102 } 103 104 env->pc = env->config->exception_vector[EXC_RESET0 + env->static_vectors]; 105 env->sregs[LITBASE] &= ~1; 106 #ifndef CONFIG_USER_ONLY 107 env->sregs[PS] = xtensa_option_enabled(env->config, 108 XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10; 109 env->pending_irq_level = 0; 110 #else 111 env->sregs[PS] = PS_UM | (3 << PS_RING_SHIFT); 112 if (xtensa_option_enabled(env->config, 113 XTENSA_OPTION_WINDOWED_REGISTER) && 114 !xtensa_abi_call0()) { 115 env->sregs[PS] |= PS_WOE; 116 } 117 env->sregs[CPENABLE] = 0xff; 118 #endif 119 env->sregs[VECBASE] = env->config->vecbase; 120 env->sregs[IBREAKENABLE] = 0; 121 env->sregs[MEMCTL] = MEMCTL_IL0EN & env->config->memctl_mask; 122 env->sregs[ATOMCTL] = xtensa_option_enabled(env->config, 123 XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15; 124 env->sregs[CONFIGID0] = env->config->configid[0]; 125 env->sregs[CONFIGID1] = env->config->configid[1]; 126 env->exclusive_addr = -1; 127 128 #ifndef CONFIG_USER_ONLY 129 reset_mmu(env); 130 s->halted = env->runstall; 131 #endif 132 set_no_signaling_nans(!dfpu, &env->fp_status); 133 set_use_first_nan(!dfpu, &env->fp_status); 134 } 135 136 static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model) 137 { 138 ObjectClass *oc; 139 char *typename; 140 141 typename = g_strdup_printf(XTENSA_CPU_TYPE_NAME("%s"), cpu_model); 142 oc = object_class_by_name(typename); 143 g_free(typename); 144 if (oc == NULL || !object_class_dynamic_cast(oc, TYPE_XTENSA_CPU) || 145 object_class_is_abstract(oc)) { 146 return NULL; 147 } 148 return oc; 149 } 150 151 static void xtensa_cpu_disas_set_info(CPUState *cs, disassemble_info *info) 152 { 153 XtensaCPU *cpu = XTENSA_CPU(cs); 154 155 info->private_data = cpu->env.config->isa; 156 info->print_insn = print_insn_xtensa; 157 } 158 159 static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp) 160 { 161 CPUState *cs = CPU(dev); 162 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev); 163 Error *local_err = NULL; 164 165 #ifndef CONFIG_USER_ONLY 166 xtensa_irq_init(&XTENSA_CPU(dev)->env); 167 #endif 168 169 cpu_exec_realizefn(cs, &local_err); 170 if (local_err != NULL) { 171 error_propagate(errp, local_err); 172 return; 173 } 174 175 cs->gdb_num_regs = xcc->config->gdb_regmap.num_regs; 176 177 qemu_init_vcpu(cs); 178 179 xcc->parent_realize(dev, errp); 180 } 181 182 static void xtensa_cpu_initfn(Object *obj) 183 { 184 XtensaCPU *cpu = XTENSA_CPU(obj); 185 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj); 186 CPUXtensaState *env = &cpu->env; 187 188 env->config = xcc->config; 189 190 #ifndef CONFIG_USER_ONLY 191 env->address_space_er = g_malloc(sizeof(*env->address_space_er)); 192 env->system_er = g_malloc(sizeof(*env->system_er)); 193 memory_region_init_io(env->system_er, obj, NULL, env, "er", 194 UINT64_C(0x100000000)); 195 address_space_init(env->address_space_er, env->system_er, "ER"); 196 197 cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu, 0); 198 clock_set_hz(cpu->clock, env->config->clock_freq_khz * 1000); 199 #endif 200 } 201 202 XtensaCPU *xtensa_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk) 203 { 204 DeviceState *cpu; 205 206 cpu = DEVICE(object_new(cpu_type)); 207 qdev_connect_clock_in(cpu, "clk-in", cpu_refclk); 208 qdev_realize(cpu, NULL, &error_abort); 209 210 return XTENSA_CPU(cpu); 211 } 212 213 #ifndef CONFIG_USER_ONLY 214 static const VMStateDescription vmstate_xtensa_cpu = { 215 .name = "cpu", 216 .unmigratable = 1, 217 }; 218 219 #include "hw/core/sysemu-cpu-ops.h" 220 221 static const struct SysemuCPUOps xtensa_sysemu_ops = { 222 .get_phys_page_debug = xtensa_cpu_get_phys_page_debug, 223 }; 224 #endif 225 226 #include "hw/core/tcg-cpu-ops.h" 227 228 static const struct TCGCPUOps xtensa_tcg_ops = { 229 .initialize = xtensa_translate_init, 230 .debug_excp_handler = xtensa_breakpoint_handler, 231 .restore_state_to_opc = xtensa_restore_state_to_opc, 232 233 #ifndef CONFIG_USER_ONLY 234 .tlb_fill = xtensa_cpu_tlb_fill, 235 .cpu_exec_interrupt = xtensa_cpu_exec_interrupt, 236 .do_interrupt = xtensa_cpu_do_interrupt, 237 .do_transaction_failed = xtensa_cpu_do_transaction_failed, 238 .do_unaligned_access = xtensa_cpu_do_unaligned_access, 239 #endif /* !CONFIG_USER_ONLY */ 240 }; 241 242 static void xtensa_cpu_class_init(ObjectClass *oc, void *data) 243 { 244 DeviceClass *dc = DEVICE_CLASS(oc); 245 CPUClass *cc = CPU_CLASS(oc); 246 XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc); 247 ResettableClass *rc = RESETTABLE_CLASS(oc); 248 249 device_class_set_parent_realize(dc, xtensa_cpu_realizefn, 250 &xcc->parent_realize); 251 252 resettable_class_set_parent_phases(rc, NULL, xtensa_cpu_reset_hold, NULL, 253 &xcc->parent_phases); 254 255 cc->class_by_name = xtensa_cpu_class_by_name; 256 cc->has_work = xtensa_cpu_has_work; 257 cc->dump_state = xtensa_cpu_dump_state; 258 cc->set_pc = xtensa_cpu_set_pc; 259 cc->get_pc = xtensa_cpu_get_pc; 260 cc->gdb_read_register = xtensa_cpu_gdb_read_register; 261 cc->gdb_write_register = xtensa_cpu_gdb_write_register; 262 cc->gdb_stop_before_watchpoint = true; 263 #ifndef CONFIG_USER_ONLY 264 cc->sysemu_ops = &xtensa_sysemu_ops; 265 dc->vmsd = &vmstate_xtensa_cpu; 266 #endif 267 cc->disas_set_info = xtensa_cpu_disas_set_info; 268 cc->tcg_ops = &xtensa_tcg_ops; 269 } 270 271 static const TypeInfo xtensa_cpu_type_info = { 272 .name = TYPE_XTENSA_CPU, 273 .parent = TYPE_CPU, 274 .instance_size = sizeof(XtensaCPU), 275 .instance_align = __alignof(XtensaCPU), 276 .instance_init = xtensa_cpu_initfn, 277 .abstract = true, 278 .class_size = sizeof(XtensaCPUClass), 279 .class_init = xtensa_cpu_class_init, 280 }; 281 282 static void xtensa_cpu_register_types(void) 283 { 284 type_register_static(&xtensa_cpu_type_info); 285 } 286 287 type_init(xtensa_cpu_register_types) 288