1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * QEMU Xtensa CPU 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. 5fcf5ef2aSThomas Huth * Copyright (c) 2012 SUSE LINUX Products GmbH 6fcf5ef2aSThomas Huth * All rights reserved. 7fcf5ef2aSThomas Huth * 8fcf5ef2aSThomas Huth * Redistribution and use in source and binary forms, with or without 9fcf5ef2aSThomas Huth * modification, are permitted provided that the following conditions are met: 10fcf5ef2aSThomas Huth * * Redistributions of source code must retain the above copyright 11fcf5ef2aSThomas Huth * notice, this list of conditions and the following disclaimer. 12fcf5ef2aSThomas Huth * * Redistributions in binary form must reproduce the above copyright 13fcf5ef2aSThomas Huth * notice, this list of conditions and the following disclaimer in the 14fcf5ef2aSThomas Huth * documentation and/or other materials provided with the distribution. 15fcf5ef2aSThomas Huth * * Neither the name of the Open Source and Linux Lab nor the 16fcf5ef2aSThomas Huth * names of its contributors may be used to endorse or promote products 17fcf5ef2aSThomas Huth * derived from this software without specific prior written permission. 18fcf5ef2aSThomas Huth * 19fcf5ef2aSThomas Huth * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20fcf5ef2aSThomas Huth * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21fcf5ef2aSThomas Huth * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22fcf5ef2aSThomas Huth * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 23fcf5ef2aSThomas Huth * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24fcf5ef2aSThomas Huth * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25fcf5ef2aSThomas Huth * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 26fcf5ef2aSThomas Huth * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27fcf5ef2aSThomas Huth * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 28fcf5ef2aSThomas Huth * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29fcf5ef2aSThomas Huth */ 30fcf5ef2aSThomas Huth 31fcf5ef2aSThomas Huth #include "qemu/osdep.h" 32fcf5ef2aSThomas Huth #include "qapi/error.h" 33fcf5ef2aSThomas Huth #include "cpu.h" 34cfa9f051SMax Filippov #include "fpu/softfloat.h" 350b8fa32fSMarkus Armbruster #include "qemu/module.h" 36fcf5ef2aSThomas Huth #include "migration/vmstate.h" 37*9e377be1SMax Filippov #include "hw/qdev-clock.h" 38fcf5ef2aSThomas Huth 39fcf5ef2aSThomas Huth 40fcf5ef2aSThomas Huth static void xtensa_cpu_set_pc(CPUState *cs, vaddr value) 41fcf5ef2aSThomas Huth { 42fcf5ef2aSThomas Huth XtensaCPU *cpu = XTENSA_CPU(cs); 43fcf5ef2aSThomas Huth 44fcf5ef2aSThomas Huth cpu->env.pc = value; 45fcf5ef2aSThomas Huth } 46fcf5ef2aSThomas Huth 47fcf5ef2aSThomas Huth static bool xtensa_cpu_has_work(CPUState *cs) 48fcf5ef2aSThomas Huth { 49ba7651fbSMax Filippov #ifndef CONFIG_USER_ONLY 50fcf5ef2aSThomas Huth XtensaCPU *cpu = XTENSA_CPU(cs); 51fcf5ef2aSThomas Huth 52bd527a83SMax Filippov return !cpu->env.runstall && cpu->env.pending_irq_level; 53ba7651fbSMax Filippov #else 54ba7651fbSMax Filippov return true; 55ba7651fbSMax Filippov #endif 56fcf5ef2aSThomas Huth } 57fcf5ef2aSThomas Huth 58130ea832SMax Filippov #ifdef CONFIG_USER_ONLY 59130ea832SMax Filippov static bool abi_call0; 60130ea832SMax Filippov 61130ea832SMax Filippov void xtensa_set_abi_call0(void) 62130ea832SMax Filippov { 63130ea832SMax Filippov abi_call0 = true; 64130ea832SMax Filippov } 65130ea832SMax Filippov 66130ea832SMax Filippov bool xtensa_abi_call0(void) 67130ea832SMax Filippov { 68130ea832SMax Filippov return abi_call0; 69130ea832SMax Filippov } 70130ea832SMax Filippov #endif 71130ea832SMax Filippov 72781c67caSPeter Maydell static void xtensa_cpu_reset(DeviceState *dev) 73fcf5ef2aSThomas Huth { 74781c67caSPeter Maydell CPUState *s = CPU(dev); 75fcf5ef2aSThomas Huth XtensaCPU *cpu = XTENSA_CPU(s); 76fcf5ef2aSThomas Huth XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(cpu); 77fcf5ef2aSThomas Huth CPUXtensaState *env = &cpu->env; 78cfa9f051SMax Filippov bool dfpu = xtensa_option_enabled(env->config, 79cfa9f051SMax Filippov XTENSA_OPTION_DFP_COPROCESSOR); 80fcf5ef2aSThomas Huth 81781c67caSPeter Maydell xcc->parent_reset(dev); 82fcf5ef2aSThomas Huth 8317ab14acSMax Filippov env->pc = env->config->exception_vector[EXC_RESET0 + env->static_vectors]; 84fcf5ef2aSThomas Huth env->sregs[LITBASE] &= ~1; 85ba7651fbSMax Filippov #ifndef CONFIG_USER_ONLY 86fcf5ef2aSThomas Huth env->sregs[PS] = xtensa_option_enabled(env->config, 87fcf5ef2aSThomas Huth XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10; 88ba7651fbSMax Filippov env->pending_irq_level = 0; 89ba7651fbSMax Filippov #else 90130ea832SMax Filippov env->sregs[PS] = PS_UM | (3 << PS_RING_SHIFT); 91130ea832SMax Filippov if (xtensa_option_enabled(env->config, 92130ea832SMax Filippov XTENSA_OPTION_WINDOWED_REGISTER) && 93130ea832SMax Filippov !xtensa_abi_call0()) { 94130ea832SMax Filippov env->sregs[PS] |= PS_WOE; 95130ea832SMax Filippov } 96ab97f050SMax Filippov env->sregs[CPENABLE] = 0xff; 97ba7651fbSMax Filippov #endif 98fcf5ef2aSThomas Huth env->sregs[VECBASE] = env->config->vecbase; 99fcf5ef2aSThomas Huth env->sregs[IBREAKENABLE] = 0; 1009e03ade4SMax Filippov env->sregs[MEMCTL] = MEMCTL_IL0EN & env->config->memctl_mask; 101fcf5ef2aSThomas Huth env->sregs[ATOMCTL] = xtensa_option_enabled(env->config, 102fcf5ef2aSThomas Huth XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15; 103fcf5ef2aSThomas Huth env->sregs[CONFIGID0] = env->config->configid[0]; 104fcf5ef2aSThomas Huth env->sregs[CONFIGID1] = env->config->configid[1]; 105b345e140SMax Filippov env->exclusive_addr = -1; 106fcf5ef2aSThomas Huth 107ba7651fbSMax Filippov #ifndef CONFIG_USER_ONLY 108fcf5ef2aSThomas Huth reset_mmu(env); 109bd527a83SMax Filippov s->halted = env->runstall; 110ba7651fbSMax Filippov #endif 111cfa9f051SMax Filippov set_no_signaling_nans(!dfpu, &env->fp_status); 112cfa9f051SMax Filippov set_use_first_nan(!dfpu, &env->fp_status); 113fcf5ef2aSThomas Huth } 114fcf5ef2aSThomas Huth 115fcf5ef2aSThomas Huth static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model) 116fcf5ef2aSThomas Huth { 117fcf5ef2aSThomas Huth ObjectClass *oc; 118fcf5ef2aSThomas Huth char *typename; 119fcf5ef2aSThomas Huth 120a5247d76SIgor Mammedov typename = g_strdup_printf(XTENSA_CPU_TYPE_NAME("%s"), cpu_model); 121fcf5ef2aSThomas Huth oc = object_class_by_name(typename); 122fcf5ef2aSThomas Huth g_free(typename); 123fcf5ef2aSThomas Huth if (oc == NULL || !object_class_dynamic_cast(oc, TYPE_XTENSA_CPU) || 124fcf5ef2aSThomas Huth object_class_is_abstract(oc)) { 125fcf5ef2aSThomas Huth return NULL; 126fcf5ef2aSThomas Huth } 127fcf5ef2aSThomas Huth return oc; 128fcf5ef2aSThomas Huth } 129fcf5ef2aSThomas Huth 1305a6539e6SMax Filippov static void xtensa_cpu_disas_set_info(CPUState *cs, disassemble_info *info) 1315a6539e6SMax Filippov { 1325a6539e6SMax Filippov XtensaCPU *cpu = XTENSA_CPU(cs); 1335a6539e6SMax Filippov 1345a6539e6SMax Filippov info->private_data = cpu->env.config->isa; 1355a6539e6SMax Filippov info->print_insn = print_insn_xtensa; 1365a6539e6SMax Filippov } 1375a6539e6SMax Filippov 138fcf5ef2aSThomas Huth static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp) 139fcf5ef2aSThomas Huth { 140fcf5ef2aSThomas Huth CPUState *cs = CPU(dev); 141fcf5ef2aSThomas Huth XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev); 142fcf5ef2aSThomas Huth Error *local_err = NULL; 143fcf5ef2aSThomas Huth 144ba7651fbSMax Filippov #ifndef CONFIG_USER_ONLY 145ba7651fbSMax Filippov xtensa_irq_init(&XTENSA_CPU(dev)->env); 146ba7651fbSMax Filippov #endif 1478e36271bSIgor Mammedov 148fcf5ef2aSThomas Huth cpu_exec_realizefn(cs, &local_err); 149fcf5ef2aSThomas Huth if (local_err != NULL) { 150fcf5ef2aSThomas Huth error_propagate(errp, local_err); 151fcf5ef2aSThomas Huth return; 152fcf5ef2aSThomas Huth } 153fcf5ef2aSThomas Huth 154fcf5ef2aSThomas Huth cs->gdb_num_regs = xcc->config->gdb_regmap.num_regs; 155fcf5ef2aSThomas Huth 156fcf5ef2aSThomas Huth qemu_init_vcpu(cs); 157fcf5ef2aSThomas Huth 158fcf5ef2aSThomas Huth xcc->parent_realize(dev, errp); 159fcf5ef2aSThomas Huth } 160fcf5ef2aSThomas Huth 161fcf5ef2aSThomas Huth static void xtensa_cpu_initfn(Object *obj) 162fcf5ef2aSThomas Huth { 163fcf5ef2aSThomas Huth XtensaCPU *cpu = XTENSA_CPU(obj); 164fcf5ef2aSThomas Huth XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj); 165fcf5ef2aSThomas Huth CPUXtensaState *env = &cpu->env; 166fcf5ef2aSThomas Huth 1677506ed90SRichard Henderson cpu_set_cpustate_pointers(cpu); 168fcf5ef2aSThomas Huth env->config = xcc->config; 169fcf5ef2aSThomas Huth 170ba7651fbSMax Filippov #ifndef CONFIG_USER_ONLY 1713a3c9dc4SMax Filippov env->address_space_er = g_malloc(sizeof(*env->address_space_er)); 1723a3c9dc4SMax Filippov env->system_er = g_malloc(sizeof(*env->system_er)); 17309d98b69SThomas Huth memory_region_init_io(env->system_er, obj, NULL, env, "er", 1743a3c9dc4SMax Filippov UINT64_C(0x100000000)); 1753a3c9dc4SMax Filippov address_space_init(env->address_space_er, env->system_er, "ER"); 176*9e377be1SMax Filippov 177*9e377be1SMax Filippov cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu, 0); 178*9e377be1SMax Filippov clock_set_hz(cpu->clock, env->config->clock_freq_khz * 1000); 179ba7651fbSMax Filippov #endif 180fcf5ef2aSThomas Huth } 181fcf5ef2aSThomas Huth 182*9e377be1SMax Filippov XtensaCPU *xtensa_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk) 183*9e377be1SMax Filippov { 184*9e377be1SMax Filippov DeviceState *cpu; 185*9e377be1SMax Filippov 186*9e377be1SMax Filippov cpu = DEVICE(object_new(cpu_type)); 187*9e377be1SMax Filippov qdev_connect_clock_in(cpu, "clk-in", cpu_refclk); 188*9e377be1SMax Filippov qdev_realize(cpu, NULL, &error_abort); 189*9e377be1SMax Filippov 190*9e377be1SMax Filippov return XTENSA_CPU(cpu); 191*9e377be1SMax Filippov } 192*9e377be1SMax Filippov 1934336073bSPhilippe Mathieu-Daudé #ifndef CONFIG_USER_ONLY 194fcf5ef2aSThomas Huth static const VMStateDescription vmstate_xtensa_cpu = { 195fcf5ef2aSThomas Huth .name = "cpu", 196fcf5ef2aSThomas Huth .unmigratable = 1, 197fcf5ef2aSThomas Huth }; 1988b80bd28SPhilippe Mathieu-Daudé 1998b80bd28SPhilippe Mathieu-Daudé #include "hw/core/sysemu-cpu-ops.h" 2008b80bd28SPhilippe Mathieu-Daudé 2018b80bd28SPhilippe Mathieu-Daudé static const struct SysemuCPUOps xtensa_sysemu_ops = { 20208928c6dSPhilippe Mathieu-Daudé .get_phys_page_debug = xtensa_cpu_get_phys_page_debug, 2038b80bd28SPhilippe Mathieu-Daudé }; 2044336073bSPhilippe Mathieu-Daudé #endif 205fcf5ef2aSThomas Huth 20678271684SClaudio Fontana #include "hw/core/tcg-cpu-ops.h" 20778271684SClaudio Fontana 20811906557SRichard Henderson static const struct TCGCPUOps xtensa_tcg_ops = { 20978271684SClaudio Fontana .initialize = xtensa_translate_init, 21078271684SClaudio Fontana .debug_excp_handler = xtensa_breakpoint_handler, 21178271684SClaudio Fontana 21278271684SClaudio Fontana #ifndef CONFIG_USER_ONLY 2136407f64fSRichard Henderson .tlb_fill = xtensa_cpu_tlb_fill, 214f364a7f9SPhilippe Mathieu-Daudé .cpu_exec_interrupt = xtensa_cpu_exec_interrupt, 21578271684SClaudio Fontana .do_interrupt = xtensa_cpu_do_interrupt, 21678271684SClaudio Fontana .do_transaction_failed = xtensa_cpu_do_transaction_failed, 21778271684SClaudio Fontana .do_unaligned_access = xtensa_cpu_do_unaligned_access, 21878271684SClaudio Fontana #endif /* !CONFIG_USER_ONLY */ 21978271684SClaudio Fontana }; 22078271684SClaudio Fontana 221fcf5ef2aSThomas Huth static void xtensa_cpu_class_init(ObjectClass *oc, void *data) 222fcf5ef2aSThomas Huth { 223fcf5ef2aSThomas Huth DeviceClass *dc = DEVICE_CLASS(oc); 224fcf5ef2aSThomas Huth CPUClass *cc = CPU_CLASS(oc); 225fcf5ef2aSThomas Huth XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc); 226fcf5ef2aSThomas Huth 227bf853881SPhilippe Mathieu-Daudé device_class_set_parent_realize(dc, xtensa_cpu_realizefn, 228bf853881SPhilippe Mathieu-Daudé &xcc->parent_realize); 229fcf5ef2aSThomas Huth 230781c67caSPeter Maydell device_class_set_parent_reset(dc, xtensa_cpu_reset, &xcc->parent_reset); 231fcf5ef2aSThomas Huth 232fcf5ef2aSThomas Huth cc->class_by_name = xtensa_cpu_class_by_name; 233fcf5ef2aSThomas Huth cc->has_work = xtensa_cpu_has_work; 234fcf5ef2aSThomas Huth cc->dump_state = xtensa_cpu_dump_state; 235fcf5ef2aSThomas Huth cc->set_pc = xtensa_cpu_set_pc; 236fcf5ef2aSThomas Huth cc->gdb_read_register = xtensa_cpu_gdb_read_register; 237fcf5ef2aSThomas Huth cc->gdb_write_register = xtensa_cpu_gdb_write_register; 238fcf5ef2aSThomas Huth cc->gdb_stop_before_watchpoint = true; 239b008c456SRichard Henderson #ifndef CONFIG_USER_ONLY 2408b80bd28SPhilippe Mathieu-Daudé cc->sysemu_ops = &xtensa_sysemu_ops; 2414336073bSPhilippe Mathieu-Daudé dc->vmsd = &vmstate_xtensa_cpu; 242fcf5ef2aSThomas Huth #endif 2435a6539e6SMax Filippov cc->disas_set_info = xtensa_cpu_disas_set_info; 24478271684SClaudio Fontana cc->tcg_ops = &xtensa_tcg_ops; 245fcf5ef2aSThomas Huth } 246fcf5ef2aSThomas Huth 247fcf5ef2aSThomas Huth static const TypeInfo xtensa_cpu_type_info = { 248fcf5ef2aSThomas Huth .name = TYPE_XTENSA_CPU, 249fcf5ef2aSThomas Huth .parent = TYPE_CPU, 250fcf5ef2aSThomas Huth .instance_size = sizeof(XtensaCPU), 251fcf5ef2aSThomas Huth .instance_init = xtensa_cpu_initfn, 252fcf5ef2aSThomas Huth .abstract = true, 253fcf5ef2aSThomas Huth .class_size = sizeof(XtensaCPUClass), 254fcf5ef2aSThomas Huth .class_init = xtensa_cpu_class_init, 255fcf5ef2aSThomas Huth }; 256fcf5ef2aSThomas Huth 257fcf5ef2aSThomas Huth static void xtensa_cpu_register_types(void) 258fcf5ef2aSThomas Huth { 259fcf5ef2aSThomas Huth type_register_static(&xtensa_cpu_type_info); 260fcf5ef2aSThomas Huth } 261fcf5ef2aSThomas Huth 262fcf5ef2aSThomas Huth type_init(xtensa_cpu_register_types) 263