1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * QEMU Xtensa CPU 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. 5fcf5ef2aSThomas Huth * Copyright (c) 2012 SUSE LINUX Products GmbH 6fcf5ef2aSThomas Huth * All rights reserved. 7fcf5ef2aSThomas Huth * 8fcf5ef2aSThomas Huth * Redistribution and use in source and binary forms, with or without 9fcf5ef2aSThomas Huth * modification, are permitted provided that the following conditions are met: 10fcf5ef2aSThomas Huth * * Redistributions of source code must retain the above copyright 11fcf5ef2aSThomas Huth * notice, this list of conditions and the following disclaimer. 12fcf5ef2aSThomas Huth * * Redistributions in binary form must reproduce the above copyright 13fcf5ef2aSThomas Huth * notice, this list of conditions and the following disclaimer in the 14fcf5ef2aSThomas Huth * documentation and/or other materials provided with the distribution. 15fcf5ef2aSThomas Huth * * Neither the name of the Open Source and Linux Lab nor the 16fcf5ef2aSThomas Huth * names of its contributors may be used to endorse or promote products 17fcf5ef2aSThomas Huth * derived from this software without specific prior written permission. 18fcf5ef2aSThomas Huth * 19fcf5ef2aSThomas Huth * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20fcf5ef2aSThomas Huth * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21fcf5ef2aSThomas Huth * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22fcf5ef2aSThomas Huth * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 23fcf5ef2aSThomas Huth * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24fcf5ef2aSThomas Huth * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25fcf5ef2aSThomas Huth * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 26fcf5ef2aSThomas Huth * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27fcf5ef2aSThomas Huth * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 28fcf5ef2aSThomas Huth * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29fcf5ef2aSThomas Huth */ 30fcf5ef2aSThomas Huth 31fcf5ef2aSThomas Huth #include "qemu/osdep.h" 32fcf5ef2aSThomas Huth #include "qapi/error.h" 33fcf5ef2aSThomas Huth #include "cpu.h" 34fcf5ef2aSThomas Huth #include "qemu-common.h" 35fcf5ef2aSThomas Huth #include "migration/vmstate.h" 36fcf5ef2aSThomas Huth #include "exec/exec-all.h" 37fcf5ef2aSThomas Huth 38fcf5ef2aSThomas Huth 39fcf5ef2aSThomas Huth static void xtensa_cpu_set_pc(CPUState *cs, vaddr value) 40fcf5ef2aSThomas Huth { 41fcf5ef2aSThomas Huth XtensaCPU *cpu = XTENSA_CPU(cs); 42fcf5ef2aSThomas Huth 43fcf5ef2aSThomas Huth cpu->env.pc = value; 44fcf5ef2aSThomas Huth } 45fcf5ef2aSThomas Huth 46fcf5ef2aSThomas Huth static bool xtensa_cpu_has_work(CPUState *cs) 47fcf5ef2aSThomas Huth { 48fcf5ef2aSThomas Huth XtensaCPU *cpu = XTENSA_CPU(cs); 49fcf5ef2aSThomas Huth 50bd527a83SMax Filippov return !cpu->env.runstall && cpu->env.pending_irq_level; 51fcf5ef2aSThomas Huth } 52fcf5ef2aSThomas Huth 53fcf5ef2aSThomas Huth /* CPUClass::reset() */ 54fcf5ef2aSThomas Huth static void xtensa_cpu_reset(CPUState *s) 55fcf5ef2aSThomas Huth { 56fcf5ef2aSThomas Huth XtensaCPU *cpu = XTENSA_CPU(s); 57fcf5ef2aSThomas Huth XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(cpu); 58fcf5ef2aSThomas Huth CPUXtensaState *env = &cpu->env; 59fcf5ef2aSThomas Huth 60fcf5ef2aSThomas Huth xcc->parent_reset(s); 61fcf5ef2aSThomas Huth 62fcf5ef2aSThomas Huth env->exception_taken = 0; 6317ab14acSMax Filippov env->pc = env->config->exception_vector[EXC_RESET0 + env->static_vectors]; 64fcf5ef2aSThomas Huth env->sregs[LITBASE] &= ~1; 65fcf5ef2aSThomas Huth env->sregs[PS] = xtensa_option_enabled(env->config, 66fcf5ef2aSThomas Huth XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10; 67fcf5ef2aSThomas Huth env->sregs[VECBASE] = env->config->vecbase; 68fcf5ef2aSThomas Huth env->sregs[IBREAKENABLE] = 0; 69*9e03ade4SMax Filippov env->sregs[MEMCTL] = MEMCTL_IL0EN & env->config->memctl_mask; 70fcf5ef2aSThomas Huth env->sregs[CACHEATTR] = 0x22222222; 71fcf5ef2aSThomas Huth env->sregs[ATOMCTL] = xtensa_option_enabled(env->config, 72fcf5ef2aSThomas Huth XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15; 73fcf5ef2aSThomas Huth env->sregs[CONFIGID0] = env->config->configid[0]; 74fcf5ef2aSThomas Huth env->sregs[CONFIGID1] = env->config->configid[1]; 75fcf5ef2aSThomas Huth 76fcf5ef2aSThomas Huth env->pending_irq_level = 0; 77fcf5ef2aSThomas Huth reset_mmu(env); 78bd527a83SMax Filippov s->halted = env->runstall; 79fcf5ef2aSThomas Huth } 80fcf5ef2aSThomas Huth 81fcf5ef2aSThomas Huth static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model) 82fcf5ef2aSThomas Huth { 83fcf5ef2aSThomas Huth ObjectClass *oc; 84fcf5ef2aSThomas Huth char *typename; 85fcf5ef2aSThomas Huth 86fcf5ef2aSThomas Huth if (cpu_model == NULL) { 87fcf5ef2aSThomas Huth return NULL; 88fcf5ef2aSThomas Huth } 89fcf5ef2aSThomas Huth 90fcf5ef2aSThomas Huth typename = g_strdup_printf("%s-" TYPE_XTENSA_CPU, cpu_model); 91fcf5ef2aSThomas Huth oc = object_class_by_name(typename); 92fcf5ef2aSThomas Huth g_free(typename); 93fcf5ef2aSThomas Huth if (oc == NULL || !object_class_dynamic_cast(oc, TYPE_XTENSA_CPU) || 94fcf5ef2aSThomas Huth object_class_is_abstract(oc)) { 95fcf5ef2aSThomas Huth return NULL; 96fcf5ef2aSThomas Huth } 97fcf5ef2aSThomas Huth return oc; 98fcf5ef2aSThomas Huth } 99fcf5ef2aSThomas Huth 100fcf5ef2aSThomas Huth static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp) 101fcf5ef2aSThomas Huth { 102fcf5ef2aSThomas Huth CPUState *cs = CPU(dev); 103fcf5ef2aSThomas Huth XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev); 104fcf5ef2aSThomas Huth Error *local_err = NULL; 105fcf5ef2aSThomas Huth 106fcf5ef2aSThomas Huth cpu_exec_realizefn(cs, &local_err); 107fcf5ef2aSThomas Huth if (local_err != NULL) { 108fcf5ef2aSThomas Huth error_propagate(errp, local_err); 109fcf5ef2aSThomas Huth return; 110fcf5ef2aSThomas Huth } 111fcf5ef2aSThomas Huth 112fcf5ef2aSThomas Huth cs->gdb_num_regs = xcc->config->gdb_regmap.num_regs; 113fcf5ef2aSThomas Huth 114fcf5ef2aSThomas Huth qemu_init_vcpu(cs); 115fcf5ef2aSThomas Huth 116fcf5ef2aSThomas Huth xcc->parent_realize(dev, errp); 117fcf5ef2aSThomas Huth } 118fcf5ef2aSThomas Huth 119fcf5ef2aSThomas Huth static void xtensa_cpu_initfn(Object *obj) 120fcf5ef2aSThomas Huth { 121fcf5ef2aSThomas Huth CPUState *cs = CPU(obj); 122fcf5ef2aSThomas Huth XtensaCPU *cpu = XTENSA_CPU(obj); 123fcf5ef2aSThomas Huth XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj); 124fcf5ef2aSThomas Huth CPUXtensaState *env = &cpu->env; 125fcf5ef2aSThomas Huth static bool tcg_inited; 126fcf5ef2aSThomas Huth 127fcf5ef2aSThomas Huth cs->env_ptr = env; 128fcf5ef2aSThomas Huth env->config = xcc->config; 129fcf5ef2aSThomas Huth 130fcf5ef2aSThomas Huth if (tcg_enabled() && !tcg_inited) { 131fcf5ef2aSThomas Huth tcg_inited = true; 132fcf5ef2aSThomas Huth xtensa_translate_init(); 133fcf5ef2aSThomas Huth } 134fcf5ef2aSThomas Huth } 135fcf5ef2aSThomas Huth 136fcf5ef2aSThomas Huth static const VMStateDescription vmstate_xtensa_cpu = { 137fcf5ef2aSThomas Huth .name = "cpu", 138fcf5ef2aSThomas Huth .unmigratable = 1, 139fcf5ef2aSThomas Huth }; 140fcf5ef2aSThomas Huth 141fcf5ef2aSThomas Huth static void xtensa_cpu_class_init(ObjectClass *oc, void *data) 142fcf5ef2aSThomas Huth { 143fcf5ef2aSThomas Huth DeviceClass *dc = DEVICE_CLASS(oc); 144fcf5ef2aSThomas Huth CPUClass *cc = CPU_CLASS(oc); 145fcf5ef2aSThomas Huth XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc); 146fcf5ef2aSThomas Huth 147fcf5ef2aSThomas Huth xcc->parent_realize = dc->realize; 148fcf5ef2aSThomas Huth dc->realize = xtensa_cpu_realizefn; 149fcf5ef2aSThomas Huth 150fcf5ef2aSThomas Huth xcc->parent_reset = cc->reset; 151fcf5ef2aSThomas Huth cc->reset = xtensa_cpu_reset; 152fcf5ef2aSThomas Huth 153fcf5ef2aSThomas Huth cc->class_by_name = xtensa_cpu_class_by_name; 154fcf5ef2aSThomas Huth cc->has_work = xtensa_cpu_has_work; 155fcf5ef2aSThomas Huth cc->do_interrupt = xtensa_cpu_do_interrupt; 156fcf5ef2aSThomas Huth cc->cpu_exec_interrupt = xtensa_cpu_exec_interrupt; 157fcf5ef2aSThomas Huth cc->dump_state = xtensa_cpu_dump_state; 158fcf5ef2aSThomas Huth cc->set_pc = xtensa_cpu_set_pc; 159fcf5ef2aSThomas Huth cc->gdb_read_register = xtensa_cpu_gdb_read_register; 160fcf5ef2aSThomas Huth cc->gdb_write_register = xtensa_cpu_gdb_write_register; 161fcf5ef2aSThomas Huth cc->gdb_stop_before_watchpoint = true; 162fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 163fcf5ef2aSThomas Huth cc->do_unaligned_access = xtensa_cpu_do_unaligned_access; 164fcf5ef2aSThomas Huth cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug; 165fcf5ef2aSThomas Huth cc->do_unassigned_access = xtensa_cpu_do_unassigned_access; 166fcf5ef2aSThomas Huth #endif 167fcf5ef2aSThomas Huth cc->debug_excp_handler = xtensa_breakpoint_handler; 168fcf5ef2aSThomas Huth dc->vmsd = &vmstate_xtensa_cpu; 169fcf5ef2aSThomas Huth } 170fcf5ef2aSThomas Huth 171fcf5ef2aSThomas Huth static const TypeInfo xtensa_cpu_type_info = { 172fcf5ef2aSThomas Huth .name = TYPE_XTENSA_CPU, 173fcf5ef2aSThomas Huth .parent = TYPE_CPU, 174fcf5ef2aSThomas Huth .instance_size = sizeof(XtensaCPU), 175fcf5ef2aSThomas Huth .instance_init = xtensa_cpu_initfn, 176fcf5ef2aSThomas Huth .abstract = true, 177fcf5ef2aSThomas Huth .class_size = sizeof(XtensaCPUClass), 178fcf5ef2aSThomas Huth .class_init = xtensa_cpu_class_init, 179fcf5ef2aSThomas Huth }; 180fcf5ef2aSThomas Huth 181fcf5ef2aSThomas Huth static void xtensa_cpu_register_types(void) 182fcf5ef2aSThomas Huth { 183fcf5ef2aSThomas Huth type_register_static(&xtensa_cpu_type_info); 184fcf5ef2aSThomas Huth } 185fcf5ef2aSThomas Huth 186fcf5ef2aSThomas Huth type_init(xtensa_cpu_register_types) 187